drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* Compliance test status bits  */
  48 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  49 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52
  53 struct dp_link_dpll {
  54         int clock;
  55         struct dpll dpll;
  56 };
  57
  58 static const struct dp_link_dpll gen4_dpll[] = {
  59         { 162000,
  60                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  61         { 270000,
  62                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  63 };
  64
  65 static const struct dp_link_dpll pch_dpll[] = {
  66         { 162000,
  67                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  68         { 270000,
  69                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  70 };
  71
  72 static const struct dp_link_dpll vlv_dpll[] = {
  73         { 162000,
  74                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  75         { 270000,
  76                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  77 };
  78
  79 /*
  80  * CHV supports eDP 1.4 that have  more link rates.
  81  * Below only provides the fixed rate but exclude variable rate.
  82  */
  83 static const struct dp_link_dpll chv_dpll[] = {
  84         /*
  85          * CHV requires to program fractional division for m2.
  86          * m2 is stored in fixed point format using formula below
  87          * (m2_int << 22) | m2_fraction
  88          */
  89         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  90                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  91         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  92                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  93         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  95 };
  96
  97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  98                                   324000, 432000, 540000 };
  99 static const int skl_rates[] = { 162000, 216000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int cnl_rates[] = { 162000, 216000, 270000,
 102                                  324000, 432000, 540000,
 103                                  648000, 810000 };
 104 static const int default_rates[] = { 162000, 270000, 540000 };
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 121 {
 122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 123
 124         return intel_dig_port->base.base.dev;
 125 }
 126
 127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 128 {
 129         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 130 }
 131
 132 static void intel_dp_link_down(struct intel_dp *intel_dp);
 133 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 134 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 135 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 136 static void vlv_steal_power_sequencer(struct drm_device *dev,
 137                                       enum pipe pipe);
 138 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 139
 140 /* update sink rates from dpcd */
 141 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 142 {
 143         int i, max_rate;
 144
 145         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 146
 147         for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
 148                 if (default_rates[i] > max_rate)
 149                         break;
 150                 intel_dp->sink_rates[i] = default_rates[i];
 151         }
 152
 153         intel_dp->num_sink_rates = i;
 154 }
 155
 156 /* Theoretical max between source and sink */
 157 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 158 {
 159         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 160 }
 161
 162 /* Theoretical max between source and sink */
 163 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 164 {
 165         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 166         int source_max = intel_dig_port->max_lanes;
 167         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 168
 169         return min(source_max, sink_max);
 170 }
 171
 172 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 173 {
 174         return intel_dp->max_link_lane_count;
 175 }
 176
 177 int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 181         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 182 }
 183
 184 int
 185 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 186 {
 187         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 188          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 189          * is transmitted every LS_Clk per lane, there is no need to account for
 190          * the channel encoding that is done in the PHY layer here.
 191          */
 192
 193         return max_link_clock * max_lanes;
 194 }
 195
 196 static int
 197 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 198 {
 199         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 200         struct intel_encoder *encoder = &intel_dig_port->base;
 201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 202         int max_dotclk = dev_priv->max_dotclk_freq;
 203         int ds_max_dotclk;
 204
 205         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 206
 207         if (type != DP_DS_PORT_TYPE_VGA)
 208                 return max_dotclk;
 209
 210         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 211                                                     intel_dp->downstream_ports);
 212
 213         if (ds_max_dotclk != 0)
 214                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 215
 216         return max_dotclk;
 217 }
 218
 219 static void
 220 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 221 {
 222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 223         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 224         enum port port = dig_port->port;
 225         const int *source_rates;
 226         int size;
 227         u32 voltage;
 228
 229         /* This should only be done once */
 230         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 231
 232         if (IS_GEN9_LP(dev_priv)) {
 233                 source_rates = bxt_rates;
 234                 size = ARRAY_SIZE(bxt_rates);
 235         } else if (IS_CANNONLAKE(dev_priv)) {
 236                 source_rates = cnl_rates;
 237                 size = ARRAY_SIZE(cnl_rates);
 238                 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 239                 if (port == PORT_A || port == PORT_D ||
 240                     voltage == VOLTAGE_INFO_0_85V)
 241                         size -= 2;
 242         } else if (IS_GEN9_BC(dev_priv)) {
 243                 source_rates = skl_rates;
 244                 size = ARRAY_SIZE(skl_rates);
 245         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 246                    IS_BROADWELL(dev_priv)) {
 247                 source_rates = default_rates;
 248                 size = ARRAY_SIZE(default_rates);
 249         } else {
 250                 source_rates = default_rates;
 251                 size = ARRAY_SIZE(default_rates) - 1;
 252         }
 253
 254         intel_dp->source_rates = source_rates;
 255         intel_dp->num_source_rates = size;
 256 }
 257
 258 static int intersect_rates(const int *source_rates, int source_len,
 259                            const int *sink_rates, int sink_len,
 260                            int *common_rates)
 261 {
 262         int i = 0, j = 0, k = 0;
 263
 264         while (i < source_len && j < sink_len) {
 265                 if (source_rates[i] == sink_rates[j]) {
 266                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 267                                 return k;
 268                         common_rates[k] = source_rates[i];
 269                         ++k;
 270                         ++i;
 271                         ++j;
 272                 } else if (source_rates[i] < sink_rates[j]) {
 273                         ++i;
 274                 } else {
 275                         ++j;
 276                 }
 277         }
 278         return k;
 279 }
 280
 281 /* return index of rate in rates array, or -1 if not found */
 282 static int intel_dp_rate_index(const int *rates, int len, int rate)
 283 {
 284         int i;
 285
 286         for (i = 0; i < len; i++)
 287                 if (rate == rates[i])
 288                         return i;
 289
 290         return -1;
 291 }
 292
 293 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 294 {
 295         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 296
 297         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 298                                                      intel_dp->num_source_rates,
 299                                                      intel_dp->sink_rates,
 300                                                      intel_dp->num_sink_rates,
 301                                                      intel_dp->common_rates);
 302
 303         /* Paranoia, there should always be something in common. */
 304         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 305                 intel_dp->common_rates[0] = default_rates[0];
 306                 intel_dp->num_common_rates = 1;
 307         }
 308 }
 309
 310 /* get length of common rates potentially limited by max_rate */
 311 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 312                                           int max_rate)
 313 {
 314         const int *common_rates = intel_dp->common_rates;
 315         int i, common_len = intel_dp->num_common_rates;
 316
 317         /* Limit results by potentially reduced max rate */
 318         for (i = 0; i < common_len; i++) {
 319                 if (common_rates[common_len - i - 1] <= max_rate)
 320                         return common_len - i;
 321         }
 322
 323         return 0;
 324 }
 325
 326 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 327                                        uint8_t lane_count)
 328 {
 329         /*
 330          * FIXME: we need to synchronize the current link parameters with
 331          * hardware readout. Currently fast link training doesn't work on
 332          * boot-up.
 333          */
 334         if (link_rate == 0 ||
 335             link_rate > intel_dp->max_link_rate)
 336                 return false;
 337
 338         if (lane_count == 0 ||
 339             lane_count > intel_dp_max_lane_count(intel_dp))
 340                 return false;
 341
 342         return true;
 343 }
 344
 345 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 346                                             int link_rate, uint8_t lane_count)
 347 {
 348         int index;
 349
 350         index = intel_dp_rate_index(intel_dp->common_rates,
 351                                     intel_dp->num_common_rates,
 352                                     link_rate);
 353         if (index > 0) {
 354                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 355                 intel_dp->max_link_lane_count = lane_count;
 356         } else if (lane_count > 1) {
 357                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 358                 intel_dp->max_link_lane_count = lane_count >> 1;
 359         } else {
 360                 DRM_ERROR("Link Training Unsuccessful\n");
 361                 return -1;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static enum drm_mode_status
 368 intel_dp_mode_valid(struct drm_connector *connector,
 369                     struct drm_display_mode *mode)
 370 {
 371         struct intel_dp *intel_dp = intel_attached_dp(connector);
 372         struct intel_connector *intel_connector = to_intel_connector(connector);
 373         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 374         int target_clock = mode->clock;
 375         int max_rate, mode_rate, max_lanes, max_link_clock;
 376         int max_dotclk;
 377
 378         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 379
 380         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 381                 if (mode->hdisplay > fixed_mode->hdisplay)
 382                         return MODE_PANEL;
 383
 384                 if (mode->vdisplay > fixed_mode->vdisplay)
 385                         return MODE_PANEL;
 386
 387                 target_clock = fixed_mode->clock;
 388         }
 389
 390         max_link_clock = intel_dp_max_link_rate(intel_dp);
 391         max_lanes = intel_dp_max_lane_count(intel_dp);
 392
 393         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 394         mode_rate = intel_dp_link_required(target_clock, 18);
 395
 396         if (mode_rate > max_rate || target_clock > max_dotclk)
 397                 return MODE_CLOCK_HIGH;
 398
 399         if (mode->clock < 10000)
 400                 return MODE_CLOCK_LOW;
 401
 402         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 403                 return MODE_H_ILLEGAL;
 404
 405         return MODE_OK;
 406 }
 407
 408 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 409 {
 410         int     i;
 411         uint32_t v = 0;
 412
 413         if (src_bytes > 4)
 414                 src_bytes = 4;
 415         for (i = 0; i < src_bytes; i++)
 416                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 417         return v;
 418 }
 419
 420 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 421 {
 422         int i;
 423         if (dst_bytes > 4)
 424                 dst_bytes = 4;
 425         for (i = 0; i < dst_bytes; i++)
 426                 dst[i] = src >> ((3-i) * 8);
 427 }
 428
 429 static void
 430 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 431                                     struct intel_dp *intel_dp);
 432 static void
 433 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 434                                               struct intel_dp *intel_dp,
 435                                               bool force_disable_vdd);
 436 static void
 437 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 438
 439 static void pps_lock(struct intel_dp *intel_dp)
 440 {
 441         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 442         struct intel_encoder *encoder = &intel_dig_port->base;
 443         struct drm_device *dev = encoder->base.dev;
 444         struct drm_i915_private *dev_priv = to_i915(dev);
 445
 446         /*
 447          * See vlv_power_sequencer_reset() why we need
 448          * a power domain reference here.
 449          */
 450         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 451
 452         mutex_lock(&dev_priv->pps_mutex);
 453 }
 454
 455 static void pps_unlock(struct intel_dp *intel_dp)
 456 {
 457         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 458         struct intel_encoder *encoder = &intel_dig_port->base;
 459         struct drm_device *dev = encoder->base.dev;
 460         struct drm_i915_private *dev_priv = to_i915(dev);
 461
 462         mutex_unlock(&dev_priv->pps_mutex);
 463
 464         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 465 }
 466
 467 static void
 468 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 469 {
 470         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 471         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 472         enum pipe pipe = intel_dp->pps_pipe;
 473         bool pll_enabled, release_cl_override = false;
 474         enum dpio_phy phy = DPIO_PHY(pipe);
 475         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 476         uint32_t DP;
 477
 478         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 479                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 480                  pipe_name(pipe), port_name(intel_dig_port->port)))
 481                 return;
 482
 483         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 484                       pipe_name(pipe), port_name(intel_dig_port->port));
 485
 486         /* Preserve the BIOS-computed detected bit. This is
 487          * supposed to be read-only.
 488          */
 489         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 490         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 491         DP |= DP_PORT_WIDTH(1);
 492         DP |= DP_LINK_TRAIN_PAT_1;
 493
 494         if (IS_CHERRYVIEW(dev_priv))
 495                 DP |= DP_PIPE_SELECT_CHV(pipe);
 496         else if (pipe == PIPE_B)
 497                 DP |= DP_PIPEB_SELECT;
 498
 499         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 500
 501         /*
 502          * The DPLL for the pipe must be enabled for this to work.
 503          * So enable temporarily it if it's not already enabled.
 504          */
 505         if (!pll_enabled) {
 506                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 507                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 508
 509                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 510                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 511                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 512                                   pipe_name(pipe));
 513                         return;
 514                 }
 515         }
 516
 517         /*
 518          * Similar magic as in intel_dp_enable_port().
 519          * We _must_ do this port enable + disable trick
 520          * to make this power seqeuencer lock onto the port.
 521          * Otherwise even VDD force bit won't work.
 522          */
 523         I915_WRITE(intel_dp->output_reg, DP);
 524         POSTING_READ(intel_dp->output_reg);
 525
 526         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 527         POSTING_READ(intel_dp->output_reg);
 528
 529         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 530         POSTING_READ(intel_dp->output_reg);
 531
 532         if (!pll_enabled) {
 533                 vlv_force_pll_off(dev_priv, pipe);
 534
 535                 if (release_cl_override)
 536                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 537         }
 538 }
 539
 540 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 541 {
 542         struct intel_encoder *encoder;
 543         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 544
 545         /*
 546          * We don't have power sequencer currently.
 547          * Pick one that's not used by other ports.
 548          */
 549         for_each_intel_encoder(&dev_priv->drm, encoder) {
 550                 struct intel_dp *intel_dp;
 551
 552                 if (encoder->type != INTEL_OUTPUT_DP &&
 553                     encoder->type != INTEL_OUTPUT_EDP)
 554                         continue;
 555
 556                 intel_dp = enc_to_intel_dp(&encoder->base);
 557
 558                 if (encoder->type == INTEL_OUTPUT_EDP) {
 559                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 560                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 561
 562                         if (intel_dp->pps_pipe != INVALID_PIPE)
 563                                 pipes &= ~(1 << intel_dp->pps_pipe);
 564                 } else {
 565                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 566
 567                         if (intel_dp->active_pipe != INVALID_PIPE)
 568                                 pipes &= ~(1 << intel_dp->active_pipe);
 569                 }
 570         }
 571
 572         if (pipes == 0)
 573                 return INVALID_PIPE;
 574
 575         return ffs(pipes) - 1;
 576 }
 577
 578 static enum pipe
 579 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 580 {
 581         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 582         struct drm_device *dev = intel_dig_port->base.base.dev;
 583         struct drm_i915_private *dev_priv = to_i915(dev);
 584         enum pipe pipe;
 585
 586         lockdep_assert_held(&dev_priv->pps_mutex);
 587
 588         /* We should never land here with regular DP ports */
 589         WARN_ON(!intel_dp_is_edp(intel_dp));
 590
 591         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 592                 intel_dp->active_pipe != intel_dp->pps_pipe);
 593
 594         if (intel_dp->pps_pipe != INVALID_PIPE)
 595                 return intel_dp->pps_pipe;
 596
 597         pipe = vlv_find_free_pps(dev_priv);
 598
 599         /*
 600          * Didn't find one. This should not happen since there
 601          * are two power sequencers and up to two eDP ports.
 602          */
 603         if (WARN_ON(pipe == INVALID_PIPE))
 604                 pipe = PIPE_A;
 605
 606         vlv_steal_power_sequencer(dev, pipe);
 607         intel_dp->pps_pipe = pipe;
 608
 609         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 610                       pipe_name(intel_dp->pps_pipe),
 611                       port_name(intel_dig_port->port));
 612
 613         /* init power sequencer on this pipe and port */
 614         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 615         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 616
 617         /*
 618          * Even vdd force doesn't work until we've made
 619          * the power sequencer lock in on the port.
 620          */
 621         vlv_power_sequencer_kick(intel_dp);
 622
 623         return intel_dp->pps_pipe;
 624 }
 625
 626 static int
 627 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 628 {
 629         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 630         struct drm_device *dev = intel_dig_port->base.base.dev;
 631         struct drm_i915_private *dev_priv = to_i915(dev);
 632
 633         lockdep_assert_held(&dev_priv->pps_mutex);
 634
 635         /* We should never land here with regular DP ports */
 636         WARN_ON(!intel_dp_is_edp(intel_dp));
 637
 638         /*
 639          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 640          * mapping needs to be retrieved from VBT, for now just hard-code to
 641          * use instance #0 always.
 642          */
 643         if (!intel_dp->pps_reset)
 644                 return 0;
 645
 646         intel_dp->pps_reset = false;
 647
 648         /*
 649          * Only the HW needs to be reprogrammed, the SW state is fixed and
 650          * has been setup during connector init.
 651          */
 652         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 653
 654         return 0;
 655 }
 656
 657 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 658                                enum pipe pipe);
 659
 660 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 661                                enum pipe pipe)
 662 {
 663         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 664 }
 665
 666 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 667                                 enum pipe pipe)
 668 {
 669         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 670 }
 671
 672 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 673                          enum pipe pipe)
 674 {
 675         return true;
 676 }
 677
 678 static enum pipe
 679 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 680                      enum port port,
 681                      vlv_pipe_check pipe_check)
 682 {
 683         enum pipe pipe;
 684
 685         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 686                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 687                         PANEL_PORT_SELECT_MASK;
 688
 689                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 690                         continue;
 691
 692                 if (!pipe_check(dev_priv, pipe))
 693                         continue;
 694
 695                 return pipe;
 696         }
 697
 698         return INVALID_PIPE;
 699 }
 700
 701 static void
 702 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 703 {
 704         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 705         struct drm_device *dev = intel_dig_port->base.base.dev;
 706         struct drm_i915_private *dev_priv = to_i915(dev);
 707         enum port port = intel_dig_port->port;
 708
 709         lockdep_assert_held(&dev_priv->pps_mutex);
 710
 711         /* try to find a pipe with this port selected */
 712         /* first pick one where the panel is on */
 713         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 714                                                   vlv_pipe_has_pp_on);
 715         /* didn't find one? pick one where vdd is on */
 716         if (intel_dp->pps_pipe == INVALID_PIPE)
 717                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 718                                                           vlv_pipe_has_vdd_on);
 719         /* didn't find one? pick one with just the correct port */
 720         if (intel_dp->pps_pipe == INVALID_PIPE)
 721                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 722                                                           vlv_pipe_any);
 723
 724         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 725         if (intel_dp->pps_pipe == INVALID_PIPE) {
 726                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 727                               port_name(port));
 728                 return;
 729         }
 730
 731         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 732                       port_name(port), pipe_name(intel_dp->pps_pipe));
 733
 734         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 735         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 736 }
 737
 738 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 739 {
 740         struct drm_device *dev = &dev_priv->drm;
 741         struct intel_encoder *encoder;
 742
 743         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 744                     !IS_GEN9_LP(dev_priv)))
 745                 return;
 746
 747         /*
 748          * We can't grab pps_mutex here due to deadlock with power_domain
 749          * mutex when power_domain functions are called while holding pps_mutex.
 750          * That also means that in order to use pps_pipe the code needs to
 751          * hold both a power domain reference and pps_mutex, and the power domain
 752          * reference get/put must be done while _not_ holding pps_mutex.
 753          * pps_{lock,unlock}() do these steps in the correct order, so one
 754          * should use them always.
 755          */
 756
 757         for_each_intel_encoder(dev, encoder) {
 758                 struct intel_dp *intel_dp;
 759
 760                 if (encoder->type != INTEL_OUTPUT_DP &&
 761                     encoder->type != INTEL_OUTPUT_EDP)
 762                         continue;
 763
 764                 intel_dp = enc_to_intel_dp(&encoder->base);
 765
 766                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 767
 768                 if (encoder->type != INTEL_OUTPUT_EDP)
 769                         continue;
 770
 771                 if (IS_GEN9_LP(dev_priv))
 772                         intel_dp->pps_reset = true;
 773                 else
 774                         intel_dp->pps_pipe = INVALID_PIPE;
 775         }
 776 }
 777
 778 struct pps_registers {
 779         i915_reg_t pp_ctrl;
 780         i915_reg_t pp_stat;
 781         i915_reg_t pp_on;
 782         i915_reg_t pp_off;
 783         i915_reg_t pp_div;
 784 };
 785
 786 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 787                                     struct intel_dp *intel_dp,
 788                                     struct pps_registers *regs)
 789 {
 790         int pps_idx = 0;
 791
 792         memset(regs, 0, sizeof(*regs));
 793
 794         if (IS_GEN9_LP(dev_priv))
 795                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 796         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 797                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 798
 799         regs->pp_ctrl = PP_CONTROL(pps_idx);
 800         regs->pp_stat = PP_STATUS(pps_idx);
 801         regs->pp_on = PP_ON_DELAYS(pps_idx);
 802         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 803         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 804                 regs->pp_div = PP_DIVISOR(pps_idx);
 805 }
 806
 807 static i915_reg_t
 808 _pp_ctrl_reg(struct intel_dp *intel_dp)
 809 {
 810         struct pps_registers regs;
 811
 812         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 813                                 &regs);
 814
 815         return regs.pp_ctrl;
 816 }
 817
 818 static i915_reg_t
 819 _pp_stat_reg(struct intel_dp *intel_dp)
 820 {
 821         struct pps_registers regs;
 822
 823         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 824                                 &regs);
 825
 826         return regs.pp_stat;
 827 }
 828
 829 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 830    This function only applicable when panel PM state is not to be tracked */
 831 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 832                               void *unused)
 833 {
 834         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 835                                                  edp_notifier);
 836         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 837         struct drm_i915_private *dev_priv = to_i915(dev);
 838
 839         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 840                 return 0;
 841
 842         pps_lock(intel_dp);
 843
 844         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 845                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 846                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 847                 u32 pp_div;
 848
 849                 pp_ctrl_reg = PP_CONTROL(pipe);
 850                 pp_div_reg  = PP_DIVISOR(pipe);
 851                 pp_div = I915_READ(pp_div_reg);
 852                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 853
 854                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 855                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 856                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 857                 msleep(intel_dp->panel_power_cycle_delay);
 858         }
 859
 860         pps_unlock(intel_dp);
 861
 862         return 0;
 863 }
 864
 865 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 866 {
 867         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 868         struct drm_i915_private *dev_priv = to_i915(dev);
 869
 870         lockdep_assert_held(&dev_priv->pps_mutex);
 871
 872         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 873             intel_dp->pps_pipe == INVALID_PIPE)
 874                 return false;
 875
 876         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 877 }
 878
 879 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 880 {
 881         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 882         struct drm_i915_private *dev_priv = to_i915(dev);
 883
 884         lockdep_assert_held(&dev_priv->pps_mutex);
 885
 886         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 887             intel_dp->pps_pipe == INVALID_PIPE)
 888                 return false;
 889
 890         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 891 }
 892
 893 static void
 894 intel_dp_check_edp(struct intel_dp *intel_dp)
 895 {
 896         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 897         struct drm_i915_private *dev_priv = to_i915(dev);
 898
 899         if (!intel_dp_is_edp(intel_dp))
 900                 return;
 901
 902         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 903                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 904                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 905                               I915_READ(_pp_stat_reg(intel_dp)),
 906                               I915_READ(_pp_ctrl_reg(intel_dp)));
 907         }
 908 }
 909
 910 static uint32_t
 911 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 912 {
 913         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 914         struct drm_device *dev = intel_dig_port->base.base.dev;
 915         struct drm_i915_private *dev_priv = to_i915(dev);
 916         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 917         uint32_t status;
 918         bool done;
 919
 920 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 921         if (has_aux_irq)
 922                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 923                                           msecs_to_jiffies_timeout(10));
 924         else
 925                 done = wait_for(C, 10) == 0;
 926         if (!done)
 927                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 928                           has_aux_irq);
 929 #undef C
 930
 931         return status;
 932 }
 933
 934 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 935 {
 936         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 937         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 938
 939         if (index)
 940                 return 0;
 941
 942         /*
 943          * The clock divider is based off the hrawclk, and would like to run at
 944          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 945          */
 946         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 947 }
 948
 949 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 950 {
 951         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 952         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 953
 954         if (index)
 955                 return 0;
 956
 957         /*
 958          * The clock divider is based off the cdclk or PCH rawclk, and would
 959          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 960          * divide by 2000 and use that
 961          */
 962         if (intel_dig_port->port == PORT_A)
 963                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 964         else
 965                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 966 }
 967
 968 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 969 {
 970         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 971         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 972
 973         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 974                 /* Workaround for non-ULT HSW */
 975                 switch (index) {
 976                 case 0: return 63;
 977                 case 1: return 72;
 978                 default: return 0;
 979                 }
 980         }
 981
 982         return ilk_get_aux_clock_divider(intel_dp, index);
 983 }
 984
 985 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 986 {
 987         /*
 988          * SKL doesn't need us to program the AUX clock divider (Hardware will
 989          * derive the clock from CDCLK automatically). We still implement the
 990          * get_aux_clock_divider vfunc to plug-in into the existing code.
 991          */
 992         return index ? 0 : 1;
 993 }
 994
 995 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 996                                      bool has_aux_irq,
 997                                      int send_bytes,
 998                                      uint32_t aux_clock_divider)
 999 {
1000         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1001         struct drm_i915_private *dev_priv =
1002                         to_i915(intel_dig_port->base.base.dev);
1003         uint32_t precharge, timeout;
1004
1005         if (IS_GEN6(dev_priv))
1006                 precharge = 3;
1007         else
1008                 precharge = 5;
1009
1010         if (IS_BROADWELL(dev_priv))
1011                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1012         else
1013                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1014
1015         return DP_AUX_CH_CTL_SEND_BUSY |
1016                DP_AUX_CH_CTL_DONE |
1017                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1018                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1019                timeout |
1020                DP_AUX_CH_CTL_RECEIVE_ERROR |
1021                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1022                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1023                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1024 }
1025
1026 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1027                                       bool has_aux_irq,
1028                                       int send_bytes,
1029                                       uint32_t unused)
1030 {
1031         return DP_AUX_CH_CTL_SEND_BUSY |
1032                DP_AUX_CH_CTL_DONE |
1033                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1034                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1035                DP_AUX_CH_CTL_TIME_OUT_MAX |
1036                DP_AUX_CH_CTL_RECEIVE_ERROR |
1037                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1038                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1039                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1040 }
1041
1042 static int
1043 intel_dp_aux_ch(struct intel_dp *intel_dp,
1044                 const uint8_t *send, int send_bytes,
1045                 uint8_t *recv, int recv_size)
1046 {
1047         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1048         struct drm_i915_private *dev_priv =
1049                         to_i915(intel_dig_port->base.base.dev);
1050         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1051         uint32_t aux_clock_divider;
1052         int i, ret, recv_bytes;
1053         uint32_t status;
1054         int try, clock = 0;
1055         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1056         bool vdd;
1057
1058         pps_lock(intel_dp);
1059
1060         /*
1061          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1062          * In such cases we want to leave VDD enabled and it's up to upper layers
1063          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1064          * ourselves.
1065          */
1066         vdd = edp_panel_vdd_on(intel_dp);
1067
1068         /* dp aux is extremely sensitive to irq latency, hence request the
1069          * lowest possible wakeup latency and so prevent the cpu from going into
1070          * deep sleep states.
1071          */
1072         pm_qos_update_request(&dev_priv->pm_qos, 0);
1073
1074         intel_dp_check_edp(intel_dp);
1075
1076         /* Try to wait for any previous AUX channel activity */
1077         for (try = 0; try < 3; try++) {
1078                 status = I915_READ_NOTRACE(ch_ctl);
1079                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1080                         break;
1081                 msleep(1);
1082         }
1083
1084         if (try == 3) {
1085                 static u32 last_status = -1;
1086                 const u32 status = I915_READ(ch_ctl);
1087
1088                 if (status != last_status) {
1089                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1090                              status);
1091                         last_status = status;
1092                 }
1093
1094                 ret = -EBUSY;
1095                 goto out;
1096         }
1097
1098         /* Only 5 data registers! */
1099         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1100                 ret = -E2BIG;
1101                 goto out;
1102         }
1103
1104         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1105                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1106                                                           has_aux_irq,
1107                                                           send_bytes,
1108                                                           aux_clock_divider);
1109
1110                 /* Must try at least 3 times according to DP spec */
1111                 for (try = 0; try < 5; try++) {
1112                         /* Load the send data into the aux channel data registers */
1113                         for (i = 0; i < send_bytes; i += 4)
1114                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1115                                            intel_dp_pack_aux(send + i,
1116                                                              send_bytes - i));
1117
1118                         /* Send the command and wait for it to complete */
1119                         I915_WRITE(ch_ctl, send_ctl);
1120
1121                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1122
1123                         /* Clear done status and any errors */
1124                         I915_WRITE(ch_ctl,
1125                                    status |
1126                                    DP_AUX_CH_CTL_DONE |
1127                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1128                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1129
1130                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1131                                 continue;
1132
1133                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1134                          *   400us delay required for errors and timeouts
1135                          *   Timeout errors from the HW already meet this
1136                          *   requirement so skip to next iteration
1137                          */
1138                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1139                                 usleep_range(400, 500);
1140                                 continue;
1141                         }
1142                         if (status & DP_AUX_CH_CTL_DONE)
1143                                 goto done;
1144                 }
1145         }
1146
1147         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1148                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1149                 ret = -EBUSY;
1150                 goto out;
1151         }
1152
1153 done:
1154         /* Check for timeout or receive error.
1155          * Timeouts occur when the sink is not connected
1156          */
1157         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1158                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1159                 ret = -EIO;
1160                 goto out;
1161         }
1162
1163         /* Timeouts occur when the device isn't connected, so they're
1164          * "normal" -- don't fill the kernel log with these */
1165         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1166                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1167                 ret = -ETIMEDOUT;
1168                 goto out;
1169         }
1170
1171         /* Unload any bytes sent back from the other side */
1172         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1173                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1174
1175         /*
1176          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1177          * We have no idea of what happened so we return -EBUSY so
1178          * drm layer takes care for the necessary retries.
1179          */
1180         if (recv_bytes == 0 || recv_bytes > 20) {
1181                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1182                               recv_bytes);
1183                 /*
1184                  * FIXME: This patch was created on top of a series that
1185                  * organize the retries at drm level. There EBUSY should
1186                  * also take care for 1ms wait before retrying.
1187                  * That aux retries re-org is still needed and after that is
1188                  * merged we remove this sleep from here.
1189                  */
1190                 usleep_range(1000, 1500);
1191                 ret = -EBUSY;
1192                 goto out;
1193         }
1194
1195         if (recv_bytes > recv_size)
1196                 recv_bytes = recv_size;
1197
1198         for (i = 0; i < recv_bytes; i += 4)
1199                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1200                                     recv + i, recv_bytes - i);
1201
1202         ret = recv_bytes;
1203 out:
1204         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1205
1206         if (vdd)
1207                 edp_panel_vdd_off(intel_dp, false);
1208
1209         pps_unlock(intel_dp);
1210
1211         return ret;
1212 }
1213
1214 #define BARE_ADDRESS_SIZE       3
1215 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1216 static ssize_t
1217 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1218 {
1219         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1220         uint8_t txbuf[20], rxbuf[20];
1221         size_t txsize, rxsize;
1222         int ret;
1223
1224         txbuf[0] = (msg->request << 4) |
1225                 ((msg->address >> 16) & 0xf);
1226         txbuf[1] = (msg->address >> 8) & 0xff;
1227         txbuf[2] = msg->address & 0xff;
1228         txbuf[3] = msg->size - 1;
1229
1230         switch (msg->request & ~DP_AUX_I2C_MOT) {
1231         case DP_AUX_NATIVE_WRITE:
1232         case DP_AUX_I2C_WRITE:
1233         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1234                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1235                 rxsize = 2; /* 0 or 1 data bytes */
1236
1237                 if (WARN_ON(txsize > 20))
1238                         return -E2BIG;
1239
1240                 WARN_ON(!msg->buffer != !msg->size);
1241
1242                 if (msg->buffer)
1243                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1244
1245                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1246                 if (ret > 0) {
1247                         msg->reply = rxbuf[0] >> 4;
1248
1249                         if (ret > 1) {
1250                                 /* Number of bytes written in a short write. */
1251                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1252                         } else {
1253                                 /* Return payload size. */
1254                                 ret = msg->size;
1255                         }
1256                 }
1257                 break;
1258
1259         case DP_AUX_NATIVE_READ:
1260         case DP_AUX_I2C_READ:
1261                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1262                 rxsize = msg->size + 1;
1263
1264                 if (WARN_ON(rxsize > 20))
1265                         return -E2BIG;
1266
1267                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1268                 if (ret > 0) {
1269                         msg->reply = rxbuf[0] >> 4;
1270                         /*
1271                          * Assume happy day, and copy the data. The caller is
1272                          * expected to check msg->reply before touching it.
1273                          *
1274                          * Return payload size.
1275                          */
1276                         ret--;
1277                         memcpy(msg->buffer, rxbuf + 1, ret);
1278                 }
1279                 break;
1280
1281         default:
1282                 ret = -EINVAL;
1283                 break;
1284         }
1285
1286         return ret;
1287 }
1288
1289 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1290                                 enum port port)
1291 {
1292         const struct ddi_vbt_port_info *info =
1293                 &dev_priv->vbt.ddi_port_info[port];
1294         enum port aux_port;
1295
1296         if (!info->alternate_aux_channel) {
1297                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1298                               port_name(port), port_name(port));
1299                 return port;
1300         }
1301
1302         switch (info->alternate_aux_channel) {
1303         case DP_AUX_A:
1304                 aux_port = PORT_A;
1305                 break;
1306         case DP_AUX_B:
1307                 aux_port = PORT_B;
1308                 break;
1309         case DP_AUX_C:
1310                 aux_port = PORT_C;
1311                 break;
1312         case DP_AUX_D:
1313                 aux_port = PORT_D;
1314                 break;
1315         default:
1316                 MISSING_CASE(info->alternate_aux_channel);
1317                 aux_port = PORT_A;
1318                 break;
1319         }
1320
1321         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1322                       port_name(aux_port), port_name(port));
1323
1324         return aux_port;
1325 }
1326
1327 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1328                                   enum port port)
1329 {
1330         switch (port) {
1331         case PORT_B:
1332         case PORT_C:
1333         case PORT_D:
1334                 return DP_AUX_CH_CTL(port);
1335         default:
1336                 MISSING_CASE(port);
1337                 return DP_AUX_CH_CTL(PORT_B);
1338         }
1339 }
1340
1341 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1342                                    enum port port, int index)
1343 {
1344         switch (port) {
1345         case PORT_B:
1346         case PORT_C:
1347         case PORT_D:
1348                 return DP_AUX_CH_DATA(port, index);
1349         default:
1350                 MISSING_CASE(port);
1351                 return DP_AUX_CH_DATA(PORT_B, index);
1352         }
1353 }
1354
1355 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1356                                   enum port port)
1357 {
1358         switch (port) {
1359         case PORT_A:
1360                 return DP_AUX_CH_CTL(port);
1361         case PORT_B:
1362         case PORT_C:
1363         case PORT_D:
1364                 return PCH_DP_AUX_CH_CTL(port);
1365         default:
1366                 MISSING_CASE(port);
1367                 return DP_AUX_CH_CTL(PORT_A);
1368         }
1369 }
1370
1371 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1372                                    enum port port, int index)
1373 {
1374         switch (port) {
1375         case PORT_A:
1376                 return DP_AUX_CH_DATA(port, index);
1377         case PORT_B:
1378         case PORT_C:
1379         case PORT_D:
1380                 return PCH_DP_AUX_CH_DATA(port, index);
1381         default:
1382                 MISSING_CASE(port);
1383                 return DP_AUX_CH_DATA(PORT_A, index);
1384         }
1385 }
1386
1387 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1388                                   enum port port)
1389 {
1390         switch (port) {
1391         case PORT_A:
1392         case PORT_B:
1393         case PORT_C:
1394         case PORT_D:
1395                 return DP_AUX_CH_CTL(port);
1396         default:
1397                 MISSING_CASE(port);
1398                 return DP_AUX_CH_CTL(PORT_A);
1399         }
1400 }
1401
1402 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1403                                    enum port port, int index)
1404 {
1405         switch (port) {
1406         case PORT_A:
1407         case PORT_B:
1408         case PORT_C:
1409         case PORT_D:
1410                 return DP_AUX_CH_DATA(port, index);
1411         default:
1412                 MISSING_CASE(port);
1413                 return DP_AUX_CH_DATA(PORT_A, index);
1414         }
1415 }
1416
1417 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1418                                     enum port port)
1419 {
1420         if (INTEL_INFO(dev_priv)->gen >= 9)
1421                 return skl_aux_ctl_reg(dev_priv, port);
1422         else if (HAS_PCH_SPLIT(dev_priv))
1423                 return ilk_aux_ctl_reg(dev_priv, port);
1424         else
1425                 return g4x_aux_ctl_reg(dev_priv, port);
1426 }
1427
1428 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1429                                      enum port port, int index)
1430 {
1431         if (INTEL_INFO(dev_priv)->gen >= 9)
1432                 return skl_aux_data_reg(dev_priv, port, index);
1433         else if (HAS_PCH_SPLIT(dev_priv))
1434                 return ilk_aux_data_reg(dev_priv, port, index);
1435         else
1436                 return g4x_aux_data_reg(dev_priv, port, index);
1437 }
1438
1439 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1442         enum port port = intel_aux_port(dev_priv,
1443                                         dp_to_dig_port(intel_dp)->port);
1444         int i;
1445
1446         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1447         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1448                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1449 }
1450
1451 static void
1452 intel_dp_aux_fini(struct intel_dp *intel_dp)
1453 {
1454         kfree(intel_dp->aux.name);
1455 }
1456
1457 static void
1458 intel_dp_aux_init(struct intel_dp *intel_dp)
1459 {
1460         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1461         enum port port = intel_dig_port->port;
1462
1463         intel_aux_reg_init(intel_dp);
1464         drm_dp_aux_init(&intel_dp->aux);
1465
1466         /* Failure to allocate our preferred name is not critical */
1467         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1468         intel_dp->aux.transfer = intel_dp_aux_transfer;
1469 }
1470
1471 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1472 {
1473         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1474
1475         return max_rate >= 540000;
1476 }
1477
1478 static void
1479 intel_dp_set_clock(struct intel_encoder *encoder,
1480                    struct intel_crtc_state *pipe_config)
1481 {
1482         struct drm_device *dev = encoder->base.dev;
1483         struct drm_i915_private *dev_priv = to_i915(dev);
1484         const struct dp_link_dpll *divisor = NULL;
1485         int i, count = 0;
1486
1487         if (IS_G4X(dev_priv)) {
1488                 divisor = gen4_dpll;
1489                 count = ARRAY_SIZE(gen4_dpll);
1490         } else if (HAS_PCH_SPLIT(dev_priv)) {
1491                 divisor = pch_dpll;
1492                 count = ARRAY_SIZE(pch_dpll);
1493         } else if (IS_CHERRYVIEW(dev_priv)) {
1494                 divisor = chv_dpll;
1495                 count = ARRAY_SIZE(chv_dpll);
1496         } else if (IS_VALLEYVIEW(dev_priv)) {
1497                 divisor = vlv_dpll;
1498                 count = ARRAY_SIZE(vlv_dpll);
1499         }
1500
1501         if (divisor && count) {
1502                 for (i = 0; i < count; i++) {
1503                         if (pipe_config->port_clock == divisor[i].clock) {
1504                                 pipe_config->dpll = divisor[i].dpll;
1505                                 pipe_config->clock_set = true;
1506                                 break;
1507                         }
1508                 }
1509         }
1510 }
1511
1512 static void snprintf_int_array(char *str, size_t len,
1513                                const int *array, int nelem)
1514 {
1515         int i;
1516
1517         str[0] = '\0';
1518
1519         for (i = 0; i < nelem; i++) {
1520                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1521                 if (r >= len)
1522                         return;
1523                 str += r;
1524                 len -= r;
1525         }
1526 }
1527
1528 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1529 {
1530         char str[128]; /* FIXME: too big for stack? */
1531
1532         if ((drm_debug & DRM_UT_KMS) == 0)
1533                 return;
1534
1535         snprintf_int_array(str, sizeof(str),
1536                            intel_dp->source_rates, intel_dp->num_source_rates);
1537         DRM_DEBUG_KMS("source rates: %s\n", str);
1538
1539         snprintf_int_array(str, sizeof(str),
1540                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1541         DRM_DEBUG_KMS("sink rates: %s\n", str);
1542
1543         snprintf_int_array(str, sizeof(str),
1544                            intel_dp->common_rates, intel_dp->num_common_rates);
1545         DRM_DEBUG_KMS("common rates: %s\n", str);
1546 }
1547
1548 int
1549 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1550 {
1551         int len;
1552
1553         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1554         if (WARN_ON(len <= 0))
1555                 return 162000;
1556
1557         return intel_dp->common_rates[len - 1];
1558 }
1559
1560 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1561 {
1562         int i = intel_dp_rate_index(intel_dp->sink_rates,
1563                                     intel_dp->num_sink_rates, rate);
1564
1565         if (WARN_ON(i < 0))
1566                 i = 0;
1567
1568         return i;
1569 }
1570
1571 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1572                            uint8_t *link_bw, uint8_t *rate_select)
1573 {
1574         /* eDP 1.4 rate select method. */
1575         if (intel_dp->use_rate_select) {
1576                 *link_bw = 0;
1577                 *rate_select =
1578                         intel_dp_rate_select(intel_dp, port_clock);
1579         } else {
1580                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1581                 *rate_select = 0;
1582         }
1583 }
1584
1585 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1586                                 struct intel_crtc_state *pipe_config)
1587 {
1588         int bpp, bpc;
1589
1590         bpp = pipe_config->pipe_bpp;
1591         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1592
1593         if (bpc > 0)
1594                 bpp = min(bpp, 3*bpc);
1595
1596         /* For DP Compliance we override the computed bpp for the pipe */
1597         if (intel_dp->compliance.test_data.bpc != 0) {
1598                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1599                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1600                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1601                               pipe_config->pipe_bpp);
1602         }
1603         return bpp;
1604 }
1605
1606 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1607                                        struct drm_display_mode *m2)
1608 {
1609         bool bres = false;
1610
1611         if (m1 && m2)
1612                 bres = (m1->hdisplay == m2->hdisplay &&
1613                         m1->hsync_start == m2->hsync_start &&
1614                         m1->hsync_end == m2->hsync_end &&
1615                         m1->htotal == m2->htotal &&
1616                         m1->vdisplay == m2->vdisplay &&
1617                         m1->vsync_start == m2->vsync_start &&
1618                         m1->vsync_end == m2->vsync_end &&
1619                         m1->vtotal == m2->vtotal);
1620         return bres;
1621 }
1622
1623 bool
1624 intel_dp_compute_config(struct intel_encoder *encoder,
1625                         struct intel_crtc_state *pipe_config,
1626                         struct drm_connector_state *conn_state)
1627 {
1628         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1629         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1630         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1631         enum port port = dp_to_dig_port(intel_dp)->port;
1632         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1633         struct intel_connector *intel_connector = intel_dp->attached_connector;
1634         struct intel_digital_connector_state *intel_conn_state =
1635                 to_intel_digital_connector_state(conn_state);
1636         int lane_count, clock;
1637         int min_lane_count = 1;
1638         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1639         /* Conveniently, the link BW constants become indices with a shift...*/
1640         int min_clock = 0;
1641         int max_clock;
1642         int bpp, mode_rate;
1643         int link_avail, link_clock;
1644         int common_len;
1645         uint8_t link_bw, rate_select;
1646         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1647                                            DP_DPCD_QUIRK_LIMITED_M_N);
1648
1649         common_len = intel_dp_common_len_rate_limit(intel_dp,
1650                                                     intel_dp->max_link_rate);
1651
1652         /* No common link rates between source and sink */
1653         WARN_ON(common_len <= 0);
1654
1655         max_clock = common_len - 1;
1656
1657         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1658                 pipe_config->has_pch_encoder = true;
1659
1660         pipe_config->has_drrs = false;
1661         if (port == PORT_A)
1662                 pipe_config->has_audio = false;
1663         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1664                 pipe_config->has_audio = intel_dp->has_audio;
1665         else
1666                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1667
1668         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1669                 struct drm_display_mode *panel_mode =
1670                         intel_connector->panel.alt_fixed_mode;
1671                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1672
1673                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1674                         panel_mode = intel_connector->panel.fixed_mode;
1675
1676                 drm_mode_debug_printmodeline(panel_mode);
1677
1678                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1679
1680                 if (INTEL_GEN(dev_priv) >= 9) {
1681                         int ret;
1682                         ret = skl_update_scaler_crtc(pipe_config);
1683                         if (ret)
1684                                 return ret;
1685                 }
1686
1687                 if (HAS_GMCH_DISPLAY(dev_priv))
1688                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1689                                                  conn_state->scaling_mode);
1690                 else
1691                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1692                                                 conn_state->scaling_mode);
1693         }
1694
1695         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1696                 return false;
1697
1698         /* Use values requested by Compliance Test Request */
1699         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1700                 int index;
1701
1702                 /* Validate the compliance test data since max values
1703                  * might have changed due to link train fallback.
1704                  */
1705                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1706                                                intel_dp->compliance.test_lane_count)) {
1707                         index = intel_dp_rate_index(intel_dp->common_rates,
1708                                                     intel_dp->num_common_rates,
1709                                                     intel_dp->compliance.test_link_rate);
1710                         if (index >= 0)
1711                                 min_clock = max_clock = index;
1712                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1713                 }
1714         }
1715         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1716                       "max bw %d pixel clock %iKHz\n",
1717                       max_lane_count, intel_dp->common_rates[max_clock],
1718                       adjusted_mode->crtc_clock);
1719
1720         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1721          * bpc in between. */
1722         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1723         if (intel_dp_is_edp(intel_dp)) {
1724
1725                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1726                 if (intel_connector->base.display_info.bpc == 0 &&
1727                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1728                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1729                                       dev_priv->vbt.edp.bpp);
1730                         bpp = dev_priv->vbt.edp.bpp;
1731                 }
1732
1733                 /*
1734                  * Use the maximum clock and number of lanes the eDP panel
1735                  * advertizes being capable of. The panels are generally
1736                  * designed to support only a single clock and lane
1737                  * configuration, and typically these values correspond to the
1738                  * native resolution of the panel.
1739                  */
1740                 min_lane_count = max_lane_count;
1741                 min_clock = max_clock;
1742         }
1743
1744         for (; bpp >= 6*3; bpp -= 2*3) {
1745                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1746                                                    bpp);
1747
1748                 for (clock = min_clock; clock <= max_clock; clock++) {
1749                         for (lane_count = min_lane_count;
1750                                 lane_count <= max_lane_count;
1751                                 lane_count <<= 1) {
1752
1753                                 link_clock = intel_dp->common_rates[clock];
1754                                 link_avail = intel_dp_max_data_rate(link_clock,
1755                                                                     lane_count);
1756
1757                                 if (mode_rate <= link_avail) {
1758                                         goto found;
1759                                 }
1760                         }
1761                 }
1762         }
1763
1764         return false;
1765
1766 found:
1767         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1768                 /*
1769                  * See:
1770                  * CEA-861-E - 5.1 Default Encoding Parameters
1771                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1772                  */
1773                 pipe_config->limited_color_range =
1774                         bpp != 18 &&
1775                         drm_default_rgb_quant_range(adjusted_mode) ==
1776                         HDMI_QUANTIZATION_RANGE_LIMITED;
1777         } else {
1778                 pipe_config->limited_color_range =
1779                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1780         }
1781
1782         pipe_config->lane_count = lane_count;
1783
1784         pipe_config->pipe_bpp = bpp;
1785         pipe_config->port_clock = intel_dp->common_rates[clock];
1786
1787         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1788                               &link_bw, &rate_select);
1789
1790         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1791                       link_bw, rate_select, pipe_config->lane_count,
1792                       pipe_config->port_clock, bpp);
1793         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1794                       mode_rate, link_avail);
1795
1796         intel_link_compute_m_n(bpp, lane_count,
1797                                adjusted_mode->crtc_clock,
1798                                pipe_config->port_clock,
1799                                &pipe_config->dp_m_n,
1800                                reduce_m_n);
1801
1802         if (intel_connector->panel.downclock_mode != NULL &&
1803                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1804                         pipe_config->has_drrs = true;
1805                         intel_link_compute_m_n(bpp, lane_count,
1806                                 intel_connector->panel.downclock_mode->clock,
1807                                 pipe_config->port_clock,
1808                                 &pipe_config->dp_m2_n2,
1809                                 reduce_m_n);
1810         }
1811
1812         /*
1813          * DPLL0 VCO may need to be adjusted to get the correct
1814          * clock for eDP. This will affect cdclk as well.
1815          */
1816         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1817                 int vco;
1818
1819                 switch (pipe_config->port_clock / 2) {
1820                 case 108000:
1821                 case 216000:
1822                         vco = 8640000;
1823                         break;
1824                 default:
1825                         vco = 8100000;
1826                         break;
1827                 }
1828
1829                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1830         }
1831
1832         if (!HAS_DDI(dev_priv))
1833                 intel_dp_set_clock(encoder, pipe_config);
1834
1835         intel_psr_compute_config(intel_dp, pipe_config);
1836
1837         return true;
1838 }
1839
1840 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1841                               int link_rate, uint8_t lane_count,
1842                               bool link_mst)
1843 {
1844         intel_dp->link_rate = link_rate;
1845         intel_dp->lane_count = lane_count;
1846         intel_dp->link_mst = link_mst;
1847 }
1848
1849 static void intel_dp_prepare(struct intel_encoder *encoder,
1850                              const struct intel_crtc_state *pipe_config)
1851 {
1852         struct drm_device *dev = encoder->base.dev;
1853         struct drm_i915_private *dev_priv = to_i915(dev);
1854         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1855         enum port port = dp_to_dig_port(intel_dp)->port;
1856         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1857         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1858
1859         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1860                                  pipe_config->lane_count,
1861                                  intel_crtc_has_type(pipe_config,
1862                                                      INTEL_OUTPUT_DP_MST));
1863
1864         /*
1865          * There are four kinds of DP registers:
1866          *
1867          *      IBX PCH
1868          *      SNB CPU
1869          *      IVB CPU
1870          *      CPT PCH
1871          *
1872          * IBX PCH and CPU are the same for almost everything,
1873          * except that the CPU DP PLL is configured in this
1874          * register
1875          *
1876          * CPT PCH is quite different, having many bits moved
1877          * to the TRANS_DP_CTL register instead. That
1878          * configuration happens (oddly) in ironlake_pch_enable
1879          */
1880
1881         /* Preserve the BIOS-computed detected bit. This is
1882          * supposed to be read-only.
1883          */
1884         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1885
1886         /* Handle DP bits in common between all three register formats */
1887         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1888         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1889
1890         /* Split out the IBX/CPU vs CPT settings */
1891
1892         if (IS_GEN7(dev_priv) && port == PORT_A) {
1893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1894                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1895                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1896                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1897                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1898
1899                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1900                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1901
1902                 intel_dp->DP |= crtc->pipe << 29;
1903         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1904                 u32 trans_dp;
1905
1906                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1907
1908                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1909                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1910                         trans_dp |= TRANS_DP_ENH_FRAMING;
1911                 else
1912                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1913                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1914         } else {
1915                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1916                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1917
1918                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1919                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1920                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1921                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1922                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1923
1924                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1925                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1926
1927                 if (IS_CHERRYVIEW(dev_priv))
1928                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1929                 else if (crtc->pipe == PIPE_B)
1930                         intel_dp->DP |= DP_PIPEB_SELECT;
1931         }
1932 }
1933
1934 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1935 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1936
1937 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1938 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1939
1940 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1941 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1942
1943 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1944                                    struct intel_dp *intel_dp);
1945
1946 static void wait_panel_status(struct intel_dp *intel_dp,
1947                                        u32 mask,
1948                                        u32 value)
1949 {
1950         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1953
1954         lockdep_assert_held(&dev_priv->pps_mutex);
1955
1956         intel_pps_verify_state(dev_priv, intel_dp);
1957
1958         pp_stat_reg = _pp_stat_reg(intel_dp);
1959         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1960
1961         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1962                         mask, value,
1963                         I915_READ(pp_stat_reg),
1964                         I915_READ(pp_ctrl_reg));
1965
1966         if (intel_wait_for_register(dev_priv,
1967                                     pp_stat_reg, mask, value,
1968                                     5000))
1969                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1970                                 I915_READ(pp_stat_reg),
1971                                 I915_READ(pp_ctrl_reg));
1972
1973         DRM_DEBUG_KMS("Wait complete\n");
1974 }
1975
1976 static void wait_panel_on(struct intel_dp *intel_dp)
1977 {
1978         DRM_DEBUG_KMS("Wait for panel power on\n");
1979         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1980 }
1981
1982 static void wait_panel_off(struct intel_dp *intel_dp)
1983 {
1984         DRM_DEBUG_KMS("Wait for panel power off time\n");
1985         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1986 }
1987
1988 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1989 {
1990         ktime_t panel_power_on_time;
1991         s64 panel_power_off_duration;
1992
1993         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1994
1995         /* take the difference of currrent time and panel power off time
1996          * and then make panel wait for t11_t12 if needed. */
1997         panel_power_on_time = ktime_get_boottime();
1998         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1999
2000         /* When we disable the VDD override bit last we have to do the manual
2001          * wait. */
2002         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2003                 wait_remaining_ms_from_jiffies(jiffies,
2004                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2005
2006         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2007 }
2008
2009 static void wait_backlight_on(struct intel_dp *intel_dp)
2010 {
2011         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2012                                        intel_dp->backlight_on_delay);
2013 }
2014
2015 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2016 {
2017         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2018                                        intel_dp->backlight_off_delay);
2019 }
2020
2021 /* Read the current pp_control value, unlocking the register if it
2022  * is locked
2023  */
2024
2025 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2026 {
2027         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2028         struct drm_i915_private *dev_priv = to_i915(dev);
2029         u32 control;
2030
2031         lockdep_assert_held(&dev_priv->pps_mutex);
2032
2033         control = I915_READ(_pp_ctrl_reg(intel_dp));
2034         if (WARN_ON(!HAS_DDI(dev_priv) &&
2035                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2036                 control &= ~PANEL_UNLOCK_MASK;
2037                 control |= PANEL_UNLOCK_REGS;
2038         }
2039         return control;
2040 }
2041
2042 /*
2043  * Must be paired with edp_panel_vdd_off().
2044  * Must hold pps_mutex around the whole on/off sequence.
2045  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2046  */
2047 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2048 {
2049         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2050         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2051         struct drm_i915_private *dev_priv = to_i915(dev);
2052         u32 pp;
2053         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2054         bool need_to_disable = !intel_dp->want_panel_vdd;
2055
2056         lockdep_assert_held(&dev_priv->pps_mutex);
2057
2058         if (!intel_dp_is_edp(intel_dp))
2059                 return false;
2060
2061         cancel_delayed_work(&intel_dp->panel_vdd_work);
2062         intel_dp->want_panel_vdd = true;
2063
2064         if (edp_have_panel_vdd(intel_dp))
2065                 return need_to_disable;
2066
2067         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2068
2069         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2070                       port_name(intel_dig_port->port));
2071
2072         if (!edp_have_panel_power(intel_dp))
2073                 wait_panel_power_cycle(intel_dp);
2074
2075         pp = ironlake_get_pp_control(intel_dp);
2076         pp |= EDP_FORCE_VDD;
2077
2078         pp_stat_reg = _pp_stat_reg(intel_dp);
2079         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2080
2081         I915_WRITE(pp_ctrl_reg, pp);
2082         POSTING_READ(pp_ctrl_reg);
2083         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2084                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2085         /*
2086          * If the panel wasn't on, delay before accessing aux channel
2087          */
2088         if (!edp_have_panel_power(intel_dp)) {
2089                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2090                               port_name(intel_dig_port->port));
2091                 msleep(intel_dp->panel_power_up_delay);
2092         }
2093
2094         return need_to_disable;
2095 }
2096
2097 /*
2098  * Must be paired with intel_edp_panel_vdd_off() or
2099  * intel_edp_panel_off().
2100  * Nested calls to these functions are not allowed since
2101  * we drop the lock. Caller must use some higher level
2102  * locking to prevent nested calls from other threads.
2103  */
2104 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2105 {
2106         bool vdd;
2107
2108         if (!intel_dp_is_edp(intel_dp))
2109                 return;
2110
2111         pps_lock(intel_dp);
2112         vdd = edp_panel_vdd_on(intel_dp);
2113         pps_unlock(intel_dp);
2114
2115         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2116              port_name(dp_to_dig_port(intel_dp)->port));
2117 }
2118
2119 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2120 {
2121         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2122         struct drm_i915_private *dev_priv = to_i915(dev);
2123         struct intel_digital_port *intel_dig_port =
2124                 dp_to_dig_port(intel_dp);
2125         u32 pp;
2126         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2127
2128         lockdep_assert_held(&dev_priv->pps_mutex);
2129
2130         WARN_ON(intel_dp->want_panel_vdd);
2131
2132         if (!edp_have_panel_vdd(intel_dp))
2133                 return;
2134
2135         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2136                       port_name(intel_dig_port->port));
2137
2138         pp = ironlake_get_pp_control(intel_dp);
2139         pp &= ~EDP_FORCE_VDD;
2140
2141         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2142         pp_stat_reg = _pp_stat_reg(intel_dp);
2143
2144         I915_WRITE(pp_ctrl_reg, pp);
2145         POSTING_READ(pp_ctrl_reg);
2146
2147         /* Make sure sequencer is idle before allowing subsequent activity */
2148         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2149         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2150
2151         if ((pp & PANEL_POWER_ON) == 0)
2152                 intel_dp->panel_power_off_time = ktime_get_boottime();
2153
2154         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2155 }
2156
2157 static void edp_panel_vdd_work(struct work_struct *__work)
2158 {
2159         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2160                                                  struct intel_dp, panel_vdd_work);
2161
2162         pps_lock(intel_dp);
2163         if (!intel_dp->want_panel_vdd)
2164                 edp_panel_vdd_off_sync(intel_dp);
2165         pps_unlock(intel_dp);
2166 }
2167
2168 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2169 {
2170         unsigned long delay;
2171
2172         /*
2173          * Queue the timer to fire a long time from now (relative to the power
2174          * down delay) to keep the panel power up across a sequence of
2175          * operations.
2176          */
2177         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2178         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2179 }
2180
2181 /*
2182  * Must be paired with edp_panel_vdd_on().
2183  * Must hold pps_mutex around the whole on/off sequence.
2184  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2185  */
2186 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2187 {
2188         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2189
2190         lockdep_assert_held(&dev_priv->pps_mutex);
2191
2192         if (!intel_dp_is_edp(intel_dp))
2193                 return;
2194
2195         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2196              port_name(dp_to_dig_port(intel_dp)->port));
2197
2198         intel_dp->want_panel_vdd = false;
2199
2200         if (sync)
2201                 edp_panel_vdd_off_sync(intel_dp);
2202         else
2203                 edp_panel_vdd_schedule_off(intel_dp);
2204 }
2205
2206 static void edp_panel_on(struct intel_dp *intel_dp)
2207 {
2208         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2209         struct drm_i915_private *dev_priv = to_i915(dev);
2210         u32 pp;
2211         i915_reg_t pp_ctrl_reg;
2212
2213         lockdep_assert_held(&dev_priv->pps_mutex);
2214
2215         if (!intel_dp_is_edp(intel_dp))
2216                 return;
2217
2218         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2219                       port_name(dp_to_dig_port(intel_dp)->port));
2220
2221         if (WARN(edp_have_panel_power(intel_dp),
2222                  "eDP port %c panel power already on\n",
2223                  port_name(dp_to_dig_port(intel_dp)->port)))
2224                 return;
2225
2226         wait_panel_power_cycle(intel_dp);
2227
2228         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2229         pp = ironlake_get_pp_control(intel_dp);
2230         if (IS_GEN5(dev_priv)) {
2231                 /* ILK workaround: disable reset around power sequence */
2232                 pp &= ~PANEL_POWER_RESET;
2233                 I915_WRITE(pp_ctrl_reg, pp);
2234                 POSTING_READ(pp_ctrl_reg);
2235         }
2236
2237         pp |= PANEL_POWER_ON;
2238         if (!IS_GEN5(dev_priv))
2239                 pp |= PANEL_POWER_RESET;
2240
2241         I915_WRITE(pp_ctrl_reg, pp);
2242         POSTING_READ(pp_ctrl_reg);
2243
2244         wait_panel_on(intel_dp);
2245         intel_dp->last_power_on = jiffies;
2246
2247         if (IS_GEN5(dev_priv)) {
2248                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2249                 I915_WRITE(pp_ctrl_reg, pp);
2250                 POSTING_READ(pp_ctrl_reg);
2251         }
2252 }
2253
2254 void intel_edp_panel_on(struct intel_dp *intel_dp)
2255 {
2256         if (!intel_dp_is_edp(intel_dp))
2257                 return;
2258
2259         pps_lock(intel_dp);
2260         edp_panel_on(intel_dp);
2261         pps_unlock(intel_dp);
2262 }
2263
2264
2265 static void edp_panel_off(struct intel_dp *intel_dp)
2266 {
2267         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2268         struct drm_i915_private *dev_priv = to_i915(dev);
2269         u32 pp;
2270         i915_reg_t pp_ctrl_reg;
2271
2272         lockdep_assert_held(&dev_priv->pps_mutex);
2273
2274         if (!intel_dp_is_edp(intel_dp))
2275                 return;
2276
2277         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2278                       port_name(dp_to_dig_port(intel_dp)->port));
2279
2280         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2281              port_name(dp_to_dig_port(intel_dp)->port));
2282
2283         pp = ironlake_get_pp_control(intel_dp);
2284         /* We need to switch off panel power _and_ force vdd, for otherwise some
2285          * panels get very unhappy and cease to work. */
2286         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2287                 EDP_BLC_ENABLE);
2288
2289         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2290
2291         intel_dp->want_panel_vdd = false;
2292
2293         I915_WRITE(pp_ctrl_reg, pp);
2294         POSTING_READ(pp_ctrl_reg);
2295
2296         wait_panel_off(intel_dp);
2297         intel_dp->panel_power_off_time = ktime_get_boottime();
2298
2299         /* We got a reference when we enabled the VDD. */
2300         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2301 }
2302
2303 void intel_edp_panel_off(struct intel_dp *intel_dp)
2304 {
2305         if (!intel_dp_is_edp(intel_dp))
2306                 return;
2307
2308         pps_lock(intel_dp);
2309         edp_panel_off(intel_dp);
2310         pps_unlock(intel_dp);
2311 }
2312
2313 /* Enable backlight in the panel power control. */
2314 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2315 {
2316         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2317         struct drm_device *dev = intel_dig_port->base.base.dev;
2318         struct drm_i915_private *dev_priv = to_i915(dev);
2319         u32 pp;
2320         i915_reg_t pp_ctrl_reg;
2321
2322         /*
2323          * If we enable the backlight right away following a panel power
2324          * on, we may see slight flicker as the panel syncs with the eDP
2325          * link.  So delay a bit to make sure the image is solid before
2326          * allowing it to appear.
2327          */
2328         wait_backlight_on(intel_dp);
2329
2330         pps_lock(intel_dp);
2331
2332         pp = ironlake_get_pp_control(intel_dp);
2333         pp |= EDP_BLC_ENABLE;
2334
2335         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2336
2337         I915_WRITE(pp_ctrl_reg, pp);
2338         POSTING_READ(pp_ctrl_reg);
2339
2340         pps_unlock(intel_dp);
2341 }
2342
2343 /* Enable backlight PWM and backlight PP control. */
2344 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2345                             const struct drm_connector_state *conn_state)
2346 {
2347         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2348
2349         if (!intel_dp_is_edp(intel_dp))
2350                 return;
2351
2352         DRM_DEBUG_KMS("\n");
2353
2354         intel_panel_enable_backlight(crtc_state, conn_state);
2355         _intel_edp_backlight_on(intel_dp);
2356 }
2357
2358 /* Disable backlight in the panel power control. */
2359 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2360 {
2361         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2362         struct drm_i915_private *dev_priv = to_i915(dev);
2363         u32 pp;
2364         i915_reg_t pp_ctrl_reg;
2365
2366         if (!intel_dp_is_edp(intel_dp))
2367                 return;
2368
2369         pps_lock(intel_dp);
2370
2371         pp = ironlake_get_pp_control(intel_dp);
2372         pp &= ~EDP_BLC_ENABLE;
2373
2374         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2375
2376         I915_WRITE(pp_ctrl_reg, pp);
2377         POSTING_READ(pp_ctrl_reg);
2378
2379         pps_unlock(intel_dp);
2380
2381         intel_dp->last_backlight_off = jiffies;
2382         edp_wait_backlight_off(intel_dp);
2383 }
2384
2385 /* Disable backlight PP control and backlight PWM. */
2386 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2387 {
2388         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2389
2390         if (!intel_dp_is_edp(intel_dp))
2391                 return;
2392
2393         DRM_DEBUG_KMS("\n");
2394
2395         _intel_edp_backlight_off(intel_dp);
2396         intel_panel_disable_backlight(old_conn_state);
2397 }
2398
2399 /*
2400  * Hook for controlling the panel power control backlight through the bl_power
2401  * sysfs attribute. Take care to handle multiple calls.
2402  */
2403 static void intel_edp_backlight_power(struct intel_connector *connector,
2404                                       bool enable)
2405 {
2406         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2407         bool is_enabled;
2408
2409         pps_lock(intel_dp);
2410         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2411         pps_unlock(intel_dp);
2412
2413         if (is_enabled == enable)
2414                 return;
2415
2416         DRM_DEBUG_KMS("panel power control backlight %s\n",
2417                       enable ? "enable" : "disable");
2418
2419         if (enable)
2420                 _intel_edp_backlight_on(intel_dp);
2421         else
2422                 _intel_edp_backlight_off(intel_dp);
2423 }
2424
2425 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2426 {
2427         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2428         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2429         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2430
2431         I915_STATE_WARN(cur_state != state,
2432                         "DP port %c state assertion failure (expected %s, current %s)\n",
2433                         port_name(dig_port->port),
2434                         onoff(state), onoff(cur_state));
2435 }
2436 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2437
2438 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2439 {
2440         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2441
2442         I915_STATE_WARN(cur_state != state,
2443                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2444                         onoff(state), onoff(cur_state));
2445 }
2446 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2447 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2448
2449 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2450                                 const struct intel_crtc_state *pipe_config)
2451 {
2452         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2454
2455         assert_pipe_disabled(dev_priv, crtc->pipe);
2456         assert_dp_port_disabled(intel_dp);
2457         assert_edp_pll_disabled(dev_priv);
2458
2459         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2460                       pipe_config->port_clock);
2461
2462         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2463
2464         if (pipe_config->port_clock == 162000)
2465                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2466         else
2467                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2468
2469         I915_WRITE(DP_A, intel_dp->DP);
2470         POSTING_READ(DP_A);
2471         udelay(500);
2472
2473         /*
2474          * [DevILK] Work around required when enabling DP PLL
2475          * while a pipe is enabled going to FDI:
2476          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2477          * 2. Program DP PLL enable
2478          */
2479         if (IS_GEN5(dev_priv))
2480                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2481
2482         intel_dp->DP |= DP_PLL_ENABLE;
2483
2484         I915_WRITE(DP_A, intel_dp->DP);
2485         POSTING_READ(DP_A);
2486         udelay(200);
2487 }
2488
2489 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2490 {
2491         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2492         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2493         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2494
2495         assert_pipe_disabled(dev_priv, crtc->pipe);
2496         assert_dp_port_disabled(intel_dp);
2497         assert_edp_pll_enabled(dev_priv);
2498
2499         DRM_DEBUG_KMS("disabling eDP PLL\n");
2500
2501         intel_dp->DP &= ~DP_PLL_ENABLE;
2502
2503         I915_WRITE(DP_A, intel_dp->DP);
2504         POSTING_READ(DP_A);
2505         udelay(200);
2506 }
2507
2508 /* If the sink supports it, try to set the power state appropriately */
2509 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2510 {
2511         int ret, i;
2512
2513         /* Should have a valid DPCD by this point */
2514         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2515                 return;
2516
2517         if (mode != DRM_MODE_DPMS_ON) {
2518                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2519                                          DP_SET_POWER_D3);
2520         } else {
2521                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2522
2523                 /*
2524                  * When turning on, we need to retry for 1ms to give the sink
2525                  * time to wake up.
2526                  */
2527                 for (i = 0; i < 3; i++) {
2528                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2529                                                  DP_SET_POWER_D0);
2530                         if (ret == 1)
2531                                 break;
2532                         msleep(1);
2533                 }
2534
2535                 if (ret == 1 && lspcon->active)
2536                         lspcon_wait_pcon_mode(lspcon);
2537         }
2538
2539         if (ret != 1)
2540                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2541                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2542 }
2543
2544 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2545                                   enum pipe *pipe)
2546 {
2547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2548         enum port port = dp_to_dig_port(intel_dp)->port;
2549         struct drm_device *dev = encoder->base.dev;
2550         struct drm_i915_private *dev_priv = to_i915(dev);
2551         u32 tmp;
2552         bool ret;
2553
2554         if (!intel_display_power_get_if_enabled(dev_priv,
2555                                                 encoder->power_domain))
2556                 return false;
2557
2558         ret = false;
2559
2560         tmp = I915_READ(intel_dp->output_reg);
2561
2562         if (!(tmp & DP_PORT_EN))
2563                 goto out;
2564
2565         if (IS_GEN7(dev_priv) && port == PORT_A) {
2566                 *pipe = PORT_TO_PIPE_CPT(tmp);
2567         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2568                 enum pipe p;
2569
2570                 for_each_pipe(dev_priv, p) {
2571                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2572                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2573                                 *pipe = p;
2574                                 ret = true;
2575
2576                                 goto out;
2577                         }
2578                 }
2579
2580                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2581                               i915_mmio_reg_offset(intel_dp->output_reg));
2582         } else if (IS_CHERRYVIEW(dev_priv)) {
2583                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2584         } else {
2585                 *pipe = PORT_TO_PIPE(tmp);
2586         }
2587
2588         ret = true;
2589
2590 out:
2591         intel_display_power_put(dev_priv, encoder->power_domain);
2592
2593         return ret;
2594 }
2595
2596 static void intel_dp_get_config(struct intel_encoder *encoder,
2597                                 struct intel_crtc_state *pipe_config)
2598 {
2599         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2600         u32 tmp, flags = 0;
2601         struct drm_device *dev = encoder->base.dev;
2602         struct drm_i915_private *dev_priv = to_i915(dev);
2603         enum port port = dp_to_dig_port(intel_dp)->port;
2604         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2605
2606         tmp = I915_READ(intel_dp->output_reg);
2607
2608         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2609
2610         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2611                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2612
2613                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2614                         flags |= DRM_MODE_FLAG_PHSYNC;
2615                 else
2616                         flags |= DRM_MODE_FLAG_NHSYNC;
2617
2618                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2619                         flags |= DRM_MODE_FLAG_PVSYNC;
2620                 else
2621                         flags |= DRM_MODE_FLAG_NVSYNC;
2622         } else {
2623                 if (tmp & DP_SYNC_HS_HIGH)
2624                         flags |= DRM_MODE_FLAG_PHSYNC;
2625                 else
2626                         flags |= DRM_MODE_FLAG_NHSYNC;
2627
2628                 if (tmp & DP_SYNC_VS_HIGH)
2629                         flags |= DRM_MODE_FLAG_PVSYNC;
2630                 else
2631                         flags |= DRM_MODE_FLAG_NVSYNC;
2632         }
2633
2634         pipe_config->base.adjusted_mode.flags |= flags;
2635
2636         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2637                 pipe_config->limited_color_range = true;
2638
2639         pipe_config->lane_count =
2640                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2641
2642         intel_dp_get_m_n(crtc, pipe_config);
2643
2644         if (port == PORT_A) {
2645                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2646                         pipe_config->port_clock = 162000;
2647                 else
2648                         pipe_config->port_clock = 270000;
2649         }
2650
2651         pipe_config->base.adjusted_mode.crtc_clock =
2652                 intel_dotclock_calculate(pipe_config->port_clock,
2653                                          &pipe_config->dp_m_n);
2654
2655         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2656             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2657                 /*
2658                  * This is a big fat ugly hack.
2659                  *
2660                  * Some machines in UEFI boot mode provide us a VBT that has 18
2661                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2662                  * unknown we fail to light up. Yet the same BIOS boots up with
2663                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2664                  * max, not what it tells us to use.
2665                  *
2666                  * Note: This will still be broken if the eDP panel is not lit
2667                  * up by the BIOS, and thus we can't get the mode at module
2668                  * load.
2669                  */
2670                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2671                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2672                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2673         }
2674 }
2675
2676 static void intel_disable_dp(struct intel_encoder *encoder,
2677                              const struct intel_crtc_state *old_crtc_state,
2678                              const struct drm_connector_state *old_conn_state)
2679 {
2680         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2681
2682         if (old_crtc_state->has_audio)
2683                 intel_audio_codec_disable(encoder);
2684
2685         /* Make sure the panel is off before trying to change the mode. But also
2686          * ensure that we have vdd while we switch off the panel. */
2687         intel_edp_panel_vdd_on(intel_dp);
2688         intel_edp_backlight_off(old_conn_state);
2689         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2690         intel_edp_panel_off(intel_dp);
2691 }
2692
2693 static void g4x_disable_dp(struct intel_encoder *encoder,
2694                            const struct intel_crtc_state *old_crtc_state,
2695                            const struct drm_connector_state *old_conn_state)
2696 {
2697         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2698
2699         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2700
2701         /* disable the port before the pipe on g4x */
2702         intel_dp_link_down(intel_dp);
2703 }
2704
2705 static void ilk_disable_dp(struct intel_encoder *encoder,
2706                            const struct intel_crtc_state *old_crtc_state,
2707                            const struct drm_connector_state *old_conn_state)
2708 {
2709         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2710 }
2711
2712 static void vlv_disable_dp(struct intel_encoder *encoder,
2713                            const struct intel_crtc_state *old_crtc_state,
2714                            const struct drm_connector_state *old_conn_state)
2715 {
2716         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2717
2718         intel_psr_disable(intel_dp, old_crtc_state);
2719
2720         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2721 }
2722
2723 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2724                                 const struct intel_crtc_state *old_crtc_state,
2725                                 const struct drm_connector_state *old_conn_state)
2726 {
2727         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2728         enum port port = dp_to_dig_port(intel_dp)->port;
2729
2730         intel_dp_link_down(intel_dp);
2731
2732         /* Only ilk+ has port A */
2733         if (port == PORT_A)
2734                 ironlake_edp_pll_off(intel_dp);
2735 }
2736
2737 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2738                                 const struct intel_crtc_state *old_crtc_state,
2739                                 const struct drm_connector_state *old_conn_state)
2740 {
2741         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742
2743         intel_dp_link_down(intel_dp);
2744 }
2745
2746 static void chv_post_disable_dp(struct intel_encoder *encoder,
2747                                 const struct intel_crtc_state *old_crtc_state,
2748                                 const struct drm_connector_state *old_conn_state)
2749 {
2750         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2751         struct drm_device *dev = encoder->base.dev;
2752         struct drm_i915_private *dev_priv = to_i915(dev);
2753
2754         intel_dp_link_down(intel_dp);
2755
2756         mutex_lock(&dev_priv->sb_lock);
2757
2758         /* Assert data lane reset */
2759         chv_data_lane_soft_reset(encoder, true);
2760
2761         mutex_unlock(&dev_priv->sb_lock);
2762 }
2763
2764 static void
2765 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2766                          uint32_t *DP,
2767                          uint8_t dp_train_pat)
2768 {
2769         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2770         struct drm_device *dev = intel_dig_port->base.base.dev;
2771         struct drm_i915_private *dev_priv = to_i915(dev);
2772         enum port port = intel_dig_port->port;
2773
2774         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2775                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2776                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2777
2778         if (HAS_DDI(dev_priv)) {
2779                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2780
2781                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2782                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2783                 else
2784                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2785
2786                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2787                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2788                 case DP_TRAINING_PATTERN_DISABLE:
2789                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2790
2791                         break;
2792                 case DP_TRAINING_PATTERN_1:
2793                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2794                         break;
2795                 case DP_TRAINING_PATTERN_2:
2796                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2797                         break;
2798                 case DP_TRAINING_PATTERN_3:
2799                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2800                         break;
2801                 }
2802                 I915_WRITE(DP_TP_CTL(port), temp);
2803
2804         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2805                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2806                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2807
2808                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2809                 case DP_TRAINING_PATTERN_DISABLE:
2810                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2811                         break;
2812                 case DP_TRAINING_PATTERN_1:
2813                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2814                         break;
2815                 case DP_TRAINING_PATTERN_2:
2816                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2817                         break;
2818                 case DP_TRAINING_PATTERN_3:
2819                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2820                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2821                         break;
2822                 }
2823
2824         } else {
2825                 if (IS_CHERRYVIEW(dev_priv))
2826                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2827                 else
2828                         *DP &= ~DP_LINK_TRAIN_MASK;
2829
2830                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2831                 case DP_TRAINING_PATTERN_DISABLE:
2832                         *DP |= DP_LINK_TRAIN_OFF;
2833                         break;
2834                 case DP_TRAINING_PATTERN_1:
2835                         *DP |= DP_LINK_TRAIN_PAT_1;
2836                         break;
2837                 case DP_TRAINING_PATTERN_2:
2838                         *DP |= DP_LINK_TRAIN_PAT_2;
2839                         break;
2840                 case DP_TRAINING_PATTERN_3:
2841                         if (IS_CHERRYVIEW(dev_priv)) {
2842                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2843                         } else {
2844                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2845                                 *DP |= DP_LINK_TRAIN_PAT_2;
2846                         }
2847                         break;
2848                 }
2849         }
2850 }
2851
2852 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2853                                  const struct intel_crtc_state *old_crtc_state)
2854 {
2855         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2856         struct drm_i915_private *dev_priv = to_i915(dev);
2857
2858         /* enable with pattern 1 (as per spec) */
2859
2860         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2861
2862         /*
2863          * Magic for VLV/CHV. We _must_ first set up the register
2864          * without actually enabling the port, and then do another
2865          * write to enable the port. Otherwise link training will
2866          * fail when the power sequencer is freshly used for this port.
2867          */
2868         intel_dp->DP |= DP_PORT_EN;
2869         if (old_crtc_state->has_audio)
2870                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2871
2872         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2873         POSTING_READ(intel_dp->output_reg);
2874 }
2875
2876 static void intel_enable_dp(struct intel_encoder *encoder,
2877                             const struct intel_crtc_state *pipe_config,
2878                             const struct drm_connector_state *conn_state)
2879 {
2880         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2881         struct drm_device *dev = encoder->base.dev;
2882         struct drm_i915_private *dev_priv = to_i915(dev);
2883         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2884         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2885         enum pipe pipe = crtc->pipe;
2886
2887         if (WARN_ON(dp_reg & DP_PORT_EN))
2888                 return;
2889
2890         pps_lock(intel_dp);
2891
2892         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2893                 vlv_init_panel_power_sequencer(intel_dp);
2894
2895         intel_dp_enable_port(intel_dp, pipe_config);
2896
2897         edp_panel_vdd_on(intel_dp);
2898         edp_panel_on(intel_dp);
2899         edp_panel_vdd_off(intel_dp, true);
2900
2901         pps_unlock(intel_dp);
2902
2903         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2904                 unsigned int lane_mask = 0x0;
2905
2906                 if (IS_CHERRYVIEW(dev_priv))
2907                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2908
2909                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2910                                     lane_mask);
2911         }
2912
2913         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2914         intel_dp_start_link_train(intel_dp);
2915         intel_dp_stop_link_train(intel_dp);
2916
2917         if (pipe_config->has_audio) {
2918                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2919                                  pipe_name(pipe));
2920                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2921         }
2922 }
2923
2924 static void g4x_enable_dp(struct intel_encoder *encoder,
2925                           const struct intel_crtc_state *pipe_config,
2926                           const struct drm_connector_state *conn_state)
2927 {
2928         intel_enable_dp(encoder, pipe_config, conn_state);
2929         intel_edp_backlight_on(pipe_config, conn_state);
2930 }
2931
2932 static void vlv_enable_dp(struct intel_encoder *encoder,
2933                           const struct intel_crtc_state *pipe_config,
2934                           const struct drm_connector_state *conn_state)
2935 {
2936         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2937
2938         intel_edp_backlight_on(pipe_config, conn_state);
2939         intel_psr_enable(intel_dp, pipe_config);
2940 }
2941
2942 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2943                               const struct intel_crtc_state *pipe_config,
2944                               const struct drm_connector_state *conn_state)
2945 {
2946         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2947         enum port port = dp_to_dig_port(intel_dp)->port;
2948
2949         intel_dp_prepare(encoder, pipe_config);
2950
2951         /* Only ilk+ has port A */
2952         if (port == PORT_A)
2953                 ironlake_edp_pll_on(intel_dp, pipe_config);
2954 }
2955
2956 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2957 {
2958         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2959         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2960         enum pipe pipe = intel_dp->pps_pipe;
2961         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2962
2963         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2964
2965         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2966                 return;
2967
2968         edp_panel_vdd_off_sync(intel_dp);
2969
2970         /*
2971          * VLV seems to get confused when multiple power seqeuencers
2972          * have the same port selected (even if only one has power/vdd
2973          * enabled). The failure manifests as vlv_wait_port_ready() failing
2974          * CHV on the other hand doesn't seem to mind having the same port
2975          * selected in multiple power seqeuencers, but let's clear the
2976          * port select always when logically disconnecting a power sequencer
2977          * from a port.
2978          */
2979         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2980                       pipe_name(pipe), port_name(intel_dig_port->port));
2981         I915_WRITE(pp_on_reg, 0);
2982         POSTING_READ(pp_on_reg);
2983
2984         intel_dp->pps_pipe = INVALID_PIPE;
2985 }
2986
2987 static void vlv_steal_power_sequencer(struct drm_device *dev,
2988                                       enum pipe pipe)
2989 {
2990         struct drm_i915_private *dev_priv = to_i915(dev);
2991         struct intel_encoder *encoder;
2992
2993         lockdep_assert_held(&dev_priv->pps_mutex);
2994
2995         for_each_intel_encoder(dev, encoder) {
2996                 struct intel_dp *intel_dp;
2997                 enum port port;
2998
2999                 if (encoder->type != INTEL_OUTPUT_DP &&
3000                     encoder->type != INTEL_OUTPUT_EDP)
3001                         continue;
3002
3003                 intel_dp = enc_to_intel_dp(&encoder->base);
3004                 port = dp_to_dig_port(intel_dp)->port;
3005
3006                 WARN(intel_dp->active_pipe == pipe,
3007                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3008                      pipe_name(pipe), port_name(port));
3009
3010                 if (intel_dp->pps_pipe != pipe)
3011                         continue;
3012
3013                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3014                               pipe_name(pipe), port_name(port));
3015
3016                 /* make sure vdd is off before we steal it */
3017                 vlv_detach_power_sequencer(intel_dp);
3018         }
3019 }
3020
3021 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
3022 {
3023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3024         struct intel_encoder *encoder = &intel_dig_port->base;
3025         struct drm_device *dev = encoder->base.dev;
3026         struct drm_i915_private *dev_priv = to_i915(dev);
3027         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3028
3029         lockdep_assert_held(&dev_priv->pps_mutex);
3030
3031         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3032
3033         if (intel_dp->pps_pipe != INVALID_PIPE &&
3034             intel_dp->pps_pipe != crtc->pipe) {
3035                 /*
3036                  * If another power sequencer was being used on this
3037                  * port previously make sure to turn off vdd there while
3038                  * we still have control of it.
3039                  */
3040                 vlv_detach_power_sequencer(intel_dp);
3041         }
3042
3043         /*
3044          * We may be stealing the power
3045          * sequencer from another port.
3046          */
3047         vlv_steal_power_sequencer(dev, crtc->pipe);
3048
3049         intel_dp->active_pipe = crtc->pipe;
3050
3051         if (!intel_dp_is_edp(intel_dp))
3052                 return;
3053
3054         /* now it's all ours */
3055         intel_dp->pps_pipe = crtc->pipe;
3056
3057         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3058                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3059
3060         /* init power sequencer on this pipe and port */
3061         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3062         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3063 }
3064
3065 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3066                               const struct intel_crtc_state *pipe_config,
3067                               const struct drm_connector_state *conn_state)
3068 {
3069         vlv_phy_pre_encoder_enable(encoder);
3070
3071         intel_enable_dp(encoder, pipe_config, conn_state);
3072 }
3073
3074 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3075                                   const struct intel_crtc_state *pipe_config,
3076                                   const struct drm_connector_state *conn_state)
3077 {
3078         intel_dp_prepare(encoder, pipe_config);
3079
3080         vlv_phy_pre_pll_enable(encoder);
3081 }
3082
3083 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3084                               const struct intel_crtc_state *pipe_config,
3085                               const struct drm_connector_state *conn_state)
3086 {
3087         chv_phy_pre_encoder_enable(encoder);
3088
3089         intel_enable_dp(encoder, pipe_config, conn_state);
3090
3091         /* Second common lane will stay alive on its own now */
3092         chv_phy_release_cl2_override(encoder);
3093 }
3094
3095 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3096                                   const struct intel_crtc_state *pipe_config,
3097                                   const struct drm_connector_state *conn_state)
3098 {
3099         intel_dp_prepare(encoder, pipe_config);
3100
3101         chv_phy_pre_pll_enable(encoder);
3102 }
3103
3104 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3105                                     const struct intel_crtc_state *pipe_config,
3106                                     const struct drm_connector_state *conn_state)
3107 {
3108         chv_phy_post_pll_disable(encoder);
3109 }
3110
3111 /*
3112  * Fetch AUX CH registers 0x202 - 0x207 which contain
3113  * link status information
3114  */
3115 bool
3116 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3117 {
3118         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3119                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3120 }
3121
3122 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3123 {
3124         uint8_t psr_caps = 0;
3125
3126         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3127                 return false;
3128         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3129 }
3130
3131 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3132 {
3133         uint8_t dprx = 0;
3134
3135         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3136                               &dprx) != 1)
3137                 return false;
3138         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3139 }
3140
3141 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3142 {
3143         uint8_t alpm_caps = 0;
3144
3145         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3146                               &alpm_caps) != 1)
3147                 return false;
3148         return alpm_caps & DP_ALPM_CAP;
3149 }
3150
3151 /* These are source-specific values. */
3152 uint8_t
3153 intel_dp_voltage_max(struct intel_dp *intel_dp)
3154 {
3155         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3156         enum port port = dp_to_dig_port(intel_dp)->port;
3157
3158         if (IS_GEN9_LP(dev_priv))
3159                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3160         else if (INTEL_GEN(dev_priv) >= 9) {
3161                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3162                 return intel_ddi_dp_voltage_max(encoder);
3163         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3164                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3165         else if (IS_GEN7(dev_priv) && port == PORT_A)
3166                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3167         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3168                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3169         else
3170                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3171 }
3172
3173 uint8_t
3174 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3175 {
3176         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3177         enum port port = dp_to_dig_port(intel_dp)->port;
3178
3179         if (INTEL_GEN(dev_priv) >= 9) {
3180                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3181                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3182                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3184                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3185                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3186                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3187                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3188                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3189                 default:
3190                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3191                 }
3192         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3193                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3195                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3196                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3197                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3199                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3200                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3201                 default:
3202                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3203                 }
3204         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3205                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3206                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3207                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3209                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3210                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3211                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3212                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3213                 default:
3214                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3215                 }
3216         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3217                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3218                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3219                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3220                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3222                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3223                 default:
3224                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3225                 }
3226         } else {
3227                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3228                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3229                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3230                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3231                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3233                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3234                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3235                 default:
3236                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3237                 }
3238         }
3239 }
3240
3241 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3242 {
3243         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3244         unsigned long demph_reg_value, preemph_reg_value,
3245                 uniqtranscale_reg_value;
3246         uint8_t train_set = intel_dp->train_set[0];
3247
3248         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3249         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3250                 preemph_reg_value = 0x0004000;
3251                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3253                         demph_reg_value = 0x2B405555;
3254                         uniqtranscale_reg_value = 0x552AB83A;
3255                         break;
3256                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3257                         demph_reg_value = 0x2B404040;
3258                         uniqtranscale_reg_value = 0x5548B83A;
3259                         break;
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3261                         demph_reg_value = 0x2B245555;
3262                         uniqtranscale_reg_value = 0x5560B83A;
3263                         break;
3264                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3265                         demph_reg_value = 0x2B405555;
3266                         uniqtranscale_reg_value = 0x5598DA3A;
3267                         break;
3268                 default:
3269                         return 0;
3270                 }
3271                 break;
3272         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3273                 preemph_reg_value = 0x0002000;
3274                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3275                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3276                         demph_reg_value = 0x2B404040;
3277                         uniqtranscale_reg_value = 0x5552B83A;
3278                         break;
3279                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3280                         demph_reg_value = 0x2B404848;
3281                         uniqtranscale_reg_value = 0x5580B83A;
3282                         break;
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3284                         demph_reg_value = 0x2B404040;
3285                         uniqtranscale_reg_value = 0x55ADDA3A;
3286                         break;
3287                 default:
3288                         return 0;
3289                 }
3290                 break;
3291         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3292                 preemph_reg_value = 0x0000000;
3293                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3294                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3295                         demph_reg_value = 0x2B305555;
3296                         uniqtranscale_reg_value = 0x5570B83A;
3297                         break;
3298                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3299                         demph_reg_value = 0x2B2B4040;
3300                         uniqtranscale_reg_value = 0x55ADDA3A;
3301                         break;
3302                 default:
3303                         return 0;
3304                 }
3305                 break;
3306         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3307                 preemph_reg_value = 0x0006000;
3308                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3309                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3310                         demph_reg_value = 0x1B405555;
3311                         uniqtranscale_reg_value = 0x55ADDA3A;
3312                         break;
3313                 default:
3314                         return 0;
3315                 }
3316                 break;
3317         default:
3318                 return 0;
3319         }
3320
3321         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3322                                  uniqtranscale_reg_value, 0);
3323
3324         return 0;
3325 }
3326
3327 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3328 {
3329         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3330         u32 deemph_reg_value, margin_reg_value;
3331         bool uniq_trans_scale = false;
3332         uint8_t train_set = intel_dp->train_set[0];
3333
3334         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3335         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3336                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3337                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3338                         deemph_reg_value = 128;
3339                         margin_reg_value = 52;
3340                         break;
3341                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3342                         deemph_reg_value = 128;
3343                         margin_reg_value = 77;
3344                         break;
3345                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3346                         deemph_reg_value = 128;
3347                         margin_reg_value = 102;
3348                         break;
3349                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3350                         deemph_reg_value = 128;
3351                         margin_reg_value = 154;
3352                         uniq_trans_scale = true;
3353                         break;
3354                 default:
3355                         return 0;
3356                 }
3357                 break;
3358         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3359                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3360                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3361                         deemph_reg_value = 85;
3362                         margin_reg_value = 78;
3363                         break;
3364                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3365                         deemph_reg_value = 85;
3366                         margin_reg_value = 116;
3367                         break;
3368                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3369                         deemph_reg_value = 85;
3370                         margin_reg_value = 154;
3371                         break;
3372                 default:
3373                         return 0;
3374                 }
3375                 break;
3376         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3377                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3378                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3379                         deemph_reg_value = 64;
3380                         margin_reg_value = 104;
3381                         break;
3382                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3383                         deemph_reg_value = 64;
3384                         margin_reg_value = 154;
3385                         break;
3386                 default:
3387                         return 0;
3388                 }
3389                 break;
3390         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3391                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3392                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3393                         deemph_reg_value = 43;
3394                         margin_reg_value = 154;
3395                         break;
3396                 default:
3397                         return 0;
3398                 }
3399                 break;
3400         default:
3401                 return 0;
3402         }
3403
3404         chv_set_phy_signal_level(encoder, deemph_reg_value,
3405                                  margin_reg_value, uniq_trans_scale);
3406
3407         return 0;
3408 }
3409
3410 static uint32_t
3411 gen4_signal_levels(uint8_t train_set)
3412 {
3413         uint32_t        signal_levels = 0;
3414
3415         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3416         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3417         default:
3418                 signal_levels |= DP_VOLTAGE_0_4;
3419                 break;
3420         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3421                 signal_levels |= DP_VOLTAGE_0_6;
3422                 break;
3423         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3424                 signal_levels |= DP_VOLTAGE_0_8;
3425                 break;
3426         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3427                 signal_levels |= DP_VOLTAGE_1_2;
3428                 break;
3429         }
3430         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3431         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3432         default:
3433                 signal_levels |= DP_PRE_EMPHASIS_0;
3434                 break;
3435         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3436                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3437                 break;
3438         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3439                 signal_levels |= DP_PRE_EMPHASIS_6;
3440                 break;
3441         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3442                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3443                 break;
3444         }
3445         return signal_levels;
3446 }
3447
3448 /* Gen6's DP voltage swing and pre-emphasis control */
3449 static uint32_t
3450 gen6_edp_signal_levels(uint8_t train_set)
3451 {
3452         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3453                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3454         switch (signal_levels) {
3455         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3456         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3457                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3458         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3459                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3460         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3461         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3462                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3463         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3464         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3465                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3468                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3469         default:
3470                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3471                               "0x%x\n", signal_levels);
3472                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3473         }
3474 }
3475
3476 /* Gen7's DP voltage swing and pre-emphasis control */
3477 static uint32_t
3478 gen7_edp_signal_levels(uint8_t train_set)
3479 {
3480         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3481                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3482         switch (signal_levels) {
3483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3484                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3485         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3486                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3488                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3489
3490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3491                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3492         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3493                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3494
3495         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3496                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3497         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3498                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3499
3500         default:
3501                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3502                               "0x%x\n", signal_levels);
3503                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3504         }
3505 }
3506
3507 void
3508 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3509 {
3510         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3511         enum port port = intel_dig_port->port;
3512         struct drm_device *dev = intel_dig_port->base.base.dev;
3513         struct drm_i915_private *dev_priv = to_i915(dev);
3514         uint32_t signal_levels, mask = 0;
3515         uint8_t train_set = intel_dp->train_set[0];
3516
3517         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3518                 signal_levels = bxt_signal_levels(intel_dp);
3519         } else if (HAS_DDI(dev_priv)) {
3520                 signal_levels = ddi_signal_levels(intel_dp);
3521                 mask = DDI_BUF_EMP_MASK;
3522         } else if (IS_CHERRYVIEW(dev_priv)) {
3523                 signal_levels = chv_signal_levels(intel_dp);
3524         } else if (IS_VALLEYVIEW(dev_priv)) {
3525                 signal_levels = vlv_signal_levels(intel_dp);
3526         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3527                 signal_levels = gen7_edp_signal_levels(train_set);
3528                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3529         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3530                 signal_levels = gen6_edp_signal_levels(train_set);
3531                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3532         } else {
3533                 signal_levels = gen4_signal_levels(train_set);
3534                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3535         }
3536
3537         if (mask)
3538                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3539
3540         DRM_DEBUG_KMS("Using vswing level %d\n",
3541                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3542         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3543                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3544                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3545
3546         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3547
3548         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3549         POSTING_READ(intel_dp->output_reg);
3550 }
3551
3552 void
3553 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3554                                        uint8_t dp_train_pat)
3555 {
3556         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3557         struct drm_i915_private *dev_priv =
3558                 to_i915(intel_dig_port->base.base.dev);
3559
3560         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3561
3562         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3563         POSTING_READ(intel_dp->output_reg);
3564 }
3565
3566 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3567 {
3568         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3569         struct drm_device *dev = intel_dig_port->base.base.dev;
3570         struct drm_i915_private *dev_priv = to_i915(dev);
3571         enum port port = intel_dig_port->port;
3572         uint32_t val;
3573
3574         if (!HAS_DDI(dev_priv))
3575                 return;
3576
3577         val = I915_READ(DP_TP_CTL(port));
3578         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3579         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3580         I915_WRITE(DP_TP_CTL(port), val);
3581
3582         /*
3583          * On PORT_A we can have only eDP in SST mode. There the only reason
3584          * we need to set idle transmission mode is to work around a HW issue
3585          * where we enable the pipe while not in idle link-training mode.
3586          * In this case there is requirement to wait for a minimum number of
3587          * idle patterns to be sent.
3588          */
3589         if (port == PORT_A)
3590                 return;
3591
3592         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3593                                     DP_TP_STATUS_IDLE_DONE,
3594                                     DP_TP_STATUS_IDLE_DONE,
3595                                     1))
3596                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3597 }
3598
3599 static void
3600 intel_dp_link_down(struct intel_dp *intel_dp)
3601 {
3602         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3603         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3604         enum port port = intel_dig_port->port;
3605         struct drm_device *dev = intel_dig_port->base.base.dev;
3606         struct drm_i915_private *dev_priv = to_i915(dev);
3607         uint32_t DP = intel_dp->DP;
3608
3609         if (WARN_ON(HAS_DDI(dev_priv)))
3610                 return;
3611
3612         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3613                 return;
3614
3615         DRM_DEBUG_KMS("\n");
3616
3617         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3618             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3619                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3620                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3621         } else {
3622                 if (IS_CHERRYVIEW(dev_priv))
3623                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3624                 else
3625                         DP &= ~DP_LINK_TRAIN_MASK;
3626                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3627         }
3628         I915_WRITE(intel_dp->output_reg, DP);
3629         POSTING_READ(intel_dp->output_reg);
3630
3631         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3632         I915_WRITE(intel_dp->output_reg, DP);
3633         POSTING_READ(intel_dp->output_reg);
3634
3635         /*
3636          * HW workaround for IBX, we need to move the port
3637          * to transcoder A after disabling it to allow the
3638          * matching HDMI port to be enabled on transcoder A.
3639          */
3640         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3641                 /*
3642                  * We get CPU/PCH FIFO underruns on the other pipe when
3643                  * doing the workaround. Sweep them under the rug.
3644                  */
3645                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3646                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3647
3648                 /* always enable with pattern 1 (as per spec) */
3649                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3650                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3651                 I915_WRITE(intel_dp->output_reg, DP);
3652                 POSTING_READ(intel_dp->output_reg);
3653
3654                 DP &= ~DP_PORT_EN;
3655                 I915_WRITE(intel_dp->output_reg, DP);
3656                 POSTING_READ(intel_dp->output_reg);
3657
3658                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3659                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3660                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3661         }
3662
3663         msleep(intel_dp->panel_power_down_delay);
3664
3665         intel_dp->DP = DP;
3666
3667         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3668                 pps_lock(intel_dp);
3669                 intel_dp->active_pipe = INVALID_PIPE;
3670                 pps_unlock(intel_dp);
3671         }
3672 }
3673
3674 bool
3675 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3676 {
3677         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3678                              sizeof(intel_dp->dpcd)) < 0)
3679                 return false; /* aux transfer failed */
3680
3681         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3682
3683         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3684 }
3685
3686 static bool
3687 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3688 {
3689         struct drm_i915_private *dev_priv =
3690                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3691
3692         /* this function is meant to be called only once */
3693         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3694
3695         if (!intel_dp_read_dpcd(intel_dp))
3696                 return false;
3697
3698         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3699                          drm_dp_is_branch(intel_dp->dpcd));
3700
3701         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3702                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3703                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3704
3705         /* Check if the panel supports PSR */
3706         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3707                          intel_dp->psr_dpcd,
3708                          sizeof(intel_dp->psr_dpcd));
3709         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3710                 dev_priv->psr.sink_support = true;
3711                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3712         }
3713
3714         if (INTEL_GEN(dev_priv) >= 9 &&
3715             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3716                 uint8_t frame_sync_cap;
3717
3718                 dev_priv->psr.sink_support = true;
3719                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3720                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3721                                       &frame_sync_cap) != 1)
3722                         frame_sync_cap = 0;
3723                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3724                 /* PSR2 needs frame sync as well */
3725                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3726                 DRM_DEBUG_KMS("PSR2 %s on sink",
3727                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3728
3729                 if (dev_priv->psr.psr2_support) {
3730                         dev_priv->psr.y_cord_support =
3731                                 intel_dp_get_y_cord_status(intel_dp);
3732                         dev_priv->psr.colorimetry_support =
3733                                 intel_dp_get_colorimetry_status(intel_dp);
3734                         dev_priv->psr.alpm =
3735                                 intel_dp_get_alpm_status(intel_dp);
3736                 }
3737
3738         }
3739
3740         /* Read the eDP Display control capabilities registers */
3741         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3742             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3743                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3744                              sizeof(intel_dp->edp_dpcd))
3745                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3746                               intel_dp->edp_dpcd);
3747
3748         /* Intermediate frequency support */
3749         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3750                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3751                 int i;
3752
3753                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3754                                 sink_rates, sizeof(sink_rates));
3755
3756                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3757                         int val = le16_to_cpu(sink_rates[i]);
3758
3759                         if (val == 0)
3760                                 break;
3761
3762                         /* Value read multiplied by 200kHz gives the per-lane
3763                          * link rate in kHz. The source rates are, however,
3764                          * stored in terms of LS_Clk kHz. The full conversion
3765                          * back to symbols is
3766                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3767                          */
3768                         intel_dp->sink_rates[i] = (val * 200) / 10;
3769                 }
3770                 intel_dp->num_sink_rates = i;
3771         }
3772
3773         if (intel_dp->num_sink_rates)
3774                 intel_dp->use_rate_select = true;
3775         else
3776                 intel_dp_set_sink_rates(intel_dp);
3777
3778         intel_dp_set_common_rates(intel_dp);
3779
3780         return true;
3781 }
3782
3783
3784 static bool
3785 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3786 {
3787         u8 sink_count;
3788
3789         if (!intel_dp_read_dpcd(intel_dp))
3790                 return false;
3791
3792         /* Don't clobber cached eDP rates. */
3793         if (!intel_dp_is_edp(intel_dp)) {
3794                 intel_dp_set_sink_rates(intel_dp);
3795                 intel_dp_set_common_rates(intel_dp);
3796         }
3797
3798         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3799                 return false;
3800
3801         /*
3802          * Sink count can change between short pulse hpd hence
3803          * a member variable in intel_dp will track any changes
3804          * between short pulse interrupts.
3805          */
3806         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3807
3808         /*
3809          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3810          * a dongle is present but no display. Unless we require to know
3811          * if a dongle is present or not, we don't need to update
3812          * downstream port information. So, an early return here saves
3813          * time from performing other operations which are not required.
3814          */
3815         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3816                 return false;
3817
3818         if (!drm_dp_is_branch(intel_dp->dpcd))
3819                 return true; /* native DP sink */
3820
3821         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3822                 return true; /* no per-port downstream info */
3823
3824         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3825                              intel_dp->downstream_ports,
3826                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3827                 return false; /* downstream port status fetch failed */
3828
3829         return true;
3830 }
3831
3832 static bool
3833 intel_dp_can_mst(struct intel_dp *intel_dp)
3834 {
3835         u8 mstm_cap;
3836
3837         if (!i915_modparams.enable_dp_mst)
3838                 return false;
3839
3840         if (!intel_dp->can_mst)
3841                 return false;
3842
3843         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3844                 return false;
3845
3846         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3847                 return false;
3848
3849         return mstm_cap & DP_MST_CAP;
3850 }
3851
3852 static void
3853 intel_dp_configure_mst(struct intel_dp *intel_dp)
3854 {
3855         if (!i915_modparams.enable_dp_mst)
3856                 return;
3857
3858         if (!intel_dp->can_mst)
3859                 return;
3860
3861         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3862
3863         if (intel_dp->is_mst)
3864                 DRM_DEBUG_KMS("Sink is MST capable\n");
3865         else
3866                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3867
3868         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3869                                         intel_dp->is_mst);
3870 }
3871
3872 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3873 {
3874         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3875         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3876         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3877         u8 buf;
3878         int ret = 0;
3879         int count = 0;
3880         int attempts = 10;
3881
3882         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3883                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3884                 ret = -EIO;
3885                 goto out;
3886         }
3887
3888         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3889                                buf & ~DP_TEST_SINK_START) < 0) {
3890                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3891                 ret = -EIO;
3892                 goto out;
3893         }
3894
3895         do {
3896                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3897
3898                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3899                                       DP_TEST_SINK_MISC, &buf) < 0) {
3900                         ret = -EIO;
3901                         goto out;
3902                 }
3903                 count = buf & DP_TEST_COUNT_MASK;
3904         } while (--attempts && count);
3905
3906         if (attempts == 0) {
3907                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3908                 ret = -ETIMEDOUT;
3909         }
3910
3911  out:
3912         hsw_enable_ips(intel_crtc);
3913         return ret;
3914 }
3915
3916 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3917 {
3918         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3919         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3920         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3921         u8 buf;
3922         int ret;
3923
3924         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3925                 return -EIO;
3926
3927         if (!(buf & DP_TEST_CRC_SUPPORTED))
3928                 return -ENOTTY;
3929
3930         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3931                 return -EIO;
3932
3933         if (buf & DP_TEST_SINK_START) {
3934                 ret = intel_dp_sink_crc_stop(intel_dp);
3935                 if (ret)
3936                         return ret;
3937         }
3938
3939         hsw_disable_ips(intel_crtc);
3940
3941         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3942                                buf | DP_TEST_SINK_START) < 0) {
3943                 hsw_enable_ips(intel_crtc);
3944                 return -EIO;
3945         }
3946
3947         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3948         return 0;
3949 }
3950
3951 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3952 {
3953         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3954         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3955         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3956         u8 buf;
3957         int count, ret;
3958         int attempts = 6;
3959
3960         ret = intel_dp_sink_crc_start(intel_dp);
3961         if (ret)
3962                 return ret;
3963
3964         do {
3965                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3966
3967                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3968                                       DP_TEST_SINK_MISC, &buf) < 0) {
3969                         ret = -EIO;
3970                         goto stop;
3971                 }
3972                 count = buf & DP_TEST_COUNT_MASK;
3973
3974         } while (--attempts && count == 0);
3975
3976         if (attempts == 0) {
3977                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3978                 ret = -ETIMEDOUT;
3979                 goto stop;
3980         }
3981
3982         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3983                 ret = -EIO;
3984                 goto stop;
3985         }
3986
3987 stop:
3988         intel_dp_sink_crc_stop(intel_dp);
3989         return ret;
3990 }
3991
3992 static bool
3993 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3994 {
3995         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3996                                  sink_irq_vector) == 1;
3997 }
3998
3999 static bool
4000 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4001 {
4002         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4003                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4004                 DP_DPRX_ESI_LEN;
4005 }
4006
4007 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4008 {
4009         int status = 0;
4010         int test_link_rate;
4011         uint8_t test_lane_count, test_link_bw;
4012         /* (DP CTS 1.2)
4013          * 4.3.1.11
4014          */
4015         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4016         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4017                                    &test_lane_count);
4018
4019         if (status <= 0) {
4020                 DRM_DEBUG_KMS("Lane count read failed\n");
4021                 return DP_TEST_NAK;
4022         }
4023         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4024
4025         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4026                                    &test_link_bw);
4027         if (status <= 0) {
4028                 DRM_DEBUG_KMS("Link Rate read failed\n");
4029                 return DP_TEST_NAK;
4030         }
4031         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4032
4033         /* Validate the requested link rate and lane count */
4034         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4035                                         test_lane_count))
4036                 return DP_TEST_NAK;
4037
4038         intel_dp->compliance.test_lane_count = test_lane_count;
4039         intel_dp->compliance.test_link_rate = test_link_rate;
4040
4041         return DP_TEST_ACK;
4042 }
4043
4044 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4045 {
4046         uint8_t test_pattern;
4047         uint8_t test_misc;
4048         __be16 h_width, v_height;
4049         int status = 0;
4050
4051         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4052         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4053                                    &test_pattern);
4054         if (status <= 0) {
4055                 DRM_DEBUG_KMS("Test pattern read failed\n");
4056                 return DP_TEST_NAK;
4057         }
4058         if (test_pattern != DP_COLOR_RAMP)
4059                 return DP_TEST_NAK;
4060
4061         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4062                                   &h_width, 2);
4063         if (status <= 0) {
4064                 DRM_DEBUG_KMS("H Width read failed\n");
4065                 return DP_TEST_NAK;
4066         }
4067
4068         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4069                                   &v_height, 2);
4070         if (status <= 0) {
4071                 DRM_DEBUG_KMS("V Height read failed\n");
4072                 return DP_TEST_NAK;
4073         }
4074
4075         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4076                                    &test_misc);
4077         if (status <= 0) {
4078                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4079                 return DP_TEST_NAK;
4080         }
4081         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4082                 return DP_TEST_NAK;
4083         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4084                 return DP_TEST_NAK;
4085         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4086         case DP_TEST_BIT_DEPTH_6:
4087                 intel_dp->compliance.test_data.bpc = 6;
4088                 break;
4089         case DP_TEST_BIT_DEPTH_8:
4090                 intel_dp->compliance.test_data.bpc = 8;
4091                 break;
4092         default:
4093                 return DP_TEST_NAK;
4094         }
4095
4096         intel_dp->compliance.test_data.video_pattern = test_pattern;
4097         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4098         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4099         /* Set test active flag here so userspace doesn't interrupt things */
4100         intel_dp->compliance.test_active = 1;
4101
4102         return DP_TEST_ACK;
4103 }
4104
4105 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4106 {
4107         uint8_t test_result = DP_TEST_ACK;
4108         struct intel_connector *intel_connector = intel_dp->attached_connector;
4109         struct drm_connector *connector = &intel_connector->base;
4110
4111         if (intel_connector->detect_edid == NULL ||
4112             connector->edid_corrupt ||
4113             intel_dp->aux.i2c_defer_count > 6) {
4114                 /* Check EDID read for NACKs, DEFERs and corruption
4115                  * (DP CTS 1.2 Core r1.1)
4116                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4117                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4118                  *    4.2.2.6 : EDID corruption detected
4119                  * Use failsafe mode for all cases
4120                  */
4121                 if (intel_dp->aux.i2c_nack_count > 0 ||
4122                         intel_dp->aux.i2c_defer_count > 0)
4123                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4124                                       intel_dp->aux.i2c_nack_count,
4125                                       intel_dp->aux.i2c_defer_count);
4126                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4127         } else {
4128                 struct edid *block = intel_connector->detect_edid;
4129
4130                 /* We have to write the checksum
4131                  * of the last block read
4132                  */
4133                 block += intel_connector->detect_edid->extensions;
4134
4135                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4136                                        block->checksum) <= 0)
4137                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4138
4139                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4140                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4141         }
4142
4143         /* Set test active flag here so userspace doesn't interrupt things */
4144         intel_dp->compliance.test_active = 1;
4145
4146         return test_result;
4147 }
4148
4149 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4150 {
4151         uint8_t test_result = DP_TEST_NAK;
4152         return test_result;
4153 }
4154
4155 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4156 {
4157         uint8_t response = DP_TEST_NAK;
4158         uint8_t request = 0;
4159         int status;
4160
4161         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4162         if (status <= 0) {
4163                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4164                 goto update_status;
4165         }
4166
4167         switch (request) {
4168         case DP_TEST_LINK_TRAINING:
4169                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4170                 response = intel_dp_autotest_link_training(intel_dp);
4171                 break;
4172         case DP_TEST_LINK_VIDEO_PATTERN:
4173                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4174                 response = intel_dp_autotest_video_pattern(intel_dp);
4175                 break;
4176         case DP_TEST_LINK_EDID_READ:
4177                 DRM_DEBUG_KMS("EDID test requested\n");
4178                 response = intel_dp_autotest_edid(intel_dp);
4179                 break;
4180         case DP_TEST_LINK_PHY_TEST_PATTERN:
4181                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4182                 response = intel_dp_autotest_phy_pattern(intel_dp);
4183                 break;
4184         default:
4185                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4186                 break;
4187         }
4188
4189         if (response & DP_TEST_ACK)
4190                 intel_dp->compliance.test_type = request;
4191
4192 update_status:
4193         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4194         if (status <= 0)
4195                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4196 }
4197
4198 static int
4199 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4200 {
4201         bool bret;
4202
4203         if (intel_dp->is_mst) {
4204                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4205                 int ret = 0;
4206                 int retry;
4207                 bool handled;
4208                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4209 go_again:
4210                 if (bret == true) {
4211
4212                         /* check link status - esi[10] = 0x200c */
4213                         if (intel_dp->active_mst_links &&
4214                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4215                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4216                                 intel_dp_start_link_train(intel_dp);
4217                                 intel_dp_stop_link_train(intel_dp);
4218                         }
4219
4220                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4221                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4222
4223                         if (handled) {
4224                                 for (retry = 0; retry < 3; retry++) {
4225                                         int wret;
4226                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4227                                                                  DP_SINK_COUNT_ESI+1,
4228                                                                  &esi[1], 3);
4229                                         if (wret == 3) {
4230                                                 break;
4231                                         }
4232                                 }
4233
4234                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4235                                 if (bret == true) {
4236                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4237                                         goto go_again;
4238                                 }
4239                         } else
4240                                 ret = 0;
4241
4242                         return ret;
4243                 } else {
4244                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4245                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4246                         intel_dp->is_mst = false;
4247                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4248                         /* send a hotplug event */
4249                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4250                 }
4251         }
4252         return -EINVAL;
4253 }
4254
4255 static void
4256 intel_dp_retrain_link(struct intel_dp *intel_dp)
4257 {
4258         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4259         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4260         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4261
4262         /* Suppress underruns caused by re-training */
4263         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4264         if (crtc->config->has_pch_encoder)
4265                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4266                                                       intel_crtc_pch_transcoder(crtc), false);
4267
4268         intel_dp_start_link_train(intel_dp);
4269         intel_dp_stop_link_train(intel_dp);
4270
4271         /* Keep underrun reporting disabled until things are stable */
4272         intel_wait_for_vblank(dev_priv, crtc->pipe);
4273
4274         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4275         if (crtc->config->has_pch_encoder)
4276                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4277                                                       intel_crtc_pch_transcoder(crtc), true);
4278 }
4279
4280 static void
4281 intel_dp_check_link_status(struct intel_dp *intel_dp)
4282 {
4283         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4284         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4285         u8 link_status[DP_LINK_STATUS_SIZE];
4286
4287         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4288
4289         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4290                 DRM_ERROR("Failed to get link status\n");
4291                 return;
4292         }
4293
4294         if (!intel_encoder->base.crtc)
4295                 return;
4296
4297         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4298                 return;
4299
4300         /*
4301          * Validate the cached values of intel_dp->link_rate and
4302          * intel_dp->lane_count before attempting to retrain.
4303          */
4304         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4305                                         intel_dp->lane_count))
4306                 return;
4307
4308         /* Retrain if Channel EQ or CR not ok */
4309         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4310                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4311                               intel_encoder->base.name);
4312
4313                 intel_dp_retrain_link(intel_dp);
4314         }
4315 }
4316
4317 /*
4318  * According to DP spec
4319  * 5.1.2:
4320  *  1. Read DPCD
4321  *  2. Configure link according to Receiver Capabilities
4322  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4323  *  4. Check link status on receipt of hot-plug interrupt
4324  *
4325  * intel_dp_short_pulse -  handles short pulse interrupts
4326  * when full detection is not required.
4327  * Returns %true if short pulse is handled and full detection
4328  * is NOT required and %false otherwise.
4329  */
4330 static bool
4331 intel_dp_short_pulse(struct intel_dp *intel_dp)
4332 {
4333         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4334         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4335         u8 sink_irq_vector = 0;
4336         u8 old_sink_count = intel_dp->sink_count;
4337         bool ret;
4338
4339         /*
4340          * Clearing compliance test variables to allow capturing
4341          * of values for next automated test request.
4342          */
4343         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4344
4345         /*
4346          * Now read the DPCD to see if it's actually running
4347          * If the current value of sink count doesn't match with
4348          * the value that was stored earlier or dpcd read failed
4349          * we need to do full detection
4350          */
4351         ret = intel_dp_get_dpcd(intel_dp);
4352
4353         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4354                 /* No need to proceed if we are going to do full detect */
4355                 return false;
4356         }
4357
4358         /* Try to read the source of the interrupt */
4359         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4360             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4361             sink_irq_vector != 0) {
4362                 /* Clear interrupt source */
4363                 drm_dp_dpcd_writeb(&intel_dp->aux,
4364                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4365                                    sink_irq_vector);
4366
4367                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4368                         intel_dp_handle_test_request(intel_dp);
4369                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4370                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4371         }
4372
4373         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4374         intel_dp_check_link_status(intel_dp);
4375         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4376         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4377                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4378                 /* Send a Hotplug Uevent to userspace to start modeset */
4379                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4380         }
4381
4382         return true;
4383 }
4384
4385 /* XXX this is probably wrong for multiple downstream ports */
4386 static enum drm_connector_status
4387 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4388 {
4389         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4390         uint8_t *dpcd = intel_dp->dpcd;
4391         uint8_t type;
4392
4393         if (lspcon->active)
4394                 lspcon_resume(lspcon);
4395
4396         if (!intel_dp_get_dpcd(intel_dp))
4397                 return connector_status_disconnected;
4398
4399         if (intel_dp_is_edp(intel_dp))
4400                 return connector_status_connected;
4401
4402         /* if there's no downstream port, we're done */
4403         if (!drm_dp_is_branch(dpcd))
4404                 return connector_status_connected;
4405
4406         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4407         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4408             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4409
4410                 return intel_dp->sink_count ?
4411                 connector_status_connected : connector_status_disconnected;
4412         }
4413
4414         if (intel_dp_can_mst(intel_dp))
4415                 return connector_status_connected;
4416
4417         /* If no HPD, poke DDC gently */
4418         if (drm_probe_ddc(&intel_dp->aux.ddc))
4419                 return connector_status_connected;
4420
4421         /* Well we tried, say unknown for unreliable port types */
4422         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4423                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4424                 if (type == DP_DS_PORT_TYPE_VGA ||
4425                     type == DP_DS_PORT_TYPE_NON_EDID)
4426                         return connector_status_unknown;
4427         } else {
4428                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4429                         DP_DWN_STRM_PORT_TYPE_MASK;
4430                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4431                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4432                         return connector_status_unknown;
4433         }
4434
4435         /* Anything else is out of spec, warn and ignore */
4436         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4437         return connector_status_disconnected;
4438 }
4439
4440 static enum drm_connector_status
4441 edp_detect(struct intel_dp *intel_dp)
4442 {
4443         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4444         struct drm_i915_private *dev_priv = to_i915(dev);
4445         enum drm_connector_status status;
4446
4447         status = intel_panel_detect(dev_priv);
4448         if (status == connector_status_unknown)
4449                 status = connector_status_connected;
4450
4451         return status;
4452 }
4453
4454 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4455                                        struct intel_digital_port *port)
4456 {
4457         u32 bit;
4458
4459         switch (port->port) {
4460         case PORT_B:
4461                 bit = SDE_PORTB_HOTPLUG;
4462                 break;
4463         case PORT_C:
4464                 bit = SDE_PORTC_HOTPLUG;
4465                 break;
4466         case PORT_D:
4467                 bit = SDE_PORTD_HOTPLUG;
4468                 break;
4469         default:
4470                 MISSING_CASE(port->port);
4471                 return false;
4472         }
4473
4474         return I915_READ(SDEISR) & bit;
4475 }
4476
4477 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4478                                        struct intel_digital_port *port)
4479 {
4480         u32 bit;
4481
4482         switch (port->port) {
4483         case PORT_B:
4484                 bit = SDE_PORTB_HOTPLUG_CPT;
4485                 break;
4486         case PORT_C:
4487                 bit = SDE_PORTC_HOTPLUG_CPT;
4488                 break;
4489         case PORT_D:
4490                 bit = SDE_PORTD_HOTPLUG_CPT;
4491                 break;
4492         default:
4493                 MISSING_CASE(port->port);
4494                 return false;
4495         }
4496
4497         return I915_READ(SDEISR) & bit;
4498 }
4499
4500 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4501                                        struct intel_digital_port *port)
4502 {
4503         u32 bit;
4504
4505         switch (port->port) {
4506         case PORT_A:
4507                 bit = SDE_PORTA_HOTPLUG_SPT;
4508                 break;
4509         case PORT_E:
4510                 bit = SDE_PORTE_HOTPLUG_SPT;
4511                 break;
4512         default:
4513                 return cpt_digital_port_connected(dev_priv, port);
4514         }
4515
4516         return I915_READ(SDEISR) & bit;
4517 }
4518
4519 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4520                                        struct intel_digital_port *port)
4521 {
4522         u32 bit;
4523
4524         switch (port->port) {
4525         case PORT_B:
4526                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4527                 break;
4528         case PORT_C:
4529                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4530                 break;
4531         case PORT_D:
4532                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4533                 break;
4534         default:
4535                 MISSING_CASE(port->port);
4536                 return false;
4537         }
4538
4539         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4540 }
4541
4542 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4543                                         struct intel_digital_port *port)
4544 {
4545         u32 bit;
4546
4547         switch (port->port) {
4548         case PORT_B:
4549                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4550                 break;
4551         case PORT_C:
4552                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4553                 break;
4554         case PORT_D:
4555                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4556                 break;
4557         default:
4558                 MISSING_CASE(port->port);
4559                 return false;
4560         }
4561
4562         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4563 }
4564
4565 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4566                                        struct intel_digital_port *port)
4567 {
4568         if (port->port == PORT_A)
4569                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4570         else
4571                 return ibx_digital_port_connected(dev_priv, port);
4572 }
4573
4574 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4575                                        struct intel_digital_port *port)
4576 {
4577         if (port->port == PORT_A)
4578                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4579         else
4580                 return cpt_digital_port_connected(dev_priv, port);
4581 }
4582
4583 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4584                                        struct intel_digital_port *port)
4585 {
4586         if (port->port == PORT_A)
4587                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4588         else
4589                 return cpt_digital_port_connected(dev_priv, port);
4590 }
4591
4592 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4593                                        struct intel_digital_port *port)
4594 {
4595         if (port->port == PORT_A)
4596                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4597         else
4598                 return cpt_digital_port_connected(dev_priv, port);
4599 }
4600
4601 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4602                                        struct intel_digital_port *intel_dig_port)
4603 {
4604         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4605         enum port port;
4606         u32 bit;
4607
4608         port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4609         switch (port) {
4610         case PORT_A:
4611                 bit = BXT_DE_PORT_HP_DDIA;
4612                 break;
4613         case PORT_B:
4614                 bit = BXT_DE_PORT_HP_DDIB;
4615                 break;
4616         case PORT_C:
4617                 bit = BXT_DE_PORT_HP_DDIC;
4618                 break;
4619         default:
4620                 MISSING_CASE(port);
4621                 return false;
4622         }
4623
4624         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4625 }
4626
4627 /*
4628  * intel_digital_port_connected - is the specified port connected?
4629  * @dev_priv: i915 private structure
4630  * @port: the port to test
4631  *
4632  * Return %true if @port is connected, %false otherwise.
4633  */
4634 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4635                                   struct intel_digital_port *port)
4636 {
4637         if (HAS_GMCH_DISPLAY(dev_priv)) {
4638                 if (IS_GM45(dev_priv))
4639                         return gm45_digital_port_connected(dev_priv, port);
4640                 else
4641                         return g4x_digital_port_connected(dev_priv, port);
4642         }
4643
4644         if (IS_GEN5(dev_priv))
4645                 return ilk_digital_port_connected(dev_priv, port);
4646         else if (IS_GEN6(dev_priv))
4647                 return snb_digital_port_connected(dev_priv, port);
4648         else if (IS_GEN7(dev_priv))
4649                 return ivb_digital_port_connected(dev_priv, port);
4650         else if (IS_GEN8(dev_priv))
4651                 return bdw_digital_port_connected(dev_priv, port);
4652         else if (IS_GEN9_LP(dev_priv))
4653                 return bxt_digital_port_connected(dev_priv, port);
4654         else
4655                 return spt_digital_port_connected(dev_priv, port);
4656 }
4657
4658 static struct edid *
4659 intel_dp_get_edid(struct intel_dp *intel_dp)
4660 {
4661         struct intel_connector *intel_connector = intel_dp->attached_connector;
4662
4663         /* use cached edid if we have one */
4664         if (intel_connector->edid) {
4665                 /* invalid edid */
4666                 if (IS_ERR(intel_connector->edid))
4667                         return NULL;
4668
4669                 return drm_edid_duplicate(intel_connector->edid);
4670         } else
4671                 return drm_get_edid(&intel_connector->base,
4672                                     &intel_dp->aux.ddc);
4673 }
4674
4675 static void
4676 intel_dp_set_edid(struct intel_dp *intel_dp)
4677 {
4678         struct intel_connector *intel_connector = intel_dp->attached_connector;
4679         struct edid *edid;
4680
4681         intel_dp_unset_edid(intel_dp);
4682         edid = intel_dp_get_edid(intel_dp);
4683         intel_connector->detect_edid = edid;
4684
4685         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4686 }
4687
4688 static void
4689 intel_dp_unset_edid(struct intel_dp *intel_dp)
4690 {
4691         struct intel_connector *intel_connector = intel_dp->attached_connector;
4692
4693         kfree(intel_connector->detect_edid);
4694         intel_connector->detect_edid = NULL;
4695
4696         intel_dp->has_audio = false;
4697 }
4698
4699 static int
4700 intel_dp_long_pulse(struct intel_connector *intel_connector)
4701 {
4702         struct drm_connector *connector = &intel_connector->base;
4703         struct intel_dp *intel_dp = intel_attached_dp(connector);
4704         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4705         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4706         struct drm_device *dev = connector->dev;
4707         enum drm_connector_status status;
4708         u8 sink_irq_vector = 0;
4709
4710         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4711
4712         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4713
4714         /* Can't disconnect eDP, but you can close the lid... */
4715         if (intel_dp_is_edp(intel_dp))
4716                 status = edp_detect(intel_dp);
4717         else if (intel_digital_port_connected(to_i915(dev),
4718                                               dp_to_dig_port(intel_dp)))
4719                 status = intel_dp_detect_dpcd(intel_dp);
4720         else
4721                 status = connector_status_disconnected;
4722
4723         if (status == connector_status_disconnected) {
4724                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4725
4726                 if (intel_dp->is_mst) {
4727                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4728                                       intel_dp->is_mst,
4729                                       intel_dp->mst_mgr.mst_state);
4730                         intel_dp->is_mst = false;
4731                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4732                                                         intel_dp->is_mst);
4733                 }
4734
4735                 goto out;
4736         }
4737
4738         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4739                 intel_encoder->type = INTEL_OUTPUT_DP;
4740
4741         if (intel_dp->reset_link_params) {
4742                 /* Initial max link lane count */
4743                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4744
4745                 /* Initial max link rate */
4746                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4747
4748                 intel_dp->reset_link_params = false;
4749         }
4750
4751         intel_dp_print_rates(intel_dp);
4752
4753         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4754                          drm_dp_is_branch(intel_dp->dpcd));
4755
4756         intel_dp_configure_mst(intel_dp);
4757
4758         if (intel_dp->is_mst) {
4759                 /*
4760                  * If we are in MST mode then this connector
4761                  * won't appear connected or have anything
4762                  * with EDID on it
4763                  */
4764                 status = connector_status_disconnected;
4765                 goto out;
4766         } else {
4767                 /*
4768                  * If display is now connected check links status,
4769                  * there has been known issues of link loss triggerring
4770                  * long pulse.
4771                  *
4772                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4773                  * weird HPD ping pong during modesets. So we can apparently
4774                  * end up with HPD going low during a modeset, and then
4775                  * going back up soon after. And once that happens we must
4776                  * retrain the link to get a picture. That's in case no
4777                  * userspace component reacted to intermittent HPD dip.
4778                  */
4779                 intel_dp_check_link_status(intel_dp);
4780         }
4781
4782         /*
4783          * Clearing NACK and defer counts to get their exact values
4784          * while reading EDID which are required by Compliance tests
4785          * 4.2.2.4 and 4.2.2.5
4786          */
4787         intel_dp->aux.i2c_nack_count = 0;
4788         intel_dp->aux.i2c_defer_count = 0;
4789
4790         intel_dp_set_edid(intel_dp);
4791         if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
4792                 status = connector_status_connected;
4793         intel_dp->detect_done = true;
4794
4795         /* Try to read the source of the interrupt */
4796         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4797             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4798             sink_irq_vector != 0) {
4799                 /* Clear interrupt source */
4800                 drm_dp_dpcd_writeb(&intel_dp->aux,
4801                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4802                                    sink_irq_vector);
4803
4804                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4805                         intel_dp_handle_test_request(intel_dp);
4806                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4807                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4808         }
4809
4810 out:
4811         if (status != connector_status_connected && !intel_dp->is_mst)
4812                 intel_dp_unset_edid(intel_dp);
4813
4814         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4815         return status;
4816 }
4817
4818 static int
4819 intel_dp_detect(struct drm_connector *connector,
4820                 struct drm_modeset_acquire_ctx *ctx,
4821                 bool force)
4822 {
4823         struct intel_dp *intel_dp = intel_attached_dp(connector);
4824         int status = connector->status;
4825
4826         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4827                       connector->base.id, connector->name);
4828
4829         /* If full detect is not performed yet, do a full detect */
4830         if (!intel_dp->detect_done)
4831                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4832
4833         intel_dp->detect_done = false;
4834
4835         return status;
4836 }
4837
4838 static void
4839 intel_dp_force(struct drm_connector *connector)
4840 {
4841         struct intel_dp *intel_dp = intel_attached_dp(connector);
4842         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4843         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4844
4845         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4846                       connector->base.id, connector->name);
4847         intel_dp_unset_edid(intel_dp);
4848
4849         if (connector->status != connector_status_connected)
4850                 return;
4851
4852         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4853
4854         intel_dp_set_edid(intel_dp);
4855
4856         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4857
4858         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4859                 intel_encoder->type = INTEL_OUTPUT_DP;
4860 }
4861
4862 static int intel_dp_get_modes(struct drm_connector *connector)
4863 {
4864         struct intel_connector *intel_connector = to_intel_connector(connector);
4865         struct edid *edid;
4866
4867         edid = intel_connector->detect_edid;
4868         if (edid) {
4869                 int ret = intel_connector_update_modes(connector, edid);
4870                 if (ret)
4871                         return ret;
4872         }
4873
4874         /* if eDP has no EDID, fall back to fixed mode */
4875         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4876             intel_connector->panel.fixed_mode) {
4877                 struct drm_display_mode *mode;
4878
4879                 mode = drm_mode_duplicate(connector->dev,
4880                                           intel_connector->panel.fixed_mode);
4881                 if (mode) {
4882                         drm_mode_probed_add(connector, mode);
4883                         return 1;
4884                 }
4885         }
4886
4887         return 0;
4888 }
4889
4890 static int
4891 intel_dp_connector_register(struct drm_connector *connector)
4892 {
4893         struct intel_dp *intel_dp = intel_attached_dp(connector);
4894         int ret;
4895
4896         ret = intel_connector_register(connector);
4897         if (ret)
4898                 return ret;
4899
4900         i915_debugfs_connector_add(connector);
4901
4902         DRM_DEBUG_KMS("registering %s bus for %s\n",
4903                       intel_dp->aux.name, connector->kdev->kobj.name);
4904
4905         intel_dp->aux.dev = connector->kdev;
4906         return drm_dp_aux_register(&intel_dp->aux);
4907 }
4908
4909 static void
4910 intel_dp_connector_unregister(struct drm_connector *connector)
4911 {
4912         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4913         intel_connector_unregister(connector);
4914 }
4915
4916 static void
4917 intel_dp_connector_destroy(struct drm_connector *connector)
4918 {
4919         struct intel_connector *intel_connector = to_intel_connector(connector);
4920
4921         kfree(intel_connector->detect_edid);
4922
4923         if (!IS_ERR_OR_NULL(intel_connector->edid))
4924                 kfree(intel_connector->edid);
4925
4926         /*
4927          * Can't call intel_dp_is_edp() since the encoder may have been
4928          * destroyed already.
4929          */
4930         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4931                 intel_panel_fini(&intel_connector->panel);
4932
4933         drm_connector_cleanup(connector);
4934         kfree(connector);
4935 }
4936
4937 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4938 {
4939         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4940         struct intel_dp *intel_dp = &intel_dig_port->dp;
4941
4942         intel_dp_mst_encoder_cleanup(intel_dig_port);
4943         if (intel_dp_is_edp(intel_dp)) {
4944                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4945                 /*
4946                  * vdd might still be enabled do to the delayed vdd off.
4947                  * Make sure vdd is actually turned off here.
4948                  */
4949                 pps_lock(intel_dp);
4950                 edp_panel_vdd_off_sync(intel_dp);
4951                 pps_unlock(intel_dp);
4952
4953                 if (intel_dp->edp_notifier.notifier_call) {
4954                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4955                         intel_dp->edp_notifier.notifier_call = NULL;
4956                 }
4957         }
4958
4959         intel_dp_aux_fini(intel_dp);
4960
4961         drm_encoder_cleanup(encoder);
4962         kfree(intel_dig_port);
4963 }
4964
4965 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4966 {
4967         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4968
4969         if (!intel_dp_is_edp(intel_dp))
4970                 return;
4971
4972         /*
4973          * vdd might still be enabled do to the delayed vdd off.
4974          * Make sure vdd is actually turned off here.
4975          */
4976         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4977         pps_lock(intel_dp);
4978         edp_panel_vdd_off_sync(intel_dp);
4979         pps_unlock(intel_dp);
4980 }
4981
4982 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4983 {
4984         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4985         struct drm_device *dev = intel_dig_port->base.base.dev;
4986         struct drm_i915_private *dev_priv = to_i915(dev);
4987
4988         lockdep_assert_held(&dev_priv->pps_mutex);
4989
4990         if (!edp_have_panel_vdd(intel_dp))
4991                 return;
4992
4993         /*
4994          * The VDD bit needs a power domain reference, so if the bit is
4995          * already enabled when we boot or resume, grab this reference and
4996          * schedule a vdd off, so we don't hold on to the reference
4997          * indefinitely.
4998          */
4999         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5000         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5001
5002         edp_panel_vdd_schedule_off(intel_dp);
5003 }
5004
5005 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5006 {
5007         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5008
5009         if ((intel_dp->DP & DP_PORT_EN) == 0)
5010                 return INVALID_PIPE;
5011
5012         if (IS_CHERRYVIEW(dev_priv))
5013                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5014         else
5015                 return PORT_TO_PIPE(intel_dp->DP);
5016 }
5017
5018 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5019 {
5020         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5021         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5022         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5023
5024         if (!HAS_DDI(dev_priv))
5025                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5026
5027         if (lspcon->active)
5028                 lspcon_resume(lspcon);
5029
5030         intel_dp->reset_link_params = true;
5031
5032         pps_lock(intel_dp);
5033
5034         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5035                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5036
5037         if (intel_dp_is_edp(intel_dp)) {
5038                 /* Reinit the power sequencer, in case BIOS did something with it. */
5039                 intel_dp_pps_init(encoder->dev, intel_dp);
5040                 intel_edp_panel_vdd_sanitize(intel_dp);
5041         }
5042
5043         pps_unlock(intel_dp);
5044 }
5045
5046 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5047         .force = intel_dp_force,
5048         .fill_modes = drm_helper_probe_single_connector_modes,
5049         .atomic_get_property = intel_digital_connector_atomic_get_property,
5050         .atomic_set_property = intel_digital_connector_atomic_set_property,
5051         .late_register = intel_dp_connector_register,
5052         .early_unregister = intel_dp_connector_unregister,
5053         .destroy = intel_dp_connector_destroy,
5054         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5055         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5056 };
5057
5058 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5059         .detect_ctx = intel_dp_detect,
5060         .get_modes = intel_dp_get_modes,
5061         .mode_valid = intel_dp_mode_valid,
5062         .atomic_check = intel_digital_connector_atomic_check,
5063 };
5064
5065 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5066         .reset = intel_dp_encoder_reset,
5067         .destroy = intel_dp_encoder_destroy,
5068 };
5069
5070 enum irqreturn
5071 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5072 {
5073         struct intel_dp *intel_dp = &intel_dig_port->dp;
5074         struct drm_device *dev = intel_dig_port->base.base.dev;
5075         struct drm_i915_private *dev_priv = to_i915(dev);
5076         enum irqreturn ret = IRQ_NONE;
5077
5078         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5079             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5080                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5081
5082         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5083                 /*
5084                  * vdd off can generate a long pulse on eDP which
5085                  * would require vdd on to handle it, and thus we
5086                  * would end up in an endless cycle of
5087                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5088                  */
5089                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5090                               port_name(intel_dig_port->port));
5091                 return IRQ_HANDLED;
5092         }
5093
5094         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5095                       port_name(intel_dig_port->port),
5096                       long_hpd ? "long" : "short");
5097
5098         if (long_hpd) {
5099                 intel_dp->reset_link_params = true;
5100                 intel_dp->detect_done = false;
5101                 return IRQ_NONE;
5102         }
5103
5104         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5105
5106         if (intel_dp->is_mst) {
5107                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5108                         /*
5109                          * If we were in MST mode, and device is not
5110                          * there, get out of MST mode
5111                          */
5112                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5113                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5114                         intel_dp->is_mst = false;
5115                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5116                                                         intel_dp->is_mst);
5117                         intel_dp->detect_done = false;
5118                         goto put_power;
5119                 }
5120         }
5121
5122         if (!intel_dp->is_mst) {
5123                 if (!intel_dp_short_pulse(intel_dp)) {
5124                         intel_dp->detect_done = false;
5125                         goto put_power;
5126                 }
5127         }
5128
5129         ret = IRQ_HANDLED;
5130
5131 put_power:
5132         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5133
5134         return ret;
5135 }
5136
5137 /* check the VBT to see whether the eDP is on another port */
5138 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5139 {
5140         /*
5141          * eDP not supported on g4x. so bail out early just
5142          * for a bit extra safety in case the VBT is bonkers.
5143          */
5144         if (INTEL_GEN(dev_priv) < 5)
5145                 return false;
5146
5147         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5148                 return true;
5149
5150         return intel_bios_is_port_edp(dev_priv, port);
5151 }
5152
5153 static void
5154 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5155 {
5156         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5157
5158         intel_attach_force_audio_property(connector);
5159         intel_attach_broadcast_rgb_property(connector);
5160
5161         if (intel_dp_is_edp(intel_dp)) {
5162                 u32 allowed_scalers;
5163
5164                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5165                 if (!HAS_GMCH_DISPLAY(dev_priv))
5166                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5167
5168                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5169
5170                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5171
5172         }
5173 }
5174
5175 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5176 {
5177         intel_dp->panel_power_off_time = ktime_get_boottime();
5178         intel_dp->last_power_on = jiffies;
5179         intel_dp->last_backlight_off = jiffies;
5180 }
5181
5182 static void
5183 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5184                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5185 {
5186         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5187         struct pps_registers regs;
5188
5189         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5190
5191         /* Workaround: Need to write PP_CONTROL with the unlock key as
5192          * the very first thing. */
5193         pp_ctl = ironlake_get_pp_control(intel_dp);
5194
5195         pp_on = I915_READ(regs.pp_on);
5196         pp_off = I915_READ(regs.pp_off);
5197         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5198                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5199                 pp_div = I915_READ(regs.pp_div);
5200         }
5201
5202         /* Pull timing values out of registers */
5203         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5204                      PANEL_POWER_UP_DELAY_SHIFT;
5205
5206         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5207                   PANEL_LIGHT_ON_DELAY_SHIFT;
5208
5209         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5210                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5211
5212         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5213                    PANEL_POWER_DOWN_DELAY_SHIFT;
5214
5215         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5216                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5217                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5218         } else {
5219                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5220                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5221         }
5222 }
5223
5224 static void
5225 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5226 {
5227         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5228                       state_name,
5229                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5230 }
5231
5232 static void
5233 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5234                        struct intel_dp *intel_dp)
5235 {
5236         struct edp_power_seq hw;
5237         struct edp_power_seq *sw = &intel_dp->pps_delays;
5238
5239         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5240
5241         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5242             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5243                 DRM_ERROR("PPS state mismatch\n");
5244                 intel_pps_dump_state("sw", sw);
5245                 intel_pps_dump_state("hw", &hw);
5246         }
5247 }
5248
5249 static void
5250 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5251                                     struct intel_dp *intel_dp)
5252 {
5253         struct drm_i915_private *dev_priv = to_i915(dev);
5254         struct edp_power_seq cur, vbt, spec,
5255                 *final = &intel_dp->pps_delays;
5256
5257         lockdep_assert_held(&dev_priv->pps_mutex);
5258
5259         /* already initialized? */
5260         if (final->t11_t12 != 0)
5261                 return;
5262
5263         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5264
5265         intel_pps_dump_state("cur", &cur);
5266
5267         vbt = dev_priv->vbt.edp.pps;
5268         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5269          * of 500ms appears to be too short. Ocassionally the panel
5270          * just fails to power back on. Increasing the delay to 800ms
5271          * seems sufficient to avoid this problem.
5272          */
5273         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5274                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5275                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5276                               vbt.t11_t12);
5277         }
5278         /* T11_T12 delay is special and actually in units of 100ms, but zero
5279          * based in the hw (so we need to add 100 ms). But the sw vbt
5280          * table multiplies it with 1000 to make it in units of 100usec,
5281          * too. */
5282         vbt.t11_t12 += 100 * 10;
5283
5284         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5285          * our hw here, which are all in 100usec. */
5286         spec.t1_t3 = 210 * 10;
5287         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5288         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5289         spec.t10 = 500 * 10;
5290         /* This one is special and actually in units of 100ms, but zero
5291          * based in the hw (so we need to add 100 ms). But the sw vbt
5292          * table multiplies it with 1000 to make it in units of 100usec,
5293          * too. */
5294         spec.t11_t12 = (510 + 100) * 10;
5295
5296         intel_pps_dump_state("vbt", &vbt);
5297
5298         /* Use the max of the register settings and vbt. If both are
5299          * unset, fall back to the spec limits. */
5300 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5301                                        spec.field : \
5302                                        max(cur.field, vbt.field))
5303         assign_final(t1_t3);
5304         assign_final(t8);
5305         assign_final(t9);
5306         assign_final(t10);
5307         assign_final(t11_t12);
5308 #undef assign_final
5309
5310 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5311         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5312         intel_dp->backlight_on_delay = get_delay(t8);
5313         intel_dp->backlight_off_delay = get_delay(t9);
5314         intel_dp->panel_power_down_delay = get_delay(t10);
5315         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5316 #undef get_delay
5317
5318         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5319                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5320                       intel_dp->panel_power_cycle_delay);
5321
5322         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5323                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5324
5325         /*
5326          * We override the HW backlight delays to 1 because we do manual waits
5327          * on them. For T8, even BSpec recommends doing it. For T9, if we
5328          * don't do this, we'll end up waiting for the backlight off delay
5329          * twice: once when we do the manual sleep, and once when we disable
5330          * the panel and wait for the PP_STATUS bit to become zero.
5331          */
5332         final->t8 = 1;
5333         final->t9 = 1;
5334 }
5335
5336 static void
5337 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5338                                               struct intel_dp *intel_dp,
5339                                               bool force_disable_vdd)
5340 {
5341         struct drm_i915_private *dev_priv = to_i915(dev);
5342         u32 pp_on, pp_off, pp_div, port_sel = 0;
5343         int div = dev_priv->rawclk_freq / 1000;
5344         struct pps_registers regs;
5345         enum port port = dp_to_dig_port(intel_dp)->port;
5346         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5347
5348         lockdep_assert_held(&dev_priv->pps_mutex);
5349
5350         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5351
5352         /*
5353          * On some VLV machines the BIOS can leave the VDD
5354          * enabled even on power seqeuencers which aren't
5355          * hooked up to any port. This would mess up the
5356          * power domain tracking the first time we pick
5357          * one of these power sequencers for use since
5358          * edp_panel_vdd_on() would notice that the VDD was
5359          * already on and therefore wouldn't grab the power
5360          * domain reference. Disable VDD first to avoid this.
5361          * This also avoids spuriously turning the VDD on as
5362          * soon as the new power seqeuencer gets initialized.
5363          */
5364         if (force_disable_vdd) {
5365                 u32 pp = ironlake_get_pp_control(intel_dp);
5366
5367                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5368
5369                 if (pp & EDP_FORCE_VDD)
5370                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5371
5372                 pp &= ~EDP_FORCE_VDD;
5373
5374                 I915_WRITE(regs.pp_ctrl, pp);
5375         }
5376
5377         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5378                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5379         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5380                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5381         /* Compute the divisor for the pp clock, simply match the Bspec
5382          * formula. */
5383         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5384                 pp_div = I915_READ(regs.pp_ctrl);
5385                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5386                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5387                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5388         } else {
5389                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5390                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5391                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5392         }
5393
5394         /* Haswell doesn't have any port selection bits for the panel
5395          * power sequencer any more. */
5396         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5397                 port_sel = PANEL_PORT_SELECT_VLV(port);
5398         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5399                 if (port == PORT_A)
5400                         port_sel = PANEL_PORT_SELECT_DPA;
5401                 else
5402                         port_sel = PANEL_PORT_SELECT_DPD;
5403         }
5404
5405         pp_on |= port_sel;
5406
5407         I915_WRITE(regs.pp_on, pp_on);
5408         I915_WRITE(regs.pp_off, pp_off);
5409         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5410                 I915_WRITE(regs.pp_ctrl, pp_div);
5411         else
5412                 I915_WRITE(regs.pp_div, pp_div);
5413
5414         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5415                       I915_READ(regs.pp_on),
5416                       I915_READ(regs.pp_off),
5417                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5418                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5419                       I915_READ(regs.pp_div));
5420 }
5421
5422 static void intel_dp_pps_init(struct drm_device *dev,
5423                               struct intel_dp *intel_dp)
5424 {
5425         struct drm_i915_private *dev_priv = to_i915(dev);
5426
5427         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5428                 vlv_initial_power_sequencer_setup(intel_dp);
5429         } else {
5430                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5431                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5432         }
5433 }
5434
5435 /**
5436  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5437  * @dev_priv: i915 device
5438  * @crtc_state: a pointer to the active intel_crtc_state
5439  * @refresh_rate: RR to be programmed
5440  *
5441  * This function gets called when refresh rate (RR) has to be changed from
5442  * one frequency to another. Switches can be between high and low RR
5443  * supported by the panel or to any other RR based on media playback (in
5444  * this case, RR value needs to be passed from user space).
5445  *
5446  * The caller of this function needs to take a lock on dev_priv->drrs.
5447  */
5448 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5449                                     const struct intel_crtc_state *crtc_state,
5450                                     int refresh_rate)
5451 {
5452         struct intel_encoder *encoder;
5453         struct intel_digital_port *dig_port = NULL;
5454         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5456         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5457
5458         if (refresh_rate <= 0) {
5459                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5460                 return;
5461         }
5462
5463         if (intel_dp == NULL) {
5464                 DRM_DEBUG_KMS("DRRS not supported.\n");
5465                 return;
5466         }
5467
5468         dig_port = dp_to_dig_port(intel_dp);
5469         encoder = &dig_port->base;
5470         intel_crtc = to_intel_crtc(encoder->base.crtc);
5471
5472         if (!intel_crtc) {
5473                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5474                 return;
5475         }
5476
5477         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5478                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5479                 return;
5480         }
5481
5482         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5483                         refresh_rate)
5484                 index = DRRS_LOW_RR;
5485
5486         if (index == dev_priv->drrs.refresh_rate_type) {
5487                 DRM_DEBUG_KMS(
5488                         "DRRS requested for previously set RR...ignoring\n");
5489                 return;
5490         }
5491
5492         if (!crtc_state->base.active) {
5493                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5494                 return;
5495         }
5496
5497         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5498                 switch (index) {
5499                 case DRRS_HIGH_RR:
5500                         intel_dp_set_m_n(intel_crtc, M1_N1);
5501                         break;
5502                 case DRRS_LOW_RR:
5503                         intel_dp_set_m_n(intel_crtc, M2_N2);
5504                         break;
5505                 case DRRS_MAX_RR:
5506                 default:
5507                         DRM_ERROR("Unsupported refreshrate type\n");
5508                 }
5509         } else if (INTEL_GEN(dev_priv) > 6) {
5510                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5511                 u32 val;
5512
5513                 val = I915_READ(reg);
5514                 if (index > DRRS_HIGH_RR) {
5515                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5516                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5517                         else
5518                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5519                 } else {
5520                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5521                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5522                         else
5523                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5524                 }
5525                 I915_WRITE(reg, val);
5526         }
5527
5528         dev_priv->drrs.refresh_rate_type = index;
5529
5530         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5531 }
5532
5533 /**
5534  * intel_edp_drrs_enable - init drrs struct if supported
5535  * @intel_dp: DP struct
5536  * @crtc_state: A pointer to the active crtc state.
5537  *
5538  * Initializes frontbuffer_bits and drrs.dp
5539  */
5540 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5541                            const struct intel_crtc_state *crtc_state)
5542 {
5543         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5544         struct drm_i915_private *dev_priv = to_i915(dev);
5545
5546         if (!crtc_state->has_drrs) {
5547                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5548                 return;
5549         }
5550
5551         if (dev_priv->psr.enabled) {
5552                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5553                 return;
5554         }
5555
5556         mutex_lock(&dev_priv->drrs.mutex);
5557         if (WARN_ON(dev_priv->drrs.dp)) {
5558                 DRM_ERROR("DRRS already enabled\n");
5559                 goto unlock;
5560         }
5561
5562         dev_priv->drrs.busy_frontbuffer_bits = 0;
5563
5564         dev_priv->drrs.dp = intel_dp;
5565
5566 unlock:
5567         mutex_unlock(&dev_priv->drrs.mutex);
5568 }
5569
5570 /**
5571  * intel_edp_drrs_disable - Disable DRRS
5572  * @intel_dp: DP struct
5573  * @old_crtc_state: Pointer to old crtc_state.
5574  *
5575  */
5576 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5577                             const struct intel_crtc_state *old_crtc_state)
5578 {
5579         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5580         struct drm_i915_private *dev_priv = to_i915(dev);
5581
5582         if (!old_crtc_state->has_drrs)
5583                 return;
5584
5585         mutex_lock(&dev_priv->drrs.mutex);
5586         if (!dev_priv->drrs.dp) {
5587                 mutex_unlock(&dev_priv->drrs.mutex);
5588                 return;
5589         }
5590
5591         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5592                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5593                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5594
5595         dev_priv->drrs.dp = NULL;
5596         mutex_unlock(&dev_priv->drrs.mutex);
5597
5598         cancel_delayed_work_sync(&dev_priv->drrs.work);
5599 }
5600
5601 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5602 {
5603         struct drm_i915_private *dev_priv =
5604                 container_of(work, typeof(*dev_priv), drrs.work.work);
5605         struct intel_dp *intel_dp;
5606
5607         mutex_lock(&dev_priv->drrs.mutex);
5608
5609         intel_dp = dev_priv->drrs.dp;
5610
5611         if (!intel_dp)
5612                 goto unlock;
5613
5614         /*
5615          * The delayed work can race with an invalidate hence we need to
5616          * recheck.
5617          */
5618
5619         if (dev_priv->drrs.busy_frontbuffer_bits)
5620                 goto unlock;
5621
5622         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5623                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5624
5625                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5626                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5627         }
5628
5629 unlock:
5630         mutex_unlock(&dev_priv->drrs.mutex);
5631 }
5632
5633 /**
5634  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5635  * @dev_priv: i915 device
5636  * @frontbuffer_bits: frontbuffer plane tracking bits
5637  *
5638  * This function gets called everytime rendering on the given planes start.
5639  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5640  *
5641  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5642  */
5643 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5644                                unsigned int frontbuffer_bits)
5645 {
5646         struct drm_crtc *crtc;
5647         enum pipe pipe;
5648
5649         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5650                 return;
5651
5652         cancel_delayed_work(&dev_priv->drrs.work);
5653
5654         mutex_lock(&dev_priv->drrs.mutex);
5655         if (!dev_priv->drrs.dp) {
5656                 mutex_unlock(&dev_priv->drrs.mutex);
5657                 return;
5658         }
5659
5660         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5661         pipe = to_intel_crtc(crtc)->pipe;
5662
5663         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5664         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5665
5666         /* invalidate means busy screen hence upclock */
5667         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5668                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5669                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5670
5671         mutex_unlock(&dev_priv->drrs.mutex);
5672 }
5673
5674 /**
5675  * intel_edp_drrs_flush - Restart Idleness DRRS
5676  * @dev_priv: i915 device
5677  * @frontbuffer_bits: frontbuffer plane tracking bits
5678  *
5679  * This function gets called every time rendering on the given planes has
5680  * completed or flip on a crtc is completed. So DRRS should be upclocked
5681  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5682  * if no other planes are dirty.
5683  *
5684  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5685  */
5686 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5687                           unsigned int frontbuffer_bits)
5688 {
5689         struct drm_crtc *crtc;
5690         enum pipe pipe;
5691
5692         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5693                 return;
5694
5695         cancel_delayed_work(&dev_priv->drrs.work);
5696
5697         mutex_lock(&dev_priv->drrs.mutex);
5698         if (!dev_priv->drrs.dp) {
5699                 mutex_unlock(&dev_priv->drrs.mutex);
5700                 return;
5701         }
5702
5703         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5704         pipe = to_intel_crtc(crtc)->pipe;
5705
5706         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5707         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5708
5709         /* flush means busy screen hence upclock */
5710         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5711                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5712                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5713
5714         /*
5715          * flush also means no more activity hence schedule downclock, if all
5716          * other fbs are quiescent too
5717          */
5718         if (!dev_priv->drrs.busy_frontbuffer_bits)
5719                 schedule_delayed_work(&dev_priv->drrs.work,
5720                                 msecs_to_jiffies(1000));
5721         mutex_unlock(&dev_priv->drrs.mutex);
5722 }
5723
5724 /**
5725  * DOC: Display Refresh Rate Switching (DRRS)
5726  *
5727  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5728  * which enables swtching between low and high refresh rates,
5729  * dynamically, based on the usage scenario. This feature is applicable
5730  * for internal panels.
5731  *
5732  * Indication that the panel supports DRRS is given by the panel EDID, which
5733  * would list multiple refresh rates for one resolution.
5734  *
5735  * DRRS is of 2 types - static and seamless.
5736  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5737  * (may appear as a blink on screen) and is used in dock-undock scenario.
5738  * Seamless DRRS involves changing RR without any visual effect to the user
5739  * and can be used during normal system usage. This is done by programming
5740  * certain registers.
5741  *
5742  * Support for static/seamless DRRS may be indicated in the VBT based on
5743  * inputs from the panel spec.
5744  *
5745  * DRRS saves power by switching to low RR based on usage scenarios.
5746  *
5747  * The implementation is based on frontbuffer tracking implementation.  When
5748  * there is a disturbance on the screen triggered by user activity or a periodic
5749  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5750  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5751  * made.
5752  *
5753  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5754  * and intel_edp_drrs_flush() are called.
5755  *
5756  * DRRS can be further extended to support other internal panels and also
5757  * the scenario of video playback wherein RR is set based on the rate
5758  * requested by userspace.
5759  */
5760
5761 /**
5762  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5763  * @intel_connector: eDP connector
5764  * @fixed_mode: preferred mode of panel
5765  *
5766  * This function is  called only once at driver load to initialize basic
5767  * DRRS stuff.
5768  *
5769  * Returns:
5770  * Downclock mode if panel supports it, else return NULL.
5771  * DRRS support is determined by the presence of downclock mode (apart
5772  * from VBT setting).
5773  */
5774 static struct drm_display_mode *
5775 intel_dp_drrs_init(struct intel_connector *intel_connector,
5776                 struct drm_display_mode *fixed_mode)
5777 {
5778         struct drm_connector *connector = &intel_connector->base;
5779         struct drm_device *dev = connector->dev;
5780         struct drm_i915_private *dev_priv = to_i915(dev);
5781         struct drm_display_mode *downclock_mode = NULL;
5782
5783         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5784         mutex_init(&dev_priv->drrs.mutex);
5785
5786         if (INTEL_GEN(dev_priv) <= 6) {
5787                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5788                 return NULL;
5789         }
5790
5791         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5792                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5793                 return NULL;
5794         }
5795
5796         downclock_mode = intel_find_panel_downclock
5797                                         (dev_priv, fixed_mode, connector);
5798
5799         if (!downclock_mode) {
5800                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5801                 return NULL;
5802         }
5803
5804         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5805
5806         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5807         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5808         return downclock_mode;
5809 }
5810
5811 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5812                                      struct intel_connector *intel_connector)
5813 {
5814         struct drm_connector *connector = &intel_connector->base;
5815         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5816         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5817         struct drm_device *dev = intel_encoder->base.dev;
5818         struct drm_i915_private *dev_priv = to_i915(dev);
5819         struct drm_display_mode *fixed_mode = NULL;
5820         struct drm_display_mode *alt_fixed_mode = NULL;
5821         struct drm_display_mode *downclock_mode = NULL;
5822         bool has_dpcd;
5823         struct drm_display_mode *scan;
5824         struct edid *edid;
5825         enum pipe pipe = INVALID_PIPE;
5826
5827         if (!intel_dp_is_edp(intel_dp))
5828                 return true;
5829
5830         /*
5831          * On IBX/CPT we may get here with LVDS already registered. Since the
5832          * driver uses the only internal power sequencer available for both
5833          * eDP and LVDS bail out early in this case to prevent interfering
5834          * with an already powered-on LVDS power sequencer.
5835          */
5836         if (intel_get_lvds_encoder(dev)) {
5837                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5838                 DRM_INFO("LVDS was detected, not registering eDP\n");
5839
5840                 return false;
5841         }
5842
5843         pps_lock(intel_dp);
5844
5845         intel_dp_init_panel_power_timestamps(intel_dp);
5846         intel_dp_pps_init(dev, intel_dp);
5847         intel_edp_panel_vdd_sanitize(intel_dp);
5848
5849         pps_unlock(intel_dp);
5850
5851         /* Cache DPCD and EDID for edp. */
5852         has_dpcd = intel_edp_init_dpcd(intel_dp);
5853
5854         if (!has_dpcd) {
5855                 /* if this fails, presume the device is a ghost */
5856                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5857                 goto out_vdd_off;
5858         }
5859
5860         mutex_lock(&dev->mode_config.mutex);
5861         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5862         if (edid) {
5863                 if (drm_add_edid_modes(connector, edid)) {
5864                         drm_mode_connector_update_edid_property(connector,
5865                                                                 edid);
5866                         drm_edid_to_eld(connector, edid);
5867                 } else {
5868                         kfree(edid);
5869                         edid = ERR_PTR(-EINVAL);
5870                 }
5871         } else {
5872                 edid = ERR_PTR(-ENOENT);
5873         }
5874         intel_connector->edid = edid;
5875
5876         /* prefer fixed mode from EDID if available, save an alt mode also */
5877         list_for_each_entry(scan, &connector->probed_modes, head) {
5878                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5879                         fixed_mode = drm_mode_duplicate(dev, scan);
5880                         downclock_mode = intel_dp_drrs_init(
5881                                                 intel_connector, fixed_mode);
5882                 } else if (!alt_fixed_mode) {
5883                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5884                 }
5885         }
5886
5887         /* fallback to VBT if available for eDP */
5888         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5889                 fixed_mode = drm_mode_duplicate(dev,
5890                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5891                 if (fixed_mode) {
5892                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5893                         connector->display_info.width_mm = fixed_mode->width_mm;
5894                         connector->display_info.height_mm = fixed_mode->height_mm;
5895                 }
5896         }
5897         mutex_unlock(&dev->mode_config.mutex);
5898
5899         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5900                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5901                 register_reboot_notifier(&intel_dp->edp_notifier);
5902
5903                 /*
5904                  * Figure out the current pipe for the initial backlight setup.
5905                  * If the current pipe isn't valid, try the PPS pipe, and if that
5906                  * fails just assume pipe A.
5907                  */
5908                 pipe = vlv_active_pipe(intel_dp);
5909
5910                 if (pipe != PIPE_A && pipe != PIPE_B)
5911                         pipe = intel_dp->pps_pipe;
5912
5913                 if (pipe != PIPE_A && pipe != PIPE_B)
5914                         pipe = PIPE_A;
5915
5916                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5917                               pipe_name(pipe));
5918         }
5919
5920         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5921                          downclock_mode);
5922         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5923         intel_panel_setup_backlight(connector, pipe);
5924
5925         return true;
5926
5927 out_vdd_off:
5928         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5929         /*
5930          * vdd might still be enabled do to the delayed vdd off.
5931          * Make sure vdd is actually turned off here.
5932          */
5933         pps_lock(intel_dp);
5934         edp_panel_vdd_off_sync(intel_dp);
5935         pps_unlock(intel_dp);
5936
5937         return false;
5938 }
5939
5940 /* Set up the hotplug pin and aux power domain. */
5941 static void
5942 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5943 {
5944         struct intel_encoder *encoder = &intel_dig_port->base;
5945         struct intel_dp *intel_dp = &intel_dig_port->dp;
5946
5947         encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port);
5948
5949         switch (intel_dig_port->port) {
5950         case PORT_A:
5951                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5952                 break;
5953         case PORT_B:
5954                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5955                 break;
5956         case PORT_C:
5957                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5958                 break;
5959         case PORT_D:
5960                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5961                 break;
5962         case PORT_E:
5963                 /* FIXME: Check VBT for actual wiring of PORT E */
5964                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5965                 break;
5966         default:
5967                 MISSING_CASE(intel_dig_port->port);
5968         }
5969 }
5970
5971 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5972 {
5973         struct intel_connector *intel_connector;
5974         struct drm_connector *connector;
5975
5976         intel_connector = container_of(work, typeof(*intel_connector),
5977                                        modeset_retry_work);
5978         connector = &intel_connector->base;
5979         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5980                       connector->name);
5981
5982         /* Grab the locks before changing connector property*/
5983         mutex_lock(&connector->dev->mode_config.mutex);
5984         /* Set connector link status to BAD and send a Uevent to notify
5985          * userspace to do a modeset.
5986          */
5987         drm_mode_connector_set_link_status_property(connector,
5988                                                     DRM_MODE_LINK_STATUS_BAD);
5989         mutex_unlock(&connector->dev->mode_config.mutex);
5990         /* Send Hotplug uevent so userspace can reprobe */
5991         drm_kms_helper_hotplug_event(connector->dev);
5992 }
5993
5994 bool
5995 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5996                         struct intel_connector *intel_connector)
5997 {
5998         struct drm_connector *connector = &intel_connector->base;
5999         struct intel_dp *intel_dp = &intel_dig_port->dp;
6000         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6001         struct drm_device *dev = intel_encoder->base.dev;
6002         struct drm_i915_private *dev_priv = to_i915(dev);
6003         enum port port = intel_dig_port->port;
6004         int type;
6005
6006         /* Initialize the work for modeset in case of link train failure */
6007         INIT_WORK(&intel_connector->modeset_retry_work,
6008                   intel_dp_modeset_retry_work_fn);
6009
6010         if (WARN(intel_dig_port->max_lanes < 1,
6011                  "Not enough lanes (%d) for DP on port %c\n",
6012                  intel_dig_port->max_lanes, port_name(port)))
6013                 return false;
6014
6015         intel_dp_set_source_rates(intel_dp);
6016
6017         intel_dp->reset_link_params = true;
6018         intel_dp->pps_pipe = INVALID_PIPE;
6019         intel_dp->active_pipe = INVALID_PIPE;
6020
6021         /* intel_dp vfuncs */
6022         if (INTEL_GEN(dev_priv) >= 9)
6023                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6024         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6025                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6026         else if (HAS_PCH_SPLIT(dev_priv))
6027                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6028         else
6029                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6030
6031         if (INTEL_GEN(dev_priv) >= 9)
6032                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6033         else
6034                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6035
6036         if (HAS_DDI(dev_priv))
6037                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6038
6039         /* Preserve the current hw state. */
6040         intel_dp->DP = I915_READ(intel_dp->output_reg);
6041         intel_dp->attached_connector = intel_connector;
6042
6043         if (intel_dp_is_port_edp(dev_priv, port))
6044                 type = DRM_MODE_CONNECTOR_eDP;
6045         else
6046                 type = DRM_MODE_CONNECTOR_DisplayPort;
6047
6048         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6049                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6050
6051         /*
6052          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6053          * for DP the encoder type can be set by the caller to
6054          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6055          */
6056         if (type == DRM_MODE_CONNECTOR_eDP)
6057                 intel_encoder->type = INTEL_OUTPUT_EDP;
6058
6059         /* eDP only on port B and/or C on vlv/chv */
6060         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6061                     intel_dp_is_edp(intel_dp) &&
6062                     port != PORT_B && port != PORT_C))
6063                 return false;
6064
6065         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6066                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6067                         port_name(port));
6068
6069         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6070         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6071
6072         connector->interlace_allowed = true;
6073         connector->doublescan_allowed = 0;
6074
6075         intel_dp_init_connector_port_info(intel_dig_port);
6076
6077         intel_dp_aux_init(intel_dp);
6078
6079         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6080                           edp_panel_vdd_work);
6081
6082         intel_connector_attach_encoder(intel_connector, intel_encoder);
6083
6084         if (HAS_DDI(dev_priv))
6085                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6086         else
6087                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6088
6089         /* init MST on ports that can support it */
6090         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6091             (port == PORT_B || port == PORT_C || port == PORT_D))
6092                 intel_dp_mst_encoder_init(intel_dig_port,
6093                                           intel_connector->base.base.id);
6094
6095         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6096                 intel_dp_aux_fini(intel_dp);
6097                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6098                 goto fail;
6099         }
6100
6101         intel_dp_add_properties(intel_dp, connector);
6102
6103         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6104          * 0xd.  Failure to do so will result in spurious interrupts being
6105          * generated on the port when a cable is not attached.
6106          */
6107         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6108                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6109                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6110         }
6111
6112         return true;
6113
6114 fail:
6115         drm_connector_cleanup(connector);
6116
6117         return false;
6118 }
6119
6120 bool intel_dp_init(struct drm_i915_private *dev_priv,
6121                    i915_reg_t output_reg,
6122                    enum port port)
6123 {
6124         struct intel_digital_port *intel_dig_port;
6125         struct intel_encoder *intel_encoder;
6126         struct drm_encoder *encoder;
6127         struct intel_connector *intel_connector;
6128
6129         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6130         if (!intel_dig_port)
6131                 return false;
6132
6133         intel_connector = intel_connector_alloc();
6134         if (!intel_connector)
6135                 goto err_connector_alloc;
6136
6137         intel_encoder = &intel_dig_port->base;
6138         encoder = &intel_encoder->base;
6139
6140         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6141                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6142                              "DP %c", port_name(port)))
6143                 goto err_encoder_init;
6144
6145         intel_encoder->compute_config = intel_dp_compute_config;
6146         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6147         intel_encoder->get_config = intel_dp_get_config;
6148         intel_encoder->suspend = intel_dp_encoder_suspend;
6149         if (IS_CHERRYVIEW(dev_priv)) {
6150                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6151                 intel_encoder->pre_enable = chv_pre_enable_dp;
6152                 intel_encoder->enable = vlv_enable_dp;
6153                 intel_encoder->disable = vlv_disable_dp;
6154                 intel_encoder->post_disable = chv_post_disable_dp;
6155                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6156         } else if (IS_VALLEYVIEW(dev_priv)) {
6157                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6158                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6159                 intel_encoder->enable = vlv_enable_dp;
6160                 intel_encoder->disable = vlv_disable_dp;
6161                 intel_encoder->post_disable = vlv_post_disable_dp;
6162         } else if (INTEL_GEN(dev_priv) >= 5) {
6163                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6164                 intel_encoder->enable = g4x_enable_dp;
6165                 intel_encoder->disable = ilk_disable_dp;
6166                 intel_encoder->post_disable = ilk_post_disable_dp;
6167         } else {
6168                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6169                 intel_encoder->enable = g4x_enable_dp;
6170                 intel_encoder->disable = g4x_disable_dp;
6171         }
6172
6173         intel_dig_port->port = port;
6174         intel_dig_port->dp.output_reg = output_reg;
6175         intel_dig_port->max_lanes = 4;
6176
6177         intel_encoder->type = INTEL_OUTPUT_DP;
6178         intel_encoder->power_domain = intel_port_to_power_domain(port);
6179         if (IS_CHERRYVIEW(dev_priv)) {
6180                 if (port == PORT_D)
6181                         intel_encoder->crtc_mask = 1 << 2;
6182                 else
6183                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6184         } else {
6185                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6186         }
6187         intel_encoder->cloneable = 0;
6188         intel_encoder->port = port;
6189
6190         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6191         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6192
6193         if (port != PORT_A)
6194                 intel_infoframe_init(intel_dig_port);
6195
6196         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6197                 goto err_init_connector;
6198
6199         return true;
6200
6201 err_init_connector:
6202         drm_encoder_cleanup(encoder);
6203 err_encoder_init:
6204         kfree(intel_connector);
6205 err_connector_alloc:
6206         kfree(intel_dig_port);
6207         return false;
6208 }
6209
6210 void intel_dp_mst_suspend(struct drm_device *dev)
6211 {
6212         struct drm_i915_private *dev_priv = to_i915(dev);
6213         int i;
6214
6215         /* disable MST */
6216         for (i = 0; i < I915_MAX_PORTS; i++) {
6217                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6218
6219                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6220                         continue;
6221
6222                 if (intel_dig_port->dp.is_mst)
6223                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6224         }
6225 }
6226
6227 void intel_dp_mst_resume(struct drm_device *dev)
6228 {
6229         struct drm_i915_private *dev_priv = to_i915(dev);
6230         int i;
6231
6232         for (i = 0; i < I915_MAX_PORTS; i++) {
6233                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6234                 int ret;
6235
6236                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6237                         continue;
6238
6239                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6240                 if (ret)
6241                         intel_dp_check_mst_status(&intel_dig_port->dp);
6242         }
6243 }