drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 111 {
 112         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 113 }
 114
 115 static void intel_dp_link_down(struct intel_encoder *encoder,
 116                                const struct intel_crtc_state *old_crtc_state);
 117 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 118 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 119 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 120                                            const struct intel_crtc_state *crtc_state);
 121 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 122                                       enum pipe pipe);
 123 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 124
 125 /* update sink rates from dpcd */
 126 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 127 {
 128         static const int dp_rates[] = {
 129                 162000, 270000, 540000, 810000
 130         };
 131         int i, max_rate;
 132
 133         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134
 135         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 136                 if (dp_rates[i] > max_rate)
 137                         break;
 138                 intel_dp->sink_rates[i] = dp_rates[i];
 139         }
 140
 141         intel_dp->num_sink_rates = i;
 142 }
 143
 144 /* Get length of rates array potentially limited by max_rate. */
 145 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 146 {
 147         int i;
 148
 149         /* Limit results by potentially reduced max rate */
 150         for (i = 0; i < len; i++) {
 151                 if (rates[len - i - 1] <= max_rate)
 152                         return len - i;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /* Get length of common rates array potentially limited by max_rate. */
 159 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 160                                           int max_rate)
 161 {
 162         return intel_dp_rate_limit_len(intel_dp->common_rates,
 163                                        intel_dp->num_common_rates, max_rate);
 164 }
 165
 166 /* Theoretical max between source and sink */
 167 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 168 {
 169         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 170 }
 171
 172 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 173 {
 174         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 175         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 176         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 177         u32 lane_info;
 178
 179         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 180                 return 4;
 181
 182         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 183                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 184                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 185
 186         switch (lane_info) {
 187         default:
 188                 MISSING_CASE(lane_info);
 189         case 1:
 190         case 2:
 191         case 4:
 192         case 8:
 193                 return 1;
 194         case 3:
 195         case 12:
 196                 return 2;
 197         case 15:
 198                 return 4;
 199         }
 200 }
 201
 202 /* Theoretical max between source and sink */
 203 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 204 {
 205         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 206         int source_max = intel_dig_port->max_lanes;
 207         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 208         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 209
 210         return min3(source_max, sink_max, fia_max);
 211 }
 212
 213 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->max_link_lane_count;
 216 }
 217
 218 int
 219 intel_dp_link_required(int pixel_clock, int bpp)
 220 {
 221         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 222         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 223 }
 224
 225 void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
 226 {
 227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 228         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 229         enum port port = intel_dig_port->base.port;
 230         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 231         u32 ln0, ln1, lane_info;
 232
 233         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
 234                 return;
 235
 236         ln0 = I915_READ(MG_DP_MODE(port, 0));
 237         ln1 = I915_READ(MG_DP_MODE(port, 1));
 238
 239         switch (intel_dig_port->tc_type) {
 240         case TC_PORT_TYPEC:
 241                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 242                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
 243
 244                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 245                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 246                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 247
 248                 switch (lane_info) {
 249                 case 0x1:
 250                 case 0x4:
 251                         break;
 252                 case 0x2:
 253                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
 254                         break;
 255                 case 0x3:
 256                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 257                                MG_DP_MODE_CFG_DP_X2_MODE;
 258                         break;
 259                 case 0x8:
 260                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
 261                         break;
 262                 case 0xC:
 263                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 264                                MG_DP_MODE_CFG_DP_X2_MODE;
 265                         break;
 266                 case 0xF:
 267                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
 268                                MG_DP_MODE_CFG_DP_X2_MODE;
 269                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
 270                                MG_DP_MODE_CFG_DP_X2_MODE;
 271                         break;
 272                 default:
 273                         MISSING_CASE(lane_info);
 274                 }
 275                 break;
 276
 277         case TC_PORT_LEGACY:
 278                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 279                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
 280                 break;
 281
 282         default:
 283                 MISSING_CASE(intel_dig_port->tc_type);
 284                 return;
 285         }
 286
 287         I915_WRITE(MG_DP_MODE(port, 0), ln0);
 288         I915_WRITE(MG_DP_MODE(port, 1), ln1);
 289 }
 290
 291 void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
 292 {
 293         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 294         enum port port = dig_port->base.port;
 295         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 296         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 297         u32 val;
 298         int i;
 299
 300         if (tc_port == PORT_TC_NONE)
 301                 return;
 302
 303         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 304                 val = I915_READ(mg_regs[i]);
 305                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
 306                        MG_DP_MODE_CFG_TRPWR_GATING |
 307                        MG_DP_MODE_CFG_CLNPWR_GATING |
 308                        MG_DP_MODE_CFG_DIGPWR_GATING |
 309                        MG_DP_MODE_CFG_GAONPWR_GATING;
 310                 I915_WRITE(mg_regs[i], val);
 311         }
 312
 313         val = I915_READ(MG_MISC_SUS0(tc_port));
 314         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
 315                MG_MISC_SUS0_CFG_TR2PWR_GATING |
 316                MG_MISC_SUS0_CFG_CL2PWR_GATING |
 317                MG_MISC_SUS0_CFG_GAONPWR_GATING |
 318                MG_MISC_SUS0_CFG_TRPWR_GATING |
 319                MG_MISC_SUS0_CFG_CL1PWR_GATING |
 320                MG_MISC_SUS0_CFG_DGPWR_GATING;
 321         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 322 }
 323
 324 void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
 325 {
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         enum port port = dig_port->base.port;
 328         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
 329         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
 330         u32 val;
 331         int i;
 332
 333         if (tc_port == PORT_TC_NONE)
 334                 return;
 335
 336         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
 337                 val = I915_READ(mg_regs[i]);
 338                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
 339                          MG_DP_MODE_CFG_TRPWR_GATING |
 340                          MG_DP_MODE_CFG_CLNPWR_GATING |
 341                          MG_DP_MODE_CFG_DIGPWR_GATING |
 342                          MG_DP_MODE_CFG_GAONPWR_GATING);
 343                 I915_WRITE(mg_regs[i], val);
 344         }
 345
 346         val = I915_READ(MG_MISC_SUS0(tc_port));
 347         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
 348                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
 349                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
 350                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
 351                  MG_MISC_SUS0_CFG_TRPWR_GATING |
 352                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
 353                  MG_MISC_SUS0_CFG_DGPWR_GATING);
 354         I915_WRITE(MG_MISC_SUS0(tc_port), val);
 355 }
 356
 357 int
 358 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 359 {
 360         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 361          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 362          * is transmitted every LS_Clk per lane, there is no need to account for
 363          * the channel encoding that is done in the PHY layer here.
 364          */
 365
 366         return max_link_clock * max_lanes;
 367 }
 368
 369 static int
 370 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 371 {
 372         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 373         struct intel_encoder *encoder = &intel_dig_port->base;
 374         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 375         int max_dotclk = dev_priv->max_dotclk_freq;
 376         int ds_max_dotclk;
 377
 378         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 379
 380         if (type != DP_DS_PORT_TYPE_VGA)
 381                 return max_dotclk;
 382
 383         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 384                                                     intel_dp->downstream_ports);
 385
 386         if (ds_max_dotclk != 0)
 387                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 388
 389         return max_dotclk;
 390 }
 391
 392 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 393 {
 394         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 395         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 396         enum port port = dig_port->base.port;
 397
 398         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 399
 400         /* Low voltage SKUs are limited to max of 5.4G */
 401         if (voltage == VOLTAGE_INFO_0_85V)
 402                 return 540000;
 403
 404         /* For this SKU 8.1G is supported in all ports */
 405         if (IS_CNL_WITH_PORT_F(dev_priv))
 406                 return 810000;
 407
 408         /* For other SKUs, max rate on ports A and D is 5.4G */
 409         if (port == PORT_A || port == PORT_D)
 410                 return 540000;
 411
 412         return 810000;
 413 }
 414
 415 static int icl_max_source_rate(struct intel_dp *intel_dp)
 416 {
 417         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 418         enum port port = dig_port->base.port;
 419
 420         if (port == PORT_B)
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static void
 427 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 428 {
 429         /* The values must be in increasing order */
 430         static const int cnl_rates[] = {
 431                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 432         };
 433         static const int bxt_rates[] = {
 434                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 435         };
 436         static const int skl_rates[] = {
 437                 162000, 216000, 270000, 324000, 432000, 540000
 438         };
 439         static const int hsw_rates[] = {
 440                 162000, 270000, 540000
 441         };
 442         static const int g4x_rates[] = {
 443                 162000, 270000
 444         };
 445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 446         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 447         const struct ddi_vbt_port_info *info =
 448                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 449         const int *source_rates;
 450         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 451
 452         /* This should only be done once */
 453         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 454
 455         if (INTEL_GEN(dev_priv) >= 10) {
 456                 source_rates = cnl_rates;
 457                 size = ARRAY_SIZE(cnl_rates);
 458                 if (INTEL_GEN(dev_priv) == 10)
 459                         max_rate = cnl_max_source_rate(intel_dp);
 460                 else
 461                         max_rate = icl_max_source_rate(intel_dp);
 462         } else if (IS_GEN9_LP(dev_priv)) {
 463                 source_rates = bxt_rates;
 464                 size = ARRAY_SIZE(bxt_rates);
 465         } else if (IS_GEN9_BC(dev_priv)) {
 466                 source_rates = skl_rates;
 467                 size = ARRAY_SIZE(skl_rates);
 468         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 469                    IS_BROADWELL(dev_priv)) {
 470                 source_rates = hsw_rates;
 471                 size = ARRAY_SIZE(hsw_rates);
 472         } else {
 473                 source_rates = g4x_rates;
 474                 size = ARRAY_SIZE(g4x_rates);
 475         }
 476
 477         if (max_rate && vbt_max_rate)
 478                 max_rate = min(max_rate, vbt_max_rate);
 479         else if (vbt_max_rate)
 480                 max_rate = vbt_max_rate;
 481
 482         if (max_rate)
 483                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 484
 485         intel_dp->source_rates = source_rates;
 486         intel_dp->num_source_rates = size;
 487 }
 488
 489 static int intersect_rates(const int *source_rates, int source_len,
 490                            const int *sink_rates, int sink_len,
 491                            int *common_rates)
 492 {
 493         int i = 0, j = 0, k = 0;
 494
 495         while (i < source_len && j < sink_len) {
 496                 if (source_rates[i] == sink_rates[j]) {
 497                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 498                                 return k;
 499                         common_rates[k] = source_rates[i];
 500                         ++k;
 501                         ++i;
 502                         ++j;
 503                 } else if (source_rates[i] < sink_rates[j]) {
 504                         ++i;
 505                 } else {
 506                         ++j;
 507                 }
 508         }
 509         return k;
 510 }
 511
 512 /* return index of rate in rates array, or -1 if not found */
 513 static int intel_dp_rate_index(const int *rates, int len, int rate)
 514 {
 515         int i;
 516
 517         for (i = 0; i < len; i++)
 518                 if (rate == rates[i])
 519                         return i;
 520
 521         return -1;
 522 }
 523
 524 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 525 {
 526         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 527
 528         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 529                                                      intel_dp->num_source_rates,
 530                                                      intel_dp->sink_rates,
 531                                                      intel_dp->num_sink_rates,
 532                                                      intel_dp->common_rates);
 533
 534         /* Paranoia, there should always be something in common. */
 535         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 536                 intel_dp->common_rates[0] = 162000;
 537                 intel_dp->num_common_rates = 1;
 538         }
 539 }
 540
 541 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 542                                        uint8_t lane_count)
 543 {
 544         /*
 545          * FIXME: we need to synchronize the current link parameters with
 546          * hardware readout. Currently fast link training doesn't work on
 547          * boot-up.
 548          */
 549         if (link_rate == 0 ||
 550             link_rate > intel_dp->max_link_rate)
 551                 return false;
 552
 553         if (lane_count == 0 ||
 554             lane_count > intel_dp_max_lane_count(intel_dp))
 555                 return false;
 556
 557         return true;
 558 }
 559
 560 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 561                                             int link_rate, uint8_t lane_count)
 562 {
 563         int index;
 564
 565         index = intel_dp_rate_index(intel_dp->common_rates,
 566                                     intel_dp->num_common_rates,
 567                                     link_rate);
 568         if (index > 0) {
 569                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 570                 intel_dp->max_link_lane_count = lane_count;
 571         } else if (lane_count > 1) {
 572                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 573                 intel_dp->max_link_lane_count = lane_count >> 1;
 574         } else {
 575                 DRM_ERROR("Link Training Unsuccessful\n");
 576                 return -1;
 577         }
 578
 579         return 0;
 580 }
 581
 582 static enum drm_mode_status
 583 intel_dp_mode_valid(struct drm_connector *connector,
 584                     struct drm_display_mode *mode)
 585 {
 586         struct intel_dp *intel_dp = intel_attached_dp(connector);
 587         struct intel_connector *intel_connector = to_intel_connector(connector);
 588         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 589         int target_clock = mode->clock;
 590         int max_rate, mode_rate, max_lanes, max_link_clock;
 591         int max_dotclk;
 592
 593         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 594                 return MODE_NO_DBLESCAN;
 595
 596         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 597
 598         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 599                 if (mode->hdisplay > fixed_mode->hdisplay)
 600                         return MODE_PANEL;
 601
 602                 if (mode->vdisplay > fixed_mode->vdisplay)
 603                         return MODE_PANEL;
 604
 605                 target_clock = fixed_mode->clock;
 606         }
 607
 608         max_link_clock = intel_dp_max_link_rate(intel_dp);
 609         max_lanes = intel_dp_max_lane_count(intel_dp);
 610
 611         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 612         mode_rate = intel_dp_link_required(target_clock, 18);
 613
 614         if (mode_rate > max_rate || target_clock > max_dotclk)
 615                 return MODE_CLOCK_HIGH;
 616
 617         if (mode->clock < 10000)
 618                 return MODE_CLOCK_LOW;
 619
 620         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 621                 return MODE_H_ILLEGAL;
 622
 623         return MODE_OK;
 624 }
 625
 626 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 627 {
 628         int     i;
 629         uint32_t v = 0;
 630
 631         if (src_bytes > 4)
 632                 src_bytes = 4;
 633         for (i = 0; i < src_bytes; i++)
 634                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 635         return v;
 636 }
 637
 638 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 639 {
 640         int i;
 641         if (dst_bytes > 4)
 642                 dst_bytes = 4;
 643         for (i = 0; i < dst_bytes; i++)
 644                 dst[i] = src >> ((3-i) * 8);
 645 }
 646
 647 static void
 648 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 649 static void
 650 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 651                                               bool force_disable_vdd);
 652 static void
 653 intel_dp_pps_init(struct intel_dp *intel_dp);
 654
 655 static void pps_lock(struct intel_dp *intel_dp)
 656 {
 657         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 658
 659         /*
 660          * See intel_power_sequencer_reset() why we need
 661          * a power domain reference here.
 662          */
 663         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 664
 665         mutex_lock(&dev_priv->pps_mutex);
 666 }
 667
 668 static void pps_unlock(struct intel_dp *intel_dp)
 669 {
 670         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 671
 672         mutex_unlock(&dev_priv->pps_mutex);
 673
 674         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 675 }
 676
 677 static void
 678 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 679 {
 680         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 681         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 682         enum pipe pipe = intel_dp->pps_pipe;
 683         bool pll_enabled, release_cl_override = false;
 684         enum dpio_phy phy = DPIO_PHY(pipe);
 685         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 686         uint32_t DP;
 687
 688         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 689                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 690                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 691                 return;
 692
 693         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 694                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 695
 696         /* Preserve the BIOS-computed detected bit. This is
 697          * supposed to be read-only.
 698          */
 699         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 700         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 701         DP |= DP_PORT_WIDTH(1);
 702         DP |= DP_LINK_TRAIN_PAT_1;
 703
 704         if (IS_CHERRYVIEW(dev_priv))
 705                 DP |= DP_PIPE_SEL_CHV(pipe);
 706         else
 707                 DP |= DP_PIPE_SEL(pipe);
 708
 709         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 710
 711         /*
 712          * The DPLL for the pipe must be enabled for this to work.
 713          * So enable temporarily it if it's not already enabled.
 714          */
 715         if (!pll_enabled) {
 716                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 717                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 718
 719                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 720                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 721                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 722                                   pipe_name(pipe));
 723                         return;
 724                 }
 725         }
 726
 727         /*
 728          * Similar magic as in intel_dp_enable_port().
 729          * We _must_ do this port enable + disable trick
 730          * to make this power sequencer lock onto the port.
 731          * Otherwise even VDD force bit won't work.
 732          */
 733         I915_WRITE(intel_dp->output_reg, DP);
 734         POSTING_READ(intel_dp->output_reg);
 735
 736         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 737         POSTING_READ(intel_dp->output_reg);
 738
 739         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 740         POSTING_READ(intel_dp->output_reg);
 741
 742         if (!pll_enabled) {
 743                 vlv_force_pll_off(dev_priv, pipe);
 744
 745                 if (release_cl_override)
 746                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 747         }
 748 }
 749
 750 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 751 {
 752         struct intel_encoder *encoder;
 753         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 754
 755         /*
 756          * We don't have power sequencer currently.
 757          * Pick one that's not used by other ports.
 758          */
 759         for_each_intel_dp(&dev_priv->drm, encoder) {
 760                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 761
 762                 if (encoder->type == INTEL_OUTPUT_EDP) {
 763                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 764                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 765
 766                         if (intel_dp->pps_pipe != INVALID_PIPE)
 767                                 pipes &= ~(1 << intel_dp->pps_pipe);
 768                 } else {
 769                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 770
 771                         if (intel_dp->active_pipe != INVALID_PIPE)
 772                                 pipes &= ~(1 << intel_dp->active_pipe);
 773                 }
 774         }
 775
 776         if (pipes == 0)
 777                 return INVALID_PIPE;
 778
 779         return ffs(pipes) - 1;
 780 }
 781
 782 static enum pipe
 783 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 784 {
 785         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 786         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 787         enum pipe pipe;
 788
 789         lockdep_assert_held(&dev_priv->pps_mutex);
 790
 791         /* We should never land here with regular DP ports */
 792         WARN_ON(!intel_dp_is_edp(intel_dp));
 793
 794         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 795                 intel_dp->active_pipe != intel_dp->pps_pipe);
 796
 797         if (intel_dp->pps_pipe != INVALID_PIPE)
 798                 return intel_dp->pps_pipe;
 799
 800         pipe = vlv_find_free_pps(dev_priv);
 801
 802         /*
 803          * Didn't find one. This should not happen since there
 804          * are two power sequencers and up to two eDP ports.
 805          */
 806         if (WARN_ON(pipe == INVALID_PIPE))
 807                 pipe = PIPE_A;
 808
 809         vlv_steal_power_sequencer(dev_priv, pipe);
 810         intel_dp->pps_pipe = pipe;
 811
 812         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 813                       pipe_name(intel_dp->pps_pipe),
 814                       port_name(intel_dig_port->base.port));
 815
 816         /* init power sequencer on this pipe and port */
 817         intel_dp_init_panel_power_sequencer(intel_dp);
 818         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 819
 820         /*
 821          * Even vdd force doesn't work until we've made
 822          * the power sequencer lock in on the port.
 823          */
 824         vlv_power_sequencer_kick(intel_dp);
 825
 826         return intel_dp->pps_pipe;
 827 }
 828
 829 static int
 830 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 831 {
 832         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 833         int backlight_controller = dev_priv->vbt.backlight.controller;
 834
 835         lockdep_assert_held(&dev_priv->pps_mutex);
 836
 837         /* We should never land here with regular DP ports */
 838         WARN_ON(!intel_dp_is_edp(intel_dp));
 839
 840         if (!intel_dp->pps_reset)
 841                 return backlight_controller;
 842
 843         intel_dp->pps_reset = false;
 844
 845         /*
 846          * Only the HW needs to be reprogrammed, the SW state is fixed and
 847          * has been setup during connector init.
 848          */
 849         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 850
 851         return backlight_controller;
 852 }
 853
 854 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 855                                enum pipe pipe);
 856
 857 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 858                                enum pipe pipe)
 859 {
 860         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 861 }
 862
 863 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 864                                 enum pipe pipe)
 865 {
 866         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 867 }
 868
 869 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 870                          enum pipe pipe)
 871 {
 872         return true;
 873 }
 874
 875 static enum pipe
 876 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 877                      enum port port,
 878                      vlv_pipe_check pipe_check)
 879 {
 880         enum pipe pipe;
 881
 882         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 883                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 884                         PANEL_PORT_SELECT_MASK;
 885
 886                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 887                         continue;
 888
 889                 if (!pipe_check(dev_priv, pipe))
 890                         continue;
 891
 892                 return pipe;
 893         }
 894
 895         return INVALID_PIPE;
 896 }
 897
 898 static void
 899 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 902         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 903         enum port port = intel_dig_port->base.port;
 904
 905         lockdep_assert_held(&dev_priv->pps_mutex);
 906
 907         /* try to find a pipe with this port selected */
 908         /* first pick one where the panel is on */
 909         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 910                                                   vlv_pipe_has_pp_on);
 911         /* didn't find one? pick one where vdd is on */
 912         if (intel_dp->pps_pipe == INVALID_PIPE)
 913                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 914                                                           vlv_pipe_has_vdd_on);
 915         /* didn't find one? pick one with just the correct port */
 916         if (intel_dp->pps_pipe == INVALID_PIPE)
 917                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 918                                                           vlv_pipe_any);
 919
 920         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 921         if (intel_dp->pps_pipe == INVALID_PIPE) {
 922                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 923                               port_name(port));
 924                 return;
 925         }
 926
 927         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 928                       port_name(port), pipe_name(intel_dp->pps_pipe));
 929
 930         intel_dp_init_panel_power_sequencer(intel_dp);
 931         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 932 }
 933
 934 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 935 {
 936         struct intel_encoder *encoder;
 937
 938         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 939                     !IS_GEN9_LP(dev_priv)))
 940                 return;
 941
 942         /*
 943          * We can't grab pps_mutex here due to deadlock with power_domain
 944          * mutex when power_domain functions are called while holding pps_mutex.
 945          * That also means that in order to use pps_pipe the code needs to
 946          * hold both a power domain reference and pps_mutex, and the power domain
 947          * reference get/put must be done while _not_ holding pps_mutex.
 948          * pps_{lock,unlock}() do these steps in the correct order, so one
 949          * should use them always.
 950          */
 951
 952         for_each_intel_dp(&dev_priv->drm, encoder) {
 953                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 954
 955                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 956
 957                 if (encoder->type != INTEL_OUTPUT_EDP)
 958                         continue;
 959
 960                 if (IS_GEN9_LP(dev_priv))
 961                         intel_dp->pps_reset = true;
 962                 else
 963                         intel_dp->pps_pipe = INVALID_PIPE;
 964         }
 965 }
 966
 967 struct pps_registers {
 968         i915_reg_t pp_ctrl;
 969         i915_reg_t pp_stat;
 970         i915_reg_t pp_on;
 971         i915_reg_t pp_off;
 972         i915_reg_t pp_div;
 973 };
 974
 975 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 976                                     struct pps_registers *regs)
 977 {
 978         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 979         int pps_idx = 0;
 980
 981         memset(regs, 0, sizeof(*regs));
 982
 983         if (IS_GEN9_LP(dev_priv))
 984                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 985         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 986                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 987
 988         regs->pp_ctrl = PP_CONTROL(pps_idx);
 989         regs->pp_stat = PP_STATUS(pps_idx);
 990         regs->pp_on = PP_ON_DELAYS(pps_idx);
 991         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 992         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 993             !HAS_PCH_ICP(dev_priv))
 994                 regs->pp_div = PP_DIVISOR(pps_idx);
 995 }
 996
 997 static i915_reg_t
 998 _pp_ctrl_reg(struct intel_dp *intel_dp)
 999 {
1000         struct pps_registers regs;
1001
1002         intel_pps_get_registers(intel_dp, &regs);
1003
1004         return regs.pp_ctrl;
1005 }
1006
1007 static i915_reg_t
1008 _pp_stat_reg(struct intel_dp *intel_dp)
1009 {
1010         struct pps_registers regs;
1011
1012         intel_pps_get_registers(intel_dp, &regs);
1013
1014         return regs.pp_stat;
1015 }
1016
1017 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1018    This function only applicable when panel PM state is not to be tracked */
1019 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1020                               void *unused)
1021 {
1022         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1023                                                  edp_notifier);
1024         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1025
1026         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1027                 return 0;
1028
1029         pps_lock(intel_dp);
1030
1031         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1032                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1033                 i915_reg_t pp_ctrl_reg, pp_div_reg;
1034                 u32 pp_div;
1035
1036                 pp_ctrl_reg = PP_CONTROL(pipe);
1037                 pp_div_reg  = PP_DIVISOR(pipe);
1038                 pp_div = I915_READ(pp_div_reg);
1039                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1040
1041                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1042                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1043                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1044                 msleep(intel_dp->panel_power_cycle_delay);
1045         }
1046
1047         pps_unlock(intel_dp);
1048
1049         return 0;
1050 }
1051
1052 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1053 {
1054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1055
1056         lockdep_assert_held(&dev_priv->pps_mutex);
1057
1058         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1059             intel_dp->pps_pipe == INVALID_PIPE)
1060                 return false;
1061
1062         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1063 }
1064
1065 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1066 {
1067         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1068
1069         lockdep_assert_held(&dev_priv->pps_mutex);
1070
1071         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1072             intel_dp->pps_pipe == INVALID_PIPE)
1073                 return false;
1074
1075         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1076 }
1077
1078 static void
1079 intel_dp_check_edp(struct intel_dp *intel_dp)
1080 {
1081         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1082
1083         if (!intel_dp_is_edp(intel_dp))
1084                 return;
1085
1086         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1087                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1088                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1089                               I915_READ(_pp_stat_reg(intel_dp)),
1090                               I915_READ(_pp_ctrl_reg(intel_dp)));
1091         }
1092 }
1093
1094 static uint32_t
1095 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1096 {
1097         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1099         uint32_t status;
1100         bool done;
1101
1102 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1103         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1104                                   msecs_to_jiffies_timeout(10));
1105         if (!done)
1106                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1107 #undef C
1108
1109         return status;
1110 }
1111
1112 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1113 {
1114         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1115
1116         if (index)
1117                 return 0;
1118
1119         /*
1120          * The clock divider is based off the hrawclk, and would like to run at
1121          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1122          */
1123         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1124 }
1125
1126 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1127 {
1128         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1129
1130         if (index)
1131                 return 0;
1132
1133         /*
1134          * The clock divider is based off the cdclk or PCH rawclk, and would
1135          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1136          * divide by 2000 and use that
1137          */
1138         if (intel_dp->aux_ch == AUX_CH_A)
1139                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1140         else
1141                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1142 }
1143
1144 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1145 {
1146         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1147
1148         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1149                 /* Workaround for non-ULT HSW */
1150                 switch (index) {
1151                 case 0: return 63;
1152                 case 1: return 72;
1153                 default: return 0;
1154                 }
1155         }
1156
1157         return ilk_get_aux_clock_divider(intel_dp, index);
1158 }
1159
1160 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1161 {
1162         /*
1163          * SKL doesn't need us to program the AUX clock divider (Hardware will
1164          * derive the clock from CDCLK automatically). We still implement the
1165          * get_aux_clock_divider vfunc to plug-in into the existing code.
1166          */
1167         return index ? 0 : 1;
1168 }
1169
1170 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1171                                      int send_bytes,
1172                                      uint32_t aux_clock_divider)
1173 {
1174         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1175         struct drm_i915_private *dev_priv =
1176                         to_i915(intel_dig_port->base.base.dev);
1177         uint32_t precharge, timeout;
1178
1179         if (IS_GEN6(dev_priv))
1180                 precharge = 3;
1181         else
1182                 precharge = 5;
1183
1184         if (IS_BROADWELL(dev_priv))
1185                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1186         else
1187                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1188
1189         return DP_AUX_CH_CTL_SEND_BUSY |
1190                DP_AUX_CH_CTL_DONE |
1191                DP_AUX_CH_CTL_INTERRUPT |
1192                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1193                timeout |
1194                DP_AUX_CH_CTL_RECEIVE_ERROR |
1195                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1196                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1197                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1198 }
1199
1200 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1201                                       int send_bytes,
1202                                       uint32_t unused)
1203 {
1204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205         uint32_t ret;
1206
1207         ret = DP_AUX_CH_CTL_SEND_BUSY |
1208               DP_AUX_CH_CTL_DONE |
1209               DP_AUX_CH_CTL_INTERRUPT |
1210               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1211               DP_AUX_CH_CTL_TIME_OUT_MAX |
1212               DP_AUX_CH_CTL_RECEIVE_ERROR |
1213               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1214               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1215               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1216
1217         if (intel_dig_port->tc_type == TC_PORT_TBT)
1218                 ret |= DP_AUX_CH_CTL_TBT_IO;
1219
1220         return ret;
1221 }
1222
1223 static int
1224 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1225                   const uint8_t *send, int send_bytes,
1226                   uint8_t *recv, int recv_size,
1227                   u32 aux_send_ctl_flags)
1228 {
1229         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1230         struct drm_i915_private *dev_priv =
1231                         to_i915(intel_dig_port->base.base.dev);
1232         i915_reg_t ch_ctl, ch_data[5];
1233         uint32_t aux_clock_divider;
1234         int i, ret, recv_bytes;
1235         uint32_t status;
1236         int try, clock = 0;
1237         bool vdd;
1238
1239         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1240         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1241                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1242
1243         pps_lock(intel_dp);
1244
1245         /*
1246          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1247          * In such cases we want to leave VDD enabled and it's up to upper layers
1248          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1249          * ourselves.
1250          */
1251         vdd = edp_panel_vdd_on(intel_dp);
1252
1253         /* dp aux is extremely sensitive to irq latency, hence request the
1254          * lowest possible wakeup latency and so prevent the cpu from going into
1255          * deep sleep states.
1256          */
1257         pm_qos_update_request(&dev_priv->pm_qos, 0);
1258
1259         intel_dp_check_edp(intel_dp);
1260
1261         /* Try to wait for any previous AUX channel activity */
1262         for (try = 0; try < 3; try++) {
1263                 status = I915_READ_NOTRACE(ch_ctl);
1264                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1265                         break;
1266                 msleep(1);
1267         }
1268
1269         if (try == 3) {
1270                 static u32 last_status = -1;
1271                 const u32 status = I915_READ(ch_ctl);
1272
1273                 if (status != last_status) {
1274                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1275                              status);
1276                         last_status = status;
1277                 }
1278
1279                 ret = -EBUSY;
1280                 goto out;
1281         }
1282
1283         /* Only 5 data registers! */
1284         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1285                 ret = -E2BIG;
1286                 goto out;
1287         }
1288
1289         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1290                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1291                                                           send_bytes,
1292                                                           aux_clock_divider);
1293
1294                 send_ctl |= aux_send_ctl_flags;
1295
1296                 /* Must try at least 3 times according to DP spec */
1297                 for (try = 0; try < 5; try++) {
1298                         /* Load the send data into the aux channel data registers */
1299                         for (i = 0; i < send_bytes; i += 4)
1300                                 I915_WRITE(ch_data[i >> 2],
1301                                            intel_dp_pack_aux(send + i,
1302                                                              send_bytes - i));
1303
1304                         /* Send the command and wait for it to complete */
1305                         I915_WRITE(ch_ctl, send_ctl);
1306
1307                         status = intel_dp_aux_wait_done(intel_dp);
1308
1309                         /* Clear done status and any errors */
1310                         I915_WRITE(ch_ctl,
1311                                    status |
1312                                    DP_AUX_CH_CTL_DONE |
1313                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1314                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1315
1316                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1317                          *   400us delay required for errors and timeouts
1318                          *   Timeout errors from the HW already meet this
1319                          *   requirement so skip to next iteration
1320                          */
1321                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1322                                 continue;
1323
1324                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1325                                 usleep_range(400, 500);
1326                                 continue;
1327                         }
1328                         if (status & DP_AUX_CH_CTL_DONE)
1329                                 goto done;
1330                 }
1331         }
1332
1333         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1334                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1335                 ret = -EBUSY;
1336                 goto out;
1337         }
1338
1339 done:
1340         /* Check for timeout or receive error.
1341          * Timeouts occur when the sink is not connected
1342          */
1343         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1344                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1345                 ret = -EIO;
1346                 goto out;
1347         }
1348
1349         /* Timeouts occur when the device isn't connected, so they're
1350          * "normal" -- don't fill the kernel log with these */
1351         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1352                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1353                 ret = -ETIMEDOUT;
1354                 goto out;
1355         }
1356
1357         /* Unload any bytes sent back from the other side */
1358         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1359                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1360
1361         /*
1362          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1363          * We have no idea of what happened so we return -EBUSY so
1364          * drm layer takes care for the necessary retries.
1365          */
1366         if (recv_bytes == 0 || recv_bytes > 20) {
1367                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1368                               recv_bytes);
1369                 ret = -EBUSY;
1370                 goto out;
1371         }
1372
1373         if (recv_bytes > recv_size)
1374                 recv_bytes = recv_size;
1375
1376         for (i = 0; i < recv_bytes; i += 4)
1377                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1378                                     recv + i, recv_bytes - i);
1379
1380         ret = recv_bytes;
1381 out:
1382         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1383
1384         if (vdd)
1385                 edp_panel_vdd_off(intel_dp, false);
1386
1387         pps_unlock(intel_dp);
1388
1389         return ret;
1390 }
1391
1392 #define BARE_ADDRESS_SIZE       3
1393 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1394
1395 static void
1396 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1397                     const struct drm_dp_aux_msg *msg)
1398 {
1399         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1400         txbuf[1] = (msg->address >> 8) & 0xff;
1401         txbuf[2] = msg->address & 0xff;
1402         txbuf[3] = msg->size - 1;
1403 }
1404
1405 static ssize_t
1406 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1407 {
1408         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1409         uint8_t txbuf[20], rxbuf[20];
1410         size_t txsize, rxsize;
1411         int ret;
1412
1413         intel_dp_aux_header(txbuf, msg);
1414
1415         switch (msg->request & ~DP_AUX_I2C_MOT) {
1416         case DP_AUX_NATIVE_WRITE:
1417         case DP_AUX_I2C_WRITE:
1418         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1419                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1420                 rxsize = 2; /* 0 or 1 data bytes */
1421
1422                 if (WARN_ON(txsize > 20))
1423                         return -E2BIG;
1424
1425                 WARN_ON(!msg->buffer != !msg->size);
1426
1427                 if (msg->buffer)
1428                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1429
1430                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1431                                         rxbuf, rxsize, 0);
1432                 if (ret > 0) {
1433                         msg->reply = rxbuf[0] >> 4;
1434
1435                         if (ret > 1) {
1436                                 /* Number of bytes written in a short write. */
1437                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1438                         } else {
1439                                 /* Return payload size. */
1440                                 ret = msg->size;
1441                         }
1442                 }
1443                 break;
1444
1445         case DP_AUX_NATIVE_READ:
1446         case DP_AUX_I2C_READ:
1447                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1448                 rxsize = msg->size + 1;
1449
1450                 if (WARN_ON(rxsize > 20))
1451                         return -E2BIG;
1452
1453                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1454                                         rxbuf, rxsize, 0);
1455                 if (ret > 0) {
1456                         msg->reply = rxbuf[0] >> 4;
1457                         /*
1458                          * Assume happy day, and copy the data. The caller is
1459                          * expected to check msg->reply before touching it.
1460                          *
1461                          * Return payload size.
1462                          */
1463                         ret--;
1464                         memcpy(msg->buffer, rxbuf + 1, ret);
1465                 }
1466                 break;
1467
1468         default:
1469                 ret = -EINVAL;
1470                 break;
1471         }
1472
1473         return ret;
1474 }
1475
1476 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1477 {
1478         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1480         enum port port = encoder->port;
1481         const struct ddi_vbt_port_info *info =
1482                 &dev_priv->vbt.ddi_port_info[port];
1483         enum aux_ch aux_ch;
1484
1485         if (!info->alternate_aux_channel) {
1486                 aux_ch = (enum aux_ch) port;
1487
1488                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1489                               aux_ch_name(aux_ch), port_name(port));
1490                 return aux_ch;
1491         }
1492
1493         switch (info->alternate_aux_channel) {
1494         case DP_AUX_A:
1495                 aux_ch = AUX_CH_A;
1496                 break;
1497         case DP_AUX_B:
1498                 aux_ch = AUX_CH_B;
1499                 break;
1500         case DP_AUX_C:
1501                 aux_ch = AUX_CH_C;
1502                 break;
1503         case DP_AUX_D:
1504                 aux_ch = AUX_CH_D;
1505                 break;
1506         case DP_AUX_E:
1507                 aux_ch = AUX_CH_E;
1508                 break;
1509         case DP_AUX_F:
1510                 aux_ch = AUX_CH_F;
1511                 break;
1512         default:
1513                 MISSING_CASE(info->alternate_aux_channel);
1514                 aux_ch = AUX_CH_A;
1515                 break;
1516         }
1517
1518         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1519                       aux_ch_name(aux_ch), port_name(port));
1520
1521         return aux_ch;
1522 }
1523
1524 static enum intel_display_power_domain
1525 intel_aux_power_domain(struct intel_dp *intel_dp)
1526 {
1527         switch (intel_dp->aux_ch) {
1528         case AUX_CH_A:
1529                 return POWER_DOMAIN_AUX_A;
1530         case AUX_CH_B:
1531                 return POWER_DOMAIN_AUX_B;
1532         case AUX_CH_C:
1533                 return POWER_DOMAIN_AUX_C;
1534         case AUX_CH_D:
1535                 return POWER_DOMAIN_AUX_D;
1536         case AUX_CH_E:
1537                 return POWER_DOMAIN_AUX_E;
1538         case AUX_CH_F:
1539                 return POWER_DOMAIN_AUX_F;
1540         default:
1541                 MISSING_CASE(intel_dp->aux_ch);
1542                 return POWER_DOMAIN_AUX_A;
1543         }
1544 }
1545
1546 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1547 {
1548         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1549         enum aux_ch aux_ch = intel_dp->aux_ch;
1550
1551         switch (aux_ch) {
1552         case AUX_CH_B:
1553         case AUX_CH_C:
1554         case AUX_CH_D:
1555                 return DP_AUX_CH_CTL(aux_ch);
1556         default:
1557                 MISSING_CASE(aux_ch);
1558                 return DP_AUX_CH_CTL(AUX_CH_B);
1559         }
1560 }
1561
1562 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1563 {
1564         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1565         enum aux_ch aux_ch = intel_dp->aux_ch;
1566
1567         switch (aux_ch) {
1568         case AUX_CH_B:
1569         case AUX_CH_C:
1570         case AUX_CH_D:
1571                 return DP_AUX_CH_DATA(aux_ch, index);
1572         default:
1573                 MISSING_CASE(aux_ch);
1574                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1575         }
1576 }
1577
1578 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1579 {
1580         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1581         enum aux_ch aux_ch = intel_dp->aux_ch;
1582
1583         switch (aux_ch) {
1584         case AUX_CH_A:
1585                 return DP_AUX_CH_CTL(aux_ch);
1586         case AUX_CH_B:
1587         case AUX_CH_C:
1588         case AUX_CH_D:
1589                 return PCH_DP_AUX_CH_CTL(aux_ch);
1590         default:
1591                 MISSING_CASE(aux_ch);
1592                 return DP_AUX_CH_CTL(AUX_CH_A);
1593         }
1594 }
1595
1596 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1597 {
1598         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1599         enum aux_ch aux_ch = intel_dp->aux_ch;
1600
1601         switch (aux_ch) {
1602         case AUX_CH_A:
1603                 return DP_AUX_CH_DATA(aux_ch, index);
1604         case AUX_CH_B:
1605         case AUX_CH_C:
1606         case AUX_CH_D:
1607                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1608         default:
1609                 MISSING_CASE(aux_ch);
1610                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1611         }
1612 }
1613
1614 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1615 {
1616         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1617         enum aux_ch aux_ch = intel_dp->aux_ch;
1618
1619         switch (aux_ch) {
1620         case AUX_CH_A:
1621         case AUX_CH_B:
1622         case AUX_CH_C:
1623         case AUX_CH_D:
1624         case AUX_CH_E:
1625         case AUX_CH_F:
1626                 return DP_AUX_CH_CTL(aux_ch);
1627         default:
1628                 MISSING_CASE(aux_ch);
1629                 return DP_AUX_CH_CTL(AUX_CH_A);
1630         }
1631 }
1632
1633 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1634 {
1635         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1636         enum aux_ch aux_ch = intel_dp->aux_ch;
1637
1638         switch (aux_ch) {
1639         case AUX_CH_A:
1640         case AUX_CH_B:
1641         case AUX_CH_C:
1642         case AUX_CH_D:
1643         case AUX_CH_E:
1644         case AUX_CH_F:
1645                 return DP_AUX_CH_DATA(aux_ch, index);
1646         default:
1647                 MISSING_CASE(aux_ch);
1648                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1649         }
1650 }
1651
1652 static void
1653 intel_dp_aux_fini(struct intel_dp *intel_dp)
1654 {
1655         kfree(intel_dp->aux.name);
1656 }
1657
1658 static void
1659 intel_dp_aux_init(struct intel_dp *intel_dp)
1660 {
1661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1662         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1663
1664         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1665         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1666
1667         if (INTEL_GEN(dev_priv) >= 9) {
1668                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1669                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1670         } else if (HAS_PCH_SPLIT(dev_priv)) {
1671                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1672                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1673         } else {
1674                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1675                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1676         }
1677
1678         if (INTEL_GEN(dev_priv) >= 9)
1679                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1680         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1681                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1682         else if (HAS_PCH_SPLIT(dev_priv))
1683                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1684         else
1685                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1686
1687         if (INTEL_GEN(dev_priv) >= 9)
1688                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1689         else
1690                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1691
1692         drm_dp_aux_init(&intel_dp->aux);
1693
1694         /* Failure to allocate our preferred name is not critical */
1695         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1696                                        port_name(encoder->port));
1697         intel_dp->aux.transfer = intel_dp_aux_transfer;
1698 }
1699
1700 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1701 {
1702         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1703
1704         return max_rate >= 540000;
1705 }
1706
1707 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1708 {
1709         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1710
1711         return max_rate >= 810000;
1712 }
1713
1714 static void
1715 intel_dp_set_clock(struct intel_encoder *encoder,
1716                    struct intel_crtc_state *pipe_config)
1717 {
1718         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1719         const struct dp_link_dpll *divisor = NULL;
1720         int i, count = 0;
1721
1722         if (IS_G4X(dev_priv)) {
1723                 divisor = g4x_dpll;
1724                 count = ARRAY_SIZE(g4x_dpll);
1725         } else if (HAS_PCH_SPLIT(dev_priv)) {
1726                 divisor = pch_dpll;
1727                 count = ARRAY_SIZE(pch_dpll);
1728         } else if (IS_CHERRYVIEW(dev_priv)) {
1729                 divisor = chv_dpll;
1730                 count = ARRAY_SIZE(chv_dpll);
1731         } else if (IS_VALLEYVIEW(dev_priv)) {
1732                 divisor = vlv_dpll;
1733                 count = ARRAY_SIZE(vlv_dpll);
1734         }
1735
1736         if (divisor && count) {
1737                 for (i = 0; i < count; i++) {
1738                         if (pipe_config->port_clock == divisor[i].clock) {
1739                                 pipe_config->dpll = divisor[i].dpll;
1740                                 pipe_config->clock_set = true;
1741                                 break;
1742                         }
1743                 }
1744         }
1745 }
1746
1747 static void snprintf_int_array(char *str, size_t len,
1748                                const int *array, int nelem)
1749 {
1750         int i;
1751
1752         str[0] = '\0';
1753
1754         for (i = 0; i < nelem; i++) {
1755                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1756                 if (r >= len)
1757                         return;
1758                 str += r;
1759                 len -= r;
1760         }
1761 }
1762
1763 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1764 {
1765         char str[128]; /* FIXME: too big for stack? */
1766
1767         if ((drm_debug & DRM_UT_KMS) == 0)
1768                 return;
1769
1770         snprintf_int_array(str, sizeof(str),
1771                            intel_dp->source_rates, intel_dp->num_source_rates);
1772         DRM_DEBUG_KMS("source rates: %s\n", str);
1773
1774         snprintf_int_array(str, sizeof(str),
1775                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1776         DRM_DEBUG_KMS("sink rates: %s\n", str);
1777
1778         snprintf_int_array(str, sizeof(str),
1779                            intel_dp->common_rates, intel_dp->num_common_rates);
1780         DRM_DEBUG_KMS("common rates: %s\n", str);
1781 }
1782
1783 int
1784 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1785 {
1786         int len;
1787
1788         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1789         if (WARN_ON(len <= 0))
1790                 return 162000;
1791
1792         return intel_dp->common_rates[len - 1];
1793 }
1794
1795 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1796 {
1797         int i = intel_dp_rate_index(intel_dp->sink_rates,
1798                                     intel_dp->num_sink_rates, rate);
1799
1800         if (WARN_ON(i < 0))
1801                 i = 0;
1802
1803         return i;
1804 }
1805
1806 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1807                            uint8_t *link_bw, uint8_t *rate_select)
1808 {
1809         /* eDP 1.4 rate select method. */
1810         if (intel_dp->use_rate_select) {
1811                 *link_bw = 0;
1812                 *rate_select =
1813                         intel_dp_rate_select(intel_dp, port_clock);
1814         } else {
1815                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1816                 *rate_select = 0;
1817         }
1818 }
1819
1820 struct link_config_limits {
1821         int min_clock, max_clock;
1822         int min_lane_count, max_lane_count;
1823         int min_bpp, max_bpp;
1824 };
1825
1826 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1827                                 struct intel_crtc_state *pipe_config)
1828 {
1829         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1830         struct intel_connector *intel_connector = intel_dp->attached_connector;
1831         int bpp, bpc;
1832
1833         bpp = pipe_config->pipe_bpp;
1834         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1835
1836         if (bpc > 0)
1837                 bpp = min(bpp, 3*bpc);
1838
1839         if (intel_dp_is_edp(intel_dp)) {
1840                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1841                 if (intel_connector->base.display_info.bpc == 0 &&
1842                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1843                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1844                                       dev_priv->vbt.edp.bpp);
1845                         bpp = dev_priv->vbt.edp.bpp;
1846                 }
1847         }
1848
1849         return bpp;
1850 }
1851
1852 /* Adjust link config limits based on compliance test requests. */
1853 static void
1854 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1855                                   struct intel_crtc_state *pipe_config,
1856                                   struct link_config_limits *limits)
1857 {
1858         /* For DP Compliance we override the computed bpp for the pipe */
1859         if (intel_dp->compliance.test_data.bpc != 0) {
1860                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1861
1862                 limits->min_bpp = limits->max_bpp = bpp;
1863                 pipe_config->dither_force_disable = bpp == 6 * 3;
1864
1865                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1866         }
1867
1868         /* Use values requested by Compliance Test Request */
1869         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1870                 int index;
1871
1872                 /* Validate the compliance test data since max values
1873                  * might have changed due to link train fallback.
1874                  */
1875                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1876                                                intel_dp->compliance.test_lane_count)) {
1877                         index = intel_dp_rate_index(intel_dp->common_rates,
1878                                                     intel_dp->num_common_rates,
1879                                                     intel_dp->compliance.test_link_rate);
1880                         if (index >= 0)
1881                                 limits->min_clock = limits->max_clock = index;
1882                         limits->min_lane_count = limits->max_lane_count =
1883                                 intel_dp->compliance.test_lane_count;
1884                 }
1885         }
1886 }
1887
1888 /* Optimize link config in order: max bpp, min clock, min lanes */
1889 static bool
1890 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1891                                   struct intel_crtc_state *pipe_config,
1892                                   const struct link_config_limits *limits)
1893 {
1894         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1895         int bpp, clock, lane_count;
1896         int mode_rate, link_clock, link_avail;
1897
1898         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1899                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1900                                                    bpp);
1901
1902                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1903                         for (lane_count = limits->min_lane_count;
1904                              lane_count <= limits->max_lane_count;
1905                              lane_count <<= 1) {
1906                                 link_clock = intel_dp->common_rates[clock];
1907                                 link_avail = intel_dp_max_data_rate(link_clock,
1908                                                                     lane_count);
1909
1910                                 if (mode_rate <= link_avail) {
1911                                         pipe_config->lane_count = lane_count;
1912                                         pipe_config->pipe_bpp = bpp;
1913                                         pipe_config->port_clock = link_clock;
1914
1915                                         return true;
1916                                 }
1917                         }
1918                 }
1919         }
1920
1921         return false;
1922 }
1923
1924 /* Optimize link config in order: max bpp, min lanes, min clock */
1925 static bool
1926 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1927                                   struct intel_crtc_state *pipe_config,
1928                                   const struct link_config_limits *limits)
1929 {
1930         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1931         int bpp, clock, lane_count;
1932         int mode_rate, link_clock, link_avail;
1933
1934         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1935                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1936                                                    bpp);
1937
1938                 for (lane_count = limits->min_lane_count;
1939                      lane_count <= limits->max_lane_count;
1940                      lane_count <<= 1) {
1941                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1942                                 link_clock = intel_dp->common_rates[clock];
1943                                 link_avail = intel_dp_max_data_rate(link_clock,
1944                                                                     lane_count);
1945
1946                                 if (mode_rate <= link_avail) {
1947                                         pipe_config->lane_count = lane_count;
1948                                         pipe_config->pipe_bpp = bpp;
1949                                         pipe_config->port_clock = link_clock;
1950
1951                                         return true;
1952                                 }
1953                         }
1954                 }
1955         }
1956
1957         return false;
1958 }
1959
1960 static bool
1961 intel_dp_compute_link_config(struct intel_encoder *encoder,
1962                              struct intel_crtc_state *pipe_config)
1963 {
1964         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1965         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1966         struct link_config_limits limits;
1967         int common_len;
1968
1969         common_len = intel_dp_common_len_rate_limit(intel_dp,
1970                                                     intel_dp->max_link_rate);
1971
1972         /* No common link rates between source and sink */
1973         WARN_ON(common_len <= 0);
1974
1975         limits.min_clock = 0;
1976         limits.max_clock = common_len - 1;
1977
1978         limits.min_lane_count = 1;
1979         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1980
1981         limits.min_bpp = 6 * 3;
1982         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1983
1984         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
1985                 /*
1986                  * Use the maximum clock and number of lanes the eDP panel
1987                  * advertizes being capable of. The eDP 1.3 and earlier panels
1988                  * are generally designed to support only a single clock and
1989                  * lane configuration, and typically these values correspond to
1990                  * the native resolution of the panel. With eDP 1.4 rate select
1991                  * and DSC, this is decreasingly the case, and we need to be
1992                  * able to select less than maximum link config.
1993                  */
1994                 limits.min_lane_count = limits.max_lane_count;
1995                 limits.min_clock = limits.max_clock;
1996         }
1997
1998         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1999
2000         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2001                       "max rate %d max bpp %d pixel clock %iKHz\n",
2002                       limits.max_lane_count,
2003                       intel_dp->common_rates[limits.max_clock],
2004                       limits.max_bpp, adjusted_mode->crtc_clock);
2005
2006         if (intel_dp_is_edp(intel_dp)) {
2007                 /*
2008                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2009                  * section A.1: "It is recommended that the minimum number of
2010                  * lanes be used, using the minimum link rate allowed for that
2011                  * lane configuration."
2012                  *
2013                  * Note that we use the max clock and lane count for eDP 1.3 and
2014                  * earlier, and fast vs. wide is irrelevant.
2015                  */
2016                 if (!intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2017                                                        &limits))
2018                         return false;
2019         } else {
2020                 /* Optimize for slow and wide. */
2021                 if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2022                                                        &limits))
2023                         return false;
2024         }
2025
2026         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2027                       pipe_config->lane_count, pipe_config->port_clock,
2028                       pipe_config->pipe_bpp);
2029
2030         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2031                       intel_dp_link_required(adjusted_mode->crtc_clock,
2032                                              pipe_config->pipe_bpp),
2033                       intel_dp_max_data_rate(pipe_config->port_clock,
2034                                              pipe_config->lane_count));
2035
2036         return true;
2037 }
2038
2039 bool
2040 intel_dp_compute_config(struct intel_encoder *encoder,
2041                         struct intel_crtc_state *pipe_config,
2042                         struct drm_connector_state *conn_state)
2043 {
2044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2045         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2046         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2047         enum port port = encoder->port;
2048         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2049         struct intel_connector *intel_connector = intel_dp->attached_connector;
2050         struct intel_digital_connector_state *intel_conn_state =
2051                 to_intel_digital_connector_state(conn_state);
2052         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2053                                            DP_DPCD_QUIRK_CONSTANT_N);
2054
2055         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2056                 pipe_config->has_pch_encoder = true;
2057
2058         pipe_config->has_drrs = false;
2059         if (IS_G4X(dev_priv) || port == PORT_A)
2060                 pipe_config->has_audio = false;
2061         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2062                 pipe_config->has_audio = intel_dp->has_audio;
2063         else
2064                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2065
2066         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2067                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2068                                        adjusted_mode);
2069
2070                 if (INTEL_GEN(dev_priv) >= 9) {
2071                         int ret;
2072
2073                         ret = skl_update_scaler_crtc(pipe_config);
2074                         if (ret)
2075                                 return ret;
2076                 }
2077
2078                 if (HAS_GMCH_DISPLAY(dev_priv))
2079                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2080                                                  conn_state->scaling_mode);
2081                 else
2082                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2083                                                 conn_state->scaling_mode);
2084         }
2085
2086         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2087                 return false;
2088
2089         if (HAS_GMCH_DISPLAY(dev_priv) &&
2090             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2091                 return false;
2092
2093         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2094                 return false;
2095
2096         if (!intel_dp_compute_link_config(encoder, pipe_config))
2097                 return false;
2098
2099         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2100                 /*
2101                  * See:
2102                  * CEA-861-E - 5.1 Default Encoding Parameters
2103                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2104                  */
2105                 pipe_config->limited_color_range =
2106                         pipe_config->pipe_bpp != 18 &&
2107                         drm_default_rgb_quant_range(adjusted_mode) ==
2108                         HDMI_QUANTIZATION_RANGE_LIMITED;
2109         } else {
2110                 pipe_config->limited_color_range =
2111                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2112         }
2113
2114         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
2115                                adjusted_mode->crtc_clock,
2116                                pipe_config->port_clock,
2117                                &pipe_config->dp_m_n,
2118                                constant_n);
2119
2120         if (intel_connector->panel.downclock_mode != NULL &&
2121                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2122                         pipe_config->has_drrs = true;
2123                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2124                                                pipe_config->lane_count,
2125                                                intel_connector->panel.downclock_mode->clock,
2126                                                pipe_config->port_clock,
2127                                                &pipe_config->dp_m2_n2,
2128                                                constant_n);
2129         }
2130
2131         if (!HAS_DDI(dev_priv))
2132                 intel_dp_set_clock(encoder, pipe_config);
2133
2134         intel_psr_compute_config(intel_dp, pipe_config);
2135
2136         return true;
2137 }
2138
2139 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2140                               int link_rate, uint8_t lane_count,
2141                               bool link_mst)
2142 {
2143         intel_dp->link_trained = false;
2144         intel_dp->link_rate = link_rate;
2145         intel_dp->lane_count = lane_count;
2146         intel_dp->link_mst = link_mst;
2147 }
2148
2149 static void intel_dp_prepare(struct intel_encoder *encoder,
2150                              const struct intel_crtc_state *pipe_config)
2151 {
2152         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2153         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2154         enum port port = encoder->port;
2155         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2156         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2157
2158         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2159                                  pipe_config->lane_count,
2160                                  intel_crtc_has_type(pipe_config,
2161                                                      INTEL_OUTPUT_DP_MST));
2162
2163         /*
2164          * There are four kinds of DP registers:
2165          *
2166          *      IBX PCH
2167          *      SNB CPU
2168          *      IVB CPU
2169          *      CPT PCH
2170          *
2171          * IBX PCH and CPU are the same for almost everything,
2172          * except that the CPU DP PLL is configured in this
2173          * register
2174          *
2175          * CPT PCH is quite different, having many bits moved
2176          * to the TRANS_DP_CTL register instead. That
2177          * configuration happens (oddly) in ironlake_pch_enable
2178          */
2179
2180         /* Preserve the BIOS-computed detected bit. This is
2181          * supposed to be read-only.
2182          */
2183         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2184
2185         /* Handle DP bits in common between all three register formats */
2186         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2187         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2188
2189         /* Split out the IBX/CPU vs CPT settings */
2190
2191         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2192                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2193                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2194                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2195                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2196                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2197
2198                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2199                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2200
2201                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2202         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2203                 u32 trans_dp;
2204
2205                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2206
2207                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2208                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2209                         trans_dp |= TRANS_DP_ENH_FRAMING;
2210                 else
2211                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2212                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2213         } else {
2214                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2215                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2216
2217                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2218                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2219                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2220                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2221                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2222
2223                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2224                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2225
2226                 if (IS_CHERRYVIEW(dev_priv))
2227                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2228                 else
2229                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2230         }
2231 }
2232
2233 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2234 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2235
2236 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2237 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2238
2239 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2240 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2241
2242 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2243
2244 static void wait_panel_status(struct intel_dp *intel_dp,
2245                                        u32 mask,
2246                                        u32 value)
2247 {
2248         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2249         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2250
2251         lockdep_assert_held(&dev_priv->pps_mutex);
2252
2253         intel_pps_verify_state(intel_dp);
2254
2255         pp_stat_reg = _pp_stat_reg(intel_dp);
2256         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2257
2258         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2259                         mask, value,
2260                         I915_READ(pp_stat_reg),
2261                         I915_READ(pp_ctrl_reg));
2262
2263         if (intel_wait_for_register(dev_priv,
2264                                     pp_stat_reg, mask, value,
2265                                     5000))
2266                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2267                                 I915_READ(pp_stat_reg),
2268                                 I915_READ(pp_ctrl_reg));
2269
2270         DRM_DEBUG_KMS("Wait complete\n");
2271 }
2272
2273 static void wait_panel_on(struct intel_dp *intel_dp)
2274 {
2275         DRM_DEBUG_KMS("Wait for panel power on\n");
2276         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2277 }
2278
2279 static void wait_panel_off(struct intel_dp *intel_dp)
2280 {
2281         DRM_DEBUG_KMS("Wait for panel power off time\n");
2282         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2283 }
2284
2285 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2286 {
2287         ktime_t panel_power_on_time;
2288         s64 panel_power_off_duration;
2289
2290         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2291
2292         /* take the difference of currrent time and panel power off time
2293          * and then make panel wait for t11_t12 if needed. */
2294         panel_power_on_time = ktime_get_boottime();
2295         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2296
2297         /* When we disable the VDD override bit last we have to do the manual
2298          * wait. */
2299         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2300                 wait_remaining_ms_from_jiffies(jiffies,
2301                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2302
2303         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2304 }
2305
2306 static void wait_backlight_on(struct intel_dp *intel_dp)
2307 {
2308         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2309                                        intel_dp->backlight_on_delay);
2310 }
2311
2312 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2313 {
2314         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2315                                        intel_dp->backlight_off_delay);
2316 }
2317
2318 /* Read the current pp_control value, unlocking the register if it
2319  * is locked
2320  */
2321
2322 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2323 {
2324         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2325         u32 control;
2326
2327         lockdep_assert_held(&dev_priv->pps_mutex);
2328
2329         control = I915_READ(_pp_ctrl_reg(intel_dp));
2330         if (WARN_ON(!HAS_DDI(dev_priv) &&
2331                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2332                 control &= ~PANEL_UNLOCK_MASK;
2333                 control |= PANEL_UNLOCK_REGS;
2334         }
2335         return control;
2336 }
2337
2338 /*
2339  * Must be paired with edp_panel_vdd_off().
2340  * Must hold pps_mutex around the whole on/off sequence.
2341  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2342  */
2343 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2344 {
2345         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2346         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2347         u32 pp;
2348         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2349         bool need_to_disable = !intel_dp->want_panel_vdd;
2350
2351         lockdep_assert_held(&dev_priv->pps_mutex);
2352
2353         if (!intel_dp_is_edp(intel_dp))
2354                 return false;
2355
2356         cancel_delayed_work(&intel_dp->panel_vdd_work);
2357         intel_dp->want_panel_vdd = true;
2358
2359         if (edp_have_panel_vdd(intel_dp))
2360                 return need_to_disable;
2361
2362         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2363
2364         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2365                       port_name(intel_dig_port->base.port));
2366
2367         if (!edp_have_panel_power(intel_dp))
2368                 wait_panel_power_cycle(intel_dp);
2369
2370         pp = ironlake_get_pp_control(intel_dp);
2371         pp |= EDP_FORCE_VDD;
2372
2373         pp_stat_reg = _pp_stat_reg(intel_dp);
2374         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2375
2376         I915_WRITE(pp_ctrl_reg, pp);
2377         POSTING_READ(pp_ctrl_reg);
2378         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2379                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2380         /*
2381          * If the panel wasn't on, delay before accessing aux channel
2382          */
2383         if (!edp_have_panel_power(intel_dp)) {
2384                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2385                               port_name(intel_dig_port->base.port));
2386                 msleep(intel_dp->panel_power_up_delay);
2387         }
2388
2389         return need_to_disable;
2390 }
2391
2392 /*
2393  * Must be paired with intel_edp_panel_vdd_off() or
2394  * intel_edp_panel_off().
2395  * Nested calls to these functions are not allowed since
2396  * we drop the lock. Caller must use some higher level
2397  * locking to prevent nested calls from other threads.
2398  */
2399 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2400 {
2401         bool vdd;
2402
2403         if (!intel_dp_is_edp(intel_dp))
2404                 return;
2405
2406         pps_lock(intel_dp);
2407         vdd = edp_panel_vdd_on(intel_dp);
2408         pps_unlock(intel_dp);
2409
2410         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2411              port_name(dp_to_dig_port(intel_dp)->base.port));
2412 }
2413
2414 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2415 {
2416         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2417         struct intel_digital_port *intel_dig_port =
2418                 dp_to_dig_port(intel_dp);
2419         u32 pp;
2420         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2421
2422         lockdep_assert_held(&dev_priv->pps_mutex);
2423
2424         WARN_ON(intel_dp->want_panel_vdd);
2425
2426         if (!edp_have_panel_vdd(intel_dp))
2427                 return;
2428
2429         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2430                       port_name(intel_dig_port->base.port));
2431
2432         pp = ironlake_get_pp_control(intel_dp);
2433         pp &= ~EDP_FORCE_VDD;
2434
2435         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2436         pp_stat_reg = _pp_stat_reg(intel_dp);
2437
2438         I915_WRITE(pp_ctrl_reg, pp);
2439         POSTING_READ(pp_ctrl_reg);
2440
2441         /* Make sure sequencer is idle before allowing subsequent activity */
2442         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2443         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2444
2445         if ((pp & PANEL_POWER_ON) == 0)
2446                 intel_dp->panel_power_off_time = ktime_get_boottime();
2447
2448         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2449 }
2450
2451 static void edp_panel_vdd_work(struct work_struct *__work)
2452 {
2453         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2454                                                  struct intel_dp, panel_vdd_work);
2455
2456         pps_lock(intel_dp);
2457         if (!intel_dp->want_panel_vdd)
2458                 edp_panel_vdd_off_sync(intel_dp);
2459         pps_unlock(intel_dp);
2460 }
2461
2462 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2463 {
2464         unsigned long delay;
2465
2466         /*
2467          * Queue the timer to fire a long time from now (relative to the power
2468          * down delay) to keep the panel power up across a sequence of
2469          * operations.
2470          */
2471         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2472         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2473 }
2474
2475 /*
2476  * Must be paired with edp_panel_vdd_on().
2477  * Must hold pps_mutex around the whole on/off sequence.
2478  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2479  */
2480 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2481 {
2482         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2483
2484         lockdep_assert_held(&dev_priv->pps_mutex);
2485
2486         if (!intel_dp_is_edp(intel_dp))
2487                 return;
2488
2489         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2490              port_name(dp_to_dig_port(intel_dp)->base.port));
2491
2492         intel_dp->want_panel_vdd = false;
2493
2494         if (sync)
2495                 edp_panel_vdd_off_sync(intel_dp);
2496         else
2497                 edp_panel_vdd_schedule_off(intel_dp);
2498 }
2499
2500 static void edp_panel_on(struct intel_dp *intel_dp)
2501 {
2502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2503         u32 pp;
2504         i915_reg_t pp_ctrl_reg;
2505
2506         lockdep_assert_held(&dev_priv->pps_mutex);
2507
2508         if (!intel_dp_is_edp(intel_dp))
2509                 return;
2510
2511         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2512                       port_name(dp_to_dig_port(intel_dp)->base.port));
2513
2514         if (WARN(edp_have_panel_power(intel_dp),
2515                  "eDP port %c panel power already on\n",
2516                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2517                 return;
2518
2519         wait_panel_power_cycle(intel_dp);
2520
2521         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2522         pp = ironlake_get_pp_control(intel_dp);
2523         if (IS_GEN5(dev_priv)) {
2524                 /* ILK workaround: disable reset around power sequence */
2525                 pp &= ~PANEL_POWER_RESET;
2526                 I915_WRITE(pp_ctrl_reg, pp);
2527                 POSTING_READ(pp_ctrl_reg);
2528         }
2529
2530         pp |= PANEL_POWER_ON;
2531         if (!IS_GEN5(dev_priv))
2532                 pp |= PANEL_POWER_RESET;
2533
2534         I915_WRITE(pp_ctrl_reg, pp);
2535         POSTING_READ(pp_ctrl_reg);
2536
2537         wait_panel_on(intel_dp);
2538         intel_dp->last_power_on = jiffies;
2539
2540         if (IS_GEN5(dev_priv)) {
2541                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2542                 I915_WRITE(pp_ctrl_reg, pp);
2543                 POSTING_READ(pp_ctrl_reg);
2544         }
2545 }
2546
2547 void intel_edp_panel_on(struct intel_dp *intel_dp)
2548 {
2549         if (!intel_dp_is_edp(intel_dp))
2550                 return;
2551
2552         pps_lock(intel_dp);
2553         edp_panel_on(intel_dp);
2554         pps_unlock(intel_dp);
2555 }
2556
2557
2558 static void edp_panel_off(struct intel_dp *intel_dp)
2559 {
2560         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2561         u32 pp;
2562         i915_reg_t pp_ctrl_reg;
2563
2564         lockdep_assert_held(&dev_priv->pps_mutex);
2565
2566         if (!intel_dp_is_edp(intel_dp))
2567                 return;
2568
2569         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2570                       port_name(dp_to_dig_port(intel_dp)->base.port));
2571
2572         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2573              port_name(dp_to_dig_port(intel_dp)->base.port));
2574
2575         pp = ironlake_get_pp_control(intel_dp);
2576         /* We need to switch off panel power _and_ force vdd, for otherwise some
2577          * panels get very unhappy and cease to work. */
2578         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2579                 EDP_BLC_ENABLE);
2580
2581         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2582
2583         intel_dp->want_panel_vdd = false;
2584
2585         I915_WRITE(pp_ctrl_reg, pp);
2586         POSTING_READ(pp_ctrl_reg);
2587
2588         wait_panel_off(intel_dp);
2589         intel_dp->panel_power_off_time = ktime_get_boottime();
2590
2591         /* We got a reference when we enabled the VDD. */
2592         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2593 }
2594
2595 void intel_edp_panel_off(struct intel_dp *intel_dp)
2596 {
2597         if (!intel_dp_is_edp(intel_dp))
2598                 return;
2599
2600         pps_lock(intel_dp);
2601         edp_panel_off(intel_dp);
2602         pps_unlock(intel_dp);
2603 }
2604
2605 /* Enable backlight in the panel power control. */
2606 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2607 {
2608         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2609         u32 pp;
2610         i915_reg_t pp_ctrl_reg;
2611
2612         /*
2613          * If we enable the backlight right away following a panel power
2614          * on, we may see slight flicker as the panel syncs with the eDP
2615          * link.  So delay a bit to make sure the image is solid before
2616          * allowing it to appear.
2617          */
2618         wait_backlight_on(intel_dp);
2619
2620         pps_lock(intel_dp);
2621
2622         pp = ironlake_get_pp_control(intel_dp);
2623         pp |= EDP_BLC_ENABLE;
2624
2625         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2626
2627         I915_WRITE(pp_ctrl_reg, pp);
2628         POSTING_READ(pp_ctrl_reg);
2629
2630         pps_unlock(intel_dp);
2631 }
2632
2633 /* Enable backlight PWM and backlight PP control. */
2634 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2635                             const struct drm_connector_state *conn_state)
2636 {
2637         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2638
2639         if (!intel_dp_is_edp(intel_dp))
2640                 return;
2641
2642         DRM_DEBUG_KMS("\n");
2643
2644         intel_panel_enable_backlight(crtc_state, conn_state);
2645         _intel_edp_backlight_on(intel_dp);
2646 }
2647
2648 /* Disable backlight in the panel power control. */
2649 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2650 {
2651         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2652         u32 pp;
2653         i915_reg_t pp_ctrl_reg;
2654
2655         if (!intel_dp_is_edp(intel_dp))
2656                 return;
2657
2658         pps_lock(intel_dp);
2659
2660         pp = ironlake_get_pp_control(intel_dp);
2661         pp &= ~EDP_BLC_ENABLE;
2662
2663         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2664
2665         I915_WRITE(pp_ctrl_reg, pp);
2666         POSTING_READ(pp_ctrl_reg);
2667
2668         pps_unlock(intel_dp);
2669
2670         intel_dp->last_backlight_off = jiffies;
2671         edp_wait_backlight_off(intel_dp);
2672 }
2673
2674 /* Disable backlight PP control and backlight PWM. */
2675 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2676 {
2677         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2678
2679         if (!intel_dp_is_edp(intel_dp))
2680                 return;
2681
2682         DRM_DEBUG_KMS("\n");
2683
2684         _intel_edp_backlight_off(intel_dp);
2685         intel_panel_disable_backlight(old_conn_state);
2686 }
2687
2688 /*
2689  * Hook for controlling the panel power control backlight through the bl_power
2690  * sysfs attribute. Take care to handle multiple calls.
2691  */
2692 static void intel_edp_backlight_power(struct intel_connector *connector,
2693                                       bool enable)
2694 {
2695         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2696         bool is_enabled;
2697
2698         pps_lock(intel_dp);
2699         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2700         pps_unlock(intel_dp);
2701
2702         if (is_enabled == enable)
2703                 return;
2704
2705         DRM_DEBUG_KMS("panel power control backlight %s\n",
2706                       enable ? "enable" : "disable");
2707
2708         if (enable)
2709                 _intel_edp_backlight_on(intel_dp);
2710         else
2711                 _intel_edp_backlight_off(intel_dp);
2712 }
2713
2714 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2715 {
2716         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2717         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2718         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2719
2720         I915_STATE_WARN(cur_state != state,
2721                         "DP port %c state assertion failure (expected %s, current %s)\n",
2722                         port_name(dig_port->base.port),
2723                         onoff(state), onoff(cur_state));
2724 }
2725 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2726
2727 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2728 {
2729         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2730
2731         I915_STATE_WARN(cur_state != state,
2732                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2733                         onoff(state), onoff(cur_state));
2734 }
2735 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2736 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2737
2738 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2739                                 const struct intel_crtc_state *pipe_config)
2740 {
2741         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2743
2744         assert_pipe_disabled(dev_priv, crtc->pipe);
2745         assert_dp_port_disabled(intel_dp);
2746         assert_edp_pll_disabled(dev_priv);
2747
2748         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2749                       pipe_config->port_clock);
2750
2751         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2752
2753         if (pipe_config->port_clock == 162000)
2754                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2755         else
2756                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2757
2758         I915_WRITE(DP_A, intel_dp->DP);
2759         POSTING_READ(DP_A);
2760         udelay(500);
2761
2762         /*
2763          * [DevILK] Work around required when enabling DP PLL
2764          * while a pipe is enabled going to FDI:
2765          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2766          * 2. Program DP PLL enable
2767          */
2768         if (IS_GEN5(dev_priv))
2769                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2770
2771         intel_dp->DP |= DP_PLL_ENABLE;
2772
2773         I915_WRITE(DP_A, intel_dp->DP);
2774         POSTING_READ(DP_A);
2775         udelay(200);
2776 }
2777
2778 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2779                                  const struct intel_crtc_state *old_crtc_state)
2780 {
2781         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2782         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2783
2784         assert_pipe_disabled(dev_priv, crtc->pipe);
2785         assert_dp_port_disabled(intel_dp);
2786         assert_edp_pll_enabled(dev_priv);
2787
2788         DRM_DEBUG_KMS("disabling eDP PLL\n");
2789
2790         intel_dp->DP &= ~DP_PLL_ENABLE;
2791
2792         I915_WRITE(DP_A, intel_dp->DP);
2793         POSTING_READ(DP_A);
2794         udelay(200);
2795 }
2796
2797 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2798 {
2799         /*
2800          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2801          * be capable of signalling downstream hpd with a long pulse.
2802          * Whether or not that means D3 is safe to use is not clear,
2803          * but let's assume so until proven otherwise.
2804          *
2805          * FIXME should really check all downstream ports...
2806          */
2807         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2808                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2809                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2810 }
2811
2812 /* If the sink supports it, try to set the power state appropriately */
2813 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2814 {
2815         int ret, i;
2816
2817         /* Should have a valid DPCD by this point */
2818         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2819                 return;
2820
2821         if (mode != DRM_MODE_DPMS_ON) {
2822                 if (downstream_hpd_needs_d0(intel_dp))
2823                         return;
2824
2825                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2826                                          DP_SET_POWER_D3);
2827         } else {
2828                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2829
2830                 /*
2831                  * When turning on, we need to retry for 1ms to give the sink
2832                  * time to wake up.
2833                  */
2834                 for (i = 0; i < 3; i++) {
2835                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2836                                                  DP_SET_POWER_D0);
2837                         if (ret == 1)
2838                                 break;
2839                         msleep(1);
2840                 }
2841
2842                 if (ret == 1 && lspcon->active)
2843                         lspcon_wait_pcon_mode(lspcon);
2844         }
2845
2846         if (ret != 1)
2847                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2848                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2849 }
2850
2851 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2852                                  enum port port, enum pipe *pipe)
2853 {
2854         enum pipe p;
2855
2856         for_each_pipe(dev_priv, p) {
2857                 u32 val = I915_READ(TRANS_DP_CTL(p));
2858
2859                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2860                         *pipe = p;
2861                         return true;
2862                 }
2863         }
2864
2865         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2866
2867         /* must initialize pipe to something for the asserts */
2868         *pipe = PIPE_A;
2869
2870         return false;
2871 }
2872
2873 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2874                            i915_reg_t dp_reg, enum port port,
2875                            enum pipe *pipe)
2876 {
2877         bool ret;
2878         u32 val;
2879
2880         val = I915_READ(dp_reg);
2881
2882         ret = val & DP_PORT_EN;
2883
2884         /* asserts want to know the pipe even if the port is disabled */
2885         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2886                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2887         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2888                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2889         else if (IS_CHERRYVIEW(dev_priv))
2890                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2891         else
2892                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2893
2894         return ret;
2895 }
2896
2897 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2898                                   enum pipe *pipe)
2899 {
2900         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2901         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2902         bool ret;
2903
2904         if (!intel_display_power_get_if_enabled(dev_priv,
2905                                                 encoder->power_domain))
2906                 return false;
2907
2908         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2909                                     encoder->port, pipe);
2910
2911         intel_display_power_put(dev_priv, encoder->power_domain);
2912
2913         return ret;
2914 }
2915
2916 static void intel_dp_get_config(struct intel_encoder *encoder,
2917                                 struct intel_crtc_state *pipe_config)
2918 {
2919         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2920         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2921         u32 tmp, flags = 0;
2922         enum port port = encoder->port;
2923         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2924
2925         if (encoder->type == INTEL_OUTPUT_EDP)
2926                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2927         else
2928                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2929
2930         tmp = I915_READ(intel_dp->output_reg);
2931
2932         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2933
2934         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2935                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2936
2937                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2938                         flags |= DRM_MODE_FLAG_PHSYNC;
2939                 else
2940                         flags |= DRM_MODE_FLAG_NHSYNC;
2941
2942                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2943                         flags |= DRM_MODE_FLAG_PVSYNC;
2944                 else
2945                         flags |= DRM_MODE_FLAG_NVSYNC;
2946         } else {
2947                 if (tmp & DP_SYNC_HS_HIGH)
2948                         flags |= DRM_MODE_FLAG_PHSYNC;
2949                 else
2950                         flags |= DRM_MODE_FLAG_NHSYNC;
2951
2952                 if (tmp & DP_SYNC_VS_HIGH)
2953                         flags |= DRM_MODE_FLAG_PVSYNC;
2954                 else
2955                         flags |= DRM_MODE_FLAG_NVSYNC;
2956         }
2957
2958         pipe_config->base.adjusted_mode.flags |= flags;
2959
2960         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2961                 pipe_config->limited_color_range = true;
2962
2963         pipe_config->lane_count =
2964                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2965
2966         intel_dp_get_m_n(crtc, pipe_config);
2967
2968         if (port == PORT_A) {
2969                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2970                         pipe_config->port_clock = 162000;
2971                 else
2972                         pipe_config->port_clock = 270000;
2973         }
2974
2975         pipe_config->base.adjusted_mode.crtc_clock =
2976                 intel_dotclock_calculate(pipe_config->port_clock,
2977                                          &pipe_config->dp_m_n);
2978
2979         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2980             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2981                 /*
2982                  * This is a big fat ugly hack.
2983                  *
2984                  * Some machines in UEFI boot mode provide us a VBT that has 18
2985                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2986                  * unknown we fail to light up. Yet the same BIOS boots up with
2987                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2988                  * max, not what it tells us to use.
2989                  *
2990                  * Note: This will still be broken if the eDP panel is not lit
2991                  * up by the BIOS, and thus we can't get the mode at module
2992                  * load.
2993                  */
2994                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2995                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2996                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2997         }
2998 }
2999
3000 static void intel_disable_dp(struct intel_encoder *encoder,
3001                              const struct intel_crtc_state *old_crtc_state,
3002                              const struct drm_connector_state *old_conn_state)
3003 {
3004         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3005
3006         intel_dp->link_trained = false;
3007
3008         if (old_crtc_state->has_audio)
3009                 intel_audio_codec_disable(encoder,
3010                                           old_crtc_state, old_conn_state);
3011
3012         /* Make sure the panel is off before trying to change the mode. But also
3013          * ensure that we have vdd while we switch off the panel. */
3014         intel_edp_panel_vdd_on(intel_dp);
3015         intel_edp_backlight_off(old_conn_state);
3016         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3017         intel_edp_panel_off(intel_dp);
3018 }
3019
3020 static void g4x_disable_dp(struct intel_encoder *encoder,
3021                            const struct intel_crtc_state *old_crtc_state,
3022                            const struct drm_connector_state *old_conn_state)
3023 {
3024         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3025 }
3026
3027 static void vlv_disable_dp(struct intel_encoder *encoder,
3028                            const struct intel_crtc_state *old_crtc_state,
3029                            const struct drm_connector_state *old_conn_state)
3030 {
3031         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3032 }
3033
3034 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3035                                 const struct intel_crtc_state *old_crtc_state,
3036                                 const struct drm_connector_state *old_conn_state)
3037 {
3038         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3039         enum port port = encoder->port;
3040
3041         /*
3042          * Bspec does not list a specific disable sequence for g4x DP.
3043          * Follow the ilk+ sequence (disable pipe before the port) for
3044          * g4x DP as it does not suffer from underruns like the normal
3045          * g4x modeset sequence (disable pipe after the port).
3046          */
3047         intel_dp_link_down(encoder, old_crtc_state);
3048
3049         /* Only ilk+ has port A */
3050         if (port == PORT_A)
3051                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3052 }
3053
3054 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3055                                 const struct intel_crtc_state *old_crtc_state,
3056                                 const struct drm_connector_state *old_conn_state)
3057 {
3058         intel_dp_link_down(encoder, old_crtc_state);
3059 }
3060
3061 static void chv_post_disable_dp(struct intel_encoder *encoder,
3062                                 const struct intel_crtc_state *old_crtc_state,
3063                                 const struct drm_connector_state *old_conn_state)
3064 {
3065         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3066
3067         intel_dp_link_down(encoder, old_crtc_state);
3068
3069         mutex_lock(&dev_priv->sb_lock);
3070
3071         /* Assert data lane reset */
3072         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3073
3074         mutex_unlock(&dev_priv->sb_lock);
3075 }
3076
3077 static void
3078 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3079                          uint32_t *DP,
3080                          uint8_t dp_train_pat)
3081 {
3082         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3083         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3084         enum port port = intel_dig_port->base.port;
3085         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3086
3087         if (dp_train_pat & train_pat_mask)
3088                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3089                               dp_train_pat & train_pat_mask);
3090
3091         if (HAS_DDI(dev_priv)) {
3092                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3093
3094                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3095                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3096                 else
3097                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3098
3099                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3100                 switch (dp_train_pat & train_pat_mask) {
3101                 case DP_TRAINING_PATTERN_DISABLE:
3102                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3103
3104                         break;
3105                 case DP_TRAINING_PATTERN_1:
3106                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3107                         break;
3108                 case DP_TRAINING_PATTERN_2:
3109                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3110                         break;
3111                 case DP_TRAINING_PATTERN_3:
3112                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3113                         break;
3114                 case DP_TRAINING_PATTERN_4:
3115                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3116                         break;
3117                 }
3118                 I915_WRITE(DP_TP_CTL(port), temp);
3119
3120         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3121                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3122                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3123
3124                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3125                 case DP_TRAINING_PATTERN_DISABLE:
3126                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3127                         break;
3128                 case DP_TRAINING_PATTERN_1:
3129                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3130                         break;
3131                 case DP_TRAINING_PATTERN_2:
3132                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3133                         break;
3134                 case DP_TRAINING_PATTERN_3:
3135                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3136                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3137                         break;
3138                 }
3139
3140         } else {
3141                 *DP &= ~DP_LINK_TRAIN_MASK;
3142
3143                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3144                 case DP_TRAINING_PATTERN_DISABLE:
3145                         *DP |= DP_LINK_TRAIN_OFF;
3146                         break;
3147                 case DP_TRAINING_PATTERN_1:
3148                         *DP |= DP_LINK_TRAIN_PAT_1;
3149                         break;
3150                 case DP_TRAINING_PATTERN_2:
3151                         *DP |= DP_LINK_TRAIN_PAT_2;
3152                         break;
3153                 case DP_TRAINING_PATTERN_3:
3154                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3155                         *DP |= DP_LINK_TRAIN_PAT_2;
3156                         break;
3157                 }
3158         }
3159 }
3160
3161 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3162                                  const struct intel_crtc_state *old_crtc_state)
3163 {
3164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3165
3166         /* enable with pattern 1 (as per spec) */
3167
3168         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3169
3170         /*
3171          * Magic for VLV/CHV. We _must_ first set up the register
3172          * without actually enabling the port, and then do another
3173          * write to enable the port. Otherwise link training will
3174          * fail when the power sequencer is freshly used for this port.
3175          */
3176         intel_dp->DP |= DP_PORT_EN;
3177         if (old_crtc_state->has_audio)
3178                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3179
3180         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3181         POSTING_READ(intel_dp->output_reg);
3182 }
3183
3184 static void intel_enable_dp(struct intel_encoder *encoder,
3185                             const struct intel_crtc_state *pipe_config,
3186                             const struct drm_connector_state *conn_state)
3187 {
3188         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3189         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3190         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3191         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3192         enum pipe pipe = crtc->pipe;
3193
3194         if (WARN_ON(dp_reg & DP_PORT_EN))
3195                 return;
3196
3197         pps_lock(intel_dp);
3198
3199         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3200                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3201
3202         intel_dp_enable_port(intel_dp, pipe_config);
3203
3204         edp_panel_vdd_on(intel_dp);
3205         edp_panel_on(intel_dp);
3206         edp_panel_vdd_off(intel_dp, true);
3207
3208         pps_unlock(intel_dp);
3209
3210         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3211                 unsigned int lane_mask = 0x0;
3212
3213                 if (IS_CHERRYVIEW(dev_priv))
3214                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3215
3216                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3217                                     lane_mask);
3218         }
3219
3220         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3221         intel_dp_start_link_train(intel_dp);
3222         intel_dp_stop_link_train(intel_dp);
3223
3224         if (pipe_config->has_audio) {
3225                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3226                                  pipe_name(pipe));
3227                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3228         }
3229 }
3230
3231 static void g4x_enable_dp(struct intel_encoder *encoder,
3232                           const struct intel_crtc_state *pipe_config,
3233                           const struct drm_connector_state *conn_state)
3234 {
3235         intel_enable_dp(encoder, pipe_config, conn_state);
3236         intel_edp_backlight_on(pipe_config, conn_state);
3237 }
3238
3239 static void vlv_enable_dp(struct intel_encoder *encoder,
3240                           const struct intel_crtc_state *pipe_config,
3241                           const struct drm_connector_state *conn_state)
3242 {
3243         intel_edp_backlight_on(pipe_config, conn_state);
3244 }
3245
3246 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3247                               const struct intel_crtc_state *pipe_config,
3248                               const struct drm_connector_state *conn_state)
3249 {
3250         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3251         enum port port = encoder->port;
3252
3253         intel_dp_prepare(encoder, pipe_config);
3254
3255         /* Only ilk+ has port A */
3256         if (port == PORT_A)
3257                 ironlake_edp_pll_on(intel_dp, pipe_config);
3258 }
3259
3260 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3261 {
3262         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3263         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3264         enum pipe pipe = intel_dp->pps_pipe;
3265         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3266
3267         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3268
3269         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3270                 return;
3271
3272         edp_panel_vdd_off_sync(intel_dp);
3273
3274         /*
3275          * VLV seems to get confused when multiple power sequencers
3276          * have the same port selected (even if only one has power/vdd
3277          * enabled). The failure manifests as vlv_wait_port_ready() failing
3278          * CHV on the other hand doesn't seem to mind having the same port
3279          * selected in multiple power sequencers, but let's clear the
3280          * port select always when logically disconnecting a power sequencer
3281          * from a port.
3282          */
3283         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3284                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3285         I915_WRITE(pp_on_reg, 0);
3286         POSTING_READ(pp_on_reg);
3287
3288         intel_dp->pps_pipe = INVALID_PIPE;
3289 }
3290
3291 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3292                                       enum pipe pipe)
3293 {
3294         struct intel_encoder *encoder;
3295
3296         lockdep_assert_held(&dev_priv->pps_mutex);
3297
3298         for_each_intel_dp(&dev_priv->drm, encoder) {
3299                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3300                 enum port port = encoder->port;
3301
3302                 WARN(intel_dp->active_pipe == pipe,
3303                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3304                      pipe_name(pipe), port_name(port));
3305
3306                 if (intel_dp->pps_pipe != pipe)
3307                         continue;
3308
3309                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3310                               pipe_name(pipe), port_name(port));
3311
3312                 /* make sure vdd is off before we steal it */
3313                 vlv_detach_power_sequencer(intel_dp);
3314         }
3315 }
3316
3317 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3318                                            const struct intel_crtc_state *crtc_state)
3319 {
3320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3321         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3322         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3323
3324         lockdep_assert_held(&dev_priv->pps_mutex);
3325
3326         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3327
3328         if (intel_dp->pps_pipe != INVALID_PIPE &&
3329             intel_dp->pps_pipe != crtc->pipe) {
3330                 /*
3331                  * If another power sequencer was being used on this
3332                  * port previously make sure to turn off vdd there while
3333                  * we still have control of it.
3334                  */
3335                 vlv_detach_power_sequencer(intel_dp);
3336         }
3337
3338         /*
3339          * We may be stealing the power
3340          * sequencer from another port.
3341          */
3342         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3343
3344         intel_dp->active_pipe = crtc->pipe;
3345
3346         if (!intel_dp_is_edp(intel_dp))
3347                 return;
3348
3349         /* now it's all ours */
3350         intel_dp->pps_pipe = crtc->pipe;
3351
3352         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3353                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3354
3355         /* init power sequencer on this pipe and port */
3356         intel_dp_init_panel_power_sequencer(intel_dp);
3357         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3358 }
3359
3360 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3361                               const struct intel_crtc_state *pipe_config,
3362                               const struct drm_connector_state *conn_state)
3363 {
3364         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3365
3366         intel_enable_dp(encoder, pipe_config, conn_state);
3367 }
3368
3369 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3370                                   const struct intel_crtc_state *pipe_config,
3371                                   const struct drm_connector_state *conn_state)
3372 {
3373         intel_dp_prepare(encoder, pipe_config);
3374
3375         vlv_phy_pre_pll_enable(encoder, pipe_config);
3376 }
3377
3378 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3379                               const struct intel_crtc_state *pipe_config,
3380                               const struct drm_connector_state *conn_state)
3381 {
3382         chv_phy_pre_encoder_enable(encoder, pipe_config);
3383
3384         intel_enable_dp(encoder, pipe_config, conn_state);
3385
3386         /* Second common lane will stay alive on its own now */
3387         chv_phy_release_cl2_override(encoder);
3388 }
3389
3390 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3391                                   const struct intel_crtc_state *pipe_config,
3392                                   const struct drm_connector_state *conn_state)
3393 {
3394         intel_dp_prepare(encoder, pipe_config);
3395
3396         chv_phy_pre_pll_enable(encoder, pipe_config);
3397 }
3398
3399 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3400                                     const struct intel_crtc_state *old_crtc_state,
3401                                     const struct drm_connector_state *old_conn_state)
3402 {
3403         chv_phy_post_pll_disable(encoder, old_crtc_state);
3404 }
3405
3406 /*
3407  * Fetch AUX CH registers 0x202 - 0x207 which contain
3408  * link status information
3409  */
3410 bool
3411 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3412 {
3413         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3414                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3415 }
3416
3417 /* These are source-specific values. */
3418 uint8_t
3419 intel_dp_voltage_max(struct intel_dp *intel_dp)
3420 {
3421         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3422         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3423         enum port port = encoder->port;
3424
3425         if (HAS_DDI(dev_priv))
3426                 return intel_ddi_dp_voltage_max(encoder);
3427         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3428                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3429         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3430                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3431         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3432                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3433         else
3434                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3435 }
3436
3437 uint8_t
3438 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3439 {
3440         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3441         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3442         enum port port = encoder->port;
3443
3444         if (HAS_DDI(dev_priv)) {
3445                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3446         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3447                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3448                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3449                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3450                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3451                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3452                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3453                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3454                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3455                 default:
3456                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3457                 }
3458         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3459                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3460                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3461                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3462                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3463                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3464                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3465                 default:
3466                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3467                 }
3468         } else {
3469                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3470                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3471                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3472                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3473                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3474                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3475                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3476                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3477                 default:
3478                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3479                 }
3480         }
3481 }
3482
3483 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3484 {
3485         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3486         unsigned long demph_reg_value, preemph_reg_value,
3487                 uniqtranscale_reg_value;
3488         uint8_t train_set = intel_dp->train_set[0];
3489
3490         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3491         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3492                 preemph_reg_value = 0x0004000;
3493                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3494                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3495                         demph_reg_value = 0x2B405555;
3496                         uniqtranscale_reg_value = 0x552AB83A;
3497                         break;
3498                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3499                         demph_reg_value = 0x2B404040;
3500                         uniqtranscale_reg_value = 0x5548B83A;
3501                         break;
3502                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3503                         demph_reg_value = 0x2B245555;
3504                         uniqtranscale_reg_value = 0x5560B83A;
3505                         break;
3506                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3507                         demph_reg_value = 0x2B405555;
3508                         uniqtranscale_reg_value = 0x5598DA3A;
3509                         break;
3510                 default:
3511                         return 0;
3512                 }
3513                 break;
3514         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3515                 preemph_reg_value = 0x0002000;
3516                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3517                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3518                         demph_reg_value = 0x2B404040;
3519                         uniqtranscale_reg_value = 0x5552B83A;
3520                         break;
3521                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3522                         demph_reg_value = 0x2B404848;
3523                         uniqtranscale_reg_value = 0x5580B83A;
3524                         break;
3525                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3526                         demph_reg_value = 0x2B404040;
3527                         uniqtranscale_reg_value = 0x55ADDA3A;
3528                         break;
3529                 default:
3530                         return 0;
3531                 }
3532                 break;
3533         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3534                 preemph_reg_value = 0x0000000;
3535                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3536                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3537                         demph_reg_value = 0x2B305555;
3538                         uniqtranscale_reg_value = 0x5570B83A;
3539                         break;
3540                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3541                         demph_reg_value = 0x2B2B4040;
3542                         uniqtranscale_reg_value = 0x55ADDA3A;
3543                         break;
3544                 default:
3545                         return 0;
3546                 }
3547                 break;
3548         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3549                 preemph_reg_value = 0x0006000;
3550                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3551                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3552                         demph_reg_value = 0x1B405555;
3553                         uniqtranscale_reg_value = 0x55ADDA3A;
3554                         break;
3555                 default:
3556                         return 0;
3557                 }
3558                 break;
3559         default:
3560                 return 0;
3561         }
3562
3563         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3564                                  uniqtranscale_reg_value, 0);
3565
3566         return 0;
3567 }
3568
3569 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3570 {
3571         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3572         u32 deemph_reg_value, margin_reg_value;
3573         bool uniq_trans_scale = false;
3574         uint8_t train_set = intel_dp->train_set[0];
3575
3576         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3577         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3578                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3579                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3580                         deemph_reg_value = 128;
3581                         margin_reg_value = 52;
3582                         break;
3583                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3584                         deemph_reg_value = 128;
3585                         margin_reg_value = 77;
3586                         break;
3587                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3588                         deemph_reg_value = 128;
3589                         margin_reg_value = 102;
3590                         break;
3591                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3592                         deemph_reg_value = 128;
3593                         margin_reg_value = 154;
3594                         uniq_trans_scale = true;
3595                         break;
3596                 default:
3597                         return 0;
3598                 }
3599                 break;
3600         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3601                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3602                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3603                         deemph_reg_value = 85;
3604                         margin_reg_value = 78;
3605                         break;
3606                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3607                         deemph_reg_value = 85;
3608                         margin_reg_value = 116;
3609                         break;
3610                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3611                         deemph_reg_value = 85;
3612                         margin_reg_value = 154;
3613                         break;
3614                 default:
3615                         return 0;
3616                 }
3617                 break;
3618         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3619                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3620                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3621                         deemph_reg_value = 64;
3622                         margin_reg_value = 104;
3623                         break;
3624                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3625                         deemph_reg_value = 64;
3626                         margin_reg_value = 154;
3627                         break;
3628                 default:
3629                         return 0;
3630                 }
3631                 break;
3632         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3633                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3634                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3635                         deemph_reg_value = 43;
3636                         margin_reg_value = 154;
3637                         break;
3638                 default:
3639                         return 0;
3640                 }
3641                 break;
3642         default:
3643                 return 0;
3644         }
3645
3646         chv_set_phy_signal_level(encoder, deemph_reg_value,
3647                                  margin_reg_value, uniq_trans_scale);
3648
3649         return 0;
3650 }
3651
3652 static uint32_t
3653 g4x_signal_levels(uint8_t train_set)
3654 {
3655         uint32_t        signal_levels = 0;
3656
3657         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3658         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3659         default:
3660                 signal_levels |= DP_VOLTAGE_0_4;
3661                 break;
3662         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3663                 signal_levels |= DP_VOLTAGE_0_6;
3664                 break;
3665         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3666                 signal_levels |= DP_VOLTAGE_0_8;
3667                 break;
3668         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3669                 signal_levels |= DP_VOLTAGE_1_2;
3670                 break;
3671         }
3672         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3673         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3674         default:
3675                 signal_levels |= DP_PRE_EMPHASIS_0;
3676                 break;
3677         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3678                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3679                 break;
3680         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3681                 signal_levels |= DP_PRE_EMPHASIS_6;
3682                 break;
3683         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3684                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3685                 break;
3686         }
3687         return signal_levels;
3688 }
3689
3690 /* SNB CPU eDP voltage swing and pre-emphasis control */
3691 static uint32_t
3692 snb_cpu_edp_signal_levels(uint8_t train_set)
3693 {
3694         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3695                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3696         switch (signal_levels) {
3697         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3698         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3699                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3700         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3701                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3702         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3703         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3704                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3705         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3706         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3707                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3708         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3709         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3710                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3711         default:
3712                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3713                               "0x%x\n", signal_levels);
3714                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3715         }
3716 }
3717
3718 /* IVB CPU eDP voltage swing and pre-emphasis control */
3719 static uint32_t
3720 ivb_cpu_edp_signal_levels(uint8_t train_set)
3721 {
3722         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3723                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3724         switch (signal_levels) {
3725         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3726                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3727         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3728                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3729         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3730                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3731
3732         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3733                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3734         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3735                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3736
3737         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3738                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3739         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3740                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3741
3742         default:
3743                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3744                               "0x%x\n", signal_levels);
3745                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3746         }
3747 }
3748
3749 void
3750 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3751 {
3752         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3753         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3754         enum port port = intel_dig_port->base.port;
3755         uint32_t signal_levels, mask = 0;
3756         uint8_t train_set = intel_dp->train_set[0];
3757
3758         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3759                 signal_levels = bxt_signal_levels(intel_dp);
3760         } else if (HAS_DDI(dev_priv)) {
3761                 signal_levels = ddi_signal_levels(intel_dp);
3762                 mask = DDI_BUF_EMP_MASK;
3763         } else if (IS_CHERRYVIEW(dev_priv)) {
3764                 signal_levels = chv_signal_levels(intel_dp);
3765         } else if (IS_VALLEYVIEW(dev_priv)) {
3766                 signal_levels = vlv_signal_levels(intel_dp);
3767         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3768                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3769                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3770         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3771                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3772                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3773         } else {
3774                 signal_levels = g4x_signal_levels(train_set);
3775                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3776         }
3777
3778         if (mask)
3779                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3780
3781         DRM_DEBUG_KMS("Using vswing level %d\n",
3782                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3783         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3784                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3785                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3786
3787         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3788
3789         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3790         POSTING_READ(intel_dp->output_reg);
3791 }
3792
3793 void
3794 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3795                                        uint8_t dp_train_pat)
3796 {
3797         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3798         struct drm_i915_private *dev_priv =
3799                 to_i915(intel_dig_port->base.base.dev);
3800
3801         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3802
3803         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3804         POSTING_READ(intel_dp->output_reg);
3805 }
3806
3807 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3808 {
3809         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3810         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3811         enum port port = intel_dig_port->base.port;
3812         uint32_t val;
3813
3814         if (!HAS_DDI(dev_priv))
3815                 return;
3816
3817         val = I915_READ(DP_TP_CTL(port));
3818         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3819         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3820         I915_WRITE(DP_TP_CTL(port), val);
3821
3822         /*
3823          * On PORT_A we can have only eDP in SST mode. There the only reason
3824          * we need to set idle transmission mode is to work around a HW issue
3825          * where we enable the pipe while not in idle link-training mode.
3826          * In this case there is requirement to wait for a minimum number of
3827          * idle patterns to be sent.
3828          */
3829         if (port == PORT_A)
3830                 return;
3831
3832         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3833                                     DP_TP_STATUS_IDLE_DONE,
3834                                     DP_TP_STATUS_IDLE_DONE,
3835                                     1))
3836                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3837 }
3838
3839 static void
3840 intel_dp_link_down(struct intel_encoder *encoder,
3841                    const struct intel_crtc_state *old_crtc_state)
3842 {
3843         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3844         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3845         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3846         enum port port = encoder->port;
3847         uint32_t DP = intel_dp->DP;
3848
3849         if (WARN_ON(HAS_DDI(dev_priv)))
3850                 return;
3851
3852         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3853                 return;
3854
3855         DRM_DEBUG_KMS("\n");
3856
3857         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3858             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3859                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3860                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3861         } else {
3862                 DP &= ~DP_LINK_TRAIN_MASK;
3863                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3864         }
3865         I915_WRITE(intel_dp->output_reg, DP);
3866         POSTING_READ(intel_dp->output_reg);
3867
3868         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3869         I915_WRITE(intel_dp->output_reg, DP);
3870         POSTING_READ(intel_dp->output_reg);
3871
3872         /*
3873          * HW workaround for IBX, we need to move the port
3874          * to transcoder A after disabling it to allow the
3875          * matching HDMI port to be enabled on transcoder A.
3876          */
3877         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3878                 /*
3879                  * We get CPU/PCH FIFO underruns on the other pipe when
3880                  * doing the workaround. Sweep them under the rug.
3881                  */
3882                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3883                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3884
3885                 /* always enable with pattern 1 (as per spec) */
3886                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3887                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3888                         DP_LINK_TRAIN_PAT_1;
3889                 I915_WRITE(intel_dp->output_reg, DP);
3890                 POSTING_READ(intel_dp->output_reg);
3891
3892                 DP &= ~DP_PORT_EN;
3893                 I915_WRITE(intel_dp->output_reg, DP);
3894                 POSTING_READ(intel_dp->output_reg);
3895
3896                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3897                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3898                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3899         }
3900
3901         msleep(intel_dp->panel_power_down_delay);
3902
3903         intel_dp->DP = DP;
3904
3905         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3906                 pps_lock(intel_dp);
3907                 intel_dp->active_pipe = INVALID_PIPE;
3908                 pps_unlock(intel_dp);
3909         }
3910 }
3911
3912 bool
3913 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3914 {
3915         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3916                              sizeof(intel_dp->dpcd)) < 0)
3917                 return false; /* aux transfer failed */
3918
3919         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3920
3921         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3922 }
3923
3924 static bool
3925 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3926 {
3927         struct drm_i915_private *dev_priv =
3928                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3929
3930         /* this function is meant to be called only once */
3931         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3932
3933         if (!intel_dp_read_dpcd(intel_dp))
3934                 return false;
3935
3936         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3937                          drm_dp_is_branch(intel_dp->dpcd));
3938
3939         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3940                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3941                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3942
3943         /*
3944          * Read the eDP display control registers.
3945          *
3946          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3947          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3948          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3949          * method). The display control registers should read zero if they're
3950          * not supported anyway.
3951          */
3952         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3953                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3954                              sizeof(intel_dp->edp_dpcd))
3955                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3956                               intel_dp->edp_dpcd);
3957
3958         /*
3959          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3960          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3961          */
3962         intel_psr_init_dpcd(intel_dp);
3963
3964         /* Read the eDP 1.4+ supported link rates. */
3965         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3966                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3967                 int i;
3968
3969                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3970                                 sink_rates, sizeof(sink_rates));
3971
3972                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3973                         int val = le16_to_cpu(sink_rates[i]);
3974
3975                         if (val == 0)
3976                                 break;
3977
3978                         /* Value read multiplied by 200kHz gives the per-lane
3979                          * link rate in kHz. The source rates are, however,
3980                          * stored in terms of LS_Clk kHz. The full conversion
3981                          * back to symbols is
3982                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3983                          */
3984                         intel_dp->sink_rates[i] = (val * 200) / 10;
3985                 }
3986                 intel_dp->num_sink_rates = i;
3987         }
3988
3989         /*
3990          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3991          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3992          */
3993         if (intel_dp->num_sink_rates)
3994                 intel_dp->use_rate_select = true;
3995         else
3996                 intel_dp_set_sink_rates(intel_dp);
3997
3998         intel_dp_set_common_rates(intel_dp);
3999
4000         return true;
4001 }
4002
4003
4004 static bool
4005 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4006 {
4007         u8 sink_count;
4008
4009         if (!intel_dp_read_dpcd(intel_dp))
4010                 return false;
4011
4012         /* Don't clobber cached eDP rates. */
4013         if (!intel_dp_is_edp(intel_dp)) {
4014                 intel_dp_set_sink_rates(intel_dp);
4015                 intel_dp_set_common_rates(intel_dp);
4016         }
4017
4018         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
4019                 return false;
4020
4021         /*
4022          * Sink count can change between short pulse hpd hence
4023          * a member variable in intel_dp will track any changes
4024          * between short pulse interrupts.
4025          */
4026         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
4027
4028         /*
4029          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4030          * a dongle is present but no display. Unless we require to know
4031          * if a dongle is present or not, we don't need to update
4032          * downstream port information. So, an early return here saves
4033          * time from performing other operations which are not required.
4034          */
4035         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
4036                 return false;
4037
4038         if (!drm_dp_is_branch(intel_dp->dpcd))
4039                 return true; /* native DP sink */
4040
4041         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4042                 return true; /* no per-port downstream info */
4043
4044         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4045                              intel_dp->downstream_ports,
4046                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4047                 return false; /* downstream port status fetch failed */
4048
4049         return true;
4050 }
4051
4052 static bool
4053 intel_dp_can_mst(struct intel_dp *intel_dp)
4054 {
4055         u8 mstm_cap;
4056
4057         if (!i915_modparams.enable_dp_mst)
4058                 return false;
4059
4060         if (!intel_dp->can_mst)
4061                 return false;
4062
4063         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4064                 return false;
4065
4066         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4067                 return false;
4068
4069         return mstm_cap & DP_MST_CAP;
4070 }
4071
4072 static void
4073 intel_dp_configure_mst(struct intel_dp *intel_dp)
4074 {
4075         if (!i915_modparams.enable_dp_mst)
4076                 return;
4077
4078         if (!intel_dp->can_mst)
4079                 return;
4080
4081         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
4082
4083         if (intel_dp->is_mst)
4084                 DRM_DEBUG_KMS("Sink is MST capable\n");
4085         else
4086                 DRM_DEBUG_KMS("Sink is not MST capable\n");
4087
4088         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4089                                         intel_dp->is_mst);
4090 }
4091
4092 static bool
4093 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4094 {
4095         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4096                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4097                 DP_DPRX_ESI_LEN;
4098 }
4099
4100 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4101 {
4102         int status = 0;
4103         int test_link_rate;
4104         uint8_t test_lane_count, test_link_bw;
4105         /* (DP CTS 1.2)
4106          * 4.3.1.11
4107          */
4108         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4109         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4110                                    &test_lane_count);
4111
4112         if (status <= 0) {
4113                 DRM_DEBUG_KMS("Lane count read failed\n");
4114                 return DP_TEST_NAK;
4115         }
4116         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4117
4118         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4119                                    &test_link_bw);
4120         if (status <= 0) {
4121                 DRM_DEBUG_KMS("Link Rate read failed\n");
4122                 return DP_TEST_NAK;
4123         }
4124         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4125
4126         /* Validate the requested link rate and lane count */
4127         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4128                                         test_lane_count))
4129                 return DP_TEST_NAK;
4130
4131         intel_dp->compliance.test_lane_count = test_lane_count;
4132         intel_dp->compliance.test_link_rate = test_link_rate;
4133
4134         return DP_TEST_ACK;
4135 }
4136
4137 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4138 {
4139         uint8_t test_pattern;
4140         uint8_t test_misc;
4141         __be16 h_width, v_height;
4142         int status = 0;
4143
4144         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4145         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4146                                    &test_pattern);
4147         if (status <= 0) {
4148                 DRM_DEBUG_KMS("Test pattern read failed\n");
4149                 return DP_TEST_NAK;
4150         }
4151         if (test_pattern != DP_COLOR_RAMP)
4152                 return DP_TEST_NAK;
4153
4154         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4155                                   &h_width, 2);
4156         if (status <= 0) {
4157                 DRM_DEBUG_KMS("H Width read failed\n");
4158                 return DP_TEST_NAK;
4159         }
4160
4161         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4162                                   &v_height, 2);
4163         if (status <= 0) {
4164                 DRM_DEBUG_KMS("V Height read failed\n");
4165                 return DP_TEST_NAK;
4166         }
4167
4168         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4169                                    &test_misc);
4170         if (status <= 0) {
4171                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4172                 return DP_TEST_NAK;
4173         }
4174         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4175                 return DP_TEST_NAK;
4176         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4177                 return DP_TEST_NAK;
4178         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4179         case DP_TEST_BIT_DEPTH_6:
4180                 intel_dp->compliance.test_data.bpc = 6;
4181                 break;
4182         case DP_TEST_BIT_DEPTH_8:
4183                 intel_dp->compliance.test_data.bpc = 8;
4184                 break;
4185         default:
4186                 return DP_TEST_NAK;
4187         }
4188
4189         intel_dp->compliance.test_data.video_pattern = test_pattern;
4190         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4191         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4192         /* Set test active flag here so userspace doesn't interrupt things */
4193         intel_dp->compliance.test_active = 1;
4194
4195         return DP_TEST_ACK;
4196 }
4197
4198 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4199 {
4200         uint8_t test_result = DP_TEST_ACK;
4201         struct intel_connector *intel_connector = intel_dp->attached_connector;
4202         struct drm_connector *connector = &intel_connector->base;
4203
4204         if (intel_connector->detect_edid == NULL ||
4205             connector->edid_corrupt ||
4206             intel_dp->aux.i2c_defer_count > 6) {
4207                 /* Check EDID read for NACKs, DEFERs and corruption
4208                  * (DP CTS 1.2 Core r1.1)
4209                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4210                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4211                  *    4.2.2.6 : EDID corruption detected
4212                  * Use failsafe mode for all cases
4213                  */
4214                 if (intel_dp->aux.i2c_nack_count > 0 ||
4215                         intel_dp->aux.i2c_defer_count > 0)
4216                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4217                                       intel_dp->aux.i2c_nack_count,
4218                                       intel_dp->aux.i2c_defer_count);
4219                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4220         } else {
4221                 struct edid *block = intel_connector->detect_edid;
4222
4223                 /* We have to write the checksum
4224                  * of the last block read
4225                  */
4226                 block += intel_connector->detect_edid->extensions;
4227
4228                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4229                                        block->checksum) <= 0)
4230                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4231
4232                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4233                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4234         }
4235
4236         /* Set test active flag here so userspace doesn't interrupt things */
4237         intel_dp->compliance.test_active = 1;
4238
4239         return test_result;
4240 }
4241
4242 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4243 {
4244         uint8_t test_result = DP_TEST_NAK;
4245         return test_result;
4246 }
4247
4248 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4249 {
4250         uint8_t response = DP_TEST_NAK;
4251         uint8_t request = 0;
4252         int status;
4253
4254         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4255         if (status <= 0) {
4256                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4257                 goto update_status;
4258         }
4259
4260         switch (request) {
4261         case DP_TEST_LINK_TRAINING:
4262                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4263                 response = intel_dp_autotest_link_training(intel_dp);
4264                 break;
4265         case DP_TEST_LINK_VIDEO_PATTERN:
4266                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4267                 response = intel_dp_autotest_video_pattern(intel_dp);
4268                 break;
4269         case DP_TEST_LINK_EDID_READ:
4270                 DRM_DEBUG_KMS("EDID test requested\n");
4271                 response = intel_dp_autotest_edid(intel_dp);
4272                 break;
4273         case DP_TEST_LINK_PHY_TEST_PATTERN:
4274                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4275                 response = intel_dp_autotest_phy_pattern(intel_dp);
4276                 break;
4277         default:
4278                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4279                 break;
4280         }
4281
4282         if (response & DP_TEST_ACK)
4283                 intel_dp->compliance.test_type = request;
4284
4285 update_status:
4286         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4287         if (status <= 0)
4288                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4289 }
4290
4291 static int
4292 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4293 {
4294         bool bret;
4295
4296         if (intel_dp->is_mst) {
4297                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4298                 int ret = 0;
4299                 int retry;
4300                 bool handled;
4301
4302                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4303                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4304 go_again:
4305                 if (bret == true) {
4306
4307                         /* check link status - esi[10] = 0x200c */
4308                         if (intel_dp->active_mst_links > 0 &&
4309                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4310                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4311                                 intel_dp_start_link_train(intel_dp);
4312                                 intel_dp_stop_link_train(intel_dp);
4313                         }
4314
4315                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4316                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4317
4318                         if (handled) {
4319                                 for (retry = 0; retry < 3; retry++) {
4320                                         int wret;
4321                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4322                                                                  DP_SINK_COUNT_ESI+1,
4323                                                                  &esi[1], 3);
4324                                         if (wret == 3) {
4325                                                 break;
4326                                         }
4327                                 }
4328
4329                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4330                                 if (bret == true) {
4331                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4332                                         goto go_again;
4333                                 }
4334                         } else
4335                                 ret = 0;
4336
4337                         return ret;
4338                 } else {
4339                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4340                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4341                         intel_dp->is_mst = false;
4342                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4343                         /* send a hotplug event */
4344                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4345                 }
4346         }
4347         return -EINVAL;
4348 }
4349
4350 static bool
4351 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4352 {
4353         u8 link_status[DP_LINK_STATUS_SIZE];
4354
4355         if (!intel_dp->link_trained)
4356                 return false;
4357
4358         if (!intel_dp_get_link_status(intel_dp, link_status))
4359                 return false;
4360
4361         /*
4362          * Validate the cached values of intel_dp->link_rate and
4363          * intel_dp->lane_count before attempting to retrain.
4364          */
4365         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4366                                         intel_dp->lane_count))
4367                 return false;
4368
4369         /* Retrain if Channel EQ or CR not ok */
4370         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4371 }
4372
4373 int intel_dp_retrain_link(struct intel_encoder *encoder,
4374                           struct drm_modeset_acquire_ctx *ctx)
4375 {
4376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4377         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4378         struct intel_connector *connector = intel_dp->attached_connector;
4379         struct drm_connector_state *conn_state;
4380         struct intel_crtc_state *crtc_state;
4381         struct intel_crtc *crtc;
4382         int ret;
4383
4384         /* FIXME handle the MST connectors as well */
4385
4386         if (!connector || connector->base.status != connector_status_connected)
4387                 return 0;
4388
4389         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4390                                ctx);
4391         if (ret)
4392                 return ret;
4393
4394         conn_state = connector->base.state;
4395
4396         crtc = to_intel_crtc(conn_state->crtc);
4397         if (!crtc)
4398                 return 0;
4399
4400         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4401         if (ret)
4402                 return ret;
4403
4404         crtc_state = to_intel_crtc_state(crtc->base.state);
4405
4406         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4407
4408         if (!crtc_state->base.active)
4409                 return 0;
4410
4411         if (conn_state->commit &&
4412             !try_wait_for_completion(&conn_state->commit->hw_done))
4413                 return 0;
4414
4415         if (!intel_dp_needs_link_retrain(intel_dp))
4416                 return 0;
4417
4418         /* Suppress underruns caused by re-training */
4419         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4420         if (crtc->config->has_pch_encoder)
4421                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4422                                                       intel_crtc_pch_transcoder(crtc), false);
4423
4424         intel_dp_start_link_train(intel_dp);
4425         intel_dp_stop_link_train(intel_dp);
4426
4427         /* Keep underrun reporting disabled until things are stable */
4428         intel_wait_for_vblank(dev_priv, crtc->pipe);
4429
4430         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4431         if (crtc->config->has_pch_encoder)
4432                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4433                                                       intel_crtc_pch_transcoder(crtc), true);
4434
4435         return 0;
4436 }
4437
4438 /*
4439  * If display is now connected check links status,
4440  * there has been known issues of link loss triggering
4441  * long pulse.
4442  *
4443  * Some sinks (eg. ASUS PB287Q) seem to perform some
4444  * weird HPD ping pong during modesets. So we can apparently
4445  * end up with HPD going low during a modeset, and then
4446  * going back up soon after. And once that happens we must
4447  * retrain the link to get a picture. That's in case no
4448  * userspace component reacted to intermittent HPD dip.
4449  */
4450 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4451                              struct intel_connector *connector)
4452 {
4453         struct drm_modeset_acquire_ctx ctx;
4454         bool changed;
4455         int ret;
4456
4457         changed = intel_encoder_hotplug(encoder, connector);
4458
4459         drm_modeset_acquire_init(&ctx, 0);
4460
4461         for (;;) {
4462                 ret = intel_dp_retrain_link(encoder, &ctx);
4463
4464                 if (ret == -EDEADLK) {
4465                         drm_modeset_backoff(&ctx);
4466                         continue;
4467                 }
4468
4469                 break;
4470         }
4471
4472         drm_modeset_drop_locks(&ctx);
4473         drm_modeset_acquire_fini(&ctx);
4474         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4475
4476         return changed;
4477 }
4478
4479 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4480 {
4481         u8 val;
4482
4483         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4484                 return;
4485
4486         if (drm_dp_dpcd_readb(&intel_dp->aux,
4487                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4488                 return;
4489
4490         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4491
4492         if (val & DP_AUTOMATED_TEST_REQUEST)
4493                 intel_dp_handle_test_request(intel_dp);
4494
4495         if (val & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4496                 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4497 }
4498
4499 /*
4500  * According to DP spec
4501  * 5.1.2:
4502  *  1. Read DPCD
4503  *  2. Configure link according to Receiver Capabilities
4504  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4505  *  4. Check link status on receipt of hot-plug interrupt
4506  *
4507  * intel_dp_short_pulse -  handles short pulse interrupts
4508  * when full detection is not required.
4509  * Returns %true if short pulse is handled and full detection
4510  * is NOT required and %false otherwise.
4511  */
4512 static bool
4513 intel_dp_short_pulse(struct intel_dp *intel_dp)
4514 {
4515         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4516         u8 old_sink_count = intel_dp->sink_count;
4517         bool ret;
4518
4519         /*
4520          * Clearing compliance test variables to allow capturing
4521          * of values for next automated test request.
4522          */
4523         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4524
4525         /*
4526          * Now read the DPCD to see if it's actually running
4527          * If the current value of sink count doesn't match with
4528          * the value that was stored earlier or dpcd read failed
4529          * we need to do full detection
4530          */
4531         ret = intel_dp_get_dpcd(intel_dp);
4532
4533         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4534                 /* No need to proceed if we are going to do full detect */
4535                 return false;
4536         }
4537
4538         intel_dp_check_service_irq(intel_dp);
4539
4540         /* Handle CEC interrupts, if any */
4541         drm_dp_cec_irq(&intel_dp->aux);
4542
4543         /* defer to the hotplug work for link retraining if needed */
4544         if (intel_dp_needs_link_retrain(intel_dp))
4545                 return false;
4546
4547         intel_psr_short_pulse(intel_dp);
4548
4549         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4550                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4551                 /* Send a Hotplug Uevent to userspace to start modeset */
4552                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4553         }
4554
4555         return true;
4556 }
4557
4558 /* XXX this is probably wrong for multiple downstream ports */
4559 static enum drm_connector_status
4560 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4561 {
4562         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4563         uint8_t *dpcd = intel_dp->dpcd;
4564         uint8_t type;
4565
4566         if (lspcon->active)
4567                 lspcon_resume(lspcon);
4568
4569         if (!intel_dp_get_dpcd(intel_dp))
4570                 return connector_status_disconnected;
4571
4572         if (intel_dp_is_edp(intel_dp))
4573                 return connector_status_connected;
4574
4575         /* if there's no downstream port, we're done */
4576         if (!drm_dp_is_branch(dpcd))
4577                 return connector_status_connected;
4578
4579         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4580         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4581             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4582
4583                 return intel_dp->sink_count ?
4584                 connector_status_connected : connector_status_disconnected;
4585         }
4586
4587         if (intel_dp_can_mst(intel_dp))
4588                 return connector_status_connected;
4589
4590         /* If no HPD, poke DDC gently */
4591         if (drm_probe_ddc(&intel_dp->aux.ddc))
4592                 return connector_status_connected;
4593
4594         /* Well we tried, say unknown for unreliable port types */
4595         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4596                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4597                 if (type == DP_DS_PORT_TYPE_VGA ||
4598                     type == DP_DS_PORT_TYPE_NON_EDID)
4599                         return connector_status_unknown;
4600         } else {
4601                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4602                         DP_DWN_STRM_PORT_TYPE_MASK;
4603                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4604                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4605                         return connector_status_unknown;
4606         }
4607
4608         /* Anything else is out of spec, warn and ignore */
4609         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4610         return connector_status_disconnected;
4611 }
4612
4613 static enum drm_connector_status
4614 edp_detect(struct intel_dp *intel_dp)
4615 {
4616         return connector_status_connected;
4617 }
4618
4619 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4620 {
4621         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4622         u32 bit;
4623
4624         switch (encoder->hpd_pin) {
4625         case HPD_PORT_B:
4626                 bit = SDE_PORTB_HOTPLUG;
4627                 break;
4628         case HPD_PORT_C:
4629                 bit = SDE_PORTC_HOTPLUG;
4630                 break;
4631         case HPD_PORT_D:
4632                 bit = SDE_PORTD_HOTPLUG;
4633                 break;
4634         default:
4635                 MISSING_CASE(encoder->hpd_pin);
4636                 return false;
4637         }
4638
4639         return I915_READ(SDEISR) & bit;
4640 }
4641
4642 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4643 {
4644         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4645         u32 bit;
4646
4647         switch (encoder->hpd_pin) {
4648         case HPD_PORT_B:
4649                 bit = SDE_PORTB_HOTPLUG_CPT;
4650                 break;
4651         case HPD_PORT_C:
4652                 bit = SDE_PORTC_HOTPLUG_CPT;
4653                 break;
4654         case HPD_PORT_D:
4655                 bit = SDE_PORTD_HOTPLUG_CPT;
4656                 break;
4657         default:
4658                 MISSING_CASE(encoder->hpd_pin);
4659                 return false;
4660         }
4661
4662         return I915_READ(SDEISR) & bit;
4663 }
4664
4665 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4666 {
4667         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4668         u32 bit;
4669
4670         switch (encoder->hpd_pin) {
4671         case HPD_PORT_A:
4672                 bit = SDE_PORTA_HOTPLUG_SPT;
4673                 break;
4674         case HPD_PORT_E:
4675                 bit = SDE_PORTE_HOTPLUG_SPT;
4676                 break;
4677         default:
4678                 return cpt_digital_port_connected(encoder);
4679         }
4680
4681         return I915_READ(SDEISR) & bit;
4682 }
4683
4684 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4685 {
4686         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4687         u32 bit;
4688
4689         switch (encoder->hpd_pin) {
4690         case HPD_PORT_B:
4691                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4692                 break;
4693         case HPD_PORT_C:
4694                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4695                 break;
4696         case HPD_PORT_D:
4697                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4698                 break;
4699         default:
4700                 MISSING_CASE(encoder->hpd_pin);
4701                 return false;
4702         }
4703
4704         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4705 }
4706
4707 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4708 {
4709         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4710         u32 bit;
4711
4712         switch (encoder->hpd_pin) {
4713         case HPD_PORT_B:
4714                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4715                 break;
4716         case HPD_PORT_C:
4717                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4718                 break;
4719         case HPD_PORT_D:
4720                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4721                 break;
4722         default:
4723                 MISSING_CASE(encoder->hpd_pin);
4724                 return false;
4725         }
4726
4727         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4728 }
4729
4730 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4731 {
4732         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4733
4734         if (encoder->hpd_pin == HPD_PORT_A)
4735                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4736         else
4737                 return ibx_digital_port_connected(encoder);
4738 }
4739
4740 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4741 {
4742         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4743
4744         if (encoder->hpd_pin == HPD_PORT_A)
4745                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4746         else
4747                 return cpt_digital_port_connected(encoder);
4748 }
4749
4750 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4751 {
4752         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4753
4754         if (encoder->hpd_pin == HPD_PORT_A)
4755                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4756         else
4757                 return cpt_digital_port_connected(encoder);
4758 }
4759
4760 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4761 {
4762         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4763
4764         if (encoder->hpd_pin == HPD_PORT_A)
4765                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4766         else
4767                 return cpt_digital_port_connected(encoder);
4768 }
4769
4770 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4771 {
4772         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4773         u32 bit;
4774
4775         switch (encoder->hpd_pin) {
4776         case HPD_PORT_A:
4777                 bit = BXT_DE_PORT_HP_DDIA;
4778                 break;
4779         case HPD_PORT_B:
4780                 bit = BXT_DE_PORT_HP_DDIB;
4781                 break;
4782         case HPD_PORT_C:
4783                 bit = BXT_DE_PORT_HP_DDIC;
4784                 break;
4785         default:
4786                 MISSING_CASE(encoder->hpd_pin);
4787                 return false;
4788         }
4789
4790         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4791 }
4792
4793 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
4794                                      struct intel_digital_port *intel_dig_port)
4795 {
4796         enum port port = intel_dig_port->base.port;
4797
4798         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
4799 }
4800
4801 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4802                                     struct intel_digital_port *intel_dig_port,
4803                                     bool is_legacy, bool is_typec, bool is_tbt)
4804 {
4805         enum port port = intel_dig_port->base.port;
4806         enum tc_port_type old_type = intel_dig_port->tc_type;
4807         const char *type_str;
4808
4809         WARN_ON(is_legacy + is_typec + is_tbt != 1);
4810
4811         if (is_legacy) {
4812                 intel_dig_port->tc_type = TC_PORT_LEGACY;
4813                 type_str = "legacy";
4814         } else if (is_typec) {
4815                 intel_dig_port->tc_type = TC_PORT_TYPEC;
4816                 type_str = "typec";
4817         } else if (is_tbt) {
4818                 intel_dig_port->tc_type = TC_PORT_TBT;
4819                 type_str = "tbt";
4820         } else {
4821                 return;
4822         }
4823
4824         /* Types are not supposed to be changed at runtime. */
4825         WARN_ON(old_type != TC_PORT_UNKNOWN &&
4826                 old_type != intel_dig_port->tc_type);
4827
4828         if (old_type != intel_dig_port->tc_type)
4829                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
4830                               type_str);
4831 }
4832
4833 /*
4834  * This function implements the first part of the Connect Flow described by our
4835  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
4836  * lanes, EDID, etc) is done as needed in the typical places.
4837  *
4838  * Unlike the other ports, type-C ports are not available to use as soon as we
4839  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
4840  * display, USB, etc. As a result, handshaking through FIA is required around
4841  * connect and disconnect to cleanly transfer ownership with the controller and
4842  * set the type-C power state.
4843  *
4844  * We could opt to only do the connect flow when we actually try to use the AUX
4845  * channels or do a modeset, then immediately run the disconnect flow after
4846  * usage, but there are some implications on this for a dynamic environment:
4847  * things may go away or change behind our backs. So for now our driver is
4848  * always trying to acquire ownership of the controller as soon as it gets an
4849  * interrupt (or polls state and sees a port is connected) and only gives it
4850  * back when it sees a disconnect. Implementation of a more fine-grained model
4851  * will require a lot of coordination with user space and thorough testing for
4852  * the extra possible cases.
4853  */
4854 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4855                                struct intel_digital_port *dig_port)
4856 {
4857         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4858         u32 val;
4859
4860         if (dig_port->tc_type != TC_PORT_LEGACY &&
4861             dig_port->tc_type != TC_PORT_TYPEC)
4862                 return true;
4863
4864         val = I915_READ(PORT_TX_DFLEXDPPMS);
4865         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
4866                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
4867                 return false;
4868         }
4869
4870         /*
4871          * This function may be called many times in a row without an HPD event
4872          * in between, so try to avoid the write when we can.
4873          */
4874         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4875         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
4876                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4877                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4878         }
4879
4880         /*
4881          * Now we have to re-check the live state, in case the port recently
4882          * became disconnected. Not necessary for legacy mode.
4883          */
4884         if (dig_port->tc_type == TC_PORT_TYPEC &&
4885             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4886                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4887                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4888                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4889                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4890                 return false;
4891         }
4892
4893         return true;
4894 }
4895
4896 /*
4897  * See the comment at the connect function. This implements the Disconnect
4898  * Flow.
4899  */
4900 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4901                                   struct intel_digital_port *dig_port)
4902 {
4903         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4904         u32 val;
4905
4906         if (dig_port->tc_type != TC_PORT_LEGACY &&
4907             dig_port->tc_type != TC_PORT_TYPEC)
4908                 return;
4909
4910         /*
4911          * This function may be called many times in a row without an HPD event
4912          * in between, so try to avoid the write when we can.
4913          */
4914         val = I915_READ(PORT_TX_DFLEXDPCSSS);
4915         if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
4916                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4917                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4918         }
4919 }
4920
4921 /*
4922  * The type-C ports are different because even when they are connected, they may
4923  * not be available/usable by the graphics driver: see the comment on
4924  * icl_tc_phy_connect(). So in our driver instead of adding the additional
4925  * concept of "usable" and make everything check for "connected and usable" we
4926  * define a port as "connected" when it is not only connected, but also when it
4927  * is usable by the rest of the driver. That maintains the old assumption that
4928  * connected ports are usable, and avoids exposing to the users objects they
4929  * can't really use.
4930  */
4931 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
4932                                   struct intel_digital_port *intel_dig_port)
4933 {
4934         enum port port = intel_dig_port->base.port;
4935         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4936         bool is_legacy, is_typec, is_tbt;
4937         u32 dpsp;
4938
4939         is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
4940
4941         /*
4942          * The spec says we shouldn't be using the ISR bits for detecting
4943          * between TC and TBT. We should use DFLEXDPSP.
4944          */
4945         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
4946         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
4947         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
4948
4949         if (!is_legacy && !is_typec && !is_tbt) {
4950                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
4951                 return false;
4952         }
4953
4954         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
4955                                 is_tbt);
4956
4957         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
4958                 return false;
4959
4960         return true;
4961 }
4962
4963 static bool icl_digital_port_connected(struct intel_encoder *encoder)
4964 {
4965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4966         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4967
4968         switch (encoder->hpd_pin) {
4969         case HPD_PORT_A:
4970         case HPD_PORT_B:
4971                 return icl_combo_port_connected(dev_priv, dig_port);
4972         case HPD_PORT_C:
4973         case HPD_PORT_D:
4974         case HPD_PORT_E:
4975         case HPD_PORT_F:
4976                 return icl_tc_port_connected(dev_priv, dig_port);
4977         default:
4978                 MISSING_CASE(encoder->hpd_pin);
4979                 return false;
4980         }
4981 }
4982
4983 /*
4984  * intel_digital_port_connected - is the specified port connected?
4985  * @encoder: intel_encoder
4986  *
4987  * In cases where there's a connector physically connected but it can't be used
4988  * by our hardware we also return false, since the rest of the driver should
4989  * pretty much treat the port as disconnected. This is relevant for type-C
4990  * (starting on ICL) where there's ownership involved.
4991  *
4992  * Return %true if port is connected, %false otherwise.
4993  */
4994 bool intel_digital_port_connected(struct intel_encoder *encoder)
4995 {
4996         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4997
4998         if (HAS_GMCH_DISPLAY(dev_priv)) {
4999                 if (IS_GM45(dev_priv))
5000                         return gm45_digital_port_connected(encoder);
5001                 else
5002                         return g4x_digital_port_connected(encoder);
5003         }
5004
5005         if (IS_GEN5(dev_priv))
5006                 return ilk_digital_port_connected(encoder);
5007         else if (IS_GEN6(dev_priv))
5008                 return snb_digital_port_connected(encoder);
5009         else if (IS_GEN7(dev_priv))
5010                 return ivb_digital_port_connected(encoder);
5011         else if (IS_GEN8(dev_priv))
5012                 return bdw_digital_port_connected(encoder);
5013         else if (IS_GEN9_LP(dev_priv))
5014                 return bxt_digital_port_connected(encoder);
5015         else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
5016                 return spt_digital_port_connected(encoder);
5017         else
5018                 return icl_digital_port_connected(encoder);
5019 }
5020
5021 static struct edid *
5022 intel_dp_get_edid(struct intel_dp *intel_dp)
5023 {
5024         struct intel_connector *intel_connector = intel_dp->attached_connector;
5025
5026         /* use cached edid if we have one */
5027         if (intel_connector->edid) {
5028                 /* invalid edid */
5029                 if (IS_ERR(intel_connector->edid))
5030                         return NULL;
5031
5032                 return drm_edid_duplicate(intel_connector->edid);
5033         } else
5034                 return drm_get_edid(&intel_connector->base,
5035                                     &intel_dp->aux.ddc);
5036 }
5037
5038 static void
5039 intel_dp_set_edid(struct intel_dp *intel_dp)
5040 {
5041         struct intel_connector *intel_connector = intel_dp->attached_connector;
5042         struct edid *edid;
5043
5044         intel_dp_unset_edid(intel_dp);
5045         edid = intel_dp_get_edid(intel_dp);
5046         intel_connector->detect_edid = edid;
5047
5048         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5049         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5050 }
5051
5052 static void
5053 intel_dp_unset_edid(struct intel_dp *intel_dp)
5054 {
5055         struct intel_connector *intel_connector = intel_dp->attached_connector;
5056
5057         drm_dp_cec_unset_edid(&intel_dp->aux);
5058         kfree(intel_connector->detect_edid);
5059         intel_connector->detect_edid = NULL;
5060
5061         intel_dp->has_audio = false;
5062 }
5063
5064 static int
5065 intel_dp_detect(struct drm_connector *connector,
5066                 struct drm_modeset_acquire_ctx *ctx,
5067                 bool force)
5068 {
5069         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5070         struct intel_dp *intel_dp = intel_attached_dp(connector);
5071         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5072         enum drm_connector_status status;
5073
5074         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5075                       connector->base.id, connector->name);
5076         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5077
5078         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5079
5080         /* Can't disconnect eDP */
5081         if (intel_dp_is_edp(intel_dp))
5082                 status = edp_detect(intel_dp);
5083         else if (intel_digital_port_connected(encoder))
5084                 status = intel_dp_detect_dpcd(intel_dp);
5085         else
5086                 status = connector_status_disconnected;
5087
5088         if (status == connector_status_disconnected) {
5089                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5090
5091                 if (intel_dp->is_mst) {
5092                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5093                                       intel_dp->is_mst,
5094                                       intel_dp->mst_mgr.mst_state);
5095                         intel_dp->is_mst = false;
5096                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5097                                                         intel_dp->is_mst);
5098                 }
5099
5100                 goto out;
5101         }
5102
5103         if (intel_dp->reset_link_params) {
5104                 /* Initial max link lane count */
5105                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5106
5107                 /* Initial max link rate */
5108                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5109
5110                 intel_dp->reset_link_params = false;
5111         }
5112
5113         intel_dp_print_rates(intel_dp);
5114
5115         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5116                          drm_dp_is_branch(intel_dp->dpcd));
5117
5118         intel_dp_configure_mst(intel_dp);
5119
5120         if (intel_dp->is_mst) {
5121                 /*
5122                  * If we are in MST mode then this connector
5123                  * won't appear connected or have anything
5124                  * with EDID on it
5125                  */
5126                 status = connector_status_disconnected;
5127                 goto out;
5128         }
5129
5130         /*
5131          * Some external monitors do not signal loss of link synchronization
5132          * with an IRQ_HPD, so force a link status check.
5133          */
5134         if (!intel_dp_is_edp(intel_dp)) {
5135                 int ret;
5136
5137                 ret = intel_dp_retrain_link(encoder, ctx);
5138                 if (ret) {
5139                         intel_display_power_put(dev_priv,
5140                                                 intel_dp->aux_power_domain);
5141                         return ret;
5142                 }
5143         }
5144
5145         /*
5146          * Clearing NACK and defer counts to get their exact values
5147          * while reading EDID which are required by Compliance tests
5148          * 4.2.2.4 and 4.2.2.5
5149          */
5150         intel_dp->aux.i2c_nack_count = 0;
5151         intel_dp->aux.i2c_defer_count = 0;
5152
5153         intel_dp_set_edid(intel_dp);
5154         if (intel_dp_is_edp(intel_dp) ||
5155             to_intel_connector(connector)->detect_edid)
5156                 status = connector_status_connected;
5157
5158         intel_dp_check_service_irq(intel_dp);
5159
5160 out:
5161         if (status != connector_status_connected && !intel_dp->is_mst)
5162                 intel_dp_unset_edid(intel_dp);
5163
5164         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5165         return status;
5166 }
5167
5168 static void
5169 intel_dp_force(struct drm_connector *connector)
5170 {
5171         struct intel_dp *intel_dp = intel_attached_dp(connector);
5172         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
5173         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5174
5175         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5176                       connector->base.id, connector->name);
5177         intel_dp_unset_edid(intel_dp);
5178
5179         if (connector->status != connector_status_connected)
5180                 return;
5181
5182         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5183
5184         intel_dp_set_edid(intel_dp);
5185
5186         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5187 }
5188
5189 static int intel_dp_get_modes(struct drm_connector *connector)
5190 {
5191         struct intel_connector *intel_connector = to_intel_connector(connector);
5192         struct edid *edid;
5193
5194         edid = intel_connector->detect_edid;
5195         if (edid) {
5196                 int ret = intel_connector_update_modes(connector, edid);
5197                 if (ret)
5198                         return ret;
5199         }
5200
5201         /* if eDP has no EDID, fall back to fixed mode */
5202         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5203             intel_connector->panel.fixed_mode) {
5204                 struct drm_display_mode *mode;
5205
5206                 mode = drm_mode_duplicate(connector->dev,
5207                                           intel_connector->panel.fixed_mode);
5208                 if (mode) {
5209                         drm_mode_probed_add(connector, mode);
5210                         return 1;
5211                 }
5212         }
5213
5214         return 0;
5215 }
5216
5217 static int
5218 intel_dp_connector_register(struct drm_connector *connector)
5219 {
5220         struct intel_dp *intel_dp = intel_attached_dp(connector);
5221         struct drm_device *dev = connector->dev;
5222         int ret;
5223
5224         ret = intel_connector_register(connector);
5225         if (ret)
5226                 return ret;
5227
5228         i915_debugfs_connector_add(connector);
5229
5230         DRM_DEBUG_KMS("registering %s bus for %s\n",
5231                       intel_dp->aux.name, connector->kdev->kobj.name);
5232
5233         intel_dp->aux.dev = connector->kdev;
5234         ret = drm_dp_aux_register(&intel_dp->aux);
5235         if (!ret)
5236                 drm_dp_cec_register_connector(&intel_dp->aux,
5237                                               connector->name, dev->dev);
5238         return ret;
5239 }
5240
5241 static void
5242 intel_dp_connector_unregister(struct drm_connector *connector)
5243 {
5244         struct intel_dp *intel_dp = intel_attached_dp(connector);
5245
5246         drm_dp_cec_unregister_connector(&intel_dp->aux);
5247         drm_dp_aux_unregister(&intel_dp->aux);
5248         intel_connector_unregister(connector);
5249 }
5250
5251 static void
5252 intel_dp_connector_destroy(struct drm_connector *connector)
5253 {
5254         struct intel_connector *intel_connector = to_intel_connector(connector);
5255
5256         kfree(intel_connector->detect_edid);
5257
5258         if (!IS_ERR_OR_NULL(intel_connector->edid))
5259                 kfree(intel_connector->edid);
5260
5261         /*
5262          * Can't call intel_dp_is_edp() since the encoder may have been
5263          * destroyed already.
5264          */
5265         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5266                 intel_panel_fini(&intel_connector->panel);
5267
5268         drm_connector_cleanup(connector);
5269         kfree(connector);
5270 }
5271
5272 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5273 {
5274         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5275         struct intel_dp *intel_dp = &intel_dig_port->dp;
5276
5277         intel_dp_mst_encoder_cleanup(intel_dig_port);
5278         if (intel_dp_is_edp(intel_dp)) {
5279                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5280                 /*
5281                  * vdd might still be enabled do to the delayed vdd off.
5282                  * Make sure vdd is actually turned off here.
5283                  */
5284                 pps_lock(intel_dp);
5285                 edp_panel_vdd_off_sync(intel_dp);
5286                 pps_unlock(intel_dp);
5287
5288                 if (intel_dp->edp_notifier.notifier_call) {
5289                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5290                         intel_dp->edp_notifier.notifier_call = NULL;
5291                 }
5292         }
5293
5294         intel_dp_aux_fini(intel_dp);
5295
5296         drm_encoder_cleanup(encoder);
5297         kfree(intel_dig_port);
5298 }
5299
5300 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5301 {
5302         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5303
5304         if (!intel_dp_is_edp(intel_dp))
5305                 return;
5306
5307         /*
5308          * vdd might still be enabled do to the delayed vdd off.
5309          * Make sure vdd is actually turned off here.
5310          */
5311         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5312         pps_lock(intel_dp);
5313         edp_panel_vdd_off_sync(intel_dp);
5314         pps_unlock(intel_dp);
5315 }
5316
5317 static
5318 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5319                                 u8 *an)
5320 {
5321         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5322         static const struct drm_dp_aux_msg msg = {
5323                 .request = DP_AUX_NATIVE_WRITE,
5324                 .address = DP_AUX_HDCP_AKSV,
5325                 .size = DRM_HDCP_KSV_LEN,
5326         };
5327         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5328         ssize_t dpcd_ret;
5329         int ret;
5330
5331         /* Output An first, that's easy */
5332         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5333                                      an, DRM_HDCP_AN_LEN);
5334         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5335                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5336                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5337         }
5338
5339         /*
5340          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5341          * order to get it on the wire, we need to create the AUX header as if
5342          * we were writing the data, and then tickle the hardware to output the
5343          * data once the header is sent out.
5344          */
5345         intel_dp_aux_header(txbuf, &msg);
5346
5347         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5348                                 rxbuf, sizeof(rxbuf),
5349                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5350         if (ret < 0) {
5351                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5352                 return ret;
5353         } else if (ret == 0) {
5354                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5355                 return -EIO;
5356         }
5357
5358         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5359         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5360 }
5361
5362 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5363                                    u8 *bksv)
5364 {
5365         ssize_t ret;
5366         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5367                                DRM_HDCP_KSV_LEN);
5368         if (ret != DRM_HDCP_KSV_LEN) {
5369                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5370                 return ret >= 0 ? -EIO : ret;
5371         }
5372         return 0;
5373 }
5374
5375 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5376                                       u8 *bstatus)
5377 {
5378         ssize_t ret;
5379         /*
5380          * For some reason the HDMI and DP HDCP specs call this register
5381          * definition by different names. In the HDMI spec, it's called BSTATUS,
5382          * but in DP it's called BINFO.
5383          */
5384         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5385                                bstatus, DRM_HDCP_BSTATUS_LEN);
5386         if (ret != DRM_HDCP_BSTATUS_LEN) {
5387                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5388                 return ret >= 0 ? -EIO : ret;
5389         }
5390         return 0;
5391 }
5392
5393 static
5394 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5395                              u8 *bcaps)
5396 {
5397         ssize_t ret;
5398
5399         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5400                                bcaps, 1);
5401         if (ret != 1) {
5402                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5403                 return ret >= 0 ? -EIO : ret;
5404         }
5405
5406         return 0;
5407 }
5408
5409 static
5410 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5411                                    bool *repeater_present)
5412 {
5413         ssize_t ret;
5414         u8 bcaps;
5415
5416         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5417         if (ret)
5418                 return ret;
5419
5420         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5421         return 0;
5422 }
5423
5424 static
5425 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5426                                 u8 *ri_prime)
5427 {
5428         ssize_t ret;
5429         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5430                                ri_prime, DRM_HDCP_RI_LEN);
5431         if (ret != DRM_HDCP_RI_LEN) {
5432                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5433                 return ret >= 0 ? -EIO : ret;
5434         }
5435         return 0;
5436 }
5437
5438 static
5439 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5440                                  bool *ksv_ready)
5441 {
5442         ssize_t ret;
5443         u8 bstatus;
5444         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5445                                &bstatus, 1);
5446         if (ret != 1) {
5447                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5448                 return ret >= 0 ? -EIO : ret;
5449         }
5450         *ksv_ready = bstatus & DP_BSTATUS_READY;
5451         return 0;
5452 }
5453
5454 static
5455 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5456                                 int num_downstream, u8 *ksv_fifo)
5457 {
5458         ssize_t ret;
5459         int i;
5460
5461         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5462         for (i = 0; i < num_downstream; i += 3) {
5463                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5464                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5465                                        DP_AUX_HDCP_KSV_FIFO,
5466                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5467                                        len);
5468                 if (ret != len) {
5469                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5470                                   ret);
5471                         return ret >= 0 ? -EIO : ret;
5472                 }
5473         }
5474         return 0;
5475 }
5476
5477 static
5478 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5479                                     int i, u32 *part)
5480 {
5481         ssize_t ret;
5482
5483         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5484                 return -EINVAL;
5485
5486         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5487                                DP_AUX_HDCP_V_PRIME(i), part,
5488                                DRM_HDCP_V_PRIME_PART_LEN);
5489         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5490                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5491                 return ret >= 0 ? -EIO : ret;
5492         }
5493         return 0;
5494 }
5495
5496 static
5497 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5498                                     bool enable)
5499 {
5500         /* Not used for single stream DisplayPort setups */
5501         return 0;
5502 }
5503
5504 static
5505 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5506 {
5507         ssize_t ret;
5508         u8 bstatus;
5509
5510         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5511                                &bstatus, 1);
5512         if (ret != 1) {
5513                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5514                 return false;
5515         }
5516
5517         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5518 }
5519
5520 static
5521 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5522                           bool *hdcp_capable)
5523 {
5524         ssize_t ret;
5525         u8 bcaps;
5526
5527         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5528         if (ret)
5529                 return ret;
5530
5531         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5532         return 0;
5533 }
5534
5535 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5536         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5537         .read_bksv = intel_dp_hdcp_read_bksv,
5538         .read_bstatus = intel_dp_hdcp_read_bstatus,
5539         .repeater_present = intel_dp_hdcp_repeater_present,
5540         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5541         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5542         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5543         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5544         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5545         .check_link = intel_dp_hdcp_check_link,
5546         .hdcp_capable = intel_dp_hdcp_capable,
5547 };
5548
5549 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5550 {
5551         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5552
5553         lockdep_assert_held(&dev_priv->pps_mutex);
5554
5555         if (!edp_have_panel_vdd(intel_dp))
5556                 return;
5557
5558         /*
5559          * The VDD bit needs a power domain reference, so if the bit is
5560          * already enabled when we boot or resume, grab this reference and
5561          * schedule a vdd off, so we don't hold on to the reference
5562          * indefinitely.
5563          */
5564         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5565         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5566
5567         edp_panel_vdd_schedule_off(intel_dp);
5568 }
5569
5570 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5571 {
5572         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5573         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5574         enum pipe pipe;
5575
5576         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5577                                   encoder->port, &pipe))
5578                 return pipe;
5579
5580         return INVALID_PIPE;
5581 }
5582
5583 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5584 {
5585         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5586         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5587         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5588
5589         if (!HAS_DDI(dev_priv))
5590                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5591
5592         if (lspcon->active)
5593                 lspcon_resume(lspcon);
5594
5595         intel_dp->reset_link_params = true;
5596
5597         pps_lock(intel_dp);
5598
5599         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5600                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5601
5602         if (intel_dp_is_edp(intel_dp)) {
5603                 /* Reinit the power sequencer, in case BIOS did something with it. */
5604                 intel_dp_pps_init(intel_dp);
5605                 intel_edp_panel_vdd_sanitize(intel_dp);
5606         }
5607
5608         pps_unlock(intel_dp);
5609 }
5610
5611 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5612         .force = intel_dp_force,
5613         .fill_modes = drm_helper_probe_single_connector_modes,
5614         .atomic_get_property = intel_digital_connector_atomic_get_property,
5615         .atomic_set_property = intel_digital_connector_atomic_set_property,
5616         .late_register = intel_dp_connector_register,
5617         .early_unregister = intel_dp_connector_unregister,
5618         .destroy = intel_dp_connector_destroy,
5619         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5620         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5621 };
5622
5623 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5624         .detect_ctx = intel_dp_detect,
5625         .get_modes = intel_dp_get_modes,
5626         .mode_valid = intel_dp_mode_valid,
5627         .atomic_check = intel_digital_connector_atomic_check,
5628 };
5629
5630 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5631         .reset = intel_dp_encoder_reset,
5632         .destroy = intel_dp_encoder_destroy,
5633 };
5634
5635 enum irqreturn
5636 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5637 {
5638         struct intel_dp *intel_dp = &intel_dig_port->dp;
5639         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5640         enum irqreturn ret = IRQ_NONE;
5641
5642         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5643                 /*
5644                  * vdd off can generate a long pulse on eDP which
5645                  * would require vdd on to handle it, and thus we
5646                  * would end up in an endless cycle of
5647                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5648                  */
5649                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5650                               port_name(intel_dig_port->base.port));
5651                 return IRQ_HANDLED;
5652         }
5653
5654         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5655                       port_name(intel_dig_port->base.port),
5656                       long_hpd ? "long" : "short");
5657
5658         if (long_hpd) {
5659                 intel_dp->reset_link_params = true;
5660                 return IRQ_NONE;
5661         }
5662
5663         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5664
5665         if (intel_dp->is_mst) {
5666                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5667                         /*
5668                          * If we were in MST mode, and device is not
5669                          * there, get out of MST mode
5670                          */
5671                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5672                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5673                         intel_dp->is_mst = false;
5674                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5675                                                         intel_dp->is_mst);
5676                         goto put_power;
5677                 }
5678         }
5679
5680         if (!intel_dp->is_mst) {
5681                 bool handled;
5682
5683                 handled = intel_dp_short_pulse(intel_dp);
5684
5685                 /* Short pulse can signify loss of hdcp authentication */
5686                 intel_hdcp_check_link(intel_dp->attached_connector);
5687
5688                 if (!handled)
5689                         goto put_power;
5690         }
5691
5692         ret = IRQ_HANDLED;
5693
5694 put_power:
5695         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5696
5697         return ret;
5698 }
5699
5700 /* check the VBT to see whether the eDP is on another port */
5701 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5702 {
5703         /*
5704          * eDP not supported on g4x. so bail out early just
5705          * for a bit extra safety in case the VBT is bonkers.
5706          */
5707         if (INTEL_GEN(dev_priv) < 5)
5708                 return false;
5709
5710         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5711                 return true;
5712
5713         return intel_bios_is_port_edp(dev_priv, port);
5714 }
5715
5716 static void
5717 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5718 {
5719         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5720         enum port port = dp_to_dig_port(intel_dp)->base.port;
5721
5722         if (!IS_G4X(dev_priv) && port != PORT_A)
5723                 intel_attach_force_audio_property(connector);
5724
5725         intel_attach_broadcast_rgb_property(connector);
5726
5727         if (intel_dp_is_edp(intel_dp)) {
5728                 u32 allowed_scalers;
5729
5730                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5731                 if (!HAS_GMCH_DISPLAY(dev_priv))
5732                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5733
5734                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5735
5736                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5737
5738         }
5739 }
5740
5741 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5742 {
5743         intel_dp->panel_power_off_time = ktime_get_boottime();
5744         intel_dp->last_power_on = jiffies;
5745         intel_dp->last_backlight_off = jiffies;
5746 }
5747
5748 static void
5749 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5750 {
5751         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5752         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5753         struct pps_registers regs;
5754
5755         intel_pps_get_registers(intel_dp, &regs);
5756
5757         /* Workaround: Need to write PP_CONTROL with the unlock key as
5758          * the very first thing. */
5759         pp_ctl = ironlake_get_pp_control(intel_dp);
5760
5761         pp_on = I915_READ(regs.pp_on);
5762         pp_off = I915_READ(regs.pp_off);
5763         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5764             !HAS_PCH_ICP(dev_priv)) {
5765                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5766                 pp_div = I915_READ(regs.pp_div);
5767         }
5768
5769         /* Pull timing values out of registers */
5770         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5771                      PANEL_POWER_UP_DELAY_SHIFT;
5772
5773         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5774                   PANEL_LIGHT_ON_DELAY_SHIFT;
5775
5776         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5777                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5778
5779         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5780                    PANEL_POWER_DOWN_DELAY_SHIFT;
5781
5782         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5783             HAS_PCH_ICP(dev_priv)) {
5784                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5785                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5786         } else {
5787                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5788                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5789         }
5790 }
5791
5792 static void
5793 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5794 {
5795         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5796                       state_name,
5797                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5798 }
5799
5800 static void
5801 intel_pps_verify_state(struct intel_dp *intel_dp)
5802 {
5803         struct edp_power_seq hw;
5804         struct edp_power_seq *sw = &intel_dp->pps_delays;
5805
5806         intel_pps_readout_hw_state(intel_dp, &hw);
5807
5808         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5809             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5810                 DRM_ERROR("PPS state mismatch\n");
5811                 intel_pps_dump_state("sw", sw);
5812                 intel_pps_dump_state("hw", &hw);
5813         }
5814 }
5815
5816 static void
5817 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5818 {
5819         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5820         struct edp_power_seq cur, vbt, spec,
5821                 *final = &intel_dp->pps_delays;
5822
5823         lockdep_assert_held(&dev_priv->pps_mutex);
5824
5825         /* already initialized? */
5826         if (final->t11_t12 != 0)
5827                 return;
5828
5829         intel_pps_readout_hw_state(intel_dp, &cur);
5830
5831         intel_pps_dump_state("cur", &cur);
5832
5833         vbt = dev_priv->vbt.edp.pps;
5834         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5835          * of 500ms appears to be too short. Ocassionally the panel
5836          * just fails to power back on. Increasing the delay to 800ms
5837          * seems sufficient to avoid this problem.
5838          */
5839         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5840                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5841                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5842                               vbt.t11_t12);
5843         }
5844         /* T11_T12 delay is special and actually in units of 100ms, but zero
5845          * based in the hw (so we need to add 100 ms). But the sw vbt
5846          * table multiplies it with 1000 to make it in units of 100usec,
5847          * too. */
5848         vbt.t11_t12 += 100 * 10;
5849
5850         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5851          * our hw here, which are all in 100usec. */
5852         spec.t1_t3 = 210 * 10;
5853         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5854         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5855         spec.t10 = 500 * 10;
5856         /* This one is special and actually in units of 100ms, but zero
5857          * based in the hw (so we need to add 100 ms). But the sw vbt
5858          * table multiplies it with 1000 to make it in units of 100usec,
5859          * too. */
5860         spec.t11_t12 = (510 + 100) * 10;
5861
5862         intel_pps_dump_state("vbt", &vbt);
5863
5864         /* Use the max of the register settings and vbt. If both are
5865          * unset, fall back to the spec limits. */
5866 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5867                                        spec.field : \
5868                                        max(cur.field, vbt.field))
5869         assign_final(t1_t3);
5870         assign_final(t8);
5871         assign_final(t9);
5872         assign_final(t10);
5873         assign_final(t11_t12);
5874 #undef assign_final
5875
5876 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5877         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5878         intel_dp->backlight_on_delay = get_delay(t8);
5879         intel_dp->backlight_off_delay = get_delay(t9);
5880         intel_dp->panel_power_down_delay = get_delay(t10);
5881         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5882 #undef get_delay
5883
5884         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5885                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5886                       intel_dp->panel_power_cycle_delay);
5887
5888         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5889                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5890
5891         /*
5892          * We override the HW backlight delays to 1 because we do manual waits
5893          * on them. For T8, even BSpec recommends doing it. For T9, if we
5894          * don't do this, we'll end up waiting for the backlight off delay
5895          * twice: once when we do the manual sleep, and once when we disable
5896          * the panel and wait for the PP_STATUS bit to become zero.
5897          */
5898         final->t8 = 1;
5899         final->t9 = 1;
5900
5901         /*
5902          * HW has only a 100msec granularity for t11_t12 so round it up
5903          * accordingly.
5904          */
5905         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5906 }
5907
5908 static void
5909 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5910                                               bool force_disable_vdd)
5911 {
5912         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5913         u32 pp_on, pp_off, pp_div, port_sel = 0;
5914         int div = dev_priv->rawclk_freq / 1000;
5915         struct pps_registers regs;
5916         enum port port = dp_to_dig_port(intel_dp)->base.port;
5917         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5918
5919         lockdep_assert_held(&dev_priv->pps_mutex);
5920
5921         intel_pps_get_registers(intel_dp, &regs);
5922
5923         /*
5924          * On some VLV machines the BIOS can leave the VDD
5925          * enabled even on power sequencers which aren't
5926          * hooked up to any port. This would mess up the
5927          * power domain tracking the first time we pick
5928          * one of these power sequencers for use since
5929          * edp_panel_vdd_on() would notice that the VDD was
5930          * already on and therefore wouldn't grab the power
5931          * domain reference. Disable VDD first to avoid this.
5932          * This also avoids spuriously turning the VDD on as
5933          * soon as the new power sequencer gets initialized.
5934          */
5935         if (force_disable_vdd) {
5936                 u32 pp = ironlake_get_pp_control(intel_dp);
5937
5938                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5939
5940                 if (pp & EDP_FORCE_VDD)
5941                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5942
5943                 pp &= ~EDP_FORCE_VDD;
5944
5945                 I915_WRITE(regs.pp_ctrl, pp);
5946         }
5947
5948         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5949                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5950         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5951                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5952         /* Compute the divisor for the pp clock, simply match the Bspec
5953          * formula. */
5954         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5955             HAS_PCH_ICP(dev_priv)) {
5956                 pp_div = I915_READ(regs.pp_ctrl);
5957                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5958                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5959                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5960         } else {
5961                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5962                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5963                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5964         }
5965
5966         /* Haswell doesn't have any port selection bits for the panel
5967          * power sequencer any more. */
5968         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5969                 port_sel = PANEL_PORT_SELECT_VLV(port);
5970         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5971                 switch (port) {
5972                 case PORT_A:
5973                         port_sel = PANEL_PORT_SELECT_DPA;
5974                         break;
5975                 case PORT_C:
5976                         port_sel = PANEL_PORT_SELECT_DPC;
5977                         break;
5978                 case PORT_D:
5979                         port_sel = PANEL_PORT_SELECT_DPD;
5980                         break;
5981                 default:
5982                         MISSING_CASE(port);
5983                         break;
5984                 }
5985         }
5986
5987         pp_on |= port_sel;
5988
5989         I915_WRITE(regs.pp_on, pp_on);
5990         I915_WRITE(regs.pp_off, pp_off);
5991         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5992             HAS_PCH_ICP(dev_priv))
5993                 I915_WRITE(regs.pp_ctrl, pp_div);
5994         else
5995                 I915_WRITE(regs.pp_div, pp_div);
5996
5997         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5998                       I915_READ(regs.pp_on),
5999                       I915_READ(regs.pp_off),
6000                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
6001                        HAS_PCH_ICP(dev_priv)) ?
6002                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6003                       I915_READ(regs.pp_div));
6004 }
6005
6006 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6007 {
6008         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6009
6010         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6011                 vlv_initial_power_sequencer_setup(intel_dp);
6012         } else {
6013                 intel_dp_init_panel_power_sequencer(intel_dp);
6014                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6015         }
6016 }
6017
6018 /**
6019  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6020  * @dev_priv: i915 device
6021  * @crtc_state: a pointer to the active intel_crtc_state
6022  * @refresh_rate: RR to be programmed
6023  *
6024  * This function gets called when refresh rate (RR) has to be changed from
6025  * one frequency to another. Switches can be between high and low RR
6026  * supported by the panel or to any other RR based on media playback (in
6027  * this case, RR value needs to be passed from user space).
6028  *
6029  * The caller of this function needs to take a lock on dev_priv->drrs.
6030  */
6031 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6032                                     const struct intel_crtc_state *crtc_state,
6033                                     int refresh_rate)
6034 {
6035         struct intel_encoder *encoder;
6036         struct intel_digital_port *dig_port = NULL;
6037         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6039         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6040
6041         if (refresh_rate <= 0) {
6042                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6043                 return;
6044         }
6045
6046         if (intel_dp == NULL) {
6047                 DRM_DEBUG_KMS("DRRS not supported.\n");
6048                 return;
6049         }
6050
6051         dig_port = dp_to_dig_port(intel_dp);
6052         encoder = &dig_port->base;
6053
6054         if (!intel_crtc) {
6055                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6056                 return;
6057         }
6058
6059         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6060                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6061                 return;
6062         }
6063
6064         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6065                         refresh_rate)
6066                 index = DRRS_LOW_RR;
6067
6068         if (index == dev_priv->drrs.refresh_rate_type) {
6069                 DRM_DEBUG_KMS(
6070                         "DRRS requested for previously set RR...ignoring\n");
6071                 return;
6072         }
6073
6074         if (!crtc_state->base.active) {
6075                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6076                 return;
6077         }
6078
6079         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6080                 switch (index) {
6081                 case DRRS_HIGH_RR:
6082                         intel_dp_set_m_n(intel_crtc, M1_N1);
6083                         break;
6084                 case DRRS_LOW_RR:
6085                         intel_dp_set_m_n(intel_crtc, M2_N2);
6086                         break;
6087                 case DRRS_MAX_RR:
6088                 default:
6089                         DRM_ERROR("Unsupported refreshrate type\n");
6090                 }
6091         } else if (INTEL_GEN(dev_priv) > 6) {
6092                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6093                 u32 val;
6094
6095                 val = I915_READ(reg);
6096                 if (index > DRRS_HIGH_RR) {
6097                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6098                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6099                         else
6100                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6101                 } else {
6102                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6103                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6104                         else
6105                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6106                 }
6107                 I915_WRITE(reg, val);
6108         }
6109
6110         dev_priv->drrs.refresh_rate_type = index;
6111
6112         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6113 }
6114
6115 /**
6116  * intel_edp_drrs_enable - init drrs struct if supported
6117  * @intel_dp: DP struct
6118  * @crtc_state: A pointer to the active crtc state.
6119  *
6120  * Initializes frontbuffer_bits and drrs.dp
6121  */
6122 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6123                            const struct intel_crtc_state *crtc_state)
6124 {
6125         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6126
6127         if (!crtc_state->has_drrs) {
6128                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6129                 return;
6130         }
6131
6132         if (dev_priv->psr.enabled) {
6133                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6134                 return;
6135         }
6136
6137         mutex_lock(&dev_priv->drrs.mutex);
6138         if (WARN_ON(dev_priv->drrs.dp)) {
6139                 DRM_ERROR("DRRS already enabled\n");
6140                 goto unlock;
6141         }
6142
6143         dev_priv->drrs.busy_frontbuffer_bits = 0;
6144
6145         dev_priv->drrs.dp = intel_dp;
6146
6147 unlock:
6148         mutex_unlock(&dev_priv->drrs.mutex);
6149 }
6150
6151 /**
6152  * intel_edp_drrs_disable - Disable DRRS
6153  * @intel_dp: DP struct
6154  * @old_crtc_state: Pointer to old crtc_state.
6155  *
6156  */
6157 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6158                             const struct intel_crtc_state *old_crtc_state)
6159 {
6160         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6161
6162         if (!old_crtc_state->has_drrs)
6163                 return;
6164
6165         mutex_lock(&dev_priv->drrs.mutex);
6166         if (!dev_priv->drrs.dp) {
6167                 mutex_unlock(&dev_priv->drrs.mutex);
6168                 return;
6169         }
6170
6171         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6172                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6173                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6174
6175         dev_priv->drrs.dp = NULL;
6176         mutex_unlock(&dev_priv->drrs.mutex);
6177
6178         cancel_delayed_work_sync(&dev_priv->drrs.work);
6179 }
6180
6181 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6182 {
6183         struct drm_i915_private *dev_priv =
6184                 container_of(work, typeof(*dev_priv), drrs.work.work);
6185         struct intel_dp *intel_dp;
6186
6187         mutex_lock(&dev_priv->drrs.mutex);
6188
6189         intel_dp = dev_priv->drrs.dp;
6190
6191         if (!intel_dp)
6192                 goto unlock;
6193
6194         /*
6195          * The delayed work can race with an invalidate hence we need to
6196          * recheck.
6197          */
6198
6199         if (dev_priv->drrs.busy_frontbuffer_bits)
6200                 goto unlock;
6201
6202         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6203                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6204
6205                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6206                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6207         }
6208
6209 unlock:
6210         mutex_unlock(&dev_priv->drrs.mutex);
6211 }
6212
6213 /**
6214  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6215  * @dev_priv: i915 device
6216  * @frontbuffer_bits: frontbuffer plane tracking bits
6217  *
6218  * This function gets called everytime rendering on the given planes start.
6219  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6220  *
6221  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6222  */
6223 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6224                                unsigned int frontbuffer_bits)
6225 {
6226         struct drm_crtc *crtc;
6227         enum pipe pipe;
6228
6229         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6230                 return;
6231
6232         cancel_delayed_work(&dev_priv->drrs.work);
6233
6234         mutex_lock(&dev_priv->drrs.mutex);
6235         if (!dev_priv->drrs.dp) {
6236                 mutex_unlock(&dev_priv->drrs.mutex);
6237                 return;
6238         }
6239
6240         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6241         pipe = to_intel_crtc(crtc)->pipe;
6242
6243         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6244         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6245
6246         /* invalidate means busy screen hence upclock */
6247         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6248                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6249                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6250
6251         mutex_unlock(&dev_priv->drrs.mutex);
6252 }
6253
6254 /**
6255  * intel_edp_drrs_flush - Restart Idleness DRRS
6256  * @dev_priv: i915 device
6257  * @frontbuffer_bits: frontbuffer plane tracking bits
6258  *
6259  * This function gets called every time rendering on the given planes has
6260  * completed or flip on a crtc is completed. So DRRS should be upclocked
6261  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6262  * if no other planes are dirty.
6263  *
6264  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6265  */
6266 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6267                           unsigned int frontbuffer_bits)
6268 {
6269         struct drm_crtc *crtc;
6270         enum pipe pipe;
6271
6272         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6273                 return;
6274
6275         cancel_delayed_work(&dev_priv->drrs.work);
6276
6277         mutex_lock(&dev_priv->drrs.mutex);
6278         if (!dev_priv->drrs.dp) {
6279                 mutex_unlock(&dev_priv->drrs.mutex);
6280                 return;
6281         }
6282
6283         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6284         pipe = to_intel_crtc(crtc)->pipe;
6285
6286         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6287         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6288
6289         /* flush means busy screen hence upclock */
6290         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6291                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6292                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6293
6294         /*
6295          * flush also means no more activity hence schedule downclock, if all
6296          * other fbs are quiescent too
6297          */
6298         if (!dev_priv->drrs.busy_frontbuffer_bits)
6299                 schedule_delayed_work(&dev_priv->drrs.work,
6300                                 msecs_to_jiffies(1000));
6301         mutex_unlock(&dev_priv->drrs.mutex);
6302 }
6303
6304 /**
6305  * DOC: Display Refresh Rate Switching (DRRS)
6306  *
6307  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6308  * which enables swtching between low and high refresh rates,
6309  * dynamically, based on the usage scenario. This feature is applicable
6310  * for internal panels.
6311  *
6312  * Indication that the panel supports DRRS is given by the panel EDID, which
6313  * would list multiple refresh rates for one resolution.
6314  *
6315  * DRRS is of 2 types - static and seamless.
6316  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6317  * (may appear as a blink on screen) and is used in dock-undock scenario.
6318  * Seamless DRRS involves changing RR without any visual effect to the user
6319  * and can be used during normal system usage. This is done by programming
6320  * certain registers.
6321  *
6322  * Support for static/seamless DRRS may be indicated in the VBT based on
6323  * inputs from the panel spec.
6324  *
6325  * DRRS saves power by switching to low RR based on usage scenarios.
6326  *
6327  * The implementation is based on frontbuffer tracking implementation.  When
6328  * there is a disturbance on the screen triggered by user activity or a periodic
6329  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6330  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6331  * made.
6332  *
6333  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6334  * and intel_edp_drrs_flush() are called.
6335  *
6336  * DRRS can be further extended to support other internal panels and also
6337  * the scenario of video playback wherein RR is set based on the rate
6338  * requested by userspace.
6339  */
6340
6341 /**
6342  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6343  * @connector: eDP connector
6344  * @fixed_mode: preferred mode of panel
6345  *
6346  * This function is  called only once at driver load to initialize basic
6347  * DRRS stuff.
6348  *
6349  * Returns:
6350  * Downclock mode if panel supports it, else return NULL.
6351  * DRRS support is determined by the presence of downclock mode (apart
6352  * from VBT setting).
6353  */
6354 static struct drm_display_mode *
6355 intel_dp_drrs_init(struct intel_connector *connector,
6356                    struct drm_display_mode *fixed_mode)
6357 {
6358         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6359         struct drm_display_mode *downclock_mode = NULL;
6360
6361         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6362         mutex_init(&dev_priv->drrs.mutex);
6363
6364         if (INTEL_GEN(dev_priv) <= 6) {
6365                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6366                 return NULL;
6367         }
6368
6369         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6370                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6371                 return NULL;
6372         }
6373
6374         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6375                                                     &connector->base);
6376
6377         if (!downclock_mode) {
6378                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6379                 return NULL;
6380         }
6381
6382         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6383
6384         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6385         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6386         return downclock_mode;
6387 }
6388
6389 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6390                                      struct intel_connector *intel_connector)
6391 {
6392         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6393         struct drm_device *dev = &dev_priv->drm;
6394         struct drm_connector *connector = &intel_connector->base;
6395         struct drm_display_mode *fixed_mode = NULL;
6396         struct drm_display_mode *downclock_mode = NULL;
6397         bool has_dpcd;
6398         struct drm_display_mode *scan;
6399         struct edid *edid;
6400         enum pipe pipe = INVALID_PIPE;
6401
6402         if (!intel_dp_is_edp(intel_dp))
6403                 return true;
6404
6405         /*
6406          * On IBX/CPT we may get here with LVDS already registered. Since the
6407          * driver uses the only internal power sequencer available for both
6408          * eDP and LVDS bail out early in this case to prevent interfering
6409          * with an already powered-on LVDS power sequencer.
6410          */
6411         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6412                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6413                 DRM_INFO("LVDS was detected, not registering eDP\n");
6414
6415                 return false;
6416         }
6417
6418         pps_lock(intel_dp);
6419
6420         intel_dp_init_panel_power_timestamps(intel_dp);
6421         intel_dp_pps_init(intel_dp);
6422         intel_edp_panel_vdd_sanitize(intel_dp);
6423
6424         pps_unlock(intel_dp);
6425
6426         /* Cache DPCD and EDID for edp. */
6427         has_dpcd = intel_edp_init_dpcd(intel_dp);
6428
6429         if (!has_dpcd) {
6430                 /* if this fails, presume the device is a ghost */
6431                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6432                 goto out_vdd_off;
6433         }
6434
6435         mutex_lock(&dev->mode_config.mutex);
6436         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6437         if (edid) {
6438                 if (drm_add_edid_modes(connector, edid)) {
6439                         drm_connector_update_edid_property(connector,
6440                                                                 edid);
6441                 } else {
6442                         kfree(edid);
6443                         edid = ERR_PTR(-EINVAL);
6444                 }
6445         } else {
6446                 edid = ERR_PTR(-ENOENT);
6447         }
6448         intel_connector->edid = edid;
6449
6450         /* prefer fixed mode from EDID if available */
6451         list_for_each_entry(scan, &connector->probed_modes, head) {
6452                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6453                         fixed_mode = drm_mode_duplicate(dev, scan);
6454                         downclock_mode = intel_dp_drrs_init(
6455                                                 intel_connector, fixed_mode);
6456                         break;
6457                 }
6458         }
6459
6460         /* fallback to VBT if available for eDP */
6461         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6462                 fixed_mode = drm_mode_duplicate(dev,
6463                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6464                 if (fixed_mode) {
6465                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6466                         connector->display_info.width_mm = fixed_mode->width_mm;
6467                         connector->display_info.height_mm = fixed_mode->height_mm;
6468                 }
6469         }
6470         mutex_unlock(&dev->mode_config.mutex);
6471
6472         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6473                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6474                 register_reboot_notifier(&intel_dp->edp_notifier);
6475
6476                 /*
6477                  * Figure out the current pipe for the initial backlight setup.
6478                  * If the current pipe isn't valid, try the PPS pipe, and if that
6479                  * fails just assume pipe A.
6480                  */
6481                 pipe = vlv_active_pipe(intel_dp);
6482
6483                 if (pipe != PIPE_A && pipe != PIPE_B)
6484                         pipe = intel_dp->pps_pipe;
6485
6486                 if (pipe != PIPE_A && pipe != PIPE_B)
6487                         pipe = PIPE_A;
6488
6489                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6490                               pipe_name(pipe));
6491         }
6492
6493         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6494         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6495         intel_panel_setup_backlight(connector, pipe);
6496
6497         if (fixed_mode)
6498                 drm_connector_init_panel_orientation_property(
6499                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6500
6501         return true;
6502
6503 out_vdd_off:
6504         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6505         /*
6506          * vdd might still be enabled do to the delayed vdd off.
6507          * Make sure vdd is actually turned off here.
6508          */
6509         pps_lock(intel_dp);
6510         edp_panel_vdd_off_sync(intel_dp);
6511         pps_unlock(intel_dp);
6512
6513         return false;
6514 }
6515
6516 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6517 {
6518         struct intel_connector *intel_connector;
6519         struct drm_connector *connector;
6520
6521         intel_connector = container_of(work, typeof(*intel_connector),
6522                                        modeset_retry_work);
6523         connector = &intel_connector->base;
6524         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6525                       connector->name);
6526
6527         /* Grab the locks before changing connector property*/
6528         mutex_lock(&connector->dev->mode_config.mutex);
6529         /* Set connector link status to BAD and send a Uevent to notify
6530          * userspace to do a modeset.
6531          */
6532         drm_connector_set_link_status_property(connector,
6533                                                DRM_MODE_LINK_STATUS_BAD);
6534         mutex_unlock(&connector->dev->mode_config.mutex);
6535         /* Send Hotplug uevent so userspace can reprobe */
6536         drm_kms_helper_hotplug_event(connector->dev);
6537 }
6538
6539 bool
6540 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6541                         struct intel_connector *intel_connector)
6542 {
6543         struct drm_connector *connector = &intel_connector->base;
6544         struct intel_dp *intel_dp = &intel_dig_port->dp;
6545         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6546         struct drm_device *dev = intel_encoder->base.dev;
6547         struct drm_i915_private *dev_priv = to_i915(dev);
6548         enum port port = intel_encoder->port;
6549         int type;
6550
6551         /* Initialize the work for modeset in case of link train failure */
6552         INIT_WORK(&intel_connector->modeset_retry_work,
6553                   intel_dp_modeset_retry_work_fn);
6554
6555         if (WARN(intel_dig_port->max_lanes < 1,
6556                  "Not enough lanes (%d) for DP on port %c\n",
6557                  intel_dig_port->max_lanes, port_name(port)))
6558                 return false;
6559
6560         intel_dp_set_source_rates(intel_dp);
6561
6562         intel_dp->reset_link_params = true;
6563         intel_dp->pps_pipe = INVALID_PIPE;
6564         intel_dp->active_pipe = INVALID_PIPE;
6565
6566         /* intel_dp vfuncs */
6567         if (HAS_DDI(dev_priv))
6568                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6569
6570         /* Preserve the current hw state. */
6571         intel_dp->DP = I915_READ(intel_dp->output_reg);
6572         intel_dp->attached_connector = intel_connector;
6573
6574         if (intel_dp_is_port_edp(dev_priv, port))
6575                 type = DRM_MODE_CONNECTOR_eDP;
6576         else
6577                 type = DRM_MODE_CONNECTOR_DisplayPort;
6578
6579         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6580                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6581
6582         /*
6583          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6584          * for DP the encoder type can be set by the caller to
6585          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6586          */
6587         if (type == DRM_MODE_CONNECTOR_eDP)
6588                 intel_encoder->type = INTEL_OUTPUT_EDP;
6589
6590         /* eDP only on port B and/or C on vlv/chv */
6591         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6592                     intel_dp_is_edp(intel_dp) &&
6593                     port != PORT_B && port != PORT_C))
6594                 return false;
6595
6596         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6597                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6598                         port_name(port));
6599
6600         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6601         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6602
6603         if (!HAS_GMCH_DISPLAY(dev_priv))
6604                 connector->interlace_allowed = true;
6605         connector->doublescan_allowed = 0;
6606
6607         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6608
6609         intel_dp_aux_init(intel_dp);
6610
6611         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6612                           edp_panel_vdd_work);
6613
6614         intel_connector_attach_encoder(intel_connector, intel_encoder);
6615
6616         if (HAS_DDI(dev_priv))
6617                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6618         else
6619                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6620
6621         /* init MST on ports that can support it */
6622         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6623             (port == PORT_B || port == PORT_C ||
6624              port == PORT_D || port == PORT_F))
6625                 intel_dp_mst_encoder_init(intel_dig_port,
6626                                           intel_connector->base.base.id);
6627
6628         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6629                 intel_dp_aux_fini(intel_dp);
6630                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6631                 goto fail;
6632         }
6633
6634         intel_dp_add_properties(intel_dp, connector);
6635
6636         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6637                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6638                 if (ret)
6639                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6640         }
6641
6642         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6643          * 0xd.  Failure to do so will result in spurious interrupts being
6644          * generated on the port when a cable is not attached.
6645          */
6646         if (IS_G45(dev_priv)) {
6647                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6648                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6649         }
6650
6651         return true;
6652
6653 fail:
6654         drm_connector_cleanup(connector);
6655
6656         return false;
6657 }
6658
6659 bool intel_dp_init(struct drm_i915_private *dev_priv,
6660                    i915_reg_t output_reg,
6661                    enum port port)
6662 {
6663         struct intel_digital_port *intel_dig_port;
6664         struct intel_encoder *intel_encoder;
6665         struct drm_encoder *encoder;
6666         struct intel_connector *intel_connector;
6667
6668         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6669         if (!intel_dig_port)
6670                 return false;
6671
6672         intel_connector = intel_connector_alloc();
6673         if (!intel_connector)
6674                 goto err_connector_alloc;
6675
6676         intel_encoder = &intel_dig_port->base;
6677         encoder = &intel_encoder->base;
6678
6679         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6680                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6681                              "DP %c", port_name(port)))
6682                 goto err_encoder_init;
6683
6684         intel_encoder->hotplug = intel_dp_hotplug;
6685         intel_encoder->compute_config = intel_dp_compute_config;
6686         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6687         intel_encoder->get_config = intel_dp_get_config;
6688         intel_encoder->suspend = intel_dp_encoder_suspend;
6689         if (IS_CHERRYVIEW(dev_priv)) {
6690                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6691                 intel_encoder->pre_enable = chv_pre_enable_dp;
6692                 intel_encoder->enable = vlv_enable_dp;
6693                 intel_encoder->disable = vlv_disable_dp;
6694                 intel_encoder->post_disable = chv_post_disable_dp;
6695                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6696         } else if (IS_VALLEYVIEW(dev_priv)) {
6697                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6698                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6699                 intel_encoder->enable = vlv_enable_dp;
6700                 intel_encoder->disable = vlv_disable_dp;
6701                 intel_encoder->post_disable = vlv_post_disable_dp;
6702         } else {
6703                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6704                 intel_encoder->enable = g4x_enable_dp;
6705                 intel_encoder->disable = g4x_disable_dp;
6706                 intel_encoder->post_disable = g4x_post_disable_dp;
6707         }
6708
6709         intel_dig_port->dp.output_reg = output_reg;
6710         intel_dig_port->max_lanes = 4;
6711
6712         intel_encoder->type = INTEL_OUTPUT_DP;
6713         intel_encoder->power_domain = intel_port_to_power_domain(port);
6714         if (IS_CHERRYVIEW(dev_priv)) {
6715                 if (port == PORT_D)
6716                         intel_encoder->crtc_mask = 1 << 2;
6717                 else
6718                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6719         } else {
6720                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6721         }
6722         intel_encoder->cloneable = 0;
6723         intel_encoder->port = port;
6724
6725         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6726
6727         if (port != PORT_A)
6728                 intel_infoframe_init(intel_dig_port);
6729
6730         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6731                 goto err_init_connector;
6732
6733         return true;
6734
6735 err_init_connector:
6736         drm_encoder_cleanup(encoder);
6737 err_encoder_init:
6738         kfree(intel_connector);
6739 err_connector_alloc:
6740         kfree(intel_dig_port);
6741         return false;
6742 }
6743
6744 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6745 {
6746         struct intel_encoder *encoder;
6747
6748         for_each_intel_encoder(&dev_priv->drm, encoder) {
6749                 struct intel_dp *intel_dp;
6750
6751                 if (encoder->type != INTEL_OUTPUT_DDI)
6752                         continue;
6753
6754                 intel_dp = enc_to_intel_dp(&encoder->base);
6755
6756                 if (!intel_dp->can_mst)
6757                         continue;
6758
6759                 if (intel_dp->is_mst)
6760                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6761         }
6762 }
6763
6764 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6765 {
6766         struct intel_encoder *encoder;
6767
6768         for_each_intel_encoder(&dev_priv->drm, encoder) {
6769                 struct intel_dp *intel_dp;
6770                 int ret;
6771
6772                 if (encoder->type != INTEL_OUTPUT_DDI)
6773                         continue;
6774
6775                 intel_dp = enc_to_intel_dp(&encoder->base);
6776
6777                 if (!intel_dp->can_mst)
6778                         continue;
6779
6780                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6781                 if (ret)
6782                         intel_dp_check_mst_status(intel_dp);
6783         }
6784 }