2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
46 #define DP_DPRX_ESI_LEN 14
48 /* Compliance test status bits */
49 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
50 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
59 static const struct dp_link_dpll g4x_dpll[] = {
61 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
63 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
66 static const struct dp_link_dpll pch_dpll[] = {
68 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
70 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
73 static const struct dp_link_dpll vlv_dpll[] = {
75 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
77 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
81 * CHV supports eDP 1.4 that have more link rates.
82 * Below only provides the fixed rate but exclude variable rate.
84 static const struct dp_link_dpll chv_dpll[] = {
86 * CHV requires to program fractional division for m2.
87 * m2 is stored in fixed point format using formula below
88 * (m2_int << 22) | m2_fraction
90 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
91 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
92 { 270000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
97 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
98 * @intel_dp: DP struct
100 * If a CPU or PCH DP output is attached to an eDP panel, this function
101 * will return true, and false otherwise.
103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
105 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
107 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
110 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
112 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
114 return intel_dig_port->base.base.dev;
117 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
119 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
122 static void intel_dp_link_down(struct intel_encoder *encoder,
123 const struct intel_crtc_state *old_crtc_state);
124 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
125 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
126 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
127 const struct intel_crtc_state *crtc_state);
128 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
130 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
132 /* update sink rates from dpcd */
133 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
135 static const int dp_rates[] = {
136 162000, 270000, 540000, 810000
140 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
142 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
143 if (dp_rates[i] > max_rate)
145 intel_dp->sink_rates[i] = dp_rates[i];
148 intel_dp->num_sink_rates = i;
151 /* Get length of rates array potentially limited by max_rate. */
152 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
156 /* Limit results by potentially reduced max rate */
157 for (i = 0; i < len; i++) {
158 if (rates[len - i - 1] <= max_rate)
165 /* Get length of common rates array potentially limited by max_rate. */
166 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
169 return intel_dp_rate_limit_len(intel_dp->common_rates,
170 intel_dp->num_common_rates, max_rate);
173 /* Theoretical max between source and sink */
174 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
176 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
179 /* Theoretical max between source and sink */
180 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
182 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
183 int source_max = intel_dig_port->max_lanes;
184 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
186 return min(source_max, sink_max);
189 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
191 return intel_dp->max_link_lane_count;
195 intel_dp_link_required(int pixel_clock, int bpp)
197 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
198 return DIV_ROUND_UP(pixel_clock * bpp, 8);
202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
204 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
205 * link rate that is generally expressed in Gbps. Since, 8 bits of data
206 * is transmitted every LS_Clk per lane, there is no need to account for
207 * the channel encoding that is done in the PHY layer here.
210 return max_link_clock * max_lanes;
214 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
217 struct intel_encoder *encoder = &intel_dig_port->base;
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
219 int max_dotclk = dev_priv->max_dotclk_freq;
222 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
224 if (type != DP_DS_PORT_TYPE_VGA)
227 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
228 intel_dp->downstream_ports);
230 if (ds_max_dotclk != 0)
231 max_dotclk = min(max_dotclk, ds_max_dotclk);
236 static int cnl_max_source_rate(struct intel_dp *intel_dp)
238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
239 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
240 enum port port = dig_port->base.port;
242 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
244 /* Low voltage SKUs are limited to max of 5.4G */
245 if (voltage == VOLTAGE_INFO_0_85V)
248 /* For this SKU 8.1G is supported in all ports */
249 if (IS_CNL_WITH_PORT_F(dev_priv))
252 /* For other SKUs, max rate on ports A and D is 5.4G */
253 if (port == PORT_A || port == PORT_D)
259 static int icl_max_source_rate(struct intel_dp *intel_dp)
261 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
262 enum port port = dig_port->base.port;
271 intel_dp_set_source_rates(struct intel_dp *intel_dp)
273 /* The values must be in increasing order */
274 static const int cnl_rates[] = {
275 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
277 static const int bxt_rates[] = {
278 162000, 216000, 243000, 270000, 324000, 432000, 540000
280 static const int skl_rates[] = {
281 162000, 216000, 270000, 324000, 432000, 540000
283 static const int hsw_rates[] = {
284 162000, 270000, 540000
286 static const int g4x_rates[] = {
289 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
290 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
291 const struct ddi_vbt_port_info *info =
292 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
293 const int *source_rates;
294 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
296 /* This should only be done once */
297 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
299 if (INTEL_GEN(dev_priv) >= 10) {
300 source_rates = cnl_rates;
301 size = ARRAY_SIZE(cnl_rates);
302 if (INTEL_GEN(dev_priv) == 10)
303 max_rate = cnl_max_source_rate(intel_dp);
305 max_rate = icl_max_source_rate(intel_dp);
306 } else if (IS_GEN9_LP(dev_priv)) {
307 source_rates = bxt_rates;
308 size = ARRAY_SIZE(bxt_rates);
309 } else if (IS_GEN9_BC(dev_priv)) {
310 source_rates = skl_rates;
311 size = ARRAY_SIZE(skl_rates);
312 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
313 IS_BROADWELL(dev_priv)) {
314 source_rates = hsw_rates;
315 size = ARRAY_SIZE(hsw_rates);
317 source_rates = g4x_rates;
318 size = ARRAY_SIZE(g4x_rates);
321 if (max_rate && vbt_max_rate)
322 max_rate = min(max_rate, vbt_max_rate);
323 else if (vbt_max_rate)
324 max_rate = vbt_max_rate;
327 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
329 intel_dp->source_rates = source_rates;
330 intel_dp->num_source_rates = size;
333 static int intersect_rates(const int *source_rates, int source_len,
334 const int *sink_rates, int sink_len,
337 int i = 0, j = 0, k = 0;
339 while (i < source_len && j < sink_len) {
340 if (source_rates[i] == sink_rates[j]) {
341 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
343 common_rates[k] = source_rates[i];
347 } else if (source_rates[i] < sink_rates[j]) {
356 /* return index of rate in rates array, or -1 if not found */
357 static int intel_dp_rate_index(const int *rates, int len, int rate)
361 for (i = 0; i < len; i++)
362 if (rate == rates[i])
368 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
370 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
372 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
373 intel_dp->num_source_rates,
374 intel_dp->sink_rates,
375 intel_dp->num_sink_rates,
376 intel_dp->common_rates);
378 /* Paranoia, there should always be something in common. */
379 if (WARN_ON(intel_dp->num_common_rates == 0)) {
380 intel_dp->common_rates[0] = 162000;
381 intel_dp->num_common_rates = 1;
385 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
389 * FIXME: we need to synchronize the current link parameters with
390 * hardware readout. Currently fast link training doesn't work on
393 if (link_rate == 0 ||
394 link_rate > intel_dp->max_link_rate)
397 if (lane_count == 0 ||
398 lane_count > intel_dp_max_lane_count(intel_dp))
404 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
405 int link_rate, uint8_t lane_count)
409 index = intel_dp_rate_index(intel_dp->common_rates,
410 intel_dp->num_common_rates,
413 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
414 intel_dp->max_link_lane_count = lane_count;
415 } else if (lane_count > 1) {
416 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
417 intel_dp->max_link_lane_count = lane_count >> 1;
419 DRM_ERROR("Link Training Unsuccessful\n");
426 static enum drm_mode_status
427 intel_dp_mode_valid(struct drm_connector *connector,
428 struct drm_display_mode *mode)
430 struct intel_dp *intel_dp = intel_attached_dp(connector);
431 struct intel_connector *intel_connector = to_intel_connector(connector);
432 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
433 int target_clock = mode->clock;
434 int max_rate, mode_rate, max_lanes, max_link_clock;
437 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
438 return MODE_NO_DBLESCAN;
440 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
442 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
443 if (mode->hdisplay > fixed_mode->hdisplay)
446 if (mode->vdisplay > fixed_mode->vdisplay)
449 target_clock = fixed_mode->clock;
452 max_link_clock = intel_dp_max_link_rate(intel_dp);
453 max_lanes = intel_dp_max_lane_count(intel_dp);
455 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
456 mode_rate = intel_dp_link_required(target_clock, 18);
458 if (mode_rate > max_rate || target_clock > max_dotclk)
459 return MODE_CLOCK_HIGH;
461 if (mode->clock < 10000)
462 return MODE_CLOCK_LOW;
464 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
465 return MODE_H_ILLEGAL;
470 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
477 for (i = 0; i < src_bytes; i++)
478 v |= ((uint32_t) src[i]) << ((3-i) * 8);
482 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
487 for (i = 0; i < dst_bytes; i++)
488 dst[i] = src >> ((3-i) * 8);
492 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
494 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
495 bool force_disable_vdd);
497 intel_dp_pps_init(struct intel_dp *intel_dp);
499 static void pps_lock(struct intel_dp *intel_dp)
501 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
504 * See intel_power_sequencer_reset() why we need
505 * a power domain reference here.
507 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
509 mutex_lock(&dev_priv->pps_mutex);
512 static void pps_unlock(struct intel_dp *intel_dp)
514 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
516 mutex_unlock(&dev_priv->pps_mutex);
518 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
522 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
524 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
525 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
526 enum pipe pipe = intel_dp->pps_pipe;
527 bool pll_enabled, release_cl_override = false;
528 enum dpio_phy phy = DPIO_PHY(pipe);
529 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
532 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
533 "skipping pipe %c power sequencer kick due to port %c being active\n",
534 pipe_name(pipe), port_name(intel_dig_port->base.port)))
537 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
538 pipe_name(pipe), port_name(intel_dig_port->base.port));
540 /* Preserve the BIOS-computed detected bit. This is
541 * supposed to be read-only.
543 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
544 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
545 DP |= DP_PORT_WIDTH(1);
546 DP |= DP_LINK_TRAIN_PAT_1;
548 if (IS_CHERRYVIEW(dev_priv))
549 DP |= DP_PIPE_SEL_CHV(pipe);
551 DP |= DP_PIPE_SEL(pipe);
553 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
556 * The DPLL for the pipe must be enabled for this to work.
557 * So enable temporarily it if it's not already enabled.
560 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
561 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
563 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
564 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
565 DRM_ERROR("Failed to force on pll for pipe %c!\n",
572 * Similar magic as in intel_dp_enable_port().
573 * We _must_ do this port enable + disable trick
574 * to make this power sequencer lock onto the port.
575 * Otherwise even VDD force bit won't work.
577 I915_WRITE(intel_dp->output_reg, DP);
578 POSTING_READ(intel_dp->output_reg);
580 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
581 POSTING_READ(intel_dp->output_reg);
583 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
584 POSTING_READ(intel_dp->output_reg);
587 vlv_force_pll_off(dev_priv, pipe);
589 if (release_cl_override)
590 chv_phy_powergate_ch(dev_priv, phy, ch, false);
594 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
596 struct intel_encoder *encoder;
597 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
600 * We don't have power sequencer currently.
601 * Pick one that's not used by other ports.
603 for_each_intel_dp(&dev_priv->drm, encoder) {
604 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
606 if (encoder->type == INTEL_OUTPUT_EDP) {
607 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
608 intel_dp->active_pipe != intel_dp->pps_pipe);
610 if (intel_dp->pps_pipe != INVALID_PIPE)
611 pipes &= ~(1 << intel_dp->pps_pipe);
613 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
615 if (intel_dp->active_pipe != INVALID_PIPE)
616 pipes &= ~(1 << intel_dp->active_pipe);
623 return ffs(pipes) - 1;
627 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
629 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
630 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
633 lockdep_assert_held(&dev_priv->pps_mutex);
635 /* We should never land here with regular DP ports */
636 WARN_ON(!intel_dp_is_edp(intel_dp));
638 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
639 intel_dp->active_pipe != intel_dp->pps_pipe);
641 if (intel_dp->pps_pipe != INVALID_PIPE)
642 return intel_dp->pps_pipe;
644 pipe = vlv_find_free_pps(dev_priv);
647 * Didn't find one. This should not happen since there
648 * are two power sequencers and up to two eDP ports.
650 if (WARN_ON(pipe == INVALID_PIPE))
653 vlv_steal_power_sequencer(dev_priv, pipe);
654 intel_dp->pps_pipe = pipe;
656 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
657 pipe_name(intel_dp->pps_pipe),
658 port_name(intel_dig_port->base.port));
660 /* init power sequencer on this pipe and port */
661 intel_dp_init_panel_power_sequencer(intel_dp);
662 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
665 * Even vdd force doesn't work until we've made
666 * the power sequencer lock in on the port.
668 vlv_power_sequencer_kick(intel_dp);
670 return intel_dp->pps_pipe;
674 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
676 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
677 int backlight_controller = dev_priv->vbt.backlight.controller;
679 lockdep_assert_held(&dev_priv->pps_mutex);
681 /* We should never land here with regular DP ports */
682 WARN_ON(!intel_dp_is_edp(intel_dp));
684 if (!intel_dp->pps_reset)
685 return backlight_controller;
687 intel_dp->pps_reset = false;
690 * Only the HW needs to be reprogrammed, the SW state is fixed and
691 * has been setup during connector init.
693 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
695 return backlight_controller;
698 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
701 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
704 return I915_READ(PP_STATUS(pipe)) & PP_ON;
707 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
710 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
713 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
720 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
722 vlv_pipe_check pipe_check)
726 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
727 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
728 PANEL_PORT_SELECT_MASK;
730 if (port_sel != PANEL_PORT_SELECT_VLV(port))
733 if (!pipe_check(dev_priv, pipe))
743 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
745 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
746 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
747 enum port port = intel_dig_port->base.port;
749 lockdep_assert_held(&dev_priv->pps_mutex);
751 /* try to find a pipe with this port selected */
752 /* first pick one where the panel is on */
753 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
755 /* didn't find one? pick one where vdd is on */
756 if (intel_dp->pps_pipe == INVALID_PIPE)
757 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
758 vlv_pipe_has_vdd_on);
759 /* didn't find one? pick one with just the correct port */
760 if (intel_dp->pps_pipe == INVALID_PIPE)
761 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
764 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
765 if (intel_dp->pps_pipe == INVALID_PIPE) {
766 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
771 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
772 port_name(port), pipe_name(intel_dp->pps_pipe));
774 intel_dp_init_panel_power_sequencer(intel_dp);
775 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
778 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
780 struct intel_encoder *encoder;
782 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
783 !IS_GEN9_LP(dev_priv)))
787 * We can't grab pps_mutex here due to deadlock with power_domain
788 * mutex when power_domain functions are called while holding pps_mutex.
789 * That also means that in order to use pps_pipe the code needs to
790 * hold both a power domain reference and pps_mutex, and the power domain
791 * reference get/put must be done while _not_ holding pps_mutex.
792 * pps_{lock,unlock}() do these steps in the correct order, so one
793 * should use them always.
796 for_each_intel_dp(&dev_priv->drm, encoder) {
797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
799 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
801 if (encoder->type != INTEL_OUTPUT_EDP)
804 if (IS_GEN9_LP(dev_priv))
805 intel_dp->pps_reset = true;
807 intel_dp->pps_pipe = INVALID_PIPE;
811 struct pps_registers {
819 static void intel_pps_get_registers(struct intel_dp *intel_dp,
820 struct pps_registers *regs)
822 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
825 memset(regs, 0, sizeof(*regs));
827 if (IS_GEN9_LP(dev_priv))
828 pps_idx = bxt_power_sequencer_idx(intel_dp);
829 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
830 pps_idx = vlv_power_sequencer_pipe(intel_dp);
832 regs->pp_ctrl = PP_CONTROL(pps_idx);
833 regs->pp_stat = PP_STATUS(pps_idx);
834 regs->pp_on = PP_ON_DELAYS(pps_idx);
835 regs->pp_off = PP_OFF_DELAYS(pps_idx);
836 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
837 !HAS_PCH_ICP(dev_priv))
838 regs->pp_div = PP_DIVISOR(pps_idx);
842 _pp_ctrl_reg(struct intel_dp *intel_dp)
844 struct pps_registers regs;
846 intel_pps_get_registers(intel_dp, ®s);
852 _pp_stat_reg(struct intel_dp *intel_dp)
854 struct pps_registers regs;
856 intel_pps_get_registers(intel_dp, ®s);
861 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
862 This function only applicable when panel PM state is not to be tracked */
863 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
866 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
868 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
870 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
875 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
876 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
877 i915_reg_t pp_ctrl_reg, pp_div_reg;
880 pp_ctrl_reg = PP_CONTROL(pipe);
881 pp_div_reg = PP_DIVISOR(pipe);
882 pp_div = I915_READ(pp_div_reg);
883 pp_div &= PP_REFERENCE_DIVIDER_MASK;
885 /* 0x1F write to PP_DIV_REG sets max cycle delay */
886 I915_WRITE(pp_div_reg, pp_div | 0x1F);
887 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
888 msleep(intel_dp->panel_power_cycle_delay);
891 pps_unlock(intel_dp);
896 static bool edp_have_panel_power(struct intel_dp *intel_dp)
898 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
900 lockdep_assert_held(&dev_priv->pps_mutex);
902 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
903 intel_dp->pps_pipe == INVALID_PIPE)
906 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
909 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
911 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
913 lockdep_assert_held(&dev_priv->pps_mutex);
915 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
916 intel_dp->pps_pipe == INVALID_PIPE)
919 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
923 intel_dp_check_edp(struct intel_dp *intel_dp)
925 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
927 if (!intel_dp_is_edp(intel_dp))
930 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
931 WARN(1, "eDP powered off while attempting aux channel communication.\n");
932 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
933 I915_READ(_pp_stat_reg(intel_dp)),
934 I915_READ(_pp_ctrl_reg(intel_dp)));
939 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
941 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
942 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
946 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
947 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
948 msecs_to_jiffies_timeout(10));
950 DRM_ERROR("dp aux hw did not signal timeout!\n");
956 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
958 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
964 * The clock divider is based off the hrawclk, and would like to run at
965 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
967 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
970 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
972 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
978 * The clock divider is based off the cdclk or PCH rawclk, and would
979 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
980 * divide by 2000 and use that
982 if (intel_dp->aux_ch == AUX_CH_A)
983 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
985 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
988 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
990 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
992 if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
993 /* Workaround for non-ULT HSW */
1001 return ilk_get_aux_clock_divider(intel_dp, index);
1004 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1007 * SKL doesn't need us to program the AUX clock divider (Hardware will
1008 * derive the clock from CDCLK automatically). We still implement the
1009 * get_aux_clock_divider vfunc to plug-in into the existing code.
1011 return index ? 0 : 1;
1014 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1016 uint32_t aux_clock_divider)
1018 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1019 struct drm_i915_private *dev_priv =
1020 to_i915(intel_dig_port->base.base.dev);
1021 uint32_t precharge, timeout;
1023 if (IS_GEN6(dev_priv))
1028 if (IS_BROADWELL(dev_priv))
1029 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1031 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1033 return DP_AUX_CH_CTL_SEND_BUSY |
1034 DP_AUX_CH_CTL_DONE |
1035 DP_AUX_CH_CTL_INTERRUPT |
1036 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1038 DP_AUX_CH_CTL_RECEIVE_ERROR |
1039 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1040 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1041 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1044 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1048 return DP_AUX_CH_CTL_SEND_BUSY |
1049 DP_AUX_CH_CTL_DONE |
1050 DP_AUX_CH_CTL_INTERRUPT |
1051 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1052 DP_AUX_CH_CTL_TIME_OUT_MAX |
1053 DP_AUX_CH_CTL_RECEIVE_ERROR |
1054 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1055 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1056 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1060 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1061 const uint8_t *send, int send_bytes,
1062 uint8_t *recv, int recv_size,
1063 u32 aux_send_ctl_flags)
1065 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1066 struct drm_i915_private *dev_priv =
1067 to_i915(intel_dig_port->base.base.dev);
1068 i915_reg_t ch_ctl, ch_data[5];
1069 uint32_t aux_clock_divider;
1070 int i, ret, recv_bytes;
1075 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1076 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1077 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1082 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1083 * In such cases we want to leave VDD enabled and it's up to upper layers
1084 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1087 vdd = edp_panel_vdd_on(intel_dp);
1089 /* dp aux is extremely sensitive to irq latency, hence request the
1090 * lowest possible wakeup latency and so prevent the cpu from going into
1091 * deep sleep states.
1093 pm_qos_update_request(&dev_priv->pm_qos, 0);
1095 intel_dp_check_edp(intel_dp);
1097 /* Try to wait for any previous AUX channel activity */
1098 for (try = 0; try < 3; try++) {
1099 status = I915_READ_NOTRACE(ch_ctl);
1100 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1106 static u32 last_status = -1;
1107 const u32 status = I915_READ(ch_ctl);
1109 if (status != last_status) {
1110 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1112 last_status = status;
1119 /* Only 5 data registers! */
1120 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1125 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1126 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1130 send_ctl |= aux_send_ctl_flags;
1132 /* Must try at least 3 times according to DP spec */
1133 for (try = 0; try < 5; try++) {
1134 /* Load the send data into the aux channel data registers */
1135 for (i = 0; i < send_bytes; i += 4)
1136 I915_WRITE(ch_data[i >> 2],
1137 intel_dp_pack_aux(send + i,
1140 /* Send the command and wait for it to complete */
1141 I915_WRITE(ch_ctl, send_ctl);
1143 status = intel_dp_aux_wait_done(intel_dp);
1145 /* Clear done status and any errors */
1148 DP_AUX_CH_CTL_DONE |
1149 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1150 DP_AUX_CH_CTL_RECEIVE_ERROR);
1152 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1153 * 400us delay required for errors and timeouts
1154 * Timeout errors from the HW already meet this
1155 * requirement so skip to next iteration
1157 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1160 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1161 usleep_range(400, 500);
1164 if (status & DP_AUX_CH_CTL_DONE)
1169 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1170 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1176 /* Check for timeout or receive error.
1177 * Timeouts occur when the sink is not connected
1179 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1180 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1185 /* Timeouts occur when the device isn't connected, so they're
1186 * "normal" -- don't fill the kernel log with these */
1187 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1188 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1193 /* Unload any bytes sent back from the other side */
1194 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1195 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1198 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1199 * We have no idea of what happened so we return -EBUSY so
1200 * drm layer takes care for the necessary retries.
1202 if (recv_bytes == 0 || recv_bytes > 20) {
1203 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1209 if (recv_bytes > recv_size)
1210 recv_bytes = recv_size;
1212 for (i = 0; i < recv_bytes; i += 4)
1213 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1214 recv + i, recv_bytes - i);
1218 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1221 edp_panel_vdd_off(intel_dp, false);
1223 pps_unlock(intel_dp);
1228 #define BARE_ADDRESS_SIZE 3
1229 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1232 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1233 const struct drm_dp_aux_msg *msg)
1235 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1236 txbuf[1] = (msg->address >> 8) & 0xff;
1237 txbuf[2] = msg->address & 0xff;
1238 txbuf[3] = msg->size - 1;
1242 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1244 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1245 uint8_t txbuf[20], rxbuf[20];
1246 size_t txsize, rxsize;
1249 intel_dp_aux_header(txbuf, msg);
1251 switch (msg->request & ~DP_AUX_I2C_MOT) {
1252 case DP_AUX_NATIVE_WRITE:
1253 case DP_AUX_I2C_WRITE:
1254 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1255 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1256 rxsize = 2; /* 0 or 1 data bytes */
1258 if (WARN_ON(txsize > 20))
1261 WARN_ON(!msg->buffer != !msg->size);
1264 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1266 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1269 msg->reply = rxbuf[0] >> 4;
1272 /* Number of bytes written in a short write. */
1273 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1275 /* Return payload size. */
1281 case DP_AUX_NATIVE_READ:
1282 case DP_AUX_I2C_READ:
1283 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1284 rxsize = msg->size + 1;
1286 if (WARN_ON(rxsize > 20))
1289 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1292 msg->reply = rxbuf[0] >> 4;
1294 * Assume happy day, and copy the data. The caller is
1295 * expected to check msg->reply before touching it.
1297 * Return payload size.
1300 memcpy(msg->buffer, rxbuf + 1, ret);
1312 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1314 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1316 enum port port = encoder->port;
1317 const struct ddi_vbt_port_info *info =
1318 &dev_priv->vbt.ddi_port_info[port];
1321 if (!info->alternate_aux_channel) {
1322 aux_ch = (enum aux_ch) port;
1324 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1325 aux_ch_name(aux_ch), port_name(port));
1329 switch (info->alternate_aux_channel) {
1349 MISSING_CASE(info->alternate_aux_channel);
1354 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1355 aux_ch_name(aux_ch), port_name(port));
1360 static enum intel_display_power_domain
1361 intel_aux_power_domain(struct intel_dp *intel_dp)
1363 switch (intel_dp->aux_ch) {
1365 return POWER_DOMAIN_AUX_A;
1367 return POWER_DOMAIN_AUX_B;
1369 return POWER_DOMAIN_AUX_C;
1371 return POWER_DOMAIN_AUX_D;
1373 return POWER_DOMAIN_AUX_E;
1375 return POWER_DOMAIN_AUX_F;
1377 MISSING_CASE(intel_dp->aux_ch);
1378 return POWER_DOMAIN_AUX_A;
1382 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1384 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1385 enum aux_ch aux_ch = intel_dp->aux_ch;
1391 return DP_AUX_CH_CTL(aux_ch);
1393 MISSING_CASE(aux_ch);
1394 return DP_AUX_CH_CTL(AUX_CH_B);
1398 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1400 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1401 enum aux_ch aux_ch = intel_dp->aux_ch;
1407 return DP_AUX_CH_DATA(aux_ch, index);
1409 MISSING_CASE(aux_ch);
1410 return DP_AUX_CH_DATA(AUX_CH_B, index);
1414 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1416 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1417 enum aux_ch aux_ch = intel_dp->aux_ch;
1421 return DP_AUX_CH_CTL(aux_ch);
1425 return PCH_DP_AUX_CH_CTL(aux_ch);
1427 MISSING_CASE(aux_ch);
1428 return DP_AUX_CH_CTL(AUX_CH_A);
1432 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1434 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1435 enum aux_ch aux_ch = intel_dp->aux_ch;
1439 return DP_AUX_CH_DATA(aux_ch, index);
1443 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1445 MISSING_CASE(aux_ch);
1446 return DP_AUX_CH_DATA(AUX_CH_A, index);
1450 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1452 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1453 enum aux_ch aux_ch = intel_dp->aux_ch;
1462 return DP_AUX_CH_CTL(aux_ch);
1464 MISSING_CASE(aux_ch);
1465 return DP_AUX_CH_CTL(AUX_CH_A);
1469 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1471 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1472 enum aux_ch aux_ch = intel_dp->aux_ch;
1481 return DP_AUX_CH_DATA(aux_ch, index);
1483 MISSING_CASE(aux_ch);
1484 return DP_AUX_CH_DATA(AUX_CH_A, index);
1489 intel_dp_aux_fini(struct intel_dp *intel_dp)
1491 kfree(intel_dp->aux.name);
1495 intel_dp_aux_init(struct intel_dp *intel_dp)
1497 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1498 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1500 intel_dp->aux_ch = intel_aux_ch(intel_dp);
1501 intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1503 if (INTEL_GEN(dev_priv) >= 9) {
1504 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1505 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1506 } else if (HAS_PCH_SPLIT(dev_priv)) {
1507 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1508 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1510 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1511 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1514 if (INTEL_GEN(dev_priv) >= 9)
1515 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1516 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1517 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1518 else if (HAS_PCH_SPLIT(dev_priv))
1519 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1521 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1523 if (INTEL_GEN(dev_priv) >= 9)
1524 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1526 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1528 drm_dp_aux_init(&intel_dp->aux);
1530 /* Failure to allocate our preferred name is not critical */
1531 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1532 port_name(encoder->port));
1533 intel_dp->aux.transfer = intel_dp_aux_transfer;
1536 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1538 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1540 return max_rate >= 540000;
1543 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1545 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1547 return max_rate >= 810000;
1551 intel_dp_set_clock(struct intel_encoder *encoder,
1552 struct intel_crtc_state *pipe_config)
1554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1555 const struct dp_link_dpll *divisor = NULL;
1558 if (IS_G4X(dev_priv)) {
1560 count = ARRAY_SIZE(g4x_dpll);
1561 } else if (HAS_PCH_SPLIT(dev_priv)) {
1563 count = ARRAY_SIZE(pch_dpll);
1564 } else if (IS_CHERRYVIEW(dev_priv)) {
1566 count = ARRAY_SIZE(chv_dpll);
1567 } else if (IS_VALLEYVIEW(dev_priv)) {
1569 count = ARRAY_SIZE(vlv_dpll);
1572 if (divisor && count) {
1573 for (i = 0; i < count; i++) {
1574 if (pipe_config->port_clock == divisor[i].clock) {
1575 pipe_config->dpll = divisor[i].dpll;
1576 pipe_config->clock_set = true;
1583 static void snprintf_int_array(char *str, size_t len,
1584 const int *array, int nelem)
1590 for (i = 0; i < nelem; i++) {
1591 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1599 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1601 char str[128]; /* FIXME: too big for stack? */
1603 if ((drm_debug & DRM_UT_KMS) == 0)
1606 snprintf_int_array(str, sizeof(str),
1607 intel_dp->source_rates, intel_dp->num_source_rates);
1608 DRM_DEBUG_KMS("source rates: %s\n", str);
1610 snprintf_int_array(str, sizeof(str),
1611 intel_dp->sink_rates, intel_dp->num_sink_rates);
1612 DRM_DEBUG_KMS("sink rates: %s\n", str);
1614 snprintf_int_array(str, sizeof(str),
1615 intel_dp->common_rates, intel_dp->num_common_rates);
1616 DRM_DEBUG_KMS("common rates: %s\n", str);
1620 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1624 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1625 if (WARN_ON(len <= 0))
1628 return intel_dp->common_rates[len - 1];
1631 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1633 int i = intel_dp_rate_index(intel_dp->sink_rates,
1634 intel_dp->num_sink_rates, rate);
1642 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1643 uint8_t *link_bw, uint8_t *rate_select)
1645 /* eDP 1.4 rate select method. */
1646 if (intel_dp->use_rate_select) {
1649 intel_dp_rate_select(intel_dp, port_clock);
1651 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1656 struct link_config_limits {
1657 int min_clock, max_clock;
1658 int min_lane_count, max_lane_count;
1659 int min_bpp, max_bpp;
1662 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1663 struct intel_crtc_state *pipe_config)
1665 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1666 struct intel_connector *intel_connector = intel_dp->attached_connector;
1669 bpp = pipe_config->pipe_bpp;
1670 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1673 bpp = min(bpp, 3*bpc);
1675 if (intel_dp_is_edp(intel_dp)) {
1676 /* Get bpp from vbt only for panels that dont have bpp in edid */
1677 if (intel_connector->base.display_info.bpc == 0 &&
1678 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1679 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1680 dev_priv->vbt.edp.bpp);
1681 bpp = dev_priv->vbt.edp.bpp;
1688 /* Adjust link config limits based on compliance test requests. */
1690 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1691 struct intel_crtc_state *pipe_config,
1692 struct link_config_limits *limits)
1694 /* For DP Compliance we override the computed bpp for the pipe */
1695 if (intel_dp->compliance.test_data.bpc != 0) {
1696 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1698 limits->min_bpp = limits->max_bpp = bpp;
1699 pipe_config->dither_force_disable = bpp == 6 * 3;
1701 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1704 /* Use values requested by Compliance Test Request */
1705 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1708 /* Validate the compliance test data since max values
1709 * might have changed due to link train fallback.
1711 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1712 intel_dp->compliance.test_lane_count)) {
1713 index = intel_dp_rate_index(intel_dp->common_rates,
1714 intel_dp->num_common_rates,
1715 intel_dp->compliance.test_link_rate);
1717 limits->min_clock = limits->max_clock = index;
1718 limits->min_lane_count = limits->max_lane_count =
1719 intel_dp->compliance.test_lane_count;
1724 /* Optimize link config in order: max bpp, min clock, min lanes */
1726 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1727 struct intel_crtc_state *pipe_config,
1728 const struct link_config_limits *limits)
1730 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1731 int bpp, clock, lane_count;
1732 int mode_rate, link_clock, link_avail;
1734 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1735 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1738 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1739 for (lane_count = limits->min_lane_count;
1740 lane_count <= limits->max_lane_count;
1742 link_clock = intel_dp->common_rates[clock];
1743 link_avail = intel_dp_max_data_rate(link_clock,
1746 if (mode_rate <= link_avail) {
1747 pipe_config->lane_count = lane_count;
1748 pipe_config->pipe_bpp = bpp;
1749 pipe_config->port_clock = link_clock;
1761 intel_dp_compute_link_config(struct intel_encoder *encoder,
1762 struct intel_crtc_state *pipe_config)
1764 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1766 struct link_config_limits limits;
1769 common_len = intel_dp_common_len_rate_limit(intel_dp,
1770 intel_dp->max_link_rate);
1772 /* No common link rates between source and sink */
1773 WARN_ON(common_len <= 0);
1775 limits.min_clock = 0;
1776 limits.max_clock = common_len - 1;
1778 limits.min_lane_count = 1;
1779 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1781 limits.min_bpp = 6 * 3;
1782 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1784 if (intel_dp_is_edp(intel_dp)) {
1786 * Use the maximum clock and number of lanes the eDP panel
1787 * advertizes being capable of. The panels are generally
1788 * designed to support only a single clock and lane
1789 * configuration, and typically these values correspond to the
1790 * native resolution of the panel.
1792 limits.min_lane_count = limits.max_lane_count;
1793 limits.min_clock = limits.max_clock;
1796 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1798 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1799 "max rate %d max bpp %d pixel clock %iKHz\n",
1800 limits.max_lane_count,
1801 intel_dp->common_rates[limits.max_clock],
1802 limits.max_bpp, adjusted_mode->crtc_clock);
1805 * Optimize for slow and wide. This is the place to add alternative
1806 * optimization policy.
1808 if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1811 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1812 pipe_config->lane_count, pipe_config->port_clock,
1813 pipe_config->pipe_bpp);
1815 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1816 intel_dp_link_required(adjusted_mode->crtc_clock,
1817 pipe_config->pipe_bpp),
1818 intel_dp_max_data_rate(pipe_config->port_clock,
1819 pipe_config->lane_count));
1825 intel_dp_compute_config(struct intel_encoder *encoder,
1826 struct intel_crtc_state *pipe_config,
1827 struct drm_connector_state *conn_state)
1829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1830 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832 enum port port = encoder->port;
1833 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1834 struct intel_connector *intel_connector = intel_dp->attached_connector;
1835 struct intel_digital_connector_state *intel_conn_state =
1836 to_intel_digital_connector_state(conn_state);
1837 bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1838 DP_DPCD_QUIRK_LIMITED_M_N);
1840 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1841 pipe_config->has_pch_encoder = true;
1843 pipe_config->has_drrs = false;
1844 if (IS_G4X(dev_priv) || port == PORT_A)
1845 pipe_config->has_audio = false;
1846 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1847 pipe_config->has_audio = intel_dp->has_audio;
1849 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1851 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1852 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1855 if (INTEL_GEN(dev_priv) >= 9) {
1858 ret = skl_update_scaler_crtc(pipe_config);
1863 if (HAS_GMCH_DISPLAY(dev_priv))
1864 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1865 conn_state->scaling_mode);
1867 intel_pch_panel_fitting(intel_crtc, pipe_config,
1868 conn_state->scaling_mode);
1871 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1874 if (HAS_GMCH_DISPLAY(dev_priv) &&
1875 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1878 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1881 if (!intel_dp_compute_link_config(encoder, pipe_config))
1884 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1887 * CEA-861-E - 5.1 Default Encoding Parameters
1888 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1890 pipe_config->limited_color_range =
1891 pipe_config->pipe_bpp != 18 &&
1892 drm_default_rgb_quant_range(adjusted_mode) ==
1893 HDMI_QUANTIZATION_RANGE_LIMITED;
1895 pipe_config->limited_color_range =
1896 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1899 intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
1900 adjusted_mode->crtc_clock,
1901 pipe_config->port_clock,
1902 &pipe_config->dp_m_n,
1905 if (intel_connector->panel.downclock_mode != NULL &&
1906 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1907 pipe_config->has_drrs = true;
1908 intel_link_compute_m_n(pipe_config->pipe_bpp,
1909 pipe_config->lane_count,
1910 intel_connector->panel.downclock_mode->clock,
1911 pipe_config->port_clock,
1912 &pipe_config->dp_m2_n2,
1916 if (!HAS_DDI(dev_priv))
1917 intel_dp_set_clock(encoder, pipe_config);
1919 intel_psr_compute_config(intel_dp, pipe_config);
1924 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1925 int link_rate, uint8_t lane_count,
1928 intel_dp->link_trained = false;
1929 intel_dp->link_rate = link_rate;
1930 intel_dp->lane_count = lane_count;
1931 intel_dp->link_mst = link_mst;
1934 static void intel_dp_prepare(struct intel_encoder *encoder,
1935 const struct intel_crtc_state *pipe_config)
1937 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1939 enum port port = encoder->port;
1940 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1941 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1943 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1944 pipe_config->lane_count,
1945 intel_crtc_has_type(pipe_config,
1946 INTEL_OUTPUT_DP_MST));
1949 * There are four kinds of DP registers:
1956 * IBX PCH and CPU are the same for almost everything,
1957 * except that the CPU DP PLL is configured in this
1960 * CPT PCH is quite different, having many bits moved
1961 * to the TRANS_DP_CTL register instead. That
1962 * configuration happens (oddly) in ironlake_pch_enable
1965 /* Preserve the BIOS-computed detected bit. This is
1966 * supposed to be read-only.
1968 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1970 /* Handle DP bits in common between all three register formats */
1971 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1972 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1974 /* Split out the IBX/CPU vs CPT settings */
1976 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1978 intel_dp->DP |= DP_SYNC_HS_HIGH;
1979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1980 intel_dp->DP |= DP_SYNC_VS_HIGH;
1981 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1984 intel_dp->DP |= DP_ENHANCED_FRAMING;
1986 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
1987 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1990 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1992 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1994 trans_dp |= TRANS_DP_ENH_FRAMING;
1996 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1997 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1999 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2000 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2002 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2003 intel_dp->DP |= DP_SYNC_HS_HIGH;
2004 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2005 intel_dp->DP |= DP_SYNC_VS_HIGH;
2006 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2008 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2009 intel_dp->DP |= DP_ENHANCED_FRAMING;
2011 if (IS_CHERRYVIEW(dev_priv))
2012 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2014 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2018 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2019 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2021 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2022 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2024 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2025 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2027 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2029 static void wait_panel_status(struct intel_dp *intel_dp,
2033 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2034 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2036 lockdep_assert_held(&dev_priv->pps_mutex);
2038 intel_pps_verify_state(intel_dp);
2040 pp_stat_reg = _pp_stat_reg(intel_dp);
2041 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2043 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2045 I915_READ(pp_stat_reg),
2046 I915_READ(pp_ctrl_reg));
2048 if (intel_wait_for_register(dev_priv,
2049 pp_stat_reg, mask, value,
2051 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2052 I915_READ(pp_stat_reg),
2053 I915_READ(pp_ctrl_reg));
2055 DRM_DEBUG_KMS("Wait complete\n");
2058 static void wait_panel_on(struct intel_dp *intel_dp)
2060 DRM_DEBUG_KMS("Wait for panel power on\n");
2061 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2064 static void wait_panel_off(struct intel_dp *intel_dp)
2066 DRM_DEBUG_KMS("Wait for panel power off time\n");
2067 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2070 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2072 ktime_t panel_power_on_time;
2073 s64 panel_power_off_duration;
2075 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2077 /* take the difference of currrent time and panel power off time
2078 * and then make panel wait for t11_t12 if needed. */
2079 panel_power_on_time = ktime_get_boottime();
2080 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2082 /* When we disable the VDD override bit last we have to do the manual
2084 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2085 wait_remaining_ms_from_jiffies(jiffies,
2086 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2088 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2091 static void wait_backlight_on(struct intel_dp *intel_dp)
2093 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2094 intel_dp->backlight_on_delay);
2097 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2099 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2100 intel_dp->backlight_off_delay);
2103 /* Read the current pp_control value, unlocking the register if it
2107 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2109 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2112 lockdep_assert_held(&dev_priv->pps_mutex);
2114 control = I915_READ(_pp_ctrl_reg(intel_dp));
2115 if (WARN_ON(!HAS_DDI(dev_priv) &&
2116 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2117 control &= ~PANEL_UNLOCK_MASK;
2118 control |= PANEL_UNLOCK_REGS;
2124 * Must be paired with edp_panel_vdd_off().
2125 * Must hold pps_mutex around the whole on/off sequence.
2126 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2128 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2130 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2131 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2133 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2134 bool need_to_disable = !intel_dp->want_panel_vdd;
2136 lockdep_assert_held(&dev_priv->pps_mutex);
2138 if (!intel_dp_is_edp(intel_dp))
2141 cancel_delayed_work(&intel_dp->panel_vdd_work);
2142 intel_dp->want_panel_vdd = true;
2144 if (edp_have_panel_vdd(intel_dp))
2145 return need_to_disable;
2147 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2149 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2150 port_name(intel_dig_port->base.port));
2152 if (!edp_have_panel_power(intel_dp))
2153 wait_panel_power_cycle(intel_dp);
2155 pp = ironlake_get_pp_control(intel_dp);
2156 pp |= EDP_FORCE_VDD;
2158 pp_stat_reg = _pp_stat_reg(intel_dp);
2159 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2161 I915_WRITE(pp_ctrl_reg, pp);
2162 POSTING_READ(pp_ctrl_reg);
2163 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2164 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2166 * If the panel wasn't on, delay before accessing aux channel
2168 if (!edp_have_panel_power(intel_dp)) {
2169 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2170 port_name(intel_dig_port->base.port));
2171 msleep(intel_dp->panel_power_up_delay);
2174 return need_to_disable;
2178 * Must be paired with intel_edp_panel_vdd_off() or
2179 * intel_edp_panel_off().
2180 * Nested calls to these functions are not allowed since
2181 * we drop the lock. Caller must use some higher level
2182 * locking to prevent nested calls from other threads.
2184 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2188 if (!intel_dp_is_edp(intel_dp))
2192 vdd = edp_panel_vdd_on(intel_dp);
2193 pps_unlock(intel_dp);
2195 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2196 port_name(dp_to_dig_port(intel_dp)->base.port));
2199 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2201 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2202 struct intel_digital_port *intel_dig_port =
2203 dp_to_dig_port(intel_dp);
2205 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2207 lockdep_assert_held(&dev_priv->pps_mutex);
2209 WARN_ON(intel_dp->want_panel_vdd);
2211 if (!edp_have_panel_vdd(intel_dp))
2214 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2215 port_name(intel_dig_port->base.port));
2217 pp = ironlake_get_pp_control(intel_dp);
2218 pp &= ~EDP_FORCE_VDD;
2220 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2221 pp_stat_reg = _pp_stat_reg(intel_dp);
2223 I915_WRITE(pp_ctrl_reg, pp);
2224 POSTING_READ(pp_ctrl_reg);
2226 /* Make sure sequencer is idle before allowing subsequent activity */
2227 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2228 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2230 if ((pp & PANEL_POWER_ON) == 0)
2231 intel_dp->panel_power_off_time = ktime_get_boottime();
2233 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2236 static void edp_panel_vdd_work(struct work_struct *__work)
2238 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2239 struct intel_dp, panel_vdd_work);
2242 if (!intel_dp->want_panel_vdd)
2243 edp_panel_vdd_off_sync(intel_dp);
2244 pps_unlock(intel_dp);
2247 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2249 unsigned long delay;
2252 * Queue the timer to fire a long time from now (relative to the power
2253 * down delay) to keep the panel power up across a sequence of
2256 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2257 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2261 * Must be paired with edp_panel_vdd_on().
2262 * Must hold pps_mutex around the whole on/off sequence.
2263 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2265 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2267 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2269 lockdep_assert_held(&dev_priv->pps_mutex);
2271 if (!intel_dp_is_edp(intel_dp))
2274 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2275 port_name(dp_to_dig_port(intel_dp)->base.port));
2277 intel_dp->want_panel_vdd = false;
2280 edp_panel_vdd_off_sync(intel_dp);
2282 edp_panel_vdd_schedule_off(intel_dp);
2285 static void edp_panel_on(struct intel_dp *intel_dp)
2287 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2289 i915_reg_t pp_ctrl_reg;
2291 lockdep_assert_held(&dev_priv->pps_mutex);
2293 if (!intel_dp_is_edp(intel_dp))
2296 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2297 port_name(dp_to_dig_port(intel_dp)->base.port));
2299 if (WARN(edp_have_panel_power(intel_dp),
2300 "eDP port %c panel power already on\n",
2301 port_name(dp_to_dig_port(intel_dp)->base.port)))
2304 wait_panel_power_cycle(intel_dp);
2306 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2307 pp = ironlake_get_pp_control(intel_dp);
2308 if (IS_GEN5(dev_priv)) {
2309 /* ILK workaround: disable reset around power sequence */
2310 pp &= ~PANEL_POWER_RESET;
2311 I915_WRITE(pp_ctrl_reg, pp);
2312 POSTING_READ(pp_ctrl_reg);
2315 pp |= PANEL_POWER_ON;
2316 if (!IS_GEN5(dev_priv))
2317 pp |= PANEL_POWER_RESET;
2319 I915_WRITE(pp_ctrl_reg, pp);
2320 POSTING_READ(pp_ctrl_reg);
2322 wait_panel_on(intel_dp);
2323 intel_dp->last_power_on = jiffies;
2325 if (IS_GEN5(dev_priv)) {
2326 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2327 I915_WRITE(pp_ctrl_reg, pp);
2328 POSTING_READ(pp_ctrl_reg);
2332 void intel_edp_panel_on(struct intel_dp *intel_dp)
2334 if (!intel_dp_is_edp(intel_dp))
2338 edp_panel_on(intel_dp);
2339 pps_unlock(intel_dp);
2343 static void edp_panel_off(struct intel_dp *intel_dp)
2345 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2347 i915_reg_t pp_ctrl_reg;
2349 lockdep_assert_held(&dev_priv->pps_mutex);
2351 if (!intel_dp_is_edp(intel_dp))
2354 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2355 port_name(dp_to_dig_port(intel_dp)->base.port));
2357 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2358 port_name(dp_to_dig_port(intel_dp)->base.port));
2360 pp = ironlake_get_pp_control(intel_dp);
2361 /* We need to switch off panel power _and_ force vdd, for otherwise some
2362 * panels get very unhappy and cease to work. */
2363 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2368 intel_dp->want_panel_vdd = false;
2370 I915_WRITE(pp_ctrl_reg, pp);
2371 POSTING_READ(pp_ctrl_reg);
2373 wait_panel_off(intel_dp);
2374 intel_dp->panel_power_off_time = ktime_get_boottime();
2376 /* We got a reference when we enabled the VDD. */
2377 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2380 void intel_edp_panel_off(struct intel_dp *intel_dp)
2382 if (!intel_dp_is_edp(intel_dp))
2386 edp_panel_off(intel_dp);
2387 pps_unlock(intel_dp);
2390 /* Enable backlight in the panel power control. */
2391 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2393 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2395 i915_reg_t pp_ctrl_reg;
2398 * If we enable the backlight right away following a panel power
2399 * on, we may see slight flicker as the panel syncs with the eDP
2400 * link. So delay a bit to make sure the image is solid before
2401 * allowing it to appear.
2403 wait_backlight_on(intel_dp);
2407 pp = ironlake_get_pp_control(intel_dp);
2408 pp |= EDP_BLC_ENABLE;
2410 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2412 I915_WRITE(pp_ctrl_reg, pp);
2413 POSTING_READ(pp_ctrl_reg);
2415 pps_unlock(intel_dp);
2418 /* Enable backlight PWM and backlight PP control. */
2419 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2420 const struct drm_connector_state *conn_state)
2422 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2424 if (!intel_dp_is_edp(intel_dp))
2427 DRM_DEBUG_KMS("\n");
2429 intel_panel_enable_backlight(crtc_state, conn_state);
2430 _intel_edp_backlight_on(intel_dp);
2433 /* Disable backlight in the panel power control. */
2434 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2436 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2438 i915_reg_t pp_ctrl_reg;
2440 if (!intel_dp_is_edp(intel_dp))
2445 pp = ironlake_get_pp_control(intel_dp);
2446 pp &= ~EDP_BLC_ENABLE;
2448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2450 I915_WRITE(pp_ctrl_reg, pp);
2451 POSTING_READ(pp_ctrl_reg);
2453 pps_unlock(intel_dp);
2455 intel_dp->last_backlight_off = jiffies;
2456 edp_wait_backlight_off(intel_dp);
2459 /* Disable backlight PP control and backlight PWM. */
2460 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2462 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2464 if (!intel_dp_is_edp(intel_dp))
2467 DRM_DEBUG_KMS("\n");
2469 _intel_edp_backlight_off(intel_dp);
2470 intel_panel_disable_backlight(old_conn_state);
2474 * Hook for controlling the panel power control backlight through the bl_power
2475 * sysfs attribute. Take care to handle multiple calls.
2477 static void intel_edp_backlight_power(struct intel_connector *connector,
2480 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2484 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2485 pps_unlock(intel_dp);
2487 if (is_enabled == enable)
2490 DRM_DEBUG_KMS("panel power control backlight %s\n",
2491 enable ? "enable" : "disable");
2494 _intel_edp_backlight_on(intel_dp);
2496 _intel_edp_backlight_off(intel_dp);
2499 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2501 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2502 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2503 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2505 I915_STATE_WARN(cur_state != state,
2506 "DP port %c state assertion failure (expected %s, current %s)\n",
2507 port_name(dig_port->base.port),
2508 onoff(state), onoff(cur_state));
2510 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2512 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2514 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2516 I915_STATE_WARN(cur_state != state,
2517 "eDP PLL state assertion failure (expected %s, current %s)\n",
2518 onoff(state), onoff(cur_state));
2520 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2521 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2523 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2524 const struct intel_crtc_state *pipe_config)
2526 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2527 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2529 assert_pipe_disabled(dev_priv, crtc->pipe);
2530 assert_dp_port_disabled(intel_dp);
2531 assert_edp_pll_disabled(dev_priv);
2533 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2534 pipe_config->port_clock);
2536 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2538 if (pipe_config->port_clock == 162000)
2539 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2541 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2543 I915_WRITE(DP_A, intel_dp->DP);
2548 * [DevILK] Work around required when enabling DP PLL
2549 * while a pipe is enabled going to FDI:
2550 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2551 * 2. Program DP PLL enable
2553 if (IS_GEN5(dev_priv))
2554 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2556 intel_dp->DP |= DP_PLL_ENABLE;
2558 I915_WRITE(DP_A, intel_dp->DP);
2563 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2564 const struct intel_crtc_state *old_crtc_state)
2566 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2567 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2569 assert_pipe_disabled(dev_priv, crtc->pipe);
2570 assert_dp_port_disabled(intel_dp);
2571 assert_edp_pll_enabled(dev_priv);
2573 DRM_DEBUG_KMS("disabling eDP PLL\n");
2575 intel_dp->DP &= ~DP_PLL_ENABLE;
2577 I915_WRITE(DP_A, intel_dp->DP);
2582 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2585 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2586 * be capable of signalling downstream hpd with a long pulse.
2587 * Whether or not that means D3 is safe to use is not clear,
2588 * but let's assume so until proven otherwise.
2590 * FIXME should really check all downstream ports...
2592 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2593 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2594 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2597 /* If the sink supports it, try to set the power state appropriately */
2598 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2602 /* Should have a valid DPCD by this point */
2603 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2606 if (mode != DRM_MODE_DPMS_ON) {
2607 if (downstream_hpd_needs_d0(intel_dp))
2610 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2613 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2616 * When turning on, we need to retry for 1ms to give the sink
2619 for (i = 0; i < 3; i++) {
2620 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2627 if (ret == 1 && lspcon->active)
2628 lspcon_wait_pcon_mode(lspcon);
2632 DRM_DEBUG_KMS("failed to %s sink power state\n",
2633 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2636 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2637 enum port port, enum pipe *pipe)
2641 for_each_pipe(dev_priv, p) {
2642 u32 val = I915_READ(TRANS_DP_CTL(p));
2644 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2650 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2652 /* must initialize pipe to something for the asserts */
2658 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2659 i915_reg_t dp_reg, enum port port,
2665 val = I915_READ(dp_reg);
2667 ret = val & DP_PORT_EN;
2669 /* asserts want to know the pipe even if the port is disabled */
2670 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2671 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2672 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2673 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2674 else if (IS_CHERRYVIEW(dev_priv))
2675 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2677 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2682 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2686 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2689 if (!intel_display_power_get_if_enabled(dev_priv,
2690 encoder->power_domain))
2693 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2694 encoder->port, pipe);
2696 intel_display_power_put(dev_priv, encoder->power_domain);
2701 static void intel_dp_get_config(struct intel_encoder *encoder,
2702 struct intel_crtc_state *pipe_config)
2704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2705 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2707 enum port port = encoder->port;
2708 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2710 if (encoder->type == INTEL_OUTPUT_EDP)
2711 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2713 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2715 tmp = I915_READ(intel_dp->output_reg);
2717 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2719 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2720 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2722 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2723 flags |= DRM_MODE_FLAG_PHSYNC;
2725 flags |= DRM_MODE_FLAG_NHSYNC;
2727 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2728 flags |= DRM_MODE_FLAG_PVSYNC;
2730 flags |= DRM_MODE_FLAG_NVSYNC;
2732 if (tmp & DP_SYNC_HS_HIGH)
2733 flags |= DRM_MODE_FLAG_PHSYNC;
2735 flags |= DRM_MODE_FLAG_NHSYNC;
2737 if (tmp & DP_SYNC_VS_HIGH)
2738 flags |= DRM_MODE_FLAG_PVSYNC;
2740 flags |= DRM_MODE_FLAG_NVSYNC;
2743 pipe_config->base.adjusted_mode.flags |= flags;
2745 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2746 pipe_config->limited_color_range = true;
2748 pipe_config->lane_count =
2749 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2751 intel_dp_get_m_n(crtc, pipe_config);
2753 if (port == PORT_A) {
2754 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2755 pipe_config->port_clock = 162000;
2757 pipe_config->port_clock = 270000;
2760 pipe_config->base.adjusted_mode.crtc_clock =
2761 intel_dotclock_calculate(pipe_config->port_clock,
2762 &pipe_config->dp_m_n);
2764 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2765 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2767 * This is a big fat ugly hack.
2769 * Some machines in UEFI boot mode provide us a VBT that has 18
2770 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2771 * unknown we fail to light up. Yet the same BIOS boots up with
2772 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2773 * max, not what it tells us to use.
2775 * Note: This will still be broken if the eDP panel is not lit
2776 * up by the BIOS, and thus we can't get the mode at module
2779 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2780 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2781 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2785 static void intel_disable_dp(struct intel_encoder *encoder,
2786 const struct intel_crtc_state *old_crtc_state,
2787 const struct drm_connector_state *old_conn_state)
2789 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2791 intel_dp->link_trained = false;
2793 if (old_crtc_state->has_audio)
2794 intel_audio_codec_disable(encoder,
2795 old_crtc_state, old_conn_state);
2797 /* Make sure the panel is off before trying to change the mode. But also
2798 * ensure that we have vdd while we switch off the panel. */
2799 intel_edp_panel_vdd_on(intel_dp);
2800 intel_edp_backlight_off(old_conn_state);
2801 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2802 intel_edp_panel_off(intel_dp);
2805 static void g4x_disable_dp(struct intel_encoder *encoder,
2806 const struct intel_crtc_state *old_crtc_state,
2807 const struct drm_connector_state *old_conn_state)
2809 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2812 static void vlv_disable_dp(struct intel_encoder *encoder,
2813 const struct intel_crtc_state *old_crtc_state,
2814 const struct drm_connector_state *old_conn_state)
2816 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2819 static void g4x_post_disable_dp(struct intel_encoder *encoder,
2820 const struct intel_crtc_state *old_crtc_state,
2821 const struct drm_connector_state *old_conn_state)
2823 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2824 enum port port = encoder->port;
2827 * Bspec does not list a specific disable sequence for g4x DP.
2828 * Follow the ilk+ sequence (disable pipe before the port) for
2829 * g4x DP as it does not suffer from underruns like the normal
2830 * g4x modeset sequence (disable pipe after the port).
2832 intel_dp_link_down(encoder, old_crtc_state);
2834 /* Only ilk+ has port A */
2836 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2839 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2840 const struct intel_crtc_state *old_crtc_state,
2841 const struct drm_connector_state *old_conn_state)
2843 intel_dp_link_down(encoder, old_crtc_state);
2846 static void chv_post_disable_dp(struct intel_encoder *encoder,
2847 const struct intel_crtc_state *old_crtc_state,
2848 const struct drm_connector_state *old_conn_state)
2850 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2852 intel_dp_link_down(encoder, old_crtc_state);
2854 mutex_lock(&dev_priv->sb_lock);
2856 /* Assert data lane reset */
2857 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2859 mutex_unlock(&dev_priv->sb_lock);
2863 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2865 uint8_t dp_train_pat)
2867 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2869 enum port port = intel_dig_port->base.port;
2870 uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
2872 if (dp_train_pat & train_pat_mask)
2873 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2874 dp_train_pat & train_pat_mask);
2876 if (HAS_DDI(dev_priv)) {
2877 uint32_t temp = I915_READ(DP_TP_CTL(port));
2879 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2880 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2882 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2884 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2885 switch (dp_train_pat & train_pat_mask) {
2886 case DP_TRAINING_PATTERN_DISABLE:
2887 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2890 case DP_TRAINING_PATTERN_1:
2891 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2893 case DP_TRAINING_PATTERN_2:
2894 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2896 case DP_TRAINING_PATTERN_3:
2897 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2899 case DP_TRAINING_PATTERN_4:
2900 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
2903 I915_WRITE(DP_TP_CTL(port), temp);
2905 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
2906 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2907 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2909 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2910 case DP_TRAINING_PATTERN_DISABLE:
2911 *DP |= DP_LINK_TRAIN_OFF_CPT;
2913 case DP_TRAINING_PATTERN_1:
2914 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2916 case DP_TRAINING_PATTERN_2:
2917 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2919 case DP_TRAINING_PATTERN_3:
2920 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2921 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2926 *DP &= ~DP_LINK_TRAIN_MASK;
2928 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2929 case DP_TRAINING_PATTERN_DISABLE:
2930 *DP |= DP_LINK_TRAIN_OFF;
2932 case DP_TRAINING_PATTERN_1:
2933 *DP |= DP_LINK_TRAIN_PAT_1;
2935 case DP_TRAINING_PATTERN_2:
2936 *DP |= DP_LINK_TRAIN_PAT_2;
2938 case DP_TRAINING_PATTERN_3:
2939 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2940 *DP |= DP_LINK_TRAIN_PAT_2;
2946 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2947 const struct intel_crtc_state *old_crtc_state)
2949 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2951 /* enable with pattern 1 (as per spec) */
2953 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2956 * Magic for VLV/CHV. We _must_ first set up the register
2957 * without actually enabling the port, and then do another
2958 * write to enable the port. Otherwise link training will
2959 * fail when the power sequencer is freshly used for this port.
2961 intel_dp->DP |= DP_PORT_EN;
2962 if (old_crtc_state->has_audio)
2963 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2965 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2966 POSTING_READ(intel_dp->output_reg);
2969 static void intel_enable_dp(struct intel_encoder *encoder,
2970 const struct intel_crtc_state *pipe_config,
2971 const struct drm_connector_state *conn_state)
2973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2974 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2975 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2976 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2977 enum pipe pipe = crtc->pipe;
2979 if (WARN_ON(dp_reg & DP_PORT_EN))
2984 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2985 vlv_init_panel_power_sequencer(encoder, pipe_config);
2987 intel_dp_enable_port(intel_dp, pipe_config);
2989 edp_panel_vdd_on(intel_dp);
2990 edp_panel_on(intel_dp);
2991 edp_panel_vdd_off(intel_dp, true);
2993 pps_unlock(intel_dp);
2995 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2996 unsigned int lane_mask = 0x0;
2998 if (IS_CHERRYVIEW(dev_priv))
2999 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3001 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3005 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3006 intel_dp_start_link_train(intel_dp);
3007 intel_dp_stop_link_train(intel_dp);
3009 if (pipe_config->has_audio) {
3010 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3012 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3016 static void g4x_enable_dp(struct intel_encoder *encoder,
3017 const struct intel_crtc_state *pipe_config,
3018 const struct drm_connector_state *conn_state)
3020 intel_enable_dp(encoder, pipe_config, conn_state);
3021 intel_edp_backlight_on(pipe_config, conn_state);
3024 static void vlv_enable_dp(struct intel_encoder *encoder,
3025 const struct intel_crtc_state *pipe_config,
3026 const struct drm_connector_state *conn_state)
3028 intel_edp_backlight_on(pipe_config, conn_state);
3031 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3032 const struct intel_crtc_state *pipe_config,
3033 const struct drm_connector_state *conn_state)
3035 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3036 enum port port = encoder->port;
3038 intel_dp_prepare(encoder, pipe_config);
3040 /* Only ilk+ has port A */
3042 ironlake_edp_pll_on(intel_dp, pipe_config);
3045 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3047 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3048 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3049 enum pipe pipe = intel_dp->pps_pipe;
3050 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3052 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3054 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3057 edp_panel_vdd_off_sync(intel_dp);
3060 * VLV seems to get confused when multiple power sequencers
3061 * have the same port selected (even if only one has power/vdd
3062 * enabled). The failure manifests as vlv_wait_port_ready() failing
3063 * CHV on the other hand doesn't seem to mind having the same port
3064 * selected in multiple power sequencers, but let's clear the
3065 * port select always when logically disconnecting a power sequencer
3068 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3069 pipe_name(pipe), port_name(intel_dig_port->base.port));
3070 I915_WRITE(pp_on_reg, 0);
3071 POSTING_READ(pp_on_reg);
3073 intel_dp->pps_pipe = INVALID_PIPE;
3076 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3079 struct intel_encoder *encoder;
3081 lockdep_assert_held(&dev_priv->pps_mutex);
3083 for_each_intel_dp(&dev_priv->drm, encoder) {
3084 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3085 enum port port = encoder->port;
3087 WARN(intel_dp->active_pipe == pipe,
3088 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3089 pipe_name(pipe), port_name(port));
3091 if (intel_dp->pps_pipe != pipe)
3094 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3095 pipe_name(pipe), port_name(port));
3097 /* make sure vdd is off before we steal it */
3098 vlv_detach_power_sequencer(intel_dp);
3102 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3103 const struct intel_crtc_state *crtc_state)
3105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3106 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3109 lockdep_assert_held(&dev_priv->pps_mutex);
3111 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3113 if (intel_dp->pps_pipe != INVALID_PIPE &&
3114 intel_dp->pps_pipe != crtc->pipe) {
3116 * If another power sequencer was being used on this
3117 * port previously make sure to turn off vdd there while
3118 * we still have control of it.
3120 vlv_detach_power_sequencer(intel_dp);
3124 * We may be stealing the power
3125 * sequencer from another port.
3127 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3129 intel_dp->active_pipe = crtc->pipe;
3131 if (!intel_dp_is_edp(intel_dp))
3134 /* now it's all ours */
3135 intel_dp->pps_pipe = crtc->pipe;
3137 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3138 pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3140 /* init power sequencer on this pipe and port */
3141 intel_dp_init_panel_power_sequencer(intel_dp);
3142 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3145 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3146 const struct intel_crtc_state *pipe_config,
3147 const struct drm_connector_state *conn_state)
3149 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3151 intel_enable_dp(encoder, pipe_config, conn_state);
3154 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3155 const struct intel_crtc_state *pipe_config,
3156 const struct drm_connector_state *conn_state)
3158 intel_dp_prepare(encoder, pipe_config);
3160 vlv_phy_pre_pll_enable(encoder, pipe_config);
3163 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3164 const struct intel_crtc_state *pipe_config,
3165 const struct drm_connector_state *conn_state)
3167 chv_phy_pre_encoder_enable(encoder, pipe_config);
3169 intel_enable_dp(encoder, pipe_config, conn_state);
3171 /* Second common lane will stay alive on its own now */
3172 chv_phy_release_cl2_override(encoder);
3175 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3176 const struct intel_crtc_state *pipe_config,
3177 const struct drm_connector_state *conn_state)
3179 intel_dp_prepare(encoder, pipe_config);
3181 chv_phy_pre_pll_enable(encoder, pipe_config);
3184 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3185 const struct intel_crtc_state *old_crtc_state,
3186 const struct drm_connector_state *old_conn_state)
3188 chv_phy_post_pll_disable(encoder, old_crtc_state);
3192 * Fetch AUX CH registers 0x202 - 0x207 which contain
3193 * link status information
3196 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3198 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3199 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3202 /* These are source-specific values. */
3204 intel_dp_voltage_max(struct intel_dp *intel_dp)
3206 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3207 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3208 enum port port = encoder->port;
3210 if (HAS_DDI(dev_priv))
3211 return intel_ddi_dp_voltage_max(encoder);
3212 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3213 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3214 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3215 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3216 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3217 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3219 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3223 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3225 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3226 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3227 enum port port = encoder->port;
3229 if (HAS_DDI(dev_priv)) {
3230 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3231 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3232 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3234 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3236 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3238 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3241 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3243 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3244 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3246 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3249 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3251 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3254 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3256 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3258 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3260 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3263 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3268 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3270 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3271 unsigned long demph_reg_value, preemph_reg_value,
3272 uniqtranscale_reg_value;
3273 uint8_t train_set = intel_dp->train_set[0];
3275 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3276 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3277 preemph_reg_value = 0x0004000;
3278 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3280 demph_reg_value = 0x2B405555;
3281 uniqtranscale_reg_value = 0x552AB83A;
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3284 demph_reg_value = 0x2B404040;
3285 uniqtranscale_reg_value = 0x5548B83A;
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3288 demph_reg_value = 0x2B245555;
3289 uniqtranscale_reg_value = 0x5560B83A;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3292 demph_reg_value = 0x2B405555;
3293 uniqtranscale_reg_value = 0x5598DA3A;
3299 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3300 preemph_reg_value = 0x0002000;
3301 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3303 demph_reg_value = 0x2B404040;
3304 uniqtranscale_reg_value = 0x5552B83A;
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3307 demph_reg_value = 0x2B404848;
3308 uniqtranscale_reg_value = 0x5580B83A;
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3311 demph_reg_value = 0x2B404040;
3312 uniqtranscale_reg_value = 0x55ADDA3A;
3318 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3319 preemph_reg_value = 0x0000000;
3320 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3322 demph_reg_value = 0x2B305555;
3323 uniqtranscale_reg_value = 0x5570B83A;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3326 demph_reg_value = 0x2B2B4040;
3327 uniqtranscale_reg_value = 0x55ADDA3A;
3333 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3334 preemph_reg_value = 0x0006000;
3335 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3337 demph_reg_value = 0x1B405555;
3338 uniqtranscale_reg_value = 0x55ADDA3A;
3348 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3349 uniqtranscale_reg_value, 0);
3354 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3356 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3357 u32 deemph_reg_value, margin_reg_value;
3358 bool uniq_trans_scale = false;
3359 uint8_t train_set = intel_dp->train_set[0];
3361 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3362 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3363 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3365 deemph_reg_value = 128;
3366 margin_reg_value = 52;
3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3369 deemph_reg_value = 128;
3370 margin_reg_value = 77;
3372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3373 deemph_reg_value = 128;
3374 margin_reg_value = 102;
3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3377 deemph_reg_value = 128;
3378 margin_reg_value = 154;
3379 uniq_trans_scale = true;
3385 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3386 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3388 deemph_reg_value = 85;
3389 margin_reg_value = 78;
3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3392 deemph_reg_value = 85;
3393 margin_reg_value = 116;
3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3396 deemph_reg_value = 85;
3397 margin_reg_value = 154;
3403 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3404 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3406 deemph_reg_value = 64;
3407 margin_reg_value = 104;
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3410 deemph_reg_value = 64;
3411 margin_reg_value = 154;
3417 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3418 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3420 deemph_reg_value = 43;
3421 margin_reg_value = 154;
3431 chv_set_phy_signal_level(encoder, deemph_reg_value,
3432 margin_reg_value, uniq_trans_scale);
3438 g4x_signal_levels(uint8_t train_set)
3440 uint32_t signal_levels = 0;
3442 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3445 signal_levels |= DP_VOLTAGE_0_4;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3448 signal_levels |= DP_VOLTAGE_0_6;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3451 signal_levels |= DP_VOLTAGE_0_8;
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3454 signal_levels |= DP_VOLTAGE_1_2;
3457 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3458 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3460 signal_levels |= DP_PRE_EMPHASIS_0;
3462 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3463 signal_levels |= DP_PRE_EMPHASIS_3_5;
3465 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3466 signal_levels |= DP_PRE_EMPHASIS_6;
3468 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3469 signal_levels |= DP_PRE_EMPHASIS_9_5;
3472 return signal_levels;
3475 /* SNB CPU eDP voltage swing and pre-emphasis control */
3477 snb_cpu_edp_signal_levels(uint8_t train_set)
3479 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3480 DP_TRAIN_PRE_EMPHASIS_MASK);
3481 switch (signal_levels) {
3482 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3484 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3486 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3489 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3491 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3492 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3493 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3494 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3495 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3497 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3498 "0x%x\n", signal_levels);
3499 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3503 /* IVB CPU eDP voltage swing and pre-emphasis control */
3505 ivb_cpu_edp_signal_levels(uint8_t train_set)
3507 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3508 DP_TRAIN_PRE_EMPHASIS_MASK);
3509 switch (signal_levels) {
3510 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3512 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3513 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3514 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3515 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3517 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3518 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3519 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3520 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3523 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3525 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3528 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3529 "0x%x\n", signal_levels);
3530 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3535 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3537 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3538 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3539 enum port port = intel_dig_port->base.port;
3540 uint32_t signal_levels, mask = 0;
3541 uint8_t train_set = intel_dp->train_set[0];
3543 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3544 signal_levels = bxt_signal_levels(intel_dp);
3545 } else if (HAS_DDI(dev_priv)) {
3546 signal_levels = ddi_signal_levels(intel_dp);
3547 mask = DDI_BUF_EMP_MASK;
3548 } else if (IS_CHERRYVIEW(dev_priv)) {
3549 signal_levels = chv_signal_levels(intel_dp);
3550 } else if (IS_VALLEYVIEW(dev_priv)) {
3551 signal_levels = vlv_signal_levels(intel_dp);
3552 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3553 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3554 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3555 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3556 signal_levels = snb_cpu_edp_signal_levels(train_set);
3557 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3559 signal_levels = g4x_signal_levels(train_set);
3560 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3564 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3566 DRM_DEBUG_KMS("Using vswing level %d\n",
3567 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3568 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3569 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3570 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3572 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3574 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3575 POSTING_READ(intel_dp->output_reg);
3579 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3580 uint8_t dp_train_pat)
3582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3583 struct drm_i915_private *dev_priv =
3584 to_i915(intel_dig_port->base.base.dev);
3586 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3588 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3589 POSTING_READ(intel_dp->output_reg);
3592 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3594 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3595 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3596 enum port port = intel_dig_port->base.port;
3599 if (!HAS_DDI(dev_priv))
3602 val = I915_READ(DP_TP_CTL(port));
3603 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3604 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3605 I915_WRITE(DP_TP_CTL(port), val);
3608 * On PORT_A we can have only eDP in SST mode. There the only reason
3609 * we need to set idle transmission mode is to work around a HW issue
3610 * where we enable the pipe while not in idle link-training mode.
3611 * In this case there is requirement to wait for a minimum number of
3612 * idle patterns to be sent.
3617 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3618 DP_TP_STATUS_IDLE_DONE,
3619 DP_TP_STATUS_IDLE_DONE,
3621 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3625 intel_dp_link_down(struct intel_encoder *encoder,
3626 const struct intel_crtc_state *old_crtc_state)
3628 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3629 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3630 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3631 enum port port = encoder->port;
3632 uint32_t DP = intel_dp->DP;
3634 if (WARN_ON(HAS_DDI(dev_priv)))
3637 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3640 DRM_DEBUG_KMS("\n");
3642 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3643 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3644 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3645 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3647 DP &= ~DP_LINK_TRAIN_MASK;
3648 DP |= DP_LINK_TRAIN_PAT_IDLE;
3650 I915_WRITE(intel_dp->output_reg, DP);
3651 POSTING_READ(intel_dp->output_reg);
3653 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3654 I915_WRITE(intel_dp->output_reg, DP);
3655 POSTING_READ(intel_dp->output_reg);
3658 * HW workaround for IBX, we need to move the port
3659 * to transcoder A after disabling it to allow the
3660 * matching HDMI port to be enabled on transcoder A.
3662 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3664 * We get CPU/PCH FIFO underruns on the other pipe when
3665 * doing the workaround. Sweep them under the rug.
3667 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3668 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3670 /* always enable with pattern 1 (as per spec) */
3671 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3672 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3673 DP_LINK_TRAIN_PAT_1;
3674 I915_WRITE(intel_dp->output_reg, DP);
3675 POSTING_READ(intel_dp->output_reg);
3678 I915_WRITE(intel_dp->output_reg, DP);
3679 POSTING_READ(intel_dp->output_reg);
3681 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3682 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3683 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3686 msleep(intel_dp->panel_power_down_delay);
3690 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3692 intel_dp->active_pipe = INVALID_PIPE;
3693 pps_unlock(intel_dp);
3698 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3700 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3701 sizeof(intel_dp->dpcd)) < 0)
3702 return false; /* aux transfer failed */
3704 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3706 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3710 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3712 struct drm_i915_private *dev_priv =
3713 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3715 /* this function is meant to be called only once */
3716 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3718 if (!intel_dp_read_dpcd(intel_dp))
3721 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3722 drm_dp_is_branch(intel_dp->dpcd));
3724 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3725 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3726 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3729 * Read the eDP display control registers.
3731 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3732 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3733 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3734 * method). The display control registers should read zero if they're
3735 * not supported anyway.
3737 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3738 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3739 sizeof(intel_dp->edp_dpcd))
3740 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3741 intel_dp->edp_dpcd);
3744 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3745 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3747 intel_psr_init_dpcd(intel_dp);
3749 /* Read the eDP 1.4+ supported link rates. */
3750 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3751 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3754 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3755 sink_rates, sizeof(sink_rates));
3757 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3758 int val = le16_to_cpu(sink_rates[i]);
3763 /* Value read multiplied by 200kHz gives the per-lane
3764 * link rate in kHz. The source rates are, however,
3765 * stored in terms of LS_Clk kHz. The full conversion
3766 * back to symbols is
3767 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3769 intel_dp->sink_rates[i] = (val * 200) / 10;
3771 intel_dp->num_sink_rates = i;
3775 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3776 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3778 if (intel_dp->num_sink_rates)
3779 intel_dp->use_rate_select = true;
3781 intel_dp_set_sink_rates(intel_dp);
3783 intel_dp_set_common_rates(intel_dp);
3790 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3794 if (!intel_dp_read_dpcd(intel_dp))
3797 /* Don't clobber cached eDP rates. */
3798 if (!intel_dp_is_edp(intel_dp)) {
3799 intel_dp_set_sink_rates(intel_dp);
3800 intel_dp_set_common_rates(intel_dp);
3803 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3807 * Sink count can change between short pulse hpd hence
3808 * a member variable in intel_dp will track any changes
3809 * between short pulse interrupts.
3811 intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3814 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3815 * a dongle is present but no display. Unless we require to know
3816 * if a dongle is present or not, we don't need to update
3817 * downstream port information. So, an early return here saves
3818 * time from performing other operations which are not required.
3820 if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3823 if (!drm_dp_is_branch(intel_dp->dpcd))
3824 return true; /* native DP sink */
3826 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3827 return true; /* no per-port downstream info */
3829 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3830 intel_dp->downstream_ports,
3831 DP_MAX_DOWNSTREAM_PORTS) < 0)
3832 return false; /* downstream port status fetch failed */
3838 intel_dp_can_mst(struct intel_dp *intel_dp)
3842 if (!i915_modparams.enable_dp_mst)
3845 if (!intel_dp->can_mst)
3848 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3851 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3854 return mstm_cap & DP_MST_CAP;
3858 intel_dp_configure_mst(struct intel_dp *intel_dp)
3860 if (!i915_modparams.enable_dp_mst)
3863 if (!intel_dp->can_mst)
3866 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3868 if (intel_dp->is_mst)
3869 DRM_DEBUG_KMS("Sink is MST capable\n");
3871 DRM_DEBUG_KMS("Sink is not MST capable\n");
3873 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3878 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3880 return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3881 sink_irq_vector) == 1;
3885 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3887 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3888 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3892 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3896 uint8_t test_lane_count, test_link_bw;
3900 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3901 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3905 DRM_DEBUG_KMS("Lane count read failed\n");
3908 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3910 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3913 DRM_DEBUG_KMS("Link Rate read failed\n");
3916 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3918 /* Validate the requested link rate and lane count */
3919 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3923 intel_dp->compliance.test_lane_count = test_lane_count;
3924 intel_dp->compliance.test_link_rate = test_link_rate;
3929 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3931 uint8_t test_pattern;
3933 __be16 h_width, v_height;
3936 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3937 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3940 DRM_DEBUG_KMS("Test pattern read failed\n");
3943 if (test_pattern != DP_COLOR_RAMP)
3946 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3949 DRM_DEBUG_KMS("H Width read failed\n");
3953 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3956 DRM_DEBUG_KMS("V Height read failed\n");
3960 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3963 DRM_DEBUG_KMS("TEST MISC read failed\n");
3966 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3968 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3970 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3971 case DP_TEST_BIT_DEPTH_6:
3972 intel_dp->compliance.test_data.bpc = 6;
3974 case DP_TEST_BIT_DEPTH_8:
3975 intel_dp->compliance.test_data.bpc = 8;
3981 intel_dp->compliance.test_data.video_pattern = test_pattern;
3982 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3983 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3984 /* Set test active flag here so userspace doesn't interrupt things */
3985 intel_dp->compliance.test_active = 1;
3990 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3992 uint8_t test_result = DP_TEST_ACK;
3993 struct intel_connector *intel_connector = intel_dp->attached_connector;
3994 struct drm_connector *connector = &intel_connector->base;
3996 if (intel_connector->detect_edid == NULL ||
3997 connector->edid_corrupt ||
3998 intel_dp->aux.i2c_defer_count > 6) {
3999 /* Check EDID read for NACKs, DEFERs and corruption
4000 * (DP CTS 1.2 Core r1.1)
4001 * 4.2.2.4 : Failed EDID read, I2C_NAK
4002 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4003 * 4.2.2.6 : EDID corruption detected
4004 * Use failsafe mode for all cases
4006 if (intel_dp->aux.i2c_nack_count > 0 ||
4007 intel_dp->aux.i2c_defer_count > 0)
4008 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4009 intel_dp->aux.i2c_nack_count,
4010 intel_dp->aux.i2c_defer_count);
4011 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4013 struct edid *block = intel_connector->detect_edid;
4015 /* We have to write the checksum
4016 * of the last block read
4018 block += intel_connector->detect_edid->extensions;
4020 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4021 block->checksum) <= 0)
4022 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4024 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4025 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4028 /* Set test active flag here so userspace doesn't interrupt things */
4029 intel_dp->compliance.test_active = 1;
4034 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4036 uint8_t test_result = DP_TEST_NAK;
4040 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4042 uint8_t response = DP_TEST_NAK;
4043 uint8_t request = 0;
4046 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4048 DRM_DEBUG_KMS("Could not read test request from sink\n");
4053 case DP_TEST_LINK_TRAINING:
4054 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4055 response = intel_dp_autotest_link_training(intel_dp);
4057 case DP_TEST_LINK_VIDEO_PATTERN:
4058 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4059 response = intel_dp_autotest_video_pattern(intel_dp);
4061 case DP_TEST_LINK_EDID_READ:
4062 DRM_DEBUG_KMS("EDID test requested\n");
4063 response = intel_dp_autotest_edid(intel_dp);
4065 case DP_TEST_LINK_PHY_TEST_PATTERN:
4066 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4067 response = intel_dp_autotest_phy_pattern(intel_dp);
4070 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4074 if (response & DP_TEST_ACK)
4075 intel_dp->compliance.test_type = request;
4078 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4080 DRM_DEBUG_KMS("Could not write test response to sink\n");
4084 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4088 if (intel_dp->is_mst) {
4089 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4093 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4097 /* check link status - esi[10] = 0x200c */
4098 if (intel_dp->active_mst_links &&
4099 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4100 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4101 intel_dp_start_link_train(intel_dp);
4102 intel_dp_stop_link_train(intel_dp);
4105 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4106 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4109 for (retry = 0; retry < 3; retry++) {
4111 wret = drm_dp_dpcd_write(&intel_dp->aux,
4112 DP_SINK_COUNT_ESI+1,
4119 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4121 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4129 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4130 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4131 intel_dp->is_mst = false;
4132 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4133 /* send a hotplug event */
4134 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4141 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4143 u8 link_status[DP_LINK_STATUS_SIZE];
4145 if (!intel_dp->link_trained)
4148 if (!intel_dp_get_link_status(intel_dp, link_status))
4152 * Validate the cached values of intel_dp->link_rate and
4153 * intel_dp->lane_count before attempting to retrain.
4155 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4156 intel_dp->lane_count))
4159 /* Retrain if Channel EQ or CR not ok */
4160 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4163 int intel_dp_retrain_link(struct intel_encoder *encoder,
4164 struct drm_modeset_acquire_ctx *ctx)
4166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4167 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4168 struct intel_connector *connector = intel_dp->attached_connector;
4169 struct drm_connector_state *conn_state;
4170 struct intel_crtc_state *crtc_state;
4171 struct intel_crtc *crtc;
4174 /* FIXME handle the MST connectors as well */
4176 if (!connector || connector->base.status != connector_status_connected)
4179 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4184 conn_state = connector->base.state;
4186 crtc = to_intel_crtc(conn_state->crtc);
4190 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4194 crtc_state = to_intel_crtc_state(crtc->base.state);
4196 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4198 if (!crtc_state->base.active)
4201 if (conn_state->commit &&
4202 !try_wait_for_completion(&conn_state->commit->hw_done))
4205 if (!intel_dp_needs_link_retrain(intel_dp))
4208 /* Suppress underruns caused by re-training */
4209 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4210 if (crtc->config->has_pch_encoder)
4211 intel_set_pch_fifo_underrun_reporting(dev_priv,
4212 intel_crtc_pch_transcoder(crtc), false);
4214 intel_dp_start_link_train(intel_dp);
4215 intel_dp_stop_link_train(intel_dp);
4217 /* Keep underrun reporting disabled until things are stable */
4218 intel_wait_for_vblank(dev_priv, crtc->pipe);
4220 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4221 if (crtc->config->has_pch_encoder)
4222 intel_set_pch_fifo_underrun_reporting(dev_priv,
4223 intel_crtc_pch_transcoder(crtc), true);
4229 * If display is now connected check links status,
4230 * there has been known issues of link loss triggering
4233 * Some sinks (eg. ASUS PB287Q) seem to perform some
4234 * weird HPD ping pong during modesets. So we can apparently
4235 * end up with HPD going low during a modeset, and then
4236 * going back up soon after. And once that happens we must
4237 * retrain the link to get a picture. That's in case no
4238 * userspace component reacted to intermittent HPD dip.
4240 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4241 struct intel_connector *connector)
4243 struct drm_modeset_acquire_ctx ctx;
4247 changed = intel_encoder_hotplug(encoder, connector);
4249 drm_modeset_acquire_init(&ctx, 0);
4252 ret = intel_dp_retrain_link(encoder, &ctx);
4254 if (ret == -EDEADLK) {
4255 drm_modeset_backoff(&ctx);
4262 drm_modeset_drop_locks(&ctx);
4263 drm_modeset_acquire_fini(&ctx);
4264 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4270 * According to DP spec
4273 * 2. Configure link according to Receiver Capabilities
4274 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4275 * 4. Check link status on receipt of hot-plug interrupt
4277 * intel_dp_short_pulse - handles short pulse interrupts
4278 * when full detection is not required.
4279 * Returns %true if short pulse is handled and full detection
4280 * is NOT required and %false otherwise.
4283 intel_dp_short_pulse(struct intel_dp *intel_dp)
4285 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4286 u8 sink_irq_vector = 0;
4287 u8 old_sink_count = intel_dp->sink_count;
4291 * Clearing compliance test variables to allow capturing
4292 * of values for next automated test request.
4294 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4297 * Now read the DPCD to see if it's actually running
4298 * If the current value of sink count doesn't match with
4299 * the value that was stored earlier or dpcd read failed
4300 * we need to do full detection
4302 ret = intel_dp_get_dpcd(intel_dp);
4304 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4305 /* No need to proceed if we are going to do full detect */
4309 /* Try to read the source of the interrupt */
4310 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4311 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4312 sink_irq_vector != 0) {
4313 /* Clear interrupt source */
4314 drm_dp_dpcd_writeb(&intel_dp->aux,
4315 DP_DEVICE_SERVICE_IRQ_VECTOR,
4318 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4319 intel_dp_handle_test_request(intel_dp);
4320 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4321 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4324 /* Handle CEC interrupts, if any */
4325 drm_dp_cec_irq(&intel_dp->aux);
4327 /* defer to the hotplug work for link retraining if needed */
4328 if (intel_dp_needs_link_retrain(intel_dp))
4331 intel_psr_short_pulse(intel_dp);
4333 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4334 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4335 /* Send a Hotplug Uevent to userspace to start modeset */
4336 drm_kms_helper_hotplug_event(&dev_priv->drm);
4342 /* XXX this is probably wrong for multiple downstream ports */
4343 static enum drm_connector_status
4344 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4346 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4347 uint8_t *dpcd = intel_dp->dpcd;
4351 lspcon_resume(lspcon);
4353 if (!intel_dp_get_dpcd(intel_dp))
4354 return connector_status_disconnected;
4356 if (intel_dp_is_edp(intel_dp))
4357 return connector_status_connected;
4359 /* if there's no downstream port, we're done */
4360 if (!drm_dp_is_branch(dpcd))
4361 return connector_status_connected;
4363 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4364 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4365 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4367 return intel_dp->sink_count ?
4368 connector_status_connected : connector_status_disconnected;
4371 if (intel_dp_can_mst(intel_dp))
4372 return connector_status_connected;
4374 /* If no HPD, poke DDC gently */
4375 if (drm_probe_ddc(&intel_dp->aux.ddc))
4376 return connector_status_connected;
4378 /* Well we tried, say unknown for unreliable port types */
4379 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4380 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4381 if (type == DP_DS_PORT_TYPE_VGA ||
4382 type == DP_DS_PORT_TYPE_NON_EDID)
4383 return connector_status_unknown;
4385 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4386 DP_DWN_STRM_PORT_TYPE_MASK;
4387 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4388 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4389 return connector_status_unknown;
4392 /* Anything else is out of spec, warn and ignore */
4393 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4394 return connector_status_disconnected;
4397 static enum drm_connector_status
4398 edp_detect(struct intel_dp *intel_dp)
4400 return connector_status_connected;
4403 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4408 switch (encoder->hpd_pin) {
4410 bit = SDE_PORTB_HOTPLUG;
4413 bit = SDE_PORTC_HOTPLUG;
4416 bit = SDE_PORTD_HOTPLUG;
4419 MISSING_CASE(encoder->hpd_pin);
4423 return I915_READ(SDEISR) & bit;
4426 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4428 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4431 switch (encoder->hpd_pin) {
4433 bit = SDE_PORTB_HOTPLUG_CPT;
4436 bit = SDE_PORTC_HOTPLUG_CPT;
4439 bit = SDE_PORTD_HOTPLUG_CPT;
4442 MISSING_CASE(encoder->hpd_pin);
4446 return I915_READ(SDEISR) & bit;
4449 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4454 switch (encoder->hpd_pin) {
4456 bit = SDE_PORTA_HOTPLUG_SPT;
4459 bit = SDE_PORTE_HOTPLUG_SPT;
4462 return cpt_digital_port_connected(encoder);
4465 return I915_READ(SDEISR) & bit;
4468 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4473 switch (encoder->hpd_pin) {
4475 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4478 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4481 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4484 MISSING_CASE(encoder->hpd_pin);
4488 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4491 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4496 switch (encoder->hpd_pin) {
4498 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4501 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4504 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4507 MISSING_CASE(encoder->hpd_pin);
4511 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4514 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4516 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4518 if (encoder->hpd_pin == HPD_PORT_A)
4519 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4521 return ibx_digital_port_connected(encoder);
4524 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4528 if (encoder->hpd_pin == HPD_PORT_A)
4529 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4531 return cpt_digital_port_connected(encoder);
4534 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4538 if (encoder->hpd_pin == HPD_PORT_A)
4539 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4541 return cpt_digital_port_connected(encoder);
4544 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4548 if (encoder->hpd_pin == HPD_PORT_A)
4549 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4551 return cpt_digital_port_connected(encoder);
4554 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4556 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4559 switch (encoder->hpd_pin) {
4561 bit = BXT_DE_PORT_HP_DDIA;
4564 bit = BXT_DE_PORT_HP_DDIB;
4567 bit = BXT_DE_PORT_HP_DDIC;
4570 MISSING_CASE(encoder->hpd_pin);
4574 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4578 * intel_digital_port_connected - is the specified port connected?
4579 * @encoder: intel_encoder
4581 * Return %true if port is connected, %false otherwise.
4583 bool intel_digital_port_connected(struct intel_encoder *encoder)
4585 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4587 if (HAS_GMCH_DISPLAY(dev_priv)) {
4588 if (IS_GM45(dev_priv))
4589 return gm45_digital_port_connected(encoder);
4591 return g4x_digital_port_connected(encoder);
4594 if (IS_GEN5(dev_priv))
4595 return ilk_digital_port_connected(encoder);
4596 else if (IS_GEN6(dev_priv))
4597 return snb_digital_port_connected(encoder);
4598 else if (IS_GEN7(dev_priv))
4599 return ivb_digital_port_connected(encoder);
4600 else if (IS_GEN8(dev_priv))
4601 return bdw_digital_port_connected(encoder);
4602 else if (IS_GEN9_LP(dev_priv))
4603 return bxt_digital_port_connected(encoder);
4605 return spt_digital_port_connected(encoder);
4608 static struct edid *
4609 intel_dp_get_edid(struct intel_dp *intel_dp)
4611 struct intel_connector *intel_connector = intel_dp->attached_connector;
4613 /* use cached edid if we have one */
4614 if (intel_connector->edid) {
4616 if (IS_ERR(intel_connector->edid))
4619 return drm_edid_duplicate(intel_connector->edid);
4621 return drm_get_edid(&intel_connector->base,
4622 &intel_dp->aux.ddc);
4626 intel_dp_set_edid(struct intel_dp *intel_dp)
4628 struct intel_connector *intel_connector = intel_dp->attached_connector;
4631 intel_dp_unset_edid(intel_dp);
4632 edid = intel_dp_get_edid(intel_dp);
4633 intel_connector->detect_edid = edid;
4635 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4636 drm_dp_cec_set_edid(&intel_dp->aux, edid);
4640 intel_dp_unset_edid(struct intel_dp *intel_dp)
4642 struct intel_connector *intel_connector = intel_dp->attached_connector;
4644 drm_dp_cec_unset_edid(&intel_dp->aux);
4645 kfree(intel_connector->detect_edid);
4646 intel_connector->detect_edid = NULL;
4648 intel_dp->has_audio = false;
4652 intel_dp_long_pulse(struct intel_connector *connector,
4653 struct drm_modeset_acquire_ctx *ctx)
4655 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4656 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4657 enum drm_connector_status status;
4658 u8 sink_irq_vector = 0;
4660 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4662 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4664 /* Can't disconnect eDP */
4665 if (intel_dp_is_edp(intel_dp))
4666 status = edp_detect(intel_dp);
4667 else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4668 status = intel_dp_detect_dpcd(intel_dp);
4670 status = connector_status_disconnected;
4672 if (status == connector_status_disconnected) {
4673 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4675 if (intel_dp->is_mst) {
4676 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4678 intel_dp->mst_mgr.mst_state);
4679 intel_dp->is_mst = false;
4680 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4687 if (intel_dp->reset_link_params) {
4688 /* Initial max link lane count */
4689 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4691 /* Initial max link rate */
4692 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4694 intel_dp->reset_link_params = false;
4697 intel_dp_print_rates(intel_dp);
4699 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4700 drm_dp_is_branch(intel_dp->dpcd));
4702 intel_dp_configure_mst(intel_dp);
4704 if (intel_dp->is_mst) {
4706 * If we are in MST mode then this connector
4707 * won't appear connected or have anything
4710 status = connector_status_disconnected;
4714 * If display is now connected check links status,
4715 * there has been known issues of link loss triggering
4718 * Some sinks (eg. ASUS PB287Q) seem to perform some
4719 * weird HPD ping pong during modesets. So we can apparently
4720 * end up with HPD going low during a modeset, and then
4721 * going back up soon after. And once that happens we must
4722 * retrain the link to get a picture. That's in case no
4723 * userspace component reacted to intermittent HPD dip.
4725 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4727 intel_dp_retrain_link(encoder, ctx);
4731 * Clearing NACK and defer counts to get their exact values
4732 * while reading EDID which are required by Compliance tests
4733 * 4.2.2.4 and 4.2.2.5
4735 intel_dp->aux.i2c_nack_count = 0;
4736 intel_dp->aux.i2c_defer_count = 0;
4738 intel_dp_set_edid(intel_dp);
4739 if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4740 status = connector_status_connected;
4741 intel_dp->detect_done = true;
4743 /* Try to read the source of the interrupt */
4744 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4745 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4746 sink_irq_vector != 0) {
4747 /* Clear interrupt source */
4748 drm_dp_dpcd_writeb(&intel_dp->aux,
4749 DP_DEVICE_SERVICE_IRQ_VECTOR,
4752 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4753 intel_dp_handle_test_request(intel_dp);
4754 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4755 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4759 if (status != connector_status_connected && !intel_dp->is_mst)
4760 intel_dp_unset_edid(intel_dp);
4762 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4767 intel_dp_detect(struct drm_connector *connector,
4768 struct drm_modeset_acquire_ctx *ctx,
4771 struct intel_dp *intel_dp = intel_attached_dp(connector);
4772 int status = connector->status;
4774 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4775 connector->base.id, connector->name);
4777 /* If full detect is not performed yet, do a full detect */
4778 if (!intel_dp->detect_done) {
4779 struct drm_crtc *crtc;
4782 crtc = connector->state->crtc;
4784 ret = drm_modeset_lock(&crtc->mutex, ctx);
4789 status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
4792 intel_dp->detect_done = false;
4798 intel_dp_force(struct drm_connector *connector)
4800 struct intel_dp *intel_dp = intel_attached_dp(connector);
4801 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4802 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4804 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4805 connector->base.id, connector->name);
4806 intel_dp_unset_edid(intel_dp);
4808 if (connector->status != connector_status_connected)
4811 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4813 intel_dp_set_edid(intel_dp);
4815 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4818 static int intel_dp_get_modes(struct drm_connector *connector)
4820 struct intel_connector *intel_connector = to_intel_connector(connector);
4823 edid = intel_connector->detect_edid;
4825 int ret = intel_connector_update_modes(connector, edid);
4830 /* if eDP has no EDID, fall back to fixed mode */
4831 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4832 intel_connector->panel.fixed_mode) {
4833 struct drm_display_mode *mode;
4835 mode = drm_mode_duplicate(connector->dev,
4836 intel_connector->panel.fixed_mode);
4838 drm_mode_probed_add(connector, mode);
4847 intel_dp_connector_register(struct drm_connector *connector)
4849 struct intel_dp *intel_dp = intel_attached_dp(connector);
4850 struct drm_device *dev = connector->dev;
4853 ret = intel_connector_register(connector);
4857 i915_debugfs_connector_add(connector);
4859 DRM_DEBUG_KMS("registering %s bus for %s\n",
4860 intel_dp->aux.name, connector->kdev->kobj.name);
4862 intel_dp->aux.dev = connector->kdev;
4863 ret = drm_dp_aux_register(&intel_dp->aux);
4865 drm_dp_cec_register_connector(&intel_dp->aux,
4866 connector->name, dev->dev);
4871 intel_dp_connector_unregister(struct drm_connector *connector)
4873 struct intel_dp *intel_dp = intel_attached_dp(connector);
4875 drm_dp_cec_unregister_connector(&intel_dp->aux);
4876 drm_dp_aux_unregister(&intel_dp->aux);
4877 intel_connector_unregister(connector);
4881 intel_dp_connector_destroy(struct drm_connector *connector)
4883 struct intel_connector *intel_connector = to_intel_connector(connector);
4885 kfree(intel_connector->detect_edid);
4887 if (!IS_ERR_OR_NULL(intel_connector->edid))
4888 kfree(intel_connector->edid);
4891 * Can't call intel_dp_is_edp() since the encoder may have been
4892 * destroyed already.
4894 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4895 intel_panel_fini(&intel_connector->panel);
4897 drm_connector_cleanup(connector);
4901 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4903 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4904 struct intel_dp *intel_dp = &intel_dig_port->dp;
4906 intel_dp_mst_encoder_cleanup(intel_dig_port);
4907 if (intel_dp_is_edp(intel_dp)) {
4908 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4910 * vdd might still be enabled do to the delayed vdd off.
4911 * Make sure vdd is actually turned off here.
4914 edp_panel_vdd_off_sync(intel_dp);
4915 pps_unlock(intel_dp);
4917 if (intel_dp->edp_notifier.notifier_call) {
4918 unregister_reboot_notifier(&intel_dp->edp_notifier);
4919 intel_dp->edp_notifier.notifier_call = NULL;
4923 intel_dp_aux_fini(intel_dp);
4925 drm_encoder_cleanup(encoder);
4926 kfree(intel_dig_port);
4929 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4931 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4933 if (!intel_dp_is_edp(intel_dp))
4937 * vdd might still be enabled do to the delayed vdd off.
4938 * Make sure vdd is actually turned off here.
4940 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4942 edp_panel_vdd_off_sync(intel_dp);
4943 pps_unlock(intel_dp);
4947 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
4950 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
4951 static const struct drm_dp_aux_msg msg = {
4952 .request = DP_AUX_NATIVE_WRITE,
4953 .address = DP_AUX_HDCP_AKSV,
4954 .size = DRM_HDCP_KSV_LEN,
4956 uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
4960 /* Output An first, that's easy */
4961 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
4962 an, DRM_HDCP_AN_LEN);
4963 if (dpcd_ret != DRM_HDCP_AN_LEN) {
4964 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
4965 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
4969 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
4970 * order to get it on the wire, we need to create the AUX header as if
4971 * we were writing the data, and then tickle the hardware to output the
4972 * data once the header is sent out.
4974 intel_dp_aux_header(txbuf, &msg);
4976 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
4977 rxbuf, sizeof(rxbuf),
4978 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
4980 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
4982 } else if (ret == 0) {
4983 DRM_ERROR("Aksv write over DP/AUX was empty\n");
4987 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
4988 return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
4991 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
4995 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
4997 if (ret != DRM_HDCP_KSV_LEN) {
4998 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
4999 return ret >= 0 ? -EIO : ret;
5004 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5009 * For some reason the HDMI and DP HDCP specs call this register
5010 * definition by different names. In the HDMI spec, it's called BSTATUS,
5011 * but in DP it's called BINFO.
5013 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5014 bstatus, DRM_HDCP_BSTATUS_LEN);
5015 if (ret != DRM_HDCP_BSTATUS_LEN) {
5016 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5017 return ret >= 0 ? -EIO : ret;
5023 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5028 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5031 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5032 return ret >= 0 ? -EIO : ret;
5039 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5040 bool *repeater_present)
5045 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5049 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5054 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5058 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5059 ri_prime, DRM_HDCP_RI_LEN);
5060 if (ret != DRM_HDCP_RI_LEN) {
5061 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5062 return ret >= 0 ? -EIO : ret;
5068 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5073 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5076 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5077 return ret >= 0 ? -EIO : ret;
5079 *ksv_ready = bstatus & DP_BSTATUS_READY;
5084 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5085 int num_downstream, u8 *ksv_fifo)
5090 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5091 for (i = 0; i < num_downstream; i += 3) {
5092 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5093 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5094 DP_AUX_HDCP_KSV_FIFO,
5095 ksv_fifo + i * DRM_HDCP_KSV_LEN,
5098 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5100 return ret >= 0 ? -EIO : ret;
5107 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5112 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5115 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5116 DP_AUX_HDCP_V_PRIME(i), part,
5117 DRM_HDCP_V_PRIME_PART_LEN);
5118 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5119 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5120 return ret >= 0 ? -EIO : ret;
5126 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5129 /* Not used for single stream DisplayPort setups */
5134 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5139 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5142 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5146 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5150 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5156 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5160 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5164 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5165 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5166 .read_bksv = intel_dp_hdcp_read_bksv,
5167 .read_bstatus = intel_dp_hdcp_read_bstatus,
5168 .repeater_present = intel_dp_hdcp_repeater_present,
5169 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5170 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5171 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5172 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5173 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5174 .check_link = intel_dp_hdcp_check_link,
5175 .hdcp_capable = intel_dp_hdcp_capable,
5178 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5180 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5182 lockdep_assert_held(&dev_priv->pps_mutex);
5184 if (!edp_have_panel_vdd(intel_dp))
5188 * The VDD bit needs a power domain reference, so if the bit is
5189 * already enabled when we boot or resume, grab this reference and
5190 * schedule a vdd off, so we don't hold on to the reference
5193 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5194 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5196 edp_panel_vdd_schedule_off(intel_dp);
5199 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5201 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5202 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5205 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5206 encoder->port, &pipe))
5209 return INVALID_PIPE;
5212 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5214 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5215 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5216 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5218 if (!HAS_DDI(dev_priv))
5219 intel_dp->DP = I915_READ(intel_dp->output_reg);
5222 lspcon_resume(lspcon);
5224 intel_dp->reset_link_params = true;
5228 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5229 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5231 if (intel_dp_is_edp(intel_dp)) {
5232 /* Reinit the power sequencer, in case BIOS did something with it. */
5233 intel_dp_pps_init(intel_dp);
5234 intel_edp_panel_vdd_sanitize(intel_dp);
5237 pps_unlock(intel_dp);
5240 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5241 .force = intel_dp_force,
5242 .fill_modes = drm_helper_probe_single_connector_modes,
5243 .atomic_get_property = intel_digital_connector_atomic_get_property,
5244 .atomic_set_property = intel_digital_connector_atomic_set_property,
5245 .late_register = intel_dp_connector_register,
5246 .early_unregister = intel_dp_connector_unregister,
5247 .destroy = intel_dp_connector_destroy,
5248 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5249 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5252 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5253 .detect_ctx = intel_dp_detect,
5254 .get_modes = intel_dp_get_modes,
5255 .mode_valid = intel_dp_mode_valid,
5256 .atomic_check = intel_digital_connector_atomic_check,
5259 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5260 .reset = intel_dp_encoder_reset,
5261 .destroy = intel_dp_encoder_destroy,
5265 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5267 struct intel_dp *intel_dp = &intel_dig_port->dp;
5268 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5269 enum irqreturn ret = IRQ_NONE;
5271 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5273 * vdd off can generate a long pulse on eDP which
5274 * would require vdd on to handle it, and thus we
5275 * would end up in an endless cycle of
5276 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5278 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5279 port_name(intel_dig_port->base.port));
5283 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5284 port_name(intel_dig_port->base.port),
5285 long_hpd ? "long" : "short");
5288 intel_dp->reset_link_params = true;
5289 intel_dp->detect_done = false;
5293 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5295 if (intel_dp->is_mst) {
5296 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5298 * If we were in MST mode, and device is not
5299 * there, get out of MST mode
5301 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5302 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5303 intel_dp->is_mst = false;
5304 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5306 intel_dp->detect_done = false;
5311 if (!intel_dp->is_mst) {
5314 handled = intel_dp_short_pulse(intel_dp);
5316 /* Short pulse can signify loss of hdcp authentication */
5317 intel_hdcp_check_link(intel_dp->attached_connector);
5320 intel_dp->detect_done = false;
5328 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5333 /* check the VBT to see whether the eDP is on another port */
5334 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5337 * eDP not supported on g4x. so bail out early just
5338 * for a bit extra safety in case the VBT is bonkers.
5340 if (INTEL_GEN(dev_priv) < 5)
5343 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5346 return intel_bios_is_port_edp(dev_priv, port);
5350 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5352 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5353 enum port port = dp_to_dig_port(intel_dp)->base.port;
5355 if (!IS_G4X(dev_priv) && port != PORT_A)
5356 intel_attach_force_audio_property(connector);
5358 intel_attach_broadcast_rgb_property(connector);
5360 if (intel_dp_is_edp(intel_dp)) {
5361 u32 allowed_scalers;
5363 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5364 if (!HAS_GMCH_DISPLAY(dev_priv))
5365 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5367 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5369 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5374 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5376 intel_dp->panel_power_off_time = ktime_get_boottime();
5377 intel_dp->last_power_on = jiffies;
5378 intel_dp->last_backlight_off = jiffies;
5382 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5384 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5385 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5386 struct pps_registers regs;
5388 intel_pps_get_registers(intel_dp, ®s);
5390 /* Workaround: Need to write PP_CONTROL with the unlock key as
5391 * the very first thing. */
5392 pp_ctl = ironlake_get_pp_control(intel_dp);
5394 pp_on = I915_READ(regs.pp_on);
5395 pp_off = I915_READ(regs.pp_off);
5396 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5397 !HAS_PCH_ICP(dev_priv)) {
5398 I915_WRITE(regs.pp_ctrl, pp_ctl);
5399 pp_div = I915_READ(regs.pp_div);
5402 /* Pull timing values out of registers */
5403 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5404 PANEL_POWER_UP_DELAY_SHIFT;
5406 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5407 PANEL_LIGHT_ON_DELAY_SHIFT;
5409 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5410 PANEL_LIGHT_OFF_DELAY_SHIFT;
5412 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5413 PANEL_POWER_DOWN_DELAY_SHIFT;
5415 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5416 HAS_PCH_ICP(dev_priv)) {
5417 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5418 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5420 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5421 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5426 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5428 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5430 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5434 intel_pps_verify_state(struct intel_dp *intel_dp)
5436 struct edp_power_seq hw;
5437 struct edp_power_seq *sw = &intel_dp->pps_delays;
5439 intel_pps_readout_hw_state(intel_dp, &hw);
5441 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5442 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5443 DRM_ERROR("PPS state mismatch\n");
5444 intel_pps_dump_state("sw", sw);
5445 intel_pps_dump_state("hw", &hw);
5450 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5452 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5453 struct edp_power_seq cur, vbt, spec,
5454 *final = &intel_dp->pps_delays;
5456 lockdep_assert_held(&dev_priv->pps_mutex);
5458 /* already initialized? */
5459 if (final->t11_t12 != 0)
5462 intel_pps_readout_hw_state(intel_dp, &cur);
5464 intel_pps_dump_state("cur", &cur);
5466 vbt = dev_priv->vbt.edp.pps;
5467 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5468 * of 500ms appears to be too short. Ocassionally the panel
5469 * just fails to power back on. Increasing the delay to 800ms
5470 * seems sufficient to avoid this problem.
5472 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5473 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5474 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5477 /* T11_T12 delay is special and actually in units of 100ms, but zero
5478 * based in the hw (so we need to add 100 ms). But the sw vbt
5479 * table multiplies it with 1000 to make it in units of 100usec,
5481 vbt.t11_t12 += 100 * 10;
5483 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5484 * our hw here, which are all in 100usec. */
5485 spec.t1_t3 = 210 * 10;
5486 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5487 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5488 spec.t10 = 500 * 10;
5489 /* This one is special and actually in units of 100ms, but zero
5490 * based in the hw (so we need to add 100 ms). But the sw vbt
5491 * table multiplies it with 1000 to make it in units of 100usec,
5493 spec.t11_t12 = (510 + 100) * 10;
5495 intel_pps_dump_state("vbt", &vbt);
5497 /* Use the max of the register settings and vbt. If both are
5498 * unset, fall back to the spec limits. */
5499 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5501 max(cur.field, vbt.field))
5502 assign_final(t1_t3);
5506 assign_final(t11_t12);
5509 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5510 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5511 intel_dp->backlight_on_delay = get_delay(t8);
5512 intel_dp->backlight_off_delay = get_delay(t9);
5513 intel_dp->panel_power_down_delay = get_delay(t10);
5514 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5517 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5518 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5519 intel_dp->panel_power_cycle_delay);
5521 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5522 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5525 * We override the HW backlight delays to 1 because we do manual waits
5526 * on them. For T8, even BSpec recommends doing it. For T9, if we
5527 * don't do this, we'll end up waiting for the backlight off delay
5528 * twice: once when we do the manual sleep, and once when we disable
5529 * the panel and wait for the PP_STATUS bit to become zero.
5535 * HW has only a 100msec granularity for t11_t12 so round it up
5538 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5542 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5543 bool force_disable_vdd)
5545 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5546 u32 pp_on, pp_off, pp_div, port_sel = 0;
5547 int div = dev_priv->rawclk_freq / 1000;
5548 struct pps_registers regs;
5549 enum port port = dp_to_dig_port(intel_dp)->base.port;
5550 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5552 lockdep_assert_held(&dev_priv->pps_mutex);
5554 intel_pps_get_registers(intel_dp, ®s);
5557 * On some VLV machines the BIOS can leave the VDD
5558 * enabled even on power sequencers which aren't
5559 * hooked up to any port. This would mess up the
5560 * power domain tracking the first time we pick
5561 * one of these power sequencers for use since
5562 * edp_panel_vdd_on() would notice that the VDD was
5563 * already on and therefore wouldn't grab the power
5564 * domain reference. Disable VDD first to avoid this.
5565 * This also avoids spuriously turning the VDD on as
5566 * soon as the new power sequencer gets initialized.
5568 if (force_disable_vdd) {
5569 u32 pp = ironlake_get_pp_control(intel_dp);
5571 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5573 if (pp & EDP_FORCE_VDD)
5574 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5576 pp &= ~EDP_FORCE_VDD;
5578 I915_WRITE(regs.pp_ctrl, pp);
5581 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5582 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5583 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5584 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5585 /* Compute the divisor for the pp clock, simply match the Bspec
5587 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5588 HAS_PCH_ICP(dev_priv)) {
5589 pp_div = I915_READ(regs.pp_ctrl);
5590 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5591 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5592 << BXT_POWER_CYCLE_DELAY_SHIFT);
5594 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5595 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5596 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5599 /* Haswell doesn't have any port selection bits for the panel
5600 * power sequencer any more. */
5601 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5602 port_sel = PANEL_PORT_SELECT_VLV(port);
5603 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5606 port_sel = PANEL_PORT_SELECT_DPA;
5609 port_sel = PANEL_PORT_SELECT_DPC;
5612 port_sel = PANEL_PORT_SELECT_DPD;
5622 I915_WRITE(regs.pp_on, pp_on);
5623 I915_WRITE(regs.pp_off, pp_off);
5624 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5625 HAS_PCH_ICP(dev_priv))
5626 I915_WRITE(regs.pp_ctrl, pp_div);
5628 I915_WRITE(regs.pp_div, pp_div);
5630 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5631 I915_READ(regs.pp_on),
5632 I915_READ(regs.pp_off),
5633 (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5634 HAS_PCH_ICP(dev_priv)) ?
5635 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5636 I915_READ(regs.pp_div));
5639 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5641 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5643 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5644 vlv_initial_power_sequencer_setup(intel_dp);
5646 intel_dp_init_panel_power_sequencer(intel_dp);
5647 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5652 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5653 * @dev_priv: i915 device
5654 * @crtc_state: a pointer to the active intel_crtc_state
5655 * @refresh_rate: RR to be programmed
5657 * This function gets called when refresh rate (RR) has to be changed from
5658 * one frequency to another. Switches can be between high and low RR
5659 * supported by the panel or to any other RR based on media playback (in
5660 * this case, RR value needs to be passed from user space).
5662 * The caller of this function needs to take a lock on dev_priv->drrs.
5664 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5665 const struct intel_crtc_state *crtc_state,
5668 struct intel_encoder *encoder;
5669 struct intel_digital_port *dig_port = NULL;
5670 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5672 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5674 if (refresh_rate <= 0) {
5675 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5679 if (intel_dp == NULL) {
5680 DRM_DEBUG_KMS("DRRS not supported.\n");
5684 dig_port = dp_to_dig_port(intel_dp);
5685 encoder = &dig_port->base;
5688 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5692 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5693 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5697 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5699 index = DRRS_LOW_RR;
5701 if (index == dev_priv->drrs.refresh_rate_type) {
5703 "DRRS requested for previously set RR...ignoring\n");
5707 if (!crtc_state->base.active) {
5708 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5712 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5715 intel_dp_set_m_n(intel_crtc, M1_N1);
5718 intel_dp_set_m_n(intel_crtc, M2_N2);
5722 DRM_ERROR("Unsupported refreshrate type\n");
5724 } else if (INTEL_GEN(dev_priv) > 6) {
5725 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5728 val = I915_READ(reg);
5729 if (index > DRRS_HIGH_RR) {
5730 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5731 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5733 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5735 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5736 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5738 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5740 I915_WRITE(reg, val);
5743 dev_priv->drrs.refresh_rate_type = index;
5745 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5749 * intel_edp_drrs_enable - init drrs struct if supported
5750 * @intel_dp: DP struct
5751 * @crtc_state: A pointer to the active crtc state.
5753 * Initializes frontbuffer_bits and drrs.dp
5755 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5756 const struct intel_crtc_state *crtc_state)
5758 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5760 if (!crtc_state->has_drrs) {
5761 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5765 if (dev_priv->psr.enabled) {
5766 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5770 mutex_lock(&dev_priv->drrs.mutex);
5771 if (WARN_ON(dev_priv->drrs.dp)) {
5772 DRM_ERROR("DRRS already enabled\n");
5776 dev_priv->drrs.busy_frontbuffer_bits = 0;
5778 dev_priv->drrs.dp = intel_dp;
5781 mutex_unlock(&dev_priv->drrs.mutex);
5785 * intel_edp_drrs_disable - Disable DRRS
5786 * @intel_dp: DP struct
5787 * @old_crtc_state: Pointer to old crtc_state.
5790 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5791 const struct intel_crtc_state *old_crtc_state)
5793 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5795 if (!old_crtc_state->has_drrs)
5798 mutex_lock(&dev_priv->drrs.mutex);
5799 if (!dev_priv->drrs.dp) {
5800 mutex_unlock(&dev_priv->drrs.mutex);
5804 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5805 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5806 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5808 dev_priv->drrs.dp = NULL;
5809 mutex_unlock(&dev_priv->drrs.mutex);
5811 cancel_delayed_work_sync(&dev_priv->drrs.work);
5814 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5816 struct drm_i915_private *dev_priv =
5817 container_of(work, typeof(*dev_priv), drrs.work.work);
5818 struct intel_dp *intel_dp;
5820 mutex_lock(&dev_priv->drrs.mutex);
5822 intel_dp = dev_priv->drrs.dp;
5828 * The delayed work can race with an invalidate hence we need to
5832 if (dev_priv->drrs.busy_frontbuffer_bits)
5835 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5836 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5838 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5839 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5843 mutex_unlock(&dev_priv->drrs.mutex);
5847 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5848 * @dev_priv: i915 device
5849 * @frontbuffer_bits: frontbuffer plane tracking bits
5851 * This function gets called everytime rendering on the given planes start.
5852 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5854 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5856 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5857 unsigned int frontbuffer_bits)
5859 struct drm_crtc *crtc;
5862 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5865 cancel_delayed_work(&dev_priv->drrs.work);
5867 mutex_lock(&dev_priv->drrs.mutex);
5868 if (!dev_priv->drrs.dp) {
5869 mutex_unlock(&dev_priv->drrs.mutex);
5873 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5874 pipe = to_intel_crtc(crtc)->pipe;
5876 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5877 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5879 /* invalidate means busy screen hence upclock */
5880 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5881 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5882 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5884 mutex_unlock(&dev_priv->drrs.mutex);
5888 * intel_edp_drrs_flush - Restart Idleness DRRS
5889 * @dev_priv: i915 device
5890 * @frontbuffer_bits: frontbuffer plane tracking bits
5892 * This function gets called every time rendering on the given planes has
5893 * completed or flip on a crtc is completed. So DRRS should be upclocked
5894 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5895 * if no other planes are dirty.
5897 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5899 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5900 unsigned int frontbuffer_bits)
5902 struct drm_crtc *crtc;
5905 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5908 cancel_delayed_work(&dev_priv->drrs.work);
5910 mutex_lock(&dev_priv->drrs.mutex);
5911 if (!dev_priv->drrs.dp) {
5912 mutex_unlock(&dev_priv->drrs.mutex);
5916 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5917 pipe = to_intel_crtc(crtc)->pipe;
5919 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5920 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5922 /* flush means busy screen hence upclock */
5923 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5924 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5925 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5928 * flush also means no more activity hence schedule downclock, if all
5929 * other fbs are quiescent too
5931 if (!dev_priv->drrs.busy_frontbuffer_bits)
5932 schedule_delayed_work(&dev_priv->drrs.work,
5933 msecs_to_jiffies(1000));
5934 mutex_unlock(&dev_priv->drrs.mutex);
5938 * DOC: Display Refresh Rate Switching (DRRS)
5940 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5941 * which enables swtching between low and high refresh rates,
5942 * dynamically, based on the usage scenario. This feature is applicable
5943 * for internal panels.
5945 * Indication that the panel supports DRRS is given by the panel EDID, which
5946 * would list multiple refresh rates for one resolution.
5948 * DRRS is of 2 types - static and seamless.
5949 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5950 * (may appear as a blink on screen) and is used in dock-undock scenario.
5951 * Seamless DRRS involves changing RR without any visual effect to the user
5952 * and can be used during normal system usage. This is done by programming
5953 * certain registers.
5955 * Support for static/seamless DRRS may be indicated in the VBT based on
5956 * inputs from the panel spec.
5958 * DRRS saves power by switching to low RR based on usage scenarios.
5960 * The implementation is based on frontbuffer tracking implementation. When
5961 * there is a disturbance on the screen triggered by user activity or a periodic
5962 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5963 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5966 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5967 * and intel_edp_drrs_flush() are called.
5969 * DRRS can be further extended to support other internal panels and also
5970 * the scenario of video playback wherein RR is set based on the rate
5971 * requested by userspace.
5975 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5976 * @connector: eDP connector
5977 * @fixed_mode: preferred mode of panel
5979 * This function is called only once at driver load to initialize basic
5983 * Downclock mode if panel supports it, else return NULL.
5984 * DRRS support is determined by the presence of downclock mode (apart
5985 * from VBT setting).
5987 static struct drm_display_mode *
5988 intel_dp_drrs_init(struct intel_connector *connector,
5989 struct drm_display_mode *fixed_mode)
5991 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5992 struct drm_display_mode *downclock_mode = NULL;
5994 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5995 mutex_init(&dev_priv->drrs.mutex);
5997 if (INTEL_GEN(dev_priv) <= 6) {
5998 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6002 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6003 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6007 downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6010 if (!downclock_mode) {
6011 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6015 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6017 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6018 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6019 return downclock_mode;
6022 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6023 struct intel_connector *intel_connector)
6025 struct drm_device *dev = intel_dp_to_dev(intel_dp);
6026 struct drm_i915_private *dev_priv = to_i915(dev);
6027 struct drm_connector *connector = &intel_connector->base;
6028 struct drm_display_mode *fixed_mode = NULL;
6029 struct drm_display_mode *downclock_mode = NULL;
6031 struct drm_display_mode *scan;
6033 enum pipe pipe = INVALID_PIPE;
6035 if (!intel_dp_is_edp(intel_dp))
6039 * On IBX/CPT we may get here with LVDS already registered. Since the
6040 * driver uses the only internal power sequencer available for both
6041 * eDP and LVDS bail out early in this case to prevent interfering
6042 * with an already powered-on LVDS power sequencer.
6044 if (intel_get_lvds_encoder(&dev_priv->drm)) {
6045 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6046 DRM_INFO("LVDS was detected, not registering eDP\n");
6053 intel_dp_init_panel_power_timestamps(intel_dp);
6054 intel_dp_pps_init(intel_dp);
6055 intel_edp_panel_vdd_sanitize(intel_dp);
6057 pps_unlock(intel_dp);
6059 /* Cache DPCD and EDID for edp. */
6060 has_dpcd = intel_edp_init_dpcd(intel_dp);
6063 /* if this fails, presume the device is a ghost */
6064 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6068 mutex_lock(&dev->mode_config.mutex);
6069 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6071 if (drm_add_edid_modes(connector, edid)) {
6072 drm_connector_update_edid_property(connector,
6076 edid = ERR_PTR(-EINVAL);
6079 edid = ERR_PTR(-ENOENT);
6081 intel_connector->edid = edid;
6083 /* prefer fixed mode from EDID if available */
6084 list_for_each_entry(scan, &connector->probed_modes, head) {
6085 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6086 fixed_mode = drm_mode_duplicate(dev, scan);
6087 downclock_mode = intel_dp_drrs_init(
6088 intel_connector, fixed_mode);
6093 /* fallback to VBT if available for eDP */
6094 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6095 fixed_mode = drm_mode_duplicate(dev,
6096 dev_priv->vbt.lfp_lvds_vbt_mode);
6098 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6099 connector->display_info.width_mm = fixed_mode->width_mm;
6100 connector->display_info.height_mm = fixed_mode->height_mm;
6103 mutex_unlock(&dev->mode_config.mutex);
6105 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6106 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6107 register_reboot_notifier(&intel_dp->edp_notifier);
6110 * Figure out the current pipe for the initial backlight setup.
6111 * If the current pipe isn't valid, try the PPS pipe, and if that
6112 * fails just assume pipe A.
6114 pipe = vlv_active_pipe(intel_dp);
6116 if (pipe != PIPE_A && pipe != PIPE_B)
6117 pipe = intel_dp->pps_pipe;
6119 if (pipe != PIPE_A && pipe != PIPE_B)
6122 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6126 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6127 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6128 intel_panel_setup_backlight(connector, pipe);
6133 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6135 * vdd might still be enabled do to the delayed vdd off.
6136 * Make sure vdd is actually turned off here.
6139 edp_panel_vdd_off_sync(intel_dp);
6140 pps_unlock(intel_dp);
6145 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6147 struct intel_connector *intel_connector;
6148 struct drm_connector *connector;
6150 intel_connector = container_of(work, typeof(*intel_connector),
6151 modeset_retry_work);
6152 connector = &intel_connector->base;
6153 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6156 /* Grab the locks before changing connector property*/
6157 mutex_lock(&connector->dev->mode_config.mutex);
6158 /* Set connector link status to BAD and send a Uevent to notify
6159 * userspace to do a modeset.
6161 drm_connector_set_link_status_property(connector,
6162 DRM_MODE_LINK_STATUS_BAD);
6163 mutex_unlock(&connector->dev->mode_config.mutex);
6164 /* Send Hotplug uevent so userspace can reprobe */
6165 drm_kms_helper_hotplug_event(connector->dev);
6169 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6170 struct intel_connector *intel_connector)
6172 struct drm_connector *connector = &intel_connector->base;
6173 struct intel_dp *intel_dp = &intel_dig_port->dp;
6174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
6175 struct drm_device *dev = intel_encoder->base.dev;
6176 struct drm_i915_private *dev_priv = to_i915(dev);
6177 enum port port = intel_encoder->port;
6180 /* Initialize the work for modeset in case of link train failure */
6181 INIT_WORK(&intel_connector->modeset_retry_work,
6182 intel_dp_modeset_retry_work_fn);
6184 if (WARN(intel_dig_port->max_lanes < 1,
6185 "Not enough lanes (%d) for DP on port %c\n",
6186 intel_dig_port->max_lanes, port_name(port)))
6189 intel_dp_set_source_rates(intel_dp);
6191 intel_dp->reset_link_params = true;
6192 intel_dp->pps_pipe = INVALID_PIPE;
6193 intel_dp->active_pipe = INVALID_PIPE;
6195 /* intel_dp vfuncs */
6196 if (HAS_DDI(dev_priv))
6197 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6199 /* Preserve the current hw state. */
6200 intel_dp->DP = I915_READ(intel_dp->output_reg);
6201 intel_dp->attached_connector = intel_connector;
6203 if (intel_dp_is_port_edp(dev_priv, port))
6204 type = DRM_MODE_CONNECTOR_eDP;
6206 type = DRM_MODE_CONNECTOR_DisplayPort;
6208 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6209 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6212 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6213 * for DP the encoder type can be set by the caller to
6214 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6216 if (type == DRM_MODE_CONNECTOR_eDP)
6217 intel_encoder->type = INTEL_OUTPUT_EDP;
6219 /* eDP only on port B and/or C on vlv/chv */
6220 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6221 intel_dp_is_edp(intel_dp) &&
6222 port != PORT_B && port != PORT_C))
6225 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6226 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6229 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6230 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6232 if (!HAS_GMCH_DISPLAY(dev_priv))
6233 connector->interlace_allowed = true;
6234 connector->doublescan_allowed = 0;
6236 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6238 intel_dp_aux_init(intel_dp);
6240 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6241 edp_panel_vdd_work);
6243 intel_connector_attach_encoder(intel_connector, intel_encoder);
6245 if (HAS_DDI(dev_priv))
6246 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6248 intel_connector->get_hw_state = intel_connector_get_hw_state;
6250 /* init MST on ports that can support it */
6251 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6252 (port == PORT_B || port == PORT_C ||
6253 port == PORT_D || port == PORT_F))
6254 intel_dp_mst_encoder_init(intel_dig_port,
6255 intel_connector->base.base.id);
6257 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6258 intel_dp_aux_fini(intel_dp);
6259 intel_dp_mst_encoder_cleanup(intel_dig_port);
6263 intel_dp_add_properties(intel_dp, connector);
6265 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6266 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6268 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6271 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6272 * 0xd. Failure to do so will result in spurious interrupts being
6273 * generated on the port when a cable is not attached.
6275 if (IS_G45(dev_priv)) {
6276 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6277 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6283 drm_connector_cleanup(connector);
6288 bool intel_dp_init(struct drm_i915_private *dev_priv,
6289 i915_reg_t output_reg,
6292 struct intel_digital_port *intel_dig_port;
6293 struct intel_encoder *intel_encoder;
6294 struct drm_encoder *encoder;
6295 struct intel_connector *intel_connector;
6297 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6298 if (!intel_dig_port)
6301 intel_connector = intel_connector_alloc();
6302 if (!intel_connector)
6303 goto err_connector_alloc;
6305 intel_encoder = &intel_dig_port->base;
6306 encoder = &intel_encoder->base;
6308 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6309 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6310 "DP %c", port_name(port)))
6311 goto err_encoder_init;
6313 intel_encoder->hotplug = intel_dp_hotplug;
6314 intel_encoder->compute_config = intel_dp_compute_config;
6315 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6316 intel_encoder->get_config = intel_dp_get_config;
6317 intel_encoder->suspend = intel_dp_encoder_suspend;
6318 if (IS_CHERRYVIEW(dev_priv)) {
6319 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6320 intel_encoder->pre_enable = chv_pre_enable_dp;
6321 intel_encoder->enable = vlv_enable_dp;
6322 intel_encoder->disable = vlv_disable_dp;
6323 intel_encoder->post_disable = chv_post_disable_dp;
6324 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6325 } else if (IS_VALLEYVIEW(dev_priv)) {
6326 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6327 intel_encoder->pre_enable = vlv_pre_enable_dp;
6328 intel_encoder->enable = vlv_enable_dp;
6329 intel_encoder->disable = vlv_disable_dp;
6330 intel_encoder->post_disable = vlv_post_disable_dp;
6332 intel_encoder->pre_enable = g4x_pre_enable_dp;
6333 intel_encoder->enable = g4x_enable_dp;
6334 intel_encoder->disable = g4x_disable_dp;
6335 intel_encoder->post_disable = g4x_post_disable_dp;
6338 intel_dig_port->dp.output_reg = output_reg;
6339 intel_dig_port->max_lanes = 4;
6341 intel_encoder->type = INTEL_OUTPUT_DP;
6342 intel_encoder->power_domain = intel_port_to_power_domain(port);
6343 if (IS_CHERRYVIEW(dev_priv)) {
6345 intel_encoder->crtc_mask = 1 << 2;
6347 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6349 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6351 intel_encoder->cloneable = 0;
6352 intel_encoder->port = port;
6354 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6357 intel_infoframe_init(intel_dig_port);
6359 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6360 goto err_init_connector;
6365 drm_encoder_cleanup(encoder);
6367 kfree(intel_connector);
6368 err_connector_alloc:
6369 kfree(intel_dig_port);
6373 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6375 struct intel_encoder *encoder;
6377 for_each_intel_encoder(&dev_priv->drm, encoder) {
6378 struct intel_dp *intel_dp;
6380 if (encoder->type != INTEL_OUTPUT_DDI)
6383 intel_dp = enc_to_intel_dp(&encoder->base);
6385 if (!intel_dp->can_mst)
6388 if (intel_dp->is_mst)
6389 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6393 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6395 struct intel_encoder *encoder;
6397 for_each_intel_encoder(&dev_priv->drm, encoder) {
6398 struct intel_dp *intel_dp;
6401 if (encoder->type != INTEL_OUTPUT_DDI)
6404 intel_dp = enc_to_intel_dp(&encoder->base);
6406 if (!intel_dp->can_mst)
6409 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6411 intel_dp_check_mst_status(intel_dp);