drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_hdcp.h>
  41 #include "intel_drv.h"
  42 #include <drm/i915_drm.h>
  43 #include "i915_drv.h"
  44
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  49 #define DP_DSC_MIN_SUPPORTED_BPC                8
  50 #define DP_DSC_MAX_SUPPORTED_BPC                10
  51
  52 /* DP DSC throughput values used for slice count calculations KPixels/s */
  53 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  54 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  55 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  56
  57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  58 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  59
  60 /* Compliance test status bits  */
  61 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  62 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  63 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  64 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  65
  66 struct dp_link_dpll {
  67         int clock;
  68         struct dpll dpll;
  69 };
  70
  71 static const struct dp_link_dpll g4x_dpll[] = {
  72         { 162000,
  73                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  74         { 270000,
  75                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  76 };
  77
  78 static const struct dp_link_dpll pch_dpll[] = {
  79         { 162000,
  80                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  81         { 270000,
  82                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  83 };
  84
  85 static const struct dp_link_dpll vlv_dpll[] = {
  86         { 162000,
  87                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  88         { 270000,
  89                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  90 };
  91
  92 /*
  93  * CHV supports eDP 1.4 that have  more link rates.
  94  * Below only provides the fixed rate but exclude variable rate.
  95  */
  96 static const struct dp_link_dpll chv_dpll[] = {
  97         /*
  98          * CHV requires to program fractional division for m2.
  99          * m2 is stored in fixed point format using formula below
 100          * (m2_int << 22) | m2_fraction
 101          */
 102         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 103                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 104         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 105                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 106 };
 107
 108 /* Constants for DP DSC configurations */
 109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 110
 111 /* With Single pipe configuration, HW is capable of supporting maximum
 112  * of 4 slices per line.
 113  */
 114 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 115
 116 /**
 117  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 118  * @intel_dp: DP struct
 119  *
 120  * If a CPU or PCH DP output is attached to an eDP panel, this function
 121  * will return true, and false otherwise.
 122  */
 123 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 124 {
 125         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 126
 127         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 128 }
 129
 130 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 131 {
 132         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 133 }
 134
 135 static void intel_dp_link_down(struct intel_encoder *encoder,
 136                                const struct intel_crtc_state *old_crtc_state);
 137 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 139 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 140                                            const struct intel_crtc_state *crtc_state);
 141 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 142                                       enum pipe pipe);
 143 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 144
 145 /* update sink rates from dpcd */
 146 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 147 {
 148         static const int dp_rates[] = {
 149                 162000, 270000, 540000, 810000
 150         };
 151         int i, max_rate;
 152
 153         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 154
 155         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 156                 if (dp_rates[i] > max_rate)
 157                         break;
 158                 intel_dp->sink_rates[i] = dp_rates[i];
 159         }
 160
 161         intel_dp->num_sink_rates = i;
 162 }
 163
 164 /* Get length of rates array potentially limited by max_rate. */
 165 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 166 {
 167         int i;
 168
 169         /* Limit results by potentially reduced max rate */
 170         for (i = 0; i < len; i++) {
 171                 if (rates[len - i - 1] <= max_rate)
 172                         return len - i;
 173         }
 174
 175         return 0;
 176 }
 177
 178 /* Get length of common rates array potentially limited by max_rate. */
 179 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 180                                           int max_rate)
 181 {
 182         return intel_dp_rate_limit_len(intel_dp->common_rates,
 183                                        intel_dp->num_common_rates, max_rate);
 184 }
 185
 186 /* Theoretical max between source and sink */
 187 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 188 {
 189         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 190 }
 191
 192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 193 {
 194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 195         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 197         u32 lane_info;
 198
 199         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 200                 return 4;
 201
 202         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 203                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 204                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 205
 206         switch (lane_info) {
 207         default:
 208                 MISSING_CASE(lane_info);
 209         case 1:
 210         case 2:
 211         case 4:
 212         case 8:
 213                 return 1;
 214         case 3:
 215         case 12:
 216                 return 2;
 217         case 15:
 218                 return 4;
 219         }
 220 }
 221
 222 /* Theoretical max between source and sink */
 223 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 224 {
 225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 226         int source_max = intel_dig_port->max_lanes;
 227         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 228         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 static int
 258 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 259 {
 260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 261         struct intel_encoder *encoder = &intel_dig_port->base;
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         int max_dotclk = dev_priv->max_dotclk_freq;
 264         int ds_max_dotclk;
 265
 266         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 267
 268         if (type != DP_DS_PORT_TYPE_VGA)
 269                 return max_dotclk;
 270
 271         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 272                                                     intel_dp->downstream_ports);
 273
 274         if (ds_max_dotclk != 0)
 275                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 276
 277         return max_dotclk;
 278 }
 279
 280 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 281 {
 282         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 283         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 284         enum port port = dig_port->base.port;
 285
 286         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 287
 288         /* Low voltage SKUs are limited to max of 5.4G */
 289         if (voltage == VOLTAGE_INFO_0_85V)
 290                 return 540000;
 291
 292         /* For this SKU 8.1G is supported in all ports */
 293         if (IS_CNL_WITH_PORT_F(dev_priv))
 294                 return 810000;
 295
 296         /* For other SKUs, max rate on ports A and D is 5.4G */
 297         if (port == PORT_A || port == PORT_D)
 298                 return 540000;
 299
 300         return 810000;
 301 }
 302
 303 static int icl_max_source_rate(struct intel_dp *intel_dp)
 304 {
 305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 306         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 307         enum port port = dig_port->base.port;
 308
 309         if (intel_port_is_combophy(dev_priv, port) &&
 310             !intel_dp_is_edp(intel_dp))
 311                 return 540000;
 312
 313         return 810000;
 314 }
 315
 316 static void
 317 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 318 {
 319         /* The values must be in increasing order */
 320         static const int cnl_rates[] = {
 321                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 322         };
 323         static const int bxt_rates[] = {
 324                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 325         };
 326         static const int skl_rates[] = {
 327                 162000, 216000, 270000, 324000, 432000, 540000
 328         };
 329         static const int hsw_rates[] = {
 330                 162000, 270000, 540000
 331         };
 332         static const int g4x_rates[] = {
 333                 162000, 270000
 334         };
 335         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 337         const struct ddi_vbt_port_info *info =
 338                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 339         const int *source_rates;
 340         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 341
 342         /* This should only be done once */
 343         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 344
 345         if (INTEL_GEN(dev_priv) >= 10) {
 346                 source_rates = cnl_rates;
 347                 size = ARRAY_SIZE(cnl_rates);
 348                 if (IS_GEN(dev_priv, 10))
 349                         max_rate = cnl_max_source_rate(intel_dp);
 350                 else
 351                         max_rate = icl_max_source_rate(intel_dp);
 352         } else if (IS_GEN9_LP(dev_priv)) {
 353                 source_rates = bxt_rates;
 354                 size = ARRAY_SIZE(bxt_rates);
 355         } else if (IS_GEN9_BC(dev_priv)) {
 356                 source_rates = skl_rates;
 357                 size = ARRAY_SIZE(skl_rates);
 358         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 359                    IS_BROADWELL(dev_priv)) {
 360                 source_rates = hsw_rates;
 361                 size = ARRAY_SIZE(hsw_rates);
 362         } else {
 363                 source_rates = g4x_rates;
 364                 size = ARRAY_SIZE(g4x_rates);
 365         }
 366
 367         if (max_rate && vbt_max_rate)
 368                 max_rate = min(max_rate, vbt_max_rate);
 369         else if (vbt_max_rate)
 370                 max_rate = vbt_max_rate;
 371
 372         if (max_rate)
 373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 374
 375         intel_dp->source_rates = source_rates;
 376         intel_dp->num_source_rates = size;
 377 }
 378
 379 static int intersect_rates(const int *source_rates, int source_len,
 380                            const int *sink_rates, int sink_len,
 381                            int *common_rates)
 382 {
 383         int i = 0, j = 0, k = 0;
 384
 385         while (i < source_len && j < sink_len) {
 386                 if (source_rates[i] == sink_rates[j]) {
 387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 388                                 return k;
 389                         common_rates[k] = source_rates[i];
 390                         ++k;
 391                         ++i;
 392                         ++j;
 393                 } else if (source_rates[i] < sink_rates[j]) {
 394                         ++i;
 395                 } else {
 396                         ++j;
 397                 }
 398         }
 399         return k;
 400 }
 401
 402 /* return index of rate in rates array, or -1 if not found */
 403 static int intel_dp_rate_index(const int *rates, int len, int rate)
 404 {
 405         int i;
 406
 407         for (i = 0; i < len; i++)
 408                 if (rate == rates[i])
 409                         return i;
 410
 411         return -1;
 412 }
 413
 414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 415 {
 416         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 417
 418         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 419                                                      intel_dp->num_source_rates,
 420                                                      intel_dp->sink_rates,
 421                                                      intel_dp->num_sink_rates,
 422                                                      intel_dp->common_rates);
 423
 424         /* Paranoia, there should always be something in common. */
 425         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 426                 intel_dp->common_rates[0] = 162000;
 427                 intel_dp->num_common_rates = 1;
 428         }
 429 }
 430
 431 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 432                                        uint8_t lane_count)
 433 {
 434         /*
 435          * FIXME: we need to synchronize the current link parameters with
 436          * hardware readout. Currently fast link training doesn't work on
 437          * boot-up.
 438          */
 439         if (link_rate == 0 ||
 440             link_rate > intel_dp->max_link_rate)
 441                 return false;
 442
 443         if (lane_count == 0 ||
 444             lane_count > intel_dp_max_lane_count(intel_dp))
 445                 return false;
 446
 447         return true;
 448 }
 449
 450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 451                                                      int link_rate,
 452                                                      uint8_t lane_count)
 453 {
 454         const struct drm_display_mode *fixed_mode =
 455                 intel_dp->attached_connector->panel.fixed_mode;
 456         int mode_rate, max_rate;
 457
 458         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 459         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 460         if (mode_rate > max_rate)
 461                 return false;
 462
 463         return true;
 464 }
 465
 466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 467                                             int link_rate, uint8_t lane_count)
 468 {
 469         int index;
 470
 471         index = intel_dp_rate_index(intel_dp->common_rates,
 472                                     intel_dp->num_common_rates,
 473                                     link_rate);
 474         if (index > 0) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp->common_rates[index - 1],
 478                                                               lane_count)) {
 479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 480                         return 0;
 481                 }
 482                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 483                 intel_dp->max_link_lane_count = lane_count;
 484         } else if (lane_count > 1) {
 485                 if (intel_dp_is_edp(intel_dp) &&
 486                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 487                                                               intel_dp_max_common_rate(intel_dp),
 488                                                               lane_count >> 1)) {
 489                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 490                         return 0;
 491                 }
 492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 493                 intel_dp->max_link_lane_count = lane_count >> 1;
 494         } else {
 495                 DRM_ERROR("Link Training Unsuccessful\n");
 496                 return -1;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static enum drm_mode_status
 503 intel_dp_mode_valid(struct drm_connector *connector,
 504                     struct drm_display_mode *mode)
 505 {
 506         struct intel_dp *intel_dp = intel_attached_dp(connector);
 507         struct intel_connector *intel_connector = to_intel_connector(connector);
 508         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 509         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 510         int target_clock = mode->clock;
 511         int max_rate, mode_rate, max_lanes, max_link_clock;
 512         int max_dotclk;
 513         u16 dsc_max_output_bpp = 0;
 514         u8 dsc_slice_count = 0;
 515
 516         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 517                 return MODE_NO_DBLESCAN;
 518
 519         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 520
 521         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 522                 if (mode->hdisplay > fixed_mode->hdisplay)
 523                         return MODE_PANEL;
 524
 525                 if (mode->vdisplay > fixed_mode->vdisplay)
 526                         return MODE_PANEL;
 527
 528                 target_clock = fixed_mode->clock;
 529         }
 530
 531         max_link_clock = intel_dp_max_link_rate(intel_dp);
 532         max_lanes = intel_dp_max_lane_count(intel_dp);
 533
 534         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 535         mode_rate = intel_dp_link_required(target_clock, 18);
 536
 537         /*
 538          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 539          * integer value since we support only integer values of bpp.
 540          */
 541         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 542             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 543                 if (intel_dp_is_edp(intel_dp)) {
 544                         dsc_max_output_bpp =
 545                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 546                         dsc_slice_count =
 547                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 548                                                                 true);
 549                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 550                         dsc_max_output_bpp =
 551                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 552                                                             max_lanes,
 553                                                             target_clock,
 554                                                             mode->hdisplay) >> 4;
 555                         dsc_slice_count =
 556                                 intel_dp_dsc_get_slice_count(intel_dp,
 557                                                              target_clock,
 558                                                              mode->hdisplay);
 559                 }
 560         }
 561
 562         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 563             target_clock > max_dotclk)
 564                 return MODE_CLOCK_HIGH;
 565
 566         if (mode->clock < 10000)
 567                 return MODE_CLOCK_LOW;
 568
 569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 570                 return MODE_H_ILLEGAL;
 571
 572         return MODE_OK;
 573 }
 574
 575 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 576 {
 577         int     i;
 578         uint32_t v = 0;
 579
 580         if (src_bytes > 4)
 581                 src_bytes = 4;
 582         for (i = 0; i < src_bytes; i++)
 583                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 584         return v;
 585 }
 586
 587 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 588 {
 589         int i;
 590         if (dst_bytes > 4)
 591                 dst_bytes = 4;
 592         for (i = 0; i < dst_bytes; i++)
 593                 dst[i] = src >> ((3-i) * 8);
 594 }
 595
 596 static void
 597 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 598 static void
 599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 600                                               bool force_disable_vdd);
 601 static void
 602 intel_dp_pps_init(struct intel_dp *intel_dp);
 603
 604 static intel_wakeref_t
 605 pps_lock(struct intel_dp *intel_dp)
 606 {
 607         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 608         intel_wakeref_t wakeref;
 609
 610         /*
 611          * See intel_power_sequencer_reset() why we need
 612          * a power domain reference here.
 613          */
 614         wakeref = intel_display_power_get(dev_priv,
 615                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 616
 617         mutex_lock(&dev_priv->pps_mutex);
 618
 619         return wakeref;
 620 }
 621
 622 static intel_wakeref_t
 623 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 624 {
 625         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 626
 627         mutex_unlock(&dev_priv->pps_mutex);
 628         intel_display_power_put(dev_priv,
 629                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 630                                 wakeref);
 631         return 0;
 632 }
 633
 634 #define with_pps_lock(dp, wf) \
 635         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 636
 637 static void
 638 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 639 {
 640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 641         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 642         enum pipe pipe = intel_dp->pps_pipe;
 643         bool pll_enabled, release_cl_override = false;
 644         enum dpio_phy phy = DPIO_PHY(pipe);
 645         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 646         uint32_t DP;
 647
 648         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 649                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 650                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 651                 return;
 652
 653         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 654                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 655
 656         /* Preserve the BIOS-computed detected bit. This is
 657          * supposed to be read-only.
 658          */
 659         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 660         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 661         DP |= DP_PORT_WIDTH(1);
 662         DP |= DP_LINK_TRAIN_PAT_1;
 663
 664         if (IS_CHERRYVIEW(dev_priv))
 665                 DP |= DP_PIPE_SEL_CHV(pipe);
 666         else
 667                 DP |= DP_PIPE_SEL(pipe);
 668
 669         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 670
 671         /*
 672          * The DPLL for the pipe must be enabled for this to work.
 673          * So enable temporarily it if it's not already enabled.
 674          */
 675         if (!pll_enabled) {
 676                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 677                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 678
 679                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 680                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 681                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 682                                   pipe_name(pipe));
 683                         return;
 684                 }
 685         }
 686
 687         /*
 688          * Similar magic as in intel_dp_enable_port().
 689          * We _must_ do this port enable + disable trick
 690          * to make this power sequencer lock onto the port.
 691          * Otherwise even VDD force bit won't work.
 692          */
 693         I915_WRITE(intel_dp->output_reg, DP);
 694         POSTING_READ(intel_dp->output_reg);
 695
 696         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 697         POSTING_READ(intel_dp->output_reg);
 698
 699         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 700         POSTING_READ(intel_dp->output_reg);
 701
 702         if (!pll_enabled) {
 703                 vlv_force_pll_off(dev_priv, pipe);
 704
 705                 if (release_cl_override)
 706                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 707         }
 708 }
 709
 710 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 711 {
 712         struct intel_encoder *encoder;
 713         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 714
 715         /*
 716          * We don't have power sequencer currently.
 717          * Pick one that's not used by other ports.
 718          */
 719         for_each_intel_dp(&dev_priv->drm, encoder) {
 720                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 721
 722                 if (encoder->type == INTEL_OUTPUT_EDP) {
 723                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 724                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 725
 726                         if (intel_dp->pps_pipe != INVALID_PIPE)
 727                                 pipes &= ~(1 << intel_dp->pps_pipe);
 728                 } else {
 729                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 730
 731                         if (intel_dp->active_pipe != INVALID_PIPE)
 732                                 pipes &= ~(1 << intel_dp->active_pipe);
 733                 }
 734         }
 735
 736         if (pipes == 0)
 737                 return INVALID_PIPE;
 738
 739         return ffs(pipes) - 1;
 740 }
 741
 742 static enum pipe
 743 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 744 {
 745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 747         enum pipe pipe;
 748
 749         lockdep_assert_held(&dev_priv->pps_mutex);
 750
 751         /* We should never land here with regular DP ports */
 752         WARN_ON(!intel_dp_is_edp(intel_dp));
 753
 754         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 755                 intel_dp->active_pipe != intel_dp->pps_pipe);
 756
 757         if (intel_dp->pps_pipe != INVALID_PIPE)
 758                 return intel_dp->pps_pipe;
 759
 760         pipe = vlv_find_free_pps(dev_priv);
 761
 762         /*
 763          * Didn't find one. This should not happen since there
 764          * are two power sequencers and up to two eDP ports.
 765          */
 766         if (WARN_ON(pipe == INVALID_PIPE))
 767                 pipe = PIPE_A;
 768
 769         vlv_steal_power_sequencer(dev_priv, pipe);
 770         intel_dp->pps_pipe = pipe;
 771
 772         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 773                       pipe_name(intel_dp->pps_pipe),
 774                       port_name(intel_dig_port->base.port));
 775
 776         /* init power sequencer on this pipe and port */
 777         intel_dp_init_panel_power_sequencer(intel_dp);
 778         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 779
 780         /*
 781          * Even vdd force doesn't work until we've made
 782          * the power sequencer lock in on the port.
 783          */
 784         vlv_power_sequencer_kick(intel_dp);
 785
 786         return intel_dp->pps_pipe;
 787 }
 788
 789 static int
 790 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 791 {
 792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 793         int backlight_controller = dev_priv->vbt.backlight.controller;
 794
 795         lockdep_assert_held(&dev_priv->pps_mutex);
 796
 797         /* We should never land here with regular DP ports */
 798         WARN_ON(!intel_dp_is_edp(intel_dp));
 799
 800         if (!intel_dp->pps_reset)
 801                 return backlight_controller;
 802
 803         intel_dp->pps_reset = false;
 804
 805         /*
 806          * Only the HW needs to be reprogrammed, the SW state is fixed and
 807          * has been setup during connector init.
 808          */
 809         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 810
 811         return backlight_controller;
 812 }
 813
 814 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 815                                enum pipe pipe);
 816
 817 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 818                                enum pipe pipe)
 819 {
 820         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 821 }
 822
 823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 824                                 enum pipe pipe)
 825 {
 826         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 827 }
 828
 829 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 830                          enum pipe pipe)
 831 {
 832         return true;
 833 }
 834
 835 static enum pipe
 836 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 837                      enum port port,
 838                      vlv_pipe_check pipe_check)
 839 {
 840         enum pipe pipe;
 841
 842         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 843                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 844                         PANEL_PORT_SELECT_MASK;
 845
 846                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 847                         continue;
 848
 849                 if (!pipe_check(dev_priv, pipe))
 850                         continue;
 851
 852                 return pipe;
 853         }
 854
 855         return INVALID_PIPE;
 856 }
 857
 858 static void
 859 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 860 {
 861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 863         enum port port = intel_dig_port->base.port;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* try to find a pipe with this port selected */
 868         /* first pick one where the panel is on */
 869         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 870                                                   vlv_pipe_has_pp_on);
 871         /* didn't find one? pick one where vdd is on */
 872         if (intel_dp->pps_pipe == INVALID_PIPE)
 873                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 874                                                           vlv_pipe_has_vdd_on);
 875         /* didn't find one? pick one with just the correct port */
 876         if (intel_dp->pps_pipe == INVALID_PIPE)
 877                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 878                                                           vlv_pipe_any);
 879
 880         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 881         if (intel_dp->pps_pipe == INVALID_PIPE) {
 882                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 883                               port_name(port));
 884                 return;
 885         }
 886
 887         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 888                       port_name(port), pipe_name(intel_dp->pps_pipe));
 889
 890         intel_dp_init_panel_power_sequencer(intel_dp);
 891         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 892 }
 893
 894 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 895 {
 896         struct intel_encoder *encoder;
 897
 898         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 899                     !IS_GEN9_LP(dev_priv)))
 900                 return;
 901
 902         /*
 903          * We can't grab pps_mutex here due to deadlock with power_domain
 904          * mutex when power_domain functions are called while holding pps_mutex.
 905          * That also means that in order to use pps_pipe the code needs to
 906          * hold both a power domain reference and pps_mutex, and the power domain
 907          * reference get/put must be done while _not_ holding pps_mutex.
 908          * pps_{lock,unlock}() do these steps in the correct order, so one
 909          * should use them always.
 910          */
 911
 912         for_each_intel_dp(&dev_priv->drm, encoder) {
 913                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 914
 915                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 916
 917                 if (encoder->type != INTEL_OUTPUT_EDP)
 918                         continue;
 919
 920                 if (IS_GEN9_LP(dev_priv))
 921                         intel_dp->pps_reset = true;
 922                 else
 923                         intel_dp->pps_pipe = INVALID_PIPE;
 924         }
 925 }
 926
 927 struct pps_registers {
 928         i915_reg_t pp_ctrl;
 929         i915_reg_t pp_stat;
 930         i915_reg_t pp_on;
 931         i915_reg_t pp_off;
 932         i915_reg_t pp_div;
 933 };
 934
 935 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 936                                     struct pps_registers *regs)
 937 {
 938         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 939         int pps_idx = 0;
 940
 941         memset(regs, 0, sizeof(*regs));
 942
 943         if (IS_GEN9_LP(dev_priv))
 944                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 945         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 946                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 947
 948         regs->pp_ctrl = PP_CONTROL(pps_idx);
 949         regs->pp_stat = PP_STATUS(pps_idx);
 950         regs->pp_on = PP_ON_DELAYS(pps_idx);
 951         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 952         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 953             !HAS_PCH_ICP(dev_priv))
 954                 regs->pp_div = PP_DIVISOR(pps_idx);
 955 }
 956
 957 static i915_reg_t
 958 _pp_ctrl_reg(struct intel_dp *intel_dp)
 959 {
 960         struct pps_registers regs;
 961
 962         intel_pps_get_registers(intel_dp, &regs);
 963
 964         return regs.pp_ctrl;
 965 }
 966
 967 static i915_reg_t
 968 _pp_stat_reg(struct intel_dp *intel_dp)
 969 {
 970         struct pps_registers regs;
 971
 972         intel_pps_get_registers(intel_dp, &regs);
 973
 974         return regs.pp_stat;
 975 }
 976
 977 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 978    This function only applicable when panel PM state is not to be tracked */
 979 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 980                               void *unused)
 981 {
 982         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 983                                                  edp_notifier);
 984         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 985         intel_wakeref_t wakeref;
 986
 987         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 988                 return 0;
 989
 990         with_pps_lock(intel_dp, wakeref) {
 991                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 992                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 993                         i915_reg_t pp_ctrl_reg, pp_div_reg;
 994                         u32 pp_div;
 995
 996                         pp_ctrl_reg = PP_CONTROL(pipe);
 997                         pp_div_reg  = PP_DIVISOR(pipe);
 998                         pp_div = I915_READ(pp_div_reg);
 999                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1000
1001                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1002                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1003                         I915_WRITE(pp_ctrl_reg,
1004                                    PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1005                         msleep(intel_dp->panel_power_cycle_delay);
1006                 }
1007         }
1008
1009         return 0;
1010 }
1011
1012 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1013 {
1014         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1015
1016         lockdep_assert_held(&dev_priv->pps_mutex);
1017
1018         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1019             intel_dp->pps_pipe == INVALID_PIPE)
1020                 return false;
1021
1022         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1023 }
1024
1025 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1026 {
1027         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1028
1029         lockdep_assert_held(&dev_priv->pps_mutex);
1030
1031         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1032             intel_dp->pps_pipe == INVALID_PIPE)
1033                 return false;
1034
1035         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1036 }
1037
1038 static void
1039 intel_dp_check_edp(struct intel_dp *intel_dp)
1040 {
1041         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1042
1043         if (!intel_dp_is_edp(intel_dp))
1044                 return;
1045
1046         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1047                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1048                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1049                               I915_READ(_pp_stat_reg(intel_dp)),
1050                               I915_READ(_pp_ctrl_reg(intel_dp)));
1051         }
1052 }
1053
1054 static uint32_t
1055 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1056 {
1057         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1058         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1059         uint32_t status;
1060         bool done;
1061
1062 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1063         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1064                                   msecs_to_jiffies_timeout(10));
1065         if (!done)
1066                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1067 #undef C
1068
1069         return status;
1070 }
1071
1072 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1073 {
1074         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1075
1076         if (index)
1077                 return 0;
1078
1079         /*
1080          * The clock divider is based off the hrawclk, and would like to run at
1081          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1082          */
1083         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1084 }
1085
1086 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1087 {
1088         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1089         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1090
1091         if (index)
1092                 return 0;
1093
1094         /*
1095          * The clock divider is based off the cdclk or PCH rawclk, and would
1096          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1097          * divide by 2000 and use that
1098          */
1099         if (dig_port->aux_ch == AUX_CH_A)
1100                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1101         else
1102                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1103 }
1104
1105 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1106 {
1107         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1108         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1109
1110         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1111                 /* Workaround for non-ULT HSW */
1112                 switch (index) {
1113                 case 0: return 63;
1114                 case 1: return 72;
1115                 default: return 0;
1116                 }
1117         }
1118
1119         return ilk_get_aux_clock_divider(intel_dp, index);
1120 }
1121
1122 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1123 {
1124         /*
1125          * SKL doesn't need us to program the AUX clock divider (Hardware will
1126          * derive the clock from CDCLK automatically). We still implement the
1127          * get_aux_clock_divider vfunc to plug-in into the existing code.
1128          */
1129         return index ? 0 : 1;
1130 }
1131
1132 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1133                                      int send_bytes,
1134                                      uint32_t aux_clock_divider)
1135 {
1136         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1137         struct drm_i915_private *dev_priv =
1138                         to_i915(intel_dig_port->base.base.dev);
1139         uint32_t precharge, timeout;
1140
1141         if (IS_GEN(dev_priv, 6))
1142                 precharge = 3;
1143         else
1144                 precharge = 5;
1145
1146         if (IS_BROADWELL(dev_priv))
1147                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1148         else
1149                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1150
1151         return DP_AUX_CH_CTL_SEND_BUSY |
1152                DP_AUX_CH_CTL_DONE |
1153                DP_AUX_CH_CTL_INTERRUPT |
1154                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1155                timeout |
1156                DP_AUX_CH_CTL_RECEIVE_ERROR |
1157                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1158                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1159                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1160 }
1161
1162 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1163                                       int send_bytes,
1164                                       uint32_t unused)
1165 {
1166         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167         uint32_t ret;
1168
1169         ret = DP_AUX_CH_CTL_SEND_BUSY |
1170               DP_AUX_CH_CTL_DONE |
1171               DP_AUX_CH_CTL_INTERRUPT |
1172               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1173               DP_AUX_CH_CTL_TIME_OUT_MAX |
1174               DP_AUX_CH_CTL_RECEIVE_ERROR |
1175               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1176               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1177               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1178
1179         if (intel_dig_port->tc_type == TC_PORT_TBT)
1180                 ret |= DP_AUX_CH_CTL_TBT_IO;
1181
1182         return ret;
1183 }
1184
1185 static int
1186 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1187                   const uint8_t *send, int send_bytes,
1188                   uint8_t *recv, int recv_size,
1189                   u32 aux_send_ctl_flags)
1190 {
1191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192         struct drm_i915_private *dev_priv =
1193                         to_i915(intel_dig_port->base.base.dev);
1194         i915_reg_t ch_ctl, ch_data[5];
1195         uint32_t aux_clock_divider;
1196         intel_wakeref_t wakeref;
1197         int i, ret, recv_bytes;
1198         int try, clock = 0;
1199         uint32_t status;
1200         bool vdd;
1201
1202         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1203         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1204                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1205
1206         wakeref = pps_lock(intel_dp);
1207
1208         /*
1209          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1210          * In such cases we want to leave VDD enabled and it's up to upper layers
1211          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1212          * ourselves.
1213          */
1214         vdd = edp_panel_vdd_on(intel_dp);
1215
1216         /* dp aux is extremely sensitive to irq latency, hence request the
1217          * lowest possible wakeup latency and so prevent the cpu from going into
1218          * deep sleep states.
1219          */
1220         pm_qos_update_request(&dev_priv->pm_qos, 0);
1221
1222         intel_dp_check_edp(intel_dp);
1223
1224         /* Try to wait for any previous AUX channel activity */
1225         for (try = 0; try < 3; try++) {
1226                 status = I915_READ_NOTRACE(ch_ctl);
1227                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1228                         break;
1229                 msleep(1);
1230         }
1231
1232         if (try == 3) {
1233                 static u32 last_status = -1;
1234                 const u32 status = I915_READ(ch_ctl);
1235
1236                 if (status != last_status) {
1237                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1238                              status);
1239                         last_status = status;
1240                 }
1241
1242                 ret = -EBUSY;
1243                 goto out;
1244         }
1245
1246         /* Only 5 data registers! */
1247         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1248                 ret = -E2BIG;
1249                 goto out;
1250         }
1251
1252         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1253                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1254                                                           send_bytes,
1255                                                           aux_clock_divider);
1256
1257                 send_ctl |= aux_send_ctl_flags;
1258
1259                 /* Must try at least 3 times according to DP spec */
1260                 for (try = 0; try < 5; try++) {
1261                         /* Load the send data into the aux channel data registers */
1262                         for (i = 0; i < send_bytes; i += 4)
1263                                 I915_WRITE(ch_data[i >> 2],
1264                                            intel_dp_pack_aux(send + i,
1265                                                              send_bytes - i));
1266
1267                         /* Send the command and wait for it to complete */
1268                         I915_WRITE(ch_ctl, send_ctl);
1269
1270                         status = intel_dp_aux_wait_done(intel_dp);
1271
1272                         /* Clear done status and any errors */
1273                         I915_WRITE(ch_ctl,
1274                                    status |
1275                                    DP_AUX_CH_CTL_DONE |
1276                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1277                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1278
1279                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1280                          *   400us delay required for errors and timeouts
1281                          *   Timeout errors from the HW already meet this
1282                          *   requirement so skip to next iteration
1283                          */
1284                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1285                                 continue;
1286
1287                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1288                                 usleep_range(400, 500);
1289                                 continue;
1290                         }
1291                         if (status & DP_AUX_CH_CTL_DONE)
1292                                 goto done;
1293                 }
1294         }
1295
1296         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1297                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1298                 ret = -EBUSY;
1299                 goto out;
1300         }
1301
1302 done:
1303         /* Check for timeout or receive error.
1304          * Timeouts occur when the sink is not connected
1305          */
1306         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1307                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1308                 ret = -EIO;
1309                 goto out;
1310         }
1311
1312         /* Timeouts occur when the device isn't connected, so they're
1313          * "normal" -- don't fill the kernel log with these */
1314         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1315                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1316                 ret = -ETIMEDOUT;
1317                 goto out;
1318         }
1319
1320         /* Unload any bytes sent back from the other side */
1321         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1322                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1323
1324         /*
1325          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1326          * We have no idea of what happened so we return -EBUSY so
1327          * drm layer takes care for the necessary retries.
1328          */
1329         if (recv_bytes == 0 || recv_bytes > 20) {
1330                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1331                               recv_bytes);
1332                 ret = -EBUSY;
1333                 goto out;
1334         }
1335
1336         if (recv_bytes > recv_size)
1337                 recv_bytes = recv_size;
1338
1339         for (i = 0; i < recv_bytes; i += 4)
1340                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1341                                     recv + i, recv_bytes - i);
1342
1343         ret = recv_bytes;
1344 out:
1345         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1346
1347         if (vdd)
1348                 edp_panel_vdd_off(intel_dp, false);
1349
1350         pps_unlock(intel_dp, wakeref);
1351
1352         return ret;
1353 }
1354
1355 #define BARE_ADDRESS_SIZE       3
1356 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1357
1358 static void
1359 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1360                     const struct drm_dp_aux_msg *msg)
1361 {
1362         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1363         txbuf[1] = (msg->address >> 8) & 0xff;
1364         txbuf[2] = msg->address & 0xff;
1365         txbuf[3] = msg->size - 1;
1366 }
1367
1368 static ssize_t
1369 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1370 {
1371         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1372         uint8_t txbuf[20], rxbuf[20];
1373         size_t txsize, rxsize;
1374         int ret;
1375
1376         intel_dp_aux_header(txbuf, msg);
1377
1378         switch (msg->request & ~DP_AUX_I2C_MOT) {
1379         case DP_AUX_NATIVE_WRITE:
1380         case DP_AUX_I2C_WRITE:
1381         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1382                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1383                 rxsize = 2; /* 0 or 1 data bytes */
1384
1385                 if (WARN_ON(txsize > 20))
1386                         return -E2BIG;
1387
1388                 WARN_ON(!msg->buffer != !msg->size);
1389
1390                 if (msg->buffer)
1391                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1392
1393                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1394                                         rxbuf, rxsize, 0);
1395                 if (ret > 0) {
1396                         msg->reply = rxbuf[0] >> 4;
1397
1398                         if (ret > 1) {
1399                                 /* Number of bytes written in a short write. */
1400                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1401                         } else {
1402                                 /* Return payload size. */
1403                                 ret = msg->size;
1404                         }
1405                 }
1406                 break;
1407
1408         case DP_AUX_NATIVE_READ:
1409         case DP_AUX_I2C_READ:
1410                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1411                 rxsize = msg->size + 1;
1412
1413                 if (WARN_ON(rxsize > 20))
1414                         return -E2BIG;
1415
1416                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1417                                         rxbuf, rxsize, 0);
1418                 if (ret > 0) {
1419                         msg->reply = rxbuf[0] >> 4;
1420                         /*
1421                          * Assume happy day, and copy the data. The caller is
1422                          * expected to check msg->reply before touching it.
1423                          *
1424                          * Return payload size.
1425                          */
1426                         ret--;
1427                         memcpy(msg->buffer, rxbuf + 1, ret);
1428                 }
1429                 break;
1430
1431         default:
1432                 ret = -EINVAL;
1433                 break;
1434         }
1435
1436         return ret;
1437 }
1438
1439
1440 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1441 {
1442         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1443         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1444         enum aux_ch aux_ch = dig_port->aux_ch;
1445
1446         switch (aux_ch) {
1447         case AUX_CH_B:
1448         case AUX_CH_C:
1449         case AUX_CH_D:
1450                 return DP_AUX_CH_CTL(aux_ch);
1451         default:
1452                 MISSING_CASE(aux_ch);
1453                 return DP_AUX_CH_CTL(AUX_CH_B);
1454         }
1455 }
1456
1457 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1458 {
1459         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1460         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1461         enum aux_ch aux_ch = dig_port->aux_ch;
1462
1463         switch (aux_ch) {
1464         case AUX_CH_B:
1465         case AUX_CH_C:
1466         case AUX_CH_D:
1467                 return DP_AUX_CH_DATA(aux_ch, index);
1468         default:
1469                 MISSING_CASE(aux_ch);
1470                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1471         }
1472 }
1473
1474 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1475 {
1476         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1477         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1478         enum aux_ch aux_ch = dig_port->aux_ch;
1479
1480         switch (aux_ch) {
1481         case AUX_CH_A:
1482                 return DP_AUX_CH_CTL(aux_ch);
1483         case AUX_CH_B:
1484         case AUX_CH_C:
1485         case AUX_CH_D:
1486                 return PCH_DP_AUX_CH_CTL(aux_ch);
1487         default:
1488                 MISSING_CASE(aux_ch);
1489                 return DP_AUX_CH_CTL(AUX_CH_A);
1490         }
1491 }
1492
1493 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1494 {
1495         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1496         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1497         enum aux_ch aux_ch = dig_port->aux_ch;
1498
1499         switch (aux_ch) {
1500         case AUX_CH_A:
1501                 return DP_AUX_CH_DATA(aux_ch, index);
1502         case AUX_CH_B:
1503         case AUX_CH_C:
1504         case AUX_CH_D:
1505                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1506         default:
1507                 MISSING_CASE(aux_ch);
1508                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1509         }
1510 }
1511
1512 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1513 {
1514         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1515         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1516         enum aux_ch aux_ch = dig_port->aux_ch;
1517
1518         switch (aux_ch) {
1519         case AUX_CH_A:
1520         case AUX_CH_B:
1521         case AUX_CH_C:
1522         case AUX_CH_D:
1523         case AUX_CH_E:
1524         case AUX_CH_F:
1525                 return DP_AUX_CH_CTL(aux_ch);
1526         default:
1527                 MISSING_CASE(aux_ch);
1528                 return DP_AUX_CH_CTL(AUX_CH_A);
1529         }
1530 }
1531
1532 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1533 {
1534         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1535         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1536         enum aux_ch aux_ch = dig_port->aux_ch;
1537
1538         switch (aux_ch) {
1539         case AUX_CH_A:
1540         case AUX_CH_B:
1541         case AUX_CH_C:
1542         case AUX_CH_D:
1543         case AUX_CH_E:
1544         case AUX_CH_F:
1545                 return DP_AUX_CH_DATA(aux_ch, index);
1546         default:
1547                 MISSING_CASE(aux_ch);
1548                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1549         }
1550 }
1551
1552 static void
1553 intel_dp_aux_fini(struct intel_dp *intel_dp)
1554 {
1555         kfree(intel_dp->aux.name);
1556 }
1557
1558 static void
1559 intel_dp_aux_init(struct intel_dp *intel_dp)
1560 {
1561         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1562         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1563         struct intel_encoder *encoder = &dig_port->base;
1564
1565         if (INTEL_GEN(dev_priv) >= 9) {
1566                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1567                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1568         } else if (HAS_PCH_SPLIT(dev_priv)) {
1569                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1570                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1571         } else {
1572                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1573                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1574         }
1575
1576         if (INTEL_GEN(dev_priv) >= 9)
1577                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1578         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1579                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1580         else if (HAS_PCH_SPLIT(dev_priv))
1581                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1582         else
1583                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1584
1585         if (INTEL_GEN(dev_priv) >= 9)
1586                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1587         else
1588                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1589
1590         drm_dp_aux_init(&intel_dp->aux);
1591
1592         /* Failure to allocate our preferred name is not critical */
1593         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1594                                        port_name(encoder->port));
1595         intel_dp->aux.transfer = intel_dp_aux_transfer;
1596 }
1597
1598 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1599 {
1600         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1601
1602         return max_rate >= 540000;
1603 }
1604
1605 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1606 {
1607         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1608
1609         return max_rate >= 810000;
1610 }
1611
1612 static void
1613 intel_dp_set_clock(struct intel_encoder *encoder,
1614                    struct intel_crtc_state *pipe_config)
1615 {
1616         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1617         const struct dp_link_dpll *divisor = NULL;
1618         int i, count = 0;
1619
1620         if (IS_G4X(dev_priv)) {
1621                 divisor = g4x_dpll;
1622                 count = ARRAY_SIZE(g4x_dpll);
1623         } else if (HAS_PCH_SPLIT(dev_priv)) {
1624                 divisor = pch_dpll;
1625                 count = ARRAY_SIZE(pch_dpll);
1626         } else if (IS_CHERRYVIEW(dev_priv)) {
1627                 divisor = chv_dpll;
1628                 count = ARRAY_SIZE(chv_dpll);
1629         } else if (IS_VALLEYVIEW(dev_priv)) {
1630                 divisor = vlv_dpll;
1631                 count = ARRAY_SIZE(vlv_dpll);
1632         }
1633
1634         if (divisor && count) {
1635                 for (i = 0; i < count; i++) {
1636                         if (pipe_config->port_clock == divisor[i].clock) {
1637                                 pipe_config->dpll = divisor[i].dpll;
1638                                 pipe_config->clock_set = true;
1639                                 break;
1640                         }
1641                 }
1642         }
1643 }
1644
1645 static void snprintf_int_array(char *str, size_t len,
1646                                const int *array, int nelem)
1647 {
1648         int i;
1649
1650         str[0] = '\0';
1651
1652         for (i = 0; i < nelem; i++) {
1653                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1654                 if (r >= len)
1655                         return;
1656                 str += r;
1657                 len -= r;
1658         }
1659 }
1660
1661 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1662 {
1663         char str[128]; /* FIXME: too big for stack? */
1664
1665         if ((drm_debug & DRM_UT_KMS) == 0)
1666                 return;
1667
1668         snprintf_int_array(str, sizeof(str),
1669                            intel_dp->source_rates, intel_dp->num_source_rates);
1670         DRM_DEBUG_KMS("source rates: %s\n", str);
1671
1672         snprintf_int_array(str, sizeof(str),
1673                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1674         DRM_DEBUG_KMS("sink rates: %s\n", str);
1675
1676         snprintf_int_array(str, sizeof(str),
1677                            intel_dp->common_rates, intel_dp->num_common_rates);
1678         DRM_DEBUG_KMS("common rates: %s\n", str);
1679 }
1680
1681 int
1682 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1683 {
1684         int len;
1685
1686         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1687         if (WARN_ON(len <= 0))
1688                 return 162000;
1689
1690         return intel_dp->common_rates[len - 1];
1691 }
1692
1693 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1694 {
1695         int i = intel_dp_rate_index(intel_dp->sink_rates,
1696                                     intel_dp->num_sink_rates, rate);
1697
1698         if (WARN_ON(i < 0))
1699                 i = 0;
1700
1701         return i;
1702 }
1703
1704 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1705                            uint8_t *link_bw, uint8_t *rate_select)
1706 {
1707         /* eDP 1.4 rate select method. */
1708         if (intel_dp->use_rate_select) {
1709                 *link_bw = 0;
1710                 *rate_select =
1711                         intel_dp_rate_select(intel_dp, port_clock);
1712         } else {
1713                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1714                 *rate_select = 0;
1715         }
1716 }
1717
1718 struct link_config_limits {
1719         int min_clock, max_clock;
1720         int min_lane_count, max_lane_count;
1721         int min_bpp, max_bpp;
1722 };
1723
1724 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1725                                          const struct intel_crtc_state *pipe_config)
1726 {
1727         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1728
1729         return INTEL_GEN(dev_priv) >= 11 &&
1730                 pipe_config->cpu_transcoder != TRANSCODER_A;
1731 }
1732
1733 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1734                                   const struct intel_crtc_state *pipe_config)
1735 {
1736         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1737                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1738 }
1739
1740 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1741                                          const struct intel_crtc_state *pipe_config)
1742 {
1743         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1744
1745         return INTEL_GEN(dev_priv) >= 10 &&
1746                 pipe_config->cpu_transcoder != TRANSCODER_A;
1747 }
1748
1749 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1750                                   const struct intel_crtc_state *pipe_config)
1751 {
1752         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1753                 return false;
1754
1755         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1756                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1757 }
1758
1759 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1760                                 struct intel_crtc_state *pipe_config)
1761 {
1762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1763         struct intel_connector *intel_connector = intel_dp->attached_connector;
1764         int bpp, bpc;
1765
1766         bpp = pipe_config->pipe_bpp;
1767         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1768
1769         if (bpc > 0)
1770                 bpp = min(bpp, 3*bpc);
1771
1772         if (intel_dp_is_edp(intel_dp)) {
1773                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1774                 if (intel_connector->base.display_info.bpc == 0 &&
1775                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1776                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1777                                       dev_priv->vbt.edp.bpp);
1778                         bpp = dev_priv->vbt.edp.bpp;
1779                 }
1780         }
1781
1782         return bpp;
1783 }
1784
1785 /* Adjust link config limits based on compliance test requests. */
1786 static void
1787 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1788                                   struct intel_crtc_state *pipe_config,
1789                                   struct link_config_limits *limits)
1790 {
1791         /* For DP Compliance we override the computed bpp for the pipe */
1792         if (intel_dp->compliance.test_data.bpc != 0) {
1793                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1794
1795                 limits->min_bpp = limits->max_bpp = bpp;
1796                 pipe_config->dither_force_disable = bpp == 6 * 3;
1797
1798                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1799         }
1800
1801         /* Use values requested by Compliance Test Request */
1802         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1803                 int index;
1804
1805                 /* Validate the compliance test data since max values
1806                  * might have changed due to link train fallback.
1807                  */
1808                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1809                                                intel_dp->compliance.test_lane_count)) {
1810                         index = intel_dp_rate_index(intel_dp->common_rates,
1811                                                     intel_dp->num_common_rates,
1812                                                     intel_dp->compliance.test_link_rate);
1813                         if (index >= 0)
1814                                 limits->min_clock = limits->max_clock = index;
1815                         limits->min_lane_count = limits->max_lane_count =
1816                                 intel_dp->compliance.test_lane_count;
1817                 }
1818         }
1819 }
1820
1821 /* Optimize link config in order: max bpp, min clock, min lanes */
1822 static bool
1823 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1824                                   struct intel_crtc_state *pipe_config,
1825                                   const struct link_config_limits *limits)
1826 {
1827         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1828         int bpp, clock, lane_count;
1829         int mode_rate, link_clock, link_avail;
1830
1831         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1832                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1833                                                    bpp);
1834
1835                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1836                         for (lane_count = limits->min_lane_count;
1837                              lane_count <= limits->max_lane_count;
1838                              lane_count <<= 1) {
1839                                 link_clock = intel_dp->common_rates[clock];
1840                                 link_avail = intel_dp_max_data_rate(link_clock,
1841                                                                     lane_count);
1842
1843                                 if (mode_rate <= link_avail) {
1844                                         pipe_config->lane_count = lane_count;
1845                                         pipe_config->pipe_bpp = bpp;
1846                                         pipe_config->port_clock = link_clock;
1847
1848                                         return true;
1849                                 }
1850                         }
1851                 }
1852         }
1853
1854         return false;
1855 }
1856
1857 /* Optimize link config in order: max bpp, min lanes, min clock */
1858 static bool
1859 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1860                                   struct intel_crtc_state *pipe_config,
1861                                   const struct link_config_limits *limits)
1862 {
1863         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1864         int bpp, clock, lane_count;
1865         int mode_rate, link_clock, link_avail;
1866
1867         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1868                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1869                                                    bpp);
1870
1871                 for (lane_count = limits->min_lane_count;
1872                      lane_count <= limits->max_lane_count;
1873                      lane_count <<= 1) {
1874                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1875                                 link_clock = intel_dp->common_rates[clock];
1876                                 link_avail = intel_dp_max_data_rate(link_clock,
1877                                                                     lane_count);
1878
1879                                 if (mode_rate <= link_avail) {
1880                                         pipe_config->lane_count = lane_count;
1881                                         pipe_config->pipe_bpp = bpp;
1882                                         pipe_config->port_clock = link_clock;
1883
1884                                         return true;
1885                                 }
1886                         }
1887                 }
1888         }
1889
1890         return false;
1891 }
1892
1893 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1894 {
1895         int i, num_bpc;
1896         u8 dsc_bpc[3] = {0};
1897
1898         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1899                                                        dsc_bpc);
1900         for (i = 0; i < num_bpc; i++) {
1901                 if (dsc_max_bpc >= dsc_bpc[i])
1902                         return dsc_bpc[i] * 3;
1903         }
1904
1905         return 0;
1906 }
1907
1908 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1909                                         struct intel_crtc_state *pipe_config,
1910                                         struct drm_connector_state *conn_state,
1911                                         struct link_config_limits *limits)
1912 {
1913         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1914         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1915         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1916         u8 dsc_max_bpc;
1917         int pipe_bpp;
1918
1919         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1920                 return false;
1921
1922         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1923                             conn_state->max_requested_bpc);
1924
1925         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1926         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1927                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1928                 return false;
1929         }
1930
1931         /*
1932          * For now enable DSC for max bpp, max link rate, max lane count.
1933          * Optimize this later for the minimum possible link rate/lane count
1934          * with DSC enabled for the requested mode.
1935          */
1936         pipe_config->pipe_bpp = pipe_bpp;
1937         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1938         pipe_config->lane_count = limits->max_lane_count;
1939
1940         if (intel_dp_is_edp(intel_dp)) {
1941                 pipe_config->dsc_params.compressed_bpp =
1942                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1943                               pipe_config->pipe_bpp);
1944                 pipe_config->dsc_params.slice_count =
1945                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1946                                                         true);
1947         } else {
1948                 u16 dsc_max_output_bpp;
1949                 u8 dsc_dp_slice_count;
1950
1951                 dsc_max_output_bpp =
1952                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1953                                                     pipe_config->lane_count,
1954                                                     adjusted_mode->crtc_clock,
1955                                                     adjusted_mode->crtc_hdisplay);
1956                 dsc_dp_slice_count =
1957                         intel_dp_dsc_get_slice_count(intel_dp,
1958                                                      adjusted_mode->crtc_clock,
1959                                                      adjusted_mode->crtc_hdisplay);
1960                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1961                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1962                         return false;
1963                 }
1964                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1965                                                                dsc_max_output_bpp >> 4,
1966                                                                pipe_config->pipe_bpp);
1967                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1968         }
1969         /*
1970          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1971          * is greater than the maximum Cdclock and if slice count is even
1972          * then we need to use 2 VDSC instances.
1973          */
1974         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1975                 if (pipe_config->dsc_params.slice_count > 1) {
1976                         pipe_config->dsc_params.dsc_split = true;
1977                 } else {
1978                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1979                         return false;
1980                 }
1981         }
1982         if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
1983                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1984                               "Compressed BPP = %d\n",
1985                               pipe_config->pipe_bpp,
1986                               pipe_config->dsc_params.compressed_bpp);
1987                 return false;
1988         }
1989         pipe_config->dsc_params.compression_enable = true;
1990         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1991                       "Compressed Bpp = %d Slice Count = %d\n",
1992                       pipe_config->pipe_bpp,
1993                       pipe_config->dsc_params.compressed_bpp,
1994                       pipe_config->dsc_params.slice_count);
1995
1996         return true;
1997 }
1998
1999 static bool
2000 intel_dp_compute_link_config(struct intel_encoder *encoder,
2001                              struct intel_crtc_state *pipe_config,
2002                              struct drm_connector_state *conn_state)
2003 {
2004         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2005         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2006         struct link_config_limits limits;
2007         int common_len;
2008         bool ret;
2009
2010         common_len = intel_dp_common_len_rate_limit(intel_dp,
2011                                                     intel_dp->max_link_rate);
2012
2013         /* No common link rates between source and sink */
2014         WARN_ON(common_len <= 0);
2015
2016         limits.min_clock = 0;
2017         limits.max_clock = common_len - 1;
2018
2019         limits.min_lane_count = 1;
2020         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2021
2022         limits.min_bpp = 6 * 3;
2023         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2024
2025         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2026                 /*
2027                  * Use the maximum clock and number of lanes the eDP panel
2028                  * advertizes being capable of. The eDP 1.3 and earlier panels
2029                  * are generally designed to support only a single clock and
2030                  * lane configuration, and typically these values correspond to
2031                  * the native resolution of the panel. With eDP 1.4 rate select
2032                  * and DSC, this is decreasingly the case, and we need to be
2033                  * able to select less than maximum link config.
2034                  */
2035                 limits.min_lane_count = limits.max_lane_count;
2036                 limits.min_clock = limits.max_clock;
2037         }
2038
2039         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2040
2041         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2042                       "max rate %d max bpp %d pixel clock %iKHz\n",
2043                       limits.max_lane_count,
2044                       intel_dp->common_rates[limits.max_clock],
2045                       limits.max_bpp, adjusted_mode->crtc_clock);
2046
2047         if (intel_dp_is_edp(intel_dp))
2048                 /*
2049                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2050                  * section A.1: "It is recommended that the minimum number of
2051                  * lanes be used, using the minimum link rate allowed for that
2052                  * lane configuration."
2053                  *
2054                  * Note that we use the max clock and lane count for eDP 1.3 and
2055                  * earlier, and fast vs. wide is irrelevant.
2056                  */
2057                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2058                                                         &limits);
2059         else
2060                 /* Optimize for slow and wide. */
2061                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2062                                                         &limits);
2063
2064         /* enable compression if the mode doesn't fit available BW */
2065         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2066         if (!ret || intel_dp->force_dsc_en) {
2067                 if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
2068                                                  conn_state, &limits))
2069                         return false;
2070         }
2071
2072         if (pipe_config->dsc_params.compression_enable) {
2073                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2074                               pipe_config->lane_count, pipe_config->port_clock,
2075                               pipe_config->pipe_bpp,
2076                               pipe_config->dsc_params.compressed_bpp);
2077
2078                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2079                               intel_dp_link_required(adjusted_mode->crtc_clock,
2080                                                      pipe_config->dsc_params.compressed_bpp),
2081                               intel_dp_max_data_rate(pipe_config->port_clock,
2082                                                      pipe_config->lane_count));
2083         } else {
2084                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2085                               pipe_config->lane_count, pipe_config->port_clock,
2086                               pipe_config->pipe_bpp);
2087
2088                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2089                               intel_dp_link_required(adjusted_mode->crtc_clock,
2090                                                      pipe_config->pipe_bpp),
2091                               intel_dp_max_data_rate(pipe_config->port_clock,
2092                                                      pipe_config->lane_count));
2093         }
2094         return true;
2095 }
2096
2097 bool
2098 intel_dp_compute_config(struct intel_encoder *encoder,
2099                         struct intel_crtc_state *pipe_config,
2100                         struct drm_connector_state *conn_state)
2101 {
2102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2103         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2104         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2105         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2106         enum port port = encoder->port;
2107         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2108         struct intel_connector *intel_connector = intel_dp->attached_connector;
2109         struct intel_digital_connector_state *intel_conn_state =
2110                 to_intel_digital_connector_state(conn_state);
2111         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2112                                            DP_DPCD_QUIRK_CONSTANT_N);
2113
2114         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2115                 pipe_config->has_pch_encoder = true;
2116
2117         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2118         if (lspcon->active)
2119                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2120
2121         pipe_config->has_drrs = false;
2122         if (IS_G4X(dev_priv) || port == PORT_A)
2123                 pipe_config->has_audio = false;
2124         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2125                 pipe_config->has_audio = intel_dp->has_audio;
2126         else
2127                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2128
2129         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2130                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2131                                        adjusted_mode);
2132
2133                 if (INTEL_GEN(dev_priv) >= 9) {
2134                         int ret;
2135
2136                         ret = skl_update_scaler_crtc(pipe_config);
2137                         if (ret)
2138                                 return ret;
2139                 }
2140
2141                 if (HAS_GMCH_DISPLAY(dev_priv))
2142                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2143                                                  conn_state->scaling_mode);
2144                 else
2145                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2146                                                 conn_state->scaling_mode);
2147         }
2148
2149         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2150                 return false;
2151
2152         if (HAS_GMCH_DISPLAY(dev_priv) &&
2153             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2154                 return false;
2155
2156         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2157                 return false;
2158
2159         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2160                                   intel_dp_supports_fec(intel_dp, pipe_config);
2161
2162         if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
2163                 return false;
2164
2165         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2166                 /*
2167                  * See:
2168                  * CEA-861-E - 5.1 Default Encoding Parameters
2169                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2170                  */
2171                 pipe_config->limited_color_range =
2172                         pipe_config->pipe_bpp != 18 &&
2173                         drm_default_rgb_quant_range(adjusted_mode) ==
2174                         HDMI_QUANTIZATION_RANGE_LIMITED;
2175         } else {
2176                 pipe_config->limited_color_range =
2177                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2178         }
2179
2180         if (!pipe_config->dsc_params.compression_enable)
2181                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2182                                        pipe_config->lane_count,
2183                                        adjusted_mode->crtc_clock,
2184                                        pipe_config->port_clock,
2185                                        &pipe_config->dp_m_n,
2186                                        constant_n);
2187         else
2188                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2189                                        pipe_config->lane_count,
2190                                        adjusted_mode->crtc_clock,
2191                                        pipe_config->port_clock,
2192                                        &pipe_config->dp_m_n,
2193                                        constant_n);
2194
2195         if (intel_connector->panel.downclock_mode != NULL &&
2196                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2197                         pipe_config->has_drrs = true;
2198                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2199                                                pipe_config->lane_count,
2200                                                intel_connector->panel.downclock_mode->clock,
2201                                                pipe_config->port_clock,
2202                                                &pipe_config->dp_m2_n2,
2203                                                constant_n);
2204         }
2205
2206         if (!HAS_DDI(dev_priv))
2207                 intel_dp_set_clock(encoder, pipe_config);
2208
2209         intel_psr_compute_config(intel_dp, pipe_config);
2210
2211         return true;
2212 }
2213
2214 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2215                               int link_rate, uint8_t lane_count,
2216                               bool link_mst)
2217 {
2218         intel_dp->link_trained = false;
2219         intel_dp->link_rate = link_rate;
2220         intel_dp->lane_count = lane_count;
2221         intel_dp->link_mst = link_mst;
2222 }
2223
2224 static void intel_dp_prepare(struct intel_encoder *encoder,
2225                              const struct intel_crtc_state *pipe_config)
2226 {
2227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2228         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2229         enum port port = encoder->port;
2230         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2231         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2232
2233         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2234                                  pipe_config->lane_count,
2235                                  intel_crtc_has_type(pipe_config,
2236                                                      INTEL_OUTPUT_DP_MST));
2237
2238         /*
2239          * There are four kinds of DP registers:
2240          *
2241          *      IBX PCH
2242          *      SNB CPU
2243          *      IVB CPU
2244          *      CPT PCH
2245          *
2246          * IBX PCH and CPU are the same for almost everything,
2247          * except that the CPU DP PLL is configured in this
2248          * register
2249          *
2250          * CPT PCH is quite different, having many bits moved
2251          * to the TRANS_DP_CTL register instead. That
2252          * configuration happens (oddly) in ironlake_pch_enable
2253          */
2254
2255         /* Preserve the BIOS-computed detected bit. This is
2256          * supposed to be read-only.
2257          */
2258         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2259
2260         /* Handle DP bits in common between all three register formats */
2261         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2262         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2263
2264         /* Split out the IBX/CPU vs CPT settings */
2265
2266         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2267                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2268                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2269                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2270                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2271                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2272
2273                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2274                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2275
2276                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2277         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2278                 u32 trans_dp;
2279
2280                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2281
2282                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2283                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2284                         trans_dp |= TRANS_DP_ENH_FRAMING;
2285                 else
2286                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2287                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2288         } else {
2289                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2290                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2291
2292                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2293                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2294                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2295                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2296                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2297
2298                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2299                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2300
2301                 if (IS_CHERRYVIEW(dev_priv))
2302                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2303                 else
2304                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2305         }
2306 }
2307
2308 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2309 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2310
2311 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2312 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2313
2314 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2315 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2316
2317 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2318
2319 static void wait_panel_status(struct intel_dp *intel_dp,
2320                                        u32 mask,
2321                                        u32 value)
2322 {
2323         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2324         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2325
2326         lockdep_assert_held(&dev_priv->pps_mutex);
2327
2328         intel_pps_verify_state(intel_dp);
2329
2330         pp_stat_reg = _pp_stat_reg(intel_dp);
2331         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2332
2333         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2334                         mask, value,
2335                         I915_READ(pp_stat_reg),
2336                         I915_READ(pp_ctrl_reg));
2337
2338         if (intel_wait_for_register(dev_priv,
2339                                     pp_stat_reg, mask, value,
2340                                     5000))
2341                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2342                                 I915_READ(pp_stat_reg),
2343                                 I915_READ(pp_ctrl_reg));
2344
2345         DRM_DEBUG_KMS("Wait complete\n");
2346 }
2347
2348 static void wait_panel_on(struct intel_dp *intel_dp)
2349 {
2350         DRM_DEBUG_KMS("Wait for panel power on\n");
2351         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2352 }
2353
2354 static void wait_panel_off(struct intel_dp *intel_dp)
2355 {
2356         DRM_DEBUG_KMS("Wait for panel power off time\n");
2357         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2358 }
2359
2360 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2361 {
2362         ktime_t panel_power_on_time;
2363         s64 panel_power_off_duration;
2364
2365         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2366
2367         /* take the difference of currrent time and panel power off time
2368          * and then make panel wait for t11_t12 if needed. */
2369         panel_power_on_time = ktime_get_boottime();
2370         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2371
2372         /* When we disable the VDD override bit last we have to do the manual
2373          * wait. */
2374         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2375                 wait_remaining_ms_from_jiffies(jiffies,
2376                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2377
2378         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2379 }
2380
2381 static void wait_backlight_on(struct intel_dp *intel_dp)
2382 {
2383         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2384                                        intel_dp->backlight_on_delay);
2385 }
2386
2387 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2388 {
2389         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2390                                        intel_dp->backlight_off_delay);
2391 }
2392
2393 /* Read the current pp_control value, unlocking the register if it
2394  * is locked
2395  */
2396
2397 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2398 {
2399         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2400         u32 control;
2401
2402         lockdep_assert_held(&dev_priv->pps_mutex);
2403
2404         control = I915_READ(_pp_ctrl_reg(intel_dp));
2405         if (WARN_ON(!HAS_DDI(dev_priv) &&
2406                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2407                 control &= ~PANEL_UNLOCK_MASK;
2408                 control |= PANEL_UNLOCK_REGS;
2409         }
2410         return control;
2411 }
2412
2413 /*
2414  * Must be paired with edp_panel_vdd_off().
2415  * Must hold pps_mutex around the whole on/off sequence.
2416  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2417  */
2418 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2419 {
2420         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2421         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2422         u32 pp;
2423         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2424         bool need_to_disable = !intel_dp->want_panel_vdd;
2425
2426         lockdep_assert_held(&dev_priv->pps_mutex);
2427
2428         if (!intel_dp_is_edp(intel_dp))
2429                 return false;
2430
2431         cancel_delayed_work(&intel_dp->panel_vdd_work);
2432         intel_dp->want_panel_vdd = true;
2433
2434         if (edp_have_panel_vdd(intel_dp))
2435                 return need_to_disable;
2436
2437         intel_display_power_get(dev_priv,
2438                                 intel_aux_power_domain(intel_dig_port));
2439
2440         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2441                       port_name(intel_dig_port->base.port));
2442
2443         if (!edp_have_panel_power(intel_dp))
2444                 wait_panel_power_cycle(intel_dp);
2445
2446         pp = ironlake_get_pp_control(intel_dp);
2447         pp |= EDP_FORCE_VDD;
2448
2449         pp_stat_reg = _pp_stat_reg(intel_dp);
2450         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2451
2452         I915_WRITE(pp_ctrl_reg, pp);
2453         POSTING_READ(pp_ctrl_reg);
2454         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2455                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2456         /*
2457          * If the panel wasn't on, delay before accessing aux channel
2458          */
2459         if (!edp_have_panel_power(intel_dp)) {
2460                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2461                               port_name(intel_dig_port->base.port));
2462                 msleep(intel_dp->panel_power_up_delay);
2463         }
2464
2465         return need_to_disable;
2466 }
2467
2468 /*
2469  * Must be paired with intel_edp_panel_vdd_off() or
2470  * intel_edp_panel_off().
2471  * Nested calls to these functions are not allowed since
2472  * we drop the lock. Caller must use some higher level
2473  * locking to prevent nested calls from other threads.
2474  */
2475 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2476 {
2477         intel_wakeref_t wakeref;
2478         bool vdd;
2479
2480         if (!intel_dp_is_edp(intel_dp))
2481                 return;
2482
2483         vdd = false;
2484         with_pps_lock(intel_dp, wakeref)
2485                 vdd = edp_panel_vdd_on(intel_dp);
2486         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2487              port_name(dp_to_dig_port(intel_dp)->base.port));
2488 }
2489
2490 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2491 {
2492         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2493         struct intel_digital_port *intel_dig_port =
2494                 dp_to_dig_port(intel_dp);
2495         u32 pp;
2496         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2497
2498         lockdep_assert_held(&dev_priv->pps_mutex);
2499
2500         WARN_ON(intel_dp->want_panel_vdd);
2501
2502         if (!edp_have_panel_vdd(intel_dp))
2503                 return;
2504
2505         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2506                       port_name(intel_dig_port->base.port));
2507
2508         pp = ironlake_get_pp_control(intel_dp);
2509         pp &= ~EDP_FORCE_VDD;
2510
2511         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2512         pp_stat_reg = _pp_stat_reg(intel_dp);
2513
2514         I915_WRITE(pp_ctrl_reg, pp);
2515         POSTING_READ(pp_ctrl_reg);
2516
2517         /* Make sure sequencer is idle before allowing subsequent activity */
2518         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2519         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2520
2521         if ((pp & PANEL_POWER_ON) == 0)
2522                 intel_dp->panel_power_off_time = ktime_get_boottime();
2523
2524         intel_display_power_put_unchecked(dev_priv,
2525                                           intel_aux_power_domain(intel_dig_port));
2526 }
2527
2528 static void edp_panel_vdd_work(struct work_struct *__work)
2529 {
2530         struct intel_dp *intel_dp =
2531                 container_of(to_delayed_work(__work),
2532                              struct intel_dp, panel_vdd_work);
2533         intel_wakeref_t wakeref;
2534
2535         with_pps_lock(intel_dp, wakeref) {
2536                 if (!intel_dp->want_panel_vdd)
2537                         edp_panel_vdd_off_sync(intel_dp);
2538         }
2539 }
2540
2541 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2542 {
2543         unsigned long delay;
2544
2545         /*
2546          * Queue the timer to fire a long time from now (relative to the power
2547          * down delay) to keep the panel power up across a sequence of
2548          * operations.
2549          */
2550         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2551         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2552 }
2553
2554 /*
2555  * Must be paired with edp_panel_vdd_on().
2556  * Must hold pps_mutex around the whole on/off sequence.
2557  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2558  */
2559 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2560 {
2561         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2562
2563         lockdep_assert_held(&dev_priv->pps_mutex);
2564
2565         if (!intel_dp_is_edp(intel_dp))
2566                 return;
2567
2568         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2569              port_name(dp_to_dig_port(intel_dp)->base.port));
2570
2571         intel_dp->want_panel_vdd = false;
2572
2573         if (sync)
2574                 edp_panel_vdd_off_sync(intel_dp);
2575         else
2576                 edp_panel_vdd_schedule_off(intel_dp);
2577 }
2578
2579 static void edp_panel_on(struct intel_dp *intel_dp)
2580 {
2581         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2582         u32 pp;
2583         i915_reg_t pp_ctrl_reg;
2584
2585         lockdep_assert_held(&dev_priv->pps_mutex);
2586
2587         if (!intel_dp_is_edp(intel_dp))
2588                 return;
2589
2590         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2591                       port_name(dp_to_dig_port(intel_dp)->base.port));
2592
2593         if (WARN(edp_have_panel_power(intel_dp),
2594                  "eDP port %c panel power already on\n",
2595                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2596                 return;
2597
2598         wait_panel_power_cycle(intel_dp);
2599
2600         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2601         pp = ironlake_get_pp_control(intel_dp);
2602         if (IS_GEN(dev_priv, 5)) {
2603                 /* ILK workaround: disable reset around power sequence */
2604                 pp &= ~PANEL_POWER_RESET;
2605                 I915_WRITE(pp_ctrl_reg, pp);
2606                 POSTING_READ(pp_ctrl_reg);
2607         }
2608
2609         pp |= PANEL_POWER_ON;
2610         if (!IS_GEN(dev_priv, 5))
2611                 pp |= PANEL_POWER_RESET;
2612
2613         I915_WRITE(pp_ctrl_reg, pp);
2614         POSTING_READ(pp_ctrl_reg);
2615
2616         wait_panel_on(intel_dp);
2617         intel_dp->last_power_on = jiffies;
2618
2619         if (IS_GEN(dev_priv, 5)) {
2620                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2621                 I915_WRITE(pp_ctrl_reg, pp);
2622                 POSTING_READ(pp_ctrl_reg);
2623         }
2624 }
2625
2626 void intel_edp_panel_on(struct intel_dp *intel_dp)
2627 {
2628         intel_wakeref_t wakeref;
2629
2630         if (!intel_dp_is_edp(intel_dp))
2631                 return;
2632
2633         with_pps_lock(intel_dp, wakeref)
2634                 edp_panel_on(intel_dp);
2635 }
2636
2637
2638 static void edp_panel_off(struct intel_dp *intel_dp)
2639 {
2640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2641         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2642         u32 pp;
2643         i915_reg_t pp_ctrl_reg;
2644
2645         lockdep_assert_held(&dev_priv->pps_mutex);
2646
2647         if (!intel_dp_is_edp(intel_dp))
2648                 return;
2649
2650         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2651                       port_name(dig_port->base.port));
2652
2653         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2654              port_name(dig_port->base.port));
2655
2656         pp = ironlake_get_pp_control(intel_dp);
2657         /* We need to switch off panel power _and_ force vdd, for otherwise some
2658          * panels get very unhappy and cease to work. */
2659         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2660                 EDP_BLC_ENABLE);
2661
2662         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2663
2664         intel_dp->want_panel_vdd = false;
2665
2666         I915_WRITE(pp_ctrl_reg, pp);
2667         POSTING_READ(pp_ctrl_reg);
2668
2669         wait_panel_off(intel_dp);
2670         intel_dp->panel_power_off_time = ktime_get_boottime();
2671
2672         /* We got a reference when we enabled the VDD. */
2673         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2674 }
2675
2676 void intel_edp_panel_off(struct intel_dp *intel_dp)
2677 {
2678         intel_wakeref_t wakeref;
2679
2680         if (!intel_dp_is_edp(intel_dp))
2681                 return;
2682
2683         with_pps_lock(intel_dp, wakeref)
2684                 edp_panel_off(intel_dp);
2685 }
2686
2687 /* Enable backlight in the panel power control. */
2688 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2689 {
2690         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2691         intel_wakeref_t wakeref;
2692
2693         /*
2694          * If we enable the backlight right away following a panel power
2695          * on, we may see slight flicker as the panel syncs with the eDP
2696          * link.  So delay a bit to make sure the image is solid before
2697          * allowing it to appear.
2698          */
2699         wait_backlight_on(intel_dp);
2700
2701         with_pps_lock(intel_dp, wakeref) {
2702                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2703                 u32 pp;
2704
2705                 pp = ironlake_get_pp_control(intel_dp);
2706                 pp |= EDP_BLC_ENABLE;
2707
2708                 I915_WRITE(pp_ctrl_reg, pp);
2709                 POSTING_READ(pp_ctrl_reg);
2710         }
2711 }
2712
2713 /* Enable backlight PWM and backlight PP control. */
2714 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2715                             const struct drm_connector_state *conn_state)
2716 {
2717         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2718
2719         if (!intel_dp_is_edp(intel_dp))
2720                 return;
2721
2722         DRM_DEBUG_KMS("\n");
2723
2724         intel_panel_enable_backlight(crtc_state, conn_state);
2725         _intel_edp_backlight_on(intel_dp);
2726 }
2727
2728 /* Disable backlight in the panel power control. */
2729 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2730 {
2731         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2732         intel_wakeref_t wakeref;
2733
2734         if (!intel_dp_is_edp(intel_dp))
2735                 return;
2736
2737         with_pps_lock(intel_dp, wakeref) {
2738                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2739                 u32 pp;
2740
2741                 pp = ironlake_get_pp_control(intel_dp);
2742                 pp &= ~EDP_BLC_ENABLE;
2743
2744                 I915_WRITE(pp_ctrl_reg, pp);
2745                 POSTING_READ(pp_ctrl_reg);
2746         }
2747
2748         intel_dp->last_backlight_off = jiffies;
2749         edp_wait_backlight_off(intel_dp);
2750 }
2751
2752 /* Disable backlight PP control and backlight PWM. */
2753 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2754 {
2755         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2756
2757         if (!intel_dp_is_edp(intel_dp))
2758                 return;
2759
2760         DRM_DEBUG_KMS("\n");
2761
2762         _intel_edp_backlight_off(intel_dp);
2763         intel_panel_disable_backlight(old_conn_state);
2764 }
2765
2766 /*
2767  * Hook for controlling the panel power control backlight through the bl_power
2768  * sysfs attribute. Take care to handle multiple calls.
2769  */
2770 static void intel_edp_backlight_power(struct intel_connector *connector,
2771                                       bool enable)
2772 {
2773         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2774         intel_wakeref_t wakeref;
2775         bool is_enabled;
2776
2777         is_enabled = false;
2778         with_pps_lock(intel_dp, wakeref)
2779                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2780         if (is_enabled == enable)
2781                 return;
2782
2783         DRM_DEBUG_KMS("panel power control backlight %s\n",
2784                       enable ? "enable" : "disable");
2785
2786         if (enable)
2787                 _intel_edp_backlight_on(intel_dp);
2788         else
2789                 _intel_edp_backlight_off(intel_dp);
2790 }
2791
2792 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2793 {
2794         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2795         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2796         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2797
2798         I915_STATE_WARN(cur_state != state,
2799                         "DP port %c state assertion failure (expected %s, current %s)\n",
2800                         port_name(dig_port->base.port),
2801                         onoff(state), onoff(cur_state));
2802 }
2803 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2804
2805 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2806 {
2807         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2808
2809         I915_STATE_WARN(cur_state != state,
2810                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2811                         onoff(state), onoff(cur_state));
2812 }
2813 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2814 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2815
2816 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2817                                 const struct intel_crtc_state *pipe_config)
2818 {
2819         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2820         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2821
2822         assert_pipe_disabled(dev_priv, crtc->pipe);
2823         assert_dp_port_disabled(intel_dp);
2824         assert_edp_pll_disabled(dev_priv);
2825
2826         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2827                       pipe_config->port_clock);
2828
2829         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2830
2831         if (pipe_config->port_clock == 162000)
2832                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2833         else
2834                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2835
2836         I915_WRITE(DP_A, intel_dp->DP);
2837         POSTING_READ(DP_A);
2838         udelay(500);
2839
2840         /*
2841          * [DevILK] Work around required when enabling DP PLL
2842          * while a pipe is enabled going to FDI:
2843          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2844          * 2. Program DP PLL enable
2845          */
2846         if (IS_GEN(dev_priv, 5))
2847                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2848
2849         intel_dp->DP |= DP_PLL_ENABLE;
2850
2851         I915_WRITE(DP_A, intel_dp->DP);
2852         POSTING_READ(DP_A);
2853         udelay(200);
2854 }
2855
2856 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2857                                  const struct intel_crtc_state *old_crtc_state)
2858 {
2859         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2860         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2861
2862         assert_pipe_disabled(dev_priv, crtc->pipe);
2863         assert_dp_port_disabled(intel_dp);
2864         assert_edp_pll_enabled(dev_priv);
2865
2866         DRM_DEBUG_KMS("disabling eDP PLL\n");
2867
2868         intel_dp->DP &= ~DP_PLL_ENABLE;
2869
2870         I915_WRITE(DP_A, intel_dp->DP);
2871         POSTING_READ(DP_A);
2872         udelay(200);
2873 }
2874
2875 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2876 {
2877         /*
2878          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2879          * be capable of signalling downstream hpd with a long pulse.
2880          * Whether or not that means D3 is safe to use is not clear,
2881          * but let's assume so until proven otherwise.
2882          *
2883          * FIXME should really check all downstream ports...
2884          */
2885         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2886                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2887                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2888 }
2889
2890 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2891                                            const struct intel_crtc_state *crtc_state,
2892                                            bool enable)
2893 {
2894         int ret;
2895
2896         if (!crtc_state->dsc_params.compression_enable)
2897                 return;
2898
2899         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2900                                  enable ? DP_DECOMPRESSION_EN : 0);
2901         if (ret < 0)
2902                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2903                               enable ? "enable" : "disable");
2904 }
2905
2906 /* If the sink supports it, try to set the power state appropriately */
2907 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2908 {
2909         int ret, i;
2910
2911         /* Should have a valid DPCD by this point */
2912         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2913                 return;
2914
2915         if (mode != DRM_MODE_DPMS_ON) {
2916                 if (downstream_hpd_needs_d0(intel_dp))
2917                         return;
2918
2919                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2920                                          DP_SET_POWER_D3);
2921         } else {
2922                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2923
2924                 /*
2925                  * When turning on, we need to retry for 1ms to give the sink
2926                  * time to wake up.
2927                  */
2928                 for (i = 0; i < 3; i++) {
2929                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2930                                                  DP_SET_POWER_D0);
2931                         if (ret == 1)
2932                                 break;
2933                         msleep(1);
2934                 }
2935
2936                 if (ret == 1 && lspcon->active)
2937                         lspcon_wait_pcon_mode(lspcon);
2938         }
2939
2940         if (ret != 1)
2941                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2942                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2943 }
2944
2945 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2946                                  enum port port, enum pipe *pipe)
2947 {
2948         enum pipe p;
2949
2950         for_each_pipe(dev_priv, p) {
2951                 u32 val = I915_READ(TRANS_DP_CTL(p));
2952
2953                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2954                         *pipe = p;
2955                         return true;
2956                 }
2957         }
2958
2959         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2960
2961         /* must initialize pipe to something for the asserts */
2962         *pipe = PIPE_A;
2963
2964         return false;
2965 }
2966
2967 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2968                            i915_reg_t dp_reg, enum port port,
2969                            enum pipe *pipe)
2970 {
2971         bool ret;
2972         u32 val;
2973
2974         val = I915_READ(dp_reg);
2975
2976         ret = val & DP_PORT_EN;
2977
2978         /* asserts want to know the pipe even if the port is disabled */
2979         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2980                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2981         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2982                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2983         else if (IS_CHERRYVIEW(dev_priv))
2984                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2985         else
2986                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2987
2988         return ret;
2989 }
2990
2991 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2992                                   enum pipe *pipe)
2993 {
2994         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2995         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2996         intel_wakeref_t wakeref;
2997         bool ret;
2998
2999         wakeref = intel_display_power_get_if_enabled(dev_priv,
3000                                                      encoder->power_domain);
3001         if (!wakeref)
3002                 return false;
3003
3004         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3005                                     encoder->port, pipe);
3006
3007         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3008
3009         return ret;
3010 }
3011
3012 static void intel_dp_get_config(struct intel_encoder *encoder,
3013                                 struct intel_crtc_state *pipe_config)
3014 {
3015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3016         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3017         u32 tmp, flags = 0;
3018         enum port port = encoder->port;
3019         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3020
3021         if (encoder->type == INTEL_OUTPUT_EDP)
3022                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3023         else
3024                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3025
3026         tmp = I915_READ(intel_dp->output_reg);
3027
3028         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3029
3030         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3031                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3032
3033                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3034                         flags |= DRM_MODE_FLAG_PHSYNC;
3035                 else
3036                         flags |= DRM_MODE_FLAG_NHSYNC;
3037
3038                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3039                         flags |= DRM_MODE_FLAG_PVSYNC;
3040                 else
3041                         flags |= DRM_MODE_FLAG_NVSYNC;
3042         } else {
3043                 if (tmp & DP_SYNC_HS_HIGH)
3044                         flags |= DRM_MODE_FLAG_PHSYNC;
3045                 else
3046                         flags |= DRM_MODE_FLAG_NHSYNC;
3047
3048                 if (tmp & DP_SYNC_VS_HIGH)
3049                         flags |= DRM_MODE_FLAG_PVSYNC;
3050                 else
3051                         flags |= DRM_MODE_FLAG_NVSYNC;
3052         }
3053
3054         pipe_config->base.adjusted_mode.flags |= flags;
3055
3056         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3057                 pipe_config->limited_color_range = true;
3058
3059         pipe_config->lane_count =
3060                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3061
3062         intel_dp_get_m_n(crtc, pipe_config);
3063
3064         if (port == PORT_A) {
3065                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3066                         pipe_config->port_clock = 162000;
3067                 else
3068                         pipe_config->port_clock = 270000;
3069         }
3070
3071         pipe_config->base.adjusted_mode.crtc_clock =
3072                 intel_dotclock_calculate(pipe_config->port_clock,
3073                                          &pipe_config->dp_m_n);
3074
3075         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3076             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3077                 /*
3078                  * This is a big fat ugly hack.
3079                  *
3080                  * Some machines in UEFI boot mode provide us a VBT that has 18
3081                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3082                  * unknown we fail to light up. Yet the same BIOS boots up with
3083                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3084                  * max, not what it tells us to use.
3085                  *
3086                  * Note: This will still be broken if the eDP panel is not lit
3087                  * up by the BIOS, and thus we can't get the mode at module
3088                  * load.
3089                  */
3090                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3091                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3092                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3093         }
3094 }
3095
3096 static void intel_disable_dp(struct intel_encoder *encoder,
3097                              const struct intel_crtc_state *old_crtc_state,
3098                              const struct drm_connector_state *old_conn_state)
3099 {
3100         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3101
3102         intel_dp->link_trained = false;
3103
3104         if (old_crtc_state->has_audio)
3105                 intel_audio_codec_disable(encoder,
3106                                           old_crtc_state, old_conn_state);
3107
3108         /* Make sure the panel is off before trying to change the mode. But also
3109          * ensure that we have vdd while we switch off the panel. */
3110         intel_edp_panel_vdd_on(intel_dp);
3111         intel_edp_backlight_off(old_conn_state);
3112         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3113         intel_edp_panel_off(intel_dp);
3114 }
3115
3116 static void g4x_disable_dp(struct intel_encoder *encoder,
3117                            const struct intel_crtc_state *old_crtc_state,
3118                            const struct drm_connector_state *old_conn_state)
3119 {
3120         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3121 }
3122
3123 static void vlv_disable_dp(struct intel_encoder *encoder,
3124                            const struct intel_crtc_state *old_crtc_state,
3125                            const struct drm_connector_state *old_conn_state)
3126 {
3127         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3128 }
3129
3130 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3131                                 const struct intel_crtc_state *old_crtc_state,
3132                                 const struct drm_connector_state *old_conn_state)
3133 {
3134         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3135         enum port port = encoder->port;
3136
3137         /*
3138          * Bspec does not list a specific disable sequence for g4x DP.
3139          * Follow the ilk+ sequence (disable pipe before the port) for
3140          * g4x DP as it does not suffer from underruns like the normal
3141          * g4x modeset sequence (disable pipe after the port).
3142          */
3143         intel_dp_link_down(encoder, old_crtc_state);
3144
3145         /* Only ilk+ has port A */
3146         if (port == PORT_A)
3147                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3148 }
3149
3150 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3151                                 const struct intel_crtc_state *old_crtc_state,
3152                                 const struct drm_connector_state *old_conn_state)
3153 {
3154         intel_dp_link_down(encoder, old_crtc_state);
3155 }
3156
3157 static void chv_post_disable_dp(struct intel_encoder *encoder,
3158                                 const struct intel_crtc_state *old_crtc_state,
3159                                 const struct drm_connector_state *old_conn_state)
3160 {
3161         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3162
3163         intel_dp_link_down(encoder, old_crtc_state);
3164
3165         mutex_lock(&dev_priv->sb_lock);
3166
3167         /* Assert data lane reset */
3168         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3169
3170         mutex_unlock(&dev_priv->sb_lock);
3171 }
3172
3173 static void
3174 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3175                          uint32_t *DP,
3176                          uint8_t dp_train_pat)
3177 {
3178         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3179         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3180         enum port port = intel_dig_port->base.port;
3181         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3182
3183         if (dp_train_pat & train_pat_mask)
3184                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3185                               dp_train_pat & train_pat_mask);
3186
3187         if (HAS_DDI(dev_priv)) {
3188                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3189
3190                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3191                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3192                 else
3193                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3194
3195                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3196                 switch (dp_train_pat & train_pat_mask) {
3197                 case DP_TRAINING_PATTERN_DISABLE:
3198                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3199
3200                         break;
3201                 case DP_TRAINING_PATTERN_1:
3202                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3203                         break;
3204                 case DP_TRAINING_PATTERN_2:
3205                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3206                         break;
3207                 case DP_TRAINING_PATTERN_3:
3208                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3209                         break;
3210                 case DP_TRAINING_PATTERN_4:
3211                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3212                         break;
3213                 }
3214                 I915_WRITE(DP_TP_CTL(port), temp);
3215
3216         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3217                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3218                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3219
3220                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3221                 case DP_TRAINING_PATTERN_DISABLE:
3222                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3223                         break;
3224                 case DP_TRAINING_PATTERN_1:
3225                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3226                         break;
3227                 case DP_TRAINING_PATTERN_2:
3228                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3229                         break;
3230                 case DP_TRAINING_PATTERN_3:
3231                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3232                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3233                         break;
3234                 }
3235
3236         } else {
3237                 *DP &= ~DP_LINK_TRAIN_MASK;
3238
3239                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3240                 case DP_TRAINING_PATTERN_DISABLE:
3241                         *DP |= DP_LINK_TRAIN_OFF;
3242                         break;
3243                 case DP_TRAINING_PATTERN_1:
3244                         *DP |= DP_LINK_TRAIN_PAT_1;
3245                         break;
3246                 case DP_TRAINING_PATTERN_2:
3247                         *DP |= DP_LINK_TRAIN_PAT_2;
3248                         break;
3249                 case DP_TRAINING_PATTERN_3:
3250                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3251                         *DP |= DP_LINK_TRAIN_PAT_2;
3252                         break;
3253                 }
3254         }
3255 }
3256
3257 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3258                                  const struct intel_crtc_state *old_crtc_state)
3259 {
3260         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3261
3262         /* enable with pattern 1 (as per spec) */
3263
3264         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3265
3266         /*
3267          * Magic for VLV/CHV. We _must_ first set up the register
3268          * without actually enabling the port, and then do another
3269          * write to enable the port. Otherwise link training will
3270          * fail when the power sequencer is freshly used for this port.
3271          */
3272         intel_dp->DP |= DP_PORT_EN;
3273         if (old_crtc_state->has_audio)
3274                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3275
3276         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3277         POSTING_READ(intel_dp->output_reg);
3278 }
3279
3280 static void intel_enable_dp(struct intel_encoder *encoder,
3281                             const struct intel_crtc_state *pipe_config,
3282                             const struct drm_connector_state *conn_state)
3283 {
3284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3285         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3286         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3287         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3288         enum pipe pipe = crtc->pipe;
3289         intel_wakeref_t wakeref;
3290
3291         if (WARN_ON(dp_reg & DP_PORT_EN))
3292                 return;
3293
3294         with_pps_lock(intel_dp, wakeref) {
3295                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3296                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3297
3298                 intel_dp_enable_port(intel_dp, pipe_config);
3299
3300                 edp_panel_vdd_on(intel_dp);
3301                 edp_panel_on(intel_dp);
3302                 edp_panel_vdd_off(intel_dp, true);
3303         }
3304
3305         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3306                 unsigned int lane_mask = 0x0;
3307
3308                 if (IS_CHERRYVIEW(dev_priv))
3309                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3310
3311                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3312                                     lane_mask);
3313         }
3314
3315         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3316         intel_dp_start_link_train(intel_dp);
3317         intel_dp_stop_link_train(intel_dp);
3318
3319         if (pipe_config->has_audio) {
3320                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3321                                  pipe_name(pipe));
3322                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3323         }
3324 }
3325
3326 static void g4x_enable_dp(struct intel_encoder *encoder,
3327                           const struct intel_crtc_state *pipe_config,
3328                           const struct drm_connector_state *conn_state)
3329 {
3330         intel_enable_dp(encoder, pipe_config, conn_state);
3331         intel_edp_backlight_on(pipe_config, conn_state);
3332 }
3333
3334 static void vlv_enable_dp(struct intel_encoder *encoder,
3335                           const struct intel_crtc_state *pipe_config,
3336                           const struct drm_connector_state *conn_state)
3337 {
3338         intel_edp_backlight_on(pipe_config, conn_state);
3339 }
3340
3341 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3342                               const struct intel_crtc_state *pipe_config,
3343                               const struct drm_connector_state *conn_state)
3344 {
3345         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3346         enum port port = encoder->port;
3347
3348         intel_dp_prepare(encoder, pipe_config);
3349
3350         /* Only ilk+ has port A */
3351         if (port == PORT_A)
3352                 ironlake_edp_pll_on(intel_dp, pipe_config);
3353 }
3354
3355 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3356 {
3357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3358         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3359         enum pipe pipe = intel_dp->pps_pipe;
3360         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3361
3362         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3363
3364         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3365                 return;
3366
3367         edp_panel_vdd_off_sync(intel_dp);
3368
3369         /*
3370          * VLV seems to get confused when multiple power sequencers
3371          * have the same port selected (even if only one has power/vdd
3372          * enabled). The failure manifests as vlv_wait_port_ready() failing
3373          * CHV on the other hand doesn't seem to mind having the same port
3374          * selected in multiple power sequencers, but let's clear the
3375          * port select always when logically disconnecting a power sequencer
3376          * from a port.
3377          */
3378         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3379                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3380         I915_WRITE(pp_on_reg, 0);
3381         POSTING_READ(pp_on_reg);
3382
3383         intel_dp->pps_pipe = INVALID_PIPE;
3384 }
3385
3386 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3387                                       enum pipe pipe)
3388 {
3389         struct intel_encoder *encoder;
3390
3391         lockdep_assert_held(&dev_priv->pps_mutex);
3392
3393         for_each_intel_dp(&dev_priv->drm, encoder) {
3394                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3395                 enum port port = encoder->port;
3396
3397                 WARN(intel_dp->active_pipe == pipe,
3398                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3399                      pipe_name(pipe), port_name(port));
3400
3401                 if (intel_dp->pps_pipe != pipe)
3402                         continue;
3403
3404                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3405                               pipe_name(pipe), port_name(port));
3406
3407                 /* make sure vdd is off before we steal it */
3408                 vlv_detach_power_sequencer(intel_dp);
3409         }
3410 }
3411
3412 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3413                                            const struct intel_crtc_state *crtc_state)
3414 {
3415         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3416         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3417         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3418
3419         lockdep_assert_held(&dev_priv->pps_mutex);
3420
3421         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3422
3423         if (intel_dp->pps_pipe != INVALID_PIPE &&
3424             intel_dp->pps_pipe != crtc->pipe) {
3425                 /*
3426                  * If another power sequencer was being used on this
3427                  * port previously make sure to turn off vdd there while
3428                  * we still have control of it.
3429                  */
3430                 vlv_detach_power_sequencer(intel_dp);
3431         }
3432
3433         /*
3434          * We may be stealing the power
3435          * sequencer from another port.
3436          */
3437         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3438
3439         intel_dp->active_pipe = crtc->pipe;
3440
3441         if (!intel_dp_is_edp(intel_dp))
3442                 return;
3443
3444         /* now it's all ours */
3445         intel_dp->pps_pipe = crtc->pipe;
3446
3447         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3448                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3449
3450         /* init power sequencer on this pipe and port */
3451         intel_dp_init_panel_power_sequencer(intel_dp);
3452         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3453 }
3454
3455 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3456                               const struct intel_crtc_state *pipe_config,
3457                               const struct drm_connector_state *conn_state)
3458 {
3459         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3460
3461         intel_enable_dp(encoder, pipe_config, conn_state);
3462 }
3463
3464 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3465                                   const struct intel_crtc_state *pipe_config,
3466                                   const struct drm_connector_state *conn_state)
3467 {
3468         intel_dp_prepare(encoder, pipe_config);
3469
3470         vlv_phy_pre_pll_enable(encoder, pipe_config);
3471 }
3472
3473 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3474                               const struct intel_crtc_state *pipe_config,
3475                               const struct drm_connector_state *conn_state)
3476 {
3477         chv_phy_pre_encoder_enable(encoder, pipe_config);
3478
3479         intel_enable_dp(encoder, pipe_config, conn_state);
3480
3481         /* Second common lane will stay alive on its own now */
3482         chv_phy_release_cl2_override(encoder);
3483 }
3484
3485 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3486                                   const struct intel_crtc_state *pipe_config,
3487                                   const struct drm_connector_state *conn_state)
3488 {
3489         intel_dp_prepare(encoder, pipe_config);
3490
3491         chv_phy_pre_pll_enable(encoder, pipe_config);
3492 }
3493
3494 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3495                                     const struct intel_crtc_state *old_crtc_state,
3496                                     const struct drm_connector_state *old_conn_state)
3497 {
3498         chv_phy_post_pll_disable(encoder, old_crtc_state);
3499 }
3500
3501 /*
3502  * Fetch AUX CH registers 0x202 - 0x207 which contain
3503  * link status information
3504  */
3505 bool
3506 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3507 {
3508         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3509                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3510 }
3511
3512 /* These are source-specific values. */
3513 uint8_t
3514 intel_dp_voltage_max(struct intel_dp *intel_dp)
3515 {
3516         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3517         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3518         enum port port = encoder->port;
3519
3520         if (HAS_DDI(dev_priv))
3521                 return intel_ddi_dp_voltage_max(encoder);
3522         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3523                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3524         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3525                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3526         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3527                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3528         else
3529                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3530 }
3531
3532 uint8_t
3533 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3534 {
3535         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3536         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3537         enum port port = encoder->port;
3538
3539         if (HAS_DDI(dev_priv)) {
3540                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3541         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3542                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3543                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3544                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3545                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3546                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3547                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3548                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3549                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3550                 default:
3551                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3552                 }
3553         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3554                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3555                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3556                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3557                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3558                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3559                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3560                 default:
3561                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3562                 }
3563         } else {
3564                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3565                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3566                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3567                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3568                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3569                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3570                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3571                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3572                 default:
3573                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3574                 }
3575         }
3576 }
3577
3578 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3579 {
3580         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3581         unsigned long demph_reg_value, preemph_reg_value,
3582                 uniqtranscale_reg_value;
3583         uint8_t train_set = intel_dp->train_set[0];
3584
3585         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3586         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3587                 preemph_reg_value = 0x0004000;
3588                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3589                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3590                         demph_reg_value = 0x2B405555;
3591                         uniqtranscale_reg_value = 0x552AB83A;
3592                         break;
3593                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3594                         demph_reg_value = 0x2B404040;
3595                         uniqtranscale_reg_value = 0x5548B83A;
3596                         break;
3597                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3598                         demph_reg_value = 0x2B245555;
3599                         uniqtranscale_reg_value = 0x5560B83A;
3600                         break;
3601                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3602                         demph_reg_value = 0x2B405555;
3603                         uniqtranscale_reg_value = 0x5598DA3A;
3604                         break;
3605                 default:
3606                         return 0;
3607                 }
3608                 break;
3609         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3610                 preemph_reg_value = 0x0002000;
3611                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3612                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3613                         demph_reg_value = 0x2B404040;
3614                         uniqtranscale_reg_value = 0x5552B83A;
3615                         break;
3616                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3617                         demph_reg_value = 0x2B404848;
3618                         uniqtranscale_reg_value = 0x5580B83A;
3619                         break;
3620                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3621                         demph_reg_value = 0x2B404040;
3622                         uniqtranscale_reg_value = 0x55ADDA3A;
3623                         break;
3624                 default:
3625                         return 0;
3626                 }
3627                 break;
3628         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3629                 preemph_reg_value = 0x0000000;
3630                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3631                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3632                         demph_reg_value = 0x2B305555;
3633                         uniqtranscale_reg_value = 0x5570B83A;
3634                         break;
3635                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3636                         demph_reg_value = 0x2B2B4040;
3637                         uniqtranscale_reg_value = 0x55ADDA3A;
3638                         break;
3639                 default:
3640                         return 0;
3641                 }
3642                 break;
3643         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3644                 preemph_reg_value = 0x0006000;
3645                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3646                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3647                         demph_reg_value = 0x1B405555;
3648                         uniqtranscale_reg_value = 0x55ADDA3A;
3649                         break;
3650                 default:
3651                         return 0;
3652                 }
3653                 break;
3654         default:
3655                 return 0;
3656         }
3657
3658         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3659                                  uniqtranscale_reg_value, 0);
3660
3661         return 0;
3662 }
3663
3664 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3665 {
3666         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3667         u32 deemph_reg_value, margin_reg_value;
3668         bool uniq_trans_scale = false;
3669         uint8_t train_set = intel_dp->train_set[0];
3670
3671         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3672         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3673                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3674                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3675                         deemph_reg_value = 128;
3676                         margin_reg_value = 52;
3677                         break;
3678                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3679                         deemph_reg_value = 128;
3680                         margin_reg_value = 77;
3681                         break;
3682                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3683                         deemph_reg_value = 128;
3684                         margin_reg_value = 102;
3685                         break;
3686                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3687                         deemph_reg_value = 128;
3688                         margin_reg_value = 154;
3689                         uniq_trans_scale = true;
3690                         break;
3691                 default:
3692                         return 0;
3693                 }
3694                 break;
3695         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3696                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3697                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3698                         deemph_reg_value = 85;
3699                         margin_reg_value = 78;
3700                         break;
3701                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3702                         deemph_reg_value = 85;
3703                         margin_reg_value = 116;
3704                         break;
3705                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3706                         deemph_reg_value = 85;
3707                         margin_reg_value = 154;
3708                         break;
3709                 default:
3710                         return 0;
3711                 }
3712                 break;
3713         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3714                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3716                         deemph_reg_value = 64;
3717                         margin_reg_value = 104;
3718                         break;
3719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3720                         deemph_reg_value = 64;
3721                         margin_reg_value = 154;
3722                         break;
3723                 default:
3724                         return 0;
3725                 }
3726                 break;
3727         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3728                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3729                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3730                         deemph_reg_value = 43;
3731                         margin_reg_value = 154;
3732                         break;
3733                 default:
3734                         return 0;
3735                 }
3736                 break;
3737         default:
3738                 return 0;
3739         }
3740
3741         chv_set_phy_signal_level(encoder, deemph_reg_value,
3742                                  margin_reg_value, uniq_trans_scale);
3743
3744         return 0;
3745 }
3746
3747 static uint32_t
3748 g4x_signal_levels(uint8_t train_set)
3749 {
3750         uint32_t        signal_levels = 0;
3751
3752         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3753         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3754         default:
3755                 signal_levels |= DP_VOLTAGE_0_4;
3756                 break;
3757         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3758                 signal_levels |= DP_VOLTAGE_0_6;
3759                 break;
3760         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3761                 signal_levels |= DP_VOLTAGE_0_8;
3762                 break;
3763         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3764                 signal_levels |= DP_VOLTAGE_1_2;
3765                 break;
3766         }
3767         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3768         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3769         default:
3770                 signal_levels |= DP_PRE_EMPHASIS_0;
3771                 break;
3772         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3773                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3774                 break;
3775         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3776                 signal_levels |= DP_PRE_EMPHASIS_6;
3777                 break;
3778         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3779                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3780                 break;
3781         }
3782         return signal_levels;
3783 }
3784
3785 /* SNB CPU eDP voltage swing and pre-emphasis control */
3786 static uint32_t
3787 snb_cpu_edp_signal_levels(uint8_t train_set)
3788 {
3789         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3790                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3791         switch (signal_levels) {
3792         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3793         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3794                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3795         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3796                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3797         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3798         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3799                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3800         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3801         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3802                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3803         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3804         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3805                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3806         default:
3807                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3808                               "0x%x\n", signal_levels);
3809                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3810         }
3811 }
3812
3813 /* IVB CPU eDP voltage swing and pre-emphasis control */
3814 static uint32_t
3815 ivb_cpu_edp_signal_levels(uint8_t train_set)
3816 {
3817         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3818                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3819         switch (signal_levels) {
3820         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3821                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3822         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3823                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3824         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3825                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3826
3827         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3828                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3829         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3830                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3831
3832         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3833                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3834         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3835                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3836
3837         default:
3838                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3839                               "0x%x\n", signal_levels);
3840                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3841         }
3842 }
3843
3844 void
3845 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3846 {
3847         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3848         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3849         enum port port = intel_dig_port->base.port;
3850         uint32_t signal_levels, mask = 0;
3851         uint8_t train_set = intel_dp->train_set[0];
3852
3853         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3854                 signal_levels = bxt_signal_levels(intel_dp);
3855         } else if (HAS_DDI(dev_priv)) {
3856                 signal_levels = ddi_signal_levels(intel_dp);
3857                 mask = DDI_BUF_EMP_MASK;
3858         } else if (IS_CHERRYVIEW(dev_priv)) {
3859                 signal_levels = chv_signal_levels(intel_dp);
3860         } else if (IS_VALLEYVIEW(dev_priv)) {
3861                 signal_levels = vlv_signal_levels(intel_dp);
3862         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3863                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3864                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3865         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3866                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3867                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3868         } else {
3869                 signal_levels = g4x_signal_levels(train_set);
3870                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3871         }
3872
3873         if (mask)
3874                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3875
3876         DRM_DEBUG_KMS("Using vswing level %d\n",
3877                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3878         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3879                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3880                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3881
3882         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3883
3884         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3885         POSTING_READ(intel_dp->output_reg);
3886 }
3887
3888 void
3889 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3890                                        uint8_t dp_train_pat)
3891 {
3892         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3893         struct drm_i915_private *dev_priv =
3894                 to_i915(intel_dig_port->base.base.dev);
3895
3896         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3897
3898         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3899         POSTING_READ(intel_dp->output_reg);
3900 }
3901
3902 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3903 {
3904         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3905         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3906         enum port port = intel_dig_port->base.port;
3907         uint32_t val;
3908
3909         if (!HAS_DDI(dev_priv))
3910                 return;
3911
3912         val = I915_READ(DP_TP_CTL(port));
3913         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3914         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3915         I915_WRITE(DP_TP_CTL(port), val);
3916
3917         /*
3918          * On PORT_A we can have only eDP in SST mode. There the only reason
3919          * we need to set idle transmission mode is to work around a HW issue
3920          * where we enable the pipe while not in idle link-training mode.
3921          * In this case there is requirement to wait for a minimum number of
3922          * idle patterns to be sent.
3923          */
3924         if (port == PORT_A)
3925                 return;
3926
3927         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3928                                     DP_TP_STATUS_IDLE_DONE,
3929                                     DP_TP_STATUS_IDLE_DONE,
3930                                     1))
3931                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3932 }
3933
3934 static void
3935 intel_dp_link_down(struct intel_encoder *encoder,
3936                    const struct intel_crtc_state *old_crtc_state)
3937 {
3938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3939         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3940         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3941         enum port port = encoder->port;
3942         uint32_t DP = intel_dp->DP;
3943
3944         if (WARN_ON(HAS_DDI(dev_priv)))
3945                 return;
3946
3947         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3948                 return;
3949
3950         DRM_DEBUG_KMS("\n");
3951
3952         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3953             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3954                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3955                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3956         } else {
3957                 DP &= ~DP_LINK_TRAIN_MASK;
3958                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3959         }
3960         I915_WRITE(intel_dp->output_reg, DP);
3961         POSTING_READ(intel_dp->output_reg);
3962
3963         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3964         I915_WRITE(intel_dp->output_reg, DP);
3965         POSTING_READ(intel_dp->output_reg);
3966
3967         /*
3968          * HW workaround for IBX, we need to move the port
3969          * to transcoder A after disabling it to allow the
3970          * matching HDMI port to be enabled on transcoder A.
3971          */
3972         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3973                 /*
3974                  * We get CPU/PCH FIFO underruns on the other pipe when
3975                  * doing the workaround. Sweep them under the rug.
3976                  */
3977                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3978                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3979
3980                 /* always enable with pattern 1 (as per spec) */
3981                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3982                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3983                         DP_LINK_TRAIN_PAT_1;
3984                 I915_WRITE(intel_dp->output_reg, DP);
3985                 POSTING_READ(intel_dp->output_reg);
3986
3987                 DP &= ~DP_PORT_EN;
3988                 I915_WRITE(intel_dp->output_reg, DP);
3989                 POSTING_READ(intel_dp->output_reg);
3990
3991                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3992                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3993                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3994         }
3995
3996         msleep(intel_dp->panel_power_down_delay);
3997
3998         intel_dp->DP = DP;
3999
4000         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4001                 intel_wakeref_t wakeref;
4002
4003                 with_pps_lock(intel_dp, wakeref)
4004                         intel_dp->active_pipe = INVALID_PIPE;
4005         }
4006 }
4007
4008 static void
4009 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4010 {
4011         u8 dpcd_ext[6];
4012
4013         /*
4014          * Prior to DP1.3 the bit represented by
4015          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4016          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4017          * the true capability of the panel. The only way to check is to
4018          * then compare 0000h and 2200h.
4019          */
4020         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4021               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4022                 return;
4023
4024         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4025                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4026                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4027                 return;
4028         }
4029
4030         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4031                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4032                 return;
4033         }
4034
4035         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4036                 return;
4037
4038         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4039                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4040
4041         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4042 }
4043
4044 bool
4045 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4046 {
4047         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4048                              sizeof(intel_dp->dpcd)) < 0)
4049                 return false; /* aux transfer failed */
4050
4051         intel_dp_extended_receiver_capabilities(intel_dp);
4052
4053         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4054
4055         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4056 }
4057
4058 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4059 {
4060         /*
4061          * Clear the cached register set to avoid using stale values
4062          * for the sinks that do not support DSC.
4063          */
4064         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4065
4066         /* Clear fec_capable to avoid using stale values */
4067         intel_dp->fec_capable = 0;
4068
4069         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4070         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4071             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4072                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4073                                      intel_dp->dsc_dpcd,
4074                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4075                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4076                                   DP_DSC_SUPPORT);
4077
4078                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4079                               (int)sizeof(intel_dp->dsc_dpcd),
4080                               intel_dp->dsc_dpcd);
4081
4082                 /* FEC is supported only on DP 1.4 */
4083                 if (!intel_dp_is_edp(intel_dp) &&
4084                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4085                                       &intel_dp->fec_capable) < 0)
4086                         DRM_ERROR("Failed to read FEC DPCD register\n");
4087
4088                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4089         }
4090 }
4091
4092 static bool
4093 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4094 {
4095         struct drm_i915_private *dev_priv =
4096                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4097
4098         /* this function is meant to be called only once */
4099         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4100
4101         if (!intel_dp_read_dpcd(intel_dp))
4102                 return false;
4103
4104         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4105                          drm_dp_is_branch(intel_dp->dpcd));
4106
4107         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4108                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4109                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4110
4111         /*
4112          * Read the eDP display control registers.
4113          *
4114          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4115          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4116          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4117          * method). The display control registers should read zero if they're
4118          * not supported anyway.
4119          */
4120         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4121                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4122                              sizeof(intel_dp->edp_dpcd))
4123                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4124                               intel_dp->edp_dpcd);
4125
4126         /*
4127          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4128          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4129          */
4130         intel_psr_init_dpcd(intel_dp);
4131
4132         /* Read the eDP 1.4+ supported link rates. */
4133         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4134                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4135                 int i;
4136
4137                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4138                                 sink_rates, sizeof(sink_rates));
4139
4140                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4141                         int val = le16_to_cpu(sink_rates[i]);
4142
4143                         if (val == 0)
4144                                 break;
4145
4146                         /* Value read multiplied by 200kHz gives the per-lane
4147                          * link rate in kHz. The source rates are, however,
4148                          * stored in terms of LS_Clk kHz. The full conversion
4149                          * back to symbols is
4150                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4151                          */
4152                         intel_dp->sink_rates[i] = (val * 200) / 10;
4153                 }
4154                 intel_dp->num_sink_rates = i;
4155         }
4156
4157         /*
4158          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4159          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4160          */
4161         if (intel_dp->num_sink_rates)
4162                 intel_dp->use_rate_select = true;
4163         else
4164                 intel_dp_set_sink_rates(intel_dp);
4165
4166         intel_dp_set_common_rates(intel_dp);
4167
4168         /* Read the eDP DSC DPCD registers */
4169         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4170                 intel_dp_get_dsc_sink_cap(intel_dp);
4171
4172         return true;
4173 }
4174
4175
4176 static bool
4177 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4178 {
4179         if (!intel_dp_read_dpcd(intel_dp))
4180                 return false;
4181
4182         /* Don't clobber cached eDP rates. */
4183         if (!intel_dp_is_edp(intel_dp)) {
4184                 intel_dp_set_sink_rates(intel_dp);
4185                 intel_dp_set_common_rates(intel_dp);
4186         }
4187
4188         /*
4189          * Some eDP panels do not set a valid value for sink count, that is why
4190          * it don't care about read it here and in intel_edp_init_dpcd().
4191          */
4192         if (!intel_dp_is_edp(intel_dp)) {
4193                 u8 count;
4194                 ssize_t r;
4195
4196                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4197                 if (r < 1)
4198                         return false;
4199
4200                 /*
4201                  * Sink count can change between short pulse hpd hence
4202                  * a member variable in intel_dp will track any changes
4203                  * between short pulse interrupts.
4204                  */
4205                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4206
4207                 /*
4208                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4209                  * a dongle is present but no display. Unless we require to know
4210                  * if a dongle is present or not, we don't need to update
4211                  * downstream port information. So, an early return here saves
4212                  * time from performing other operations which are not required.
4213                  */
4214                 if (!intel_dp->sink_count)
4215                         return false;
4216         }
4217
4218         if (!drm_dp_is_branch(intel_dp->dpcd))
4219                 return true; /* native DP sink */
4220
4221         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4222                 return true; /* no per-port downstream info */
4223
4224         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4225                              intel_dp->downstream_ports,
4226                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4227                 return false; /* downstream port status fetch failed */
4228
4229         return true;
4230 }
4231
4232 static bool
4233 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4234 {
4235         u8 mstm_cap;
4236
4237         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4238                 return false;
4239
4240         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4241                 return false;
4242
4243         return mstm_cap & DP_MST_CAP;
4244 }
4245
4246 static bool
4247 intel_dp_can_mst(struct intel_dp *intel_dp)
4248 {
4249         return i915_modparams.enable_dp_mst &&
4250                 intel_dp->can_mst &&
4251                 intel_dp_sink_can_mst(intel_dp);
4252 }
4253
4254 static void
4255 intel_dp_configure_mst(struct intel_dp *intel_dp)
4256 {
4257         struct intel_encoder *encoder =
4258                 &dp_to_dig_port(intel_dp)->base;
4259         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4260
4261         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4262                       port_name(encoder->port), yesno(intel_dp->can_mst),
4263                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4264
4265         if (!intel_dp->can_mst)
4266                 return;
4267
4268         intel_dp->is_mst = sink_can_mst &&
4269                 i915_modparams.enable_dp_mst;
4270
4271         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4272                                         intel_dp->is_mst);
4273 }
4274
4275 static bool
4276 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4277 {
4278         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4279                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4280                 DP_DPRX_ESI_LEN;
4281 }
4282
4283 u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
4284                                 int mode_clock, int mode_hdisplay)
4285 {
4286         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4287         int i;
4288
4289         /*
4290          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4291          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4292          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4293          * for MST -> TimeSlotsPerMTP has to be calculated
4294          */
4295         bits_per_pixel = (link_clock * lane_count * 8 *
4296                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4297                 mode_clock;
4298
4299         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4300         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4301                 mode_hdisplay;
4302
4303         /*
4304          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4305          * check, output bpp from small joiner RAM check)
4306          */
4307         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4308
4309         /* Error out if the max bpp is less than smallest allowed valid bpp */
4310         if (bits_per_pixel < valid_dsc_bpp[0]) {
4311                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4312                 return 0;
4313         }
4314
4315         /* Find the nearest match in the array of known BPPs from VESA */
4316         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4317                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4318                         break;
4319         }
4320         bits_per_pixel = valid_dsc_bpp[i];
4321
4322         /*
4323          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4324          * fractional part is 0
4325          */
4326         return bits_per_pixel << 4;
4327 }
4328
4329 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4330                                 int mode_clock,
4331                                 int mode_hdisplay)
4332 {
4333         u8 min_slice_count, i;
4334         int max_slice_width;
4335
4336         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4337                 min_slice_count = DIV_ROUND_UP(mode_clock,
4338                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4339         else
4340                 min_slice_count = DIV_ROUND_UP(mode_clock,
4341                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4342
4343         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4344         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4345                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4346                               max_slice_width);
4347                 return 0;
4348         }
4349         /* Also take into account max slice width */
4350         min_slice_count = min_t(uint8_t, min_slice_count,
4351                                 DIV_ROUND_UP(mode_hdisplay,
4352                                              max_slice_width));
4353
4354         /* Find the closest match to the valid slice count values */
4355         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4356                 if (valid_dsc_slicecount[i] >
4357                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4358                                                     false))
4359                         break;
4360                 if (min_slice_count  <= valid_dsc_slicecount[i])
4361                         return valid_dsc_slicecount[i];
4362         }
4363
4364         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4365         return 0;
4366 }
4367
4368 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4369 {
4370         int status = 0;
4371         int test_link_rate;
4372         uint8_t test_lane_count, test_link_bw;
4373         /* (DP CTS 1.2)
4374          * 4.3.1.11
4375          */
4376         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4377         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4378                                    &test_lane_count);
4379
4380         if (status <= 0) {
4381                 DRM_DEBUG_KMS("Lane count read failed\n");
4382                 return DP_TEST_NAK;
4383         }
4384         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4385
4386         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4387                                    &test_link_bw);
4388         if (status <= 0) {
4389                 DRM_DEBUG_KMS("Link Rate read failed\n");
4390                 return DP_TEST_NAK;
4391         }
4392         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4393
4394         /* Validate the requested link rate and lane count */
4395         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4396                                         test_lane_count))
4397                 return DP_TEST_NAK;
4398
4399         intel_dp->compliance.test_lane_count = test_lane_count;
4400         intel_dp->compliance.test_link_rate = test_link_rate;
4401
4402         return DP_TEST_ACK;
4403 }
4404
4405 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4406 {
4407         uint8_t test_pattern;
4408         uint8_t test_misc;
4409         __be16 h_width, v_height;
4410         int status = 0;
4411
4412         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4413         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4414                                    &test_pattern);
4415         if (status <= 0) {
4416                 DRM_DEBUG_KMS("Test pattern read failed\n");
4417                 return DP_TEST_NAK;
4418         }
4419         if (test_pattern != DP_COLOR_RAMP)
4420                 return DP_TEST_NAK;
4421
4422         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4423                                   &h_width, 2);
4424         if (status <= 0) {
4425                 DRM_DEBUG_KMS("H Width read failed\n");
4426                 return DP_TEST_NAK;
4427         }
4428
4429         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4430                                   &v_height, 2);
4431         if (status <= 0) {
4432                 DRM_DEBUG_KMS("V Height read failed\n");
4433                 return DP_TEST_NAK;
4434         }
4435
4436         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4437                                    &test_misc);
4438         if (status <= 0) {
4439                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4440                 return DP_TEST_NAK;
4441         }
4442         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4443                 return DP_TEST_NAK;
4444         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4445                 return DP_TEST_NAK;
4446         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4447         case DP_TEST_BIT_DEPTH_6:
4448                 intel_dp->compliance.test_data.bpc = 6;
4449                 break;
4450         case DP_TEST_BIT_DEPTH_8:
4451                 intel_dp->compliance.test_data.bpc = 8;
4452                 break;
4453         default:
4454                 return DP_TEST_NAK;
4455         }
4456
4457         intel_dp->compliance.test_data.video_pattern = test_pattern;
4458         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4459         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4460         /* Set test active flag here so userspace doesn't interrupt things */
4461         intel_dp->compliance.test_active = 1;
4462
4463         return DP_TEST_ACK;
4464 }
4465
4466 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4467 {
4468         uint8_t test_result = DP_TEST_ACK;
4469         struct intel_connector *intel_connector = intel_dp->attached_connector;
4470         struct drm_connector *connector = &intel_connector->base;
4471
4472         if (intel_connector->detect_edid == NULL ||
4473             connector->edid_corrupt ||
4474             intel_dp->aux.i2c_defer_count > 6) {
4475                 /* Check EDID read for NACKs, DEFERs and corruption
4476                  * (DP CTS 1.2 Core r1.1)
4477                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4478                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4479                  *    4.2.2.6 : EDID corruption detected
4480                  * Use failsafe mode for all cases
4481                  */
4482                 if (intel_dp->aux.i2c_nack_count > 0 ||
4483                         intel_dp->aux.i2c_defer_count > 0)
4484                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4485                                       intel_dp->aux.i2c_nack_count,
4486                                       intel_dp->aux.i2c_defer_count);
4487                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4488         } else {
4489                 struct edid *block = intel_connector->detect_edid;
4490
4491                 /* We have to write the checksum
4492                  * of the last block read
4493                  */
4494                 block += intel_connector->detect_edid->extensions;
4495
4496                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4497                                        block->checksum) <= 0)
4498                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4499
4500                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4501                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4502         }
4503
4504         /* Set test active flag here so userspace doesn't interrupt things */
4505         intel_dp->compliance.test_active = 1;
4506
4507         return test_result;
4508 }
4509
4510 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4511 {
4512         uint8_t test_result = DP_TEST_NAK;
4513         return test_result;
4514 }
4515
4516 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4517 {
4518         uint8_t response = DP_TEST_NAK;
4519         uint8_t request = 0;
4520         int status;
4521
4522         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4523         if (status <= 0) {
4524                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4525                 goto update_status;
4526         }
4527
4528         switch (request) {
4529         case DP_TEST_LINK_TRAINING:
4530                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4531                 response = intel_dp_autotest_link_training(intel_dp);
4532                 break;
4533         case DP_TEST_LINK_VIDEO_PATTERN:
4534                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4535                 response = intel_dp_autotest_video_pattern(intel_dp);
4536                 break;
4537         case DP_TEST_LINK_EDID_READ:
4538                 DRM_DEBUG_KMS("EDID test requested\n");
4539                 response = intel_dp_autotest_edid(intel_dp);
4540                 break;
4541         case DP_TEST_LINK_PHY_TEST_PATTERN:
4542                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4543                 response = intel_dp_autotest_phy_pattern(intel_dp);
4544                 break;
4545         default:
4546                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4547                 break;
4548         }
4549
4550         if (response & DP_TEST_ACK)
4551                 intel_dp->compliance.test_type = request;
4552
4553 update_status:
4554         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4555         if (status <= 0)
4556                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4557 }
4558
4559 static int
4560 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4561 {
4562         bool bret;
4563
4564         if (intel_dp->is_mst) {
4565                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4566                 int ret = 0;
4567                 int retry;
4568                 bool handled;
4569
4570                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4571                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4572 go_again:
4573                 if (bret == true) {
4574
4575                         /* check link status - esi[10] = 0x200c */
4576                         if (intel_dp->active_mst_links > 0 &&
4577                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4578                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4579                                 intel_dp_start_link_train(intel_dp);
4580                                 intel_dp_stop_link_train(intel_dp);
4581                         }
4582
4583                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4584                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4585
4586                         if (handled) {
4587                                 for (retry = 0; retry < 3; retry++) {
4588                                         int wret;
4589                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4590                                                                  DP_SINK_COUNT_ESI+1,
4591                                                                  &esi[1], 3);
4592                                         if (wret == 3) {
4593                                                 break;
4594                                         }
4595                                 }
4596
4597                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4598                                 if (bret == true) {
4599                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4600                                         goto go_again;
4601                                 }
4602                         } else
4603                                 ret = 0;
4604
4605                         return ret;
4606                 } else {
4607                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4608                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4609                         intel_dp->is_mst = false;
4610                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4611                         /* send a hotplug event */
4612                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4613                 }
4614         }
4615         return -EINVAL;
4616 }
4617
4618 static bool
4619 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4620 {
4621         u8 link_status[DP_LINK_STATUS_SIZE];
4622
4623         if (!intel_dp->link_trained)
4624                 return false;
4625
4626         /*
4627          * While PSR source HW is enabled, it will control main-link sending
4628          * frames, enabling and disabling it so trying to do a retrain will fail
4629          * as the link would or not be on or it could mix training patterns
4630          * and frame data at the same time causing retrain to fail.
4631          * Also when exiting PSR, HW will retrain the link anyways fixing
4632          * any link status error.
4633          */
4634         if (intel_psr_enabled(intel_dp))
4635                 return false;
4636
4637         if (!intel_dp_get_link_status(intel_dp, link_status))
4638                 return false;
4639
4640         /*
4641          * Validate the cached values of intel_dp->link_rate and
4642          * intel_dp->lane_count before attempting to retrain.
4643          */
4644         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4645                                         intel_dp->lane_count))
4646                 return false;
4647
4648         /* Retrain if Channel EQ or CR not ok */
4649         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4650 }
4651
4652 int intel_dp_retrain_link(struct intel_encoder *encoder,
4653                           struct drm_modeset_acquire_ctx *ctx)
4654 {
4655         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4656         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4657         struct intel_connector *connector = intel_dp->attached_connector;
4658         struct drm_connector_state *conn_state;
4659         struct intel_crtc_state *crtc_state;
4660         struct intel_crtc *crtc;
4661         int ret;
4662
4663         /* FIXME handle the MST connectors as well */
4664
4665         if (!connector || connector->base.status != connector_status_connected)
4666                 return 0;
4667
4668         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4669                                ctx);
4670         if (ret)
4671                 return ret;
4672
4673         conn_state = connector->base.state;
4674
4675         crtc = to_intel_crtc(conn_state->crtc);
4676         if (!crtc)
4677                 return 0;
4678
4679         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4680         if (ret)
4681                 return ret;
4682
4683         crtc_state = to_intel_crtc_state(crtc->base.state);
4684
4685         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4686
4687         if (!crtc_state->base.active)
4688                 return 0;
4689
4690         if (conn_state->commit &&
4691             !try_wait_for_completion(&conn_state->commit->hw_done))
4692                 return 0;
4693
4694         if (!intel_dp_needs_link_retrain(intel_dp))
4695                 return 0;
4696
4697         /* Suppress underruns caused by re-training */
4698         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4699         if (crtc_state->has_pch_encoder)
4700                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4701                                                       intel_crtc_pch_transcoder(crtc), false);
4702
4703         intel_dp_start_link_train(intel_dp);
4704         intel_dp_stop_link_train(intel_dp);
4705
4706         /* Keep underrun reporting disabled until things are stable */
4707         intel_wait_for_vblank(dev_priv, crtc->pipe);
4708
4709         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4710         if (crtc_state->has_pch_encoder)
4711                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4712                                                       intel_crtc_pch_transcoder(crtc), true);
4713
4714         return 0;
4715 }
4716
4717 /*
4718  * If display is now connected check links status,
4719  * there has been known issues of link loss triggering
4720  * long pulse.
4721  *
4722  * Some sinks (eg. ASUS PB287Q) seem to perform some
4723  * weird HPD ping pong during modesets. So we can apparently
4724  * end up with HPD going low during a modeset, and then
4725  * going back up soon after. And once that happens we must
4726  * retrain the link to get a picture. That's in case no
4727  * userspace component reacted to intermittent HPD dip.
4728  */
4729 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4730                              struct intel_connector *connector)
4731 {
4732         struct drm_modeset_acquire_ctx ctx;
4733         bool changed;
4734         int ret;
4735
4736         changed = intel_encoder_hotplug(encoder, connector);
4737
4738         drm_modeset_acquire_init(&ctx, 0);
4739
4740         for (;;) {
4741                 ret = intel_dp_retrain_link(encoder, &ctx);
4742
4743                 if (ret == -EDEADLK) {
4744                         drm_modeset_backoff(&ctx);
4745                         continue;
4746                 }
4747
4748                 break;
4749         }
4750
4751         drm_modeset_drop_locks(&ctx);
4752         drm_modeset_acquire_fini(&ctx);
4753         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4754
4755         return changed;
4756 }
4757
4758 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4759 {
4760         u8 val;
4761
4762         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4763                 return;
4764
4765         if (drm_dp_dpcd_readb(&intel_dp->aux,
4766                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4767                 return;
4768
4769         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4770
4771         if (val & DP_AUTOMATED_TEST_REQUEST)
4772                 intel_dp_handle_test_request(intel_dp);
4773
4774         if (val & DP_CP_IRQ)
4775                 intel_hdcp_check_link(intel_dp->attached_connector);
4776
4777         if (val & DP_SINK_SPECIFIC_IRQ)
4778                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4779 }
4780
4781 /*
4782  * According to DP spec
4783  * 5.1.2:
4784  *  1. Read DPCD
4785  *  2. Configure link according to Receiver Capabilities
4786  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4787  *  4. Check link status on receipt of hot-plug interrupt
4788  *
4789  * intel_dp_short_pulse -  handles short pulse interrupts
4790  * when full detection is not required.
4791  * Returns %true if short pulse is handled and full detection
4792  * is NOT required and %false otherwise.
4793  */
4794 static bool
4795 intel_dp_short_pulse(struct intel_dp *intel_dp)
4796 {
4797         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4798         u8 old_sink_count = intel_dp->sink_count;
4799         bool ret;
4800
4801         /*
4802          * Clearing compliance test variables to allow capturing
4803          * of values for next automated test request.
4804          */
4805         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4806
4807         /*
4808          * Now read the DPCD to see if it's actually running
4809          * If the current value of sink count doesn't match with
4810          * the value that was stored earlier or dpcd read failed
4811          * we need to do full detection
4812          */
4813         ret = intel_dp_get_dpcd(intel_dp);
4814
4815         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4816                 /* No need to proceed if we are going to do full detect */
4817                 return false;
4818         }
4819
4820         intel_dp_check_service_irq(intel_dp);
4821
4822         /* Handle CEC interrupts, if any */
4823         drm_dp_cec_irq(&intel_dp->aux);
4824
4825         /* defer to the hotplug work for link retraining if needed */
4826         if (intel_dp_needs_link_retrain(intel_dp))
4827                 return false;
4828
4829         intel_psr_short_pulse(intel_dp);
4830
4831         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4832                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4833                 /* Send a Hotplug Uevent to userspace to start modeset */
4834                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4835         }
4836
4837         return true;
4838 }
4839
4840 /* XXX this is probably wrong for multiple downstream ports */
4841 static enum drm_connector_status
4842 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4843 {
4844         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4845         uint8_t *dpcd = intel_dp->dpcd;
4846         uint8_t type;
4847
4848         if (lspcon->active)
4849                 lspcon_resume(lspcon);
4850
4851         if (!intel_dp_get_dpcd(intel_dp))
4852                 return connector_status_disconnected;
4853
4854         if (intel_dp_is_edp(intel_dp))
4855                 return connector_status_connected;
4856
4857         /* if there's no downstream port, we're done */
4858         if (!drm_dp_is_branch(dpcd))
4859                 return connector_status_connected;
4860
4861         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4862         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4863             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4864
4865                 return intel_dp->sink_count ?
4866                 connector_status_connected : connector_status_disconnected;
4867         }
4868
4869         if (intel_dp_can_mst(intel_dp))
4870                 return connector_status_connected;
4871
4872         /* If no HPD, poke DDC gently */
4873         if (drm_probe_ddc(&intel_dp->aux.ddc))
4874                 return connector_status_connected;
4875
4876         /* Well we tried, say unknown for unreliable port types */
4877         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4878                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4879                 if (type == DP_DS_PORT_TYPE_VGA ||
4880                     type == DP_DS_PORT_TYPE_NON_EDID)
4881                         return connector_status_unknown;
4882         } else {
4883                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4884                         DP_DWN_STRM_PORT_TYPE_MASK;
4885                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4886                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4887                         return connector_status_unknown;
4888         }
4889
4890         /* Anything else is out of spec, warn and ignore */
4891         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4892         return connector_status_disconnected;
4893 }
4894
4895 static enum drm_connector_status
4896 edp_detect(struct intel_dp *intel_dp)
4897 {
4898         return connector_status_connected;
4899 }
4900
4901 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4902 {
4903         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4904         u32 bit;
4905
4906         switch (encoder->hpd_pin) {
4907         case HPD_PORT_B:
4908                 bit = SDE_PORTB_HOTPLUG;
4909                 break;
4910         case HPD_PORT_C:
4911                 bit = SDE_PORTC_HOTPLUG;
4912                 break;
4913         case HPD_PORT_D:
4914                 bit = SDE_PORTD_HOTPLUG;
4915                 break;
4916         default:
4917                 MISSING_CASE(encoder->hpd_pin);
4918                 return false;
4919         }
4920
4921         return I915_READ(SDEISR) & bit;
4922 }
4923
4924 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4925 {
4926         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4927         u32 bit;
4928
4929         switch (encoder->hpd_pin) {
4930         case HPD_PORT_B:
4931                 bit = SDE_PORTB_HOTPLUG_CPT;
4932                 break;
4933         case HPD_PORT_C:
4934                 bit = SDE_PORTC_HOTPLUG_CPT;
4935                 break;
4936         case HPD_PORT_D:
4937                 bit = SDE_PORTD_HOTPLUG_CPT;
4938                 break;
4939         default:
4940                 MISSING_CASE(encoder->hpd_pin);
4941                 return false;
4942         }
4943
4944         return I915_READ(SDEISR) & bit;
4945 }
4946
4947 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4948 {
4949         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4950         u32 bit;
4951
4952         switch (encoder->hpd_pin) {
4953         case HPD_PORT_A:
4954                 bit = SDE_PORTA_HOTPLUG_SPT;
4955                 break;
4956         case HPD_PORT_E:
4957                 bit = SDE_PORTE_HOTPLUG_SPT;
4958                 break;
4959         default:
4960                 return cpt_digital_port_connected(encoder);
4961         }
4962
4963         return I915_READ(SDEISR) & bit;
4964 }
4965
4966 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4967 {
4968         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4969         u32 bit;
4970
4971         switch (encoder->hpd_pin) {
4972         case HPD_PORT_B:
4973                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4974                 break;
4975         case HPD_PORT_C:
4976                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4977                 break;
4978         case HPD_PORT_D:
4979                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4980                 break;
4981         default:
4982                 MISSING_CASE(encoder->hpd_pin);
4983                 return false;
4984         }
4985
4986         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4987 }
4988
4989 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4990 {
4991         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4992         u32 bit;
4993
4994         switch (encoder->hpd_pin) {
4995         case HPD_PORT_B:
4996                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4997                 break;
4998         case HPD_PORT_C:
4999                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5000                 break;
5001         case HPD_PORT_D:
5002                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5003                 break;
5004         default:
5005                 MISSING_CASE(encoder->hpd_pin);
5006                 return false;
5007         }
5008
5009         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5010 }
5011
5012 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5013 {
5014         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5015
5016         if (encoder->hpd_pin == HPD_PORT_A)
5017                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5018         else
5019                 return ibx_digital_port_connected(encoder);
5020 }
5021
5022 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5023 {
5024         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5025
5026         if (encoder->hpd_pin == HPD_PORT_A)
5027                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5028         else
5029                 return cpt_digital_port_connected(encoder);
5030 }
5031
5032 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5033 {
5034         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5035
5036         if (encoder->hpd_pin == HPD_PORT_A)
5037                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5038         else
5039                 return cpt_digital_port_connected(encoder);
5040 }
5041
5042 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5043 {
5044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5045
5046         if (encoder->hpd_pin == HPD_PORT_A)
5047                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5048         else
5049                 return cpt_digital_port_connected(encoder);
5050 }
5051
5052 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5053 {
5054         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5055         u32 bit;
5056
5057         switch (encoder->hpd_pin) {
5058         case HPD_PORT_A:
5059                 bit = BXT_DE_PORT_HP_DDIA;
5060                 break;
5061         case HPD_PORT_B:
5062                 bit = BXT_DE_PORT_HP_DDIB;
5063                 break;
5064         case HPD_PORT_C:
5065                 bit = BXT_DE_PORT_HP_DDIC;
5066                 break;
5067         default:
5068                 MISSING_CASE(encoder->hpd_pin);
5069                 return false;
5070         }
5071
5072         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5073 }
5074
5075 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5076                                      struct intel_digital_port *intel_dig_port)
5077 {
5078         enum port port = intel_dig_port->base.port;
5079
5080         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5081 }
5082
5083 static const char *tc_type_name(enum tc_port_type type)
5084 {
5085         static const char * const names[] = {
5086                 [TC_PORT_UNKNOWN] = "unknown",
5087                 [TC_PORT_LEGACY] = "legacy",
5088                 [TC_PORT_TYPEC] = "typec",
5089                 [TC_PORT_TBT] = "tbt",
5090         };
5091
5092         if (WARN_ON(type >= ARRAY_SIZE(names)))
5093                 type = TC_PORT_UNKNOWN;
5094
5095         return names[type];
5096 }
5097
5098 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5099                                     struct intel_digital_port *intel_dig_port,
5100                                     bool is_legacy, bool is_typec, bool is_tbt)
5101 {
5102         enum port port = intel_dig_port->base.port;
5103         enum tc_port_type old_type = intel_dig_port->tc_type;
5104
5105         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5106
5107         if (is_legacy)
5108                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5109         else if (is_typec)
5110                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5111         else if (is_tbt)
5112                 intel_dig_port->tc_type = TC_PORT_TBT;
5113         else
5114                 return;
5115
5116         /* Types are not supposed to be changed at runtime. */
5117         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5118                 old_type != intel_dig_port->tc_type);
5119
5120         if (old_type != intel_dig_port->tc_type)
5121                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5122                               tc_type_name(intel_dig_port->tc_type));
5123 }
5124
5125 /*
5126  * This function implements the first part of the Connect Flow described by our
5127  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5128  * lanes, EDID, etc) is done as needed in the typical places.
5129  *
5130  * Unlike the other ports, type-C ports are not available to use as soon as we
5131  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5132  * display, USB, etc. As a result, handshaking through FIA is required around
5133  * connect and disconnect to cleanly transfer ownership with the controller and
5134  * set the type-C power state.
5135  *
5136  * We could opt to only do the connect flow when we actually try to use the AUX
5137  * channels or do a modeset, then immediately run the disconnect flow after
5138  * usage, but there are some implications on this for a dynamic environment:
5139  * things may go away or change behind our backs. So for now our driver is
5140  * always trying to acquire ownership of the controller as soon as it gets an
5141  * interrupt (or polls state and sees a port is connected) and only gives it
5142  * back when it sees a disconnect. Implementation of a more fine-grained model
5143  * will require a lot of coordination with user space and thorough testing for
5144  * the extra possible cases.
5145  */
5146 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5147                                struct intel_digital_port *dig_port)
5148 {
5149         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5150         u32 val;
5151
5152         if (dig_port->tc_type != TC_PORT_LEGACY &&
5153             dig_port->tc_type != TC_PORT_TYPEC)
5154                 return true;
5155
5156         val = I915_READ(PORT_TX_DFLEXDPPMS);
5157         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5158                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5159                 WARN_ON(dig_port->tc_legacy_port);
5160                 return false;
5161         }
5162
5163         /*
5164          * This function may be called many times in a row without an HPD event
5165          * in between, so try to avoid the write when we can.
5166          */
5167         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5168         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5169                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5170                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5171         }
5172
5173         /*
5174          * Now we have to re-check the live state, in case the port recently
5175          * became disconnected. Not necessary for legacy mode.
5176          */
5177         if (dig_port->tc_type == TC_PORT_TYPEC &&
5178             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5179                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5180                 icl_tc_phy_disconnect(dev_priv, dig_port);
5181                 return false;
5182         }
5183
5184         return true;
5185 }
5186
5187 /*
5188  * See the comment at the connect function. This implements the Disconnect
5189  * Flow.
5190  */
5191 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5192                            struct intel_digital_port *dig_port)
5193 {
5194         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5195
5196         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5197                 return;
5198
5199         /*
5200          * TBT disconnection flow is read the live status, what was done in
5201          * caller.
5202          */
5203         if (dig_port->tc_type == TC_PORT_TYPEC ||
5204             dig_port->tc_type == TC_PORT_LEGACY) {
5205                 u32 val;
5206
5207                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5208                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5209                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5210         }
5211
5212         DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5213                       port_name(dig_port->base.port),
5214                       tc_type_name(dig_port->tc_type));
5215
5216         dig_port->tc_type = TC_PORT_UNKNOWN;
5217 }
5218
5219 /*
5220  * The type-C ports are different because even when they are connected, they may
5221  * not be available/usable by the graphics driver: see the comment on
5222  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5223  * concept of "usable" and make everything check for "connected and usable" we
5224  * define a port as "connected" when it is not only connected, but also when it
5225  * is usable by the rest of the driver. That maintains the old assumption that
5226  * connected ports are usable, and avoids exposing to the users objects they
5227  * can't really use.
5228  */
5229 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5230                                   struct intel_digital_port *intel_dig_port)
5231 {
5232         enum port port = intel_dig_port->base.port;
5233         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5234         bool is_legacy, is_typec, is_tbt;
5235         u32 dpsp;
5236
5237         /*
5238          * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5239          * legacy. Treat the port as legacy from now on.
5240          */
5241         if (WARN_ON(!intel_dig_port->tc_legacy_port &&
5242                     I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)))
5243                 intel_dig_port->tc_legacy_port = true;
5244         is_legacy = intel_dig_port->tc_legacy_port;
5245
5246         /*
5247          * The spec says we shouldn't be using the ISR bits for detecting
5248          * between TC and TBT. We should use DFLEXDPSP.
5249          */
5250         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5251         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5252         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5253
5254         if (!is_legacy && !is_typec && !is_tbt) {
5255                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5256
5257                 return false;
5258         }
5259
5260         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5261                                 is_tbt);
5262
5263         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5264                 return false;
5265
5266         return true;
5267 }
5268
5269 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5270 {
5271         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5272         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5273
5274         if (intel_port_is_combophy(dev_priv, encoder->port))
5275                 return icl_combo_port_connected(dev_priv, dig_port);
5276         else if (intel_port_is_tc(dev_priv, encoder->port))
5277                 return icl_tc_port_connected(dev_priv, dig_port);
5278         else
5279                 MISSING_CASE(encoder->hpd_pin);
5280
5281         return false;
5282 }
5283
5284 /*
5285  * intel_digital_port_connected - is the specified port connected?
5286  * @encoder: intel_encoder
5287  *
5288  * In cases where there's a connector physically connected but it can't be used
5289  * by our hardware we also return false, since the rest of the driver should
5290  * pretty much treat the port as disconnected. This is relevant for type-C
5291  * (starting on ICL) where there's ownership involved.
5292  *
5293  * Return %true if port is connected, %false otherwise.
5294  */
5295 bool intel_digital_port_connected(struct intel_encoder *encoder)
5296 {
5297         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5298
5299         if (HAS_GMCH_DISPLAY(dev_priv)) {
5300                 if (IS_GM45(dev_priv))
5301                         return gm45_digital_port_connected(encoder);
5302                 else
5303                         return g4x_digital_port_connected(encoder);
5304         }
5305
5306         if (INTEL_GEN(dev_priv) >= 11)
5307                 return icl_digital_port_connected(encoder);
5308         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5309                 return spt_digital_port_connected(encoder);
5310         else if (IS_GEN9_LP(dev_priv))
5311                 return bxt_digital_port_connected(encoder);
5312         else if (IS_GEN(dev_priv, 8))
5313                 return bdw_digital_port_connected(encoder);
5314         else if (IS_GEN(dev_priv, 7))
5315                 return ivb_digital_port_connected(encoder);
5316         else if (IS_GEN(dev_priv, 6))
5317                 return snb_digital_port_connected(encoder);
5318         else if (IS_GEN(dev_priv, 5))
5319                 return ilk_digital_port_connected(encoder);
5320
5321         MISSING_CASE(INTEL_GEN(dev_priv));
5322         return false;
5323 }
5324
5325 static struct edid *
5326 intel_dp_get_edid(struct intel_dp *intel_dp)
5327 {
5328         struct intel_connector *intel_connector = intel_dp->attached_connector;
5329
5330         /* use cached edid if we have one */
5331         if (intel_connector->edid) {
5332                 /* invalid edid */
5333                 if (IS_ERR(intel_connector->edid))
5334                         return NULL;
5335
5336                 return drm_edid_duplicate(intel_connector->edid);
5337         } else
5338                 return drm_get_edid(&intel_connector->base,
5339                                     &intel_dp->aux.ddc);
5340 }
5341
5342 static void
5343 intel_dp_set_edid(struct intel_dp *intel_dp)
5344 {
5345         struct intel_connector *intel_connector = intel_dp->attached_connector;
5346         struct edid *edid;
5347
5348         intel_dp_unset_edid(intel_dp);
5349         edid = intel_dp_get_edid(intel_dp);
5350         intel_connector->detect_edid = edid;
5351
5352         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5353         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5354 }
5355
5356 static void
5357 intel_dp_unset_edid(struct intel_dp *intel_dp)
5358 {
5359         struct intel_connector *intel_connector = intel_dp->attached_connector;
5360
5361         drm_dp_cec_unset_edid(&intel_dp->aux);
5362         kfree(intel_connector->detect_edid);
5363         intel_connector->detect_edid = NULL;
5364
5365         intel_dp->has_audio = false;
5366 }
5367
5368 static int
5369 intel_dp_detect(struct drm_connector *connector,
5370                 struct drm_modeset_acquire_ctx *ctx,
5371                 bool force)
5372 {
5373         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5374         struct intel_dp *intel_dp = intel_attached_dp(connector);
5375         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5376         struct intel_encoder *encoder = &dig_port->base;
5377         enum drm_connector_status status;
5378         enum intel_display_power_domain aux_domain =
5379                 intel_aux_power_domain(dig_port);
5380         intel_wakeref_t wakeref;
5381
5382         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5383                       connector->base.id, connector->name);
5384         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5385
5386         wakeref = intel_display_power_get(dev_priv, aux_domain);
5387
5388         /* Can't disconnect eDP */
5389         if (intel_dp_is_edp(intel_dp))
5390                 status = edp_detect(intel_dp);
5391         else if (intel_digital_port_connected(encoder))
5392                 status = intel_dp_detect_dpcd(intel_dp);
5393         else
5394                 status = connector_status_disconnected;
5395
5396         if (status == connector_status_disconnected) {
5397                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5398                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5399
5400                 if (intel_dp->is_mst) {
5401                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5402                                       intel_dp->is_mst,
5403                                       intel_dp->mst_mgr.mst_state);
5404                         intel_dp->is_mst = false;
5405                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5406                                                         intel_dp->is_mst);
5407                 }
5408
5409                 goto out;
5410         }
5411
5412         if (intel_dp->reset_link_params) {
5413                 /* Initial max link lane count */
5414                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5415
5416                 /* Initial max link rate */
5417                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5418
5419                 intel_dp->reset_link_params = false;
5420         }
5421
5422         intel_dp_print_rates(intel_dp);
5423
5424         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5425         if (INTEL_GEN(dev_priv) >= 11)
5426                 intel_dp_get_dsc_sink_cap(intel_dp);
5427
5428         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5429                          drm_dp_is_branch(intel_dp->dpcd));
5430
5431         intel_dp_configure_mst(intel_dp);
5432
5433         if (intel_dp->is_mst) {
5434                 /*
5435                  * If we are in MST mode then this connector
5436                  * won't appear connected or have anything
5437                  * with EDID on it
5438                  */
5439                 status = connector_status_disconnected;
5440                 goto out;
5441         }
5442
5443         /*
5444          * Some external monitors do not signal loss of link synchronization
5445          * with an IRQ_HPD, so force a link status check.
5446          */
5447         if (!intel_dp_is_edp(intel_dp)) {
5448                 int ret;
5449
5450                 ret = intel_dp_retrain_link(encoder, ctx);
5451                 if (ret) {
5452                         intel_display_power_put(dev_priv, aux_domain, wakeref);
5453                         return ret;
5454                 }
5455         }
5456
5457         /*
5458          * Clearing NACK and defer counts to get their exact values
5459          * while reading EDID which are required by Compliance tests
5460          * 4.2.2.4 and 4.2.2.5
5461          */
5462         intel_dp->aux.i2c_nack_count = 0;
5463         intel_dp->aux.i2c_defer_count = 0;
5464
5465         intel_dp_set_edid(intel_dp);
5466         if (intel_dp_is_edp(intel_dp) ||
5467             to_intel_connector(connector)->detect_edid)
5468                 status = connector_status_connected;
5469
5470         intel_dp_check_service_irq(intel_dp);
5471
5472 out:
5473         if (status != connector_status_connected && !intel_dp->is_mst)
5474                 intel_dp_unset_edid(intel_dp);
5475
5476         intel_display_power_put(dev_priv, aux_domain, wakeref);
5477         return status;
5478 }
5479
5480 static void
5481 intel_dp_force(struct drm_connector *connector)
5482 {
5483         struct intel_dp *intel_dp = intel_attached_dp(connector);
5484         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5485         struct intel_encoder *intel_encoder = &dig_port->base;
5486         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5487         enum intel_display_power_domain aux_domain =
5488                 intel_aux_power_domain(dig_port);
5489         intel_wakeref_t wakeref;
5490
5491         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5492                       connector->base.id, connector->name);
5493         intel_dp_unset_edid(intel_dp);
5494
5495         if (connector->status != connector_status_connected)
5496                 return;
5497
5498         wakeref = intel_display_power_get(dev_priv, aux_domain);
5499
5500         intel_dp_set_edid(intel_dp);
5501
5502         intel_display_power_put(dev_priv, aux_domain, wakeref);
5503 }
5504
5505 static int intel_dp_get_modes(struct drm_connector *connector)
5506 {
5507         struct intel_connector *intel_connector = to_intel_connector(connector);
5508         struct edid *edid;
5509
5510         edid = intel_connector->detect_edid;
5511         if (edid) {
5512                 int ret = intel_connector_update_modes(connector, edid);
5513                 if (ret)
5514                         return ret;
5515         }
5516
5517         /* if eDP has no EDID, fall back to fixed mode */
5518         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5519             intel_connector->panel.fixed_mode) {
5520                 struct drm_display_mode *mode;
5521
5522                 mode = drm_mode_duplicate(connector->dev,
5523                                           intel_connector->panel.fixed_mode);
5524                 if (mode) {
5525                         drm_mode_probed_add(connector, mode);
5526                         return 1;
5527                 }
5528         }
5529
5530         return 0;
5531 }
5532
5533 static int
5534 intel_dp_connector_register(struct drm_connector *connector)
5535 {
5536         struct intel_dp *intel_dp = intel_attached_dp(connector);
5537         struct drm_device *dev = connector->dev;
5538         int ret;
5539
5540         ret = intel_connector_register(connector);
5541         if (ret)
5542                 return ret;
5543
5544         i915_debugfs_connector_add(connector);
5545
5546         DRM_DEBUG_KMS("registering %s bus for %s\n",
5547                       intel_dp->aux.name, connector->kdev->kobj.name);
5548
5549         intel_dp->aux.dev = connector->kdev;
5550         ret = drm_dp_aux_register(&intel_dp->aux);
5551         if (!ret)
5552                 drm_dp_cec_register_connector(&intel_dp->aux,
5553                                               connector->name, dev->dev);
5554         return ret;
5555 }
5556
5557 static void
5558 intel_dp_connector_unregister(struct drm_connector *connector)
5559 {
5560         struct intel_dp *intel_dp = intel_attached_dp(connector);
5561
5562         drm_dp_cec_unregister_connector(&intel_dp->aux);
5563         drm_dp_aux_unregister(&intel_dp->aux);
5564         intel_connector_unregister(connector);
5565 }
5566
5567 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5568 {
5569         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5570         struct intel_dp *intel_dp = &intel_dig_port->dp;
5571
5572         intel_dp_mst_encoder_cleanup(intel_dig_port);
5573         if (intel_dp_is_edp(intel_dp)) {
5574                 intel_wakeref_t wakeref;
5575
5576                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5577                 /*
5578                  * vdd might still be enabled do to the delayed vdd off.
5579                  * Make sure vdd is actually turned off here.
5580                  */
5581                 with_pps_lock(intel_dp, wakeref)
5582                         edp_panel_vdd_off_sync(intel_dp);
5583
5584                 if (intel_dp->edp_notifier.notifier_call) {
5585                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5586                         intel_dp->edp_notifier.notifier_call = NULL;
5587                 }
5588         }
5589
5590         intel_dp_aux_fini(intel_dp);
5591 }
5592
5593 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5594 {
5595         intel_dp_encoder_flush_work(encoder);
5596
5597         drm_encoder_cleanup(encoder);
5598         kfree(enc_to_dig_port(encoder));
5599 }
5600
5601 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5602 {
5603         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5604         intel_wakeref_t wakeref;
5605
5606         if (!intel_dp_is_edp(intel_dp))
5607                 return;
5608
5609         /*
5610          * vdd might still be enabled do to the delayed vdd off.
5611          * Make sure vdd is actually turned off here.
5612          */
5613         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5614         with_pps_lock(intel_dp, wakeref)
5615                 edp_panel_vdd_off_sync(intel_dp);
5616 }
5617
5618 static
5619 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5620                                 u8 *an)
5621 {
5622         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5623         static const struct drm_dp_aux_msg msg = {
5624                 .request = DP_AUX_NATIVE_WRITE,
5625                 .address = DP_AUX_HDCP_AKSV,
5626                 .size = DRM_HDCP_KSV_LEN,
5627         };
5628         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5629         ssize_t dpcd_ret;
5630         int ret;
5631
5632         /* Output An first, that's easy */
5633         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5634                                      an, DRM_HDCP_AN_LEN);
5635         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5636                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5637                               dpcd_ret);
5638                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5639         }
5640
5641         /*
5642          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5643          * order to get it on the wire, we need to create the AUX header as if
5644          * we were writing the data, and then tickle the hardware to output the
5645          * data once the header is sent out.
5646          */
5647         intel_dp_aux_header(txbuf, &msg);
5648
5649         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5650                                 rxbuf, sizeof(rxbuf),
5651                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5652         if (ret < 0) {
5653                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5654                 return ret;
5655         } else if (ret == 0) {
5656                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5657                 return -EIO;
5658         }
5659
5660         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5661         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5662                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5663                               reply);
5664                 return -EIO;
5665         }
5666         return 0;
5667 }
5668
5669 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5670                                    u8 *bksv)
5671 {
5672         ssize_t ret;
5673         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5674                                DRM_HDCP_KSV_LEN);
5675         if (ret != DRM_HDCP_KSV_LEN) {
5676                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5677                 return ret >= 0 ? -EIO : ret;
5678         }
5679         return 0;
5680 }
5681
5682 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5683                                       u8 *bstatus)
5684 {
5685         ssize_t ret;
5686         /*
5687          * For some reason the HDMI and DP HDCP specs call this register
5688          * definition by different names. In the HDMI spec, it's called BSTATUS,
5689          * but in DP it's called BINFO.
5690          */
5691         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5692                                bstatus, DRM_HDCP_BSTATUS_LEN);
5693         if (ret != DRM_HDCP_BSTATUS_LEN) {
5694                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5695                 return ret >= 0 ? -EIO : ret;
5696         }
5697         return 0;
5698 }
5699
5700 static
5701 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5702                              u8 *bcaps)
5703 {
5704         ssize_t ret;
5705
5706         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5707                                bcaps, 1);
5708         if (ret != 1) {
5709                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5710                 return ret >= 0 ? -EIO : ret;
5711         }
5712
5713         return 0;
5714 }
5715
5716 static
5717 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5718                                    bool *repeater_present)
5719 {
5720         ssize_t ret;
5721         u8 bcaps;
5722
5723         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5724         if (ret)
5725                 return ret;
5726
5727         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5728         return 0;
5729 }
5730
5731 static
5732 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5733                                 u8 *ri_prime)
5734 {
5735         ssize_t ret;
5736         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5737                                ri_prime, DRM_HDCP_RI_LEN);
5738         if (ret != DRM_HDCP_RI_LEN) {
5739                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5740                 return ret >= 0 ? -EIO : ret;
5741         }
5742         return 0;
5743 }
5744
5745 static
5746 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5747                                  bool *ksv_ready)
5748 {
5749         ssize_t ret;
5750         u8 bstatus;
5751         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5752                                &bstatus, 1);
5753         if (ret != 1) {
5754                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5755                 return ret >= 0 ? -EIO : ret;
5756         }
5757         *ksv_ready = bstatus & DP_BSTATUS_READY;
5758         return 0;
5759 }
5760
5761 static
5762 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5763                                 int num_downstream, u8 *ksv_fifo)
5764 {
5765         ssize_t ret;
5766         int i;
5767
5768         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5769         for (i = 0; i < num_downstream; i += 3) {
5770                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5771                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5772                                        DP_AUX_HDCP_KSV_FIFO,
5773                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5774                                        len);
5775                 if (ret != len) {
5776                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5777                                       i, ret);
5778                         return ret >= 0 ? -EIO : ret;
5779                 }
5780         }
5781         return 0;
5782 }
5783
5784 static
5785 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5786                                     int i, u32 *part)
5787 {
5788         ssize_t ret;
5789
5790         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5791                 return -EINVAL;
5792
5793         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5794                                DP_AUX_HDCP_V_PRIME(i), part,
5795                                DRM_HDCP_V_PRIME_PART_LEN);
5796         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5797                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5798                 return ret >= 0 ? -EIO : ret;
5799         }
5800         return 0;
5801 }
5802
5803 static
5804 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5805                                     bool enable)
5806 {
5807         /* Not used for single stream DisplayPort setups */
5808         return 0;
5809 }
5810
5811 static
5812 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5813 {
5814         ssize_t ret;
5815         u8 bstatus;
5816
5817         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5818                                &bstatus, 1);
5819         if (ret != 1) {
5820                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5821                 return false;
5822         }
5823
5824         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5825 }
5826
5827 static
5828 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5829                           bool *hdcp_capable)
5830 {
5831         ssize_t ret;
5832         u8 bcaps;
5833
5834         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5835         if (ret)
5836                 return ret;
5837
5838         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5839         return 0;
5840 }
5841
5842 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5843         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5844         .read_bksv = intel_dp_hdcp_read_bksv,
5845         .read_bstatus = intel_dp_hdcp_read_bstatus,
5846         .repeater_present = intel_dp_hdcp_repeater_present,
5847         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5848         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5849         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5850         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5851         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5852         .check_link = intel_dp_hdcp_check_link,
5853         .hdcp_capable = intel_dp_hdcp_capable,
5854 };
5855
5856 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5857 {
5858         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5859         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5860
5861         lockdep_assert_held(&dev_priv->pps_mutex);
5862
5863         if (!edp_have_panel_vdd(intel_dp))
5864                 return;
5865
5866         /*
5867          * The VDD bit needs a power domain reference, so if the bit is
5868          * already enabled when we boot or resume, grab this reference and
5869          * schedule a vdd off, so we don't hold on to the reference
5870          * indefinitely.
5871          */
5872         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5873         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5874
5875         edp_panel_vdd_schedule_off(intel_dp);
5876 }
5877
5878 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5879 {
5880         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5881         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5882         enum pipe pipe;
5883
5884         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5885                                   encoder->port, &pipe))
5886                 return pipe;
5887
5888         return INVALID_PIPE;
5889 }
5890
5891 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5892 {
5893         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5894         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5895         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5896         intel_wakeref_t wakeref;
5897
5898         if (!HAS_DDI(dev_priv))
5899                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5900
5901         if (lspcon->active)
5902                 lspcon_resume(lspcon);
5903
5904         intel_dp->reset_link_params = true;
5905
5906         with_pps_lock(intel_dp, wakeref) {
5907                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5908                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5909
5910                 if (intel_dp_is_edp(intel_dp)) {
5911                         /*
5912                          * Reinit the power sequencer, in case BIOS did
5913                          * something nasty with it.
5914                          */
5915                         intel_dp_pps_init(intel_dp);
5916                         intel_edp_panel_vdd_sanitize(intel_dp);
5917                 }
5918         }
5919 }
5920
5921 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5922         .force = intel_dp_force,
5923         .fill_modes = drm_helper_probe_single_connector_modes,
5924         .atomic_get_property = intel_digital_connector_atomic_get_property,
5925         .atomic_set_property = intel_digital_connector_atomic_set_property,
5926         .late_register = intel_dp_connector_register,
5927         .early_unregister = intel_dp_connector_unregister,
5928         .destroy = intel_connector_destroy,
5929         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5930         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5931 };
5932
5933 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5934         .detect_ctx = intel_dp_detect,
5935         .get_modes = intel_dp_get_modes,
5936         .mode_valid = intel_dp_mode_valid,
5937         .atomic_check = intel_digital_connector_atomic_check,
5938 };
5939
5940 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5941         .reset = intel_dp_encoder_reset,
5942         .destroy = intel_dp_encoder_destroy,
5943 };
5944
5945 enum irqreturn
5946 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5947 {
5948         struct intel_dp *intel_dp = &intel_dig_port->dp;
5949         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5950         enum irqreturn ret = IRQ_NONE;
5951         intel_wakeref_t wakeref;
5952
5953         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5954                 /*
5955                  * vdd off can generate a long pulse on eDP which
5956                  * would require vdd on to handle it, and thus we
5957                  * would end up in an endless cycle of
5958                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5959                  */
5960                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5961                               port_name(intel_dig_port->base.port));
5962                 return IRQ_HANDLED;
5963         }
5964
5965         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5966                       port_name(intel_dig_port->base.port),
5967                       long_hpd ? "long" : "short");
5968
5969         if (long_hpd) {
5970                 intel_dp->reset_link_params = true;
5971                 return IRQ_NONE;
5972         }
5973
5974         wakeref = intel_display_power_get(dev_priv,
5975                                           intel_aux_power_domain(intel_dig_port));
5976
5977         if (intel_dp->is_mst) {
5978                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5979                         /*
5980                          * If we were in MST mode, and device is not
5981                          * there, get out of MST mode
5982                          */
5983                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5984                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5985                         intel_dp->is_mst = false;
5986                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5987                                                         intel_dp->is_mst);
5988                         goto put_power;
5989                 }
5990         }
5991
5992         if (!intel_dp->is_mst) {
5993                 bool handled;
5994
5995                 handled = intel_dp_short_pulse(intel_dp);
5996
5997                 if (!handled)
5998                         goto put_power;
5999         }
6000
6001         ret = IRQ_HANDLED;
6002
6003 put_power:
6004         intel_display_power_put(dev_priv,
6005                                 intel_aux_power_domain(intel_dig_port),
6006                                 wakeref);
6007
6008         return ret;
6009 }
6010
6011 /* check the VBT to see whether the eDP is on another port */
6012 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6013 {
6014         /*
6015          * eDP not supported on g4x. so bail out early just
6016          * for a bit extra safety in case the VBT is bonkers.
6017          */
6018         if (INTEL_GEN(dev_priv) < 5)
6019                 return false;
6020
6021         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6022                 return true;
6023
6024         return intel_bios_is_port_edp(dev_priv, port);
6025 }
6026
6027 static void
6028 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6029 {
6030         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6031         enum port port = dp_to_dig_port(intel_dp)->base.port;
6032
6033         if (!IS_G4X(dev_priv) && port != PORT_A)
6034                 intel_attach_force_audio_property(connector);
6035
6036         intel_attach_broadcast_rgb_property(connector);
6037         if (HAS_GMCH_DISPLAY(dev_priv))
6038                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6039         else if (INTEL_GEN(dev_priv) >= 5)
6040                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6041
6042         if (intel_dp_is_edp(intel_dp)) {
6043                 u32 allowed_scalers;
6044
6045                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6046                 if (!HAS_GMCH_DISPLAY(dev_priv))
6047                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6048
6049                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6050
6051                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6052
6053         }
6054 }
6055
6056 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6057 {
6058         intel_dp->panel_power_off_time = ktime_get_boottime();
6059         intel_dp->last_power_on = jiffies;
6060         intel_dp->last_backlight_off = jiffies;
6061 }
6062
6063 static void
6064 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6065 {
6066         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6067         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
6068         struct pps_registers regs;
6069
6070         intel_pps_get_registers(intel_dp, &regs);
6071
6072         /* Workaround: Need to write PP_CONTROL with the unlock key as
6073          * the very first thing. */
6074         pp_ctl = ironlake_get_pp_control(intel_dp);
6075
6076         pp_on = I915_READ(regs.pp_on);
6077         pp_off = I915_READ(regs.pp_off);
6078         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
6079             !HAS_PCH_ICP(dev_priv)) {
6080                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6081                 pp_div = I915_READ(regs.pp_div);
6082         }
6083
6084         /* Pull timing values out of registers */
6085         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
6086                      PANEL_POWER_UP_DELAY_SHIFT;
6087
6088         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
6089                   PANEL_LIGHT_ON_DELAY_SHIFT;
6090
6091         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
6092                   PANEL_LIGHT_OFF_DELAY_SHIFT;
6093
6094         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
6095                    PANEL_POWER_DOWN_DELAY_SHIFT;
6096
6097         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6098             HAS_PCH_ICP(dev_priv)) {
6099                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
6100                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
6101         } else {
6102                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
6103                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
6104         }
6105 }
6106
6107 static void
6108 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6109 {
6110         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6111                       state_name,
6112                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6113 }
6114
6115 static void
6116 intel_pps_verify_state(struct intel_dp *intel_dp)
6117 {
6118         struct edp_power_seq hw;
6119         struct edp_power_seq *sw = &intel_dp->pps_delays;
6120
6121         intel_pps_readout_hw_state(intel_dp, &hw);
6122
6123         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6124             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6125                 DRM_ERROR("PPS state mismatch\n");
6126                 intel_pps_dump_state("sw", sw);
6127                 intel_pps_dump_state("hw", &hw);
6128         }
6129 }
6130
6131 static void
6132 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6133 {
6134         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6135         struct edp_power_seq cur, vbt, spec,
6136                 *final = &intel_dp->pps_delays;
6137
6138         lockdep_assert_held(&dev_priv->pps_mutex);
6139
6140         /* already initialized? */
6141         if (final->t11_t12 != 0)
6142                 return;
6143
6144         intel_pps_readout_hw_state(intel_dp, &cur);
6145
6146         intel_pps_dump_state("cur", &cur);
6147
6148         vbt = dev_priv->vbt.edp.pps;
6149         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6150          * of 500ms appears to be too short. Ocassionally the panel
6151          * just fails to power back on. Increasing the delay to 800ms
6152          * seems sufficient to avoid this problem.
6153          */
6154         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6155                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6156                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6157                               vbt.t11_t12);
6158         }
6159         /* T11_T12 delay is special and actually in units of 100ms, but zero
6160          * based in the hw (so we need to add 100 ms). But the sw vbt
6161          * table multiplies it with 1000 to make it in units of 100usec,
6162          * too. */
6163         vbt.t11_t12 += 100 * 10;
6164
6165         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6166          * our hw here, which are all in 100usec. */
6167         spec.t1_t3 = 210 * 10;
6168         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6169         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6170         spec.t10 = 500 * 10;
6171         /* This one is special and actually in units of 100ms, but zero
6172          * based in the hw (so we need to add 100 ms). But the sw vbt
6173          * table multiplies it with 1000 to make it in units of 100usec,
6174          * too. */
6175         spec.t11_t12 = (510 + 100) * 10;
6176
6177         intel_pps_dump_state("vbt", &vbt);
6178
6179         /* Use the max of the register settings and vbt. If both are
6180          * unset, fall back to the spec limits. */
6181 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6182                                        spec.field : \
6183                                        max(cur.field, vbt.field))
6184         assign_final(t1_t3);
6185         assign_final(t8);
6186         assign_final(t9);
6187         assign_final(t10);
6188         assign_final(t11_t12);
6189 #undef assign_final
6190
6191 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6192         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6193         intel_dp->backlight_on_delay = get_delay(t8);
6194         intel_dp->backlight_off_delay = get_delay(t9);
6195         intel_dp->panel_power_down_delay = get_delay(t10);
6196         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6197 #undef get_delay
6198
6199         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6200                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6201                       intel_dp->panel_power_cycle_delay);
6202
6203         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6204                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6205
6206         /*
6207          * We override the HW backlight delays to 1 because we do manual waits
6208          * on them. For T8, even BSpec recommends doing it. For T9, if we
6209          * don't do this, we'll end up waiting for the backlight off delay
6210          * twice: once when we do the manual sleep, and once when we disable
6211          * the panel and wait for the PP_STATUS bit to become zero.
6212          */
6213         final->t8 = 1;
6214         final->t9 = 1;
6215
6216         /*
6217          * HW has only a 100msec granularity for t11_t12 so round it up
6218          * accordingly.
6219          */
6220         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6221 }
6222
6223 static void
6224 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6225                                               bool force_disable_vdd)
6226 {
6227         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6228         u32 pp_on, pp_off, pp_div, port_sel = 0;
6229         int div = dev_priv->rawclk_freq / 1000;
6230         struct pps_registers regs;
6231         enum port port = dp_to_dig_port(intel_dp)->base.port;
6232         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6233
6234         lockdep_assert_held(&dev_priv->pps_mutex);
6235
6236         intel_pps_get_registers(intel_dp, &regs);
6237
6238         /*
6239          * On some VLV machines the BIOS can leave the VDD
6240          * enabled even on power sequencers which aren't
6241          * hooked up to any port. This would mess up the
6242          * power domain tracking the first time we pick
6243          * one of these power sequencers for use since
6244          * edp_panel_vdd_on() would notice that the VDD was
6245          * already on and therefore wouldn't grab the power
6246          * domain reference. Disable VDD first to avoid this.
6247          * This also avoids spuriously turning the VDD on as
6248          * soon as the new power sequencer gets initialized.
6249          */
6250         if (force_disable_vdd) {
6251                 u32 pp = ironlake_get_pp_control(intel_dp);
6252
6253                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6254
6255                 if (pp & EDP_FORCE_VDD)
6256                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6257
6258                 pp &= ~EDP_FORCE_VDD;
6259
6260                 I915_WRITE(regs.pp_ctrl, pp);
6261         }
6262
6263         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
6264                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
6265         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
6266                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
6267         /* Compute the divisor for the pp clock, simply match the Bspec
6268          * formula. */
6269         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6270             HAS_PCH_ICP(dev_priv)) {
6271                 pp_div = I915_READ(regs.pp_ctrl);
6272                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
6273                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6274                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
6275         } else {
6276                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
6277                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6278                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
6279         }
6280
6281         /* Haswell doesn't have any port selection bits for the panel
6282          * power sequencer any more. */
6283         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6284                 port_sel = PANEL_PORT_SELECT_VLV(port);
6285         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6286                 switch (port) {
6287                 case PORT_A:
6288                         port_sel = PANEL_PORT_SELECT_DPA;
6289                         break;
6290                 case PORT_C:
6291                         port_sel = PANEL_PORT_SELECT_DPC;
6292                         break;
6293                 case PORT_D:
6294                         port_sel = PANEL_PORT_SELECT_DPD;
6295                         break;
6296                 default:
6297                         MISSING_CASE(port);
6298                         break;
6299                 }
6300         }
6301
6302         pp_on |= port_sel;
6303
6304         I915_WRITE(regs.pp_on, pp_on);
6305         I915_WRITE(regs.pp_off, pp_off);
6306         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6307             HAS_PCH_ICP(dev_priv))
6308                 I915_WRITE(regs.pp_ctrl, pp_div);
6309         else
6310                 I915_WRITE(regs.pp_div, pp_div);
6311
6312         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6313                       I915_READ(regs.pp_on),
6314                       I915_READ(regs.pp_off),
6315                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
6316                        HAS_PCH_ICP(dev_priv)) ?
6317                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6318                       I915_READ(regs.pp_div));
6319 }
6320
6321 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6322 {
6323         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6324
6325         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6326                 vlv_initial_power_sequencer_setup(intel_dp);
6327         } else {
6328                 intel_dp_init_panel_power_sequencer(intel_dp);
6329                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6330         }
6331 }
6332
6333 /**
6334  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6335  * @dev_priv: i915 device
6336  * @crtc_state: a pointer to the active intel_crtc_state
6337  * @refresh_rate: RR to be programmed
6338  *
6339  * This function gets called when refresh rate (RR) has to be changed from
6340  * one frequency to another. Switches can be between high and low RR
6341  * supported by the panel or to any other RR based on media playback (in
6342  * this case, RR value needs to be passed from user space).
6343  *
6344  * The caller of this function needs to take a lock on dev_priv->drrs.
6345  */
6346 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6347                                     const struct intel_crtc_state *crtc_state,
6348                                     int refresh_rate)
6349 {
6350         struct intel_encoder *encoder;
6351         struct intel_digital_port *dig_port = NULL;
6352         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6354         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6355
6356         if (refresh_rate <= 0) {
6357                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6358                 return;
6359         }
6360
6361         if (intel_dp == NULL) {
6362                 DRM_DEBUG_KMS("DRRS not supported.\n");
6363                 return;
6364         }
6365
6366         dig_port = dp_to_dig_port(intel_dp);
6367         encoder = &dig_port->base;
6368
6369         if (!intel_crtc) {
6370                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6371                 return;
6372         }
6373
6374         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6375                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6376                 return;
6377         }
6378
6379         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6380                         refresh_rate)
6381                 index = DRRS_LOW_RR;
6382
6383         if (index == dev_priv->drrs.refresh_rate_type) {
6384                 DRM_DEBUG_KMS(
6385                         "DRRS requested for previously set RR...ignoring\n");
6386                 return;
6387         }
6388
6389         if (!crtc_state->base.active) {
6390                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6391                 return;
6392         }
6393
6394         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6395                 switch (index) {
6396                 case DRRS_HIGH_RR:
6397                         intel_dp_set_m_n(crtc_state, M1_N1);
6398                         break;
6399                 case DRRS_LOW_RR:
6400                         intel_dp_set_m_n(crtc_state, M2_N2);
6401                         break;
6402                 case DRRS_MAX_RR:
6403                 default:
6404                         DRM_ERROR("Unsupported refreshrate type\n");
6405                 }
6406         } else if (INTEL_GEN(dev_priv) > 6) {
6407                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6408                 u32 val;
6409
6410                 val = I915_READ(reg);
6411                 if (index > DRRS_HIGH_RR) {
6412                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6413                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6414                         else
6415                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6416                 } else {
6417                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6418                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6419                         else
6420                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6421                 }
6422                 I915_WRITE(reg, val);
6423         }
6424
6425         dev_priv->drrs.refresh_rate_type = index;
6426
6427         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6428 }
6429
6430 /**
6431  * intel_edp_drrs_enable - init drrs struct if supported
6432  * @intel_dp: DP struct
6433  * @crtc_state: A pointer to the active crtc state.
6434  *
6435  * Initializes frontbuffer_bits and drrs.dp
6436  */
6437 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6438                            const struct intel_crtc_state *crtc_state)
6439 {
6440         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6441
6442         if (!crtc_state->has_drrs) {
6443                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6444                 return;
6445         }
6446
6447         if (dev_priv->psr.enabled) {
6448                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6449                 return;
6450         }
6451
6452         mutex_lock(&dev_priv->drrs.mutex);
6453         if (dev_priv->drrs.dp) {
6454                 DRM_DEBUG_KMS("DRRS already enabled\n");
6455                 goto unlock;
6456         }
6457
6458         dev_priv->drrs.busy_frontbuffer_bits = 0;
6459
6460         dev_priv->drrs.dp = intel_dp;
6461
6462 unlock:
6463         mutex_unlock(&dev_priv->drrs.mutex);
6464 }
6465
6466 /**
6467  * intel_edp_drrs_disable - Disable DRRS
6468  * @intel_dp: DP struct
6469  * @old_crtc_state: Pointer to old crtc_state.
6470  *
6471  */
6472 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6473                             const struct intel_crtc_state *old_crtc_state)
6474 {
6475         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6476
6477         if (!old_crtc_state->has_drrs)
6478                 return;
6479
6480         mutex_lock(&dev_priv->drrs.mutex);
6481         if (!dev_priv->drrs.dp) {
6482                 mutex_unlock(&dev_priv->drrs.mutex);
6483                 return;
6484         }
6485
6486         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6487                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6488                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6489
6490         dev_priv->drrs.dp = NULL;
6491         mutex_unlock(&dev_priv->drrs.mutex);
6492
6493         cancel_delayed_work_sync(&dev_priv->drrs.work);
6494 }
6495
6496 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6497 {
6498         struct drm_i915_private *dev_priv =
6499                 container_of(work, typeof(*dev_priv), drrs.work.work);
6500         struct intel_dp *intel_dp;
6501
6502         mutex_lock(&dev_priv->drrs.mutex);
6503
6504         intel_dp = dev_priv->drrs.dp;
6505
6506         if (!intel_dp)
6507                 goto unlock;
6508
6509         /*
6510          * The delayed work can race with an invalidate hence we need to
6511          * recheck.
6512          */
6513
6514         if (dev_priv->drrs.busy_frontbuffer_bits)
6515                 goto unlock;
6516
6517         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6518                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6519
6520                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6521                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6522         }
6523
6524 unlock:
6525         mutex_unlock(&dev_priv->drrs.mutex);
6526 }
6527
6528 /**
6529  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6530  * @dev_priv: i915 device
6531  * @frontbuffer_bits: frontbuffer plane tracking bits
6532  *
6533  * This function gets called everytime rendering on the given planes start.
6534  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6535  *
6536  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6537  */
6538 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6539                                unsigned int frontbuffer_bits)
6540 {
6541         struct drm_crtc *crtc;
6542         enum pipe pipe;
6543
6544         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6545                 return;
6546
6547         cancel_delayed_work(&dev_priv->drrs.work);
6548
6549         mutex_lock(&dev_priv->drrs.mutex);
6550         if (!dev_priv->drrs.dp) {
6551                 mutex_unlock(&dev_priv->drrs.mutex);
6552                 return;
6553         }
6554
6555         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6556         pipe = to_intel_crtc(crtc)->pipe;
6557
6558         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6559         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6560
6561         /* invalidate means busy screen hence upclock */
6562         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6563                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6564                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6565
6566         mutex_unlock(&dev_priv->drrs.mutex);
6567 }
6568
6569 /**
6570  * intel_edp_drrs_flush - Restart Idleness DRRS
6571  * @dev_priv: i915 device
6572  * @frontbuffer_bits: frontbuffer plane tracking bits
6573  *
6574  * This function gets called every time rendering on the given planes has
6575  * completed or flip on a crtc is completed. So DRRS should be upclocked
6576  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6577  * if no other planes are dirty.
6578  *
6579  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6580  */
6581 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6582                           unsigned int frontbuffer_bits)
6583 {
6584         struct drm_crtc *crtc;
6585         enum pipe pipe;
6586
6587         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6588                 return;
6589
6590         cancel_delayed_work(&dev_priv->drrs.work);
6591
6592         mutex_lock(&dev_priv->drrs.mutex);
6593         if (!dev_priv->drrs.dp) {
6594                 mutex_unlock(&dev_priv->drrs.mutex);
6595                 return;
6596         }
6597
6598         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6599         pipe = to_intel_crtc(crtc)->pipe;
6600
6601         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6602         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6603
6604         /* flush means busy screen hence upclock */
6605         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6606                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6607                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6608
6609         /*
6610          * flush also means no more activity hence schedule downclock, if all
6611          * other fbs are quiescent too
6612          */
6613         if (!dev_priv->drrs.busy_frontbuffer_bits)
6614                 schedule_delayed_work(&dev_priv->drrs.work,
6615                                 msecs_to_jiffies(1000));
6616         mutex_unlock(&dev_priv->drrs.mutex);
6617 }
6618
6619 /**
6620  * DOC: Display Refresh Rate Switching (DRRS)
6621  *
6622  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6623  * which enables swtching between low and high refresh rates,
6624  * dynamically, based on the usage scenario. This feature is applicable
6625  * for internal panels.
6626  *
6627  * Indication that the panel supports DRRS is given by the panel EDID, which
6628  * would list multiple refresh rates for one resolution.
6629  *
6630  * DRRS is of 2 types - static and seamless.
6631  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6632  * (may appear as a blink on screen) and is used in dock-undock scenario.
6633  * Seamless DRRS involves changing RR without any visual effect to the user
6634  * and can be used during normal system usage. This is done by programming
6635  * certain registers.
6636  *
6637  * Support for static/seamless DRRS may be indicated in the VBT based on
6638  * inputs from the panel spec.
6639  *
6640  * DRRS saves power by switching to low RR based on usage scenarios.
6641  *
6642  * The implementation is based on frontbuffer tracking implementation.  When
6643  * there is a disturbance on the screen triggered by user activity or a periodic
6644  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6645  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6646  * made.
6647  *
6648  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6649  * and intel_edp_drrs_flush() are called.
6650  *
6651  * DRRS can be further extended to support other internal panels and also
6652  * the scenario of video playback wherein RR is set based on the rate
6653  * requested by userspace.
6654  */
6655
6656 /**
6657  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6658  * @connector: eDP connector
6659  * @fixed_mode: preferred mode of panel
6660  *
6661  * This function is  called only once at driver load to initialize basic
6662  * DRRS stuff.
6663  *
6664  * Returns:
6665  * Downclock mode if panel supports it, else return NULL.
6666  * DRRS support is determined by the presence of downclock mode (apart
6667  * from VBT setting).
6668  */
6669 static struct drm_display_mode *
6670 intel_dp_drrs_init(struct intel_connector *connector,
6671                    struct drm_display_mode *fixed_mode)
6672 {
6673         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6674         struct drm_display_mode *downclock_mode = NULL;
6675
6676         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6677         mutex_init(&dev_priv->drrs.mutex);
6678
6679         if (INTEL_GEN(dev_priv) <= 6) {
6680                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6681                 return NULL;
6682         }
6683
6684         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6685                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6686                 return NULL;
6687         }
6688
6689         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6690                                                     &connector->base);
6691
6692         if (!downclock_mode) {
6693                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6694                 return NULL;
6695         }
6696
6697         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6698
6699         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6700         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6701         return downclock_mode;
6702 }
6703
6704 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6705                                      struct intel_connector *intel_connector)
6706 {
6707         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6708         struct drm_device *dev = &dev_priv->drm;
6709         struct drm_connector *connector = &intel_connector->base;
6710         struct drm_display_mode *fixed_mode = NULL;
6711         struct drm_display_mode *downclock_mode = NULL;
6712         bool has_dpcd;
6713         struct drm_display_mode *scan;
6714         enum pipe pipe = INVALID_PIPE;
6715         intel_wakeref_t wakeref;
6716         struct edid *edid;
6717
6718         if (!intel_dp_is_edp(intel_dp))
6719                 return true;
6720
6721         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
6722
6723         /*
6724          * On IBX/CPT we may get here with LVDS already registered. Since the
6725          * driver uses the only internal power sequencer available for both
6726          * eDP and LVDS bail out early in this case to prevent interfering
6727          * with an already powered-on LVDS power sequencer.
6728          */
6729         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6730                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6731                 DRM_INFO("LVDS was detected, not registering eDP\n");
6732
6733                 return false;
6734         }
6735
6736         with_pps_lock(intel_dp, wakeref) {
6737                 intel_dp_init_panel_power_timestamps(intel_dp);
6738                 intel_dp_pps_init(intel_dp);
6739                 intel_edp_panel_vdd_sanitize(intel_dp);
6740         }
6741
6742         /* Cache DPCD and EDID for edp. */
6743         has_dpcd = intel_edp_init_dpcd(intel_dp);
6744
6745         if (!has_dpcd) {
6746                 /* if this fails, presume the device is a ghost */
6747                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6748                 goto out_vdd_off;
6749         }
6750
6751         mutex_lock(&dev->mode_config.mutex);
6752         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6753         if (edid) {
6754                 if (drm_add_edid_modes(connector, edid)) {
6755                         drm_connector_update_edid_property(connector,
6756                                                                 edid);
6757                 } else {
6758                         kfree(edid);
6759                         edid = ERR_PTR(-EINVAL);
6760                 }
6761         } else {
6762                 edid = ERR_PTR(-ENOENT);
6763         }
6764         intel_connector->edid = edid;
6765
6766         /* prefer fixed mode from EDID if available */
6767         list_for_each_entry(scan, &connector->probed_modes, head) {
6768                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6769                         fixed_mode = drm_mode_duplicate(dev, scan);
6770                         downclock_mode = intel_dp_drrs_init(
6771                                                 intel_connector, fixed_mode);
6772                         break;
6773                 }
6774         }
6775
6776         /* fallback to VBT if available for eDP */
6777         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6778                 fixed_mode = drm_mode_duplicate(dev,
6779                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6780                 if (fixed_mode) {
6781                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6782                         connector->display_info.width_mm = fixed_mode->width_mm;
6783                         connector->display_info.height_mm = fixed_mode->height_mm;
6784                 }
6785         }
6786         mutex_unlock(&dev->mode_config.mutex);
6787
6788         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6789                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6790                 register_reboot_notifier(&intel_dp->edp_notifier);
6791
6792                 /*
6793                  * Figure out the current pipe for the initial backlight setup.
6794                  * If the current pipe isn't valid, try the PPS pipe, and if that
6795                  * fails just assume pipe A.
6796                  */
6797                 pipe = vlv_active_pipe(intel_dp);
6798
6799                 if (pipe != PIPE_A && pipe != PIPE_B)
6800                         pipe = intel_dp->pps_pipe;
6801
6802                 if (pipe != PIPE_A && pipe != PIPE_B)
6803                         pipe = PIPE_A;
6804
6805                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6806                               pipe_name(pipe));
6807         }
6808
6809         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6810         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6811         intel_panel_setup_backlight(connector, pipe);
6812
6813         if (fixed_mode)
6814                 drm_connector_init_panel_orientation_property(
6815                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6816
6817         return true;
6818
6819 out_vdd_off:
6820         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6821         /*
6822          * vdd might still be enabled do to the delayed vdd off.
6823          * Make sure vdd is actually turned off here.
6824          */
6825         with_pps_lock(intel_dp, wakeref)
6826                 edp_panel_vdd_off_sync(intel_dp);
6827
6828         return false;
6829 }
6830
6831 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6832 {
6833         struct intel_connector *intel_connector;
6834         struct drm_connector *connector;
6835
6836         intel_connector = container_of(work, typeof(*intel_connector),
6837                                        modeset_retry_work);
6838         connector = &intel_connector->base;
6839         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6840                       connector->name);
6841
6842         /* Grab the locks before changing connector property*/
6843         mutex_lock(&connector->dev->mode_config.mutex);
6844         /* Set connector link status to BAD and send a Uevent to notify
6845          * userspace to do a modeset.
6846          */
6847         drm_connector_set_link_status_property(connector,
6848                                                DRM_MODE_LINK_STATUS_BAD);
6849         mutex_unlock(&connector->dev->mode_config.mutex);
6850         /* Send Hotplug uevent so userspace can reprobe */
6851         drm_kms_helper_hotplug_event(connector->dev);
6852 }
6853
6854 bool
6855 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6856                         struct intel_connector *intel_connector)
6857 {
6858         struct drm_connector *connector = &intel_connector->base;
6859         struct intel_dp *intel_dp = &intel_dig_port->dp;
6860         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6861         struct drm_device *dev = intel_encoder->base.dev;
6862         struct drm_i915_private *dev_priv = to_i915(dev);
6863         enum port port = intel_encoder->port;
6864         int type;
6865
6866         /* Initialize the work for modeset in case of link train failure */
6867         INIT_WORK(&intel_connector->modeset_retry_work,
6868                   intel_dp_modeset_retry_work_fn);
6869
6870         if (WARN(intel_dig_port->max_lanes < 1,
6871                  "Not enough lanes (%d) for DP on port %c\n",
6872                  intel_dig_port->max_lanes, port_name(port)))
6873                 return false;
6874
6875         intel_dp_set_source_rates(intel_dp);
6876
6877         intel_dp->reset_link_params = true;
6878         intel_dp->pps_pipe = INVALID_PIPE;
6879         intel_dp->active_pipe = INVALID_PIPE;
6880
6881         /* intel_dp vfuncs */
6882         if (HAS_DDI(dev_priv))
6883                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6884
6885         /* Preserve the current hw state. */
6886         intel_dp->DP = I915_READ(intel_dp->output_reg);
6887         intel_dp->attached_connector = intel_connector;
6888
6889         if (intel_dp_is_port_edp(dev_priv, port))
6890                 type = DRM_MODE_CONNECTOR_eDP;
6891         else
6892                 type = DRM_MODE_CONNECTOR_DisplayPort;
6893
6894         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6895                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6896
6897         /*
6898          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6899          * for DP the encoder type can be set by the caller to
6900          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6901          */
6902         if (type == DRM_MODE_CONNECTOR_eDP)
6903                 intel_encoder->type = INTEL_OUTPUT_EDP;
6904
6905         /* eDP only on port B and/or C on vlv/chv */
6906         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6907                     intel_dp_is_edp(intel_dp) &&
6908                     port != PORT_B && port != PORT_C))
6909                 return false;
6910
6911         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6912                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6913                         port_name(port));
6914
6915         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6916         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6917
6918         if (!HAS_GMCH_DISPLAY(dev_priv))
6919                 connector->interlace_allowed = true;
6920         connector->doublescan_allowed = 0;
6921
6922         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6923
6924         intel_dp_aux_init(intel_dp);
6925
6926         intel_connector_attach_encoder(intel_connector, intel_encoder);
6927
6928         if (HAS_DDI(dev_priv))
6929                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6930         else
6931                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6932
6933         /* init MST on ports that can support it */
6934         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6935             (port == PORT_B || port == PORT_C ||
6936              port == PORT_D || port == PORT_F))
6937                 intel_dp_mst_encoder_init(intel_dig_port,
6938                                           intel_connector->base.base.id);
6939
6940         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6941                 intel_dp_aux_fini(intel_dp);
6942                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6943                 goto fail;
6944         }
6945
6946         intel_dp_add_properties(intel_dp, connector);
6947
6948         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6949                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6950                 if (ret)
6951                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6952         }
6953
6954         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6955          * 0xd.  Failure to do so will result in spurious interrupts being
6956          * generated on the port when a cable is not attached.
6957          */
6958         if (IS_G45(dev_priv)) {
6959                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6960                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6961         }
6962
6963         return true;
6964
6965 fail:
6966         drm_connector_cleanup(connector);
6967
6968         return false;
6969 }
6970
6971 bool intel_dp_init(struct drm_i915_private *dev_priv,
6972                    i915_reg_t output_reg,
6973                    enum port port)
6974 {
6975         struct intel_digital_port *intel_dig_port;
6976         struct intel_encoder *intel_encoder;
6977         struct drm_encoder *encoder;
6978         struct intel_connector *intel_connector;
6979
6980         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6981         if (!intel_dig_port)
6982                 return false;
6983
6984         intel_connector = intel_connector_alloc();
6985         if (!intel_connector)
6986                 goto err_connector_alloc;
6987
6988         intel_encoder = &intel_dig_port->base;
6989         encoder = &intel_encoder->base;
6990
6991         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6992                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6993                              "DP %c", port_name(port)))
6994                 goto err_encoder_init;
6995
6996         intel_encoder->hotplug = intel_dp_hotplug;
6997         intel_encoder->compute_config = intel_dp_compute_config;
6998         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6999         intel_encoder->get_config = intel_dp_get_config;
7000         intel_encoder->suspend = intel_dp_encoder_suspend;
7001         if (IS_CHERRYVIEW(dev_priv)) {
7002                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7003                 intel_encoder->pre_enable = chv_pre_enable_dp;
7004                 intel_encoder->enable = vlv_enable_dp;
7005                 intel_encoder->disable = vlv_disable_dp;
7006                 intel_encoder->post_disable = chv_post_disable_dp;
7007                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7008         } else if (IS_VALLEYVIEW(dev_priv)) {
7009                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7010                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7011                 intel_encoder->enable = vlv_enable_dp;
7012                 intel_encoder->disable = vlv_disable_dp;
7013                 intel_encoder->post_disable = vlv_post_disable_dp;
7014         } else {
7015                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7016                 intel_encoder->enable = g4x_enable_dp;
7017                 intel_encoder->disable = g4x_disable_dp;
7018                 intel_encoder->post_disable = g4x_post_disable_dp;
7019         }
7020
7021         intel_dig_port->dp.output_reg = output_reg;
7022         intel_dig_port->max_lanes = 4;
7023
7024         intel_encoder->type = INTEL_OUTPUT_DP;
7025         intel_encoder->power_domain = intel_port_to_power_domain(port);
7026         if (IS_CHERRYVIEW(dev_priv)) {
7027                 if (port == PORT_D)
7028                         intel_encoder->crtc_mask = 1 << 2;
7029                 else
7030                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7031         } else {
7032                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7033         }
7034         intel_encoder->cloneable = 0;
7035         intel_encoder->port = port;
7036
7037         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7038
7039         if (port != PORT_A)
7040                 intel_infoframe_init(intel_dig_port);
7041
7042         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7043         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7044                 goto err_init_connector;
7045
7046         return true;
7047
7048 err_init_connector:
7049         drm_encoder_cleanup(encoder);
7050 err_encoder_init:
7051         kfree(intel_connector);
7052 err_connector_alloc:
7053         kfree(intel_dig_port);
7054         return false;
7055 }
7056
7057 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7058 {
7059         struct intel_encoder *encoder;
7060
7061         for_each_intel_encoder(&dev_priv->drm, encoder) {
7062                 struct intel_dp *intel_dp;
7063
7064                 if (encoder->type != INTEL_OUTPUT_DDI)
7065                         continue;
7066
7067                 intel_dp = enc_to_intel_dp(&encoder->base);
7068
7069                 if (!intel_dp->can_mst)
7070                         continue;
7071
7072                 if (intel_dp->is_mst)
7073                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7074         }
7075 }
7076
7077 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7078 {
7079         struct intel_encoder *encoder;
7080
7081         for_each_intel_encoder(&dev_priv->drm, encoder) {
7082                 struct intel_dp *intel_dp;
7083                 int ret;
7084
7085                 if (encoder->type != INTEL_OUTPUT_DDI)
7086                         continue;
7087
7088                 intel_dp = enc_to_intel_dp(&encoder->base);
7089
7090                 if (!intel_dp->can_mst)
7091                         continue;
7092
7093                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7094                 if (ret)
7095                         intel_dp_check_mst_status(intel_dp);
7096         }
7097 }