2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
28 #include <drm/drm_util.h>
29 #include <drm/i915_drm.h>
48 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
49 * rest have consecutive values and match the enum values of transcoders
50 * with a 1:1 transcoder -> pipe mapping.
60 I915_MAX_PIPES = _PIPE_EDP
63 #define pipe_name(p) ((p) + 'A')
67 * The following transcoders have a 1:1 transcoder -> pipe mapping,
68 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
69 * rest have consecutive values and match the enum values of the pipes
72 TRANSCODER_A = PIPE_A,
73 TRANSCODER_B = PIPE_B,
74 TRANSCODER_C = PIPE_C,
77 * The following transcoders can map to any pipe, their enum value
78 * doesn't need to stay fixed.
83 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
84 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
89 static inline const char *transcoder_name(enum transcoder transcoder)
100 case TRANSCODER_DSI_A:
102 case TRANSCODER_DSI_C:
109 static inline bool transcoder_is_dsi(enum transcoder transcoder)
111 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
115 * Global legacy plane identifier. Valid only for primary/sprite
116 * planes on pre-g4x, and only for primary planes on g4x-bdw.
124 #define plane_name(p) ((p) + 'A')
125 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
128 * Per-pipe plane identifier.
129 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
130 * number of planes per CRTC. Not all platforms really have this many planes,
131 * which means some arrays of size I915_MAX_PLANES may have unused entries
132 * between the topmost sprite plane and the cursor plane.
134 * This is expected to be passed to various register macros
135 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
150 #define for_each_plane_id_on_crtc(__crtc, __p) \
151 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
152 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
155 * Ports identifier referenced from other drivers.
156 * Expected to remain stable over time
158 static inline const char *port_identifier(enum port port)
207 #define I915_NUM_PHYS_VLV 2
218 #define aux_ch_name(a) ((a) + 'A')
220 enum intel_display_power_domain {
224 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
225 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
226 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
227 POWER_DOMAIN_TRANSCODER_A,
228 POWER_DOMAIN_TRANSCODER_B,
229 POWER_DOMAIN_TRANSCODER_C,
230 POWER_DOMAIN_TRANSCODER_EDP,
231 POWER_DOMAIN_TRANSCODER_EDP_VDSC,
232 POWER_DOMAIN_TRANSCODER_DSI_A,
233 POWER_DOMAIN_TRANSCODER_DSI_C,
234 POWER_DOMAIN_PORT_DDI_A_LANES,
235 POWER_DOMAIN_PORT_DDI_B_LANES,
236 POWER_DOMAIN_PORT_DDI_C_LANES,
237 POWER_DOMAIN_PORT_DDI_D_LANES,
238 POWER_DOMAIN_PORT_DDI_E_LANES,
239 POWER_DOMAIN_PORT_DDI_F_LANES,
240 POWER_DOMAIN_PORT_DDI_A_IO,
241 POWER_DOMAIN_PORT_DDI_B_IO,
242 POWER_DOMAIN_PORT_DDI_C_IO,
243 POWER_DOMAIN_PORT_DDI_D_IO,
244 POWER_DOMAIN_PORT_DDI_E_IO,
245 POWER_DOMAIN_PORT_DDI_F_IO,
246 POWER_DOMAIN_PORT_DSI,
247 POWER_DOMAIN_PORT_CRT,
248 POWER_DOMAIN_PORT_OTHER,
258 POWER_DOMAIN_AUX_IO_A,
259 POWER_DOMAIN_AUX_TBT1,
260 POWER_DOMAIN_AUX_TBT2,
261 POWER_DOMAIN_AUX_TBT3,
262 POWER_DOMAIN_AUX_TBT4,
264 POWER_DOMAIN_MODESET,
271 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
272 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
273 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
274 #define POWER_DOMAIN_TRANSCODER(tran) \
275 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
276 (tran) + POWER_DOMAIN_TRANSCODER_A)
278 /* Used by dp and fdi links */
279 struct intel_link_m_n {
287 #define for_each_pipe(__dev_priv, __p) \
288 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
290 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
291 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
292 for_each_if((__mask) & BIT(__p))
294 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
295 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
296 for_each_if ((__mask) & (1 << (__t)))
298 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
300 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
303 #define for_each_sprite(__dev_priv, __p, __s) \
305 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
308 #define for_each_port_masked(__port, __ports_mask) \
309 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
310 for_each_if((__ports_mask) & BIT(__port))
312 #define for_each_crtc(dev, crtc) \
313 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
315 #define for_each_intel_plane(dev, intel_plane) \
316 list_for_each_entry(intel_plane, \
317 &(dev)->mode_config.plane_list, \
320 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
321 list_for_each_entry(intel_plane, \
322 &(dev)->mode_config.plane_list, \
324 for_each_if((plane_mask) & \
325 drm_plane_mask(&intel_plane->base)))
327 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
328 list_for_each_entry(intel_plane, \
329 &(dev)->mode_config.plane_list, \
331 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
333 #define for_each_intel_crtc(dev, intel_crtc) \
334 list_for_each_entry(intel_crtc, \
335 &(dev)->mode_config.crtc_list, \
338 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
339 list_for_each_entry(intel_crtc, \
340 &(dev)->mode_config.crtc_list, \
342 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
344 #define for_each_intel_encoder(dev, intel_encoder) \
345 list_for_each_entry(intel_encoder, \
346 &(dev)->mode_config.encoder_list, \
349 #define for_each_intel_dp(dev, intel_encoder) \
350 for_each_intel_encoder(dev, intel_encoder) \
351 for_each_if(intel_encoder_is_dp(intel_encoder))
353 #define for_each_intel_connector_iter(intel_connector, iter) \
354 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
356 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
357 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
358 for_each_if((intel_encoder)->base.crtc == (__crtc))
360 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
361 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
362 for_each_if((intel_connector)->base.encoder == (__encoder))
364 #define for_each_power_domain(domain, mask) \
365 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
366 for_each_if(BIT_ULL(domain) & (mask))
368 #define for_each_power_well(__dev_priv, __power_well) \
369 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
370 (__power_well) - (__dev_priv)->power_domains.power_wells < \
371 (__dev_priv)->power_domains.power_well_count; \
374 #define for_each_power_well_reverse(__dev_priv, __power_well) \
375 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
376 (__dev_priv)->power_domains.power_well_count - 1; \
377 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
380 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
381 for_each_power_well(__dev_priv, __power_well) \
382 for_each_if((__power_well)->desc->domains & (__domain_mask))
384 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
385 for_each_power_well_reverse(__dev_priv, __power_well) \
386 for_each_if((__power_well)->desc->domains & (__domain_mask))
388 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
390 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
391 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
392 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
396 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
398 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
399 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
400 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
404 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
406 (__i) < (__state)->base.dev->mode_config.num_crtc && \
407 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
408 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
412 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
414 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
415 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
416 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
417 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
421 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
423 (__i) < (__state)->base.dev->mode_config.num_crtc && \
424 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
425 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
426 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
430 void intel_link_compute_m_n(u16 bpp, int nlanes,
431 int pixel_clock, int link_clock,
432 struct intel_link_m_n *m_n,
434 bool is_ccs_modifier(u64 modifier);