drivers/gpu/drm/i915/intel_display.h

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29 #include <drm/i915_drm.h>
  30
  31 enum i915_gpio {
  32         GPIOA,
  33         GPIOB,
  34         GPIOC,
  35         GPIOD,
  36         GPIOE,
  37         GPIOF,
  38         GPIOG,
  39         GPIOH,
  40         __GPIOI_UNUSED,
  41         GPIOJ,
  42         GPIOK,
  43         GPIOL,
  44         GPIOM,
  45 };
  46
  47 /*
  48  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  49  * rest have consecutive values and match the enum values of transcoders
  50  * with a 1:1 transcoder -> pipe mapping.
  51  */
  52 enum pipe {
  53         INVALID_PIPE = -1,
  54
  55         PIPE_A = 0,
  56         PIPE_B,
  57         PIPE_C,
  58         _PIPE_EDP,
  59
  60         I915_MAX_PIPES = _PIPE_EDP
  61 };
  62
  63 #define pipe_name(p) ((p) + 'A')
  64
  65 enum transcoder {
  66         /*
  67          * The following transcoders have a 1:1 transcoder -> pipe mapping,
  68          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
  69          * rest have consecutive values and match the enum values of the pipes
  70          * they map to.
  71          */
  72         TRANSCODER_A = PIPE_A,
  73         TRANSCODER_B = PIPE_B,
  74         TRANSCODER_C = PIPE_C,
  75
  76         /*
  77          * The following transcoders can map to any pipe, their enum value
  78          * doesn't need to stay fixed.
  79          */
  80         TRANSCODER_EDP,
  81         TRANSCODER_DSI_0,
  82         TRANSCODER_DSI_1,
  83         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
  84         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
  85
  86         I915_MAX_TRANSCODERS
  87 };
  88
  89 static inline const char *transcoder_name(enum transcoder transcoder)
  90 {
  91         switch (transcoder) {
  92         case TRANSCODER_A:
  93                 return "A";
  94         case TRANSCODER_B:
  95                 return "B";
  96         case TRANSCODER_C:
  97                 return "C";
  98         case TRANSCODER_EDP:
  99                 return "EDP";
 100         case TRANSCODER_DSI_A:
 101                 return "DSI A";
 102         case TRANSCODER_DSI_C:
 103                 return "DSI C";
 104         default:
 105                 return "<invalid>";
 106         }
 107 }
 108
 109 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 110 {
 111         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 112 }
 113
 114 /*
 115  * Global legacy plane identifier. Valid only for primary/sprite
 116  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 117  */
 118 enum i9xx_plane_id {
 119         PLANE_A,
 120         PLANE_B,
 121         PLANE_C,
 122 };
 123
 124 #define plane_name(p) ((p) + 'A')
 125 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 126
 127 /*
 128  * Per-pipe plane identifier.
 129  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 130  * number of planes per CRTC.  Not all platforms really have this many planes,
 131  * which means some arrays of size I915_MAX_PLANES may have unused entries
 132  * between the topmost sprite plane and the cursor plane.
 133  *
 134  * This is expected to be passed to various register macros
 135  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 136  */
 137 enum plane_id {
 138         PLANE_PRIMARY,
 139         PLANE_SPRITE0,
 140         PLANE_SPRITE1,
 141         PLANE_SPRITE2,
 142         PLANE_SPRITE3,
 143         PLANE_SPRITE4,
 144         PLANE_SPRITE5,
 145         PLANE_CURSOR,
 146
 147         I915_MAX_PLANES,
 148 };
 149
 150 #define for_each_plane_id_on_crtc(__crtc, __p) \
 151         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 152                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 153
 154 /*
 155  * Ports identifier referenced from other drivers.
 156  * Expected to remain stable over time
 157  */
 158 static inline const char *port_identifier(enum port port)
 159 {
 160         switch (port) {
 161         case PORT_A:
 162                 return "Port A";
 163         case PORT_B:
 164                 return "Port B";
 165         case PORT_C:
 166                 return "Port C";
 167         case PORT_D:
 168                 return "Port D";
 169         case PORT_E:
 170                 return "Port E";
 171         case PORT_F:
 172                 return "Port F";
 173         default:
 174                 return "<invalid>";
 175         }
 176 }
 177
 178 enum tc_port {
 179         PORT_TC_NONE = -1,
 180
 181         PORT_TC1 = 0,
 182         PORT_TC2,
 183         PORT_TC3,
 184         PORT_TC4,
 185
 186         I915_MAX_TC_PORTS
 187 };
 188
 189 enum tc_port_type {
 190         TC_PORT_UNKNOWN = 0,
 191         TC_PORT_TYPEC,
 192         TC_PORT_TBT,
 193         TC_PORT_LEGACY,
 194 };
 195
 196 enum dpio_channel {
 197         DPIO_CH0,
 198         DPIO_CH1
 199 };
 200
 201 enum dpio_phy {
 202         DPIO_PHY0,
 203         DPIO_PHY1,
 204         DPIO_PHY2,
 205 };
 206
 207 #define I915_NUM_PHYS_VLV 2
 208
 209 enum aux_ch {
 210         AUX_CH_A,
 211         AUX_CH_B,
 212         AUX_CH_C,
 213         AUX_CH_D,
 214         AUX_CH_E, /* ICL+ */
 215         AUX_CH_F,
 216 };
 217
 218 #define aux_ch_name(a) ((a) + 'A')
 219
 220 enum intel_display_power_domain {
 221         POWER_DOMAIN_PIPE_A,
 222         POWER_DOMAIN_PIPE_B,
 223         POWER_DOMAIN_PIPE_C,
 224         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 225         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 226         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 227         POWER_DOMAIN_TRANSCODER_A,
 228         POWER_DOMAIN_TRANSCODER_B,
 229         POWER_DOMAIN_TRANSCODER_C,
 230         POWER_DOMAIN_TRANSCODER_EDP,
 231         POWER_DOMAIN_TRANSCODER_EDP_VDSC,
 232         POWER_DOMAIN_TRANSCODER_DSI_A,
 233         POWER_DOMAIN_TRANSCODER_DSI_C,
 234         POWER_DOMAIN_PORT_DDI_A_LANES,
 235         POWER_DOMAIN_PORT_DDI_B_LANES,
 236         POWER_DOMAIN_PORT_DDI_C_LANES,
 237         POWER_DOMAIN_PORT_DDI_D_LANES,
 238         POWER_DOMAIN_PORT_DDI_E_LANES,
 239         POWER_DOMAIN_PORT_DDI_F_LANES,
 240         POWER_DOMAIN_PORT_DDI_A_IO,
 241         POWER_DOMAIN_PORT_DDI_B_IO,
 242         POWER_DOMAIN_PORT_DDI_C_IO,
 243         POWER_DOMAIN_PORT_DDI_D_IO,
 244         POWER_DOMAIN_PORT_DDI_E_IO,
 245         POWER_DOMAIN_PORT_DDI_F_IO,
 246         POWER_DOMAIN_PORT_DSI,
 247         POWER_DOMAIN_PORT_CRT,
 248         POWER_DOMAIN_PORT_OTHER,
 249         POWER_DOMAIN_VGA,
 250         POWER_DOMAIN_AUDIO,
 251         POWER_DOMAIN_PLLS,
 252         POWER_DOMAIN_AUX_A,
 253         POWER_DOMAIN_AUX_B,
 254         POWER_DOMAIN_AUX_C,
 255         POWER_DOMAIN_AUX_D,
 256         POWER_DOMAIN_AUX_E,
 257         POWER_DOMAIN_AUX_F,
 258         POWER_DOMAIN_AUX_IO_A,
 259         POWER_DOMAIN_AUX_TBT1,
 260         POWER_DOMAIN_AUX_TBT2,
 261         POWER_DOMAIN_AUX_TBT3,
 262         POWER_DOMAIN_AUX_TBT4,
 263         POWER_DOMAIN_GMBUS,
 264         POWER_DOMAIN_MODESET,
 265         POWER_DOMAIN_GT_IRQ,
 266         POWER_DOMAIN_INIT,
 267
 268         POWER_DOMAIN_NUM,
 269 };
 270
 271 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 272 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 273                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 274 #define POWER_DOMAIN_TRANSCODER(tran) \
 275         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 276          (tran) + POWER_DOMAIN_TRANSCODER_A)
 277
 278 /* Used by dp and fdi links */
 279 struct intel_link_m_n {
 280         u32 tu;
 281         u32 gmch_m;
 282         u32 gmch_n;
 283         u32 link_m;
 284         u32 link_n;
 285 };
 286
 287 #define for_each_pipe(__dev_priv, __p) \
 288         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 289
 290 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 291         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 292                 for_each_if((__mask) & BIT(__p))
 293
 294 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 295         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 296                 for_each_if ((__mask) & (1 << (__t)))
 297
 298 #define for_each_universal_plane(__dev_priv, __pipe, __p)               \
 299         for ((__p) = 0;                                                 \
 300              (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;       \
 301              (__p)++)
 302
 303 #define for_each_sprite(__dev_priv, __p, __s)                           \
 304         for ((__s) = 0;                                                 \
 305              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 306              (__s)++)
 307
 308 #define for_each_port_masked(__port, __ports_mask) \
 309         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
 310                 for_each_if((__ports_mask) & BIT(__port))
 311
 312 #define for_each_crtc(dev, crtc) \
 313         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 314
 315 #define for_each_intel_plane(dev, intel_plane) \
 316         list_for_each_entry(intel_plane,                        \
 317                             &(dev)->mode_config.plane_list,     \
 318                             base.head)
 319
 320 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 321         list_for_each_entry(intel_plane,                                \
 322                             &(dev)->mode_config.plane_list,             \
 323                             base.head)                                  \
 324                 for_each_if((plane_mask) &                              \
 325                             drm_plane_mask(&intel_plane->base)))
 326
 327 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 328         list_for_each_entry(intel_plane,                                \
 329                             &(dev)->mode_config.plane_list,             \
 330                             base.head)                                  \
 331                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 332
 333 #define for_each_intel_crtc(dev, intel_crtc)                            \
 334         list_for_each_entry(intel_crtc,                                 \
 335                             &(dev)->mode_config.crtc_list,              \
 336                             base.head)
 337
 338 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 339         list_for_each_entry(intel_crtc,                                 \
 340                             &(dev)->mode_config.crtc_list,              \
 341                             base.head)                                  \
 342                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 343
 344 #define for_each_intel_encoder(dev, intel_encoder)              \
 345         list_for_each_entry(intel_encoder,                      \
 346                             &(dev)->mode_config.encoder_list,   \
 347                             base.head)
 348
 349 #define for_each_intel_dp(dev, intel_encoder)                   \
 350         for_each_intel_encoder(dev, intel_encoder)              \
 351                 for_each_if(intel_encoder_is_dp(intel_encoder))
 352
 353 #define for_each_intel_connector_iter(intel_connector, iter) \
 354         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 355
 356 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 357         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 358                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 359
 360 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 361         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 362                 for_each_if((intel_connector)->base.encoder == (__encoder))
 363
 364 #define for_each_power_domain(domain, mask)                             \
 365         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 366                 for_each_if(BIT_ULL(domain) & (mask))
 367
 368 #define for_each_power_well(__dev_priv, __power_well)                           \
 369         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 370              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 371                 (__dev_priv)->power_domains.power_well_count;           \
 372              (__power_well)++)
 373
 374 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 375         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 376                               (__dev_priv)->power_domains.power_well_count - 1; \
 377              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 378              (__power_well)--)
 379
 380 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 381         for_each_power_well(__dev_priv, __power_well)                           \
 382                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 383
 384 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 385         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 386                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 387
 388 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 389         for ((__i) = 0; \
 390              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 391                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 392                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 393              (__i)++) \
 394                 for_each_if(plane)
 395
 396 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 397         for ((__i) = 0; \
 398              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 399                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 400                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 401              (__i)++) \
 402                 for_each_if(plane)
 403
 404 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 405         for ((__i) = 0; \
 406              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 407                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 408                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 409              (__i)++) \
 410                 for_each_if(crtc)
 411
 412 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 413         for ((__i) = 0; \
 414              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 415                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 416                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 417                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 418              (__i)++) \
 419                 for_each_if(plane)
 420
 421 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 422         for ((__i) = 0; \
 423              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 424                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 425                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 426                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 427              (__i)++) \
 428                 for_each_if(crtc)
 429
 430 void intel_link_compute_m_n(u16 bpp, int nlanes,
 431                             int pixel_clock, int link_clock,
 432                             struct intel_link_m_n *m_n,
 433                             bool constant_n);
 434 bool is_ccs_modifier(u64 modifier);
 435 #endif