drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats supported by all gen */
  49 #define COMMON_PRIMARY_FORMATS \
  50         DRM_FORMAT_C8, \
  51         DRM_FORMAT_RGB565, \
  52         DRM_FORMAT_XRGB8888, \
  53         DRM_FORMAT_ARGB8888
  54
  55 /* Primary plane formats for gen <= 3 */
  56 static const uint32_t intel_primary_formats_gen2[] = {
  57         COMMON_PRIMARY_FORMATS,
  58         DRM_FORMAT_XRGB1555,
  59         DRM_FORMAT_ARGB1555,
  60 };
  61
  62 /* Primary plane formats for gen >= 4 */
  63 static const uint32_t intel_primary_formats_gen4[] = {
  64         COMMON_PRIMARY_FORMATS, \
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_ABGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_ARGB2101010,
  69         DRM_FORMAT_XBGR2101010,
  70         DRM_FORMAT_ABGR2101010,
  71 };
  72
  73 /* Cursor formats */
  74 static const uint32_t intel_cursor_formats[] = {
  75         DRM_FORMAT_ARGB8888,
  76 };
  77
  78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  79
  80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  81                                 struct intel_crtc_state *pipe_config);
  82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  83                                    struct intel_crtc_state *pipe_config);
  84
  85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  86                           int x, int y, struct drm_framebuffer *old_fb);
  87 static int intel_framebuffer_init(struct drm_device *dev,
  88                                   struct intel_framebuffer *ifb,
  89                                   struct drm_mode_fb_cmd2 *mode_cmd,
  90                                   struct drm_i915_gem_object *obj);
  91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  94                                          struct intel_link_m_n *m_n,
  95                                          struct intel_link_m_n *m2_n2);
  96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  99 static void vlv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_state *pipe_config);
 101 static void chv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 105
 106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 107 {
 108         if (!connector->mst_port)
 109                 return connector->encoder;
 110         else
 111                 return &connector->mst_port->mst_encoders[pipe]->base;
 112 }
 113
 114 typedef struct {
 115         int     min, max;
 116 } intel_range_t;
 117
 118 typedef struct {
 119         int     dot_limit;
 120         int     p2_slow, p2_fast;
 121 } intel_p2_t;
 122
 123 typedef struct intel_limit intel_limit_t;
 124 struct intel_limit {
 125         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 126         intel_p2_t          p2;
 127 };
 128
 129 int
 130 intel_pch_rawclk(struct drm_device *dev)
 131 {
 132         struct drm_i915_private *dev_priv = dev->dev_private;
 133
 134         WARN_ON(!HAS_PCH_SPLIT(dev));
 135
 136         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 137 }
 138
 139 static inline u32 /* units of 100MHz */
 140 intel_fdi_link_freq(struct drm_device *dev)
 141 {
 142         if (IS_GEN5(dev)) {
 143                 struct drm_i915_private *dev_priv = dev->dev_private;
 144                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 145         } else
 146                 return 27;
 147 }
 148
 149 static const intel_limit_t intel_limits_i8xx_dac = {
 150         .dot = { .min = 25000, .max = 350000 },
 151         .vco = { .min = 908000, .max = 1512000 },
 152         .n = { .min = 2, .max = 16 },
 153         .m = { .min = 96, .max = 140 },
 154         .m1 = { .min = 18, .max = 26 },
 155         .m2 = { .min = 6, .max = 16 },
 156         .p = { .min = 4, .max = 128 },
 157         .p1 = { .min = 2, .max = 33 },
 158         .p2 = { .dot_limit = 165000,
 159                 .p2_slow = 4, .p2_fast = 2 },
 160 };
 161
 162 static const intel_limit_t intel_limits_i8xx_dvo = {
 163         .dot = { .min = 25000, .max = 350000 },
 164         .vco = { .min = 908000, .max = 1512000 },
 165         .n = { .min = 2, .max = 16 },
 166         .m = { .min = 96, .max = 140 },
 167         .m1 = { .min = 18, .max = 26 },
 168         .m2 = { .min = 6, .max = 16 },
 169         .p = { .min = 4, .max = 128 },
 170         .p1 = { .min = 2, .max = 33 },
 171         .p2 = { .dot_limit = 165000,
 172                 .p2_slow = 4, .p2_fast = 4 },
 173 };
 174
 175 static const intel_limit_t intel_limits_i8xx_lvds = {
 176         .dot = { .min = 25000, .max = 350000 },
 177         .vco = { .min = 908000, .max = 1512000 },
 178         .n = { .min = 2, .max = 16 },
 179         .m = { .min = 96, .max = 140 },
 180         .m1 = { .min = 18, .max = 26 },
 181         .m2 = { .min = 6, .max = 16 },
 182         .p = { .min = 4, .max = 128 },
 183         .p1 = { .min = 1, .max = 6 },
 184         .p2 = { .dot_limit = 165000,
 185                 .p2_slow = 14, .p2_fast = 7 },
 186 };
 187
 188 static const intel_limit_t intel_limits_i9xx_sdvo = {
 189         .dot = { .min = 20000, .max = 400000 },
 190         .vco = { .min = 1400000, .max = 2800000 },
 191         .n = { .min = 1, .max = 6 },
 192         .m = { .min = 70, .max = 120 },
 193         .m1 = { .min = 8, .max = 18 },
 194         .m2 = { .min = 3, .max = 7 },
 195         .p = { .min = 5, .max = 80 },
 196         .p1 = { .min = 1, .max = 8 },
 197         .p2 = { .dot_limit = 200000,
 198                 .p2_slow = 10, .p2_fast = 5 },
 199 };
 200
 201 static const intel_limit_t intel_limits_i9xx_lvds = {
 202         .dot = { .min = 20000, .max = 400000 },
 203         .vco = { .min = 1400000, .max = 2800000 },
 204         .n = { .min = 1, .max = 6 },
 205         .m = { .min = 70, .max = 120 },
 206         .m1 = { .min = 8, .max = 18 },
 207         .m2 = { .min = 3, .max = 7 },
 208         .p = { .min = 7, .max = 98 },
 209         .p1 = { .min = 1, .max = 8 },
 210         .p2 = { .dot_limit = 112000,
 211                 .p2_slow = 14, .p2_fast = 7 },
 212 };
 213
 214
 215 static const intel_limit_t intel_limits_g4x_sdvo = {
 216         .dot = { .min = 25000, .max = 270000 },
 217         .vco = { .min = 1750000, .max = 3500000},
 218         .n = { .min = 1, .max = 4 },
 219         .m = { .min = 104, .max = 138 },
 220         .m1 = { .min = 17, .max = 23 },
 221         .m2 = { .min = 5, .max = 11 },
 222         .p = { .min = 10, .max = 30 },
 223         .p1 = { .min = 1, .max = 3},
 224         .p2 = { .dot_limit = 270000,
 225                 .p2_slow = 10,
 226                 .p2_fast = 10
 227         },
 228 };
 229
 230 static const intel_limit_t intel_limits_g4x_hdmi = {
 231         .dot = { .min = 22000, .max = 400000 },
 232         .vco = { .min = 1750000, .max = 3500000},
 233         .n = { .min = 1, .max = 4 },
 234         .m = { .min = 104, .max = 138 },
 235         .m1 = { .min = 16, .max = 23 },
 236         .m2 = { .min = 5, .max = 11 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8},
 239         .p2 = { .dot_limit = 165000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 244         .dot = { .min = 20000, .max = 115000 },
 245         .vco = { .min = 1750000, .max = 3500000 },
 246         .n = { .min = 1, .max = 3 },
 247         .m = { .min = 104, .max = 138 },
 248         .m1 = { .min = 17, .max = 23 },
 249         .m2 = { .min = 5, .max = 11 },
 250         .p = { .min = 28, .max = 112 },
 251         .p1 = { .min = 2, .max = 8 },
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 14, .p2_fast = 14
 254         },
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 258         .dot = { .min = 80000, .max = 224000 },
 259         .vco = { .min = 1750000, .max = 3500000 },
 260         .n = { .min = 1, .max = 3 },
 261         .m = { .min = 104, .max = 138 },
 262         .m1 = { .min = 17, .max = 23 },
 263         .m2 = { .min = 5, .max = 11 },
 264         .p = { .min = 14, .max = 42 },
 265         .p1 = { .min = 2, .max = 6 },
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 7, .p2_fast = 7
 268         },
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284 };
 285
 286 static const intel_limit_t intel_limits_pineview_lvds = {
 287         .dot = { .min = 20000, .max = 400000 },
 288         .vco = { .min = 1700000, .max = 3500000 },
 289         .n = { .min = 3, .max = 6 },
 290         .m = { .min = 2, .max = 256 },
 291         .m1 = { .min = 0, .max = 0 },
 292         .m2 = { .min = 0, .max = 254 },
 293         .p = { .min = 7, .max = 112 },
 294         .p1 = { .min = 1, .max = 8 },
 295         .p2 = { .dot_limit = 112000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 /* Ironlake / Sandybridge
 300  *
 301  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 302  * the range value for them is (actual_value - 2).
 303  */
 304 static const intel_limit_t intel_limits_ironlake_dac = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 5 },
 308         .m = { .min = 79, .max = 127 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 5, .max = 80 },
 312         .p1 = { .min = 1, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 10, .p2_fast = 5 },
 315 };
 316
 317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 3 },
 321         .m = { .min = 79, .max = 118 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328 };
 329
 330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 331         .dot = { .min = 25000, .max = 350000 },
 332         .vco = { .min = 1760000, .max = 3510000 },
 333         .n = { .min = 1, .max = 3 },
 334         .m = { .min = 79, .max = 127 },
 335         .m1 = { .min = 12, .max = 22 },
 336         .m2 = { .min = 5, .max = 9 },
 337         .p = { .min = 14, .max = 56 },
 338         .p1 = { .min = 2, .max = 8 },
 339         .p2 = { .dot_limit = 225000,
 340                 .p2_slow = 7, .p2_fast = 7 },
 341 };
 342
 343 /* LVDS 100mhz refclk limits. */
 344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 345         .dot = { .min = 25000, .max = 350000 },
 346         .vco = { .min = 1760000, .max = 3510000 },
 347         .n = { .min = 1, .max = 2 },
 348         .m = { .min = 79, .max = 126 },
 349         .m1 = { .min = 12, .max = 22 },
 350         .m2 = { .min = 5, .max = 9 },
 351         .p = { .min = 28, .max = 112 },
 352         .p1 = { .min = 2, .max = 8 },
 353         .p2 = { .dot_limit = 225000,
 354                 .p2_slow = 14, .p2_fast = 14 },
 355 };
 356
 357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 358         .dot = { .min = 25000, .max = 350000 },
 359         .vco = { .min = 1760000, .max = 3510000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 79, .max = 126 },
 362         .m1 = { .min = 12, .max = 22 },
 363         .m2 = { .min = 5, .max = 9 },
 364         .p = { .min = 14, .max = 42 },
 365         .p1 = { .min = 2, .max = 6 },
 366         .p2 = { .dot_limit = 225000,
 367                 .p2_slow = 7, .p2_fast = 7 },
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv = {
 371          /*
 372           * These are the data rate limits (measured in fast clocks)
 373           * since those are the strictest limits we have. The fast
 374           * clock and actual rate limits are more relaxed, so checking
 375           * them would make no difference.
 376           */
 377         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 378         .vco = { .min = 4000000, .max = 6000000 },
 379         .n = { .min = 1, .max = 7 },
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p1 = { .min = 2, .max = 3 },
 383         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 384 };
 385
 386 static const intel_limit_t intel_limits_chv = {
 387         /*
 388          * These are the data rate limits (measured in fast clocks)
 389          * since those are the strictest limits we have.  The fast
 390          * clock and actual rate limits are more relaxed, so checking
 391          * them would make no difference.
 392          */
 393         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 394         .vco = { .min = 4800000, .max = 6480000 },
 395         .n = { .min = 1, .max = 1 },
 396         .m1 = { .min = 2, .max = 2 },
 397         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 398         .p1 = { .min = 2, .max = 4 },
 399         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 400 };
 401
 402 static void vlv_clock(int refclk, intel_clock_t *clock)
 403 {
 404         clock->m = clock->m1 * clock->m2;
 405         clock->p = clock->p1 * clock->p2;
 406         if (WARN_ON(clock->n == 0 || clock->p == 0))
 407                 return;
 408         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 409         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 410 }
 411
 412 /**
 413  * Returns whether any output on the specified pipe is of the specified type
 414  */
 415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 416 {
 417         struct drm_device *dev = crtc->base.dev;
 418         struct intel_encoder *encoder;
 419
 420         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 421                 if (encoder->type == type)
 422                         return true;
 423
 424         return false;
 425 }
 426
 427 /**
 428  * Returns whether any output on the specified pipe will have the specified
 429  * type after a staged modeset is complete, i.e., the same as
 430  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 431  * encoder->crtc.
 432  */
 433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 434 {
 435         struct drm_device *dev = crtc->base.dev;
 436         struct intel_encoder *encoder;
 437
 438         for_each_intel_encoder(dev, encoder)
 439                 if (encoder->new_crtc == crtc && encoder->type == type)
 440                         return true;
 441
 442         return false;
 443 }
 444
 445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 446                                                 int refclk)
 447 {
 448         struct drm_device *dev = crtc->base.dev;
 449         const intel_limit_t *limit;
 450
 451         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 452                 if (intel_is_dual_link_lvds(dev)) {
 453                         if (refclk == 100000)
 454                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 455                         else
 456                                 limit = &intel_limits_ironlake_dual_lvds;
 457                 } else {
 458                         if (refclk == 100000)
 459                                 limit = &intel_limits_ironlake_single_lvds_100m;
 460                         else
 461                                 limit = &intel_limits_ironlake_single_lvds;
 462                 }
 463         } else
 464                 limit = &intel_limits_ironlake_dac;
 465
 466         return limit;
 467 }
 468
 469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 470 {
 471         struct drm_device *dev = crtc->base.dev;
 472         const intel_limit_t *limit;
 473
 474         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 475                 if (intel_is_dual_link_lvds(dev))
 476                         limit = &intel_limits_g4x_dual_channel_lvds;
 477                 else
 478                         limit = &intel_limits_g4x_single_channel_lvds;
 479         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 480                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 481                 limit = &intel_limits_g4x_hdmi;
 482         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 483                 limit = &intel_limits_g4x_sdvo;
 484         } else /* The option is for other outputs */
 485                 limit = &intel_limits_i9xx_sdvo;
 486
 487         return limit;
 488 }
 489
 490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 491 {
 492         struct drm_device *dev = crtc->base.dev;
 493         const intel_limit_t *limit;
 494
 495         if (HAS_PCH_SPLIT(dev))
 496                 limit = intel_ironlake_limit(crtc, refclk);
 497         else if (IS_G4X(dev)) {
 498                 limit = intel_g4x_limit(crtc);
 499         } else if (IS_PINEVIEW(dev)) {
 500                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 501                         limit = &intel_limits_pineview_lvds;
 502                 else
 503                         limit = &intel_limits_pineview_sdvo;
 504         } else if (IS_CHERRYVIEW(dev)) {
 505                 limit = &intel_limits_chv;
 506         } else if (IS_VALLEYVIEW(dev)) {
 507                 limit = &intel_limits_vlv;
 508         } else if (!IS_GEN2(dev)) {
 509                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 510                         limit = &intel_limits_i9xx_lvds;
 511                 else
 512                         limit = &intel_limits_i9xx_sdvo;
 513         } else {
 514                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 515                         limit = &intel_limits_i8xx_lvds;
 516                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 517                         limit = &intel_limits_i8xx_dvo;
 518                 else
 519                         limit = &intel_limits_i8xx_dac;
 520         }
 521         return limit;
 522 }
 523
 524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 525 static void pineview_clock(int refclk, intel_clock_t *clock)
 526 {
 527         clock->m = clock->m2 + 2;
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n == 0 || clock->p == 0))
 530                 return;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533 }
 534
 535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 536 {
 537         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 538 }
 539
 540 static void i9xx_clock(int refclk, intel_clock_t *clock)
 541 {
 542         clock->m = i9xx_dpll_compute_m(clock);
 543         clock->p = clock->p1 * clock->p2;
 544         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 545                 return;
 546         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 547         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 548 }
 549
 550 static void chv_clock(int refclk, intel_clock_t *clock)
 551 {
 552         clock->m = clock->m1 * clock->m2;
 553         clock->p = clock->p1 * clock->p2;
 554         if (WARN_ON(clock->n == 0 || clock->p == 0))
 555                 return;
 556         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 557                         clock->n << 22);
 558         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 559 }
 560
 561 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 562 /**
 563  * Returns whether the given set of divisors are valid for a given refclk with
 564  * the given connectors.
 565  */
 566
 567 static bool intel_PLL_is_valid(struct drm_device *dev,
 568                                const intel_limit_t *limit,
 569                                const intel_clock_t *clock)
 570 {
 571         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 572                 INTELPllInvalid("n out of range\n");
 573         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 574                 INTELPllInvalid("p1 out of range\n");
 575         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 576                 INTELPllInvalid("m2 out of range\n");
 577         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 578                 INTELPllInvalid("m1 out of range\n");
 579
 580         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 581                 if (clock->m1 <= clock->m2)
 582                         INTELPllInvalid("m1 <= m2\n");
 583
 584         if (!IS_VALLEYVIEW(dev)) {
 585                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 586                         INTELPllInvalid("p out of range\n");
 587                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 588                         INTELPllInvalid("m out of range\n");
 589         }
 590
 591         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 592                 INTELPllInvalid("vco out of range\n");
 593         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 594          * connector, etc., rather than just a single range.
 595          */
 596         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 597                 INTELPllInvalid("dot out of range\n");
 598
 599         return true;
 600 }
 601
 602 static bool
 603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 604                     int target, int refclk, intel_clock_t *match_clock,
 605                     intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->base.dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         if (clock.m2 >= clock.m1)
 635                                 break;
 636                         for (clock.n = limit->n.min;
 637                              clock.n <= limit->n.max; clock.n++) {
 638                                 for (clock.p1 = limit->p1.min;
 639                                         clock.p1 <= limit->p1.max; clock.p1++) {
 640                                         int this_err;
 641
 642                                         i9xx_clock(refclk, &clock);
 643                                         if (!intel_PLL_is_valid(dev, limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 static bool
 664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         struct drm_device *dev = crtc->base.dev;
 669         intel_clock_t clock;
 670         int err = target;
 671
 672         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 673                 /*
 674                  * For LVDS just rely on its current settings for dual-channel.
 675                  * We haven't figured out how to reliably set up different
 676                  * single/dual channel state, if we even can.
 677                  */
 678                 if (intel_is_dual_link_lvds(dev))
 679                         clock.p2 = limit->p2.p2_fast;
 680                 else
 681                         clock.p2 = limit->p2.p2_slow;
 682         } else {
 683                 if (target < limit->p2.dot_limit)
 684                         clock.p2 = limit->p2.p2_slow;
 685                 else
 686                         clock.p2 = limit->p2.p2_fast;
 687         }
 688
 689         memset(best_clock, 0, sizeof(*best_clock));
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         for (clock.n = limit->n.min;
 696                              clock.n <= limit->n.max; clock.n++) {
 697                                 for (clock.p1 = limit->p1.min;
 698                                         clock.p1 <= limit->p1.max; clock.p1++) {
 699                                         int this_err;
 700
 701                                         pineview_clock(refclk, &clock);
 702                                         if (!intel_PLL_is_valid(dev, limit,
 703                                                                 &clock))
 704                                                 continue;
 705                                         if (match_clock &&
 706                                             clock.p != match_clock->p)
 707                                                 continue;
 708
 709                                         this_err = abs(clock.dot - target);
 710                                         if (this_err < err) {
 711                                                 *best_clock = clock;
 712                                                 err = this_err;
 713                                         }
 714                                 }
 715                         }
 716                 }
 717         }
 718
 719         return (err != target);
 720 }
 721
 722 static bool
 723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 724                    int target, int refclk, intel_clock_t *match_clock,
 725                    intel_clock_t *best_clock)
 726 {
 727         struct drm_device *dev = crtc->base.dev;
 728         intel_clock_t clock;
 729         int max_n;
 730         bool found;
 731         /* approximately equals target * 0.00585 */
 732         int err_most = (target >> 8) + (target >> 9);
 733         found = false;
 734
 735         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 736                 if (intel_is_dual_link_lvds(dev))
 737                         clock.p2 = limit->p2.p2_fast;
 738                 else
 739                         clock.p2 = limit->p2.p2_slow;
 740         } else {
 741                 if (target < limit->p2.dot_limit)
 742                         clock.p2 = limit->p2.p2_slow;
 743                 else
 744                         clock.p2 = limit->p2.p2_fast;
 745         }
 746
 747         memset(best_clock, 0, sizeof(*best_clock));
 748         max_n = limit->n.max;
 749         /* based on hardware requirement, prefer smaller n to precision */
 750         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 751                 /* based on hardware requirement, prefere larger m1,m2 */
 752                 for (clock.m1 = limit->m1.max;
 753                      clock.m1 >= limit->m1.min; clock.m1--) {
 754                         for (clock.m2 = limit->m2.max;
 755                              clock.m2 >= limit->m2.min; clock.m2--) {
 756                                 for (clock.p1 = limit->p1.max;
 757                                      clock.p1 >= limit->p1.min; clock.p1--) {
 758                                         int this_err;
 759
 760                                         i9xx_clock(refclk, &clock);
 761                                         if (!intel_PLL_is_valid(dev, limit,
 762                                                                 &clock))
 763                                                 continue;
 764
 765                                         this_err = abs(clock.dot - target);
 766                                         if (this_err < err_most) {
 767                                                 *best_clock = clock;
 768                                                 err_most = this_err;
 769                                                 max_n = clock.n;
 770                                                 found = true;
 771                                         }
 772                                 }
 773                         }
 774                 }
 775         }
 776         return found;
 777 }
 778
 779 /*
 780  * Check if the calculated PLL configuration is more optimal compared to the
 781  * best configuration and error found so far. Return the calculated error.
 782  */
 783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 784                                const intel_clock_t *calculated_clock,
 785                                const intel_clock_t *best_clock,
 786                                unsigned int best_error_ppm,
 787                                unsigned int *error_ppm)
 788 {
 789         /*
 790          * For CHV ignore the error and consider only the P value.
 791          * Prefer a bigger P value based on HW requirements.
 792          */
 793         if (IS_CHERRYVIEW(dev)) {
 794                 *error_ppm = 0;
 795
 796                 return calculated_clock->p > best_clock->p;
 797         }
 798
 799         if (WARN_ON_ONCE(!target_freq))
 800                 return false;
 801
 802         *error_ppm = div_u64(1000000ULL *
 803                                 abs(target_freq - calculated_clock->dot),
 804                              target_freq);
 805         /*
 806          * Prefer a better P value over a better (smaller) error if the error
 807          * is small. Ensure this preference for future configurations too by
 808          * setting the error to 0.
 809          */
 810         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 811                 *error_ppm = 0;
 812
 813                 return true;
 814         }
 815
 816         return *error_ppm + 10 < best_error_ppm;
 817 }
 818
 819 static bool
 820 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 821                    int target, int refclk, intel_clock_t *match_clock,
 822                    intel_clock_t *best_clock)
 823 {
 824         struct drm_device *dev = crtc->base.dev;
 825         intel_clock_t clock;
 826         unsigned int bestppm = 1000000;
 827         /* min update 19.2 MHz */
 828         int max_n = min(limit->n.max, refclk / 19200);
 829         bool found = false;
 830
 831         target *= 5; /* fast clock */
 832
 833         memset(best_clock, 0, sizeof(*best_clock));
 834
 835         /* based on hardware requirement, prefer smaller n to precision */
 836         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 837                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 838                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 839                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 840                                 clock.p = clock.p1 * clock.p2;
 841                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 842                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 843                                         unsigned int ppm;
 844
 845                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 846                                                                      refclk * clock.m1);
 847
 848                                         vlv_clock(refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(dev, limit,
 851                                                                 &clock))
 852                                                 continue;
 853
 854                                         if (!vlv_PLL_is_optimal(dev, target,
 855                                                                 &clock,
 856                                                                 best_clock,
 857                                                                 bestppm, &ppm))
 858                                                 continue;
 859
 860                                         *best_clock = clock;
 861                                         bestppm = ppm;
 862                                         found = true;
 863                                 }
 864                         }
 865                 }
 866         }
 867
 868         return found;
 869 }
 870
 871 static bool
 872 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 873                    int target, int refclk, intel_clock_t *match_clock,
 874                    intel_clock_t *best_clock)
 875 {
 876         struct drm_device *dev = crtc->base.dev;
 877         unsigned int best_error_ppm;
 878         intel_clock_t clock;
 879         uint64_t m2;
 880         int found = false;
 881
 882         memset(best_clock, 0, sizeof(*best_clock));
 883         best_error_ppm = 1000000;
 884
 885         /*
 886          * Based on hardware doc, the n always set to 1, and m1 always
 887          * set to 2.  If requires to support 200Mhz refclk, we need to
 888          * revisit this because n may not 1 anymore.
 889          */
 890         clock.n = 1, clock.m1 = 2;
 891         target *= 5;    /* fast clock */
 892
 893         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 894                 for (clock.p2 = limit->p2.p2_fast;
 895                                 clock.p2 >= limit->p2.p2_slow;
 896                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 897                         unsigned int error_ppm;
 898
 899                         clock.p = clock.p1 * clock.p2;
 900
 901                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 902                                         clock.n) << 22, refclk * clock.m1);
 903
 904                         if (m2 > INT_MAX/clock.m1)
 905                                 continue;
 906
 907                         clock.m2 = m2;
 908
 909                         chv_clock(refclk, &clock);
 910
 911                         if (!intel_PLL_is_valid(dev, limit, &clock))
 912                                 continue;
 913
 914                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 915                                                 best_error_ppm, &error_ppm))
 916                                 continue;
 917
 918                         *best_clock = clock;
 919                         best_error_ppm = error_ppm;
 920                         found = true;
 921                 }
 922         }
 923
 924         return found;
 925 }
 926
 927 bool intel_crtc_active(struct drm_crtc *crtc)
 928 {
 929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 930
 931         /* Be paranoid as we can arrive here with only partial
 932          * state retrieved from the hardware during setup.
 933          *
 934          * We can ditch the adjusted_mode.crtc_clock check as soon
 935          * as Haswell has gained clock readout/fastboot support.
 936          *
 937          * We can ditch the crtc->primary->fb check as soon as we can
 938          * properly reconstruct framebuffers.
 939          *
 940          * FIXME: The intel_crtc->active here should be switched to
 941          * crtc->state->active once we have proper CRTC states wired up
 942          * for atomic.
 943          */
 944         return intel_crtc->active && crtc->primary->state->fb &&
 945                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 946 }
 947
 948 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 949                                              enum pipe pipe)
 950 {
 951         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 953
 954         return intel_crtc->config->cpu_transcoder;
 955 }
 956
 957 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 958 {
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         u32 reg = PIPEDSL(pipe);
 961         u32 line1, line2;
 962         u32 line_mask;
 963
 964         if (IS_GEN2(dev))
 965                 line_mask = DSL_LINEMASK_GEN2;
 966         else
 967                 line_mask = DSL_LINEMASK_GEN3;
 968
 969         line1 = I915_READ(reg) & line_mask;
 970         mdelay(5);
 971         line2 = I915_READ(reg) & line_mask;
 972
 973         return line1 == line2;
 974 }
 975
 976 /*
 977  * intel_wait_for_pipe_off - wait for pipe to turn off
 978  * @crtc: crtc whose pipe to wait for
 979  *
 980  * After disabling a pipe, we can't wait for vblank in the usual way,
 981  * spinning on the vblank interrupt status bit, since we won't actually
 982  * see an interrupt when the pipe is disabled.
 983  *
 984  * On Gen4 and above:
 985  *   wait for the pipe register state bit to turn off
 986  *
 987  * Otherwise:
 988  *   wait for the display line value to settle (it usually
 989  *   ends up stopping at the start of the next frame).
 990  *
 991  */
 992 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 993 {
 994         struct drm_device *dev = crtc->base.dev;
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
 997         enum pipe pipe = crtc->pipe;
 998
 999         if (INTEL_INFO(dev)->gen >= 4) {
1000                 int reg = PIPECONF(cpu_transcoder);
1001
1002                 /* Wait for the Pipe State to go off */
1003                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004                              100))
1005                         WARN(1, "pipe_off wait timed out\n");
1006         } else {
1007                 /* Wait for the display line to settle */
1008                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         }
1011 }
1012
1013 /*
1014  * ibx_digital_port_connected - is the specified port connected?
1015  * @dev_priv: i915 private structure
1016  * @port: the port to test
1017  *
1018  * Returns true if @port is connected, false otherwise.
1019  */
1020 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021                                 struct intel_digital_port *port)
1022 {
1023         u32 bit;
1024
1025         if (HAS_PCH_IBX(dev_priv->dev)) {
1026                 switch (port->port) {
1027                 case PORT_B:
1028                         bit = SDE_PORTB_HOTPLUG;
1029                         break;
1030                 case PORT_C:
1031                         bit = SDE_PORTC_HOTPLUG;
1032                         break;
1033                 case PORT_D:
1034                         bit = SDE_PORTD_HOTPLUG;
1035                         break;
1036                 default:
1037                         return true;
1038                 }
1039         } else {
1040                 switch (port->port) {
1041                 case PORT_B:
1042                         bit = SDE_PORTB_HOTPLUG_CPT;
1043                         break;
1044                 case PORT_C:
1045                         bit = SDE_PORTC_HOTPLUG_CPT;
1046                         break;
1047                 case PORT_D:
1048                         bit = SDE_PORTD_HOTPLUG_CPT;
1049                         break;
1050                 default:
1051                         return true;
1052                 }
1053         }
1054
1055         return I915_READ(SDEISR) & bit;
1056 }
1057
1058 static const char *state_string(bool enabled)
1059 {
1060         return enabled ? "on" : "off";
1061 }
1062
1063 /* Only for pre-ILK configs */
1064 void assert_pll(struct drm_i915_private *dev_priv,
1065                 enum pipe pipe, bool state)
1066 {
1067         int reg;
1068         u32 val;
1069         bool cur_state;
1070
1071         reg = DPLL(pipe);
1072         val = I915_READ(reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         I915_STATE_WARN(cur_state != state,
1075              "PLL state assertion failure (expected %s, current %s)\n",
1076              state_string(state), state_string(cur_state));
1077 }
1078
1079 /* XXX: the dsi pll is shared between MIPI DSI ports */
1080 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081 {
1082         u32 val;
1083         bool cur_state;
1084
1085         mutex_lock(&dev_priv->dpio_lock);
1086         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087         mutex_unlock(&dev_priv->dpio_lock);
1088
1089         cur_state = val & DSI_PLL_VCO_EN;
1090         I915_STATE_WARN(cur_state != state,
1091              "DSI PLL state assertion failure (expected %s, current %s)\n",
1092              state_string(state), state_string(cur_state));
1093 }
1094 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
1097 struct intel_shared_dpll *
1098 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099 {
1100         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
1102         if (crtc->config->shared_dpll < 0)
1103                 return NULL;
1104
1105         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1106 }
1107
1108 /* For ILK+ */
1109 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110                         struct intel_shared_dpll *pll,
1111                         bool state)
1112 {
1113         bool cur_state;
1114         struct intel_dpll_hw_state hw_state;
1115
1116         if (WARN (!pll,
1117                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1118                 return;
1119
1120         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121         I915_STATE_WARN(cur_state != state,
1122              "%s assertion failure (expected %s, current %s)\n",
1123              pll->name, state_string(state), state_string(cur_state));
1124 }
1125
1126 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127                           enum pipe pipe, bool state)
1128 {
1129         int reg;
1130         u32 val;
1131         bool cur_state;
1132         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133                                                                       pipe);
1134
1135         if (HAS_DDI(dev_priv->dev)) {
1136                 /* DDI does not have a specific FDI_TX register */
1137                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138                 val = I915_READ(reg);
1139                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1140         } else {
1141                 reg = FDI_TX_CTL(pipe);
1142                 val = I915_READ(reg);
1143                 cur_state = !!(val & FDI_TX_ENABLE);
1144         }
1145         I915_STATE_WARN(cur_state != state,
1146              "FDI TX state assertion failure (expected %s, current %s)\n",
1147              state_string(state), state_string(cur_state));
1148 }
1149 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153                           enum pipe pipe, bool state)
1154 {
1155         int reg;
1156         u32 val;
1157         bool cur_state;
1158
1159         reg = FDI_RX_CTL(pipe);
1160         val = I915_READ(reg);
1161         cur_state = !!(val & FDI_RX_ENABLE);
1162         I915_STATE_WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (HAS_DDI(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189                        enum pipe pipe, bool state)
1190 {
1191         int reg;
1192         u32 val;
1193         bool cur_state;
1194
1195         reg = FDI_RX_CTL(pipe);
1196         val = I915_READ(reg);
1197         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198         I915_STATE_WARN(cur_state != state,
1199              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200              state_string(state), state_string(cur_state));
1201 }
1202
1203 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                            enum pipe pipe)
1205 {
1206         struct drm_device *dev = dev_priv->dev;
1207         int pp_reg;
1208         u32 val;
1209         enum pipe panel_pipe = PIPE_A;
1210         bool locked = true;
1211
1212         if (WARN_ON(HAS_DDI(dev)))
1213                 return;
1214
1215         if (HAS_PCH_SPLIT(dev)) {
1216                 u32 port_sel;
1217
1218                 pp_reg = PCH_PP_CONTROL;
1219                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223                         panel_pipe = PIPE_B;
1224                 /* XXX: else fix for eDP */
1225         } else if (IS_VALLEYVIEW(dev)) {
1226                 /* presumably write lock depends on pipe, not port select */
1227                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228                 panel_pipe = pipe;
1229         } else {
1230                 pp_reg = PP_CONTROL;
1231                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232                         panel_pipe = PIPE_B;
1233         }
1234
1235         val = I915_READ(pp_reg);
1236         if (!(val & PANEL_POWER_ON) ||
1237             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1238                 locked = false;
1239
1240         I915_STATE_WARN(panel_pipe == pipe && locked,
1241              "panel assertion failure, pipe %c regs locked\n",
1242              pipe_name(pipe));
1243 }
1244
1245 static void assert_cursor(struct drm_i915_private *dev_priv,
1246                           enum pipe pipe, bool state)
1247 {
1248         struct drm_device *dev = dev_priv->dev;
1249         bool cur_state;
1250
1251         if (IS_845G(dev) || IS_I865G(dev))
1252                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1253         else
1254                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1255
1256         I915_STATE_WARN(cur_state != state,
1257              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258              pipe_name(pipe), state_string(state), state_string(cur_state));
1259 }
1260 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
1263 void assert_pipe(struct drm_i915_private *dev_priv,
1264                  enum pipe pipe, bool state)
1265 {
1266         int reg;
1267         u32 val;
1268         bool cur_state;
1269         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270                                                                       pipe);
1271
1272         /* if we need the pipe quirk it must be always on */
1273         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1275                 state = true;
1276
1277         if (!intel_display_power_is_enabled(dev_priv,
1278                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1279                 cur_state = false;
1280         } else {
1281                 reg = PIPECONF(cpu_transcoder);
1282                 val = I915_READ(reg);
1283                 cur_state = !!(val & PIPECONF_ENABLE);
1284         }
1285
1286         I915_STATE_WARN(cur_state != state,
1287              "pipe %c assertion failure (expected %s, current %s)\n",
1288              pipe_name(pipe), state_string(state), state_string(cur_state));
1289 }
1290
1291 static void assert_plane(struct drm_i915_private *dev_priv,
1292                          enum plane plane, bool state)
1293 {
1294         int reg;
1295         u32 val;
1296         bool cur_state;
1297
1298         reg = DSPCNTR(plane);
1299         val = I915_READ(reg);
1300         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301         I915_STATE_WARN(cur_state != state,
1302              "plane %c assertion failure (expected %s, current %s)\n",
1303              plane_name(plane), state_string(state), state_string(cur_state));
1304 }
1305
1306 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
1309 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310                                    enum pipe pipe)
1311 {
1312         struct drm_device *dev = dev_priv->dev;
1313         int reg, i;
1314         u32 val;
1315         int cur_pipe;
1316
1317         /* Primary planes are fixed to pipes on gen4+ */
1318         if (INTEL_INFO(dev)->gen >= 4) {
1319                 reg = DSPCNTR(pipe);
1320                 val = I915_READ(reg);
1321                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322                      "plane %c assertion failure, should be disabled but not\n",
1323                      plane_name(pipe));
1324                 return;
1325         }
1326
1327         /* Need to check both planes against the pipe */
1328         for_each_pipe(dev_priv, i) {
1329                 reg = DSPCNTR(i);
1330                 val = I915_READ(reg);
1331                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332                         DISPPLANE_SEL_PIPE_SHIFT;
1333                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335                      plane_name(i), pipe_name(pipe));
1336         }
1337 }
1338
1339 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340                                     enum pipe pipe)
1341 {
1342         struct drm_device *dev = dev_priv->dev;
1343         int reg, sprite;
1344         u32 val;
1345
1346         if (INTEL_INFO(dev)->gen >= 9) {
1347                 for_each_sprite(dev_priv, pipe, sprite) {
1348                         val = I915_READ(PLANE_CTL(pipe, sprite));
1349                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351                              sprite, pipe_name(pipe));
1352                 }
1353         } else if (IS_VALLEYVIEW(dev)) {
1354                 for_each_sprite(dev_priv, pipe, sprite) {
1355                         reg = SPCNTR(pipe, sprite);
1356                         val = I915_READ(reg);
1357                         I915_STATE_WARN(val & SP_ENABLE,
1358                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359                              sprite_name(pipe, sprite), pipe_name(pipe));
1360                 }
1361         } else if (INTEL_INFO(dev)->gen >= 7) {
1362                 reg = SPRCTL(pipe);
1363                 val = I915_READ(reg);
1364                 I915_STATE_WARN(val & SPRITE_ENABLE,
1365                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366                      plane_name(pipe), pipe_name(pipe));
1367         } else if (INTEL_INFO(dev)->gen >= 5) {
1368                 reg = DVSCNTR(pipe);
1369                 val = I915_READ(reg);
1370                 I915_STATE_WARN(val & DVS_ENABLE,
1371                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372                      plane_name(pipe), pipe_name(pipe));
1373         }
1374 }
1375
1376 static void assert_vblank_disabled(struct drm_crtc *crtc)
1377 {
1378         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379                 drm_crtc_vblank_put(crtc);
1380 }
1381
1382 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1383 {
1384         u32 val;
1385         bool enabled;
1386
1387         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1388
1389         val = I915_READ(PCH_DREF_CONTROL);
1390         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391                             DREF_SUPERSPREAD_SOURCE_MASK));
1392         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1393 }
1394
1395 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396                                            enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400         bool enabled;
1401
1402         reg = PCH_TRANSCONF(pipe);
1403         val = I915_READ(reg);
1404         enabled = !!(val & TRANS_ENABLE);
1405         I915_STATE_WARN(enabled,
1406              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407              pipe_name(pipe));
1408 }
1409
1410 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411                             enum pipe pipe, u32 port_sel, u32 val)
1412 {
1413         if ((val & DP_PORT_EN) == 0)
1414                 return false;
1415
1416         if (HAS_PCH_CPT(dev_priv->dev)) {
1417                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420                         return false;
1421         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423                         return false;
1424         } else {
1425                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426                         return false;
1427         }
1428         return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432                               enum pipe pipe, u32 val)
1433 {
1434         if ((val & SDVO_ENABLE) == 0)
1435                 return false;
1436
1437         if (HAS_PCH_CPT(dev_priv->dev)) {
1438                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439                         return false;
1440         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442                         return false;
1443         } else {
1444                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445                         return false;
1446         }
1447         return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451                               enum pipe pipe, u32 val)
1452 {
1453         if ((val & LVDS_PORT_EN) == 0)
1454                 return false;
1455
1456         if (HAS_PCH_CPT(dev_priv->dev)) {
1457                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458                         return false;
1459         } else {
1460                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467                               enum pipe pipe, u32 val)
1468 {
1469         if ((val & ADPA_DAC_ENABLE) == 0)
1470                 return false;
1471         if (HAS_PCH_CPT(dev_priv->dev)) {
1472                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473                         return false;
1474         } else {
1475                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476                         return false;
1477         }
1478         return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482                                    enum pipe pipe, int reg, u32 port_sel)
1483 {
1484         u32 val = I915_READ(reg);
1485         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487              reg, pipe_name(pipe));
1488
1489         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490              && (val & DP_PIPEB_SELECT),
1491              "IBX PCH dp port still using transcoder B\n");
1492 }
1493
1494 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495                                      enum pipe pipe, int reg)
1496 {
1497         u32 val = I915_READ(reg);
1498         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500              reg, pipe_name(pipe));
1501
1502         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503              && (val & SDVO_PIPE_B_SELECT),
1504              "IBX PCH hdmi port still using transcoder B\n");
1505 }
1506
1507 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508                                       enum pipe pipe)
1509 {
1510         int reg;
1511         u32 val;
1512
1513         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517         reg = PCH_ADPA;
1518         val = I915_READ(reg);
1519         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520              "PCH VGA enabled on transcoder %c, should be disabled\n",
1521              pipe_name(pipe));
1522
1523         reg = PCH_LVDS;
1524         val = I915_READ(reg);
1525         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527              pipe_name(pipe));
1528
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532 }
1533
1534 static void intel_init_dpio(struct drm_device *dev)
1535 {
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538         if (!IS_VALLEYVIEW(dev))
1539                 return;
1540
1541         /*
1542          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543          * CHV x1 PHY (DP/HDMI D)
1544          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545          */
1546         if (IS_CHERRYVIEW(dev)) {
1547                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549         } else {
1550                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551         }
1552 }
1553
1554 static void vlv_enable_pll(struct intel_crtc *crtc,
1555                            const struct intel_crtc_state *pipe_config)
1556 {
1557         struct drm_device *dev = crtc->base.dev;
1558         struct drm_i915_private *dev_priv = dev->dev_private;
1559         int reg = DPLL(crtc->pipe);
1560         u32 dpll = pipe_config->dpll_hw_state.dpll;
1561
1562         assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564         /* No really, not for ILK+ */
1565         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567         /* PLL is protected by panel, make sure we can write it */
1568         if (IS_MOBILE(dev_priv->dev))
1569                 assert_panel_unlocked(dev_priv, crtc->pipe);
1570
1571         I915_WRITE(reg, dpll);
1572         POSTING_READ(reg);
1573         udelay(150);
1574
1575         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
1578         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579         POSTING_READ(DPLL_MD(crtc->pipe));
1580
1581         /* We do this three times for luck */
1582         I915_WRITE(reg, dpll);
1583         POSTING_READ(reg);
1584         udelay(150); /* wait for warmup */
1585         I915_WRITE(reg, dpll);
1586         POSTING_READ(reg);
1587         udelay(150); /* wait for warmup */
1588         I915_WRITE(reg, dpll);
1589         POSTING_READ(reg);
1590         udelay(150); /* wait for warmup */
1591 }
1592
1593 static void chv_enable_pll(struct intel_crtc *crtc,
1594                            const struct intel_crtc_state *pipe_config)
1595 {
1596         struct drm_device *dev = crtc->base.dev;
1597         struct drm_i915_private *dev_priv = dev->dev_private;
1598         int pipe = crtc->pipe;
1599         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1600         u32 tmp;
1601
1602         assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606         mutex_lock(&dev_priv->dpio_lock);
1607
1608         /* Enable back the 10bit clock to display controller */
1609         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610         tmp |= DPIO_DCLKP_EN;
1611         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613         /*
1614          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615          */
1616         udelay(1);
1617
1618         /* Enable PLL */
1619         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1620
1621         /* Check PLL is locked */
1622         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
1625         /* not sure when this should be written */
1626         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627         POSTING_READ(DPLL_MD(pipe));
1628
1629         mutex_unlock(&dev_priv->dpio_lock);
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634         struct intel_crtc *crtc;
1635         int count = 0;
1636
1637         for_each_intel_crtc(dev, crtc)
1638                 count += crtc->active &&
1639                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641         return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->base.dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         int reg = DPLL(crtc->pipe);
1649         u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651         assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653         /* No really, not for ILK+ */
1654         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1655
1656         /* PLL is protected by panel, make sure we can write it */
1657         if (IS_MOBILE(dev) && !IS_I830(dev))
1658                 assert_panel_unlocked(dev_priv, crtc->pipe);
1659
1660         /* Enable DVO 2x clock on both PLLs if necessary */
1661         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662                 /*
1663                  * It appears to be important that we don't enable this
1664                  * for the current pipe before otherwise configuring the
1665                  * PLL. No idea how this should be handled if multiple
1666                  * DVO outputs are enabled simultaneosly.
1667                  */
1668                 dpll |= DPLL_DVO_2X_MODE;
1669                 I915_WRITE(DPLL(!crtc->pipe),
1670                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671         }
1672
1673         /* Wait for the clocks to stabilize. */
1674         POSTING_READ(reg);
1675         udelay(150);
1676
1677         if (INTEL_INFO(dev)->gen >= 4) {
1678                 I915_WRITE(DPLL_MD(crtc->pipe),
1679                            crtc->config->dpll_hw_state.dpll_md);
1680         } else {
1681                 /* The pixel multiplier can only be updated once the
1682                  * DPLL is enabled and the clocks are stable.
1683                  *
1684                  * So write it again.
1685                  */
1686                 I915_WRITE(reg, dpll);
1687         }
1688
1689         /* We do this three times for luck */
1690         I915_WRITE(reg, dpll);
1691         POSTING_READ(reg);
1692         udelay(150); /* wait for warmup */
1693         I915_WRITE(reg, dpll);
1694         POSTING_READ(reg);
1695         udelay(150); /* wait for warmup */
1696         I915_WRITE(reg, dpll);
1697         POSTING_READ(reg);
1698         udelay(150); /* wait for warmup */
1699 }
1700
1701 /**
1702  * i9xx_disable_pll - disable a PLL
1703  * @dev_priv: i915 private structure
1704  * @pipe: pipe PLL to disable
1705  *
1706  * Disable the PLL for @pipe, making sure the pipe is off first.
1707  *
1708  * Note!  This is for pre-ILK only.
1709  */
1710 static void i9xx_disable_pll(struct intel_crtc *crtc)
1711 {
1712         struct drm_device *dev = crtc->base.dev;
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         enum pipe pipe = crtc->pipe;
1715
1716         /* Disable DVO 2x clock on both PLLs if necessary */
1717         if (IS_I830(dev) &&
1718             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719             intel_num_dvo_pipes(dev) == 1) {
1720                 I915_WRITE(DPLL(PIPE_B),
1721                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722                 I915_WRITE(DPLL(PIPE_A),
1723                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724         }
1725
1726         /* Don't disable pipe or pipe PLLs if needed */
1727         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1729                 return;
1730
1731         /* Make sure the pipe isn't still relying on us */
1732         assert_pipe_disabled(dev_priv, pipe);
1733
1734         I915_WRITE(DPLL(pipe), 0);
1735         POSTING_READ(DPLL(pipe));
1736 }
1737
1738 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739 {
1740         u32 val = 0;
1741
1742         /* Make sure the pipe isn't still relying on us */
1743         assert_pipe_disabled(dev_priv, pipe);
1744
1745         /*
1746          * Leave integrated clock source and reference clock enabled for pipe B.
1747          * The latter is needed for VGA hotplug / manual detection.
1748          */
1749         if (pipe == PIPE_B)
1750                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751         I915_WRITE(DPLL(pipe), val);
1752         POSTING_READ(DPLL(pipe));
1753
1754 }
1755
1756 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757 {
1758         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1759         u32 val;
1760
1761         /* Make sure the pipe isn't still relying on us */
1762         assert_pipe_disabled(dev_priv, pipe);
1763
1764         /* Set PLL en = 0 */
1765         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1766         if (pipe != PIPE_A)
1767                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768         I915_WRITE(DPLL(pipe), val);
1769         POSTING_READ(DPLL(pipe));
1770
1771         mutex_lock(&dev_priv->dpio_lock);
1772
1773         /* Disable 10bit clock to display controller */
1774         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775         val &= ~DPIO_DCLKP_EN;
1776         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
1778         /* disable left/right clock distribution */
1779         if (pipe != PIPE_B) {
1780                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783         } else {
1784                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787         }
1788
1789         mutex_unlock(&dev_priv->dpio_lock);
1790 }
1791
1792 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793                 struct intel_digital_port *dport)
1794 {
1795         u32 port_mask;
1796         int dpll_reg;
1797
1798         switch (dport->port) {
1799         case PORT_B:
1800                 port_mask = DPLL_PORTB_READY_MASK;
1801                 dpll_reg = DPLL(0);
1802                 break;
1803         case PORT_C:
1804                 port_mask = DPLL_PORTC_READY_MASK;
1805                 dpll_reg = DPLL(0);
1806                 break;
1807         case PORT_D:
1808                 port_mask = DPLL_PORTD_READY_MASK;
1809                 dpll_reg = DPIO_PHY_STATUS;
1810                 break;
1811         default:
1812                 BUG();
1813         }
1814
1815         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817                      port_name(dport->port), I915_READ(dpll_reg));
1818 }
1819
1820 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821 {
1822         struct drm_device *dev = crtc->base.dev;
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
1826         if (WARN_ON(pll == NULL))
1827                 return;
1828
1829         WARN_ON(!pll->config.crtc_mask);
1830         if (pll->active == 0) {
1831                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832                 WARN_ON(pll->on);
1833                 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835                 pll->mode_set(dev_priv, pll);
1836         }
1837 }
1838
1839 /**
1840  * intel_enable_shared_dpll - enable PCH PLL
1841  * @dev_priv: i915 private structure
1842  * @pipe: pipe PLL to enable
1843  *
1844  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845  * drives the transcoder clock.
1846  */
1847 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1848 {
1849         struct drm_device *dev = crtc->base.dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1852
1853         if (WARN_ON(pll == NULL))
1854                 return;
1855
1856         if (WARN_ON(pll->config.crtc_mask == 0))
1857                 return;
1858
1859         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860                       pll->name, pll->active, pll->on,
1861                       crtc->base.base.id);
1862
1863         if (pll->active++) {
1864                 WARN_ON(!pll->on);
1865                 assert_shared_dpll_enabled(dev_priv, pll);
1866                 return;
1867         }
1868         WARN_ON(pll->on);
1869
1870         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
1872         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873         pll->enable(dev_priv, pll);
1874         pll->on = true;
1875 }
1876
1877 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1878 {
1879         struct drm_device *dev = crtc->base.dev;
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1882
1883         /* PCH only available on ILK+ */
1884         BUG_ON(INTEL_INFO(dev)->gen < 5);
1885         if (WARN_ON(pll == NULL))
1886                return;
1887
1888         if (WARN_ON(pll->config.crtc_mask == 0))
1889                 return;
1890
1891         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892                       pll->name, pll->active, pll->on,
1893                       crtc->base.base.id);
1894
1895         if (WARN_ON(pll->active == 0)) {
1896                 assert_shared_dpll_disabled(dev_priv, pll);
1897                 return;
1898         }
1899
1900         assert_shared_dpll_enabled(dev_priv, pll);
1901         WARN_ON(!pll->on);
1902         if (--pll->active)
1903                 return;
1904
1905         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906         pll->disable(dev_priv, pll);
1907         pll->on = false;
1908
1909         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1910 }
1911
1912 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913                                            enum pipe pipe)
1914 {
1915         struct drm_device *dev = dev_priv->dev;
1916         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918         uint32_t reg, val, pipeconf_val;
1919
1920         /* PCH only available on ILK+ */
1921         BUG_ON(!HAS_PCH_SPLIT(dev));
1922
1923         /* Make sure PCH DPLL is enabled */
1924         assert_shared_dpll_enabled(dev_priv,
1925                                    intel_crtc_to_shared_dpll(intel_crtc));
1926
1927         /* FDI must be feeding us bits for PCH ports */
1928         assert_fdi_tx_enabled(dev_priv, pipe);
1929         assert_fdi_rx_enabled(dev_priv, pipe);
1930
1931         if (HAS_PCH_CPT(dev)) {
1932                 /* Workaround: Set the timing override bit before enabling the
1933                  * pch transcoder. */
1934                 reg = TRANS_CHICKEN2(pipe);
1935                 val = I915_READ(reg);
1936                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937                 I915_WRITE(reg, val);
1938         }
1939
1940         reg = PCH_TRANSCONF(pipe);
1941         val = I915_READ(reg);
1942         pipeconf_val = I915_READ(PIPECONF(pipe));
1943
1944         if (HAS_PCH_IBX(dev_priv->dev)) {
1945                 /*
1946                  * make the BPC in transcoder be consistent with
1947                  * that in pipeconf reg.
1948                  */
1949                 val &= ~PIPECONF_BPC_MASK;
1950                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1951         }
1952
1953         val &= ~TRANS_INTERLACE_MASK;
1954         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955                 if (HAS_PCH_IBX(dev_priv->dev) &&
1956                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957                         val |= TRANS_LEGACY_INTERLACED_ILK;
1958                 else
1959                         val |= TRANS_INTERLACED;
1960         else
1961                 val |= TRANS_PROGRESSIVE;
1962
1963         I915_WRITE(reg, val | TRANS_ENABLE);
1964         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1966 }
1967
1968 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969                                       enum transcoder cpu_transcoder)
1970 {
1971         u32 val, pipeconf_val;
1972
1973         /* PCH only available on ILK+ */
1974         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1975
1976         /* FDI must be feeding us bits for PCH ports */
1977         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1979
1980         /* Workaround: set timing override bit. */
1981         val = I915_READ(_TRANSA_CHICKEN2);
1982         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983         I915_WRITE(_TRANSA_CHICKEN2, val);
1984
1985         val = TRANS_ENABLE;
1986         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1987
1988         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989             PIPECONF_INTERLACED_ILK)
1990                 val |= TRANS_INTERLACED;
1991         else
1992                 val |= TRANS_PROGRESSIVE;
1993
1994         I915_WRITE(LPT_TRANSCONF, val);
1995         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996                 DRM_ERROR("Failed to enable PCH transcoder\n");
1997 }
1998
1999 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000                                             enum pipe pipe)
2001 {
2002         struct drm_device *dev = dev_priv->dev;
2003         uint32_t reg, val;
2004
2005         /* FDI relies on the transcoder */
2006         assert_fdi_tx_disabled(dev_priv, pipe);
2007         assert_fdi_rx_disabled(dev_priv, pipe);
2008
2009         /* Ports must be off as well */
2010         assert_pch_ports_disabled(dev_priv, pipe);
2011
2012         reg = PCH_TRANSCONF(pipe);
2013         val = I915_READ(reg);
2014         val &= ~TRANS_ENABLE;
2015         I915_WRITE(reg, val);
2016         /* wait for PCH transcoder off, transcoder state */
2017         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2019
2020         if (!HAS_PCH_IBX(dev)) {
2021                 /* Workaround: Clear the timing override chicken bit again. */
2022                 reg = TRANS_CHICKEN2(pipe);
2023                 val = I915_READ(reg);
2024                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025                 I915_WRITE(reg, val);
2026         }
2027 }
2028
2029 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2030 {
2031         u32 val;
2032
2033         val = I915_READ(LPT_TRANSCONF);
2034         val &= ~TRANS_ENABLE;
2035         I915_WRITE(LPT_TRANSCONF, val);
2036         /* wait for PCH transcoder off, transcoder state */
2037         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038                 DRM_ERROR("Failed to disable PCH transcoder\n");
2039
2040         /* Workaround: clear timing override bit. */
2041         val = I915_READ(_TRANSA_CHICKEN2);
2042         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043         I915_WRITE(_TRANSA_CHICKEN2, val);
2044 }
2045
2046 /**
2047  * intel_enable_pipe - enable a pipe, asserting requirements
2048  * @crtc: crtc responsible for the pipe
2049  *
2050  * Enable @crtc's pipe, making sure that various hardware specific requirements
2051  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2052  */
2053 static void intel_enable_pipe(struct intel_crtc *crtc)
2054 {
2055         struct drm_device *dev = crtc->base.dev;
2056         struct drm_i915_private *dev_priv = dev->dev_private;
2057         enum pipe pipe = crtc->pipe;
2058         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059                                                                       pipe);
2060         enum pipe pch_transcoder;
2061         int reg;
2062         u32 val;
2063
2064         assert_planes_disabled(dev_priv, pipe);
2065         assert_cursor_disabled(dev_priv, pipe);
2066         assert_sprites_disabled(dev_priv, pipe);
2067
2068         if (HAS_PCH_LPT(dev_priv->dev))
2069                 pch_transcoder = TRANSCODER_A;
2070         else
2071                 pch_transcoder = pipe;
2072
2073         /*
2074          * A pipe without a PLL won't actually be able to drive bits from
2075          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2076          * need the check.
2077          */
2078         if (!HAS_PCH_SPLIT(dev_priv->dev))
2079                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080                         assert_dsi_pll_enabled(dev_priv);
2081                 else
2082                         assert_pll_enabled(dev_priv, pipe);
2083         else {
2084                 if (crtc->config->has_pch_encoder) {
2085                         /* if driving the PCH, we need FDI enabled */
2086                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087                         assert_fdi_tx_pll_enabled(dev_priv,
2088                                                   (enum pipe) cpu_transcoder);
2089                 }
2090                 /* FIXME: assert CPU port conditions for SNB+ */
2091         }
2092
2093         reg = PIPECONF(cpu_transcoder);
2094         val = I915_READ(reg);
2095         if (val & PIPECONF_ENABLE) {
2096                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2098                 return;
2099         }
2100
2101         I915_WRITE(reg, val | PIPECONF_ENABLE);
2102         POSTING_READ(reg);
2103 }
2104
2105 /**
2106  * intel_disable_pipe - disable a pipe, asserting requirements
2107  * @crtc: crtc whose pipes is to be disabled
2108  *
2109  * Disable the pipe of @crtc, making sure that various hardware
2110  * specific requirements are met, if applicable, e.g. plane
2111  * disabled, panel fitter off, etc.
2112  *
2113  * Will wait until the pipe has shut down before returning.
2114  */
2115 static void intel_disable_pipe(struct intel_crtc *crtc)
2116 {
2117         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119         enum pipe pipe = crtc->pipe;
2120         int reg;
2121         u32 val;
2122
2123         /*
2124          * Make sure planes won't keep trying to pump pixels to us,
2125          * or we might hang the display.
2126          */
2127         assert_planes_disabled(dev_priv, pipe);
2128         assert_cursor_disabled(dev_priv, pipe);
2129         assert_sprites_disabled(dev_priv, pipe);
2130
2131         reg = PIPECONF(cpu_transcoder);
2132         val = I915_READ(reg);
2133         if ((val & PIPECONF_ENABLE) == 0)
2134                 return;
2135
2136         /*
2137          * Double wide has implications for planes
2138          * so best keep it disabled when not needed.
2139          */
2140         if (crtc->config->double_wide)
2141                 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143         /* Don't disable pipe or pipe PLLs if needed */
2144         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146                 val &= ~PIPECONF_ENABLE;
2147
2148         I915_WRITE(reg, val);
2149         if ((val & PIPECONF_ENABLE) == 0)
2150                 intel_wait_for_pipe_off(crtc);
2151 }
2152
2153 /*
2154  * Plane regs are double buffered, going from enabled->disabled needs a
2155  * trigger in order to latch.  The display address reg provides this.
2156  */
2157 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158                                enum plane plane)
2159 {
2160         struct drm_device *dev = dev_priv->dev;
2161         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2162
2163         I915_WRITE(reg, I915_READ(reg));
2164         POSTING_READ(reg);
2165 }
2166
2167 /**
2168  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169  * @plane:  plane to be enabled
2170  * @crtc: crtc for the plane
2171  *
2172  * Enable @plane on @crtc, making sure that the pipe is running first.
2173  */
2174 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175                                           struct drm_crtc *crtc)
2176 {
2177         struct drm_device *dev = plane->dev;
2178         struct drm_i915_private *dev_priv = dev->dev_private;
2179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2183
2184         if (intel_crtc->primary_enabled)
2185                 return;
2186
2187         intel_crtc->primary_enabled = true;
2188
2189         dev_priv->display.update_primary_plane(crtc, plane->fb,
2190                                                crtc->x, crtc->y);
2191
2192         /*
2193          * BDW signals flip done immediately if the plane
2194          * is disabled, even if the plane enable is already
2195          * armed to occur at the next vblank :(
2196          */
2197         if (IS_BROADWELL(dev))
2198                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2199 }
2200
2201 /**
2202  * intel_disable_primary_hw_plane - disable the primary hardware plane
2203  * @plane: plane to be disabled
2204  * @crtc: crtc for the plane
2205  *
2206  * Disable @plane on @crtc, making sure that the pipe is running first.
2207  */
2208 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209                                            struct drm_crtc *crtc)
2210 {
2211         struct drm_device *dev = plane->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
2215         if (WARN_ON(!intel_crtc->active))
2216                 return;
2217
2218         if (!intel_crtc->primary_enabled)
2219                 return;
2220
2221         intel_crtc->primary_enabled = false;
2222
2223         dev_priv->display.update_primary_plane(crtc, plane->fb,
2224                                                crtc->x, crtc->y);
2225 }
2226
2227 static bool need_vtd_wa(struct drm_device *dev)
2228 {
2229 #ifdef CONFIG_INTEL_IOMMU
2230         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231                 return true;
2232 #endif
2233         return false;
2234 }
2235
2236 unsigned int
2237 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238                   uint64_t fb_format_modifier)
2239 {
2240         unsigned int tile_height;
2241         uint32_t pixel_bytes;
2242
2243         switch (fb_format_modifier) {
2244         case DRM_FORMAT_MOD_NONE:
2245                 tile_height = 1;
2246                 break;
2247         case I915_FORMAT_MOD_X_TILED:
2248                 tile_height = IS_GEN2(dev) ? 16 : 8;
2249                 break;
2250         case I915_FORMAT_MOD_Y_TILED:
2251                 tile_height = 32;
2252                 break;
2253         case I915_FORMAT_MOD_Yf_TILED:
2254                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255                 switch (pixel_bytes) {
2256                 default:
2257                 case 1:
2258                         tile_height = 64;
2259                         break;
2260                 case 2:
2261                 case 4:
2262                         tile_height = 32;
2263                         break;
2264                 case 8:
2265                         tile_height = 16;
2266                         break;
2267                 case 16:
2268                         WARN_ONCE(1,
2269                                   "128-bit pixels are not supported for display!");
2270                         tile_height = 16;
2271                         break;
2272                 }
2273                 break;
2274         default:
2275                 MISSING_CASE(fb_format_modifier);
2276                 tile_height = 1;
2277                 break;
2278         }
2279
2280         return tile_height;
2281 }
2282
2283 unsigned int
2284 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285                       uint32_t pixel_format, uint64_t fb_format_modifier)
2286 {
2287         return ALIGN(height, intel_tile_height(dev, pixel_format,
2288                                                fb_format_modifier));
2289 }
2290
2291 static int
2292 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293                         const struct drm_plane_state *plane_state)
2294 {
2295         struct intel_rotation_info *info = &view->rotation_info;
2296         static const struct i915_ggtt_view rotated_view =
2297                                 { .type = I915_GGTT_VIEW_ROTATED };
2298
2299         *view = i915_ggtt_view_normal;
2300
2301         if (!plane_state)
2302                 return 0;
2303
2304         if (!intel_rotation_90_or_270(plane_state->rotation))
2305                 return 0;
2306
2307         *view = rotated_view;
2308
2309         info->height = fb->height;
2310         info->pixel_format = fb->pixel_format;
2311         info->pitch = fb->pitches[0];
2312         info->fb_modifier = fb->modifier[0];
2313
2314         if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2315               info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2316                 DRM_DEBUG_KMS(
2317                               "Y or Yf tiling is needed for 90/270 rotation!\n");
2318                 return -EINVAL;
2319         }
2320
2321         return 0;
2322 }
2323
2324 int
2325 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326                            struct drm_framebuffer *fb,
2327                            const struct drm_plane_state *plane_state,
2328                            struct intel_engine_cs *pipelined)
2329 {
2330         struct drm_device *dev = fb->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2333         struct i915_ggtt_view view;
2334         u32 alignment;
2335         int ret;
2336
2337         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
2339         switch (fb->modifier[0]) {
2340         case DRM_FORMAT_MOD_NONE:
2341                 if (INTEL_INFO(dev)->gen >= 9)
2342                         alignment = 256 * 1024;
2343                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2344                         alignment = 128 * 1024;
2345                 else if (INTEL_INFO(dev)->gen >= 4)
2346                         alignment = 4 * 1024;
2347                 else
2348                         alignment = 64 * 1024;
2349                 break;
2350         case I915_FORMAT_MOD_X_TILED:
2351                 if (INTEL_INFO(dev)->gen >= 9)
2352                         alignment = 256 * 1024;
2353                 else {
2354                         /* pin() will align the object as required by fence */
2355                         alignment = 0;
2356                 }
2357                 break;
2358         case I915_FORMAT_MOD_Y_TILED:
2359         case I915_FORMAT_MOD_Yf_TILED:
2360                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361                           "Y tiling bo slipped through, driver bug!\n"))
2362                         return -EINVAL;
2363                 alignment = 1 * 1024 * 1024;
2364                 break;
2365         default:
2366                 MISSING_CASE(fb->modifier[0]);
2367                 return -EINVAL;
2368         }
2369
2370         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371         if (ret)
2372                 return ret;
2373
2374         /* Note that the w/a also requires 64 PTE of padding following the
2375          * bo. We currently fill all unused PTE with the shadow page and so
2376          * we should always have valid PTE following the scanout preventing
2377          * the VT-d warning.
2378          */
2379         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380                 alignment = 256 * 1024;
2381
2382         /*
2383          * Global gtt pte registers are special registers which actually forward
2384          * writes to a chunk of system memory. Which means that there is no risk
2385          * that the register values disappear as soon as we call
2386          * intel_runtime_pm_put(), so it is correct to wrap only the
2387          * pin/unpin/fence and not more.
2388          */
2389         intel_runtime_pm_get(dev_priv);
2390
2391         dev_priv->mm.interruptible = false;
2392         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2393                                                    &view);
2394         if (ret)
2395                 goto err_interruptible;
2396
2397         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398          * fence, whereas 965+ only requires a fence if using
2399          * framebuffer compression.  For simplicity, we always install
2400          * a fence as the cost is not that onerous.
2401          */
2402         ret = i915_gem_object_get_fence(obj);
2403         if (ret)
2404                 goto err_unpin;
2405
2406         i915_gem_object_pin_fence(obj);
2407
2408         dev_priv->mm.interruptible = true;
2409         intel_runtime_pm_put(dev_priv);
2410         return 0;
2411
2412 err_unpin:
2413         i915_gem_object_unpin_from_display_plane(obj, &view);
2414 err_interruptible:
2415         dev_priv->mm.interruptible = true;
2416         intel_runtime_pm_put(dev_priv);
2417         return ret;
2418 }
2419
2420 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421                                const struct drm_plane_state *plane_state)
2422 {
2423         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2424         struct i915_ggtt_view view;
2425         int ret;
2426
2427         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
2429         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430         WARN_ONCE(ret, "Couldn't get view from plane state!");
2431
2432         i915_gem_object_unpin_fence(obj);
2433         i915_gem_object_unpin_from_display_plane(obj, &view);
2434 }
2435
2436 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437  * is assumed to be a power-of-two. */
2438 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439                                              unsigned int tiling_mode,
2440                                              unsigned int cpp,
2441                                              unsigned int pitch)
2442 {
2443         if (tiling_mode != I915_TILING_NONE) {
2444                 unsigned int tile_rows, tiles;
2445
2446                 tile_rows = *y / 8;
2447                 *y %= 8;
2448
2449                 tiles = *x / (512/cpp);
2450                 *x %= 512/cpp;
2451
2452                 return tile_rows * pitch * 8 + tiles * 4096;
2453         } else {
2454                 unsigned int offset;
2455
2456                 offset = *y * pitch + *x * cpp;
2457                 *y = 0;
2458                 *x = (offset & 4095) / cpp;
2459                 return offset & -4096;
2460         }
2461 }
2462
2463 static int i9xx_format_to_fourcc(int format)
2464 {
2465         switch (format) {
2466         case DISPPLANE_8BPP:
2467                 return DRM_FORMAT_C8;
2468         case DISPPLANE_BGRX555:
2469                 return DRM_FORMAT_XRGB1555;
2470         case DISPPLANE_BGRX565:
2471                 return DRM_FORMAT_RGB565;
2472         default:
2473         case DISPPLANE_BGRX888:
2474                 return DRM_FORMAT_XRGB8888;
2475         case DISPPLANE_RGBX888:
2476                 return DRM_FORMAT_XBGR8888;
2477         case DISPPLANE_BGRX101010:
2478                 return DRM_FORMAT_XRGB2101010;
2479         case DISPPLANE_RGBX101010:
2480                 return DRM_FORMAT_XBGR2101010;
2481         }
2482 }
2483
2484 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485 {
2486         switch (format) {
2487         case PLANE_CTL_FORMAT_RGB_565:
2488                 return DRM_FORMAT_RGB565;
2489         default:
2490         case PLANE_CTL_FORMAT_XRGB_8888:
2491                 if (rgb_order) {
2492                         if (alpha)
2493                                 return DRM_FORMAT_ABGR8888;
2494                         else
2495                                 return DRM_FORMAT_XBGR8888;
2496                 } else {
2497                         if (alpha)
2498                                 return DRM_FORMAT_ARGB8888;
2499                         else
2500                                 return DRM_FORMAT_XRGB8888;
2501                 }
2502         case PLANE_CTL_FORMAT_XRGB_2101010:
2503                 if (rgb_order)
2504                         return DRM_FORMAT_XBGR2101010;
2505                 else
2506                         return DRM_FORMAT_XRGB2101010;
2507         }
2508 }
2509
2510 static bool
2511 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512                               struct intel_initial_plane_config *plane_config)
2513 {
2514         struct drm_device *dev = crtc->base.dev;
2515         struct drm_i915_gem_object *obj = NULL;
2516         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2517         struct drm_framebuffer *fb = &plane_config->fb->base;
2518         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2520                                     PAGE_SIZE);
2521
2522         size_aligned -= base_aligned;
2523
2524         if (plane_config->size == 0)
2525                 return false;
2526
2527         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528                                                              base_aligned,
2529                                                              base_aligned,
2530                                                              size_aligned);
2531         if (!obj)
2532                 return false;
2533
2534         obj->tiling_mode = plane_config->tiling;
2535         if (obj->tiling_mode == I915_TILING_X)
2536                 obj->stride = fb->pitches[0];
2537
2538         mode_cmd.pixel_format = fb->pixel_format;
2539         mode_cmd.width = fb->width;
2540         mode_cmd.height = fb->height;
2541         mode_cmd.pitches[0] = fb->pitches[0];
2542         mode_cmd.modifier[0] = fb->modifier[0];
2543         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2544
2545         mutex_lock(&dev->struct_mutex);
2546
2547         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2548                                    &mode_cmd, obj)) {
2549                 DRM_DEBUG_KMS("intel fb init failed\n");
2550                 goto out_unref_obj;
2551         }
2552
2553         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2554         mutex_unlock(&dev->struct_mutex);
2555
2556         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2557         return true;
2558
2559 out_unref_obj:
2560         drm_gem_object_unreference(&obj->base);
2561         mutex_unlock(&dev->struct_mutex);
2562         return false;
2563 }
2564
2565 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2566 static void
2567 update_state_fb(struct drm_plane *plane)
2568 {
2569         if (plane->fb == plane->state->fb)
2570                 return;
2571
2572         if (plane->state->fb)
2573                 drm_framebuffer_unreference(plane->state->fb);
2574         plane->state->fb = plane->fb;
2575         if (plane->state->fb)
2576                 drm_framebuffer_reference(plane->state->fb);
2577 }
2578
2579 static void
2580 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2581                              struct intel_initial_plane_config *plane_config)
2582 {
2583         struct drm_device *dev = intel_crtc->base.dev;
2584         struct drm_i915_private *dev_priv = dev->dev_private;
2585         struct drm_crtc *c;
2586         struct intel_crtc *i;
2587         struct drm_i915_gem_object *obj;
2588
2589         if (!plane_config->fb)
2590                 return;
2591
2592         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2593                 struct drm_plane *primary = intel_crtc->base.primary;
2594
2595                 primary->fb = &plane_config->fb->base;
2596                 primary->state->crtc = &intel_crtc->base;
2597                 primary->crtc = &intel_crtc->base;
2598                 update_state_fb(primary);
2599
2600                 return;
2601         }
2602
2603         kfree(plane_config->fb);
2604
2605         /*
2606          * Failed to alloc the obj, check to see if we should share
2607          * an fb with another CRTC instead
2608          */
2609         for_each_crtc(dev, c) {
2610                 i = to_intel_crtc(c);
2611
2612                 if (c == &intel_crtc->base)
2613                         continue;
2614
2615                 if (!i->active)
2616                         continue;
2617
2618                 obj = intel_fb_obj(c->primary->fb);
2619                 if (obj == NULL)
2620                         continue;
2621
2622                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2623                         struct drm_plane *primary = intel_crtc->base.primary;
2624
2625                         if (obj->tiling_mode != I915_TILING_NONE)
2626                                 dev_priv->preserve_bios_swizzle = true;
2627
2628                         drm_framebuffer_reference(c->primary->fb);
2629                         primary->fb = c->primary->fb;
2630                         primary->state->crtc = &intel_crtc->base;
2631                         primary->crtc = &intel_crtc->base;
2632                         update_state_fb(intel_crtc->base.primary);
2633                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2634                         break;
2635                 }
2636         }
2637 }
2638
2639 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2640                                       struct drm_framebuffer *fb,
2641                                       int x, int y)
2642 {
2643         struct drm_device *dev = crtc->dev;
2644         struct drm_i915_private *dev_priv = dev->dev_private;
2645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646         struct drm_i915_gem_object *obj;
2647         int plane = intel_crtc->plane;
2648         unsigned long linear_offset;
2649         u32 dspcntr;
2650         u32 reg = DSPCNTR(plane);
2651         int pixel_size;
2652
2653         if (!intel_crtc->primary_enabled) {
2654                 I915_WRITE(reg, 0);
2655                 if (INTEL_INFO(dev)->gen >= 4)
2656                         I915_WRITE(DSPSURF(plane), 0);
2657                 else
2658                         I915_WRITE(DSPADDR(plane), 0);
2659                 POSTING_READ(reg);
2660                 return;
2661         }
2662
2663         obj = intel_fb_obj(fb);
2664         if (WARN_ON(obj == NULL))
2665                 return;
2666
2667         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2668
2669         dspcntr = DISPPLANE_GAMMA_ENABLE;
2670
2671         dspcntr |= DISPLAY_PLANE_ENABLE;
2672
2673         if (INTEL_INFO(dev)->gen < 4) {
2674                 if (intel_crtc->pipe == PIPE_B)
2675                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2676
2677                 /* pipesrc and dspsize control the size that is scaled from,
2678                  * which should always be the user's requested size.
2679                  */
2680                 I915_WRITE(DSPSIZE(plane),
2681                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2682                            (intel_crtc->config->pipe_src_w - 1));
2683                 I915_WRITE(DSPPOS(plane), 0);
2684         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2685                 I915_WRITE(PRIMSIZE(plane),
2686                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2687                            (intel_crtc->config->pipe_src_w - 1));
2688                 I915_WRITE(PRIMPOS(plane), 0);
2689                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2690         }
2691
2692         switch (fb->pixel_format) {
2693         case DRM_FORMAT_C8:
2694                 dspcntr |= DISPPLANE_8BPP;
2695                 break;
2696         case DRM_FORMAT_XRGB1555:
2697         case DRM_FORMAT_ARGB1555:
2698                 dspcntr |= DISPPLANE_BGRX555;
2699                 break;
2700         case DRM_FORMAT_RGB565:
2701                 dspcntr |= DISPPLANE_BGRX565;
2702                 break;
2703         case DRM_FORMAT_XRGB8888:
2704         case DRM_FORMAT_ARGB8888:
2705                 dspcntr |= DISPPLANE_BGRX888;
2706                 break;
2707         case DRM_FORMAT_XBGR8888:
2708         case DRM_FORMAT_ABGR8888:
2709                 dspcntr |= DISPPLANE_RGBX888;
2710                 break;
2711         case DRM_FORMAT_XRGB2101010:
2712         case DRM_FORMAT_ARGB2101010:
2713                 dspcntr |= DISPPLANE_BGRX101010;
2714                 break;
2715         case DRM_FORMAT_XBGR2101010:
2716         case DRM_FORMAT_ABGR2101010:
2717                 dspcntr |= DISPPLANE_RGBX101010;
2718                 break;
2719         default:
2720                 BUG();
2721         }
2722
2723         if (INTEL_INFO(dev)->gen >= 4 &&
2724             obj->tiling_mode != I915_TILING_NONE)
2725                 dspcntr |= DISPPLANE_TILED;
2726
2727         if (IS_G4X(dev))
2728                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2729
2730         linear_offset = y * fb->pitches[0] + x * pixel_size;
2731
2732         if (INTEL_INFO(dev)->gen >= 4) {
2733                 intel_crtc->dspaddr_offset =
2734                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2735                                                        pixel_size,
2736                                                        fb->pitches[0]);
2737                 linear_offset -= intel_crtc->dspaddr_offset;
2738         } else {
2739                 intel_crtc->dspaddr_offset = linear_offset;
2740         }
2741
2742         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2743                 dspcntr |= DISPPLANE_ROTATE_180;
2744
2745                 x += (intel_crtc->config->pipe_src_w - 1);
2746                 y += (intel_crtc->config->pipe_src_h - 1);
2747
2748                 /* Finding the last pixel of the last line of the display
2749                 data and adding to linear_offset*/
2750                 linear_offset +=
2751                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2752                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2753         }
2754
2755         I915_WRITE(reg, dspcntr);
2756
2757         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2758         if (INTEL_INFO(dev)->gen >= 4) {
2759                 I915_WRITE(DSPSURF(plane),
2760                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2761                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2762                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2763         } else
2764                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2765         POSTING_READ(reg);
2766 }
2767
2768 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2769                                           struct drm_framebuffer *fb,
2770                                           int x, int y)
2771 {
2772         struct drm_device *dev = crtc->dev;
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2775         struct drm_i915_gem_object *obj;
2776         int plane = intel_crtc->plane;
2777         unsigned long linear_offset;
2778         u32 dspcntr;
2779         u32 reg = DSPCNTR(plane);
2780         int pixel_size;
2781
2782         if (!intel_crtc->primary_enabled) {
2783                 I915_WRITE(reg, 0);
2784                 I915_WRITE(DSPSURF(plane), 0);
2785                 POSTING_READ(reg);
2786                 return;
2787         }
2788
2789         obj = intel_fb_obj(fb);
2790         if (WARN_ON(obj == NULL))
2791                 return;
2792
2793         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
2795         dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
2797         dspcntr |= DISPLAY_PLANE_ENABLE;
2798
2799         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2801
2802         switch (fb->pixel_format) {
2803         case DRM_FORMAT_C8:
2804                 dspcntr |= DISPPLANE_8BPP;
2805                 break;
2806         case DRM_FORMAT_RGB565:
2807                 dspcntr |= DISPPLANE_BGRX565;
2808                 break;
2809         case DRM_FORMAT_XRGB8888:
2810         case DRM_FORMAT_ARGB8888:
2811                 dspcntr |= DISPPLANE_BGRX888;
2812                 break;
2813         case DRM_FORMAT_XBGR8888:
2814         case DRM_FORMAT_ABGR8888:
2815                 dspcntr |= DISPPLANE_RGBX888;
2816                 break;
2817         case DRM_FORMAT_XRGB2101010:
2818         case DRM_FORMAT_ARGB2101010:
2819                 dspcntr |= DISPPLANE_BGRX101010;
2820                 break;
2821         case DRM_FORMAT_XBGR2101010:
2822         case DRM_FORMAT_ABGR2101010:
2823                 dspcntr |= DISPPLANE_RGBX101010;
2824                 break;
2825         default:
2826                 BUG();
2827         }
2828
2829         if (obj->tiling_mode != I915_TILING_NONE)
2830                 dspcntr |= DISPPLANE_TILED;
2831
2832         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2833                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2834
2835         linear_offset = y * fb->pitches[0] + x * pixel_size;
2836         intel_crtc->dspaddr_offset =
2837                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2838                                                pixel_size,
2839                                                fb->pitches[0]);
2840         linear_offset -= intel_crtc->dspaddr_offset;
2841         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2842                 dspcntr |= DISPPLANE_ROTATE_180;
2843
2844                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2845                         x += (intel_crtc->config->pipe_src_w - 1);
2846                         y += (intel_crtc->config->pipe_src_h - 1);
2847
2848                         /* Finding the last pixel of the last line of the display
2849                         data and adding to linear_offset*/
2850                         linear_offset +=
2851                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2852                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2853                 }
2854         }
2855
2856         I915_WRITE(reg, dspcntr);
2857
2858         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2859         I915_WRITE(DSPSURF(plane),
2860                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2861         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2862                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2863         } else {
2864                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2865                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2866         }
2867         POSTING_READ(reg);
2868 }
2869
2870 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2871                               uint32_t pixel_format)
2872 {
2873         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2874
2875         /*
2876          * The stride is either expressed as a multiple of 64 bytes
2877          * chunks for linear buffers or in number of tiles for tiled
2878          * buffers.
2879          */
2880         switch (fb_modifier) {
2881         case DRM_FORMAT_MOD_NONE:
2882                 return 64;
2883         case I915_FORMAT_MOD_X_TILED:
2884                 if (INTEL_INFO(dev)->gen == 2)
2885                         return 128;
2886                 return 512;
2887         case I915_FORMAT_MOD_Y_TILED:
2888                 /* No need to check for old gens and Y tiling since this is
2889                  * about the display engine and those will be blocked before
2890                  * we get here.
2891                  */
2892                 return 128;
2893         case I915_FORMAT_MOD_Yf_TILED:
2894                 if (bits_per_pixel == 8)
2895                         return 64;
2896                 else
2897                         return 128;
2898         default:
2899                 MISSING_CASE(fb_modifier);
2900                 return 64;
2901         }
2902 }
2903
2904 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2905                                      struct drm_i915_gem_object *obj)
2906 {
2907         enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2908
2909         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2910                 view = I915_GGTT_VIEW_ROTATED;
2911
2912         return i915_gem_obj_ggtt_offset_view(obj, view);
2913 }
2914
2915 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2916                                          struct drm_framebuffer *fb,
2917                                          int x, int y)
2918 {
2919         struct drm_device *dev = crtc->dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922         struct drm_i915_gem_object *obj;
2923         int pipe = intel_crtc->pipe;
2924         u32 plane_ctl, stride_div;
2925         unsigned long surf_addr;
2926
2927         if (!intel_crtc->primary_enabled) {
2928                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2929                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2930                 POSTING_READ(PLANE_CTL(pipe, 0));
2931                 return;
2932         }
2933
2934         plane_ctl = PLANE_CTL_ENABLE |
2935                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2936                     PLANE_CTL_PIPE_CSC_ENABLE;
2937
2938         switch (fb->pixel_format) {
2939         case DRM_FORMAT_RGB565:
2940                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2941                 break;
2942         case DRM_FORMAT_XRGB8888:
2943                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2944                 break;
2945         case DRM_FORMAT_ARGB8888:
2946                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2947                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2948                 break;
2949         case DRM_FORMAT_XBGR8888:
2950                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2951                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2952                 break;
2953         case DRM_FORMAT_ABGR8888:
2954                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2955                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2956                 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2957                 break;
2958         case DRM_FORMAT_XRGB2101010:
2959                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2960                 break;
2961         case DRM_FORMAT_XBGR2101010:
2962                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2963                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2964                 break;
2965         default:
2966                 BUG();
2967         }
2968
2969         switch (fb->modifier[0]) {
2970         case DRM_FORMAT_MOD_NONE:
2971                 break;
2972         case I915_FORMAT_MOD_X_TILED:
2973                 plane_ctl |= PLANE_CTL_TILED_X;
2974                 break;
2975         case I915_FORMAT_MOD_Y_TILED:
2976                 plane_ctl |= PLANE_CTL_TILED_Y;
2977                 break;
2978         case I915_FORMAT_MOD_Yf_TILED:
2979                 plane_ctl |= PLANE_CTL_TILED_YF;
2980                 break;
2981         default:
2982                 MISSING_CASE(fb->modifier[0]);
2983         }
2984
2985         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2986         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2987                 plane_ctl |= PLANE_CTL_ROTATE_180;
2988
2989         obj = intel_fb_obj(fb);
2990         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2991                                                fb->pixel_format);
2992         surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
2993
2994         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2995         I915_WRITE(PLANE_POS(pipe, 0), 0);
2996         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2997         I915_WRITE(PLANE_SIZE(pipe, 0),
2998                    (intel_crtc->config->pipe_src_h - 1) << 16 |
2999                    (intel_crtc->config->pipe_src_w - 1));
3000         I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
3001         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3002
3003         POSTING_READ(PLANE_SURF(pipe, 0));
3004 }
3005
3006 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3007 static int
3008 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3009                            int x, int y, enum mode_set_atomic state)
3010 {
3011         struct drm_device *dev = crtc->dev;
3012         struct drm_i915_private *dev_priv = dev->dev_private;
3013
3014         if (dev_priv->display.disable_fbc)
3015                 dev_priv->display.disable_fbc(dev);
3016
3017         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3018
3019         return 0;
3020 }
3021
3022 static void intel_complete_page_flips(struct drm_device *dev)
3023 {
3024         struct drm_crtc *crtc;
3025
3026         for_each_crtc(dev, crtc) {
3027                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028                 enum plane plane = intel_crtc->plane;
3029
3030                 intel_prepare_page_flip(dev, plane);
3031                 intel_finish_page_flip_plane(dev, plane);
3032         }
3033 }
3034
3035 static void intel_update_primary_planes(struct drm_device *dev)
3036 {
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         struct drm_crtc *crtc;
3039
3040         for_each_crtc(dev, crtc) {
3041                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042
3043                 drm_modeset_lock(&crtc->mutex, NULL);
3044                 /*
3045                  * FIXME: Once we have proper support for primary planes (and
3046                  * disabling them without disabling the entire crtc) allow again
3047                  * a NULL crtc->primary->fb.
3048                  */
3049                 if (intel_crtc->active && crtc->primary->fb)
3050                         dev_priv->display.update_primary_plane(crtc,
3051                                                                crtc->primary->fb,
3052                                                                crtc->x,
3053                                                                crtc->y);
3054                 drm_modeset_unlock(&crtc->mutex);
3055         }
3056 }
3057
3058 void intel_prepare_reset(struct drm_device *dev)
3059 {
3060         struct drm_i915_private *dev_priv = to_i915(dev);
3061         struct intel_crtc *crtc;
3062
3063         /* no reset support for gen2 */
3064         if (IS_GEN2(dev))
3065                 return;
3066
3067         /* reset doesn't touch the display */
3068         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3069                 return;
3070
3071         drm_modeset_lock_all(dev);
3072
3073         /*
3074          * Disabling the crtcs gracefully seems nicer. Also the
3075          * g33 docs say we should at least disable all the planes.
3076          */
3077         for_each_intel_crtc(dev, crtc) {
3078                 if (crtc->active)
3079                         dev_priv->display.crtc_disable(&crtc->base);
3080         }
3081 }
3082
3083 void intel_finish_reset(struct drm_device *dev)
3084 {
3085         struct drm_i915_private *dev_priv = to_i915(dev);
3086
3087         /*
3088          * Flips in the rings will be nuked by the reset,
3089          * so complete all pending flips so that user space
3090          * will get its events and not get stuck.
3091          */
3092         intel_complete_page_flips(dev);
3093
3094         /* no reset support for gen2 */
3095         if (IS_GEN2(dev))
3096                 return;
3097
3098         /* reset doesn't touch the display */
3099         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3100                 /*
3101                  * Flips in the rings have been nuked by the reset,
3102                  * so update the base address of all primary
3103                  * planes to the the last fb to make sure we're
3104                  * showing the correct fb after a reset.
3105                  */
3106                 intel_update_primary_planes(dev);
3107                 return;
3108         }
3109
3110         /*
3111          * The display has been reset as well,
3112          * so need a full re-initialization.
3113          */
3114         intel_runtime_pm_disable_interrupts(dev_priv);
3115         intel_runtime_pm_enable_interrupts(dev_priv);
3116
3117         intel_modeset_init_hw(dev);
3118
3119         spin_lock_irq(&dev_priv->irq_lock);
3120         if (dev_priv->display.hpd_irq_setup)
3121                 dev_priv->display.hpd_irq_setup(dev);
3122         spin_unlock_irq(&dev_priv->irq_lock);
3123
3124         intel_modeset_setup_hw_state(dev, true);
3125
3126         intel_hpd_init(dev_priv);
3127
3128         drm_modeset_unlock_all(dev);
3129 }
3130
3131 static int
3132 intel_finish_fb(struct drm_framebuffer *old_fb)
3133 {
3134         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3135         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3136         bool was_interruptible = dev_priv->mm.interruptible;
3137         int ret;
3138
3139         /* Big Hammer, we also need to ensure that any pending
3140          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3141          * current scanout is retired before unpinning the old
3142          * framebuffer.
3143          *
3144          * This should only fail upon a hung GPU, in which case we
3145          * can safely continue.
3146          */
3147         dev_priv->mm.interruptible = false;
3148         ret = i915_gem_object_finish_gpu(obj);
3149         dev_priv->mm.interruptible = was_interruptible;
3150
3151         return ret;
3152 }
3153
3154 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3155 {
3156         struct drm_device *dev = crtc->dev;
3157         struct drm_i915_private *dev_priv = dev->dev_private;
3158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3159         bool pending;
3160
3161         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3162             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3163                 return false;
3164
3165         spin_lock_irq(&dev->event_lock);
3166         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3167         spin_unlock_irq(&dev->event_lock);
3168
3169         return pending;
3170 }
3171
3172 static void intel_update_pipe_size(struct intel_crtc *crtc)
3173 {
3174         struct drm_device *dev = crtc->base.dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         const struct drm_display_mode *adjusted_mode;
3177
3178         if (!i915.fastboot)
3179                 return;
3180
3181         /*
3182          * Update pipe size and adjust fitter if needed: the reason for this is
3183          * that in compute_mode_changes we check the native mode (not the pfit
3184          * mode) to see if we can flip rather than do a full mode set. In the
3185          * fastboot case, we'll flip, but if we don't update the pipesrc and
3186          * pfit state, we'll end up with a big fb scanned out into the wrong
3187          * sized surface.
3188          *
3189          * To fix this properly, we need to hoist the checks up into
3190          * compute_mode_changes (or above), check the actual pfit state and
3191          * whether the platform allows pfit disable with pipe active, and only
3192          * then update the pipesrc and pfit state, even on the flip path.
3193          */
3194
3195         adjusted_mode = &crtc->config->base.adjusted_mode;
3196
3197         I915_WRITE(PIPESRC(crtc->pipe),
3198                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3199                    (adjusted_mode->crtc_vdisplay - 1));
3200         if (!crtc->config->pch_pfit.enabled &&
3201             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3202              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3203                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3204                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3205                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3206         }
3207         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3208         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3209 }
3210
3211 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3212 {
3213         struct drm_device *dev = crtc->dev;
3214         struct drm_i915_private *dev_priv = dev->dev_private;
3215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216         int pipe = intel_crtc->pipe;
3217         u32 reg, temp;
3218
3219         /* enable normal train */
3220         reg = FDI_TX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (IS_IVYBRIDGE(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3224                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         reg = FDI_RX_CTL(pipe);
3232         temp = I915_READ(reg);
3233         if (HAS_PCH_CPT(dev)) {
3234                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3235                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3236         } else {
3237                 temp &= ~FDI_LINK_TRAIN_NONE;
3238                 temp |= FDI_LINK_TRAIN_NONE;
3239         }
3240         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3241
3242         /* wait one idle pattern time */
3243         POSTING_READ(reg);
3244         udelay(1000);
3245
3246         /* IVB wants error correction enabled */
3247         if (IS_IVYBRIDGE(dev))
3248                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3249                            FDI_FE_ERRC_ENABLE);
3250 }
3251
3252 /* The FDI link training functions for ILK/Ibexpeak. */
3253 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3254 {
3255         struct drm_device *dev = crtc->dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258         int pipe = intel_crtc->pipe;
3259         u32 reg, temp, tries;
3260
3261         /* FDI needs bits from pipe first */
3262         assert_pipe_enabled(dev_priv, pipe);
3263
3264         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3265            for train result */
3266         reg = FDI_RX_IMR(pipe);
3267         temp = I915_READ(reg);
3268         temp &= ~FDI_RX_SYMBOL_LOCK;
3269         temp &= ~FDI_RX_BIT_LOCK;
3270         I915_WRITE(reg, temp);
3271         I915_READ(reg);
3272         udelay(150);
3273
3274         /* enable CPU FDI TX and PCH FDI RX */
3275         reg = FDI_TX_CTL(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3278         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3279         temp &= ~FDI_LINK_TRAIN_NONE;
3280         temp |= FDI_LINK_TRAIN_PATTERN_1;
3281         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3282
3283         reg = FDI_RX_CTL(pipe);
3284         temp = I915_READ(reg);
3285         temp &= ~FDI_LINK_TRAIN_NONE;
3286         temp |= FDI_LINK_TRAIN_PATTERN_1;
3287         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3288
3289         POSTING_READ(reg);
3290         udelay(150);
3291
3292         /* Ironlake workaround, enable clock pointer after FDI enable*/
3293         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3294         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3295                    FDI_RX_PHASE_SYNC_POINTER_EN);
3296
3297         reg = FDI_RX_IIR(pipe);
3298         for (tries = 0; tries < 5; tries++) {
3299                 temp = I915_READ(reg);
3300                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3301
3302                 if ((temp & FDI_RX_BIT_LOCK)) {
3303                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3304                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3305                         break;
3306                 }
3307         }
3308         if (tries == 5)
3309                 DRM_ERROR("FDI train 1 fail!\n");
3310
3311         /* Train 2 */
3312         reg = FDI_TX_CTL(pipe);
3313         temp = I915_READ(reg);
3314         temp &= ~FDI_LINK_TRAIN_NONE;
3315         temp |= FDI_LINK_TRAIN_PATTERN_2;
3316         I915_WRITE(reg, temp);
3317
3318         reg = FDI_RX_CTL(pipe);
3319         temp = I915_READ(reg);
3320         temp &= ~FDI_LINK_TRAIN_NONE;
3321         temp |= FDI_LINK_TRAIN_PATTERN_2;
3322         I915_WRITE(reg, temp);
3323
3324         POSTING_READ(reg);
3325         udelay(150);
3326
3327         reg = FDI_RX_IIR(pipe);
3328         for (tries = 0; tries < 5; tries++) {
3329                 temp = I915_READ(reg);
3330                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332                 if (temp & FDI_RX_SYMBOL_LOCK) {
3333                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3334                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3335                         break;
3336                 }
3337         }
3338         if (tries == 5)
3339                 DRM_ERROR("FDI train 2 fail!\n");
3340
3341         DRM_DEBUG_KMS("FDI train done\n");
3342
3343 }
3344
3345 static const int snb_b_fdi_train_param[] = {
3346         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3347         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3348         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3349         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3350 };
3351
3352 /* The FDI link training functions for SNB/Cougarpoint. */
3353 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3354 {
3355         struct drm_device *dev = crtc->dev;
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3358         int pipe = intel_crtc->pipe;
3359         u32 reg, temp, i, retry;
3360
3361         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3362            for train result */
3363         reg = FDI_RX_IMR(pipe);
3364         temp = I915_READ(reg);
3365         temp &= ~FDI_RX_SYMBOL_LOCK;
3366         temp &= ~FDI_RX_BIT_LOCK;
3367         I915_WRITE(reg, temp);
3368
3369         POSTING_READ(reg);
3370         udelay(150);
3371
3372         /* enable CPU FDI TX and PCH FDI RX */
3373         reg = FDI_TX_CTL(pipe);
3374         temp = I915_READ(reg);
3375         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3376         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3377         temp &= ~FDI_LINK_TRAIN_NONE;
3378         temp |= FDI_LINK_TRAIN_PATTERN_1;
3379         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3380         /* SNB-B */
3381         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3382         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3383
3384         I915_WRITE(FDI_RX_MISC(pipe),
3385                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3386
3387         reg = FDI_RX_CTL(pipe);
3388         temp = I915_READ(reg);
3389         if (HAS_PCH_CPT(dev)) {
3390                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3391                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3392         } else {
3393                 temp &= ~FDI_LINK_TRAIN_NONE;
3394                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3395         }
3396         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3397
3398         POSTING_READ(reg);
3399         udelay(150);
3400
3401         for (i = 0; i < 4; i++) {
3402                 reg = FDI_TX_CTL(pipe);
3403                 temp = I915_READ(reg);
3404                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3405                 temp |= snb_b_fdi_train_param[i];
3406                 I915_WRITE(reg, temp);
3407
3408                 POSTING_READ(reg);
3409                 udelay(500);
3410
3411                 for (retry = 0; retry < 5; retry++) {
3412                         reg = FDI_RX_IIR(pipe);
3413                         temp = I915_READ(reg);
3414                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3415                         if (temp & FDI_RX_BIT_LOCK) {
3416                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3417                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3418                                 break;
3419                         }
3420                         udelay(50);
3421                 }
3422                 if (retry < 5)
3423                         break;
3424         }
3425         if (i == 4)
3426                 DRM_ERROR("FDI train 1 fail!\n");
3427
3428         /* Train 2 */
3429         reg = FDI_TX_CTL(pipe);
3430         temp = I915_READ(reg);
3431         temp &= ~FDI_LINK_TRAIN_NONE;
3432         temp |= FDI_LINK_TRAIN_PATTERN_2;
3433         if (IS_GEN6(dev)) {
3434                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3435                 /* SNB-B */
3436                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3437         }
3438         I915_WRITE(reg, temp);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         if (HAS_PCH_CPT(dev)) {
3443                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3444                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3445         } else {
3446                 temp &= ~FDI_LINK_TRAIN_NONE;
3447                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3448         }
3449         I915_WRITE(reg, temp);
3450
3451         POSTING_READ(reg);
3452         udelay(150);
3453
3454         for (i = 0; i < 4; i++) {
3455                 reg = FDI_TX_CTL(pipe);
3456                 temp = I915_READ(reg);
3457                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3458                 temp |= snb_b_fdi_train_param[i];
3459                 I915_WRITE(reg, temp);
3460
3461                 POSTING_READ(reg);
3462                 udelay(500);
3463
3464                 for (retry = 0; retry < 5; retry++) {
3465                         reg = FDI_RX_IIR(pipe);
3466                         temp = I915_READ(reg);
3467                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3468                         if (temp & FDI_RX_SYMBOL_LOCK) {
3469                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3470                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3471                                 break;
3472                         }
3473                         udelay(50);
3474                 }
3475                 if (retry < 5)
3476                         break;
3477         }
3478         if (i == 4)
3479                 DRM_ERROR("FDI train 2 fail!\n");
3480
3481         DRM_DEBUG_KMS("FDI train done.\n");
3482 }
3483
3484 /* Manual link training for Ivy Bridge A0 parts */
3485 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3486 {
3487         struct drm_device *dev = crtc->dev;
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490         int pipe = intel_crtc->pipe;
3491         u32 reg, temp, i, j;
3492
3493         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3494            for train result */
3495         reg = FDI_RX_IMR(pipe);
3496         temp = I915_READ(reg);
3497         temp &= ~FDI_RX_SYMBOL_LOCK;
3498         temp &= ~FDI_RX_BIT_LOCK;
3499         I915_WRITE(reg, temp);
3500
3501         POSTING_READ(reg);
3502         udelay(150);
3503
3504         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3505                       I915_READ(FDI_RX_IIR(pipe)));
3506
3507         /* Try each vswing and preemphasis setting twice before moving on */
3508         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3509                 /* disable first in case we need to retry */
3510                 reg = FDI_TX_CTL(pipe);
3511                 temp = I915_READ(reg);
3512                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3513                 temp &= ~FDI_TX_ENABLE;
3514                 I915_WRITE(reg, temp);
3515
3516                 reg = FDI_RX_CTL(pipe);
3517                 temp = I915_READ(reg);
3518                 temp &= ~FDI_LINK_TRAIN_AUTO;
3519                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3520                 temp &= ~FDI_RX_ENABLE;
3521                 I915_WRITE(reg, temp);
3522
3523                 /* enable CPU FDI TX and PCH FDI RX */
3524                 reg = FDI_TX_CTL(pipe);
3525                 temp = I915_READ(reg);
3526                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3527                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3528                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3529                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530                 temp |= snb_b_fdi_train_param[j/2];
3531                 temp |= FDI_COMPOSITE_SYNC;
3532                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3533
3534                 I915_WRITE(FDI_RX_MISC(pipe),
3535                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3536
3537                 reg = FDI_RX_CTL(pipe);
3538                 temp = I915_READ(reg);
3539                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3540                 temp |= FDI_COMPOSITE_SYNC;
3541                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3542
3543                 POSTING_READ(reg);
3544                 udelay(1); /* should be 0.5us */
3545
3546                 for (i = 0; i < 4; i++) {
3547                         reg = FDI_RX_IIR(pipe);
3548                         temp = I915_READ(reg);
3549                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550
3551                         if (temp & FDI_RX_BIT_LOCK ||
3552                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3553                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3554                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3555                                               i);
3556                                 break;
3557                         }
3558                         udelay(1); /* should be 0.5us */
3559                 }
3560                 if (i == 4) {
3561                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3562                         continue;
3563                 }
3564
3565                 /* Train 2 */
3566                 reg = FDI_TX_CTL(pipe);
3567                 temp = I915_READ(reg);
3568                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3569                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3570                 I915_WRITE(reg, temp);
3571
3572                 reg = FDI_RX_CTL(pipe);
3573                 temp = I915_READ(reg);
3574                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3575                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3576                 I915_WRITE(reg, temp);
3577
3578                 POSTING_READ(reg);
3579                 udelay(2); /* should be 1.5us */
3580
3581                 for (i = 0; i < 4; i++) {
3582                         reg = FDI_RX_IIR(pipe);
3583                         temp = I915_READ(reg);
3584                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3585
3586                         if (temp & FDI_RX_SYMBOL_LOCK ||
3587                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3588                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3589                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3590                                               i);
3591                                 goto train_done;
3592                         }
3593                         udelay(2); /* should be 1.5us */
3594                 }
3595                 if (i == 4)
3596                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3597         }
3598
3599 train_done:
3600         DRM_DEBUG_KMS("FDI train done.\n");
3601 }
3602
3603 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3604 {
3605         struct drm_device *dev = intel_crtc->base.dev;
3606         struct drm_i915_private *dev_priv = dev->dev_private;
3607         int pipe = intel_crtc->pipe;
3608         u32 reg, temp;
3609
3610
3611         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3612         reg = FDI_RX_CTL(pipe);
3613         temp = I915_READ(reg);
3614         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3615         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3616         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3617         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3618
3619         POSTING_READ(reg);
3620         udelay(200);
3621
3622         /* Switch from Rawclk to PCDclk */
3623         temp = I915_READ(reg);
3624         I915_WRITE(reg, temp | FDI_PCDCLK);
3625
3626         POSTING_READ(reg);
3627         udelay(200);
3628
3629         /* Enable CPU FDI TX PLL, always on for Ironlake */
3630         reg = FDI_TX_CTL(pipe);
3631         temp = I915_READ(reg);
3632         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3633                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3634
3635                 POSTING_READ(reg);
3636                 udelay(100);
3637         }
3638 }
3639
3640 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3641 {
3642         struct drm_device *dev = intel_crtc->base.dev;
3643         struct drm_i915_private *dev_priv = dev->dev_private;
3644         int pipe = intel_crtc->pipe;
3645         u32 reg, temp;
3646
3647         /* Switch from PCDclk to Rawclk */
3648         reg = FDI_RX_CTL(pipe);
3649         temp = I915_READ(reg);
3650         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3651
3652         /* Disable CPU FDI TX PLL */
3653         reg = FDI_TX_CTL(pipe);
3654         temp = I915_READ(reg);
3655         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3656
3657         POSTING_READ(reg);
3658         udelay(100);
3659
3660         reg = FDI_RX_CTL(pipe);
3661         temp = I915_READ(reg);
3662         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3663
3664         /* Wait for the clocks to turn off. */
3665         POSTING_READ(reg);
3666         udelay(100);
3667 }
3668
3669 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3670 {
3671         struct drm_device *dev = crtc->dev;
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3674         int pipe = intel_crtc->pipe;
3675         u32 reg, temp;
3676
3677         /* disable CPU FDI tx and PCH FDI rx */
3678         reg = FDI_TX_CTL(pipe);
3679         temp = I915_READ(reg);
3680         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3681         POSTING_READ(reg);
3682
3683         reg = FDI_RX_CTL(pipe);
3684         temp = I915_READ(reg);
3685         temp &= ~(0x7 << 16);
3686         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3687         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3688
3689         POSTING_READ(reg);
3690         udelay(100);
3691
3692         /* Ironlake workaround, disable clock pointer after downing FDI */
3693         if (HAS_PCH_IBX(dev))
3694                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3695
3696         /* still set train pattern 1 */
3697         reg = FDI_TX_CTL(pipe);
3698         temp = I915_READ(reg);
3699         temp &= ~FDI_LINK_TRAIN_NONE;
3700         temp |= FDI_LINK_TRAIN_PATTERN_1;
3701         I915_WRITE(reg, temp);
3702
3703         reg = FDI_RX_CTL(pipe);
3704         temp = I915_READ(reg);
3705         if (HAS_PCH_CPT(dev)) {
3706                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3707                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3708         } else {
3709                 temp &= ~FDI_LINK_TRAIN_NONE;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3711         }
3712         /* BPC in FDI rx is consistent with that in PIPECONF */
3713         temp &= ~(0x07 << 16);
3714         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3715         I915_WRITE(reg, temp);
3716
3717         POSTING_READ(reg);
3718         udelay(100);
3719 }
3720
3721 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3722 {
3723         struct intel_crtc *crtc;
3724
3725         /* Note that we don't need to be called with mode_config.lock here
3726          * as our list of CRTC objects is static for the lifetime of the
3727          * device and so cannot disappear as we iterate. Similarly, we can
3728          * happily treat the predicates as racy, atomic checks as userspace
3729          * cannot claim and pin a new fb without at least acquring the
3730          * struct_mutex and so serialising with us.
3731          */
3732         for_each_intel_crtc(dev, crtc) {
3733                 if (atomic_read(&crtc->unpin_work_count) == 0)
3734                         continue;
3735
3736                 if (crtc->unpin_work)
3737                         intel_wait_for_vblank(dev, crtc->pipe);
3738
3739                 return true;
3740         }
3741
3742         return false;
3743 }
3744
3745 static void page_flip_completed(struct intel_crtc *intel_crtc)
3746 {
3747         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3748         struct intel_unpin_work *work = intel_crtc->unpin_work;
3749
3750         /* ensure that the unpin work is consistent wrt ->pending. */
3751         smp_rmb();
3752         intel_crtc->unpin_work = NULL;
3753
3754         if (work->event)
3755                 drm_send_vblank_event(intel_crtc->base.dev,
3756                                       intel_crtc->pipe,
3757                                       work->event);
3758
3759         drm_crtc_vblank_put(&intel_crtc->base);
3760
3761         wake_up_all(&dev_priv->pending_flip_queue);
3762         queue_work(dev_priv->wq, &work->work);
3763
3764         trace_i915_flip_complete(intel_crtc->plane,
3765                                  work->pending_flip_obj);
3766 }
3767
3768 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3769 {
3770         struct drm_device *dev = crtc->dev;
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3774         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3775                                        !intel_crtc_has_pending_flip(crtc),
3776                                        60*HZ) == 0)) {
3777                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778
3779                 spin_lock_irq(&dev->event_lock);
3780                 if (intel_crtc->unpin_work) {
3781                         WARN_ONCE(1, "Removing stuck page flip\n");
3782                         page_flip_completed(intel_crtc);
3783                 }
3784                 spin_unlock_irq(&dev->event_lock);
3785         }
3786
3787         if (crtc->primary->fb) {
3788                 mutex_lock(&dev->struct_mutex);
3789                 intel_finish_fb(crtc->primary->fb);
3790                 mutex_unlock(&dev->struct_mutex);
3791         }
3792 }
3793
3794 /* Program iCLKIP clock to the desired frequency */
3795 static void lpt_program_iclkip(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3800         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3801         u32 temp;
3802
3803         mutex_lock(&dev_priv->dpio_lock);
3804
3805         /* It is necessary to ungate the pixclk gate prior to programming
3806          * the divisors, and gate it back when it is done.
3807          */
3808         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3809
3810         /* Disable SSCCTL */
3811         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3812                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3813                                 SBI_SSCCTL_DISABLE,
3814                         SBI_ICLK);
3815
3816         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3817         if (clock == 20000) {
3818                 auxdiv = 1;
3819                 divsel = 0x41;
3820                 phaseinc = 0x20;
3821         } else {
3822                 /* The iCLK virtual clock root frequency is in MHz,
3823                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3824                  * divisors, it is necessary to divide one by another, so we
3825                  * convert the virtual clock precision to KHz here for higher
3826                  * precision.
3827                  */
3828                 u32 iclk_virtual_root_freq = 172800 * 1000;
3829                 u32 iclk_pi_range = 64;
3830                 u32 desired_divisor, msb_divisor_value, pi_value;
3831
3832                 desired_divisor = (iclk_virtual_root_freq / clock);
3833                 msb_divisor_value = desired_divisor / iclk_pi_range;
3834                 pi_value = desired_divisor % iclk_pi_range;
3835
3836                 auxdiv = 0;
3837                 divsel = msb_divisor_value - 2;
3838                 phaseinc = pi_value;
3839         }
3840
3841         /* This should not happen with any sane values */
3842         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3843                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3844         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3845                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3846
3847         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3848                         clock,
3849                         auxdiv,
3850                         divsel,
3851                         phasedir,
3852                         phaseinc);
3853
3854         /* Program SSCDIVINTPHASE6 */
3855         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3856         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3857         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3858         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3859         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3860         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3861         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3862         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3863
3864         /* Program SSCAUXDIV */
3865         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3866         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3867         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3868         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3869
3870         /* Enable modulator and associated divider */
3871         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3872         temp &= ~SBI_SSCCTL_DISABLE;
3873         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3874
3875         /* Wait for initialization time */
3876         udelay(24);
3877
3878         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3879
3880         mutex_unlock(&dev_priv->dpio_lock);
3881 }
3882
3883 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3884                                                 enum pipe pch_transcoder)
3885 {
3886         struct drm_device *dev = crtc->base.dev;
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3889
3890         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3891                    I915_READ(HTOTAL(cpu_transcoder)));
3892         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3893                    I915_READ(HBLANK(cpu_transcoder)));
3894         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3895                    I915_READ(HSYNC(cpu_transcoder)));
3896
3897         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3898                    I915_READ(VTOTAL(cpu_transcoder)));
3899         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3900                    I915_READ(VBLANK(cpu_transcoder)));
3901         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3902                    I915_READ(VSYNC(cpu_transcoder)));
3903         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3904                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3905 }
3906
3907 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3908 {
3909         struct drm_i915_private *dev_priv = dev->dev_private;
3910         uint32_t temp;
3911
3912         temp = I915_READ(SOUTH_CHICKEN1);
3913         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3914                 return;
3915
3916         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3917         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3918
3919         temp &= ~FDI_BC_BIFURCATION_SELECT;
3920         if (enable)
3921                 temp |= FDI_BC_BIFURCATION_SELECT;
3922
3923         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3924         I915_WRITE(SOUTH_CHICKEN1, temp);
3925         POSTING_READ(SOUTH_CHICKEN1);
3926 }
3927
3928 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3929 {
3930         struct drm_device *dev = intel_crtc->base.dev;
3931
3932         switch (intel_crtc->pipe) {
3933         case PIPE_A:
3934                 break;
3935         case PIPE_B:
3936                 if (intel_crtc->config->fdi_lanes > 2)
3937                         cpt_set_fdi_bc_bifurcation(dev, false);
3938                 else
3939                         cpt_set_fdi_bc_bifurcation(dev, true);
3940
3941                 break;
3942         case PIPE_C:
3943                 cpt_set_fdi_bc_bifurcation(dev, true);
3944
3945                 break;
3946         default:
3947                 BUG();
3948         }
3949 }
3950
3951 /*
3952  * Enable PCH resources required for PCH ports:
3953  *   - PCH PLLs
3954  *   - FDI training & RX/TX
3955  *   - update transcoder timings
3956  *   - DP transcoding bits
3957  *   - transcoder
3958  */
3959 static void ironlake_pch_enable(struct drm_crtc *crtc)
3960 {
3961         struct drm_device *dev = crtc->dev;
3962         struct drm_i915_private *dev_priv = dev->dev_private;
3963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3964         int pipe = intel_crtc->pipe;
3965         u32 reg, temp;
3966
3967         assert_pch_transcoder_disabled(dev_priv, pipe);
3968
3969         if (IS_IVYBRIDGE(dev))
3970                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3971
3972         /* Write the TU size bits before fdi link training, so that error
3973          * detection works. */
3974         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3975                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3976
3977         /* For PCH output, training FDI link */
3978         dev_priv->display.fdi_link_train(crtc);
3979
3980         /* We need to program the right clock selection before writing the pixel
3981          * mutliplier into the DPLL. */
3982         if (HAS_PCH_CPT(dev)) {
3983                 u32 sel;
3984
3985                 temp = I915_READ(PCH_DPLL_SEL);
3986                 temp |= TRANS_DPLL_ENABLE(pipe);
3987                 sel = TRANS_DPLLB_SEL(pipe);
3988                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3989                         temp |= sel;
3990                 else
3991                         temp &= ~sel;
3992                 I915_WRITE(PCH_DPLL_SEL, temp);
3993         }
3994
3995         /* XXX: pch pll's can be enabled any time before we enable the PCH
3996          * transcoder, and we actually should do this to not upset any PCH
3997          * transcoder that already use the clock when we share it.
3998          *
3999          * Note that enable_shared_dpll tries to do the right thing, but
4000          * get_shared_dpll unconditionally resets the pll - we need that to have
4001          * the right LVDS enable sequence. */
4002         intel_enable_shared_dpll(intel_crtc);
4003
4004         /* set transcoder timing, panel must allow it */
4005         assert_panel_unlocked(dev_priv, pipe);
4006         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4007
4008         intel_fdi_normal_train(crtc);
4009
4010         /* For PCH DP, enable TRANS_DP_CTL */
4011         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4012                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4013                 reg = TRANS_DP_CTL(pipe);
4014                 temp = I915_READ(reg);
4015                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4016                           TRANS_DP_SYNC_MASK |
4017                           TRANS_DP_BPC_MASK);
4018                 temp |= (TRANS_DP_OUTPUT_ENABLE |
4019                          TRANS_DP_ENH_FRAMING);
4020                 temp |= bpc << 9; /* same format but at 11:9 */
4021
4022                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4023                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4024                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4025                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4026
4027                 switch (intel_trans_dp_port_sel(crtc)) {
4028                 case PCH_DP_B:
4029                         temp |= TRANS_DP_PORT_SEL_B;
4030                         break;
4031                 case PCH_DP_C:
4032                         temp |= TRANS_DP_PORT_SEL_C;
4033                         break;
4034                 case PCH_DP_D:
4035                         temp |= TRANS_DP_PORT_SEL_D;
4036                         break;
4037                 default:
4038                         BUG();
4039                 }
4040
4041                 I915_WRITE(reg, temp);
4042         }
4043
4044         ironlake_enable_pch_transcoder(dev_priv, pipe);
4045 }
4046
4047 static void lpt_pch_enable(struct drm_crtc *crtc)
4048 {
4049         struct drm_device *dev = crtc->dev;
4050         struct drm_i915_private *dev_priv = dev->dev_private;
4051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4052         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4053
4054         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4055
4056         lpt_program_iclkip(crtc);
4057
4058         /* Set transcoder timing. */
4059         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4060
4061         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4062 }
4063
4064 void intel_put_shared_dpll(struct intel_crtc *crtc)
4065 {
4066         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4067
4068         if (pll == NULL)
4069                 return;
4070
4071         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4072                 WARN(1, "bad %s crtc mask\n", pll->name);
4073                 return;
4074         }
4075
4076         pll->config.crtc_mask &= ~(1 << crtc->pipe);
4077         if (pll->config.crtc_mask == 0) {
4078                 WARN_ON(pll->on);
4079                 WARN_ON(pll->active);
4080         }
4081
4082         crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4083 }
4084
4085 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4086                                                 struct intel_crtc_state *crtc_state)
4087 {
4088         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4089         struct intel_shared_dpll *pll;
4090         enum intel_dpll_id i;
4091
4092         if (HAS_PCH_IBX(dev_priv->dev)) {
4093                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4094                 i = (enum intel_dpll_id) crtc->pipe;
4095                 pll = &dev_priv->shared_dplls[i];
4096
4097                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4098                               crtc->base.base.id, pll->name);
4099
4100                 WARN_ON(pll->new_config->crtc_mask);
4101
4102                 goto found;
4103         }
4104
4105         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4106                 pll = &dev_priv->shared_dplls[i];
4107
4108                 /* Only want to check enabled timings first */
4109                 if (pll->new_config->crtc_mask == 0)
4110                         continue;
4111
4112                 if (memcmp(&crtc_state->dpll_hw_state,
4113                            &pll->new_config->hw_state,
4114                            sizeof(pll->new_config->hw_state)) == 0) {
4115                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4116                                       crtc->base.base.id, pll->name,
4117                                       pll->new_config->crtc_mask,
4118                                       pll->active);
4119                         goto found;
4120                 }
4121         }
4122
4123         /* Ok no matching timings, maybe there's a free one? */
4124         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4125                 pll = &dev_priv->shared_dplls[i];
4126                 if (pll->new_config->crtc_mask == 0) {
4127                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4128                                       crtc->base.base.id, pll->name);
4129                         goto found;
4130                 }
4131         }
4132
4133         return NULL;
4134
4135 found:
4136         if (pll->new_config->crtc_mask == 0)
4137                 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4138
4139         crtc_state->shared_dpll = i;
4140         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4141                          pipe_name(crtc->pipe));
4142
4143         pll->new_config->crtc_mask |= 1 << crtc->pipe;
4144
4145         return pll;
4146 }
4147
4148 /**
4149  * intel_shared_dpll_start_config - start a new PLL staged config
4150  * @dev_priv: DRM device
4151  * @clear_pipes: mask of pipes that will have their PLLs freed
4152  *
4153  * Starts a new PLL staged config, copying the current config but
4154  * releasing the references of pipes specified in clear_pipes.
4155  */
4156 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4157                                           unsigned clear_pipes)
4158 {
4159         struct intel_shared_dpll *pll;
4160         enum intel_dpll_id i;
4161
4162         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4163                 pll = &dev_priv->shared_dplls[i];
4164
4165                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4166                                           GFP_KERNEL);
4167                 if (!pll->new_config)
4168                         goto cleanup;
4169
4170                 pll->new_config->crtc_mask &= ~clear_pipes;
4171         }
4172
4173         return 0;
4174
4175 cleanup:
4176         while (--i >= 0) {
4177                 pll = &dev_priv->shared_dplls[i];
4178                 kfree(pll->new_config);
4179                 pll->new_config = NULL;
4180         }
4181
4182         return -ENOMEM;
4183 }
4184
4185 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4186 {
4187         struct intel_shared_dpll *pll;
4188         enum intel_dpll_id i;
4189
4190         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4191                 pll = &dev_priv->shared_dplls[i];
4192
4193                 WARN_ON(pll->new_config == &pll->config);
4194
4195                 pll->config = *pll->new_config;
4196                 kfree(pll->new_config);
4197                 pll->new_config = NULL;
4198         }
4199 }
4200
4201 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4202 {
4203         struct intel_shared_dpll *pll;
4204         enum intel_dpll_id i;
4205
4206         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4207                 pll = &dev_priv->shared_dplls[i];
4208
4209                 WARN_ON(pll->new_config == &pll->config);
4210
4211                 kfree(pll->new_config);
4212                 pll->new_config = NULL;
4213         }
4214 }
4215
4216 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4217 {
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         int dslreg = PIPEDSL(pipe);
4220         u32 temp;
4221
4222         temp = I915_READ(dslreg);
4223         udelay(500);
4224         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4225                 if (wait_for(I915_READ(dslreg) != temp, 5))
4226                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4227         }
4228 }
4229
4230 static void skylake_pfit_enable(struct intel_crtc *crtc)
4231 {
4232         struct drm_device *dev = crtc->base.dev;
4233         struct drm_i915_private *dev_priv = dev->dev_private;
4234         int pipe = crtc->pipe;
4235
4236         if (crtc->config->pch_pfit.enabled) {
4237                 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4238                 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4239                 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4240         }
4241 }
4242
4243 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4244 {
4245         struct drm_device *dev = crtc->base.dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         int pipe = crtc->pipe;
4248
4249         if (crtc->config->pch_pfit.enabled) {
4250                 /* Force use of hard-coded filter coefficients
4251                  * as some pre-programmed values are broken,
4252                  * e.g. x201.
4253                  */
4254                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4255                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4256                                                  PF_PIPE_SEL_IVB(pipe));
4257                 else
4258                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4259                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4260                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4261         }
4262 }
4263
4264 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4265 {
4266         struct drm_device *dev = crtc->dev;
4267         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4268         struct drm_plane *plane;
4269         struct intel_plane *intel_plane;
4270
4271         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4272                 intel_plane = to_intel_plane(plane);
4273                 if (intel_plane->pipe == pipe)
4274                         intel_plane_restore(&intel_plane->base);
4275         }
4276 }
4277
4278 /*
4279  * Disable a plane internally without actually modifying the plane's state.
4280  * This will allow us to easily restore the plane later by just reprogramming
4281  * its state.
4282  */
4283 static void disable_plane_internal(struct drm_plane *plane)
4284 {
4285         struct intel_plane *intel_plane = to_intel_plane(plane);
4286         struct drm_plane_state *state =
4287                 plane->funcs->atomic_duplicate_state(plane);
4288         struct intel_plane_state *intel_state = to_intel_plane_state(state);
4289
4290         intel_state->visible = false;
4291         intel_plane->commit_plane(plane, intel_state);
4292
4293         intel_plane_destroy_state(plane, state);
4294 }
4295
4296 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4297 {
4298         struct drm_device *dev = crtc->dev;
4299         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4300         struct drm_plane *plane;
4301         struct intel_plane *intel_plane;
4302
4303         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4304                 intel_plane = to_intel_plane(plane);
4305                 if (plane->fb && intel_plane->pipe == pipe)
4306                         disable_plane_internal(plane);
4307         }
4308 }
4309
4310 void hsw_enable_ips(struct intel_crtc *crtc)
4311 {
4312         struct drm_device *dev = crtc->base.dev;
4313         struct drm_i915_private *dev_priv = dev->dev_private;
4314
4315         if (!crtc->config->ips_enabled)
4316                 return;
4317
4318         /* We can only enable IPS after we enable a plane and wait for a vblank */
4319         intel_wait_for_vblank(dev, crtc->pipe);
4320
4321         assert_plane_enabled(dev_priv, crtc->plane);
4322         if (IS_BROADWELL(dev)) {
4323                 mutex_lock(&dev_priv->rps.hw_lock);
4324                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4325                 mutex_unlock(&dev_priv->rps.hw_lock);
4326                 /* Quoting Art Runyan: "its not safe to expect any particular
4327                  * value in IPS_CTL bit 31 after enabling IPS through the
4328                  * mailbox." Moreover, the mailbox may return a bogus state,
4329                  * so we need to just enable it and continue on.
4330                  */
4331         } else {
4332                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4333                 /* The bit only becomes 1 in the next vblank, so this wait here
4334                  * is essentially intel_wait_for_vblank. If we don't have this
4335                  * and don't wait for vblanks until the end of crtc_enable, then
4336                  * the HW state readout code will complain that the expected
4337                  * IPS_CTL value is not the one we read. */
4338                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4339                         DRM_ERROR("Timed out waiting for IPS enable\n");
4340         }
4341 }
4342
4343 void hsw_disable_ips(struct intel_crtc *crtc)
4344 {
4345         struct drm_device *dev = crtc->base.dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347
4348         if (!crtc->config->ips_enabled)
4349                 return;
4350
4351         assert_plane_enabled(dev_priv, crtc->plane);
4352         if (IS_BROADWELL(dev)) {
4353                 mutex_lock(&dev_priv->rps.hw_lock);
4354                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4355                 mutex_unlock(&dev_priv->rps.hw_lock);
4356                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4357                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4358                         DRM_ERROR("Timed out waiting for IPS disable\n");
4359         } else {
4360                 I915_WRITE(IPS_CTL, 0);
4361                 POSTING_READ(IPS_CTL);
4362         }
4363
4364         /* We need to wait for a vblank before we can disable the plane. */
4365         intel_wait_for_vblank(dev, crtc->pipe);
4366 }
4367
4368 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4369 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4370 {
4371         struct drm_device *dev = crtc->dev;
4372         struct drm_i915_private *dev_priv = dev->dev_private;
4373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374         enum pipe pipe = intel_crtc->pipe;
4375         int palreg = PALETTE(pipe);
4376         int i;
4377         bool reenable_ips = false;
4378
4379         /* The clocks have to be on to load the palette. */
4380         if (!crtc->state->enable || !intel_crtc->active)
4381                 return;
4382
4383         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4384                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4385                         assert_dsi_pll_enabled(dev_priv);
4386                 else
4387                         assert_pll_enabled(dev_priv, pipe);
4388         }
4389
4390         /* use legacy palette for Ironlake */
4391         if (!HAS_GMCH_DISPLAY(dev))
4392                 palreg = LGC_PALETTE(pipe);
4393
4394         /* Workaround : Do not read or write the pipe palette/gamma data while
4395          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4396          */
4397         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4398             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4399              GAMMA_MODE_MODE_SPLIT)) {
4400                 hsw_disable_ips(intel_crtc);
4401                 reenable_ips = true;
4402         }
4403
4404         for (i = 0; i < 256; i++) {
4405                 I915_WRITE(palreg + 4 * i,
4406                            (intel_crtc->lut_r[i] << 16) |
4407                            (intel_crtc->lut_g[i] << 8) |
4408                            intel_crtc->lut_b[i]);
4409         }
4410
4411         if (reenable_ips)
4412                 hsw_enable_ips(intel_crtc);
4413 }
4414
4415 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4416 {
4417         if (!enable && intel_crtc->overlay) {
4418                 struct drm_device *dev = intel_crtc->base.dev;
4419                 struct drm_i915_private *dev_priv = dev->dev_private;
4420
4421                 mutex_lock(&dev->struct_mutex);
4422                 dev_priv->mm.interruptible = false;
4423                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4424                 dev_priv->mm.interruptible = true;
4425                 mutex_unlock(&dev->struct_mutex);
4426         }
4427
4428         /* Let userspace switch the overlay on again. In most cases userspace
4429          * has to recompute where to put it anyway.
4430          */
4431 }
4432
4433 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4434 {
4435         struct drm_device *dev = crtc->dev;
4436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4437         int pipe = intel_crtc->pipe;
4438
4439         intel_enable_primary_hw_plane(crtc->primary, crtc);
4440         intel_enable_sprite_planes(crtc);
4441         intel_crtc_update_cursor(crtc, true);
4442         intel_crtc_dpms_overlay(intel_crtc, true);
4443
4444         hsw_enable_ips(intel_crtc);
4445
4446         mutex_lock(&dev->struct_mutex);
4447         intel_fbc_update(dev);
4448         mutex_unlock(&dev->struct_mutex);
4449
4450         /*
4451          * FIXME: Once we grow proper nuclear flip support out of this we need
4452          * to compute the mask of flip planes precisely. For the time being
4453          * consider this a flip from a NULL plane.
4454          */
4455         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4456 }
4457
4458 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4459 {
4460         struct drm_device *dev = crtc->dev;
4461         struct drm_i915_private *dev_priv = dev->dev_private;
4462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4463         int pipe = intel_crtc->pipe;
4464
4465         intel_crtc_wait_for_pending_flips(crtc);
4466
4467         if (dev_priv->fbc.crtc == intel_crtc)
4468                 intel_fbc_disable(dev);
4469
4470         hsw_disable_ips(intel_crtc);
4471
4472         intel_crtc_dpms_overlay(intel_crtc, false);
4473         intel_crtc_update_cursor(crtc, false);
4474         intel_disable_sprite_planes(crtc);
4475         intel_disable_primary_hw_plane(crtc->primary, crtc);
4476
4477         /*
4478          * FIXME: Once we grow proper nuclear flip support out of this we need
4479          * to compute the mask of flip planes precisely. For the time being
4480          * consider this a flip to a NULL plane.
4481          */
4482         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4483 }
4484
4485 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4486 {
4487         struct drm_device *dev = crtc->dev;
4488         struct drm_i915_private *dev_priv = dev->dev_private;
4489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4490         struct intel_encoder *encoder;
4491         int pipe = intel_crtc->pipe;
4492
4493         WARN_ON(!crtc->state->enable);
4494
4495         if (intel_crtc->active)
4496                 return;
4497
4498         if (intel_crtc->config->has_pch_encoder)
4499                 intel_prepare_shared_dpll(intel_crtc);
4500
4501         if (intel_crtc->config->has_dp_encoder)
4502                 intel_dp_set_m_n(intel_crtc, M1_N1);
4503
4504         intel_set_pipe_timings(intel_crtc);
4505
4506         if (intel_crtc->config->has_pch_encoder) {
4507                 intel_cpu_transcoder_set_m_n(intel_crtc,
4508                                      &intel_crtc->config->fdi_m_n, NULL);
4509         }
4510
4511         ironlake_set_pipeconf(crtc);
4512
4513         intel_crtc->active = true;
4514
4515         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4516         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4517
4518         for_each_encoder_on_crtc(dev, crtc, encoder)
4519                 if (encoder->pre_enable)
4520                         encoder->pre_enable(encoder);
4521
4522         if (intel_crtc->config->has_pch_encoder) {
4523                 /* Note: FDI PLL enabling _must_ be done before we enable the
4524                  * cpu pipes, hence this is separate from all the other fdi/pch
4525                  * enabling. */
4526                 ironlake_fdi_pll_enable(intel_crtc);
4527         } else {
4528                 assert_fdi_tx_disabled(dev_priv, pipe);
4529                 assert_fdi_rx_disabled(dev_priv, pipe);
4530         }
4531
4532         ironlake_pfit_enable(intel_crtc);
4533
4534         /*
4535          * On ILK+ LUT must be loaded before the pipe is running but with
4536          * clocks enabled
4537          */
4538         intel_crtc_load_lut(crtc);
4539
4540         intel_update_watermarks(crtc);
4541         intel_enable_pipe(intel_crtc);
4542
4543         if (intel_crtc->config->has_pch_encoder)
4544                 ironlake_pch_enable(crtc);
4545
4546         assert_vblank_disabled(crtc);
4547         drm_crtc_vblank_on(crtc);
4548
4549         for_each_encoder_on_crtc(dev, crtc, encoder)
4550                 encoder->enable(encoder);
4551
4552         if (HAS_PCH_CPT(dev))
4553                 cpt_verify_modeset(dev, intel_crtc->pipe);
4554
4555         intel_crtc_enable_planes(crtc);
4556 }
4557
4558 /* IPS only exists on ULT machines and is tied to pipe A. */
4559 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4560 {
4561         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4562 }
4563
4564 /*
4565  * This implements the workaround described in the "notes" section of the mode
4566  * set sequence documentation. When going from no pipes or single pipe to
4567  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4568  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4569  */
4570 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4571 {
4572         struct drm_device *dev = crtc->base.dev;
4573         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4574
4575         /* We want to get the other_active_crtc only if there's only 1 other
4576          * active crtc. */
4577         for_each_intel_crtc(dev, crtc_it) {
4578                 if (!crtc_it->active || crtc_it == crtc)
4579                         continue;
4580
4581                 if (other_active_crtc)
4582                         return;
4583
4584                 other_active_crtc = crtc_it;
4585         }
4586         if (!other_active_crtc)
4587                 return;
4588
4589         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4590         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4591 }
4592
4593 static void haswell_crtc_enable(struct drm_crtc *crtc)
4594 {
4595         struct drm_device *dev = crtc->dev;
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         struct intel_encoder *encoder;
4599         int pipe = intel_crtc->pipe;
4600
4601         WARN_ON(!crtc->state->enable);
4602
4603         if (intel_crtc->active)
4604                 return;
4605
4606         if (intel_crtc_to_shared_dpll(intel_crtc))
4607                 intel_enable_shared_dpll(intel_crtc);
4608
4609         if (intel_crtc->config->has_dp_encoder)
4610                 intel_dp_set_m_n(intel_crtc, M1_N1);
4611
4612         intel_set_pipe_timings(intel_crtc);
4613
4614         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4615                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4616                            intel_crtc->config->pixel_multiplier - 1);
4617         }
4618
4619         if (intel_crtc->config->has_pch_encoder) {
4620                 intel_cpu_transcoder_set_m_n(intel_crtc,
4621                                      &intel_crtc->config->fdi_m_n, NULL);
4622         }
4623
4624         haswell_set_pipeconf(crtc);
4625
4626         intel_set_pipe_csc(crtc);
4627
4628         intel_crtc->active = true;
4629
4630         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4631         for_each_encoder_on_crtc(dev, crtc, encoder)
4632                 if (encoder->pre_enable)
4633                         encoder->pre_enable(encoder);
4634
4635         if (intel_crtc->config->has_pch_encoder) {
4636                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4637                                                       true);
4638                 dev_priv->display.fdi_link_train(crtc);
4639         }
4640
4641         intel_ddi_enable_pipe_clock(intel_crtc);
4642
4643         if (IS_SKYLAKE(dev))
4644                 skylake_pfit_enable(intel_crtc);
4645         else
4646                 ironlake_pfit_enable(intel_crtc);
4647
4648         /*
4649          * On ILK+ LUT must be loaded before the pipe is running but with
4650          * clocks enabled
4651          */
4652         intel_crtc_load_lut(crtc);
4653
4654         intel_ddi_set_pipe_settings(crtc);
4655         intel_ddi_enable_transcoder_func(crtc);
4656
4657         intel_update_watermarks(crtc);
4658         intel_enable_pipe(intel_crtc);
4659
4660         if (intel_crtc->config->has_pch_encoder)
4661                 lpt_pch_enable(crtc);
4662
4663         if (intel_crtc->config->dp_encoder_is_mst)
4664                 intel_ddi_set_vc_payload_alloc(crtc, true);
4665
4666         assert_vblank_disabled(crtc);
4667         drm_crtc_vblank_on(crtc);
4668
4669         for_each_encoder_on_crtc(dev, crtc, encoder) {
4670                 encoder->enable(encoder);
4671                 intel_opregion_notify_encoder(encoder, true);
4672         }
4673
4674         /* If we change the relative order between pipe/planes enabling, we need
4675          * to change the workaround. */
4676         haswell_mode_set_planes_workaround(intel_crtc);
4677         intel_crtc_enable_planes(crtc);
4678 }
4679
4680 static void skylake_pfit_disable(struct intel_crtc *crtc)
4681 {
4682         struct drm_device *dev = crtc->base.dev;
4683         struct drm_i915_private *dev_priv = dev->dev_private;
4684         int pipe = crtc->pipe;
4685
4686         /* To avoid upsetting the power well on haswell only disable the pfit if
4687          * it's in use. The hw state code will make sure we get this right. */
4688         if (crtc->config->pch_pfit.enabled) {
4689                 I915_WRITE(PS_CTL(pipe), 0);
4690                 I915_WRITE(PS_WIN_POS(pipe), 0);
4691                 I915_WRITE(PS_WIN_SZ(pipe), 0);
4692         }
4693 }
4694
4695 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         int pipe = crtc->pipe;
4700
4701         /* To avoid upsetting the power well on haswell only disable the pfit if
4702          * it's in use. The hw state code will make sure we get this right. */
4703         if (crtc->config->pch_pfit.enabled) {
4704                 I915_WRITE(PF_CTL(pipe), 0);
4705                 I915_WRITE(PF_WIN_POS(pipe), 0);
4706                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4707         }
4708 }
4709
4710 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4711 {
4712         struct drm_device *dev = crtc->dev;
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715         struct intel_encoder *encoder;
4716         int pipe = intel_crtc->pipe;
4717         u32 reg, temp;
4718
4719         if (!intel_crtc->active)
4720                 return;
4721
4722         intel_crtc_disable_planes(crtc);
4723
4724         for_each_encoder_on_crtc(dev, crtc, encoder)
4725                 encoder->disable(encoder);
4726
4727         drm_crtc_vblank_off(crtc);
4728         assert_vblank_disabled(crtc);
4729
4730         if (intel_crtc->config->has_pch_encoder)
4731                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4732
4733         intel_disable_pipe(intel_crtc);
4734
4735         ironlake_pfit_disable(intel_crtc);
4736
4737         for_each_encoder_on_crtc(dev, crtc, encoder)
4738                 if (encoder->post_disable)
4739                         encoder->post_disable(encoder);
4740
4741         if (intel_crtc->config->has_pch_encoder) {
4742                 ironlake_fdi_disable(crtc);
4743
4744                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4745
4746                 if (HAS_PCH_CPT(dev)) {
4747                         /* disable TRANS_DP_CTL */
4748                         reg = TRANS_DP_CTL(pipe);
4749                         temp = I915_READ(reg);
4750                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4751                                   TRANS_DP_PORT_SEL_MASK);
4752                         temp |= TRANS_DP_PORT_SEL_NONE;
4753                         I915_WRITE(reg, temp);
4754
4755                         /* disable DPLL_SEL */
4756                         temp = I915_READ(PCH_DPLL_SEL);
4757                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4758                         I915_WRITE(PCH_DPLL_SEL, temp);
4759                 }
4760
4761                 /* disable PCH DPLL */
4762                 intel_disable_shared_dpll(intel_crtc);
4763
4764                 ironlake_fdi_pll_disable(intel_crtc);
4765         }
4766
4767         intel_crtc->active = false;
4768         intel_update_watermarks(crtc);
4769
4770         mutex_lock(&dev->struct_mutex);
4771         intel_fbc_update(dev);
4772         mutex_unlock(&dev->struct_mutex);
4773 }
4774
4775 static void haswell_crtc_disable(struct drm_crtc *crtc)
4776 {
4777         struct drm_device *dev = crtc->dev;
4778         struct drm_i915_private *dev_priv = dev->dev_private;
4779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4780         struct intel_encoder *encoder;
4781         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4782
4783         if (!intel_crtc->active)
4784                 return;
4785
4786         intel_crtc_disable_planes(crtc);
4787
4788         for_each_encoder_on_crtc(dev, crtc, encoder) {
4789                 intel_opregion_notify_encoder(encoder, false);
4790                 encoder->disable(encoder);
4791         }
4792
4793         drm_crtc_vblank_off(crtc);
4794         assert_vblank_disabled(crtc);
4795
4796         if (intel_crtc->config->has_pch_encoder)
4797                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4798                                                       false);
4799         intel_disable_pipe(intel_crtc);
4800
4801         if (intel_crtc->config->dp_encoder_is_mst)
4802                 intel_ddi_set_vc_payload_alloc(crtc, false);
4803
4804         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4805
4806         if (IS_SKYLAKE(dev))
4807                 skylake_pfit_disable(intel_crtc);
4808         else
4809                 ironlake_pfit_disable(intel_crtc);
4810
4811         intel_ddi_disable_pipe_clock(intel_crtc);
4812
4813         if (intel_crtc->config->has_pch_encoder) {
4814                 lpt_disable_pch_transcoder(dev_priv);
4815                 intel_ddi_fdi_disable(crtc);
4816         }
4817
4818         for_each_encoder_on_crtc(dev, crtc, encoder)
4819                 if (encoder->post_disable)
4820                         encoder->post_disable(encoder);
4821
4822         intel_crtc->active = false;
4823         intel_update_watermarks(crtc);
4824
4825         mutex_lock(&dev->struct_mutex);
4826         intel_fbc_update(dev);
4827         mutex_unlock(&dev->struct_mutex);
4828
4829         if (intel_crtc_to_shared_dpll(intel_crtc))
4830                 intel_disable_shared_dpll(intel_crtc);
4831 }
4832
4833 static void ironlake_crtc_off(struct drm_crtc *crtc)
4834 {
4835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836         intel_put_shared_dpll(intel_crtc);
4837 }
4838
4839
4840 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4841 {
4842         struct drm_device *dev = crtc->base.dev;
4843         struct drm_i915_private *dev_priv = dev->dev_private;
4844         struct intel_crtc_state *pipe_config = crtc->config;
4845
4846         if (!pipe_config->gmch_pfit.control)
4847                 return;
4848
4849         /*
4850          * The panel fitter should only be adjusted whilst the pipe is disabled,
4851          * according to register description and PRM.
4852          */
4853         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4854         assert_pipe_disabled(dev_priv, crtc->pipe);
4855
4856         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4857         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4858
4859         /* Border color in case we don't scale up to the full screen. Black by
4860          * default, change to something else for debugging. */
4861         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4862 }
4863
4864 static enum intel_display_power_domain port_to_power_domain(enum port port)
4865 {
4866         switch (port) {
4867         case PORT_A:
4868                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4869         case PORT_B:
4870                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4871         case PORT_C:
4872                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4873         case PORT_D:
4874                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4875         default:
4876                 WARN_ON_ONCE(1);
4877                 return POWER_DOMAIN_PORT_OTHER;
4878         }
4879 }
4880
4881 #define for_each_power_domain(domain, mask)                             \
4882         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4883                 if ((1 << (domain)) & (mask))
4884
4885 enum intel_display_power_domain
4886 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4887 {
4888         struct drm_device *dev = intel_encoder->base.dev;
4889         struct intel_digital_port *intel_dig_port;
4890
4891         switch (intel_encoder->type) {
4892         case INTEL_OUTPUT_UNKNOWN:
4893                 /* Only DDI platforms should ever use this output type */
4894                 WARN_ON_ONCE(!HAS_DDI(dev));
4895         case INTEL_OUTPUT_DISPLAYPORT:
4896         case INTEL_OUTPUT_HDMI:
4897         case INTEL_OUTPUT_EDP:
4898                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4899                 return port_to_power_domain(intel_dig_port->port);
4900         case INTEL_OUTPUT_DP_MST:
4901                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4902                 return port_to_power_domain(intel_dig_port->port);
4903         case INTEL_OUTPUT_ANALOG:
4904                 return POWER_DOMAIN_PORT_CRT;
4905         case INTEL_OUTPUT_DSI:
4906                 return POWER_DOMAIN_PORT_DSI;
4907         default:
4908                 return POWER_DOMAIN_PORT_OTHER;
4909         }
4910 }
4911
4912 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4913 {
4914         struct drm_device *dev = crtc->dev;
4915         struct intel_encoder *intel_encoder;
4916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917         enum pipe pipe = intel_crtc->pipe;
4918         unsigned long mask;
4919         enum transcoder transcoder;
4920
4921         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4922
4923         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4924         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4925         if (intel_crtc->config->pch_pfit.enabled ||
4926             intel_crtc->config->pch_pfit.force_thru)
4927                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4928
4929         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4930                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4931
4932         return mask;
4933 }
4934
4935 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4939         struct intel_crtc *crtc;
4940
4941         /*
4942          * First get all needed power domains, then put all unneeded, to avoid
4943          * any unnecessary toggling of the power wells.
4944          */
4945         for_each_intel_crtc(dev, crtc) {
4946                 enum intel_display_power_domain domain;
4947
4948                 if (!crtc->base.state->enable)
4949                         continue;
4950
4951                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4952
4953                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4954                         intel_display_power_get(dev_priv, domain);
4955         }
4956
4957         if (dev_priv->display.modeset_global_resources)
4958                 dev_priv->display.modeset_global_resources(dev);
4959
4960         for_each_intel_crtc(dev, crtc) {
4961                 enum intel_display_power_domain domain;
4962
4963                 for_each_power_domain(domain, crtc->enabled_power_domains)
4964                         intel_display_power_put(dev_priv, domain);
4965
4966                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4967         }
4968
4969         intel_display_set_init_power(dev_priv, false);
4970 }
4971
4972 /* returns HPLL frequency in kHz */
4973 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4974 {
4975         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4976
4977         /* Obtain SKU information */
4978         mutex_lock(&dev_priv->dpio_lock);
4979         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4980                 CCK_FUSE_HPLL_FREQ_MASK;
4981         mutex_unlock(&dev_priv->dpio_lock);
4982
4983         return vco_freq[hpll_freq] * 1000;
4984 }
4985
4986 static void vlv_update_cdclk(struct drm_device *dev)
4987 {
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989
4990         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4991         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4992                          dev_priv->vlv_cdclk_freq);
4993
4994         /*
4995          * Program the gmbus_freq based on the cdclk frequency.
4996          * BSpec erroneously claims we should aim for 4MHz, but
4997          * in fact 1MHz is the correct frequency.
4998          */
4999         I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5000 }
5001
5002 /* Adjust CDclk dividers to allow high res or save power if possible */
5003 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5004 {
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         u32 val, cmd;
5007
5008         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5009
5010         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5011                 cmd = 2;
5012         else if (cdclk == 266667)
5013                 cmd = 1;
5014         else
5015                 cmd = 0;
5016
5017         mutex_lock(&dev_priv->rps.hw_lock);
5018         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5019         val &= ~DSPFREQGUAR_MASK;
5020         val |= (cmd << DSPFREQGUAR_SHIFT);
5021         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5022         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5023                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5024                      50)) {
5025                 DRM_ERROR("timed out waiting for CDclk change\n");
5026         }
5027         mutex_unlock(&dev_priv->rps.hw_lock);
5028
5029         if (cdclk == 400000) {
5030                 u32 divider;
5031
5032                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5033
5034                 mutex_lock(&dev_priv->dpio_lock);
5035                 /* adjust cdclk divider */
5036                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5037                 val &= ~DISPLAY_FREQUENCY_VALUES;
5038                 val |= divider;
5039                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5040
5041                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5042                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5043                              50))
5044                         DRM_ERROR("timed out waiting for CDclk change\n");
5045                 mutex_unlock(&dev_priv->dpio_lock);
5046         }
5047
5048         mutex_lock(&dev_priv->dpio_lock);
5049         /* adjust self-refresh exit latency value */
5050         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5051         val &= ~0x7f;
5052
5053         /*
5054          * For high bandwidth configs, we set a higher latency in the bunit
5055          * so that the core display fetch happens in time to avoid underruns.
5056          */
5057         if (cdclk == 400000)
5058                 val |= 4500 / 250; /* 4.5 usec */
5059         else
5060                 val |= 3000 / 250; /* 3.0 usec */
5061         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5062         mutex_unlock(&dev_priv->dpio_lock);
5063
5064         vlv_update_cdclk(dev);
5065 }
5066
5067 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5068 {
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         u32 val, cmd;
5071
5072         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5073
5074         switch (cdclk) {
5075         case 333333:
5076         case 320000:
5077         case 266667:
5078         case 200000:
5079                 break;
5080         default:
5081                 MISSING_CASE(cdclk);
5082                 return;
5083         }
5084
5085         /*
5086          * Specs are full of misinformation, but testing on actual
5087          * hardware has shown that we just need to write the desired
5088          * CCK divider into the Punit register.
5089          */
5090         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5091
5092         mutex_lock(&dev_priv->rps.hw_lock);
5093         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5094         val &= ~DSPFREQGUAR_MASK_CHV;
5095         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5096         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5097         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5098                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5099                      50)) {
5100                 DRM_ERROR("timed out waiting for CDclk change\n");
5101         }
5102         mutex_unlock(&dev_priv->rps.hw_lock);
5103
5104         vlv_update_cdclk(dev);
5105 }
5106
5107 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5108                                  int max_pixclk)
5109 {
5110         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5111         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5112
5113         /*
5114          * Really only a few cases to deal with, as only 4 CDclks are supported:
5115          *   200MHz
5116          *   267MHz
5117          *   320/333MHz (depends on HPLL freq)
5118          *   400MHz (VLV only)
5119          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5120          * of the lower bin and adjust if needed.
5121          *
5122          * We seem to get an unstable or solid color picture at 200MHz.
5123          * Not sure what's wrong. For now use 200MHz only when all pipes
5124          * are off.
5125          */
5126         if (!IS_CHERRYVIEW(dev_priv) &&
5127             max_pixclk > freq_320*limit/100)
5128                 return 400000;
5129         else if (max_pixclk > 266667*limit/100)
5130                 return freq_320;
5131         else if (max_pixclk > 0)
5132                 return 266667;
5133         else
5134                 return 200000;
5135 }
5136
5137 /* compute the max pixel clock for new configuration */
5138 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5139 {
5140         struct drm_device *dev = dev_priv->dev;
5141         struct intel_crtc *intel_crtc;
5142         int max_pixclk = 0;
5143
5144         for_each_intel_crtc(dev, intel_crtc) {
5145                 if (intel_crtc->new_enabled)
5146                         max_pixclk = max(max_pixclk,
5147                                          intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5148         }
5149
5150         return max_pixclk;
5151 }
5152
5153 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5154                                             unsigned *prepare_pipes)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157         struct intel_crtc *intel_crtc;
5158         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5159
5160         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5161             dev_priv->vlv_cdclk_freq)
5162                 return;
5163
5164         /* disable/enable all currently active pipes while we change cdclk */
5165         for_each_intel_crtc(dev, intel_crtc)
5166                 if (intel_crtc->base.state->enable)
5167                         *prepare_pipes |= (1 << intel_crtc->pipe);
5168 }
5169
5170 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5171 {
5172         unsigned int credits, default_credits;
5173
5174         if (IS_CHERRYVIEW(dev_priv))
5175                 default_credits = PFI_CREDIT(12);
5176         else
5177                 default_credits = PFI_CREDIT(8);
5178
5179         if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5180                 /* CHV suggested value is 31 or 63 */
5181                 if (IS_CHERRYVIEW(dev_priv))
5182                         credits = PFI_CREDIT_31;
5183                 else
5184                         credits = PFI_CREDIT(15);
5185         } else {
5186                 credits = default_credits;
5187         }
5188
5189         /*
5190          * WA - write default credits before re-programming
5191          * FIXME: should we also set the resend bit here?
5192          */
5193         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5194                    default_credits);
5195
5196         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5197                    credits | PFI_CREDIT_RESEND);
5198
5199         /*
5200          * FIXME is this guaranteed to clear
5201          * immediately or should we poll for it?
5202          */
5203         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5204 }
5205
5206 static void valleyview_modeset_global_resources(struct drm_device *dev)
5207 {
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         int max_pixclk = intel_mode_max_pixclk(dev_priv);
5210         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5211
5212         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5213                 /*
5214                  * FIXME: We can end up here with all power domains off, yet
5215                  * with a CDCLK frequency other than the minimum. To account
5216                  * for this take the PIPE-A power domain, which covers the HW
5217                  * blocks needed for the following programming. This can be
5218                  * removed once it's guaranteed that we get here either with
5219                  * the minimum CDCLK set, or the required power domains
5220                  * enabled.
5221                  */
5222                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5223
5224                 if (IS_CHERRYVIEW(dev))
5225                         cherryview_set_cdclk(dev, req_cdclk);
5226                 else
5227                         valleyview_set_cdclk(dev, req_cdclk);
5228
5229                 vlv_program_pfi_credits(dev_priv);
5230
5231                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5232         }
5233 }
5234
5235 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5236 {
5237         struct drm_device *dev = crtc->dev;
5238         struct drm_i915_private *dev_priv = to_i915(dev);
5239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240         struct intel_encoder *encoder;
5241         int pipe = intel_crtc->pipe;
5242         bool is_dsi;
5243
5244         WARN_ON(!crtc->state->enable);
5245
5246         if (intel_crtc->active)
5247                 return;
5248
5249         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5250
5251         if (!is_dsi) {
5252                 if (IS_CHERRYVIEW(dev))
5253                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5254                 else
5255                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5256         }
5257
5258         if (intel_crtc->config->has_dp_encoder)
5259                 intel_dp_set_m_n(intel_crtc, M1_N1);
5260
5261         intel_set_pipe_timings(intel_crtc);
5262
5263         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5264                 struct drm_i915_private *dev_priv = dev->dev_private;
5265
5266                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5267                 I915_WRITE(CHV_CANVAS(pipe), 0);
5268         }
5269
5270         i9xx_set_pipeconf(intel_crtc);
5271
5272         intel_crtc->active = true;
5273
5274         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5275
5276         for_each_encoder_on_crtc(dev, crtc, encoder)
5277                 if (encoder->pre_pll_enable)
5278                         encoder->pre_pll_enable(encoder);
5279
5280         if (!is_dsi) {
5281                 if (IS_CHERRYVIEW(dev))
5282                         chv_enable_pll(intel_crtc, intel_crtc->config);
5283                 else
5284                         vlv_enable_pll(intel_crtc, intel_crtc->config);
5285         }
5286
5287         for_each_encoder_on_crtc(dev, crtc, encoder)
5288                 if (encoder->pre_enable)
5289                         encoder->pre_enable(encoder);
5290
5291         i9xx_pfit_enable(intel_crtc);
5292
5293         intel_crtc_load_lut(crtc);
5294
5295         intel_update_watermarks(crtc);
5296         intel_enable_pipe(intel_crtc);
5297
5298         assert_vblank_disabled(crtc);
5299         drm_crtc_vblank_on(crtc);
5300
5301         for_each_encoder_on_crtc(dev, crtc, encoder)
5302                 encoder->enable(encoder);
5303
5304         intel_crtc_enable_planes(crtc);
5305
5306         /* Underruns don't raise interrupts, so check manually. */
5307         i9xx_check_fifo_underruns(dev_priv);
5308 }
5309
5310 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5311 {
5312         struct drm_device *dev = crtc->base.dev;
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314
5315         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5316         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5317 }
5318
5319 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5320 {
5321         struct drm_device *dev = crtc->dev;
5322         struct drm_i915_private *dev_priv = to_i915(dev);
5323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5324         struct intel_encoder *encoder;
5325         int pipe = intel_crtc->pipe;
5326
5327         WARN_ON(!crtc->state->enable);
5328
5329         if (intel_crtc->active)
5330                 return;
5331
5332         i9xx_set_pll_dividers(intel_crtc);
5333
5334         if (intel_crtc->config->has_dp_encoder)
5335                 intel_dp_set_m_n(intel_crtc, M1_N1);
5336
5337         intel_set_pipe_timings(intel_crtc);
5338
5339         i9xx_set_pipeconf(intel_crtc);
5340
5341         intel_crtc->active = true;
5342
5343         if (!IS_GEN2(dev))
5344                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5345
5346         for_each_encoder_on_crtc(dev, crtc, encoder)
5347                 if (encoder->pre_enable)
5348                         encoder->pre_enable(encoder);
5349
5350         i9xx_enable_pll(intel_crtc);
5351
5352         i9xx_pfit_enable(intel_crtc);
5353
5354         intel_crtc_load_lut(crtc);
5355
5356         intel_update_watermarks(crtc);
5357         intel_enable_pipe(intel_crtc);
5358
5359         assert_vblank_disabled(crtc);
5360         drm_crtc_vblank_on(crtc);
5361
5362         for_each_encoder_on_crtc(dev, crtc, encoder)
5363                 encoder->enable(encoder);
5364
5365         intel_crtc_enable_planes(crtc);
5366
5367         /*
5368          * Gen2 reports pipe underruns whenever all planes are disabled.
5369          * So don't enable underrun reporting before at least some planes
5370          * are enabled.
5371          * FIXME: Need to fix the logic to work when we turn off all planes
5372          * but leave the pipe running.
5373          */
5374         if (IS_GEN2(dev))
5375                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5376
5377         /* Underruns don't raise interrupts, so check manually. */
5378         i9xx_check_fifo_underruns(dev_priv);
5379 }
5380
5381 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5382 {
5383         struct drm_device *dev = crtc->base.dev;
5384         struct drm_i915_private *dev_priv = dev->dev_private;
5385
5386         if (!crtc->config->gmch_pfit.control)
5387                 return;
5388
5389         assert_pipe_disabled(dev_priv, crtc->pipe);
5390
5391         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5392                          I915_READ(PFIT_CONTROL));
5393         I915_WRITE(PFIT_CONTROL, 0);
5394 }
5395
5396 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5397 {
5398         struct drm_device *dev = crtc->dev;
5399         struct drm_i915_private *dev_priv = dev->dev_private;
5400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401         struct intel_encoder *encoder;
5402         int pipe = intel_crtc->pipe;
5403
5404         if (!intel_crtc->active)
5405                 return;
5406
5407         /*
5408          * Gen2 reports pipe underruns whenever all planes are disabled.
5409          * So diasble underrun reporting before all the planes get disabled.
5410          * FIXME: Need to fix the logic to work when we turn off all planes
5411          * but leave the pipe running.
5412          */
5413         if (IS_GEN2(dev))
5414                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5415
5416         /*
5417          * Vblank time updates from the shadow to live plane control register
5418          * are blocked if the memory self-refresh mode is active at that
5419          * moment. So to make sure the plane gets truly disabled, disable
5420          * first the self-refresh mode. The self-refresh enable bit in turn
5421          * will be checked/applied by the HW only at the next frame start
5422          * event which is after the vblank start event, so we need to have a
5423          * wait-for-vblank between disabling the plane and the pipe.
5424          */
5425         intel_set_memory_cxsr(dev_priv, false);
5426         intel_crtc_disable_planes(crtc);
5427
5428         /*
5429          * On gen2 planes are double buffered but the pipe isn't, so we must
5430          * wait for planes to fully turn off before disabling the pipe.
5431          * We also need to wait on all gmch platforms because of the
5432          * self-refresh mode constraint explained above.
5433          */
5434         intel_wait_for_vblank(dev, pipe);
5435
5436         for_each_encoder_on_crtc(dev, crtc, encoder)
5437                 encoder->disable(encoder);
5438
5439         drm_crtc_vblank_off(crtc);
5440         assert_vblank_disabled(crtc);
5441
5442         intel_disable_pipe(intel_crtc);
5443
5444         i9xx_pfit_disable(intel_crtc);
5445
5446         for_each_encoder_on_crtc(dev, crtc, encoder)
5447                 if (encoder->post_disable)
5448                         encoder->post_disable(encoder);
5449
5450         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5451                 if (IS_CHERRYVIEW(dev))
5452                         chv_disable_pll(dev_priv, pipe);
5453                 else if (IS_VALLEYVIEW(dev))
5454                         vlv_disable_pll(dev_priv, pipe);
5455                 else
5456                         i9xx_disable_pll(intel_crtc);
5457         }
5458
5459         if (!IS_GEN2(dev))
5460                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5461
5462         intel_crtc->active = false;
5463         intel_update_watermarks(crtc);
5464
5465         mutex_lock(&dev->struct_mutex);
5466         intel_fbc_update(dev);
5467         mutex_unlock(&dev->struct_mutex);
5468 }
5469
5470 static void i9xx_crtc_off(struct drm_crtc *crtc)
5471 {
5472 }
5473
5474 /* Master function to enable/disable CRTC and corresponding power wells */
5475 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5476 {
5477         struct drm_device *dev = crtc->dev;
5478         struct drm_i915_private *dev_priv = dev->dev_private;
5479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480         enum intel_display_power_domain domain;
5481         unsigned long domains;
5482
5483         if (enable) {
5484                 if (!intel_crtc->active) {
5485                         domains = get_crtc_power_domains(crtc);
5486                         for_each_power_domain(domain, domains)
5487                                 intel_display_power_get(dev_priv, domain);
5488                         intel_crtc->enabled_power_domains = domains;
5489
5490                         dev_priv->display.crtc_enable(crtc);
5491                 }
5492         } else {
5493                 if (intel_crtc->active) {
5494                         dev_priv->display.crtc_disable(crtc);
5495
5496                         domains = intel_crtc->enabled_power_domains;
5497                         for_each_power_domain(domain, domains)
5498                                 intel_display_power_put(dev_priv, domain);
5499                         intel_crtc->enabled_power_domains = 0;
5500                 }
5501         }
5502 }
5503
5504 /**
5505  * Sets the power management mode of the pipe and plane.
5506  */
5507 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5508 {
5509         struct drm_device *dev = crtc->dev;
5510         struct intel_encoder *intel_encoder;
5511         bool enable = false;
5512
5513         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5514                 enable |= intel_encoder->connectors_active;
5515
5516         intel_crtc_control(crtc, enable);
5517 }
5518
5519 static void intel_crtc_disable(struct drm_crtc *crtc)
5520 {
5521         struct drm_device *dev = crtc->dev;
5522         struct drm_connector *connector;
5523         struct drm_i915_private *dev_priv = dev->dev_private;
5524
5525         /* crtc should still be enabled when we disable it. */
5526         WARN_ON(!crtc->state->enable);
5527
5528         dev_priv->display.crtc_disable(crtc);
5529         dev_priv->display.off(crtc);
5530
5531         crtc->primary->funcs->disable_plane(crtc->primary);
5532
5533         /* Update computed state. */
5534         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5535                 if (!connector->encoder || !connector->encoder->crtc)
5536                         continue;
5537
5538                 if (connector->encoder->crtc != crtc)
5539                         continue;
5540
5541                 connector->dpms = DRM_MODE_DPMS_OFF;
5542                 to_intel_encoder(connector->encoder)->connectors_active = false;
5543         }
5544 }
5545
5546 void intel_encoder_destroy(struct drm_encoder *encoder)
5547 {
5548         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5549
5550         drm_encoder_cleanup(encoder);
5551         kfree(intel_encoder);
5552 }
5553
5554 /* Simple dpms helper for encoders with just one connector, no cloning and only
5555  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5556  * state of the entire output pipe. */
5557 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5558 {
5559         if (mode == DRM_MODE_DPMS_ON) {
5560                 encoder->connectors_active = true;
5561
5562                 intel_crtc_update_dpms(encoder->base.crtc);
5563         } else {
5564                 encoder->connectors_active = false;
5565
5566                 intel_crtc_update_dpms(encoder->base.crtc);
5567         }
5568 }
5569
5570 /* Cross check the actual hw state with our own modeset state tracking (and it's
5571  * internal consistency). */
5572 static void intel_connector_check_state(struct intel_connector *connector)
5573 {
5574         if (connector->get_hw_state(connector)) {
5575                 struct intel_encoder *encoder = connector->encoder;
5576                 struct drm_crtc *crtc;
5577                 bool encoder_enabled;
5578                 enum pipe pipe;
5579
5580                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5581                               connector->base.base.id,
5582                               connector->base.name);
5583
5584                 /* there is no real hw state for MST connectors */
5585                 if (connector->mst_port)
5586                         return;
5587
5588                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5589                      "wrong connector dpms state\n");
5590                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5591                      "active connector not linked to encoder\n");
5592
5593                 if (encoder) {
5594                         I915_STATE_WARN(!encoder->connectors_active,
5595                              "encoder->connectors_active not set\n");
5596
5597                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5598                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5599                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
5600                                 return;
5601
5602                         crtc = encoder->base.crtc;
5603
5604                         I915_STATE_WARN(!crtc->state->enable,
5605                                         "crtc not enabled\n");
5606                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5607                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5608                              "encoder active on the wrong pipe\n");
5609                 }
5610         }
5611 }
5612
5613 /* Even simpler default implementation, if there's really no special case to
5614  * consider. */
5615 void intel_connector_dpms(struct drm_connector *connector, int mode)
5616 {
5617         /* All the simple cases only support two dpms states. */
5618         if (mode != DRM_MODE_DPMS_ON)
5619                 mode = DRM_MODE_DPMS_OFF;
5620
5621         if (mode == connector->dpms)
5622                 return;
5623
5624         connector->dpms = mode;
5625
5626         /* Only need to change hw state when actually enabled */
5627         if (connector->encoder)
5628                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5629
5630         intel_modeset_check_state(connector->dev);
5631 }
5632
5633 /* Simple connector->get_hw_state implementation for encoders that support only
5634  * one connector and no cloning and hence the encoder state determines the state
5635  * of the connector. */
5636 bool intel_connector_get_hw_state(struct intel_connector *connector)
5637 {
5638         enum pipe pipe = 0;
5639         struct intel_encoder *encoder = connector->encoder;
5640
5641         return encoder->get_hw_state(encoder, &pipe);
5642 }
5643
5644 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5645 {
5646         struct intel_crtc *crtc =
5647                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5648
5649         if (crtc->base.state->enable &&
5650             crtc->config->has_pch_encoder)
5651                 return crtc->config->fdi_lanes;
5652
5653         return 0;
5654 }
5655
5656 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5657                                      struct intel_crtc_state *pipe_config)
5658 {
5659         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5660                       pipe_name(pipe), pipe_config->fdi_lanes);
5661         if (pipe_config->fdi_lanes > 4) {
5662                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5663                               pipe_name(pipe), pipe_config->fdi_lanes);
5664                 return false;
5665         }
5666
5667         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5668                 if (pipe_config->fdi_lanes > 2) {
5669                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5670                                       pipe_config->fdi_lanes);
5671                         return false;
5672                 } else {
5673                         return true;
5674                 }
5675         }
5676
5677         if (INTEL_INFO(dev)->num_pipes == 2)
5678                 return true;
5679
5680         /* Ivybridge 3 pipe is really complicated */
5681         switch (pipe) {
5682         case PIPE_A:
5683                 return true;
5684         case PIPE_B:
5685                 if (pipe_config->fdi_lanes > 2 &&
5686                     pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5687                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5688                                       pipe_name(pipe), pipe_config->fdi_lanes);
5689                         return false;
5690                 }
5691                 return true;
5692         case PIPE_C:
5693                 if (pipe_config->fdi_lanes > 2) {
5694                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5695                                       pipe_name(pipe), pipe_config->fdi_lanes);
5696                         return false;
5697                 }
5698                 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5699                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5700                         return false;
5701                 }
5702                 return true;
5703         default:
5704                 BUG();
5705         }
5706 }
5707
5708 #define RETRY 1
5709 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5710                                        struct intel_crtc_state *pipe_config)
5711 {
5712         struct drm_device *dev = intel_crtc->base.dev;
5713         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5714         int lane, link_bw, fdi_dotclock;
5715         bool setup_ok, needs_recompute = false;
5716
5717 retry:
5718         /* FDI is a binary signal running at ~2.7GHz, encoding
5719          * each output octet as 10 bits. The actual frequency
5720          * is stored as a divider into a 100MHz clock, and the
5721          * mode pixel clock is stored in units of 1KHz.
5722          * Hence the bw of each lane in terms of the mode signal
5723          * is:
5724          */
5725         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5726
5727         fdi_dotclock = adjusted_mode->crtc_clock;
5728
5729         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5730                                            pipe_config->pipe_bpp);
5731
5732         pipe_config->fdi_lanes = lane;
5733
5734         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5735                                link_bw, &pipe_config->fdi_m_n);
5736
5737         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5738                                             intel_crtc->pipe, pipe_config);
5739         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5740                 pipe_config->pipe_bpp -= 2*3;
5741                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5742                               pipe_config->pipe_bpp);
5743                 needs_recompute = true;
5744                 pipe_config->bw_constrained = true;
5745
5746                 goto retry;
5747         }
5748
5749         if (needs_recompute)
5750                 return RETRY;
5751
5752         return setup_ok ? 0 : -EINVAL;
5753 }
5754
5755 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5756                                    struct intel_crtc_state *pipe_config)
5757 {
5758         pipe_config->ips_enabled = i915.enable_ips &&
5759                                    hsw_crtc_supports_ips(crtc) &&
5760                                    pipe_config->pipe_bpp <= 24;
5761 }
5762
5763 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5764                                      struct intel_crtc_state *pipe_config)
5765 {
5766         struct drm_device *dev = crtc->base.dev;
5767         struct drm_i915_private *dev_priv = dev->dev_private;
5768         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5769
5770         /* FIXME should check pixel clock limits on all platforms */
5771         if (INTEL_INFO(dev)->gen < 4) {
5772                 int clock_limit =
5773                         dev_priv->display.get_display_clock_speed(dev);
5774
5775                 /*
5776                  * Enable pixel doubling when the dot clock
5777                  * is > 90% of the (display) core speed.
5778                  *
5779                  * GDG double wide on either pipe,
5780                  * otherwise pipe A only.
5781                  */
5782                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5783                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5784                         clock_limit *= 2;
5785                         pipe_config->double_wide = true;
5786                 }
5787
5788                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5789                         return -EINVAL;
5790         }
5791
5792         /*
5793          * Pipe horizontal size must be even in:
5794          * - DVO ganged mode
5795          * - LVDS dual channel mode
5796          * - Double wide pipe
5797          */
5798         if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5799              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5800                 pipe_config->pipe_src_w &= ~1;
5801
5802         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5803          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5804          */
5805         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5806                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5807                 return -EINVAL;
5808
5809         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5810                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5811         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5812                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5813                  * for lvds. */
5814                 pipe_config->pipe_bpp = 8*3;
5815         }
5816
5817         if (HAS_IPS(dev))
5818                 hsw_compute_ips_config(crtc, pipe_config);
5819
5820         if (pipe_config->has_pch_encoder)
5821                 return ironlake_fdi_compute_config(crtc, pipe_config);
5822
5823         return 0;
5824 }
5825
5826 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5827 {
5828         struct drm_i915_private *dev_priv = dev->dev_private;
5829         u32 val;
5830         int divider;
5831
5832         if (dev_priv->hpll_freq == 0)
5833                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5834
5835         mutex_lock(&dev_priv->dpio_lock);
5836         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5837         mutex_unlock(&dev_priv->dpio_lock);
5838
5839         divider = val & DISPLAY_FREQUENCY_VALUES;
5840
5841         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5842              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5843              "cdclk change in progress\n");
5844
5845         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5846 }
5847
5848 static int i945_get_display_clock_speed(struct drm_device *dev)
5849 {
5850         return 400000;
5851 }
5852
5853 static int i915_get_display_clock_speed(struct drm_device *dev)
5854 {
5855         return 333000;
5856 }
5857
5858 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5859 {
5860         return 200000;
5861 }
5862
5863 static int pnv_get_display_clock_speed(struct drm_device *dev)
5864 {
5865         u16 gcfgc = 0;
5866
5867         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5868
5869         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5870         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5871                 return 267000;
5872         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5873                 return 333000;
5874         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5875                 return 444000;
5876         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5877                 return 200000;
5878         default:
5879                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5880         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5881                 return 133000;
5882         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5883                 return 167000;
5884         }
5885 }
5886
5887 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5888 {
5889         u16 gcfgc = 0;
5890
5891         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5892
5893         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5894                 return 133000;
5895         else {
5896                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5897                 case GC_DISPLAY_CLOCK_333_MHZ:
5898                         return 333000;
5899                 default:
5900                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5901                         return 190000;
5902                 }
5903         }
5904 }
5905
5906 static int i865_get_display_clock_speed(struct drm_device *dev)
5907 {
5908         return 266000;
5909 }
5910
5911 static int i855_get_display_clock_speed(struct drm_device *dev)
5912 {
5913         u16 hpllcc = 0;
5914         /* Assume that the hardware is in the high speed state.  This
5915          * should be the default.
5916          */
5917         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5918         case GC_CLOCK_133_200:
5919         case GC_CLOCK_100_200:
5920                 return 200000;
5921         case GC_CLOCK_166_250:
5922                 return 250000;
5923         case GC_CLOCK_100_133:
5924                 return 133000;
5925         }
5926
5927         /* Shouldn't happen */
5928         return 0;
5929 }
5930
5931 static int i830_get_display_clock_speed(struct drm_device *dev)
5932 {
5933         return 133000;
5934 }
5935
5936 static void
5937 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5938 {
5939         while (*num > DATA_LINK_M_N_MASK ||
5940                *den > DATA_LINK_M_N_MASK) {
5941                 *num >>= 1;
5942                 *den >>= 1;
5943         }
5944 }
5945
5946 static void compute_m_n(unsigned int m, unsigned int n,
5947                         uint32_t *ret_m, uint32_t *ret_n)
5948 {
5949         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5950         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5951         intel_reduce_m_n_ratio(ret_m, ret_n);
5952 }
5953
5954 void
5955 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5956                        int pixel_clock, int link_clock,
5957                        struct intel_link_m_n *m_n)
5958 {
5959         m_n->tu = 64;
5960
5961         compute_m_n(bits_per_pixel * pixel_clock,
5962                     link_clock * nlanes * 8,
5963                     &m_n->gmch_m, &m_n->gmch_n);
5964
5965         compute_m_n(pixel_clock, link_clock,
5966                     &m_n->link_m, &m_n->link_n);
5967 }
5968
5969 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5970 {
5971         if (i915.panel_use_ssc >= 0)
5972                 return i915.panel_use_ssc != 0;
5973         return dev_priv->vbt.lvds_use_ssc
5974                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5975 }
5976
5977 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5978 {
5979         struct drm_device *dev = crtc->base.dev;
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         int refclk;
5982
5983         if (IS_VALLEYVIEW(dev)) {
5984                 refclk = 100000;
5985         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5986             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5987                 refclk = dev_priv->vbt.lvds_ssc_freq;
5988                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5989         } else if (!IS_GEN2(dev)) {
5990                 refclk = 96000;
5991         } else {
5992                 refclk = 48000;
5993         }
5994
5995         return refclk;
5996 }
5997
5998 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5999 {
6000         return (1 << dpll->n) << 16 | dpll->m2;
6001 }
6002
6003 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6004 {
6005         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6006 }
6007
6008 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6009                                      struct intel_crtc_state *crtc_state,
6010                                      intel_clock_t *reduced_clock)
6011 {
6012         struct drm_device *dev = crtc->base.dev;
6013         u32 fp, fp2 = 0;
6014
6015         if (IS_PINEVIEW(dev)) {
6016                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6017                 if (reduced_clock)
6018                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6019         } else {
6020                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6021                 if (reduced_clock)
6022                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6023         }
6024
6025         crtc_state->dpll_hw_state.fp0 = fp;
6026
6027         crtc->lowfreq_avail = false;
6028         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6029             reduced_clock) {
6030                 crtc_state->dpll_hw_state.fp1 = fp2;
6031                 crtc->lowfreq_avail = true;
6032         } else {
6033                 crtc_state->dpll_hw_state.fp1 = fp;
6034         }
6035 }
6036
6037 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6038                 pipe)
6039 {
6040         u32 reg_val;
6041
6042         /*
6043          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6044          * and set it to a reasonable value instead.
6045          */
6046         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6047         reg_val &= 0xffffff00;
6048         reg_val |= 0x00000030;
6049         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6050
6051         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6052         reg_val &= 0x8cffffff;
6053         reg_val = 0x8c000000;
6054         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6055
6056         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6057         reg_val &= 0xffffff00;
6058         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6059
6060         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6061         reg_val &= 0x00ffffff;
6062         reg_val |= 0xb0000000;
6063         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6064 }
6065
6066 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6067                                          struct intel_link_m_n *m_n)
6068 {
6069         struct drm_device *dev = crtc->base.dev;
6070         struct drm_i915_private *dev_priv = dev->dev_private;
6071         int pipe = crtc->pipe;
6072
6073         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6074         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6075         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6076         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6077 }
6078
6079 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6080                                          struct intel_link_m_n *m_n,
6081                                          struct intel_link_m_n *m2_n2)
6082 {
6083         struct drm_device *dev = crtc->base.dev;
6084         struct drm_i915_private *dev_priv = dev->dev_private;
6085         int pipe = crtc->pipe;
6086         enum transcoder transcoder = crtc->config->cpu_transcoder;
6087
6088         if (INTEL_INFO(dev)->gen >= 5) {
6089                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6090                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6091                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6092                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6093                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6094                  * for gen < 8) and if DRRS is supported (to make sure the
6095                  * registers are not unnecessarily accessed).
6096                  */
6097                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6098                         crtc->config->has_drrs) {
6099                         I915_WRITE(PIPE_DATA_M2(transcoder),
6100                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6101                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6102                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6103                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6104                 }
6105         } else {
6106                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6107                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6108                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6109                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6110         }
6111 }
6112
6113 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6114 {
6115         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6116
6117         if (m_n == M1_N1) {
6118                 dp_m_n = &crtc->config->dp_m_n;
6119                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6120         } else if (m_n == M2_N2) {
6121
6122                 /*
6123                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6124                  * needs to be programmed into M1_N1.
6125                  */
6126                 dp_m_n = &crtc->config->dp_m2_n2;
6127         } else {
6128                 DRM_ERROR("Unsupported divider value\n");
6129                 return;
6130         }
6131
6132         if (crtc->config->has_pch_encoder)
6133                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6134         else
6135                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6136 }
6137
6138 static void vlv_update_pll(struct intel_crtc *crtc,
6139                            struct intel_crtc_state *pipe_config)
6140 {
6141         u32 dpll, dpll_md;
6142
6143         /*
6144          * Enable DPIO clock input. We should never disable the reference
6145          * clock for pipe B, since VGA hotplug / manual detection depends
6146          * on it.
6147          */
6148         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6149                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6150         /* We should never disable this, set it here for state tracking */
6151         if (crtc->pipe == PIPE_B)
6152                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6153         dpll |= DPLL_VCO_ENABLE;
6154         pipe_config->dpll_hw_state.dpll = dpll;
6155
6156         dpll_md = (pipe_config->pixel_multiplier - 1)
6157                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6158         pipe_config->dpll_hw_state.dpll_md = dpll_md;
6159 }
6160
6161 static void vlv_prepare_pll(struct intel_crtc *crtc,
6162                             const struct intel_crtc_state *pipe_config)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         int pipe = crtc->pipe;
6167         u32 mdiv;
6168         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6169         u32 coreclk, reg_val;
6170
6171         mutex_lock(&dev_priv->dpio_lock);
6172
6173         bestn = pipe_config->dpll.n;
6174         bestm1 = pipe_config->dpll.m1;
6175         bestm2 = pipe_config->dpll.m2;
6176         bestp1 = pipe_config->dpll.p1;
6177         bestp2 = pipe_config->dpll.p2;
6178
6179         /* See eDP HDMI DPIO driver vbios notes doc */
6180
6181         /* PLL B needs special handling */
6182         if (pipe == PIPE_B)
6183                 vlv_pllb_recal_opamp(dev_priv, pipe);
6184
6185         /* Set up Tx target for periodic Rcomp update */
6186         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6187
6188         /* Disable target IRef on PLL */
6189         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6190         reg_val &= 0x00ffffff;
6191         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6192
6193         /* Disable fast lock */
6194         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6195
6196         /* Set idtafcrecal before PLL is enabled */
6197         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6198         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6199         mdiv |= ((bestn << DPIO_N_SHIFT));
6200         mdiv |= (1 << DPIO_K_SHIFT);
6201
6202         /*
6203          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6204          * but we don't support that).
6205          * Note: don't use the DAC post divider as it seems unstable.
6206          */
6207         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6208         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6209
6210         mdiv |= DPIO_ENABLE_CALIBRATION;
6211         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6212
6213         /* Set HBR and RBR LPF coefficients */
6214         if (pipe_config->port_clock == 162000 ||
6215             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6216             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6217                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6218                                  0x009f0003);
6219         else
6220                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6221                                  0x00d0000f);
6222
6223         if (pipe_config->has_dp_encoder) {
6224                 /* Use SSC source */
6225                 if (pipe == PIPE_A)
6226                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6227                                          0x0df40000);
6228                 else
6229                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6230                                          0x0df70000);
6231         } else { /* HDMI or VGA */
6232                 /* Use bend source */
6233                 if (pipe == PIPE_A)
6234                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6235                                          0x0df70000);
6236                 else
6237                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6238                                          0x0df40000);
6239         }
6240
6241         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6242         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6243         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6244             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6245                 coreclk |= 0x01000000;
6246         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6247
6248         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6249         mutex_unlock(&dev_priv->dpio_lock);
6250 }
6251
6252 static void chv_update_pll(struct intel_crtc *crtc,
6253                            struct intel_crtc_state *pipe_config)
6254 {
6255         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6256                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6257                 DPLL_VCO_ENABLE;
6258         if (crtc->pipe != PIPE_A)
6259                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6260
6261         pipe_config->dpll_hw_state.dpll_md =
6262                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6263 }
6264
6265 static void chv_prepare_pll(struct intel_crtc *crtc,
6266                             const struct intel_crtc_state *pipe_config)
6267 {
6268         struct drm_device *dev = crtc->base.dev;
6269         struct drm_i915_private *dev_priv = dev->dev_private;
6270         int pipe = crtc->pipe;
6271         int dpll_reg = DPLL(crtc->pipe);
6272         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6273         u32 loopfilter, tribuf_calcntr;
6274         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6275         u32 dpio_val;
6276         int vco;
6277
6278         bestn = pipe_config->dpll.n;
6279         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6280         bestm1 = pipe_config->dpll.m1;
6281         bestm2 = pipe_config->dpll.m2 >> 22;
6282         bestp1 = pipe_config->dpll.p1;
6283         bestp2 = pipe_config->dpll.p2;
6284         vco = pipe_config->dpll.vco;
6285         dpio_val = 0;
6286         loopfilter = 0;
6287
6288         /*
6289          * Enable Refclk and SSC
6290          */
6291         I915_WRITE(dpll_reg,
6292                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6293
6294         mutex_lock(&dev_priv->dpio_lock);
6295
6296         /* p1 and p2 divider */
6297         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6298                         5 << DPIO_CHV_S1_DIV_SHIFT |
6299                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6300                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6301                         1 << DPIO_CHV_K_DIV_SHIFT);
6302
6303         /* Feedback post-divider - m2 */
6304         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6305
6306         /* Feedback refclk divider - n and m1 */
6307         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6308                         DPIO_CHV_M1_DIV_BY_2 |
6309                         1 << DPIO_CHV_N_DIV_SHIFT);
6310
6311         /* M2 fraction division */
6312         if (bestm2_frac)
6313                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6314
6315         /* M2 fraction division enable */
6316         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6317         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6318         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6319         if (bestm2_frac)
6320                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6321         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6322
6323         /* Program digital lock detect threshold */
6324         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6325         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6326                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6327         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6328         if (!bestm2_frac)
6329                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6330         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6331
6332         /* Loop filter */
6333         if (vco == 5400000) {
6334                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6335                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6336                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6337                 tribuf_calcntr = 0x9;
6338         } else if (vco <= 6200000) {
6339                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6340                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6341                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6342                 tribuf_calcntr = 0x9;
6343         } else if (vco <= 6480000) {
6344                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6345                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6346                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6347                 tribuf_calcntr = 0x8;
6348         } else {
6349                 /* Not supported. Apply the same limits as in the max case */
6350                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6351                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6352                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6353                 tribuf_calcntr = 0;
6354         }
6355         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6356
6357         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6358         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6359         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6360         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6361
6362         /* AFC Recal */
6363         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6364                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6365                         DPIO_AFC_RECAL);
6366
6367         mutex_unlock(&dev_priv->dpio_lock);
6368 }
6369
6370 /**
6371  * vlv_force_pll_on - forcibly enable just the PLL
6372  * @dev_priv: i915 private structure
6373  * @pipe: pipe PLL to enable
6374  * @dpll: PLL configuration
6375  *
6376  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6377  * in cases where we need the PLL enabled even when @pipe is not going to
6378  * be enabled.
6379  */
6380 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6381                       const struct dpll *dpll)
6382 {
6383         struct intel_crtc *crtc =
6384                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6385         struct intel_crtc_state pipe_config = {
6386                 .pixel_multiplier = 1,
6387                 .dpll = *dpll,
6388         };
6389
6390         if (IS_CHERRYVIEW(dev)) {
6391                 chv_update_pll(crtc, &pipe_config);
6392                 chv_prepare_pll(crtc, &pipe_config);
6393                 chv_enable_pll(crtc, &pipe_config);
6394         } else {
6395                 vlv_update_pll(crtc, &pipe_config);
6396                 vlv_prepare_pll(crtc, &pipe_config);
6397                 vlv_enable_pll(crtc, &pipe_config);
6398         }
6399 }
6400
6401 /**
6402  * vlv_force_pll_off - forcibly disable just the PLL
6403  * @dev_priv: i915 private structure
6404  * @pipe: pipe PLL to disable
6405  *
6406  * Disable the PLL for @pipe. To be used in cases where we need
6407  * the PLL enabled even when @pipe is not going to be enabled.
6408  */
6409 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6410 {
6411         if (IS_CHERRYVIEW(dev))
6412                 chv_disable_pll(to_i915(dev), pipe);
6413         else
6414                 vlv_disable_pll(to_i915(dev), pipe);
6415 }
6416
6417 static void i9xx_update_pll(struct intel_crtc *crtc,
6418                             struct intel_crtc_state *crtc_state,
6419                             intel_clock_t *reduced_clock,
6420                             int num_connectors)
6421 {
6422         struct drm_device *dev = crtc->base.dev;
6423         struct drm_i915_private *dev_priv = dev->dev_private;
6424         u32 dpll;
6425         bool is_sdvo;
6426         struct dpll *clock = &crtc_state->dpll;
6427
6428         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6429
6430         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6431                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6432
6433         dpll = DPLL_VGA_MODE_DIS;
6434
6435         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6436                 dpll |= DPLLB_MODE_LVDS;
6437         else
6438                 dpll |= DPLLB_MODE_DAC_SERIAL;
6439
6440         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6441                 dpll |= (crtc_state->pixel_multiplier - 1)
6442                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6443         }
6444
6445         if (is_sdvo)
6446                 dpll |= DPLL_SDVO_HIGH_SPEED;
6447
6448         if (crtc_state->has_dp_encoder)
6449                 dpll |= DPLL_SDVO_HIGH_SPEED;
6450
6451         /* compute bitmask from p1 value */
6452         if (IS_PINEVIEW(dev))
6453                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6454         else {
6455                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6456                 if (IS_G4X(dev) && reduced_clock)
6457                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6458         }
6459         switch (clock->p2) {
6460         case 5:
6461                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6462                 break;
6463         case 7:
6464                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6465                 break;
6466         case 10:
6467                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6468                 break;
6469         case 14:
6470                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6471                 break;
6472         }
6473         if (INTEL_INFO(dev)->gen >= 4)
6474                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6475
6476         if (crtc_state->sdvo_tv_clock)
6477                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6478         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6479                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6480                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6481         else
6482                 dpll |= PLL_REF_INPUT_DREFCLK;
6483
6484         dpll |= DPLL_VCO_ENABLE;
6485         crtc_state->dpll_hw_state.dpll = dpll;
6486
6487         if (INTEL_INFO(dev)->gen >= 4) {
6488                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6489                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6490                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6491         }
6492 }
6493
6494 static void i8xx_update_pll(struct intel_crtc *crtc,
6495                             struct intel_crtc_state *crtc_state,
6496                             intel_clock_t *reduced_clock,
6497                             int num_connectors)
6498 {
6499         struct drm_device *dev = crtc->base.dev;
6500         struct drm_i915_private *dev_priv = dev->dev_private;
6501         u32 dpll;
6502         struct dpll *clock = &crtc_state->dpll;
6503
6504         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6505
6506         dpll = DPLL_VGA_MODE_DIS;
6507
6508         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6509                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6510         } else {
6511                 if (clock->p1 == 2)
6512                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6513                 else
6514                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6515                 if (clock->p2 == 4)
6516                         dpll |= PLL_P2_DIVIDE_BY_4;
6517         }
6518
6519         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6520                 dpll |= DPLL_DVO_2X_MODE;
6521
6522         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6523                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6524                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6525         else
6526                 dpll |= PLL_REF_INPUT_DREFCLK;
6527
6528         dpll |= DPLL_VCO_ENABLE;
6529         crtc_state->dpll_hw_state.dpll = dpll;
6530 }
6531
6532 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6533 {
6534         struct drm_device *dev = intel_crtc->base.dev;
6535         struct drm_i915_private *dev_priv = dev->dev_private;
6536         enum pipe pipe = intel_crtc->pipe;
6537         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6538         struct drm_display_mode *adjusted_mode =
6539                 &intel_crtc->config->base.adjusted_mode;
6540         uint32_t crtc_vtotal, crtc_vblank_end;
6541         int vsyncshift = 0;
6542
6543         /* We need to be careful not to changed the adjusted mode, for otherwise
6544          * the hw state checker will get angry at the mismatch. */
6545         crtc_vtotal = adjusted_mode->crtc_vtotal;
6546         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6547
6548         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6549                 /* the chip adds 2 halflines automatically */
6550                 crtc_vtotal -= 1;
6551                 crtc_vblank_end -= 1;
6552
6553                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6554                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6555                 else
6556                         vsyncshift = adjusted_mode->crtc_hsync_start -
6557                                 adjusted_mode->crtc_htotal / 2;
6558                 if (vsyncshift < 0)
6559                         vsyncshift += adjusted_mode->crtc_htotal;
6560         }
6561
6562         if (INTEL_INFO(dev)->gen > 3)
6563                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6564
6565         I915_WRITE(HTOTAL(cpu_transcoder),
6566                    (adjusted_mode->crtc_hdisplay - 1) |
6567                    ((adjusted_mode->crtc_htotal - 1) << 16));
6568         I915_WRITE(HBLANK(cpu_transcoder),
6569                    (adjusted_mode->crtc_hblank_start - 1) |
6570                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6571         I915_WRITE(HSYNC(cpu_transcoder),
6572                    (adjusted_mode->crtc_hsync_start - 1) |
6573                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6574
6575         I915_WRITE(VTOTAL(cpu_transcoder),
6576                    (adjusted_mode->crtc_vdisplay - 1) |
6577                    ((crtc_vtotal - 1) << 16));
6578         I915_WRITE(VBLANK(cpu_transcoder),
6579                    (adjusted_mode->crtc_vblank_start - 1) |
6580                    ((crtc_vblank_end - 1) << 16));
6581         I915_WRITE(VSYNC(cpu_transcoder),
6582                    (adjusted_mode->crtc_vsync_start - 1) |
6583                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6584
6585         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6586          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6587          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6588          * bits. */
6589         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6590             (pipe == PIPE_B || pipe == PIPE_C))
6591                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6592
6593         /* pipesrc controls the size that is scaled from, which should
6594          * always be the user's requested size.
6595          */
6596         I915_WRITE(PIPESRC(pipe),
6597                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6598                    (intel_crtc->config->pipe_src_h - 1));
6599 }
6600
6601 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6602                                    struct intel_crtc_state *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6607         uint32_t tmp;
6608
6609         tmp = I915_READ(HTOTAL(cpu_transcoder));
6610         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6611         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6612         tmp = I915_READ(HBLANK(cpu_transcoder));
6613         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6614         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6615         tmp = I915_READ(HSYNC(cpu_transcoder));
6616         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6617         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6618
6619         tmp = I915_READ(VTOTAL(cpu_transcoder));
6620         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6621         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6622         tmp = I915_READ(VBLANK(cpu_transcoder));
6623         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6624         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6625         tmp = I915_READ(VSYNC(cpu_transcoder));
6626         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6627         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6628
6629         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6630                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6631                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6632                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6633         }
6634
6635         tmp = I915_READ(PIPESRC(crtc->pipe));
6636         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6637         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6638
6639         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6640         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6641 }
6642
6643 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6644                                  struct intel_crtc_state *pipe_config)
6645 {
6646         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6647         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6648         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6649         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6650
6651         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6652         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6653         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6654         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6655
6656         mode->flags = pipe_config->base.adjusted_mode.flags;
6657
6658         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6659         mode->flags |= pipe_config->base.adjusted_mode.flags;
6660 }
6661
6662 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6663 {
6664         struct drm_device *dev = intel_crtc->base.dev;
6665         struct drm_i915_private *dev_priv = dev->dev_private;
6666         uint32_t pipeconf;
6667
6668         pipeconf = 0;
6669
6670         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6671             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6672                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6673
6674         if (intel_crtc->config->double_wide)
6675                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6676
6677         /* only g4x and later have fancy bpc/dither controls */
6678         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6679                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6680                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6681                         pipeconf |= PIPECONF_DITHER_EN |
6682                                     PIPECONF_DITHER_TYPE_SP;
6683
6684                 switch (intel_crtc->config->pipe_bpp) {
6685                 case 18:
6686                         pipeconf |= PIPECONF_6BPC;
6687                         break;
6688                 case 24:
6689                         pipeconf |= PIPECONF_8BPC;
6690                         break;
6691                 case 30:
6692                         pipeconf |= PIPECONF_10BPC;
6693                         break;
6694                 default:
6695                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6696                         BUG();
6697                 }
6698         }
6699
6700         if (HAS_PIPE_CXSR(dev)) {
6701                 if (intel_crtc->lowfreq_avail) {
6702                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6703                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6704                 } else {
6705                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6706                 }
6707         }
6708
6709         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6710                 if (INTEL_INFO(dev)->gen < 4 ||
6711                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6712                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6713                 else
6714                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6715         } else
6716                 pipeconf |= PIPECONF_PROGRESSIVE;
6717
6718         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6719                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6720
6721         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6722         POSTING_READ(PIPECONF(intel_crtc->pipe));
6723 }
6724
6725 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6726                                    struct intel_crtc_state *crtc_state)
6727 {
6728         struct drm_device *dev = crtc->base.dev;
6729         struct drm_i915_private *dev_priv = dev->dev_private;
6730         int refclk, num_connectors = 0;
6731         intel_clock_t clock, reduced_clock;
6732         bool ok, has_reduced_clock = false;
6733         bool is_lvds = false, is_dsi = false;
6734         struct intel_encoder *encoder;
6735         const intel_limit_t *limit;
6736
6737         for_each_intel_encoder(dev, encoder) {
6738                 if (encoder->new_crtc != crtc)
6739                         continue;
6740
6741                 switch (encoder->type) {
6742                 case INTEL_OUTPUT_LVDS:
6743                         is_lvds = true;
6744                         break;
6745                 case INTEL_OUTPUT_DSI:
6746                         is_dsi = true;
6747                         break;
6748                 default:
6749                         break;
6750                 }
6751
6752                 num_connectors++;
6753         }
6754
6755         if (is_dsi)
6756                 return 0;
6757
6758         if (!crtc_state->clock_set) {
6759                 refclk = i9xx_get_refclk(crtc, num_connectors);
6760
6761                 /*
6762                  * Returns a set of divisors for the desired target clock with
6763                  * the given refclk, or FALSE.  The returned values represent
6764                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6765                  * 2) / p1 / p2.
6766                  */
6767                 limit = intel_limit(crtc, refclk);
6768                 ok = dev_priv->display.find_dpll(limit, crtc,
6769                                                  crtc_state->port_clock,
6770                                                  refclk, NULL, &clock);
6771                 if (!ok) {
6772                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6773                         return -EINVAL;
6774                 }
6775
6776                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6777                         /*
6778                          * Ensure we match the reduced clock's P to the target
6779                          * clock.  If the clocks don't match, we can't switch
6780                          * the display clock by using the FP0/FP1. In such case
6781                          * we will disable the LVDS downclock feature.
6782                          */
6783                         has_reduced_clock =
6784                                 dev_priv->display.find_dpll(limit, crtc,
6785                                                             dev_priv->lvds_downclock,
6786                                                             refclk, &clock,
6787                                                             &reduced_clock);
6788                 }
6789                 /* Compat-code for transition, will disappear. */
6790                 crtc_state->dpll.n = clock.n;
6791                 crtc_state->dpll.m1 = clock.m1;
6792                 crtc_state->dpll.m2 = clock.m2;
6793                 crtc_state->dpll.p1 = clock.p1;
6794                 crtc_state->dpll.p2 = clock.p2;
6795         }
6796
6797         if (IS_GEN2(dev)) {
6798                 i8xx_update_pll(crtc, crtc_state,
6799                                 has_reduced_clock ? &reduced_clock : NULL,
6800                                 num_connectors);
6801         } else if (IS_CHERRYVIEW(dev)) {
6802                 chv_update_pll(crtc, crtc_state);
6803         } else if (IS_VALLEYVIEW(dev)) {
6804                 vlv_update_pll(crtc, crtc_state);
6805         } else {
6806                 i9xx_update_pll(crtc, crtc_state,
6807                                 has_reduced_clock ? &reduced_clock : NULL,
6808                                 num_connectors);
6809         }
6810
6811         return 0;
6812 }
6813
6814 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6815                                  struct intel_crtc_state *pipe_config)
6816 {
6817         struct drm_device *dev = crtc->base.dev;
6818         struct drm_i915_private *dev_priv = dev->dev_private;
6819         uint32_t tmp;
6820
6821         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6822                 return;
6823
6824         tmp = I915_READ(PFIT_CONTROL);
6825         if (!(tmp & PFIT_ENABLE))
6826                 return;
6827
6828         /* Check whether the pfit is attached to our pipe. */
6829         if (INTEL_INFO(dev)->gen < 4) {
6830                 if (crtc->pipe != PIPE_B)
6831                         return;
6832         } else {
6833                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6834                         return;
6835         }
6836
6837         pipe_config->gmch_pfit.control = tmp;
6838         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6839         if (INTEL_INFO(dev)->gen < 5)
6840                 pipe_config->gmch_pfit.lvds_border_bits =
6841                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6842 }
6843
6844 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6845                                struct intel_crtc_state *pipe_config)
6846 {
6847         struct drm_device *dev = crtc->base.dev;
6848         struct drm_i915_private *dev_priv = dev->dev_private;
6849         int pipe = pipe_config->cpu_transcoder;
6850         intel_clock_t clock;
6851         u32 mdiv;
6852         int refclk = 100000;
6853
6854         /* In case of MIPI DPLL will not even be used */
6855         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6856                 return;
6857
6858         mutex_lock(&dev_priv->dpio_lock);
6859         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6860         mutex_unlock(&dev_priv->dpio_lock);
6861
6862         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6863         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6864         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6865         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6866         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6867
6868         vlv_clock(refclk, &clock);
6869
6870         /* clock.dot is the fast clock */
6871         pipe_config->port_clock = clock.dot / 5;
6872 }
6873
6874 static void
6875 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6876                               struct intel_initial_plane_config *plane_config)
6877 {
6878         struct drm_device *dev = crtc->base.dev;
6879         struct drm_i915_private *dev_priv = dev->dev_private;
6880         u32 val, base, offset;
6881         int pipe = crtc->pipe, plane = crtc->plane;
6882         int fourcc, pixel_format;
6883         unsigned int aligned_height;
6884         struct drm_framebuffer *fb;
6885         struct intel_framebuffer *intel_fb;
6886
6887         val = I915_READ(DSPCNTR(plane));
6888         if (!(val & DISPLAY_PLANE_ENABLE))
6889                 return;
6890
6891         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6892         if (!intel_fb) {
6893                 DRM_DEBUG_KMS("failed to alloc fb\n");
6894                 return;
6895         }
6896
6897         fb = &intel_fb->base;
6898
6899         if (INTEL_INFO(dev)->gen >= 4) {
6900                 if (val & DISPPLANE_TILED) {
6901                         plane_config->tiling = I915_TILING_X;
6902                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6903                 }
6904         }
6905
6906         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6907         fourcc = i9xx_format_to_fourcc(pixel_format);
6908         fb->pixel_format = fourcc;
6909         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6910
6911         if (INTEL_INFO(dev)->gen >= 4) {
6912                 if (plane_config->tiling)
6913                         offset = I915_READ(DSPTILEOFF(plane));
6914                 else
6915                         offset = I915_READ(DSPLINOFF(plane));
6916                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6917         } else {
6918                 base = I915_READ(DSPADDR(plane));
6919         }
6920         plane_config->base = base;
6921
6922         val = I915_READ(PIPESRC(pipe));
6923         fb->width = ((val >> 16) & 0xfff) + 1;
6924         fb->height = ((val >> 0) & 0xfff) + 1;
6925
6926         val = I915_READ(DSPSTRIDE(pipe));
6927         fb->pitches[0] = val & 0xffffffc0;
6928
6929         aligned_height = intel_fb_align_height(dev, fb->height,
6930                                                fb->pixel_format,
6931                                                fb->modifier[0]);
6932
6933         plane_config->size = fb->pitches[0] * aligned_height;
6934
6935         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6936                       pipe_name(pipe), plane, fb->width, fb->height,
6937                       fb->bits_per_pixel, base, fb->pitches[0],
6938                       plane_config->size);
6939
6940         plane_config->fb = intel_fb;
6941 }
6942
6943 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6944                                struct intel_crtc_state *pipe_config)
6945 {
6946         struct drm_device *dev = crtc->base.dev;
6947         struct drm_i915_private *dev_priv = dev->dev_private;
6948         int pipe = pipe_config->cpu_transcoder;
6949         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6950         intel_clock_t clock;
6951         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6952         int refclk = 100000;
6953
6954         mutex_lock(&dev_priv->dpio_lock);
6955         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6956         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6957         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6958         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6959         mutex_unlock(&dev_priv->dpio_lock);
6960
6961         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6962         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6963         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6964         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6965         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6966
6967         chv_clock(refclk, &clock);
6968
6969         /* clock.dot is the fast clock */
6970         pipe_config->port_clock = clock.dot / 5;
6971 }
6972
6973 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6974                                  struct intel_crtc_state *pipe_config)
6975 {
6976         struct drm_device *dev = crtc->base.dev;
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         uint32_t tmp;
6979
6980         if (!intel_display_power_is_enabled(dev_priv,
6981                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6982                 return false;
6983
6984         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6985         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6986
6987         tmp = I915_READ(PIPECONF(crtc->pipe));
6988         if (!(tmp & PIPECONF_ENABLE))
6989                 return false;
6990
6991         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6992                 switch (tmp & PIPECONF_BPC_MASK) {
6993                 case PIPECONF_6BPC:
6994                         pipe_config->pipe_bpp = 18;
6995                         break;
6996                 case PIPECONF_8BPC:
6997                         pipe_config->pipe_bpp = 24;
6998                         break;
6999                 case PIPECONF_10BPC:
7000                         pipe_config->pipe_bpp = 30;
7001                         break;
7002                 default:
7003                         break;
7004                 }
7005         }
7006
7007         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7008                 pipe_config->limited_color_range = true;
7009
7010         if (INTEL_INFO(dev)->gen < 4)
7011                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7012
7013         intel_get_pipe_timings(crtc, pipe_config);
7014
7015         i9xx_get_pfit_config(crtc, pipe_config);
7016
7017         if (INTEL_INFO(dev)->gen >= 4) {
7018                 tmp = I915_READ(DPLL_MD(crtc->pipe));
7019                 pipe_config->pixel_multiplier =
7020                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7021                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7022                 pipe_config->dpll_hw_state.dpll_md = tmp;
7023         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7024                 tmp = I915_READ(DPLL(crtc->pipe));
7025                 pipe_config->pixel_multiplier =
7026                         ((tmp & SDVO_MULTIPLIER_MASK)
7027                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7028         } else {
7029                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7030                  * port and will be fixed up in the encoder->get_config
7031                  * function. */
7032                 pipe_config->pixel_multiplier = 1;
7033         }
7034         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7035         if (!IS_VALLEYVIEW(dev)) {
7036                 /*
7037                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7038                  * on 830. Filter it out here so that we don't
7039                  * report errors due to that.
7040                  */
7041                 if (IS_I830(dev))
7042                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7043
7044                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7045                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7046         } else {
7047                 /* Mask out read-only status bits. */
7048                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7049                                                      DPLL_PORTC_READY_MASK |
7050                                                      DPLL_PORTB_READY_MASK);
7051         }
7052
7053         if (IS_CHERRYVIEW(dev))
7054                 chv_crtc_clock_get(crtc, pipe_config);
7055         else if (IS_VALLEYVIEW(dev))
7056                 vlv_crtc_clock_get(crtc, pipe_config);
7057         else
7058                 i9xx_crtc_clock_get(crtc, pipe_config);
7059
7060         return true;
7061 }
7062
7063 static void ironlake_init_pch_refclk(struct drm_device *dev)
7064 {
7065         struct drm_i915_private *dev_priv = dev->dev_private;
7066         struct intel_encoder *encoder;
7067         u32 val, final;
7068         bool has_lvds = false;
7069         bool has_cpu_edp = false;
7070         bool has_panel = false;
7071         bool has_ck505 = false;
7072         bool can_ssc = false;
7073
7074         /* We need to take the global config into account */
7075         for_each_intel_encoder(dev, encoder) {
7076                 switch (encoder->type) {
7077                 case INTEL_OUTPUT_LVDS:
7078                         has_panel = true;
7079                         has_lvds = true;
7080                         break;
7081                 case INTEL_OUTPUT_EDP:
7082                         has_panel = true;
7083                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7084                                 has_cpu_edp = true;
7085                         break;
7086                 default:
7087                         break;
7088                 }
7089         }
7090
7091         if (HAS_PCH_IBX(dev)) {
7092                 has_ck505 = dev_priv->vbt.display_clock_mode;
7093                 can_ssc = has_ck505;
7094         } else {
7095                 has_ck505 = false;
7096                 can_ssc = true;
7097         }
7098
7099         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7100                       has_panel, has_lvds, has_ck505);
7101
7102         /* Ironlake: try to setup display ref clock before DPLL
7103          * enabling. This is only under driver's control after
7104          * PCH B stepping, previous chipset stepping should be
7105          * ignoring this setting.
7106          */
7107         val = I915_READ(PCH_DREF_CONTROL);
7108
7109         /* As we must carefully and slowly disable/enable each source in turn,
7110          * compute the final state we want first and check if we need to
7111          * make any changes at all.
7112          */
7113         final = val;
7114         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7115         if (has_ck505)
7116                 final |= DREF_NONSPREAD_CK505_ENABLE;
7117         else
7118                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7119
7120         final &= ~DREF_SSC_SOURCE_MASK;
7121         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7122         final &= ~DREF_SSC1_ENABLE;
7123
7124         if (has_panel) {
7125                 final |= DREF_SSC_SOURCE_ENABLE;
7126
7127                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7128                         final |= DREF_SSC1_ENABLE;
7129
7130                 if (has_cpu_edp) {
7131                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7132                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7133                         else
7134                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7135                 } else
7136                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7137         } else {
7138                 final |= DREF_SSC_SOURCE_DISABLE;
7139                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7140         }
7141
7142         if (final == val)
7143                 return;
7144
7145         /* Always enable nonspread source */
7146         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7147
7148         if (has_ck505)
7149                 val |= DREF_NONSPREAD_CK505_ENABLE;
7150         else
7151                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7152
7153         if (has_panel) {
7154                 val &= ~DREF_SSC_SOURCE_MASK;
7155                 val |= DREF_SSC_SOURCE_ENABLE;
7156
7157                 /* SSC must be turned on before enabling the CPU output  */
7158                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7159                         DRM_DEBUG_KMS("Using SSC on panel\n");
7160                         val |= DREF_SSC1_ENABLE;
7161                 } else
7162                         val &= ~DREF_SSC1_ENABLE;
7163
7164                 /* Get SSC going before enabling the outputs */
7165                 I915_WRITE(PCH_DREF_CONTROL, val);
7166                 POSTING_READ(PCH_DREF_CONTROL);
7167                 udelay(200);
7168
7169                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7170
7171                 /* Enable CPU source on CPU attached eDP */
7172                 if (has_cpu_edp) {
7173                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7174                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7175                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7176                         } else
7177                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7178                 } else
7179                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7180
7181                 I915_WRITE(PCH_DREF_CONTROL, val);
7182                 POSTING_READ(PCH_DREF_CONTROL);
7183                 udelay(200);
7184         } else {
7185                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7186
7187                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7188
7189                 /* Turn off CPU output */
7190                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7191
7192                 I915_WRITE(PCH_DREF_CONTROL, val);
7193                 POSTING_READ(PCH_DREF_CONTROL);
7194                 udelay(200);
7195
7196                 /* Turn off the SSC source */
7197                 val &= ~DREF_SSC_SOURCE_MASK;
7198                 val |= DREF_SSC_SOURCE_DISABLE;
7199
7200                 /* Turn off SSC1 */
7201                 val &= ~DREF_SSC1_ENABLE;
7202
7203                 I915_WRITE(PCH_DREF_CONTROL, val);
7204                 POSTING_READ(PCH_DREF_CONTROL);
7205                 udelay(200);
7206         }
7207
7208         BUG_ON(val != final);
7209 }
7210
7211 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7212 {
7213         uint32_t tmp;
7214
7215         tmp = I915_READ(SOUTH_CHICKEN2);
7216         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7217         I915_WRITE(SOUTH_CHICKEN2, tmp);
7218
7219         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7220                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7221                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7222
7223         tmp = I915_READ(SOUTH_CHICKEN2);
7224         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7225         I915_WRITE(SOUTH_CHICKEN2, tmp);
7226
7227         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7228                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7229                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7230 }
7231
7232 /* WaMPhyProgramming:hsw */
7233 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7234 {
7235         uint32_t tmp;
7236
7237         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7238         tmp &= ~(0xFF << 24);
7239         tmp |= (0x12 << 24);
7240         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7241
7242         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7243         tmp |= (1 << 11);
7244         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7245
7246         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7247         tmp |= (1 << 11);
7248         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7249
7250         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7251         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7252         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7253
7254         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7255         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7256         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7257
7258         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7259         tmp &= ~(7 << 13);
7260         tmp |= (5 << 13);
7261         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7262
7263         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7264         tmp &= ~(7 << 13);
7265         tmp |= (5 << 13);
7266         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7267
7268         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7269         tmp &= ~0xFF;
7270         tmp |= 0x1C;
7271         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7272
7273         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7274         tmp &= ~0xFF;
7275         tmp |= 0x1C;
7276         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7277
7278         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7279         tmp &= ~(0xFF << 16);
7280         tmp |= (0x1C << 16);
7281         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7282
7283         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7284         tmp &= ~(0xFF << 16);
7285         tmp |= (0x1C << 16);
7286         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7287
7288         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7289         tmp |= (1 << 27);
7290         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7291
7292         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7293         tmp |= (1 << 27);
7294         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7295
7296         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7297         tmp &= ~(0xF << 28);
7298         tmp |= (4 << 28);
7299         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7300
7301         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7302         tmp &= ~(0xF << 28);
7303         tmp |= (4 << 28);
7304         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7305 }
7306
7307 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7308  * Programming" based on the parameters passed:
7309  * - Sequence to enable CLKOUT_DP
7310  * - Sequence to enable CLKOUT_DP without spread
7311  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7312  */
7313 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7314                                  bool with_fdi)
7315 {
7316         struct drm_i915_private *dev_priv = dev->dev_private;
7317         uint32_t reg, tmp;
7318
7319         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7320                 with_spread = true;
7321         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7322                  with_fdi, "LP PCH doesn't have FDI\n"))
7323                 with_fdi = false;
7324
7325         mutex_lock(&dev_priv->dpio_lock);
7326
7327         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7328         tmp &= ~SBI_SSCCTL_DISABLE;
7329         tmp |= SBI_SSCCTL_PATHALT;
7330         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7331
7332         udelay(24);
7333
7334         if (with_spread) {
7335                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7336                 tmp &= ~SBI_SSCCTL_PATHALT;
7337                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7338
7339                 if (with_fdi) {
7340                         lpt_reset_fdi_mphy(dev_priv);
7341                         lpt_program_fdi_mphy(dev_priv);
7342                 }
7343         }
7344
7345         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7346                SBI_GEN0 : SBI_DBUFF0;
7347         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7348         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7349         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7350
7351         mutex_unlock(&dev_priv->dpio_lock);
7352 }
7353
7354 /* Sequence to disable CLKOUT_DP */
7355 static void lpt_disable_clkout_dp(struct drm_device *dev)
7356 {
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         uint32_t reg, tmp;
7359
7360         mutex_lock(&dev_priv->dpio_lock);
7361
7362         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7363                SBI_GEN0 : SBI_DBUFF0;
7364         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7365         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7366         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7367
7368         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7369         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7370                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7371                         tmp |= SBI_SSCCTL_PATHALT;
7372                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7373                         udelay(32);
7374                 }
7375                 tmp |= SBI_SSCCTL_DISABLE;
7376                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7377         }
7378
7379         mutex_unlock(&dev_priv->dpio_lock);
7380 }
7381
7382 static void lpt_init_pch_refclk(struct drm_device *dev)
7383 {
7384         struct intel_encoder *encoder;
7385         bool has_vga = false;
7386
7387         for_each_intel_encoder(dev, encoder) {
7388                 switch (encoder->type) {
7389                 case INTEL_OUTPUT_ANALOG:
7390                         has_vga = true;
7391                         break;
7392                 default:
7393                         break;
7394                 }
7395         }
7396
7397         if (has_vga)
7398                 lpt_enable_clkout_dp(dev, true, true);
7399         else
7400                 lpt_disable_clkout_dp(dev);
7401 }
7402
7403 /*
7404  * Initialize reference clocks when the driver loads
7405  */
7406 void intel_init_pch_refclk(struct drm_device *dev)
7407 {
7408         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7409                 ironlake_init_pch_refclk(dev);
7410         else if (HAS_PCH_LPT(dev))
7411                 lpt_init_pch_refclk(dev);
7412 }
7413
7414 static int ironlake_get_refclk(struct drm_crtc *crtc)
7415 {
7416         struct drm_device *dev = crtc->dev;
7417         struct drm_i915_private *dev_priv = dev->dev_private;
7418         struct intel_encoder *encoder;
7419         int num_connectors = 0;
7420         bool is_lvds = false;
7421
7422         for_each_intel_encoder(dev, encoder) {
7423                 if (encoder->new_crtc != to_intel_crtc(crtc))
7424                         continue;
7425
7426                 switch (encoder->type) {
7427                 case INTEL_OUTPUT_LVDS:
7428                         is_lvds = true;
7429                         break;
7430                 default:
7431                         break;
7432                 }
7433                 num_connectors++;
7434         }
7435
7436         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7437                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7438                               dev_priv->vbt.lvds_ssc_freq);
7439                 return dev_priv->vbt.lvds_ssc_freq;
7440         }
7441
7442         return 120000;
7443 }
7444
7445 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7446 {
7447         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7449         int pipe = intel_crtc->pipe;
7450         uint32_t val;
7451
7452         val = 0;
7453
7454         switch (intel_crtc->config->pipe_bpp) {
7455         case 18:
7456                 val |= PIPECONF_6BPC;
7457                 break;
7458         case 24:
7459                 val |= PIPECONF_8BPC;
7460                 break;
7461         case 30:
7462                 val |= PIPECONF_10BPC;
7463                 break;
7464         case 36:
7465                 val |= PIPECONF_12BPC;
7466                 break;
7467         default:
7468                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7469                 BUG();
7470         }
7471
7472         if (intel_crtc->config->dither)
7473                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7474
7475         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7476                 val |= PIPECONF_INTERLACED_ILK;
7477         else
7478                 val |= PIPECONF_PROGRESSIVE;
7479
7480         if (intel_crtc->config->limited_color_range)
7481                 val |= PIPECONF_COLOR_RANGE_SELECT;
7482
7483         I915_WRITE(PIPECONF(pipe), val);
7484         POSTING_READ(PIPECONF(pipe));
7485 }
7486
7487 /*
7488  * Set up the pipe CSC unit.
7489  *
7490  * Currently only full range RGB to limited range RGB conversion
7491  * is supported, but eventually this should handle various
7492  * RGB<->YCbCr scenarios as well.
7493  */
7494 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7495 {
7496         struct drm_device *dev = crtc->dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7499         int pipe = intel_crtc->pipe;
7500         uint16_t coeff = 0x7800; /* 1.0 */
7501
7502         /*
7503          * TODO: Check what kind of values actually come out of the pipe
7504          * with these coeff/postoff values and adjust to get the best
7505          * accuracy. Perhaps we even need to take the bpc value into
7506          * consideration.
7507          */
7508
7509         if (intel_crtc->config->limited_color_range)
7510                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7511
7512         /*
7513          * GY/GU and RY/RU should be the other way around according
7514          * to BSpec, but reality doesn't agree. Just set them up in
7515          * a way that results in the correct picture.
7516          */
7517         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7518         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7519
7520         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7521         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7522
7523         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7524         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7525
7526         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7527         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7528         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7529
7530         if (INTEL_INFO(dev)->gen > 6) {
7531                 uint16_t postoff = 0;
7532
7533                 if (intel_crtc->config->limited_color_range)
7534                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7535
7536                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7537                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7538                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7539
7540                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7541         } else {
7542                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7543
7544                 if (intel_crtc->config->limited_color_range)
7545                         mode |= CSC_BLACK_SCREEN_OFFSET;
7546
7547                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7548         }
7549 }
7550
7551 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7552 {
7553         struct drm_device *dev = crtc->dev;
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7556         enum pipe pipe = intel_crtc->pipe;
7557         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7558         uint32_t val;
7559
7560         val = 0;
7561
7562         if (IS_HASWELL(dev) && intel_crtc->config->dither)
7563                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7564
7565         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7566                 val |= PIPECONF_INTERLACED_ILK;
7567         else
7568                 val |= PIPECONF_PROGRESSIVE;
7569
7570         I915_WRITE(PIPECONF(cpu_transcoder), val);
7571         POSTING_READ(PIPECONF(cpu_transcoder));
7572
7573         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7574         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7575
7576         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7577                 val = 0;
7578
7579                 switch (intel_crtc->config->pipe_bpp) {
7580                 case 18:
7581                         val |= PIPEMISC_DITHER_6_BPC;
7582                         break;
7583                 case 24:
7584                         val |= PIPEMISC_DITHER_8_BPC;
7585                         break;
7586                 case 30:
7587                         val |= PIPEMISC_DITHER_10_BPC;
7588                         break;
7589                 case 36:
7590                         val |= PIPEMISC_DITHER_12_BPC;
7591                         break;
7592                 default:
7593                         /* Case prevented by pipe_config_set_bpp. */
7594                         BUG();
7595                 }
7596
7597                 if (intel_crtc->config->dither)
7598                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7599
7600                 I915_WRITE(PIPEMISC(pipe), val);
7601         }
7602 }
7603
7604 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7605                                     struct intel_crtc_state *crtc_state,
7606                                     intel_clock_t *clock,
7607                                     bool *has_reduced_clock,
7608                                     intel_clock_t *reduced_clock)
7609 {
7610         struct drm_device *dev = crtc->dev;
7611         struct drm_i915_private *dev_priv = dev->dev_private;
7612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7613         int refclk;
7614         const intel_limit_t *limit;
7615         bool ret, is_lvds = false;
7616
7617         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7618
7619         refclk = ironlake_get_refclk(crtc);
7620
7621         /*
7622          * Returns a set of divisors for the desired target clock with the given
7623          * refclk, or FALSE.  The returned values represent the clock equation:
7624          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7625          */
7626         limit = intel_limit(intel_crtc, refclk);
7627         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7628                                           crtc_state->port_clock,
7629                                           refclk, NULL, clock);
7630         if (!ret)
7631                 return false;
7632
7633         if (is_lvds && dev_priv->lvds_downclock_avail) {
7634                 /*
7635                  * Ensure we match the reduced clock's P to the target clock.
7636                  * If the clocks don't match, we can't switch the display clock
7637                  * by using the FP0/FP1. In such case we will disable the LVDS
7638                  * downclock feature.
7639                 */
7640                 *has_reduced_clock =
7641                         dev_priv->display.find_dpll(limit, intel_crtc,
7642                                                     dev_priv->lvds_downclock,
7643                                                     refclk, clock,
7644                                                     reduced_clock);
7645         }
7646
7647         return true;
7648 }
7649
7650 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7651 {
7652         /*
7653          * Account for spread spectrum to avoid
7654          * oversubscribing the link. Max center spread
7655          * is 2.5%; use 5% for safety's sake.
7656          */
7657         u32 bps = target_clock * bpp * 21 / 20;
7658         return DIV_ROUND_UP(bps, link_bw * 8);
7659 }
7660
7661 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7662 {
7663         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7664 }
7665
7666 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7667                                       struct intel_crtc_state *crtc_state,
7668                                       u32 *fp,
7669                                       intel_clock_t *reduced_clock, u32 *fp2)
7670 {
7671         struct drm_crtc *crtc = &intel_crtc->base;
7672         struct drm_device *dev = crtc->dev;
7673         struct drm_i915_private *dev_priv = dev->dev_private;
7674         struct intel_encoder *intel_encoder;
7675         uint32_t dpll;
7676         int factor, num_connectors = 0;
7677         bool is_lvds = false, is_sdvo = false;
7678
7679         for_each_intel_encoder(dev, intel_encoder) {
7680                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7681                         continue;
7682
7683                 switch (intel_encoder->type) {
7684                 case INTEL_OUTPUT_LVDS:
7685                         is_lvds = true;
7686                         break;
7687                 case INTEL_OUTPUT_SDVO:
7688                 case INTEL_OUTPUT_HDMI:
7689                         is_sdvo = true;
7690                         break;
7691                 default:
7692                         break;
7693                 }
7694
7695                 num_connectors++;
7696         }
7697
7698         /* Enable autotuning of the PLL clock (if permissible) */
7699         factor = 21;
7700         if (is_lvds) {
7701                 if ((intel_panel_use_ssc(dev_priv) &&
7702                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7703                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7704                         factor = 25;
7705         } else if (crtc_state->sdvo_tv_clock)
7706                 factor = 20;
7707
7708         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7709                 *fp |= FP_CB_TUNE;
7710
7711         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7712                 *fp2 |= FP_CB_TUNE;
7713
7714         dpll = 0;
7715
7716         if (is_lvds)
7717                 dpll |= DPLLB_MODE_LVDS;
7718         else
7719                 dpll |= DPLLB_MODE_DAC_SERIAL;
7720
7721         dpll |= (crtc_state->pixel_multiplier - 1)
7722                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7723
7724         if (is_sdvo)
7725                 dpll |= DPLL_SDVO_HIGH_SPEED;
7726         if (crtc_state->has_dp_encoder)
7727                 dpll |= DPLL_SDVO_HIGH_SPEED;
7728
7729         /* compute bitmask from p1 value */
7730         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7731         /* also FPA1 */
7732         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7733
7734         switch (crtc_state->dpll.p2) {
7735         case 5:
7736                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7737                 break;
7738         case 7:
7739                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7740                 break;
7741         case 10:
7742                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7743                 break;
7744         case 14:
7745                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7746                 break;
7747         }
7748
7749         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7750                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7751         else
7752                 dpll |= PLL_REF_INPUT_DREFCLK;
7753
7754         return dpll | DPLL_VCO_ENABLE;
7755 }
7756
7757 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7758                                        struct intel_crtc_state *crtc_state)
7759 {
7760         struct drm_device *dev = crtc->base.dev;
7761         intel_clock_t clock, reduced_clock;
7762         u32 dpll = 0, fp = 0, fp2 = 0;
7763         bool ok, has_reduced_clock = false;
7764         bool is_lvds = false;
7765         struct intel_shared_dpll *pll;
7766
7767         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7768
7769         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7770              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7771
7772         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7773                                      &has_reduced_clock, &reduced_clock);
7774         if (!ok && !crtc_state->clock_set) {
7775                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7776                 return -EINVAL;
7777         }
7778         /* Compat-code for transition, will disappear. */
7779         if (!crtc_state->clock_set) {
7780                 crtc_state->dpll.n = clock.n;
7781                 crtc_state->dpll.m1 = clock.m1;
7782                 crtc_state->dpll.m2 = clock.m2;
7783                 crtc_state->dpll.p1 = clock.p1;
7784                 crtc_state->dpll.p2 = clock.p2;
7785         }
7786
7787         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7788         if (crtc_state->has_pch_encoder) {
7789                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7790                 if (has_reduced_clock)
7791                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7792
7793                 dpll = ironlake_compute_dpll(crtc, crtc_state,
7794                                              &fp, &reduced_clock,
7795                                              has_reduced_clock ? &fp2 : NULL);
7796
7797                 crtc_state->dpll_hw_state.dpll = dpll;
7798                 crtc_state->dpll_hw_state.fp0 = fp;
7799                 if (has_reduced_clock)
7800                         crtc_state->dpll_hw_state.fp1 = fp2;
7801                 else
7802                         crtc_state->dpll_hw_state.fp1 = fp;
7803
7804                 pll = intel_get_shared_dpll(crtc, crtc_state);
7805                 if (pll == NULL) {
7806                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7807                                          pipe_name(crtc->pipe));
7808                         return -EINVAL;
7809                 }
7810         }
7811
7812         if (is_lvds && has_reduced_clock)
7813                 crtc->lowfreq_avail = true;
7814         else
7815                 crtc->lowfreq_avail = false;
7816
7817         return 0;
7818 }
7819
7820 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7821                                          struct intel_link_m_n *m_n)
7822 {
7823         struct drm_device *dev = crtc->base.dev;
7824         struct drm_i915_private *dev_priv = dev->dev_private;
7825         enum pipe pipe = crtc->pipe;
7826
7827         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7828         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7829         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7830                 & ~TU_SIZE_MASK;
7831         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7832         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7833                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7834 }
7835
7836 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7837                                          enum transcoder transcoder,
7838                                          struct intel_link_m_n *m_n,
7839                                          struct intel_link_m_n *m2_n2)
7840 {
7841         struct drm_device *dev = crtc->base.dev;
7842         struct drm_i915_private *dev_priv = dev->dev_private;
7843         enum pipe pipe = crtc->pipe;
7844
7845         if (INTEL_INFO(dev)->gen >= 5) {
7846                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7847                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7848                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7849                         & ~TU_SIZE_MASK;
7850                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7851                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7852                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7853                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7854                  * gen < 8) and if DRRS is supported (to make sure the
7855                  * registers are not unnecessarily read).
7856                  */
7857                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7858                         crtc->config->has_drrs) {
7859                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7860                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7861                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7862                                         & ~TU_SIZE_MASK;
7863                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7864                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7865                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7866                 }
7867         } else {
7868                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7869                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7870                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7871                         & ~TU_SIZE_MASK;
7872                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7873                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7874                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7875         }
7876 }
7877
7878 void intel_dp_get_m_n(struct intel_crtc *crtc,
7879                       struct intel_crtc_state *pipe_config)
7880 {
7881         if (pipe_config->has_pch_encoder)
7882                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7883         else
7884                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7885                                              &pipe_config->dp_m_n,
7886                                              &pipe_config->dp_m2_n2);
7887 }
7888
7889 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7890                                         struct intel_crtc_state *pipe_config)
7891 {
7892         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7893                                      &pipe_config->fdi_m_n, NULL);
7894 }
7895
7896 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7897                                     struct intel_crtc_state *pipe_config)
7898 {
7899         struct drm_device *dev = crtc->base.dev;
7900         struct drm_i915_private *dev_priv = dev->dev_private;
7901         uint32_t tmp;
7902
7903         tmp = I915_READ(PS_CTL(crtc->pipe));
7904
7905         if (tmp & PS_ENABLE) {
7906                 pipe_config->pch_pfit.enabled = true;
7907                 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7908                 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7909         }
7910 }
7911
7912 static void
7913 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7914                                  struct intel_initial_plane_config *plane_config)
7915 {
7916         struct drm_device *dev = crtc->base.dev;
7917         struct drm_i915_private *dev_priv = dev->dev_private;
7918         u32 val, base, offset, stride_mult, tiling;
7919         int pipe = crtc->pipe;
7920         int fourcc, pixel_format;
7921         unsigned int aligned_height;
7922         struct drm_framebuffer *fb;
7923         struct intel_framebuffer *intel_fb;
7924
7925         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7926         if (!intel_fb) {
7927                 DRM_DEBUG_KMS("failed to alloc fb\n");
7928                 return;
7929         }
7930
7931         fb = &intel_fb->base;
7932
7933         val = I915_READ(PLANE_CTL(pipe, 0));
7934         if (!(val & PLANE_CTL_ENABLE))
7935                 goto error;
7936
7937         pixel_format = val & PLANE_CTL_FORMAT_MASK;
7938         fourcc = skl_format_to_fourcc(pixel_format,
7939                                       val & PLANE_CTL_ORDER_RGBX,
7940                                       val & PLANE_CTL_ALPHA_MASK);
7941         fb->pixel_format = fourcc;
7942         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7943
7944         tiling = val & PLANE_CTL_TILED_MASK;
7945         switch (tiling) {
7946         case PLANE_CTL_TILED_LINEAR:
7947                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7948                 break;
7949         case PLANE_CTL_TILED_X:
7950                 plane_config->tiling = I915_TILING_X;
7951                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7952                 break;
7953         case PLANE_CTL_TILED_Y:
7954                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7955                 break;
7956         case PLANE_CTL_TILED_YF:
7957                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7958                 break;
7959         default:
7960                 MISSING_CASE(tiling);
7961                 goto error;
7962         }
7963
7964         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7965         plane_config->base = base;
7966
7967         offset = I915_READ(PLANE_OFFSET(pipe, 0));
7968
7969         val = I915_READ(PLANE_SIZE(pipe, 0));
7970         fb->height = ((val >> 16) & 0xfff) + 1;
7971         fb->width = ((val >> 0) & 0x1fff) + 1;
7972
7973         val = I915_READ(PLANE_STRIDE(pipe, 0));
7974         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7975                                                 fb->pixel_format);
7976         fb->pitches[0] = (val & 0x3ff) * stride_mult;
7977
7978         aligned_height = intel_fb_align_height(dev, fb->height,
7979                                                fb->pixel_format,
7980                                                fb->modifier[0]);
7981
7982         plane_config->size = fb->pitches[0] * aligned_height;
7983
7984         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7985                       pipe_name(pipe), fb->width, fb->height,
7986                       fb->bits_per_pixel, base, fb->pitches[0],
7987                       plane_config->size);
7988
7989         plane_config->fb = intel_fb;
7990         return;
7991
7992 error:
7993         kfree(fb);
7994 }
7995
7996 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7997                                      struct intel_crtc_state *pipe_config)
7998 {
7999         struct drm_device *dev = crtc->base.dev;
8000         struct drm_i915_private *dev_priv = dev->dev_private;
8001         uint32_t tmp;
8002
8003         tmp = I915_READ(PF_CTL(crtc->pipe));
8004
8005         if (tmp & PF_ENABLE) {
8006                 pipe_config->pch_pfit.enabled = true;
8007                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8008                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8009
8010                 /* We currently do not free assignements of panel fitters on
8011                  * ivb/hsw (since we don't use the higher upscaling modes which
8012                  * differentiates them) so just WARN about this case for now. */
8013                 if (IS_GEN7(dev)) {
8014                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8015                                 PF_PIPE_SEL_IVB(crtc->pipe));
8016                 }
8017         }
8018 }
8019
8020 static void
8021 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8022                                   struct intel_initial_plane_config *plane_config)
8023 {
8024         struct drm_device *dev = crtc->base.dev;
8025         struct drm_i915_private *dev_priv = dev->dev_private;
8026         u32 val, base, offset;
8027         int pipe = crtc->pipe;
8028         int fourcc, pixel_format;
8029         unsigned int aligned_height;
8030         struct drm_framebuffer *fb;
8031         struct intel_framebuffer *intel_fb;
8032
8033         val = I915_READ(DSPCNTR(pipe));
8034         if (!(val & DISPLAY_PLANE_ENABLE))
8035                 return;
8036
8037         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8038         if (!intel_fb) {
8039                 DRM_DEBUG_KMS("failed to alloc fb\n");
8040                 return;
8041         }
8042
8043         fb = &intel_fb->base;
8044
8045         if (INTEL_INFO(dev)->gen >= 4) {
8046                 if (val & DISPPLANE_TILED) {
8047                         plane_config->tiling = I915_TILING_X;
8048                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8049                 }
8050         }
8051
8052         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8053         fourcc = i9xx_format_to_fourcc(pixel_format);
8054         fb->pixel_format = fourcc;
8055         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8056
8057         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8058         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8059                 offset = I915_READ(DSPOFFSET(pipe));
8060         } else {
8061                 if (plane_config->tiling)
8062                         offset = I915_READ(DSPTILEOFF(pipe));
8063                 else
8064                         offset = I915_READ(DSPLINOFF(pipe));
8065         }
8066         plane_config->base = base;
8067
8068         val = I915_READ(PIPESRC(pipe));
8069         fb->width = ((val >> 16) & 0xfff) + 1;
8070         fb->height = ((val >> 0) & 0xfff) + 1;
8071
8072         val = I915_READ(DSPSTRIDE(pipe));
8073         fb->pitches[0] = val & 0xffffffc0;
8074
8075         aligned_height = intel_fb_align_height(dev, fb->height,
8076                                                fb->pixel_format,
8077                                                fb->modifier[0]);
8078
8079         plane_config->size = fb->pitches[0] * aligned_height;
8080
8081         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8082                       pipe_name(pipe), fb->width, fb->height,
8083                       fb->bits_per_pixel, base, fb->pitches[0],
8084                       plane_config->size);
8085
8086         plane_config->fb = intel_fb;
8087 }
8088
8089 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8090                                      struct intel_crtc_state *pipe_config)
8091 {
8092         struct drm_device *dev = crtc->base.dev;
8093         struct drm_i915_private *dev_priv = dev->dev_private;
8094         uint32_t tmp;
8095
8096         if (!intel_display_power_is_enabled(dev_priv,
8097                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8098                 return false;
8099
8100         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8101         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8102
8103         tmp = I915_READ(PIPECONF(crtc->pipe));
8104         if (!(tmp & PIPECONF_ENABLE))
8105                 return false;
8106
8107         switch (tmp & PIPECONF_BPC_MASK) {
8108         case PIPECONF_6BPC:
8109                 pipe_config->pipe_bpp = 18;
8110                 break;
8111         case PIPECONF_8BPC:
8112                 pipe_config->pipe_bpp = 24;
8113                 break;
8114         case PIPECONF_10BPC:
8115                 pipe_config->pipe_bpp = 30;
8116                 break;
8117         case PIPECONF_12BPC:
8118                 pipe_config->pipe_bpp = 36;
8119                 break;
8120         default:
8121                 break;
8122         }
8123
8124         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8125                 pipe_config->limited_color_range = true;
8126
8127         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8128                 struct intel_shared_dpll *pll;
8129
8130                 pipe_config->has_pch_encoder = true;
8131
8132                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8133                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8134                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8135
8136                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8137
8138                 if (HAS_PCH_IBX(dev_priv->dev)) {
8139                         pipe_config->shared_dpll =
8140                                 (enum intel_dpll_id) crtc->pipe;
8141                 } else {
8142                         tmp = I915_READ(PCH_DPLL_SEL);
8143                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8144                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8145                         else
8146                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8147                 }
8148
8149                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8150
8151                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8152                                            &pipe_config->dpll_hw_state));
8153
8154                 tmp = pipe_config->dpll_hw_state.dpll;
8155                 pipe_config->pixel_multiplier =
8156                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8157                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8158
8159                 ironlake_pch_clock_get(crtc, pipe_config);
8160         } else {
8161                 pipe_config->pixel_multiplier = 1;
8162         }
8163
8164         intel_get_pipe_timings(crtc, pipe_config);
8165
8166         ironlake_get_pfit_config(crtc, pipe_config);
8167
8168         return true;
8169 }
8170
8171 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8172 {
8173         struct drm_device *dev = dev_priv->dev;
8174         struct intel_crtc *crtc;
8175
8176         for_each_intel_crtc(dev, crtc)
8177                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8178                      pipe_name(crtc->pipe));
8179
8180         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8181         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8182         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8183         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8184         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8185         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8186              "CPU PWM1 enabled\n");
8187         if (IS_HASWELL(dev))
8188                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8189                      "CPU PWM2 enabled\n");
8190         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8191              "PCH PWM1 enabled\n");
8192         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8193              "Utility pin enabled\n");
8194         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8195
8196         /*
8197          * In theory we can still leave IRQs enabled, as long as only the HPD
8198          * interrupts remain enabled. We used to check for that, but since it's
8199          * gen-specific and since we only disable LCPLL after we fully disable
8200          * the interrupts, the check below should be enough.
8201          */
8202         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8203 }
8204
8205 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8206 {
8207         struct drm_device *dev = dev_priv->dev;
8208
8209         if (IS_HASWELL(dev))
8210                 return I915_READ(D_COMP_HSW);
8211         else
8212                 return I915_READ(D_COMP_BDW);
8213 }
8214
8215 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8216 {
8217         struct drm_device *dev = dev_priv->dev;
8218
8219         if (IS_HASWELL(dev)) {
8220                 mutex_lock(&dev_priv->rps.hw_lock);
8221                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8222                                             val))
8223                         DRM_ERROR("Failed to write to D_COMP\n");
8224                 mutex_unlock(&dev_priv->rps.hw_lock);
8225         } else {
8226                 I915_WRITE(D_COMP_BDW, val);
8227                 POSTING_READ(D_COMP_BDW);
8228         }
8229 }
8230
8231 /*
8232  * This function implements pieces of two sequences from BSpec:
8233  * - Sequence for display software to disable LCPLL
8234  * - Sequence for display software to allow package C8+
8235  * The steps implemented here are just the steps that actually touch the LCPLL
8236  * register. Callers should take care of disabling all the display engine
8237  * functions, doing the mode unset, fixing interrupts, etc.
8238  */
8239 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8240                               bool switch_to_fclk, bool allow_power_down)
8241 {
8242         uint32_t val;
8243
8244         assert_can_disable_lcpll(dev_priv);
8245
8246         val = I915_READ(LCPLL_CTL);
8247
8248         if (switch_to_fclk) {
8249                 val |= LCPLL_CD_SOURCE_FCLK;
8250                 I915_WRITE(LCPLL_CTL, val);
8251
8252                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8253                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
8254                         DRM_ERROR("Switching to FCLK failed\n");
8255
8256                 val = I915_READ(LCPLL_CTL);
8257         }
8258
8259         val |= LCPLL_PLL_DISABLE;
8260         I915_WRITE(LCPLL_CTL, val);
8261         POSTING_READ(LCPLL_CTL);
8262
8263         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8264                 DRM_ERROR("LCPLL still locked\n");
8265
8266         val = hsw_read_dcomp(dev_priv);
8267         val |= D_COMP_COMP_DISABLE;
8268         hsw_write_dcomp(dev_priv, val);
8269         ndelay(100);
8270
8271         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8272                      1))
8273                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8274
8275         if (allow_power_down) {
8276                 val = I915_READ(LCPLL_CTL);
8277                 val |= LCPLL_POWER_DOWN_ALLOW;
8278                 I915_WRITE(LCPLL_CTL, val);
8279                 POSTING_READ(LCPLL_CTL);
8280         }
8281 }
8282
8283 /*
8284  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8285  * source.
8286  */
8287 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8288 {
8289         uint32_t val;
8290
8291         val = I915_READ(LCPLL_CTL);
8292
8293         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8294                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8295                 return;
8296
8297         /*
8298          * Make sure we're not on PC8 state before disabling PC8, otherwise
8299          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8300          */
8301         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8302
8303         if (val & LCPLL_POWER_DOWN_ALLOW) {
8304                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8305                 I915_WRITE(LCPLL_CTL, val);
8306                 POSTING_READ(LCPLL_CTL);
8307         }
8308
8309         val = hsw_read_dcomp(dev_priv);
8310         val |= D_COMP_COMP_FORCE;
8311         val &= ~D_COMP_COMP_DISABLE;
8312         hsw_write_dcomp(dev_priv, val);
8313
8314         val = I915_READ(LCPLL_CTL);
8315         val &= ~LCPLL_PLL_DISABLE;
8316         I915_WRITE(LCPLL_CTL, val);
8317
8318         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8319                 DRM_ERROR("LCPLL not locked yet\n");
8320
8321         if (val & LCPLL_CD_SOURCE_FCLK) {
8322                 val = I915_READ(LCPLL_CTL);
8323                 val &= ~LCPLL_CD_SOURCE_FCLK;
8324                 I915_WRITE(LCPLL_CTL, val);
8325
8326                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8327                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8328                         DRM_ERROR("Switching back to LCPLL failed\n");
8329         }
8330
8331         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8332 }
8333
8334 /*
8335  * Package states C8 and deeper are really deep PC states that can only be
8336  * reached when all the devices on the system allow it, so even if the graphics
8337  * device allows PC8+, it doesn't mean the system will actually get to these
8338  * states. Our driver only allows PC8+ when going into runtime PM.
8339  *
8340  * The requirements for PC8+ are that all the outputs are disabled, the power
8341  * well is disabled and most interrupts are disabled, and these are also
8342  * requirements for runtime PM. When these conditions are met, we manually do
8343  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8344  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8345  * hang the machine.
8346  *
8347  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8348  * the state of some registers, so when we come back from PC8+ we need to
8349  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8350  * need to take care of the registers kept by RC6. Notice that this happens even
8351  * if we don't put the device in PCI D3 state (which is what currently happens
8352  * because of the runtime PM support).
8353  *
8354  * For more, read "Display Sequences for Package C8" on the hardware
8355  * documentation.
8356  */
8357 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8358 {
8359         struct drm_device *dev = dev_priv->dev;
8360         uint32_t val;
8361
8362         DRM_DEBUG_KMS("Enabling package C8+\n");
8363
8364         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8365                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8366                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8367                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8368         }
8369
8370         lpt_disable_clkout_dp(dev);
8371         hsw_disable_lcpll(dev_priv, true, true);
8372 }
8373
8374 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8375 {
8376         struct drm_device *dev = dev_priv->dev;
8377         uint32_t val;
8378
8379         DRM_DEBUG_KMS("Disabling package C8+\n");
8380
8381         hsw_restore_lcpll(dev_priv);
8382         lpt_init_pch_refclk(dev);
8383
8384         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8385                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8386                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8387                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8388         }
8389
8390         intel_prepare_ddi(dev);
8391 }
8392
8393 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8394                                       struct intel_crtc_state *crtc_state)
8395 {
8396         if (!intel_ddi_pll_select(crtc, crtc_state))
8397                 return -EINVAL;
8398
8399         crtc->lowfreq_avail = false;
8400
8401         return 0;
8402 }
8403
8404 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8405                                 enum port port,
8406                                 struct intel_crtc_state *pipe_config)
8407 {
8408         u32 temp, dpll_ctl1;
8409
8410         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8411         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8412
8413         switch (pipe_config->ddi_pll_sel) {
8414         case SKL_DPLL0:
8415                 /*
8416                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8417                  * of the shared DPLL framework and thus needs to be read out
8418                  * separately
8419                  */
8420                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8421                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8422                 break;
8423         case SKL_DPLL1:
8424                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8425                 break;
8426         case SKL_DPLL2:
8427                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8428                 break;
8429         case SKL_DPLL3:
8430                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8431                 break;
8432         }
8433 }
8434
8435 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8436                                 enum port port,
8437                                 struct intel_crtc_state *pipe_config)
8438 {
8439         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8440
8441         switch (pipe_config->ddi_pll_sel) {
8442         case PORT_CLK_SEL_WRPLL1:
8443                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8444                 break;
8445         case PORT_CLK_SEL_WRPLL2:
8446                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8447                 break;
8448         }
8449 }
8450
8451 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8452                                        struct intel_crtc_state *pipe_config)
8453 {
8454         struct drm_device *dev = crtc->base.dev;
8455         struct drm_i915_private *dev_priv = dev->dev_private;
8456         struct intel_shared_dpll *pll;
8457         enum port port;
8458         uint32_t tmp;
8459
8460         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8461
8462         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8463
8464         if (IS_SKYLAKE(dev))
8465                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8466         else
8467                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8468
8469         if (pipe_config->shared_dpll >= 0) {
8470                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8471
8472                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8473                                            &pipe_config->dpll_hw_state));
8474         }
8475
8476         /*
8477          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8478          * DDI E. So just check whether this pipe is wired to DDI E and whether
8479          * the PCH transcoder is on.
8480          */
8481         if (INTEL_INFO(dev)->gen < 9 &&
8482             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8483                 pipe_config->has_pch_encoder = true;
8484
8485                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8486                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8487                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8488
8489                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8490         }
8491 }
8492
8493 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8494                                     struct intel_crtc_state *pipe_config)
8495 {
8496         struct drm_device *dev = crtc->base.dev;
8497         struct drm_i915_private *dev_priv = dev->dev_private;
8498         enum intel_display_power_domain pfit_domain;
8499         uint32_t tmp;
8500
8501         if (!intel_display_power_is_enabled(dev_priv,
8502                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8503                 return false;
8504
8505         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8506         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8507
8508         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8509         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8510                 enum pipe trans_edp_pipe;
8511                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8512                 default:
8513                         WARN(1, "unknown pipe linked to edp transcoder\n");
8514                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8515                 case TRANS_DDI_EDP_INPUT_A_ON:
8516                         trans_edp_pipe = PIPE_A;
8517                         break;
8518                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8519                         trans_edp_pipe = PIPE_B;
8520                         break;
8521                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8522                         trans_edp_pipe = PIPE_C;
8523                         break;
8524                 }
8525
8526                 if (trans_edp_pipe == crtc->pipe)
8527                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8528         }
8529
8530         if (!intel_display_power_is_enabled(dev_priv,
8531                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8532                 return false;
8533
8534         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8535         if (!(tmp & PIPECONF_ENABLE))
8536                 return false;
8537
8538         haswell_get_ddi_port_state(crtc, pipe_config);
8539
8540         intel_get_pipe_timings(crtc, pipe_config);
8541
8542         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8543         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8544                 if (IS_SKYLAKE(dev))
8545                         skylake_get_pfit_config(crtc, pipe_config);
8546                 else
8547                         ironlake_get_pfit_config(crtc, pipe_config);
8548         }
8549
8550         if (IS_HASWELL(dev))
8551                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8552                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8553
8554         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8555                 pipe_config->pixel_multiplier =
8556                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8557         } else {
8558                 pipe_config->pixel_multiplier = 1;
8559         }
8560
8561         return true;
8562 }
8563
8564 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8565 {
8566         struct drm_device *dev = crtc->dev;
8567         struct drm_i915_private *dev_priv = dev->dev_private;
8568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569         uint32_t cntl = 0, size = 0;
8570
8571         if (base) {
8572                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8573                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8574                 unsigned int stride = roundup_pow_of_two(width) * 4;
8575
8576                 switch (stride) {
8577                 default:
8578                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8579                                   width, stride);
8580                         stride = 256;
8581                         /* fallthrough */
8582                 case 256:
8583                 case 512:
8584                 case 1024:
8585                 case 2048:
8586                         break;
8587                 }
8588
8589                 cntl |= CURSOR_ENABLE |
8590                         CURSOR_GAMMA_ENABLE |
8591                         CURSOR_FORMAT_ARGB |
8592                         CURSOR_STRIDE(stride);
8593
8594                 size = (height << 12) | width;
8595         }
8596
8597         if (intel_crtc->cursor_cntl != 0 &&
8598             (intel_crtc->cursor_base != base ||
8599              intel_crtc->cursor_size != size ||
8600              intel_crtc->cursor_cntl != cntl)) {
8601                 /* On these chipsets we can only modify the base/size/stride
8602                  * whilst the cursor is disabled.
8603                  */
8604                 I915_WRITE(_CURACNTR, 0);
8605                 POSTING_READ(_CURACNTR);
8606                 intel_crtc->cursor_cntl = 0;
8607         }
8608
8609         if (intel_crtc->cursor_base != base) {
8610                 I915_WRITE(_CURABASE, base);
8611                 intel_crtc->cursor_base = base;
8612         }
8613
8614         if (intel_crtc->cursor_size != size) {
8615                 I915_WRITE(CURSIZE, size);
8616                 intel_crtc->cursor_size = size;
8617         }
8618
8619         if (intel_crtc->cursor_cntl != cntl) {
8620                 I915_WRITE(_CURACNTR, cntl);
8621                 POSTING_READ(_CURACNTR);
8622                 intel_crtc->cursor_cntl = cntl;
8623         }
8624 }
8625
8626 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8627 {
8628         struct drm_device *dev = crtc->dev;
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8631         int pipe = intel_crtc->pipe;
8632         uint32_t cntl;
8633
8634         cntl = 0;
8635         if (base) {
8636                 cntl = MCURSOR_GAMMA_ENABLE;
8637                 switch (intel_crtc->base.cursor->state->crtc_w) {
8638                         case 64:
8639                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8640                                 break;
8641                         case 128:
8642                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8643                                 break;
8644                         case 256:
8645                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8646                                 break;
8647                         default:
8648                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8649                                 return;
8650                 }
8651                 cntl |= pipe << 28; /* Connect to correct pipe */
8652
8653                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8654                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8655         }
8656
8657         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8658                 cntl |= CURSOR_ROTATE_180;
8659
8660         if (intel_crtc->cursor_cntl != cntl) {
8661                 I915_WRITE(CURCNTR(pipe), cntl);
8662                 POSTING_READ(CURCNTR(pipe));
8663                 intel_crtc->cursor_cntl = cntl;
8664         }
8665
8666         /* and commit changes on next vblank */
8667         I915_WRITE(CURBASE(pipe), base);
8668         POSTING_READ(CURBASE(pipe));
8669
8670         intel_crtc->cursor_base = base;
8671 }
8672
8673 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8674 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8675                                      bool on)
8676 {
8677         struct drm_device *dev = crtc->dev;
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8680         int pipe = intel_crtc->pipe;
8681         int x = crtc->cursor_x;
8682         int y = crtc->cursor_y;
8683         u32 base = 0, pos = 0;
8684
8685         if (on)
8686                 base = intel_crtc->cursor_addr;
8687
8688         if (x >= intel_crtc->config->pipe_src_w)
8689                 base = 0;
8690
8691         if (y >= intel_crtc->config->pipe_src_h)
8692                 base = 0;
8693
8694         if (x < 0) {
8695                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8696                         base = 0;
8697
8698                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8699                 x = -x;
8700         }
8701         pos |= x << CURSOR_X_SHIFT;
8702
8703         if (y < 0) {
8704                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8705                         base = 0;
8706
8707                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8708                 y = -y;
8709         }
8710         pos |= y << CURSOR_Y_SHIFT;
8711
8712         if (base == 0 && intel_crtc->cursor_base == 0)
8713                 return;
8714
8715         I915_WRITE(CURPOS(pipe), pos);
8716
8717         /* ILK+ do this automagically */
8718         if (HAS_GMCH_DISPLAY(dev) &&
8719             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8720                 base += (intel_crtc->base.cursor->state->crtc_h *
8721                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8722         }
8723
8724         if (IS_845G(dev) || IS_I865G(dev))
8725                 i845_update_cursor(crtc, base);
8726         else
8727                 i9xx_update_cursor(crtc, base);
8728 }
8729
8730 static bool cursor_size_ok(struct drm_device *dev,
8731                            uint32_t width, uint32_t height)
8732 {
8733         if (width == 0 || height == 0)
8734                 return false;
8735
8736         /*
8737          * 845g/865g are special in that they are only limited by
8738          * the width of their cursors, the height is arbitrary up to
8739          * the precision of the register. Everything else requires
8740          * square cursors, limited to a few power-of-two sizes.
8741          */
8742         if (IS_845G(dev) || IS_I865G(dev)) {
8743                 if ((width & 63) != 0)
8744                         return false;
8745
8746                 if (width > (IS_845G(dev) ? 64 : 512))
8747                         return false;
8748
8749                 if (height > 1023)
8750                         return false;
8751         } else {
8752                 switch (width | height) {
8753                 case 256:
8754                 case 128:
8755                         if (IS_GEN2(dev))
8756                                 return false;
8757                 case 64:
8758                         break;
8759                 default:
8760                         return false;
8761                 }
8762         }
8763
8764         return true;
8765 }
8766
8767 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8768                                  u16 *blue, uint32_t start, uint32_t size)
8769 {
8770         int end = (start + size > 256) ? 256 : start + size, i;
8771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8772
8773         for (i = start; i < end; i++) {
8774                 intel_crtc->lut_r[i] = red[i] >> 8;
8775                 intel_crtc->lut_g[i] = green[i] >> 8;
8776                 intel_crtc->lut_b[i] = blue[i] >> 8;
8777         }
8778
8779         intel_crtc_load_lut(crtc);
8780 }
8781
8782 /* VESA 640x480x72Hz mode to set on the pipe */
8783 static struct drm_display_mode load_detect_mode = {
8784         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8785                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8786 };
8787
8788 struct drm_framebuffer *
8789 __intel_framebuffer_create(struct drm_device *dev,
8790                            struct drm_mode_fb_cmd2 *mode_cmd,
8791                            struct drm_i915_gem_object *obj)
8792 {
8793         struct intel_framebuffer *intel_fb;
8794         int ret;
8795
8796         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8797         if (!intel_fb) {
8798                 drm_gem_object_unreference(&obj->base);
8799                 return ERR_PTR(-ENOMEM);
8800         }
8801
8802         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8803         if (ret)
8804                 goto err;
8805
8806         return &intel_fb->base;
8807 err:
8808         drm_gem_object_unreference(&obj->base);
8809         kfree(intel_fb);
8810
8811         return ERR_PTR(ret);
8812 }
8813
8814 static struct drm_framebuffer *
8815 intel_framebuffer_create(struct drm_device *dev,
8816                          struct drm_mode_fb_cmd2 *mode_cmd,
8817                          struct drm_i915_gem_object *obj)
8818 {
8819         struct drm_framebuffer *fb;
8820         int ret;
8821
8822         ret = i915_mutex_lock_interruptible(dev);
8823         if (ret)
8824                 return ERR_PTR(ret);
8825         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8826         mutex_unlock(&dev->struct_mutex);
8827
8828         return fb;
8829 }
8830
8831 static u32
8832 intel_framebuffer_pitch_for_width(int width, int bpp)
8833 {
8834         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8835         return ALIGN(pitch, 64);
8836 }
8837
8838 static u32
8839 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8840 {
8841         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8842         return PAGE_ALIGN(pitch * mode->vdisplay);
8843 }
8844
8845 static struct drm_framebuffer *
8846 intel_framebuffer_create_for_mode(struct drm_device *dev,
8847                                   struct drm_display_mode *mode,
8848                                   int depth, int bpp)
8849 {
8850         struct drm_i915_gem_object *obj;
8851         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8852
8853         obj = i915_gem_alloc_object(dev,
8854                                     intel_framebuffer_size_for_mode(mode, bpp));
8855         if (obj == NULL)
8856                 return ERR_PTR(-ENOMEM);
8857
8858         mode_cmd.width = mode->hdisplay;
8859         mode_cmd.height = mode->vdisplay;
8860         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8861                                                                 bpp);
8862         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8863
8864         return intel_framebuffer_create(dev, &mode_cmd, obj);
8865 }
8866
8867 static struct drm_framebuffer *
8868 mode_fits_in_fbdev(struct drm_device *dev,
8869                    struct drm_display_mode *mode)
8870 {
8871 #ifdef CONFIG_DRM_I915_FBDEV
8872         struct drm_i915_private *dev_priv = dev->dev_private;
8873         struct drm_i915_gem_object *obj;
8874         struct drm_framebuffer *fb;
8875
8876         if (!dev_priv->fbdev)
8877                 return NULL;
8878
8879         if (!dev_priv->fbdev->fb)
8880                 return NULL;
8881
8882         obj = dev_priv->fbdev->fb->obj;
8883         BUG_ON(!obj);
8884
8885         fb = &dev_priv->fbdev->fb->base;
8886         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8887                                                                fb->bits_per_pixel))
8888                 return NULL;
8889
8890         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8891                 return NULL;
8892
8893         return fb;
8894 #else
8895         return NULL;
8896 #endif
8897 }
8898
8899 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8900                                 struct drm_display_mode *mode,
8901                                 struct intel_load_detect_pipe *old,
8902                                 struct drm_modeset_acquire_ctx *ctx)
8903 {
8904         struct intel_crtc *intel_crtc;
8905         struct intel_encoder *intel_encoder =
8906                 intel_attached_encoder(connector);
8907         struct drm_crtc *possible_crtc;
8908         struct drm_encoder *encoder = &intel_encoder->base;
8909         struct drm_crtc *crtc = NULL;
8910         struct drm_device *dev = encoder->dev;
8911         struct drm_framebuffer *fb;
8912         struct drm_mode_config *config = &dev->mode_config;
8913         int ret, i = -1;
8914
8915         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8916                       connector->base.id, connector->name,
8917                       encoder->base.id, encoder->name);
8918
8919 retry:
8920         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8921         if (ret)
8922                 goto fail_unlock;
8923
8924         /*
8925          * Algorithm gets a little messy:
8926          *
8927          *   - if the connector already has an assigned crtc, use it (but make
8928          *     sure it's on first)
8929          *
8930          *   - try to find the first unused crtc that can drive this connector,
8931          *     and use that if we find one
8932          */
8933
8934         /* See if we already have a CRTC for this connector */
8935         if (encoder->crtc) {
8936                 crtc = encoder->crtc;
8937
8938                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8939                 if (ret)
8940                         goto fail_unlock;
8941                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8942                 if (ret)
8943                         goto fail_unlock;
8944
8945                 old->dpms_mode = connector->dpms;
8946                 old->load_detect_temp = false;
8947
8948                 /* Make sure the crtc and connector are running */
8949                 if (connector->dpms != DRM_MODE_DPMS_ON)
8950                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8951
8952                 return true;
8953         }
8954
8955         /* Find an unused one (if possible) */
8956         for_each_crtc(dev, possible_crtc) {
8957                 i++;
8958                 if (!(encoder->possible_crtcs & (1 << i)))
8959                         continue;
8960                 if (possible_crtc->state->enable)
8961                         continue;
8962                 /* This can occur when applying the pipe A quirk on resume. */
8963                 if (to_intel_crtc(possible_crtc)->new_enabled)
8964                         continue;
8965
8966                 crtc = possible_crtc;
8967                 break;
8968         }
8969
8970         /*
8971          * If we didn't find an unused CRTC, don't use any.
8972          */
8973         if (!crtc) {
8974                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8975                 goto fail_unlock;
8976         }
8977
8978         ret = drm_modeset_lock(&crtc->mutex, ctx);
8979         if (ret)
8980                 goto fail_unlock;
8981         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8982         if (ret)
8983                 goto fail_unlock;
8984         intel_encoder->new_crtc = to_intel_crtc(crtc);
8985         to_intel_connector(connector)->new_encoder = intel_encoder;
8986
8987         intel_crtc = to_intel_crtc(crtc);
8988         intel_crtc->new_enabled = true;
8989         intel_crtc->new_config = intel_crtc->config;
8990         old->dpms_mode = connector->dpms;
8991         old->load_detect_temp = true;
8992         old->release_fb = NULL;
8993
8994         if (!mode)
8995                 mode = &load_detect_mode;
8996
8997         /* We need a framebuffer large enough to accommodate all accesses
8998          * that the plane may generate whilst we perform load detection.
8999          * We can not rely on the fbcon either being present (we get called
9000          * during its initialisation to detect all boot displays, or it may
9001          * not even exist) or that it is large enough to satisfy the
9002          * requested mode.
9003          */
9004         fb = mode_fits_in_fbdev(dev, mode);
9005         if (fb == NULL) {
9006                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9007                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9008                 old->release_fb = fb;
9009         } else
9010                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9011         if (IS_ERR(fb)) {
9012                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9013                 goto fail;
9014         }
9015
9016         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
9017                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9018                 if (old->release_fb)
9019                         old->release_fb->funcs->destroy(old->release_fb);
9020                 goto fail;
9021         }
9022         crtc->primary->crtc = crtc;
9023
9024         /* let the connector get through one full cycle before testing */
9025         intel_wait_for_vblank(dev, intel_crtc->pipe);
9026         return true;
9027
9028  fail:
9029         intel_crtc->new_enabled = crtc->state->enable;
9030         if (intel_crtc->new_enabled)
9031                 intel_crtc->new_config = intel_crtc->config;
9032         else
9033                 intel_crtc->new_config = NULL;
9034 fail_unlock:
9035         if (ret == -EDEADLK) {
9036                 drm_modeset_backoff(ctx);
9037                 goto retry;
9038         }
9039
9040         return false;
9041 }
9042
9043 void intel_release_load_detect_pipe(struct drm_connector *connector,
9044                                     struct intel_load_detect_pipe *old)
9045 {
9046         struct intel_encoder *intel_encoder =
9047                 intel_attached_encoder(connector);
9048         struct drm_encoder *encoder = &intel_encoder->base;
9049         struct drm_crtc *crtc = encoder->crtc;
9050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9051
9052         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9053                       connector->base.id, connector->name,
9054                       encoder->base.id, encoder->name);
9055
9056         if (old->load_detect_temp) {
9057                 to_intel_connector(connector)->new_encoder = NULL;
9058                 intel_encoder->new_crtc = NULL;
9059                 intel_crtc->new_enabled = false;
9060                 intel_crtc->new_config = NULL;
9061                 intel_set_mode(crtc, NULL, 0, 0, NULL);
9062
9063                 if (old->release_fb) {
9064                         drm_framebuffer_unregister_private(old->release_fb);
9065                         drm_framebuffer_unreference(old->release_fb);
9066                 }
9067
9068                 return;
9069         }
9070
9071         /* Switch crtc and encoder back off if necessary */
9072         if (old->dpms_mode != DRM_MODE_DPMS_ON)
9073                 connector->funcs->dpms(connector, old->dpms_mode);
9074 }
9075
9076 static int i9xx_pll_refclk(struct drm_device *dev,
9077                            const struct intel_crtc_state *pipe_config)
9078 {
9079         struct drm_i915_private *dev_priv = dev->dev_private;
9080         u32 dpll = pipe_config->dpll_hw_state.dpll;
9081
9082         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9083                 return dev_priv->vbt.lvds_ssc_freq;
9084         else if (HAS_PCH_SPLIT(dev))
9085                 return 120000;
9086         else if (!IS_GEN2(dev))
9087                 return 96000;
9088         else
9089                 return 48000;
9090 }
9091
9092 /* Returns the clock of the currently programmed mode of the given pipe. */
9093 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9094                                 struct intel_crtc_state *pipe_config)
9095 {
9096         struct drm_device *dev = crtc->base.dev;
9097         struct drm_i915_private *dev_priv = dev->dev_private;
9098         int pipe = pipe_config->cpu_transcoder;
9099         u32 dpll = pipe_config->dpll_hw_state.dpll;
9100         u32 fp;
9101         intel_clock_t clock;
9102         int refclk = i9xx_pll_refclk(dev, pipe_config);
9103
9104         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9105                 fp = pipe_config->dpll_hw_state.fp0;
9106         else
9107                 fp = pipe_config->dpll_hw_state.fp1;
9108
9109         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9110         if (IS_PINEVIEW(dev)) {
9111                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9112                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9113         } else {
9114                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9115                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9116         }
9117
9118         if (!IS_GEN2(dev)) {
9119                 if (IS_PINEVIEW(dev))
9120                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9121                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9122                 else
9123                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9124                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9125
9126                 switch (dpll & DPLL_MODE_MASK) {
9127                 case DPLLB_MODE_DAC_SERIAL:
9128                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9129                                 5 : 10;
9130                         break;
9131                 case DPLLB_MODE_LVDS:
9132                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9133                                 7 : 14;
9134                         break;
9135                 default:
9136                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9137                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9138                         return;
9139                 }
9140
9141                 if (IS_PINEVIEW(dev))
9142                         pineview_clock(refclk, &clock);
9143                 else
9144                         i9xx_clock(refclk, &clock);
9145         } else {
9146                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9147                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9148
9149                 if (is_lvds) {
9150                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9151                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9152
9153                         if (lvds & LVDS_CLKB_POWER_UP)
9154                                 clock.p2 = 7;
9155                         else
9156                                 clock.p2 = 14;
9157                 } else {
9158                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9159                                 clock.p1 = 2;
9160                         else {
9161                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9162                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9163                         }
9164                         if (dpll & PLL_P2_DIVIDE_BY_4)
9165                                 clock.p2 = 4;
9166                         else
9167                                 clock.p2 = 2;
9168                 }
9169
9170                 i9xx_clock(refclk, &clock);
9171         }
9172
9173         /*
9174          * This value includes pixel_multiplier. We will use
9175          * port_clock to compute adjusted_mode.crtc_clock in the
9176          * encoder's get_config() function.
9177          */
9178         pipe_config->port_clock = clock.dot;
9179 }
9180
9181 int intel_dotclock_calculate(int link_freq,
9182                              const struct intel_link_m_n *m_n)
9183 {
9184         /*
9185          * The calculation for the data clock is:
9186          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9187          * But we want to avoid losing precison if possible, so:
9188          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9189          *
9190          * and the link clock is simpler:
9191          * link_clock = (m * link_clock) / n
9192          */
9193
9194         if (!m_n->link_n)
9195                 return 0;
9196
9197         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9198 }
9199
9200 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9201                                    struct intel_crtc_state *pipe_config)
9202 {
9203         struct drm_device *dev = crtc->base.dev;
9204
9205         /* read out port_clock from the DPLL */
9206         i9xx_crtc_clock_get(crtc, pipe_config);
9207
9208         /*
9209          * This value does not include pixel_multiplier.
9210          * We will check that port_clock and adjusted_mode.crtc_clock
9211          * agree once we know their relationship in the encoder's
9212          * get_config() function.
9213          */
9214         pipe_config->base.adjusted_mode.crtc_clock =
9215                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9216                                          &pipe_config->fdi_m_n);
9217 }
9218
9219 /** Returns the currently programmed mode of the given pipe. */
9220 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9221                                              struct drm_crtc *crtc)
9222 {
9223         struct drm_i915_private *dev_priv = dev->dev_private;
9224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9225         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9226         struct drm_display_mode *mode;
9227         struct intel_crtc_state pipe_config;
9228         int htot = I915_READ(HTOTAL(cpu_transcoder));
9229         int hsync = I915_READ(HSYNC(cpu_transcoder));
9230         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9231         int vsync = I915_READ(VSYNC(cpu_transcoder));
9232         enum pipe pipe = intel_crtc->pipe;
9233
9234         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9235         if (!mode)
9236                 return NULL;
9237
9238         /*
9239          * Construct a pipe_config sufficient for getting the clock info
9240          * back out of crtc_clock_get.
9241          *
9242          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9243          * to use a real value here instead.
9244          */
9245         pipe_config.cpu_transcoder = (enum transcoder) pipe;
9246         pipe_config.pixel_multiplier = 1;
9247         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9248         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9249         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9250         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9251
9252         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9253         mode->hdisplay = (htot & 0xffff) + 1;
9254         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9255         mode->hsync_start = (hsync & 0xffff) + 1;
9256         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9257         mode->vdisplay = (vtot & 0xffff) + 1;
9258         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9259         mode->vsync_start = (vsync & 0xffff) + 1;
9260         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9261
9262         drm_mode_set_name(mode);
9263
9264         return mode;
9265 }
9266
9267 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9268 {
9269         struct drm_device *dev = crtc->dev;
9270         struct drm_i915_private *dev_priv = dev->dev_private;
9271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9272
9273         if (!HAS_GMCH_DISPLAY(dev))
9274                 return;
9275
9276         if (!dev_priv->lvds_downclock_avail)
9277                 return;
9278
9279         /*
9280          * Since this is called by a timer, we should never get here in
9281          * the manual case.
9282          */
9283         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9284                 int pipe = intel_crtc->pipe;
9285                 int dpll_reg = DPLL(pipe);
9286                 int dpll;
9287
9288                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9289
9290                 assert_panel_unlocked(dev_priv, pipe);
9291
9292                 dpll = I915_READ(dpll_reg);
9293                 dpll |= DISPLAY_RATE_SELECT_FPA1;
9294                 I915_WRITE(dpll_reg, dpll);
9295                 intel_wait_for_vblank(dev, pipe);
9296                 dpll = I915_READ(dpll_reg);
9297                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9298                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9299         }
9300
9301 }
9302
9303 void intel_mark_busy(struct drm_device *dev)
9304 {
9305         struct drm_i915_private *dev_priv = dev->dev_private;
9306
9307         if (dev_priv->mm.busy)
9308                 return;
9309
9310         intel_runtime_pm_get(dev_priv);
9311         i915_update_gfx_val(dev_priv);
9312         if (INTEL_INFO(dev)->gen >= 6)
9313                 gen6_rps_busy(dev_priv);
9314         dev_priv->mm.busy = true;
9315 }
9316
9317 void intel_mark_idle(struct drm_device *dev)
9318 {
9319         struct drm_i915_private *dev_priv = dev->dev_private;
9320         struct drm_crtc *crtc;
9321
9322         if (!dev_priv->mm.busy)
9323                 return;
9324
9325         dev_priv->mm.busy = false;
9326
9327         for_each_crtc(dev, crtc) {
9328                 if (!crtc->primary->fb)
9329                         continue;
9330
9331                 intel_decrease_pllclock(crtc);
9332         }
9333
9334         if (INTEL_INFO(dev)->gen >= 6)
9335                 gen6_rps_idle(dev->dev_private);
9336
9337         intel_runtime_pm_put(dev_priv);
9338 }
9339
9340 static void intel_crtc_set_state(struct intel_crtc *crtc,
9341                                  struct intel_crtc_state *crtc_state)
9342 {
9343         kfree(crtc->config);
9344         crtc->config = crtc_state;
9345         crtc->base.state = &crtc_state->base;
9346 }
9347
9348 static void intel_crtc_destroy(struct drm_crtc *crtc)
9349 {
9350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9351         struct drm_device *dev = crtc->dev;
9352         struct intel_unpin_work *work;
9353
9354         spin_lock_irq(&dev->event_lock);
9355         work = intel_crtc->unpin_work;
9356         intel_crtc->unpin_work = NULL;
9357         spin_unlock_irq(&dev->event_lock);
9358
9359         if (work) {
9360                 cancel_work_sync(&work->work);
9361                 kfree(work);
9362         }
9363
9364         intel_crtc_set_state(intel_crtc, NULL);
9365         drm_crtc_cleanup(crtc);
9366
9367         kfree(intel_crtc);
9368 }
9369
9370 static void intel_unpin_work_fn(struct work_struct *__work)
9371 {
9372         struct intel_unpin_work *work =
9373                 container_of(__work, struct intel_unpin_work, work);
9374         struct drm_device *dev = work->crtc->dev;
9375         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9376
9377         mutex_lock(&dev->struct_mutex);
9378         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9379         drm_gem_object_unreference(&work->pending_flip_obj->base);
9380
9381         intel_fbc_update(dev);
9382
9383         if (work->flip_queued_req)
9384                 i915_gem_request_assign(&work->flip_queued_req, NULL);
9385         mutex_unlock(&dev->struct_mutex);
9386
9387         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9388         drm_framebuffer_unreference(work->old_fb);
9389
9390         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9391         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9392
9393         kfree(work);
9394 }
9395
9396 static void do_intel_finish_page_flip(struct drm_device *dev,
9397                                       struct drm_crtc *crtc)
9398 {
9399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9400         struct intel_unpin_work *work;
9401         unsigned long flags;
9402
9403         /* Ignore early vblank irqs */
9404         if (intel_crtc == NULL)
9405                 return;
9406
9407         /*
9408          * This is called both by irq handlers and the reset code (to complete
9409          * lost pageflips) so needs the full irqsave spinlocks.
9410          */
9411         spin_lock_irqsave(&dev->event_lock, flags);
9412         work = intel_crtc->unpin_work;
9413
9414         /* Ensure we don't miss a work->pending update ... */
9415         smp_rmb();
9416
9417         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9418                 spin_unlock_irqrestore(&dev->event_lock, flags);
9419                 return;
9420         }
9421
9422         page_flip_completed(intel_crtc);
9423
9424         spin_unlock_irqrestore(&dev->event_lock, flags);
9425 }
9426
9427 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9428 {
9429         struct drm_i915_private *dev_priv = dev->dev_private;
9430         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9431
9432         do_intel_finish_page_flip(dev, crtc);
9433 }
9434
9435 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9436 {
9437         struct drm_i915_private *dev_priv = dev->dev_private;
9438         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9439
9440         do_intel_finish_page_flip(dev, crtc);
9441 }
9442
9443 /* Is 'a' after or equal to 'b'? */
9444 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9445 {
9446         return !((a - b) & 0x80000000);
9447 }
9448
9449 static bool page_flip_finished(struct intel_crtc *crtc)
9450 {
9451         struct drm_device *dev = crtc->base.dev;
9452         struct drm_i915_private *dev_priv = dev->dev_private;
9453
9454         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9455             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9456                 return true;
9457
9458         /*
9459          * The relevant registers doen't exist on pre-ctg.
9460          * As the flip done interrupt doesn't trigger for mmio
9461          * flips on gmch platforms, a flip count check isn't
9462          * really needed there. But since ctg has the registers,
9463          * include it in the check anyway.
9464          */
9465         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9466                 return true;
9467
9468         /*
9469          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9470          * used the same base address. In that case the mmio flip might
9471          * have completed, but the CS hasn't even executed the flip yet.
9472          *
9473          * A flip count check isn't enough as the CS might have updated
9474          * the base address just after start of vblank, but before we
9475          * managed to process the interrupt. This means we'd complete the
9476          * CS flip too soon.
9477          *
9478          * Combining both checks should get us a good enough result. It may
9479          * still happen that the CS flip has been executed, but has not
9480          * yet actually completed. But in case the base address is the same
9481          * anyway, we don't really care.
9482          */
9483         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9484                 crtc->unpin_work->gtt_offset &&
9485                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9486                                     crtc->unpin_work->flip_count);
9487 }
9488
9489 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9490 {
9491         struct drm_i915_private *dev_priv = dev->dev_private;
9492         struct intel_crtc *intel_crtc =
9493                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9494         unsigned long flags;
9495
9496
9497         /*
9498          * This is called both by irq handlers and the reset code (to complete
9499          * lost pageflips) so needs the full irqsave spinlocks.
9500          *
9501          * NB: An MMIO update of the plane base pointer will also
9502          * generate a page-flip completion irq, i.e. every modeset
9503          * is also accompanied by a spurious intel_prepare_page_flip().
9504          */
9505         spin_lock_irqsave(&dev->event_lock, flags);
9506         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9507                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9508         spin_unlock_irqrestore(&dev->event_lock, flags);
9509 }
9510
9511 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9512 {
9513         /* Ensure that the work item is consistent when activating it ... */
9514         smp_wmb();
9515         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9516         /* and that it is marked active as soon as the irq could fire. */
9517         smp_wmb();
9518 }
9519
9520 static int intel_gen2_queue_flip(struct drm_device *dev,
9521                                  struct drm_crtc *crtc,
9522                                  struct drm_framebuffer *fb,
9523                                  struct drm_i915_gem_object *obj,
9524                                  struct intel_engine_cs *ring,
9525                                  uint32_t flags)
9526 {
9527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9528         u32 flip_mask;
9529         int ret;
9530
9531         ret = intel_ring_begin(ring, 6);
9532         if (ret)
9533                 return ret;
9534
9535         /* Can't queue multiple flips, so wait for the previous
9536          * one to finish before executing the next.
9537          */
9538         if (intel_crtc->plane)
9539                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9540         else
9541                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9542         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9543         intel_ring_emit(ring, MI_NOOP);
9544         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9545                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9546         intel_ring_emit(ring, fb->pitches[0]);
9547         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9548         intel_ring_emit(ring, 0); /* aux display base address, unused */
9549
9550         intel_mark_page_flip_active(intel_crtc);
9551         __intel_ring_advance(ring);
9552         return 0;
9553 }
9554
9555 static int intel_gen3_queue_flip(struct drm_device *dev,
9556                                  struct drm_crtc *crtc,
9557                                  struct drm_framebuffer *fb,
9558                                  struct drm_i915_gem_object *obj,
9559                                  struct intel_engine_cs *ring,
9560                                  uint32_t flags)
9561 {
9562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9563         u32 flip_mask;
9564         int ret;
9565
9566         ret = intel_ring_begin(ring, 6);
9567         if (ret)
9568                 return ret;
9569
9570         if (intel_crtc->plane)
9571                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9572         else
9573                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9574         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9575         intel_ring_emit(ring, MI_NOOP);
9576         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9577                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9578         intel_ring_emit(ring, fb->pitches[0]);
9579         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9580         intel_ring_emit(ring, MI_NOOP);
9581
9582         intel_mark_page_flip_active(intel_crtc);
9583         __intel_ring_advance(ring);
9584         return 0;
9585 }
9586
9587 static int intel_gen4_queue_flip(struct drm_device *dev,
9588                                  struct drm_crtc *crtc,
9589                                  struct drm_framebuffer *fb,
9590                                  struct drm_i915_gem_object *obj,
9591                                  struct intel_engine_cs *ring,
9592                                  uint32_t flags)
9593 {
9594         struct drm_i915_private *dev_priv = dev->dev_private;
9595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9596         uint32_t pf, pipesrc;
9597         int ret;
9598
9599         ret = intel_ring_begin(ring, 4);
9600         if (ret)
9601                 return ret;
9602
9603         /* i965+ uses the linear or tiled offsets from the
9604          * Display Registers (which do not change across a page-flip)
9605          * so we need only reprogram the base address.
9606          */
9607         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9608                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9609         intel_ring_emit(ring, fb->pitches[0]);
9610         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9611                         obj->tiling_mode);
9612
9613         /* XXX Enabling the panel-fitter across page-flip is so far
9614          * untested on non-native modes, so ignore it for now.
9615          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9616          */
9617         pf = 0;
9618         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9619         intel_ring_emit(ring, pf | pipesrc);
9620
9621         intel_mark_page_flip_active(intel_crtc);
9622         __intel_ring_advance(ring);
9623         return 0;
9624 }
9625
9626 static int intel_gen6_queue_flip(struct drm_device *dev,
9627                                  struct drm_crtc *crtc,
9628                                  struct drm_framebuffer *fb,
9629                                  struct drm_i915_gem_object *obj,
9630                                  struct intel_engine_cs *ring,
9631                                  uint32_t flags)
9632 {
9633         struct drm_i915_private *dev_priv = dev->dev_private;
9634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9635         uint32_t pf, pipesrc;
9636         int ret;
9637
9638         ret = intel_ring_begin(ring, 4);
9639         if (ret)
9640                 return ret;
9641
9642         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9643                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9644         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9645         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9646
9647         /* Contrary to the suggestions in the documentation,
9648          * "Enable Panel Fitter" does not seem to be required when page
9649          * flipping with a non-native mode, and worse causes a normal
9650          * modeset to fail.
9651          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9652          */
9653         pf = 0;
9654         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9655         intel_ring_emit(ring, pf | pipesrc);
9656
9657         intel_mark_page_flip_active(intel_crtc);
9658         __intel_ring_advance(ring);
9659         return 0;
9660 }
9661
9662 static int intel_gen7_queue_flip(struct drm_device *dev,
9663                                  struct drm_crtc *crtc,
9664                                  struct drm_framebuffer *fb,
9665                                  struct drm_i915_gem_object *obj,
9666                                  struct intel_engine_cs *ring,
9667                                  uint32_t flags)
9668 {
9669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9670         uint32_t plane_bit = 0;
9671         int len, ret;
9672
9673         switch (intel_crtc->plane) {
9674         case PLANE_A:
9675                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9676                 break;
9677         case PLANE_B:
9678                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9679                 break;
9680         case PLANE_C:
9681                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9682                 break;
9683         default:
9684                 WARN_ONCE(1, "unknown plane in flip command\n");
9685                 return -ENODEV;
9686         }
9687
9688         len = 4;
9689         if (ring->id == RCS) {
9690                 len += 6;
9691                 /*
9692                  * On Gen 8, SRM is now taking an extra dword to accommodate
9693                  * 48bits addresses, and we need a NOOP for the batch size to
9694                  * stay even.
9695                  */
9696                 if (IS_GEN8(dev))
9697                         len += 2;
9698         }
9699
9700         /*
9701          * BSpec MI_DISPLAY_FLIP for IVB:
9702          * "The full packet must be contained within the same cache line."
9703          *
9704          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9705          * cacheline, if we ever start emitting more commands before
9706          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9707          * then do the cacheline alignment, and finally emit the
9708          * MI_DISPLAY_FLIP.
9709          */
9710         ret = intel_ring_cacheline_align(ring);
9711         if (ret)
9712                 return ret;
9713
9714         ret = intel_ring_begin(ring, len);
9715         if (ret)
9716                 return ret;
9717
9718         /* Unmask the flip-done completion message. Note that the bspec says that
9719          * we should do this for both the BCS and RCS, and that we must not unmask
9720          * more than one flip event at any time (or ensure that one flip message
9721          * can be sent by waiting for flip-done prior to queueing new flips).
9722          * Experimentation says that BCS works despite DERRMR masking all
9723          * flip-done completion events and that unmasking all planes at once
9724          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9725          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9726          */
9727         if (ring->id == RCS) {
9728                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9729                 intel_ring_emit(ring, DERRMR);
9730                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9731                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9732                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9733                 if (IS_GEN8(dev))
9734                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9735                                               MI_SRM_LRM_GLOBAL_GTT);
9736                 else
9737                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9738                                               MI_SRM_LRM_GLOBAL_GTT);
9739                 intel_ring_emit(ring, DERRMR);
9740                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9741                 if (IS_GEN8(dev)) {
9742                         intel_ring_emit(ring, 0);
9743                         intel_ring_emit(ring, MI_NOOP);
9744                 }
9745         }
9746
9747         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9748         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9749         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9750         intel_ring_emit(ring, (MI_NOOP));
9751
9752         intel_mark_page_flip_active(intel_crtc);
9753         __intel_ring_advance(ring);
9754         return 0;
9755 }
9756
9757 static bool use_mmio_flip(struct intel_engine_cs *ring,
9758                           struct drm_i915_gem_object *obj)
9759 {
9760         /*
9761          * This is not being used for older platforms, because
9762          * non-availability of flip done interrupt forces us to use
9763          * CS flips. Older platforms derive flip done using some clever
9764          * tricks involving the flip_pending status bits and vblank irqs.
9765          * So using MMIO flips there would disrupt this mechanism.
9766          */
9767
9768         if (ring == NULL)
9769                 return true;
9770
9771         if (INTEL_INFO(ring->dev)->gen < 5)
9772                 return false;
9773
9774         if (i915.use_mmio_flip < 0)
9775                 return false;
9776         else if (i915.use_mmio_flip > 0)
9777                 return true;
9778         else if (i915.enable_execlists)
9779                 return true;
9780         else
9781                 return ring != i915_gem_request_get_ring(obj->last_read_req);
9782 }
9783
9784 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9785 {
9786         struct drm_device *dev = intel_crtc->base.dev;
9787         struct drm_i915_private *dev_priv = dev->dev_private;
9788         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9789         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9790         struct drm_i915_gem_object *obj = intel_fb->obj;
9791         const enum pipe pipe = intel_crtc->pipe;
9792         u32 ctl, stride;
9793
9794         ctl = I915_READ(PLANE_CTL(pipe, 0));
9795         ctl &= ~PLANE_CTL_TILED_MASK;
9796         if (obj->tiling_mode == I915_TILING_X)
9797                 ctl |= PLANE_CTL_TILED_X;
9798
9799         /*
9800          * The stride is either expressed as a multiple of 64 bytes chunks for
9801          * linear buffers or in number of tiles for tiled buffers.
9802          */
9803         stride = fb->pitches[0] >> 6;
9804         if (obj->tiling_mode == I915_TILING_X)
9805                 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9806
9807         /*
9808          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9809          * PLANE_SURF updates, the update is then guaranteed to be atomic.
9810          */
9811         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9812         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9813
9814         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9815         POSTING_READ(PLANE_SURF(pipe, 0));
9816 }
9817
9818 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9819 {
9820         struct drm_device *dev = intel_crtc->base.dev;
9821         struct drm_i915_private *dev_priv = dev->dev_private;
9822         struct intel_framebuffer *intel_fb =
9823                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9824         struct drm_i915_gem_object *obj = intel_fb->obj;
9825         u32 dspcntr;
9826         u32 reg;
9827
9828         reg = DSPCNTR(intel_crtc->plane);
9829         dspcntr = I915_READ(reg);
9830
9831         if (obj->tiling_mode != I915_TILING_NONE)
9832                 dspcntr |= DISPPLANE_TILED;
9833         else
9834                 dspcntr &= ~DISPPLANE_TILED;
9835
9836         I915_WRITE(reg, dspcntr);
9837
9838         I915_WRITE(DSPSURF(intel_crtc->plane),
9839                    intel_crtc->unpin_work->gtt_offset);
9840         POSTING_READ(DSPSURF(intel_crtc->plane));
9841
9842 }
9843
9844 /*
9845  * XXX: This is the temporary way to update the plane registers until we get
9846  * around to using the usual plane update functions for MMIO flips
9847  */
9848 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9849 {
9850         struct drm_device *dev = intel_crtc->base.dev;
9851         bool atomic_update;
9852         u32 start_vbl_count;
9853
9854         intel_mark_page_flip_active(intel_crtc);
9855
9856         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9857
9858         if (INTEL_INFO(dev)->gen >= 9)
9859                 skl_do_mmio_flip(intel_crtc);
9860         else
9861                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9862                 ilk_do_mmio_flip(intel_crtc);
9863
9864         if (atomic_update)
9865                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9866 }
9867
9868 static void intel_mmio_flip_work_func(struct work_struct *work)
9869 {
9870         struct intel_crtc *crtc =
9871                 container_of(work, struct intel_crtc, mmio_flip.work);
9872         struct intel_mmio_flip *mmio_flip;
9873
9874         mmio_flip = &crtc->mmio_flip;
9875         if (mmio_flip->req)
9876                 WARN_ON(__i915_wait_request(mmio_flip->req,
9877                                             crtc->reset_counter,
9878                                             false, NULL, NULL) != 0);
9879
9880         intel_do_mmio_flip(crtc);
9881         if (mmio_flip->req) {
9882                 mutex_lock(&crtc->base.dev->struct_mutex);
9883                 i915_gem_request_assign(&mmio_flip->req, NULL);
9884                 mutex_unlock(&crtc->base.dev->struct_mutex);
9885         }
9886 }
9887
9888 static int intel_queue_mmio_flip(struct drm_device *dev,
9889                                  struct drm_crtc *crtc,
9890                                  struct drm_framebuffer *fb,
9891                                  struct drm_i915_gem_object *obj,
9892                                  struct intel_engine_cs *ring,
9893                                  uint32_t flags)
9894 {
9895         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9896
9897         i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9898                                 obj->last_write_req);
9899
9900         schedule_work(&intel_crtc->mmio_flip.work);
9901
9902         return 0;
9903 }
9904
9905 static int intel_default_queue_flip(struct drm_device *dev,
9906                                     struct drm_crtc *crtc,
9907                                     struct drm_framebuffer *fb,
9908                                     struct drm_i915_gem_object *obj,
9909                                     struct intel_engine_cs *ring,
9910                                     uint32_t flags)
9911 {
9912         return -ENODEV;
9913 }
9914
9915 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9916                                          struct drm_crtc *crtc)
9917 {
9918         struct drm_i915_private *dev_priv = dev->dev_private;
9919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920         struct intel_unpin_work *work = intel_crtc->unpin_work;
9921         u32 addr;
9922
9923         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9924                 return true;
9925
9926         if (!work->enable_stall_check)
9927                 return false;
9928
9929         if (work->flip_ready_vblank == 0) {
9930                 if (work->flip_queued_req &&
9931                     !i915_gem_request_completed(work->flip_queued_req, true))
9932                         return false;
9933
9934                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9935         }
9936
9937         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9938                 return false;
9939
9940         /* Potential stall - if we see that the flip has happened,
9941          * assume a missed interrupt. */
9942         if (INTEL_INFO(dev)->gen >= 4)
9943                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9944         else
9945                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9946
9947         /* There is a potential issue here with a false positive after a flip
9948          * to the same address. We could address this by checking for a
9949          * non-incrementing frame counter.
9950          */
9951         return addr == work->gtt_offset;
9952 }
9953
9954 void intel_check_page_flip(struct drm_device *dev, int pipe)
9955 {
9956         struct drm_i915_private *dev_priv = dev->dev_private;
9957         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9959
9960         WARN_ON(!in_interrupt());
9961
9962         if (crtc == NULL)
9963                 return;
9964
9965         spin_lock(&dev->event_lock);
9966         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9967                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9968                          intel_crtc->unpin_work->flip_queued_vblank,
9969                          drm_vblank_count(dev, pipe));
9970                 page_flip_completed(intel_crtc);
9971         }
9972         spin_unlock(&dev->event_lock);
9973 }
9974
9975 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9976                                 struct drm_framebuffer *fb,
9977                                 struct drm_pending_vblank_event *event,
9978                                 uint32_t page_flip_flags)
9979 {
9980         struct drm_device *dev = crtc->dev;
9981         struct drm_i915_private *dev_priv = dev->dev_private;
9982         struct drm_framebuffer *old_fb = crtc->primary->fb;
9983         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9985         struct drm_plane *primary = crtc->primary;
9986         enum pipe pipe = intel_crtc->pipe;
9987         struct intel_unpin_work *work;
9988         struct intel_engine_cs *ring;
9989         int ret;
9990
9991         /*
9992          * drm_mode_page_flip_ioctl() should already catch this, but double
9993          * check to be safe.  In the future we may enable pageflipping from
9994          * a disabled primary plane.
9995          */
9996         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9997                 return -EBUSY;
9998
9999         /* Can't change pixel format via MI display flips. */
10000         if (fb->pixel_format != crtc->primary->fb->pixel_format)
10001                 return -EINVAL;
10002
10003         /*
10004          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10005          * Note that pitch changes could also affect these register.
10006          */
10007         if (INTEL_INFO(dev)->gen > 3 &&
10008             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10009              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10010                 return -EINVAL;
10011
10012         if (i915_terminally_wedged(&dev_priv->gpu_error))
10013                 goto out_hang;
10014
10015         work = kzalloc(sizeof(*work), GFP_KERNEL);
10016         if (work == NULL)
10017                 return -ENOMEM;
10018
10019         work->event = event;
10020         work->crtc = crtc;
10021         work->old_fb = old_fb;
10022         INIT_WORK(&work->work, intel_unpin_work_fn);
10023
10024         ret = drm_crtc_vblank_get(crtc);
10025         if (ret)
10026                 goto free_work;
10027
10028         /* We borrow the event spin lock for protecting unpin_work */
10029         spin_lock_irq(&dev->event_lock);
10030         if (intel_crtc->unpin_work) {
10031                 /* Before declaring the flip queue wedged, check if
10032                  * the hardware completed the operation behind our backs.
10033                  */
10034                 if (__intel_pageflip_stall_check(dev, crtc)) {
10035                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10036                         page_flip_completed(intel_crtc);
10037                 } else {
10038                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10039                         spin_unlock_irq(&dev->event_lock);
10040
10041                         drm_crtc_vblank_put(crtc);
10042                         kfree(work);
10043                         return -EBUSY;
10044                 }
10045         }
10046         intel_crtc->unpin_work = work;
10047         spin_unlock_irq(&dev->event_lock);
10048
10049         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10050                 flush_workqueue(dev_priv->wq);
10051
10052         /* Reference the objects for the scheduled work. */
10053         drm_framebuffer_reference(work->old_fb);
10054         drm_gem_object_reference(&obj->base);
10055
10056         crtc->primary->fb = fb;
10057         update_state_fb(crtc->primary);
10058
10059         work->pending_flip_obj = obj;
10060
10061         ret = i915_mutex_lock_interruptible(dev);
10062         if (ret)
10063                 goto cleanup;
10064
10065         atomic_inc(&intel_crtc->unpin_work_count);
10066         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10067
10068         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10069                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10070
10071         if (IS_VALLEYVIEW(dev)) {
10072                 ring = &dev_priv->ring[BCS];
10073                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10074                         /* vlv: DISPLAY_FLIP fails to change tiling */
10075                         ring = NULL;
10076         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10077                 ring = &dev_priv->ring[BCS];
10078         } else if (INTEL_INFO(dev)->gen >= 7) {
10079                 ring = i915_gem_request_get_ring(obj->last_read_req);
10080                 if (ring == NULL || ring->id != RCS)
10081                         ring = &dev_priv->ring[BCS];
10082         } else {
10083                 ring = &dev_priv->ring[RCS];
10084         }
10085
10086         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10087                                          crtc->primary->state, ring);
10088         if (ret)
10089                 goto cleanup_pending;
10090
10091         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10092                                                   + intel_crtc->dspaddr_offset;
10093
10094         if (use_mmio_flip(ring, obj)) {
10095                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10096                                             page_flip_flags);
10097                 if (ret)
10098                         goto cleanup_unpin;
10099
10100                 i915_gem_request_assign(&work->flip_queued_req,
10101                                         obj->last_write_req);
10102         } else {
10103                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10104                                                    page_flip_flags);
10105                 if (ret)
10106                         goto cleanup_unpin;
10107
10108                 i915_gem_request_assign(&work->flip_queued_req,
10109                                         intel_ring_get_request(ring));
10110         }
10111
10112         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10113         work->enable_stall_check = true;
10114
10115         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10116                           INTEL_FRONTBUFFER_PRIMARY(pipe));
10117
10118         intel_fbc_disable(dev);
10119         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10120         mutex_unlock(&dev->struct_mutex);
10121
10122         trace_i915_flip_request(intel_crtc->plane, obj);
10123
10124         return 0;
10125
10126 cleanup_unpin:
10127         intel_unpin_fb_obj(fb, crtc->primary->state);
10128 cleanup_pending:
10129         atomic_dec(&intel_crtc->unpin_work_count);
10130         mutex_unlock(&dev->struct_mutex);
10131 cleanup:
10132         crtc->primary->fb = old_fb;
10133         update_state_fb(crtc->primary);
10134
10135         drm_gem_object_unreference_unlocked(&obj->base);
10136         drm_framebuffer_unreference(work->old_fb);
10137
10138         spin_lock_irq(&dev->event_lock);
10139         intel_crtc->unpin_work = NULL;
10140         spin_unlock_irq(&dev->event_lock);
10141
10142         drm_crtc_vblank_put(crtc);
10143 free_work:
10144         kfree(work);
10145
10146         if (ret == -EIO) {
10147 out_hang:
10148                 ret = intel_plane_restore(primary);
10149                 if (ret == 0 && event) {
10150                         spin_lock_irq(&dev->event_lock);
10151                         drm_send_vblank_event(dev, pipe, event);
10152                         spin_unlock_irq(&dev->event_lock);
10153                 }
10154         }
10155         return ret;
10156 }
10157
10158 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10159         .mode_set_base_atomic = intel_pipe_set_base_atomic,
10160         .load_lut = intel_crtc_load_lut,
10161         .atomic_begin = intel_begin_crtc_commit,
10162         .atomic_flush = intel_finish_crtc_commit,
10163 };
10164
10165 /**
10166  * intel_modeset_update_staged_output_state
10167  *
10168  * Updates the staged output configuration state, e.g. after we've read out the
10169  * current hw state.
10170  */
10171 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10172 {
10173         struct intel_crtc *crtc;
10174         struct intel_encoder *encoder;
10175         struct intel_connector *connector;
10176
10177         for_each_intel_connector(dev, connector) {
10178                 connector->new_encoder =
10179                         to_intel_encoder(connector->base.encoder);
10180         }
10181
10182         for_each_intel_encoder(dev, encoder) {
10183                 encoder->new_crtc =
10184                         to_intel_crtc(encoder->base.crtc);
10185         }
10186
10187         for_each_intel_crtc(dev, crtc) {
10188                 crtc->new_enabled = crtc->base.state->enable;
10189
10190                 if (crtc->new_enabled)
10191                         crtc->new_config = crtc->config;
10192                 else
10193                         crtc->new_config = NULL;
10194         }
10195 }
10196
10197 /**
10198  * intel_modeset_commit_output_state
10199  *
10200  * This function copies the stage display pipe configuration to the real one.
10201  */
10202 static void intel_modeset_commit_output_state(struct drm_device *dev)
10203 {
10204         struct intel_crtc *crtc;
10205         struct intel_encoder *encoder;
10206         struct intel_connector *connector;
10207
10208         for_each_intel_connector(dev, connector) {
10209                 connector->base.encoder = &connector->new_encoder->base;
10210         }
10211
10212         for_each_intel_encoder(dev, encoder) {
10213                 encoder->base.crtc = &encoder->new_crtc->base;
10214         }
10215
10216         for_each_intel_crtc(dev, crtc) {
10217                 crtc->base.state->enable = crtc->new_enabled;
10218                 crtc->base.enabled = crtc->new_enabled;
10219         }
10220 }
10221
10222 static void
10223 connected_sink_compute_bpp(struct intel_connector *connector,
10224                            struct intel_crtc_state *pipe_config)
10225 {
10226         int bpp = pipe_config->pipe_bpp;
10227
10228         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10229                 connector->base.base.id,
10230                 connector->base.name);
10231
10232         /* Don't use an invalid EDID bpc value */
10233         if (connector->base.display_info.bpc &&
10234             connector->base.display_info.bpc * 3 < bpp) {
10235                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10236                               bpp, connector->base.display_info.bpc*3);
10237                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10238         }
10239
10240         /* Clamp bpp to 8 on screens without EDID 1.4 */
10241         if (connector->base.display_info.bpc == 0 && bpp > 24) {
10242                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10243                               bpp);
10244                 pipe_config->pipe_bpp = 24;
10245         }
10246 }
10247
10248 static int
10249 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10250                           struct drm_framebuffer *fb,
10251                           struct intel_crtc_state *pipe_config)
10252 {
10253         struct drm_device *dev = crtc->base.dev;
10254         struct intel_connector *connector;
10255         int bpp;
10256
10257         switch (fb->pixel_format) {
10258         case DRM_FORMAT_C8:
10259                 bpp = 8*3; /* since we go through a colormap */
10260                 break;
10261         case DRM_FORMAT_XRGB1555:
10262         case DRM_FORMAT_ARGB1555:
10263                 /* checked in intel_framebuffer_init already */
10264                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10265                         return -EINVAL;
10266         case DRM_FORMAT_RGB565:
10267                 bpp = 6*3; /* min is 18bpp */
10268                 break;
10269         case DRM_FORMAT_XBGR8888:
10270         case DRM_FORMAT_ABGR8888:
10271                 /* checked in intel_framebuffer_init already */
10272                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10273                         return -EINVAL;
10274         case DRM_FORMAT_XRGB8888:
10275         case DRM_FORMAT_ARGB8888:
10276                 bpp = 8*3;
10277                 break;
10278         case DRM_FORMAT_XRGB2101010:
10279         case DRM_FORMAT_ARGB2101010:
10280         case DRM_FORMAT_XBGR2101010:
10281         case DRM_FORMAT_ABGR2101010:
10282                 /* checked in intel_framebuffer_init already */
10283                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10284                         return -EINVAL;
10285                 bpp = 10*3;
10286                 break;
10287         /* TODO: gen4+ supports 16 bpc floating point, too. */
10288         default:
10289                 DRM_DEBUG_KMS("unsupported depth\n");
10290                 return -EINVAL;
10291         }
10292
10293         pipe_config->pipe_bpp = bpp;
10294
10295         /* Clamp display bpp to EDID value */
10296         for_each_intel_connector(dev, connector) {
10297                 if (!connector->new_encoder ||
10298                     connector->new_encoder->new_crtc != crtc)
10299                         continue;
10300
10301                 connected_sink_compute_bpp(connector, pipe_config);
10302         }
10303
10304         return bpp;
10305 }
10306
10307 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10308 {
10309         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10310                         "type: 0x%x flags: 0x%x\n",
10311                 mode->crtc_clock,
10312                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10313                 mode->crtc_hsync_end, mode->crtc_htotal,
10314                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10315                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10316 }
10317
10318 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10319                                    struct intel_crtc_state *pipe_config,
10320                                    const char *context)
10321 {
10322         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10323                       context, pipe_name(crtc->pipe));
10324
10325         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10326         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10327                       pipe_config->pipe_bpp, pipe_config->dither);
10328         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10329                       pipe_config->has_pch_encoder,
10330                       pipe_config->fdi_lanes,
10331                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10332                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10333                       pipe_config->fdi_m_n.tu);
10334         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10335                       pipe_config->has_dp_encoder,
10336                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10337                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10338                       pipe_config->dp_m_n.tu);
10339
10340         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10341                       pipe_config->has_dp_encoder,
10342                       pipe_config->dp_m2_n2.gmch_m,
10343                       pipe_config->dp_m2_n2.gmch_n,
10344                       pipe_config->dp_m2_n2.link_m,
10345                       pipe_config->dp_m2_n2.link_n,
10346                       pipe_config->dp_m2_n2.tu);
10347
10348         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10349                       pipe_config->has_audio,
10350                       pipe_config->has_infoframe);
10351
10352         DRM_DEBUG_KMS("requested mode:\n");
10353         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10354         DRM_DEBUG_KMS("adjusted mode:\n");
10355         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10356         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10357         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10358         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10359                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10360         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10361                       pipe_config->gmch_pfit.control,
10362                       pipe_config->gmch_pfit.pgm_ratios,
10363                       pipe_config->gmch_pfit.lvds_border_bits);
10364         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10365                       pipe_config->pch_pfit.pos,
10366                       pipe_config->pch_pfit.size,
10367                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10368         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10369         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10370 }
10371
10372 static bool encoders_cloneable(const struct intel_encoder *a,
10373                                const struct intel_encoder *b)
10374 {
10375         /* masks could be asymmetric, so check both ways */
10376         return a == b || (a->cloneable & (1 << b->type) &&
10377                           b->cloneable & (1 << a->type));
10378 }
10379
10380 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10381                                          struct intel_encoder *encoder)
10382 {
10383         struct drm_device *dev = crtc->base.dev;
10384         struct intel_encoder *source_encoder;
10385
10386         for_each_intel_encoder(dev, source_encoder) {
10387                 if (source_encoder->new_crtc != crtc)
10388                         continue;
10389
10390                 if (!encoders_cloneable(encoder, source_encoder))
10391                         return false;
10392         }
10393
10394         return true;
10395 }
10396
10397 static bool check_encoder_cloning(struct intel_crtc *crtc)
10398 {
10399         struct drm_device *dev = crtc->base.dev;
10400         struct intel_encoder *encoder;
10401
10402         for_each_intel_encoder(dev, encoder) {
10403                 if (encoder->new_crtc != crtc)
10404                         continue;
10405
10406                 if (!check_single_encoder_cloning(crtc, encoder))
10407                         return false;
10408         }
10409
10410         return true;
10411 }
10412
10413 static bool check_digital_port_conflicts(struct drm_device *dev)
10414 {
10415         struct intel_connector *connector;
10416         unsigned int used_ports = 0;
10417
10418         /*
10419          * Walk the connector list instead of the encoder
10420          * list to detect the problem on ddi platforms
10421          * where there's just one encoder per digital port.
10422          */
10423         for_each_intel_connector(dev, connector) {
10424                 struct intel_encoder *encoder = connector->new_encoder;
10425
10426                 if (!encoder)
10427                         continue;
10428
10429                 WARN_ON(!encoder->new_crtc);
10430
10431                 switch (encoder->type) {
10432                         unsigned int port_mask;
10433                 case INTEL_OUTPUT_UNKNOWN:
10434                         if (WARN_ON(!HAS_DDI(dev)))
10435                                 break;
10436                 case INTEL_OUTPUT_DISPLAYPORT:
10437                 case INTEL_OUTPUT_HDMI:
10438                 case INTEL_OUTPUT_EDP:
10439                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10440
10441                         /* the same port mustn't appear more than once */
10442                         if (used_ports & port_mask)
10443                                 return false;
10444
10445                         used_ports |= port_mask;
10446                 default:
10447                         break;
10448                 }
10449         }
10450
10451         return true;
10452 }
10453
10454 static struct intel_crtc_state *
10455 intel_modeset_pipe_config(struct drm_crtc *crtc,
10456                           struct drm_framebuffer *fb,
10457                           struct drm_display_mode *mode)
10458 {
10459         struct drm_device *dev = crtc->dev;
10460         struct intel_encoder *encoder;
10461         struct intel_crtc_state *pipe_config;
10462         int plane_bpp, ret = -EINVAL;
10463         bool retry = true;
10464
10465         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10466                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10467                 return ERR_PTR(-EINVAL);
10468         }
10469
10470         if (!check_digital_port_conflicts(dev)) {
10471                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10472                 return ERR_PTR(-EINVAL);
10473         }
10474
10475         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10476         if (!pipe_config)
10477                 return ERR_PTR(-ENOMEM);
10478
10479         pipe_config->base.crtc = crtc;
10480         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10481         drm_mode_copy(&pipe_config->base.mode, mode);
10482
10483         pipe_config->cpu_transcoder =
10484                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10485         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10486
10487         /*
10488          * Sanitize sync polarity flags based on requested ones. If neither
10489          * positive or negative polarity is requested, treat this as meaning
10490          * negative polarity.
10491          */
10492         if (!(pipe_config->base.adjusted_mode.flags &
10493               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10494                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10495
10496         if (!(pipe_config->base.adjusted_mode.flags &
10497               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10498                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10499
10500         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10501          * plane pixel format and any sink constraints into account. Returns the
10502          * source plane bpp so that dithering can be selected on mismatches
10503          * after encoders and crtc also have had their say. */
10504         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10505                                               fb, pipe_config);
10506         if (plane_bpp < 0)
10507                 goto fail;
10508
10509         /*
10510          * Determine the real pipe dimensions. Note that stereo modes can
10511          * increase the actual pipe size due to the frame doubling and
10512          * insertion of additional space for blanks between the frame. This
10513          * is stored in the crtc timings. We use the requested mode to do this
10514          * computation to clearly distinguish it from the adjusted mode, which
10515          * can be changed by the connectors in the below retry loop.
10516          */
10517         drm_crtc_get_hv_timing(&pipe_config->base.mode,
10518                                &pipe_config->pipe_src_w,
10519                                &pipe_config->pipe_src_h);
10520
10521 encoder_retry:
10522         /* Ensure the port clock defaults are reset when retrying. */
10523         pipe_config->port_clock = 0;
10524         pipe_config->pixel_multiplier = 1;
10525
10526         /* Fill in default crtc timings, allow encoders to overwrite them. */
10527         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10528                               CRTC_STEREO_DOUBLE);
10529
10530         /* Pass our mode to the connectors and the CRTC to give them a chance to
10531          * adjust it according to limitations or connector properties, and also
10532          * a chance to reject the mode entirely.
10533          */
10534         for_each_intel_encoder(dev, encoder) {
10535
10536                 if (&encoder->new_crtc->base != crtc)
10537                         continue;
10538
10539                 if (!(encoder->compute_config(encoder, pipe_config))) {
10540                         DRM_DEBUG_KMS("Encoder config failure\n");
10541                         goto fail;
10542                 }
10543         }
10544
10545         /* Set default port clock if not overwritten by the encoder. Needs to be
10546          * done afterwards in case the encoder adjusts the mode. */
10547         if (!pipe_config->port_clock)
10548                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10549                         * pipe_config->pixel_multiplier;
10550
10551         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10552         if (ret < 0) {
10553                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10554                 goto fail;
10555         }
10556
10557         if (ret == RETRY) {
10558                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10559                         ret = -EINVAL;
10560                         goto fail;
10561                 }
10562
10563                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10564                 retry = false;
10565                 goto encoder_retry;
10566         }
10567
10568         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10569         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10570                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10571
10572         return pipe_config;
10573 fail:
10574         kfree(pipe_config);
10575         return ERR_PTR(ret);
10576 }
10577
10578 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10579  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10580 static void
10581 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10582                              unsigned *prepare_pipes, unsigned *disable_pipes)
10583 {
10584         struct intel_crtc *intel_crtc;
10585         struct drm_device *dev = crtc->dev;
10586         struct intel_encoder *encoder;
10587         struct intel_connector *connector;
10588         struct drm_crtc *tmp_crtc;
10589
10590         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10591
10592         /* Check which crtcs have changed outputs connected to them, these need
10593          * to be part of the prepare_pipes mask. We don't (yet) support global
10594          * modeset across multiple crtcs, so modeset_pipes will only have one
10595          * bit set at most. */
10596         for_each_intel_connector(dev, connector) {
10597                 if (connector->base.encoder == &connector->new_encoder->base)
10598                         continue;
10599
10600                 if (connector->base.encoder) {
10601                         tmp_crtc = connector->base.encoder->crtc;
10602
10603                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10604                 }
10605
10606                 if (connector->new_encoder)
10607                         *prepare_pipes |=
10608                                 1 << connector->new_encoder->new_crtc->pipe;
10609         }
10610
10611         for_each_intel_encoder(dev, encoder) {
10612                 if (encoder->base.crtc == &encoder->new_crtc->base)
10613                         continue;
10614
10615                 if (encoder->base.crtc) {
10616                         tmp_crtc = encoder->base.crtc;
10617
10618                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10619                 }
10620
10621                 if (encoder->new_crtc)
10622                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10623         }
10624
10625         /* Check for pipes that will be enabled/disabled ... */
10626         for_each_intel_crtc(dev, intel_crtc) {
10627                 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10628                         continue;
10629
10630                 if (!intel_crtc->new_enabled)
10631                         *disable_pipes |= 1 << intel_crtc->pipe;
10632                 else
10633                         *prepare_pipes |= 1 << intel_crtc->pipe;
10634         }
10635
10636
10637         /* set_mode is also used to update properties on life display pipes. */
10638         intel_crtc = to_intel_crtc(crtc);
10639         if (intel_crtc->new_enabled)
10640                 *prepare_pipes |= 1 << intel_crtc->pipe;
10641
10642         /*
10643          * For simplicity do a full modeset on any pipe where the output routing
10644          * changed. We could be more clever, but that would require us to be
10645          * more careful with calling the relevant encoder->mode_set functions.
10646          */
10647         if (*prepare_pipes)
10648                 *modeset_pipes = *prepare_pipes;
10649
10650         /* ... and mask these out. */
10651         *modeset_pipes &= ~(*disable_pipes);
10652         *prepare_pipes &= ~(*disable_pipes);
10653
10654         /*
10655          * HACK: We don't (yet) fully support global modesets. intel_set_config
10656          * obies this rule, but the modeset restore mode of
10657          * intel_modeset_setup_hw_state does not.
10658          */
10659         *modeset_pipes &= 1 << intel_crtc->pipe;
10660         *prepare_pipes &= 1 << intel_crtc->pipe;
10661
10662         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10663                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10664 }
10665
10666 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10667 {
10668         struct drm_encoder *encoder;
10669         struct drm_device *dev = crtc->dev;
10670
10671         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10672                 if (encoder->crtc == crtc)
10673                         return true;
10674
10675         return false;
10676 }
10677
10678 static void
10679 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10680 {
10681         struct drm_i915_private *dev_priv = dev->dev_private;
10682         struct intel_encoder *intel_encoder;
10683         struct intel_crtc *intel_crtc;
10684         struct drm_connector *connector;
10685
10686         intel_shared_dpll_commit(dev_priv);
10687
10688         for_each_intel_encoder(dev, intel_encoder) {
10689                 if (!intel_encoder->base.crtc)
10690                         continue;
10691
10692                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10693
10694                 if (prepare_pipes & (1 << intel_crtc->pipe))
10695                         intel_encoder->connectors_active = false;
10696         }
10697
10698         intel_modeset_commit_output_state(dev);
10699
10700         /* Double check state. */
10701         for_each_intel_crtc(dev, intel_crtc) {
10702                 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10703                 WARN_ON(intel_crtc->new_config &&
10704                         intel_crtc->new_config != intel_crtc->config);
10705                 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10706         }
10707
10708         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10709                 if (!connector->encoder || !connector->encoder->crtc)
10710                         continue;
10711
10712                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10713
10714                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10715                         struct drm_property *dpms_property =
10716                                 dev->mode_config.dpms_property;
10717
10718                         connector->dpms = DRM_MODE_DPMS_ON;
10719                         drm_object_property_set_value(&connector->base,
10720                                                          dpms_property,
10721                                                          DRM_MODE_DPMS_ON);
10722
10723                         intel_encoder = to_intel_encoder(connector->encoder);
10724                         intel_encoder->connectors_active = true;
10725                 }
10726         }
10727
10728 }
10729
10730 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10731 {
10732         int diff;
10733
10734         if (clock1 == clock2)
10735                 return true;
10736
10737         if (!clock1 || !clock2)
10738                 return false;
10739
10740         diff = abs(clock1 - clock2);
10741
10742         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10743                 return true;
10744
10745         return false;
10746 }
10747
10748 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10749         list_for_each_entry((intel_crtc), \
10750                             &(dev)->mode_config.crtc_list, \
10751                             base.head) \
10752                 if (mask & (1 <<(intel_crtc)->pipe))
10753
10754 static bool
10755 intel_pipe_config_compare(struct drm_device *dev,
10756                           struct intel_crtc_state *current_config,
10757                           struct intel_crtc_state *pipe_config)
10758 {
10759 #define PIPE_CONF_CHECK_X(name) \
10760         if (current_config->name != pipe_config->name) { \
10761                 DRM_ERROR("mismatch in " #name " " \
10762                           "(expected 0x%08x, found 0x%08x)\n", \
10763                           current_config->name, \
10764                           pipe_config->name); \
10765                 return false; \
10766         }
10767
10768 #define PIPE_CONF_CHECK_I(name) \
10769         if (current_config->name != pipe_config->name) { \
10770                 DRM_ERROR("mismatch in " #name " " \
10771                           "(expected %i, found %i)\n", \
10772                           current_config->name, \
10773                           pipe_config->name); \
10774                 return false; \
10775         }
10776
10777 /* This is required for BDW+ where there is only one set of registers for
10778  * switching between high and low RR.
10779  * This macro can be used whenever a comparison has to be made between one
10780  * hw state and multiple sw state variables.
10781  */
10782 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10783         if ((current_config->name != pipe_config->name) && \
10784                 (current_config->alt_name != pipe_config->name)) { \
10785                         DRM_ERROR("mismatch in " #name " " \
10786                                   "(expected %i or %i, found %i)\n", \
10787                                   current_config->name, \
10788                                   current_config->alt_name, \
10789                                   pipe_config->name); \
10790                         return false; \
10791         }
10792
10793 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10794         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10795                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10796                           "(expected %i, found %i)\n", \
10797                           current_config->name & (mask), \
10798                           pipe_config->name & (mask)); \
10799                 return false; \
10800         }
10801
10802 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10803         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10804                 DRM_ERROR("mismatch in " #name " " \
10805                           "(expected %i, found %i)\n", \
10806                           current_config->name, \
10807                           pipe_config->name); \
10808                 return false; \
10809         }
10810
10811 #define PIPE_CONF_QUIRK(quirk)  \
10812         ((current_config->quirks | pipe_config->quirks) & (quirk))
10813
10814         PIPE_CONF_CHECK_I(cpu_transcoder);
10815
10816         PIPE_CONF_CHECK_I(has_pch_encoder);
10817         PIPE_CONF_CHECK_I(fdi_lanes);
10818         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10819         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10820         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10821         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10822         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10823
10824         PIPE_CONF_CHECK_I(has_dp_encoder);
10825
10826         if (INTEL_INFO(dev)->gen < 8) {
10827                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10828                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10829                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10830                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10831                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10832
10833                 if (current_config->has_drrs) {
10834                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10835                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10836                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10837                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10838                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10839                 }
10840         } else {
10841                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10842                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10843                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10844                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10845                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10846         }
10847
10848         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10849         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10850         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10851         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10852         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10853         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10854
10855         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10856         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10857         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10858         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10859         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10860         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10861
10862         PIPE_CONF_CHECK_I(pixel_multiplier);
10863         PIPE_CONF_CHECK_I(has_hdmi_sink);
10864         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10865             IS_VALLEYVIEW(dev))
10866                 PIPE_CONF_CHECK_I(limited_color_range);
10867         PIPE_CONF_CHECK_I(has_infoframe);
10868
10869         PIPE_CONF_CHECK_I(has_audio);
10870
10871         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10872                               DRM_MODE_FLAG_INTERLACE);
10873
10874         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10875                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10876                                       DRM_MODE_FLAG_PHSYNC);
10877                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10878                                       DRM_MODE_FLAG_NHSYNC);
10879                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10880                                       DRM_MODE_FLAG_PVSYNC);
10881                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10882                                       DRM_MODE_FLAG_NVSYNC);
10883         }
10884
10885         PIPE_CONF_CHECK_I(pipe_src_w);
10886         PIPE_CONF_CHECK_I(pipe_src_h);
10887
10888         /*
10889          * FIXME: BIOS likes to set up a cloned config with lvds+external
10890          * screen. Since we don't yet re-compute the pipe config when moving
10891          * just the lvds port away to another pipe the sw tracking won't match.
10892          *
10893          * Proper atomic modesets with recomputed global state will fix this.
10894          * Until then just don't check gmch state for inherited modes.
10895          */
10896         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10897                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10898                 /* pfit ratios are autocomputed by the hw on gen4+ */
10899                 if (INTEL_INFO(dev)->gen < 4)
10900                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10901                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10902         }
10903
10904         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10905         if (current_config->pch_pfit.enabled) {
10906                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10907                 PIPE_CONF_CHECK_I(pch_pfit.size);
10908         }
10909
10910         /* BDW+ don't expose a synchronous way to read the state */
10911         if (IS_HASWELL(dev))
10912                 PIPE_CONF_CHECK_I(ips_enabled);
10913
10914         PIPE_CONF_CHECK_I(double_wide);
10915
10916         PIPE_CONF_CHECK_X(ddi_pll_sel);
10917
10918         PIPE_CONF_CHECK_I(shared_dpll);
10919         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10920         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10921         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10922         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10923         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10924         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10925         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10926         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10927
10928         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10929                 PIPE_CONF_CHECK_I(pipe_bpp);
10930
10931         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10932         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10933
10934 #undef PIPE_CONF_CHECK_X
10935 #undef PIPE_CONF_CHECK_I
10936 #undef PIPE_CONF_CHECK_I_ALT
10937 #undef PIPE_CONF_CHECK_FLAGS
10938 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10939 #undef PIPE_CONF_QUIRK
10940
10941         return true;
10942 }
10943
10944 static void check_wm_state(struct drm_device *dev)
10945 {
10946         struct drm_i915_private *dev_priv = dev->dev_private;
10947         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10948         struct intel_crtc *intel_crtc;
10949         int plane;
10950
10951         if (INTEL_INFO(dev)->gen < 9)
10952                 return;
10953
10954         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10955         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10956
10957         for_each_intel_crtc(dev, intel_crtc) {
10958                 struct skl_ddb_entry *hw_entry, *sw_entry;
10959                 const enum pipe pipe = intel_crtc->pipe;
10960
10961                 if (!intel_crtc->active)
10962                         continue;
10963
10964                 /* planes */
10965                 for_each_plane(dev_priv, pipe, plane) {
10966                         hw_entry = &hw_ddb.plane[pipe][plane];
10967                         sw_entry = &sw_ddb->plane[pipe][plane];
10968
10969                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10970                                 continue;
10971
10972                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10973                                   "(expected (%u,%u), found (%u,%u))\n",
10974                                   pipe_name(pipe), plane + 1,
10975                                   sw_entry->start, sw_entry->end,
10976                                   hw_entry->start, hw_entry->end);
10977                 }
10978
10979                 /* cursor */
10980                 hw_entry = &hw_ddb.cursor[pipe];
10981                 sw_entry = &sw_ddb->cursor[pipe];
10982
10983                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10984                         continue;
10985
10986                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10987                           "(expected (%u,%u), found (%u,%u))\n",
10988                           pipe_name(pipe),
10989                           sw_entry->start, sw_entry->end,
10990                           hw_entry->start, hw_entry->end);
10991         }
10992 }
10993
10994 static void
10995 check_connector_state(struct drm_device *dev)
10996 {
10997         struct intel_connector *connector;
10998
10999         for_each_intel_connector(dev, connector) {
11000                 /* This also checks the encoder/connector hw state with the
11001                  * ->get_hw_state callbacks. */
11002                 intel_connector_check_state(connector);
11003
11004                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11005                      "connector's staged encoder doesn't match current encoder\n");
11006         }
11007 }
11008
11009 static void
11010 check_encoder_state(struct drm_device *dev)
11011 {
11012         struct intel_encoder *encoder;
11013         struct intel_connector *connector;
11014
11015         for_each_intel_encoder(dev, encoder) {
11016                 bool enabled = false;
11017                 bool active = false;
11018                 enum pipe pipe, tracked_pipe;
11019
11020                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11021                               encoder->base.base.id,
11022                               encoder->base.name);
11023
11024                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11025                      "encoder's stage crtc doesn't match current crtc\n");
11026                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11027                      "encoder's active_connectors set, but no crtc\n");
11028
11029                 for_each_intel_connector(dev, connector) {
11030                         if (connector->base.encoder != &encoder->base)
11031                                 continue;
11032                         enabled = true;
11033                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11034                                 active = true;
11035                 }
11036                 /*
11037                  * for MST connectors if we unplug the connector is gone
11038                  * away but the encoder is still connected to a crtc
11039                  * until a modeset happens in response to the hotplug.
11040                  */
11041                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11042                         continue;
11043
11044                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11045                      "encoder's enabled state mismatch "
11046                      "(expected %i, found %i)\n",
11047                      !!encoder->base.crtc, enabled);
11048                 I915_STATE_WARN(active && !encoder->base.crtc,
11049                      "active encoder with no crtc\n");
11050
11051                 I915_STATE_WARN(encoder->connectors_active != active,
11052                      "encoder's computed active state doesn't match tracked active state "
11053                      "(expected %i, found %i)\n", active, encoder->connectors_active);
11054
11055                 active = encoder->get_hw_state(encoder, &pipe);
11056                 I915_STATE_WARN(active != encoder->connectors_active,
11057                      "encoder's hw state doesn't match sw tracking "
11058                      "(expected %i, found %i)\n",
11059                      encoder->connectors_active, active);
11060
11061                 if (!encoder->base.crtc)
11062                         continue;
11063
11064                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11065                 I915_STATE_WARN(active && pipe != tracked_pipe,
11066                      "active encoder's pipe doesn't match"
11067                      "(expected %i, found %i)\n",
11068                      tracked_pipe, pipe);
11069
11070         }
11071 }
11072
11073 static void
11074 check_crtc_state(struct drm_device *dev)
11075 {
11076         struct drm_i915_private *dev_priv = dev->dev_private;
11077         struct intel_crtc *crtc;
11078         struct intel_encoder *encoder;
11079         struct intel_crtc_state pipe_config;
11080
11081         for_each_intel_crtc(dev, crtc) {
11082                 bool enabled = false;
11083                 bool active = false;
11084
11085                 memset(&pipe_config, 0, sizeof(pipe_config));
11086
11087                 DRM_DEBUG_KMS("[CRTC:%d]\n",
11088                               crtc->base.base.id);
11089
11090                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11091                      "active crtc, but not enabled in sw tracking\n");
11092
11093                 for_each_intel_encoder(dev, encoder) {
11094                         if (encoder->base.crtc != &crtc->base)
11095                                 continue;
11096                         enabled = true;
11097                         if (encoder->connectors_active)
11098                                 active = true;
11099                 }
11100
11101                 I915_STATE_WARN(active != crtc->active,
11102                      "crtc's computed active state doesn't match tracked active state "
11103                      "(expected %i, found %i)\n", active, crtc->active);
11104                 I915_STATE_WARN(enabled != crtc->base.state->enable,
11105                      "crtc's computed enabled state doesn't match tracked enabled state "
11106                      "(expected %i, found %i)\n", enabled,
11107                                 crtc->base.state->enable);
11108
11109                 active = dev_priv->display.get_pipe_config(crtc,
11110                                                            &pipe_config);
11111
11112                 /* hw state is inconsistent with the pipe quirk */
11113                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11114                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11115                         active = crtc->active;
11116
11117                 for_each_intel_encoder(dev, encoder) {
11118                         enum pipe pipe;
11119                         if (encoder->base.crtc != &crtc->base)
11120                                 continue;
11121                         if (encoder->get_hw_state(encoder, &pipe))
11122                                 encoder->get_config(encoder, &pipe_config);
11123                 }
11124
11125                 I915_STATE_WARN(crtc->active != active,
11126                      "crtc active state doesn't match with hw state "
11127                      "(expected %i, found %i)\n", crtc->active, active);
11128
11129                 if (active &&
11130                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11131                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
11132                         intel_dump_pipe_config(crtc, &pipe_config,
11133                                                "[hw state]");
11134                         intel_dump_pipe_config(crtc, crtc->config,
11135                                                "[sw state]");
11136                 }
11137         }
11138 }
11139
11140 static void
11141 check_shared_dpll_state(struct drm_device *dev)
11142 {
11143         struct drm_i915_private *dev_priv = dev->dev_private;
11144         struct intel_crtc *crtc;
11145         struct intel_dpll_hw_state dpll_hw_state;
11146         int i;
11147
11148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11149                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11150                 int enabled_crtcs = 0, active_crtcs = 0;
11151                 bool active;
11152
11153                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11154
11155                 DRM_DEBUG_KMS("%s\n", pll->name);
11156
11157                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11158
11159                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11160                      "more active pll users than references: %i vs %i\n",
11161                      pll->active, hweight32(pll->config.crtc_mask));
11162                 I915_STATE_WARN(pll->active && !pll->on,
11163                      "pll in active use but not on in sw tracking\n");
11164                 I915_STATE_WARN(pll->on && !pll->active,
11165                      "pll in on but not on in use in sw tracking\n");
11166                 I915_STATE_WARN(pll->on != active,
11167                      "pll on state mismatch (expected %i, found %i)\n",
11168                      pll->on, active);
11169
11170                 for_each_intel_crtc(dev, crtc) {
11171                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11172                                 enabled_crtcs++;
11173                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11174                                 active_crtcs++;
11175                 }
11176                 I915_STATE_WARN(pll->active != active_crtcs,
11177                      "pll active crtcs mismatch (expected %i, found %i)\n",
11178                      pll->active, active_crtcs);
11179                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11180                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
11181                      hweight32(pll->config.crtc_mask), enabled_crtcs);
11182
11183                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11184                                        sizeof(dpll_hw_state)),
11185                      "pll hw state mismatch\n");
11186         }
11187 }
11188
11189 void
11190 intel_modeset_check_state(struct drm_device *dev)
11191 {
11192         check_wm_state(dev);
11193         check_connector_state(dev);
11194         check_encoder_state(dev);
11195         check_crtc_state(dev);
11196         check_shared_dpll_state(dev);
11197 }
11198
11199 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11200                                      int dotclock)
11201 {
11202         /*
11203          * FDI already provided one idea for the dotclock.
11204          * Yell if the encoder disagrees.
11205          */
11206         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11207              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11208              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11209 }
11210
11211 static void update_scanline_offset(struct intel_crtc *crtc)
11212 {
11213         struct drm_device *dev = crtc->base.dev;
11214
11215         /*
11216          * The scanline counter increments at the leading edge of hsync.
11217          *
11218          * On most platforms it starts counting from vtotal-1 on the
11219          * first active line. That means the scanline counter value is
11220          * always one less than what we would expect. Ie. just after
11221          * start of vblank, which also occurs at start of hsync (on the
11222          * last active line), the scanline counter will read vblank_start-1.
11223          *
11224          * On gen2 the scanline counter starts counting from 1 instead
11225          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11226          * to keep the value positive), instead of adding one.
11227          *
11228          * On HSW+ the behaviour of the scanline counter depends on the output
11229          * type. For DP ports it behaves like most other platforms, but on HDMI
11230          * there's an extra 1 line difference. So we need to add two instead of
11231          * one to the value.
11232          */
11233         if (IS_GEN2(dev)) {
11234                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11235                 int vtotal;
11236
11237                 vtotal = mode->crtc_vtotal;
11238                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11239                         vtotal /= 2;
11240
11241                 crtc->scanline_offset = vtotal - 1;
11242         } else if (HAS_DDI(dev) &&
11243                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11244                 crtc->scanline_offset = 2;
11245         } else
11246                 crtc->scanline_offset = 1;
11247 }
11248
11249 static struct intel_crtc_state *
11250 intel_modeset_compute_config(struct drm_crtc *crtc,
11251                              struct drm_display_mode *mode,
11252                              struct drm_framebuffer *fb,
11253                              unsigned *modeset_pipes,
11254                              unsigned *prepare_pipes,
11255                              unsigned *disable_pipes)
11256 {
11257         struct intel_crtc_state *pipe_config = NULL;
11258
11259         intel_modeset_affected_pipes(crtc, modeset_pipes,
11260                                      prepare_pipes, disable_pipes);
11261
11262         if ((*modeset_pipes) == 0)
11263                 goto out;
11264
11265         /*
11266          * Note this needs changes when we start tracking multiple modes
11267          * and crtcs.  At that point we'll need to compute the whole config
11268          * (i.e. one pipe_config for each crtc) rather than just the one
11269          * for this crtc.
11270          */
11271         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11272         if (IS_ERR(pipe_config)) {
11273                 goto out;
11274         }
11275         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11276                                "[modeset]");
11277
11278 out:
11279         return pipe_config;
11280 }
11281
11282 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11283                                        unsigned modeset_pipes,
11284                                        unsigned disable_pipes)
11285 {
11286         struct drm_i915_private *dev_priv = to_i915(dev);
11287         unsigned clear_pipes = modeset_pipes | disable_pipes;
11288         struct intel_crtc *intel_crtc;
11289         int ret = 0;
11290
11291         if (!dev_priv->display.crtc_compute_clock)
11292                 return 0;
11293
11294         ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11295         if (ret)
11296                 goto done;
11297
11298         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11299                 struct intel_crtc_state *state = intel_crtc->new_config;
11300                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11301                                                            state);
11302                 if (ret) {
11303                         intel_shared_dpll_abort_config(dev_priv);
11304                         goto done;
11305                 }
11306         }
11307
11308 done:
11309         return ret;
11310 }
11311
11312 static int __intel_set_mode(struct drm_crtc *crtc,
11313                             struct drm_display_mode *mode,
11314                             int x, int y, struct drm_framebuffer *fb,
11315                             struct intel_crtc_state *pipe_config,
11316                             unsigned modeset_pipes,
11317                             unsigned prepare_pipes,
11318                             unsigned disable_pipes)
11319 {
11320         struct drm_device *dev = crtc->dev;
11321         struct drm_i915_private *dev_priv = dev->dev_private;
11322         struct drm_display_mode *saved_mode;
11323         struct intel_crtc *intel_crtc;
11324         int ret = 0;
11325
11326         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11327         if (!saved_mode)
11328                 return -ENOMEM;
11329
11330         *saved_mode = crtc->mode;
11331
11332         if (modeset_pipes)
11333                 to_intel_crtc(crtc)->new_config = pipe_config;
11334
11335         /*
11336          * See if the config requires any additional preparation, e.g.
11337          * to adjust global state with pipes off.  We need to do this
11338          * here so we can get the modeset_pipe updated config for the new
11339          * mode set on this crtc.  For other crtcs we need to use the
11340          * adjusted_mode bits in the crtc directly.
11341          */
11342         if (IS_VALLEYVIEW(dev)) {
11343                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11344
11345                 /* may have added more to prepare_pipes than we should */
11346                 prepare_pipes &= ~disable_pipes;
11347         }
11348
11349         ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11350         if (ret)
11351                 goto done;
11352
11353         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11354                 intel_crtc_disable(&intel_crtc->base);
11355
11356         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11357                 if (intel_crtc->base.state->enable)
11358                         dev_priv->display.crtc_disable(&intel_crtc->base);
11359         }
11360
11361         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11362          * to set it here already despite that we pass it down the callchain.
11363          *
11364          * Note we'll need to fix this up when we start tracking multiple
11365          * pipes; here we assume a single modeset_pipe and only track the
11366          * single crtc and mode.
11367          */
11368         if (modeset_pipes) {
11369                 crtc->mode = *mode;
11370                 /* mode_set/enable/disable functions rely on a correct pipe
11371                  * config. */
11372                 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11373
11374                 /*
11375                  * Calculate and store various constants which
11376                  * are later needed by vblank and swap-completion
11377                  * timestamping. They are derived from true hwmode.
11378                  */
11379                 drm_calc_timestamping_constants(crtc,
11380                                                 &pipe_config->base.adjusted_mode);
11381         }
11382
11383         /* Only after disabling all output pipelines that will be changed can we
11384          * update the the output configuration. */
11385         intel_modeset_update_state(dev, prepare_pipes);
11386
11387         modeset_update_crtc_power_domains(dev);
11388
11389         /* Set up the DPLL and any encoders state that needs to adjust or depend
11390          * on the DPLL.
11391          */
11392         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11393                 struct drm_plane *primary = intel_crtc->base.primary;
11394                 int vdisplay, hdisplay;
11395
11396                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11397                 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11398                                                    fb, 0, 0,
11399                                                    hdisplay, vdisplay,
11400                                                    x << 16, y << 16,
11401                                                    hdisplay << 16, vdisplay << 16);
11402         }
11403
11404         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11405         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11406                 update_scanline_offset(intel_crtc);
11407
11408                 dev_priv->display.crtc_enable(&intel_crtc->base);
11409         }
11410
11411         /* FIXME: add subpixel order */
11412 done:
11413         if (ret && crtc->state->enable)
11414                 crtc->mode = *saved_mode;
11415
11416         kfree(saved_mode);
11417         return ret;
11418 }
11419
11420 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11421                                 struct drm_display_mode *mode,
11422                                 int x, int y, struct drm_framebuffer *fb,
11423                                 struct intel_crtc_state *pipe_config,
11424                                 unsigned modeset_pipes,
11425                                 unsigned prepare_pipes,
11426                                 unsigned disable_pipes)
11427 {
11428         int ret;
11429
11430         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11431                                prepare_pipes, disable_pipes);
11432
11433         if (ret == 0)
11434                 intel_modeset_check_state(crtc->dev);
11435
11436         return ret;
11437 }
11438
11439 static int intel_set_mode(struct drm_crtc *crtc,
11440                           struct drm_display_mode *mode,
11441                           int x, int y, struct drm_framebuffer *fb)
11442 {
11443         struct intel_crtc_state *pipe_config;
11444         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11445
11446         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11447                                                    &modeset_pipes,
11448                                                    &prepare_pipes,
11449                                                    &disable_pipes);
11450
11451         if (IS_ERR(pipe_config))
11452                 return PTR_ERR(pipe_config);
11453
11454         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11455                                     modeset_pipes, prepare_pipes,
11456                                     disable_pipes);
11457 }
11458
11459 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11460 {
11461         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11462 }
11463
11464 #undef for_each_intel_crtc_masked
11465
11466 static void intel_set_config_free(struct intel_set_config *config)
11467 {
11468         if (!config)
11469                 return;
11470
11471         kfree(config->save_connector_encoders);
11472         kfree(config->save_encoder_crtcs);
11473         kfree(config->save_crtc_enabled);
11474         kfree(config);
11475 }
11476
11477 static int intel_set_config_save_state(struct drm_device *dev,
11478                                        struct intel_set_config *config)
11479 {
11480         struct drm_crtc *crtc;
11481         struct drm_encoder *encoder;
11482         struct drm_connector *connector;
11483         int count;
11484
11485         config->save_crtc_enabled =
11486                 kcalloc(dev->mode_config.num_crtc,
11487                         sizeof(bool), GFP_KERNEL);
11488         if (!config->save_crtc_enabled)
11489                 return -ENOMEM;
11490
11491         config->save_encoder_crtcs =
11492                 kcalloc(dev->mode_config.num_encoder,
11493                         sizeof(struct drm_crtc *), GFP_KERNEL);
11494         if (!config->save_encoder_crtcs)
11495                 return -ENOMEM;
11496
11497         config->save_connector_encoders =
11498                 kcalloc(dev->mode_config.num_connector,
11499                         sizeof(struct drm_encoder *), GFP_KERNEL);
11500         if (!config->save_connector_encoders)
11501                 return -ENOMEM;
11502
11503         /* Copy data. Note that driver private data is not affected.
11504          * Should anything bad happen only the expected state is
11505          * restored, not the drivers personal bookkeeping.
11506          */
11507         count = 0;
11508         for_each_crtc(dev, crtc) {
11509                 config->save_crtc_enabled[count++] = crtc->state->enable;
11510         }
11511
11512         count = 0;
11513         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11514                 config->save_encoder_crtcs[count++] = encoder->crtc;
11515         }
11516
11517         count = 0;
11518         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11519                 config->save_connector_encoders[count++] = connector->encoder;
11520         }
11521
11522         return 0;
11523 }
11524
11525 static void intel_set_config_restore_state(struct drm_device *dev,
11526                                            struct intel_set_config *config)
11527 {
11528         struct intel_crtc *crtc;
11529         struct intel_encoder *encoder;
11530         struct intel_connector *connector;
11531         int count;
11532
11533         count = 0;
11534         for_each_intel_crtc(dev, crtc) {
11535                 crtc->new_enabled = config->save_crtc_enabled[count++];
11536
11537                 if (crtc->new_enabled)
11538                         crtc->new_config = crtc->config;
11539                 else
11540                         crtc->new_config = NULL;
11541         }
11542
11543         count = 0;
11544         for_each_intel_encoder(dev, encoder) {
11545                 encoder->new_crtc =
11546                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11547         }
11548
11549         count = 0;
11550         for_each_intel_connector(dev, connector) {
11551                 connector->new_encoder =
11552                         to_intel_encoder(config->save_connector_encoders[count++]);
11553         }
11554 }
11555
11556 static bool
11557 is_crtc_connector_off(struct drm_mode_set *set)
11558 {
11559         int i;
11560
11561         if (set->num_connectors == 0)
11562                 return false;
11563
11564         if (WARN_ON(set->connectors == NULL))
11565                 return false;
11566
11567         for (i = 0; i < set->num_connectors; i++)
11568                 if (set->connectors[i]->encoder &&
11569                     set->connectors[i]->encoder->crtc == set->crtc &&
11570                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11571                         return true;
11572
11573         return false;
11574 }
11575
11576 static void
11577 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11578                                       struct intel_set_config *config)
11579 {
11580
11581         /* We should be able to check here if the fb has the same properties
11582          * and then just flip_or_move it */
11583         if (is_crtc_connector_off(set)) {
11584                 config->mode_changed = true;
11585         } else if (set->crtc->primary->fb != set->fb) {
11586                 /*
11587                  * If we have no fb, we can only flip as long as the crtc is
11588                  * active, otherwise we need a full mode set.  The crtc may
11589                  * be active if we've only disabled the primary plane, or
11590                  * in fastboot situations.
11591                  */
11592                 if (set->crtc->primary->fb == NULL) {
11593                         struct intel_crtc *intel_crtc =
11594                                 to_intel_crtc(set->crtc);
11595
11596                         if (intel_crtc->active) {
11597                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11598                                 config->fb_changed = true;
11599                         } else {
11600                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11601                                 config->mode_changed = true;
11602                         }
11603                 } else if (set->fb == NULL) {
11604                         config->mode_changed = true;
11605                 } else if (set->fb->pixel_format !=
11606                            set->crtc->primary->fb->pixel_format) {
11607                         config->mode_changed = true;
11608                 } else {
11609                         config->fb_changed = true;
11610                 }
11611         }
11612
11613         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11614                 config->fb_changed = true;
11615
11616         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11617                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11618                 drm_mode_debug_printmodeline(&set->crtc->mode);
11619                 drm_mode_debug_printmodeline(set->mode);
11620                 config->mode_changed = true;
11621         }
11622
11623         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11624                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11625 }
11626
11627 static int
11628 intel_modeset_stage_output_state(struct drm_device *dev,
11629                                  struct drm_mode_set *set,
11630                                  struct intel_set_config *config)
11631 {
11632         struct intel_connector *connector;
11633         struct intel_encoder *encoder;
11634         struct intel_crtc *crtc;
11635         int ro;
11636
11637         /* The upper layers ensure that we either disable a crtc or have a list
11638          * of connectors. For paranoia, double-check this. */
11639         WARN_ON(!set->fb && (set->num_connectors != 0));
11640         WARN_ON(set->fb && (set->num_connectors == 0));
11641
11642         for_each_intel_connector(dev, connector) {
11643                 /* Otherwise traverse passed in connector list and get encoders
11644                  * for them. */
11645                 for (ro = 0; ro < set->num_connectors; ro++) {
11646                         if (set->connectors[ro] == &connector->base) {
11647                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11648                                 break;
11649                         }
11650                 }
11651
11652                 /* If we disable the crtc, disable all its connectors. Also, if
11653                  * the connector is on the changing crtc but not on the new
11654                  * connector list, disable it. */
11655                 if ((!set->fb || ro == set->num_connectors) &&
11656                     connector->base.encoder &&
11657                     connector->base.encoder->crtc == set->crtc) {
11658                         connector->new_encoder = NULL;
11659
11660                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11661                                 connector->base.base.id,
11662                                 connector->base.name);
11663                 }
11664
11665
11666                 if (&connector->new_encoder->base != connector->base.encoder) {
11667                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11668                                       connector->base.base.id,
11669                                       connector->base.name);
11670                         config->mode_changed = true;
11671                 }
11672         }
11673         /* connector->new_encoder is now updated for all connectors. */
11674
11675         /* Update crtc of enabled connectors. */
11676         for_each_intel_connector(dev, connector) {
11677                 struct drm_crtc *new_crtc;
11678
11679                 if (!connector->new_encoder)
11680                         continue;
11681
11682                 new_crtc = connector->new_encoder->base.crtc;
11683
11684                 for (ro = 0; ro < set->num_connectors; ro++) {
11685                         if (set->connectors[ro] == &connector->base)
11686                                 new_crtc = set->crtc;
11687                 }
11688
11689                 /* Make sure the new CRTC will work with the encoder */
11690                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11691                                          new_crtc)) {
11692                         return -EINVAL;
11693                 }
11694                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11695
11696                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11697                         connector->base.base.id,
11698                         connector->base.name,
11699                         new_crtc->base.id);
11700         }
11701
11702         /* Check for any encoders that needs to be disabled. */
11703         for_each_intel_encoder(dev, encoder) {
11704                 int num_connectors = 0;
11705                 for_each_intel_connector(dev, connector) {
11706                         if (connector->new_encoder == encoder) {
11707                                 WARN_ON(!connector->new_encoder->new_crtc);
11708                                 num_connectors++;
11709                         }
11710                 }
11711
11712                 if (num_connectors == 0)
11713                         encoder->new_crtc = NULL;
11714                 else if (num_connectors > 1)
11715                         return -EINVAL;
11716
11717                 /* Only now check for crtc changes so we don't miss encoders
11718                  * that will be disabled. */
11719                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11720                         DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11721                                       encoder->base.base.id,
11722                                       encoder->base.name);
11723                         config->mode_changed = true;
11724                 }
11725         }
11726         /* Now we've also updated encoder->new_crtc for all encoders. */
11727         for_each_intel_connector(dev, connector) {
11728                 if (connector->new_encoder)
11729                         if (connector->new_encoder != connector->encoder)
11730                                 connector->encoder = connector->new_encoder;
11731         }
11732         for_each_intel_crtc(dev, crtc) {
11733                 crtc->new_enabled = false;
11734
11735                 for_each_intel_encoder(dev, encoder) {
11736                         if (encoder->new_crtc == crtc) {
11737                                 crtc->new_enabled = true;
11738                                 break;
11739                         }
11740                 }
11741
11742                 if (crtc->new_enabled != crtc->base.state->enable) {
11743                         DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11744                                       crtc->base.base.id,
11745                                       crtc->new_enabled ? "en" : "dis");
11746                         config->mode_changed = true;
11747                 }
11748
11749                 if (crtc->new_enabled)
11750                         crtc->new_config = crtc->config;
11751                 else
11752                         crtc->new_config = NULL;
11753         }
11754
11755         return 0;
11756 }
11757
11758 static void disable_crtc_nofb(struct intel_crtc *crtc)
11759 {
11760         struct drm_device *dev = crtc->base.dev;
11761         struct intel_encoder *encoder;
11762         struct intel_connector *connector;
11763
11764         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11765                       pipe_name(crtc->pipe));
11766
11767         for_each_intel_connector(dev, connector) {
11768                 if (connector->new_encoder &&
11769                     connector->new_encoder->new_crtc == crtc)
11770                         connector->new_encoder = NULL;
11771         }
11772
11773         for_each_intel_encoder(dev, encoder) {
11774                 if (encoder->new_crtc == crtc)
11775                         encoder->new_crtc = NULL;
11776         }
11777
11778         crtc->new_enabled = false;
11779         crtc->new_config = NULL;
11780 }
11781
11782 static int intel_crtc_set_config(struct drm_mode_set *set)
11783 {
11784         struct drm_device *dev;
11785         struct drm_mode_set save_set;
11786         struct intel_set_config *config;
11787         struct intel_crtc_state *pipe_config;
11788         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11789         int ret;
11790
11791         BUG_ON(!set);
11792         BUG_ON(!set->crtc);
11793         BUG_ON(!set->crtc->helper_private);
11794
11795         /* Enforce sane interface api - has been abused by the fb helper. */
11796         BUG_ON(!set->mode && set->fb);
11797         BUG_ON(set->fb && set->num_connectors == 0);
11798
11799         if (set->fb) {
11800                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11801                                 set->crtc->base.id, set->fb->base.id,
11802                                 (int)set->num_connectors, set->x, set->y);
11803         } else {
11804                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11805         }
11806
11807         dev = set->crtc->dev;
11808
11809         ret = -ENOMEM;
11810         config = kzalloc(sizeof(*config), GFP_KERNEL);
11811         if (!config)
11812                 goto out_config;
11813
11814         ret = intel_set_config_save_state(dev, config);
11815         if (ret)
11816                 goto out_config;
11817
11818         save_set.crtc = set->crtc;
11819         save_set.mode = &set->crtc->mode;
11820         save_set.x = set->crtc->x;
11821         save_set.y = set->crtc->y;
11822         save_set.fb = set->crtc->primary->fb;
11823
11824         /* Compute whether we need a full modeset, only an fb base update or no
11825          * change at all. In the future we might also check whether only the
11826          * mode changed, e.g. for LVDS where we only change the panel fitter in
11827          * such cases. */
11828         intel_set_config_compute_mode_changes(set, config);
11829
11830         ret = intel_modeset_stage_output_state(dev, set, config);
11831         if (ret)
11832                 goto fail;
11833
11834         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11835                                                    set->fb,
11836                                                    &modeset_pipes,
11837                                                    &prepare_pipes,
11838                                                    &disable_pipes);
11839         if (IS_ERR(pipe_config)) {
11840                 ret = PTR_ERR(pipe_config);
11841                 goto fail;
11842         } else if (pipe_config) {
11843                 if (pipe_config->has_audio !=
11844                     to_intel_crtc(set->crtc)->config->has_audio)
11845                         config->mode_changed = true;
11846
11847                 /*
11848                  * Note we have an issue here with infoframes: current code
11849                  * only updates them on the full mode set path per hw
11850                  * requirements.  So here we should be checking for any
11851                  * required changes and forcing a mode set.
11852                  */
11853         }
11854
11855         /* set_mode will free it in the mode_changed case */
11856         if (!config->mode_changed)
11857                 kfree(pipe_config);
11858
11859         intel_update_pipe_size(to_intel_crtc(set->crtc));
11860
11861         if (config->mode_changed) {
11862                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11863                                            set->x, set->y, set->fb, pipe_config,
11864                                            modeset_pipes, prepare_pipes,
11865                                            disable_pipes);
11866         } else if (config->fb_changed) {
11867                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11868                 struct drm_plane *primary = set->crtc->primary;
11869                 int vdisplay, hdisplay;
11870
11871                 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11872                 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11873                                                    0, 0, hdisplay, vdisplay,
11874                                                    set->x << 16, set->y << 16,
11875                                                    hdisplay << 16, vdisplay << 16);
11876
11877                 /*
11878                  * We need to make sure the primary plane is re-enabled if it
11879                  * has previously been turned off.
11880                  */
11881                 if (!intel_crtc->primary_enabled && ret == 0) {
11882                         WARN_ON(!intel_crtc->active);
11883                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11884                 }
11885
11886                 /*
11887                  * In the fastboot case this may be our only check of the
11888                  * state after boot.  It would be better to only do it on
11889                  * the first update, but we don't have a nice way of doing that
11890                  * (and really, set_config isn't used much for high freq page
11891                  * flipping, so increasing its cost here shouldn't be a big
11892                  * deal).
11893                  */
11894                 if (i915.fastboot && ret == 0)
11895                         intel_modeset_check_state(set->crtc->dev);
11896         }
11897
11898         if (ret) {
11899                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11900                               set->crtc->base.id, ret);
11901 fail:
11902                 intel_set_config_restore_state(dev, config);
11903
11904                 /*
11905                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11906                  * force the pipe off to avoid oopsing in the modeset code
11907                  * due to fb==NULL. This should only happen during boot since
11908                  * we don't yet reconstruct the FB from the hardware state.
11909                  */
11910                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11911                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11912
11913                 /* Try to restore the config */
11914                 if (config->mode_changed &&
11915                     intel_set_mode(save_set.crtc, save_set.mode,
11916                                    save_set.x, save_set.y, save_set.fb))
11917                         DRM_ERROR("failed to restore config after modeset failure\n");
11918         }
11919
11920 out_config:
11921         intel_set_config_free(config);
11922         return ret;
11923 }
11924
11925 static const struct drm_crtc_funcs intel_crtc_funcs = {
11926         .gamma_set = intel_crtc_gamma_set,
11927         .set_config = intel_crtc_set_config,
11928         .destroy = intel_crtc_destroy,
11929         .page_flip = intel_crtc_page_flip,
11930         .atomic_duplicate_state = intel_crtc_duplicate_state,
11931         .atomic_destroy_state = intel_crtc_destroy_state,
11932 };
11933
11934 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11935                                       struct intel_shared_dpll *pll,
11936                                       struct intel_dpll_hw_state *hw_state)
11937 {
11938         uint32_t val;
11939
11940         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11941                 return false;
11942
11943         val = I915_READ(PCH_DPLL(pll->id));
11944         hw_state->dpll = val;
11945         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11946         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11947
11948         return val & DPLL_VCO_ENABLE;
11949 }
11950
11951 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11952                                   struct intel_shared_dpll *pll)
11953 {
11954         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11955         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11956 }
11957
11958 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11959                                 struct intel_shared_dpll *pll)
11960 {
11961         /* PCH refclock must be enabled first */
11962         ibx_assert_pch_refclk_enabled(dev_priv);
11963
11964         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11965
11966         /* Wait for the clocks to stabilize. */
11967         POSTING_READ(PCH_DPLL(pll->id));
11968         udelay(150);
11969
11970         /* The pixel multiplier can only be updated once the
11971          * DPLL is enabled and the clocks are stable.
11972          *
11973          * So write it again.
11974          */
11975         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11976         POSTING_READ(PCH_DPLL(pll->id));
11977         udelay(200);
11978 }
11979
11980 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11981                                  struct intel_shared_dpll *pll)
11982 {
11983         struct drm_device *dev = dev_priv->dev;
11984         struct intel_crtc *crtc;
11985
11986         /* Make sure no transcoder isn't still depending on us. */
11987         for_each_intel_crtc(dev, crtc) {
11988                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11989                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11990         }
11991
11992         I915_WRITE(PCH_DPLL(pll->id), 0);
11993         POSTING_READ(PCH_DPLL(pll->id));
11994         udelay(200);
11995 }
11996
11997 static char *ibx_pch_dpll_names[] = {
11998         "PCH DPLL A",
11999         "PCH DPLL B",
12000 };
12001
12002 static void ibx_pch_dpll_init(struct drm_device *dev)
12003 {
12004         struct drm_i915_private *dev_priv = dev->dev_private;
12005         int i;
12006
12007         dev_priv->num_shared_dpll = 2;
12008
12009         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12010                 dev_priv->shared_dplls[i].id = i;
12011                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12012                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12013                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12014                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12015                 dev_priv->shared_dplls[i].get_hw_state =
12016                         ibx_pch_dpll_get_hw_state;
12017         }
12018 }
12019
12020 static void intel_shared_dpll_init(struct drm_device *dev)
12021 {
12022         struct drm_i915_private *dev_priv = dev->dev_private;
12023
12024         if (HAS_DDI(dev))
12025                 intel_ddi_pll_init(dev);
12026         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12027                 ibx_pch_dpll_init(dev);
12028         else
12029                 dev_priv->num_shared_dpll = 0;
12030
12031         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12032 }
12033
12034 /**
12035  * intel_wm_need_update - Check whether watermarks need updating
12036  * @plane: drm plane
12037  * @state: new plane state
12038  *
12039  * Check current plane state versus the new one to determine whether
12040  * watermarks need to be recalculated.
12041  *
12042  * Returns true or false.
12043  */
12044 bool intel_wm_need_update(struct drm_plane *plane,
12045                           struct drm_plane_state *state)
12046 {
12047         /* Update watermarks on tiling changes. */
12048         if (!plane->state->fb || !state->fb ||
12049             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12050             plane->state->rotation != state->rotation)
12051                 return true;
12052
12053         return false;
12054 }
12055
12056 /**
12057  * intel_prepare_plane_fb - Prepare fb for usage on plane
12058  * @plane: drm plane to prepare for
12059  * @fb: framebuffer to prepare for presentation
12060  *
12061  * Prepares a framebuffer for usage on a display plane.  Generally this
12062  * involves pinning the underlying object and updating the frontbuffer tracking
12063  * bits.  Some older platforms need special physical address handling for
12064  * cursor planes.
12065  *
12066  * Returns 0 on success, negative error code on failure.
12067  */
12068 int
12069 intel_prepare_plane_fb(struct drm_plane *plane,
12070                        struct drm_framebuffer *fb,
12071                        const struct drm_plane_state *new_state)
12072 {
12073         struct drm_device *dev = plane->dev;
12074         struct intel_plane *intel_plane = to_intel_plane(plane);
12075         enum pipe pipe = intel_plane->pipe;
12076         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12077         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12078         unsigned frontbuffer_bits = 0;
12079         int ret = 0;
12080
12081         if (!obj)
12082                 return 0;
12083
12084         switch (plane->type) {
12085         case DRM_PLANE_TYPE_PRIMARY:
12086                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12087                 break;
12088         case DRM_PLANE_TYPE_CURSOR:
12089                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12090                 break;
12091         case DRM_PLANE_TYPE_OVERLAY:
12092                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12093                 break;
12094         }
12095
12096         mutex_lock(&dev->struct_mutex);
12097
12098         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12099             INTEL_INFO(dev)->cursor_needs_physical) {
12100                 int align = IS_I830(dev) ? 16 * 1024 : 256;
12101                 ret = i915_gem_object_attach_phys(obj, align);
12102                 if (ret)
12103                         DRM_DEBUG_KMS("failed to attach phys object\n");
12104         } else {
12105                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12106         }
12107
12108         if (ret == 0)
12109                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12110
12111         mutex_unlock(&dev->struct_mutex);
12112
12113         return ret;
12114 }
12115
12116 /**
12117  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12118  * @plane: drm plane to clean up for
12119  * @fb: old framebuffer that was on plane
12120  *
12121  * Cleans up a framebuffer that has just been removed from a plane.
12122  */
12123 void
12124 intel_cleanup_plane_fb(struct drm_plane *plane,
12125                        struct drm_framebuffer *fb,
12126                        const struct drm_plane_state *old_state)
12127 {
12128         struct drm_device *dev = plane->dev;
12129         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12130
12131         if (WARN_ON(!obj))
12132                 return;
12133
12134         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12135             !INTEL_INFO(dev)->cursor_needs_physical) {
12136                 mutex_lock(&dev->struct_mutex);
12137                 intel_unpin_fb_obj(fb, old_state);
12138                 mutex_unlock(&dev->struct_mutex);
12139         }
12140 }
12141
12142 static int
12143 intel_check_primary_plane(struct drm_plane *plane,
12144                           struct intel_plane_state *state)
12145 {
12146         struct drm_device *dev = plane->dev;
12147         struct drm_i915_private *dev_priv = dev->dev_private;
12148         struct drm_crtc *crtc = state->base.crtc;
12149         struct intel_crtc *intel_crtc;
12150         struct drm_framebuffer *fb = state->base.fb;
12151         struct drm_rect *dest = &state->dst;
12152         struct drm_rect *src = &state->src;
12153         const struct drm_rect *clip = &state->clip;
12154         int ret;
12155
12156         crtc = crtc ? crtc : plane->crtc;
12157         intel_crtc = to_intel_crtc(crtc);
12158
12159         ret = drm_plane_helper_check_update(plane, crtc, fb,
12160                                             src, dest, clip,
12161                                             DRM_PLANE_HELPER_NO_SCALING,
12162                                             DRM_PLANE_HELPER_NO_SCALING,
12163                                             false, true, &state->visible);
12164         if (ret)
12165                 return ret;
12166
12167         if (intel_crtc->active) {
12168                 intel_crtc->atomic.wait_for_flips = true;
12169
12170                 /*
12171                  * FBC does not work on some platforms for rotated
12172                  * planes, so disable it when rotation is not 0 and
12173                  * update it when rotation is set back to 0.
12174                  *
12175                  * FIXME: This is redundant with the fbc update done in
12176                  * the primary plane enable function except that that
12177                  * one is done too late. We eventually need to unify
12178                  * this.
12179                  */
12180                 if (intel_crtc->primary_enabled &&
12181                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12182                     dev_priv->fbc.crtc == intel_crtc &&
12183                     state->base.rotation != BIT(DRM_ROTATE_0)) {
12184                         intel_crtc->atomic.disable_fbc = true;
12185                 }
12186
12187                 if (state->visible) {
12188                         /*
12189                          * BDW signals flip done immediately if the plane
12190                          * is disabled, even if the plane enable is already
12191                          * armed to occur at the next vblank :(
12192                          */
12193                         if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12194                                 intel_crtc->atomic.wait_vblank = true;
12195                 }
12196
12197                 intel_crtc->atomic.fb_bits |=
12198                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12199
12200                 intel_crtc->atomic.update_fbc = true;
12201
12202                 if (intel_wm_need_update(plane, &state->base))
12203                         intel_crtc->atomic.update_wm = true;
12204         }
12205
12206         return 0;
12207 }
12208
12209 static void
12210 intel_commit_primary_plane(struct drm_plane *plane,
12211                            struct intel_plane_state *state)
12212 {
12213         struct drm_crtc *crtc = state->base.crtc;
12214         struct drm_framebuffer *fb = state->base.fb;
12215         struct drm_device *dev = plane->dev;
12216         struct drm_i915_private *dev_priv = dev->dev_private;
12217         struct intel_crtc *intel_crtc;
12218         struct drm_rect *src = &state->src;
12219
12220         crtc = crtc ? crtc : plane->crtc;
12221         intel_crtc = to_intel_crtc(crtc);
12222
12223         plane->fb = fb;
12224         crtc->x = src->x1 >> 16;
12225         crtc->y = src->y1 >> 16;
12226
12227         if (intel_crtc->active) {
12228                 if (state->visible) {
12229                         /* FIXME: kill this fastboot hack */
12230                         intel_update_pipe_size(intel_crtc);
12231
12232                         intel_crtc->primary_enabled = true;
12233
12234                         dev_priv->display.update_primary_plane(crtc, plane->fb,
12235                                         crtc->x, crtc->y);
12236                 } else {
12237                         /*
12238                          * If clipping results in a non-visible primary plane,
12239                          * we'll disable the primary plane.  Note that this is
12240                          * a bit different than what happens if userspace
12241                          * explicitly disables the plane by passing fb=0
12242                          * because plane->fb still gets set and pinned.
12243                          */
12244                         intel_disable_primary_hw_plane(plane, crtc);
12245                 }
12246         }
12247 }
12248
12249 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12250 {
12251         struct drm_device *dev = crtc->dev;
12252         struct drm_i915_private *dev_priv = dev->dev_private;
12253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12254         struct intel_plane *intel_plane;
12255         struct drm_plane *p;
12256         unsigned fb_bits = 0;
12257
12258         /* Track fb's for any planes being disabled */
12259         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12260                 intel_plane = to_intel_plane(p);
12261
12262                 if (intel_crtc->atomic.disabled_planes &
12263                     (1 << drm_plane_index(p))) {
12264                         switch (p->type) {
12265                         case DRM_PLANE_TYPE_PRIMARY:
12266                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12267                                 break;
12268                         case DRM_PLANE_TYPE_CURSOR:
12269                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12270                                 break;
12271                         case DRM_PLANE_TYPE_OVERLAY:
12272                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12273                                 break;
12274                         }
12275
12276                         mutex_lock(&dev->struct_mutex);
12277                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12278                         mutex_unlock(&dev->struct_mutex);
12279                 }
12280         }
12281
12282         if (intel_crtc->atomic.wait_for_flips)
12283                 intel_crtc_wait_for_pending_flips(crtc);
12284
12285         if (intel_crtc->atomic.disable_fbc)
12286                 intel_fbc_disable(dev);
12287
12288         if (intel_crtc->atomic.pre_disable_primary)
12289                 intel_pre_disable_primary(crtc);
12290
12291         if (intel_crtc->atomic.update_wm)
12292                 intel_update_watermarks(crtc);
12293
12294         intel_runtime_pm_get(dev_priv);
12295
12296         /* Perform vblank evasion around commit operation */
12297         if (intel_crtc->active)
12298                 intel_crtc->atomic.evade =
12299                         intel_pipe_update_start(intel_crtc,
12300                                                 &intel_crtc->atomic.start_vbl_count);
12301 }
12302
12303 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12304 {
12305         struct drm_device *dev = crtc->dev;
12306         struct drm_i915_private *dev_priv = dev->dev_private;
12307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12308         struct drm_plane *p;
12309
12310         if (intel_crtc->atomic.evade)
12311                 intel_pipe_update_end(intel_crtc,
12312                                       intel_crtc->atomic.start_vbl_count);
12313
12314         intel_runtime_pm_put(dev_priv);
12315
12316         if (intel_crtc->atomic.wait_vblank)
12317                 intel_wait_for_vblank(dev, intel_crtc->pipe);
12318
12319         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12320
12321         if (intel_crtc->atomic.update_fbc) {
12322                 mutex_lock(&dev->struct_mutex);
12323                 intel_fbc_update(dev);
12324                 mutex_unlock(&dev->struct_mutex);
12325         }
12326
12327         if (intel_crtc->atomic.post_enable_primary)
12328                 intel_post_enable_primary(crtc);
12329
12330         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12331                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12332                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12333                                                        false, false);
12334
12335         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12336 }
12337
12338 /**
12339  * intel_plane_destroy - destroy a plane
12340  * @plane: plane to destroy
12341  *
12342  * Common destruction function for all types of planes (primary, cursor,
12343  * sprite).
12344  */
12345 void intel_plane_destroy(struct drm_plane *plane)
12346 {
12347         struct intel_plane *intel_plane = to_intel_plane(plane);
12348         drm_plane_cleanup(plane);
12349         kfree(intel_plane);
12350 }
12351
12352 const struct drm_plane_funcs intel_plane_funcs = {
12353         .update_plane = drm_plane_helper_update,
12354         .disable_plane = drm_plane_helper_disable,
12355         .destroy = intel_plane_destroy,
12356         .set_property = drm_atomic_helper_plane_set_property,
12357         .atomic_get_property = intel_plane_atomic_get_property,
12358         .atomic_set_property = intel_plane_atomic_set_property,
12359         .atomic_duplicate_state = intel_plane_duplicate_state,
12360         .atomic_destroy_state = intel_plane_destroy_state,
12361
12362 };
12363
12364 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12365                                                     int pipe)
12366 {
12367         struct intel_plane *primary;
12368         struct intel_plane_state *state;
12369         const uint32_t *intel_primary_formats;
12370         int num_formats;
12371
12372         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12373         if (primary == NULL)
12374                 return NULL;
12375
12376         state = intel_create_plane_state(&primary->base);
12377         if (!state) {
12378                 kfree(primary);
12379                 return NULL;
12380         }
12381         primary->base.state = &state->base;
12382
12383         primary->can_scale = false;
12384         primary->max_downscale = 1;
12385         primary->pipe = pipe;
12386         primary->plane = pipe;
12387         primary->check_plane = intel_check_primary_plane;
12388         primary->commit_plane = intel_commit_primary_plane;
12389         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12390                 primary->plane = !pipe;
12391
12392         if (INTEL_INFO(dev)->gen <= 3) {
12393                 intel_primary_formats = intel_primary_formats_gen2;
12394                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12395         } else {
12396                 intel_primary_formats = intel_primary_formats_gen4;
12397                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12398         }
12399
12400         drm_universal_plane_init(dev, &primary->base, 0,
12401                                  &intel_plane_funcs,
12402                                  intel_primary_formats, num_formats,
12403                                  DRM_PLANE_TYPE_PRIMARY);
12404
12405         if (INTEL_INFO(dev)->gen >= 4) {
12406                 if (!dev->mode_config.rotation_property)
12407                         dev->mode_config.rotation_property =
12408                                 drm_mode_create_rotation_property(dev,
12409                                                         BIT(DRM_ROTATE_0) |
12410                                                         BIT(DRM_ROTATE_180));
12411                 if (dev->mode_config.rotation_property)
12412                         drm_object_attach_property(&primary->base.base,
12413                                 dev->mode_config.rotation_property,
12414                                 state->base.rotation);
12415         }
12416
12417         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12418
12419         return &primary->base;
12420 }
12421
12422 static int
12423 intel_check_cursor_plane(struct drm_plane *plane,
12424                          struct intel_plane_state *state)
12425 {
12426         struct drm_crtc *crtc = state->base.crtc;
12427         struct drm_device *dev = plane->dev;
12428         struct drm_framebuffer *fb = state->base.fb;
12429         struct drm_rect *dest = &state->dst;
12430         struct drm_rect *src = &state->src;
12431         const struct drm_rect *clip = &state->clip;
12432         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12433         struct intel_crtc *intel_crtc;
12434         unsigned stride;
12435         int ret;
12436
12437         crtc = crtc ? crtc : plane->crtc;
12438         intel_crtc = to_intel_crtc(crtc);
12439
12440         ret = drm_plane_helper_check_update(plane, crtc, fb,
12441                                             src, dest, clip,
12442                                             DRM_PLANE_HELPER_NO_SCALING,
12443                                             DRM_PLANE_HELPER_NO_SCALING,
12444                                             true, true, &state->visible);
12445         if (ret)
12446                 return ret;
12447
12448
12449         /* if we want to turn off the cursor ignore width and height */
12450         if (!obj)
12451                 goto finish;
12452
12453         /* Check for which cursor types we support */
12454         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12455                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12456                           state->base.crtc_w, state->base.crtc_h);
12457                 return -EINVAL;
12458         }
12459
12460         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12461         if (obj->base.size < stride * state->base.crtc_h) {
12462                 DRM_DEBUG_KMS("buffer is too small\n");
12463                 return -ENOMEM;
12464         }
12465
12466         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12467                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12468                 ret = -EINVAL;
12469         }
12470
12471 finish:
12472         if (intel_crtc->active) {
12473                 if (plane->state->crtc_w != state->base.crtc_w)
12474                         intel_crtc->atomic.update_wm = true;
12475
12476                 intel_crtc->atomic.fb_bits |=
12477                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12478         }
12479
12480         return ret;
12481 }
12482
12483 static void
12484 intel_commit_cursor_plane(struct drm_plane *plane,
12485                           struct intel_plane_state *state)
12486 {
12487         struct drm_crtc *crtc = state->base.crtc;
12488         struct drm_device *dev = plane->dev;
12489         struct intel_crtc *intel_crtc;
12490         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12491         uint32_t addr;
12492
12493         crtc = crtc ? crtc : plane->crtc;
12494         intel_crtc = to_intel_crtc(crtc);
12495
12496         plane->fb = state->base.fb;
12497         crtc->cursor_x = state->base.crtc_x;
12498         crtc->cursor_y = state->base.crtc_y;
12499
12500         if (intel_crtc->cursor_bo == obj)
12501                 goto update;
12502
12503         if (!obj)
12504                 addr = 0;
12505         else if (!INTEL_INFO(dev)->cursor_needs_physical)
12506                 addr = i915_gem_obj_ggtt_offset(obj);
12507         else
12508                 addr = obj->phys_handle->busaddr;
12509
12510         intel_crtc->cursor_addr = addr;
12511         intel_crtc->cursor_bo = obj;
12512 update:
12513
12514         if (intel_crtc->active)
12515                 intel_crtc_update_cursor(crtc, state->visible);
12516 }
12517
12518 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12519                                                    int pipe)
12520 {
12521         struct intel_plane *cursor;
12522         struct intel_plane_state *state;
12523
12524         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12525         if (cursor == NULL)
12526                 return NULL;
12527
12528         state = intel_create_plane_state(&cursor->base);
12529         if (!state) {
12530                 kfree(cursor);
12531                 return NULL;
12532         }
12533         cursor->base.state = &state->base;
12534
12535         cursor->can_scale = false;
12536         cursor->max_downscale = 1;
12537         cursor->pipe = pipe;
12538         cursor->plane = pipe;
12539         cursor->check_plane = intel_check_cursor_plane;
12540         cursor->commit_plane = intel_commit_cursor_plane;
12541
12542         drm_universal_plane_init(dev, &cursor->base, 0,
12543                                  &intel_plane_funcs,
12544                                  intel_cursor_formats,
12545                                  ARRAY_SIZE(intel_cursor_formats),
12546                                  DRM_PLANE_TYPE_CURSOR);
12547
12548         if (INTEL_INFO(dev)->gen >= 4) {
12549                 if (!dev->mode_config.rotation_property)
12550                         dev->mode_config.rotation_property =
12551                                 drm_mode_create_rotation_property(dev,
12552                                                         BIT(DRM_ROTATE_0) |
12553                                                         BIT(DRM_ROTATE_180));
12554                 if (dev->mode_config.rotation_property)
12555                         drm_object_attach_property(&cursor->base.base,
12556                                 dev->mode_config.rotation_property,
12557                                 state->base.rotation);
12558         }
12559
12560         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12561
12562         return &cursor->base;
12563 }
12564
12565 static void intel_crtc_init(struct drm_device *dev, int pipe)
12566 {
12567         struct drm_i915_private *dev_priv = dev->dev_private;
12568         struct intel_crtc *intel_crtc;
12569         struct intel_crtc_state *crtc_state = NULL;
12570         struct drm_plane *primary = NULL;
12571         struct drm_plane *cursor = NULL;
12572         int i, ret;
12573
12574         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12575         if (intel_crtc == NULL)
12576                 return;
12577
12578         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12579         if (!crtc_state)
12580                 goto fail;
12581         intel_crtc_set_state(intel_crtc, crtc_state);
12582         crtc_state->base.crtc = &intel_crtc->base;
12583
12584         primary = intel_primary_plane_create(dev, pipe);
12585         if (!primary)
12586                 goto fail;
12587
12588         cursor = intel_cursor_plane_create(dev, pipe);
12589         if (!cursor)
12590                 goto fail;
12591
12592         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12593                                         cursor, &intel_crtc_funcs);
12594         if (ret)
12595                 goto fail;
12596
12597         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12598         for (i = 0; i < 256; i++) {
12599                 intel_crtc->lut_r[i] = i;
12600                 intel_crtc->lut_g[i] = i;
12601                 intel_crtc->lut_b[i] = i;
12602         }
12603
12604         /*
12605          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12606          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12607          */
12608         intel_crtc->pipe = pipe;
12609         intel_crtc->plane = pipe;
12610         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12611                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12612                 intel_crtc->plane = !pipe;
12613         }
12614
12615         intel_crtc->cursor_base = ~0;
12616         intel_crtc->cursor_cntl = ~0;
12617         intel_crtc->cursor_size = ~0;
12618
12619         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12620                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12621         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12622         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12623
12624         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12625
12626         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12627
12628         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12629         return;
12630
12631 fail:
12632         if (primary)
12633                 drm_plane_cleanup(primary);
12634         if (cursor)
12635                 drm_plane_cleanup(cursor);
12636         kfree(crtc_state);
12637         kfree(intel_crtc);
12638 }
12639
12640 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12641 {
12642         struct drm_encoder *encoder = connector->base.encoder;
12643         struct drm_device *dev = connector->base.dev;
12644
12645         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12646
12647         if (!encoder || WARN_ON(!encoder->crtc))
12648                 return INVALID_PIPE;
12649
12650         return to_intel_crtc(encoder->crtc)->pipe;
12651 }
12652
12653 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12654                                 struct drm_file *file)
12655 {
12656         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12657         struct drm_crtc *drmmode_crtc;
12658         struct intel_crtc *crtc;
12659
12660         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12661
12662         if (!drmmode_crtc) {
12663                 DRM_ERROR("no such CRTC id\n");
12664                 return -ENOENT;
12665         }
12666
12667         crtc = to_intel_crtc(drmmode_crtc);
12668         pipe_from_crtc_id->pipe = crtc->pipe;
12669
12670         return 0;
12671 }
12672
12673 static int intel_encoder_clones(struct intel_encoder *encoder)
12674 {
12675         struct drm_device *dev = encoder->base.dev;
12676         struct intel_encoder *source_encoder;
12677         int index_mask = 0;
12678         int entry = 0;
12679
12680         for_each_intel_encoder(dev, source_encoder) {
12681                 if (encoders_cloneable(encoder, source_encoder))
12682                         index_mask |= (1 << entry);
12683
12684                 entry++;
12685         }
12686
12687         return index_mask;
12688 }
12689
12690 static bool has_edp_a(struct drm_device *dev)
12691 {
12692         struct drm_i915_private *dev_priv = dev->dev_private;
12693
12694         if (!IS_MOBILE(dev))
12695                 return false;
12696
12697         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12698                 return false;
12699
12700         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12701                 return false;
12702
12703         return true;
12704 }
12705
12706 static bool intel_crt_present(struct drm_device *dev)
12707 {
12708         struct drm_i915_private *dev_priv = dev->dev_private;
12709
12710         if (INTEL_INFO(dev)->gen >= 9)
12711                 return false;
12712
12713         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12714                 return false;
12715
12716         if (IS_CHERRYVIEW(dev))
12717                 return false;
12718
12719         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12720                 return false;
12721
12722         return true;
12723 }
12724
12725 static void intel_setup_outputs(struct drm_device *dev)
12726 {
12727         struct drm_i915_private *dev_priv = dev->dev_private;
12728         struct intel_encoder *encoder;
12729         struct drm_connector *connector;
12730         bool dpd_is_edp = false;
12731
12732         intel_lvds_init(dev);
12733
12734         if (intel_crt_present(dev))
12735                 intel_crt_init(dev);
12736
12737         if (HAS_DDI(dev)) {
12738                 int found;
12739
12740                 /*
12741                  * Haswell uses DDI functions to detect digital outputs.
12742                  * On SKL pre-D0 the strap isn't connected, so we assume
12743                  * it's there.
12744                  */
12745                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12746                 /* WaIgnoreDDIAStrap: skl */
12747                 if (found ||
12748                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12749                         intel_ddi_init(dev, PORT_A);
12750
12751                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12752                  * register */
12753                 found = I915_READ(SFUSE_STRAP);
12754
12755                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12756                         intel_ddi_init(dev, PORT_B);
12757                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12758                         intel_ddi_init(dev, PORT_C);
12759                 if (found & SFUSE_STRAP_DDID_DETECTED)
12760                         intel_ddi_init(dev, PORT_D);
12761         } else if (HAS_PCH_SPLIT(dev)) {
12762                 int found;
12763                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12764
12765                 if (has_edp_a(dev))
12766                         intel_dp_init(dev, DP_A, PORT_A);
12767
12768                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12769                         /* PCH SDVOB multiplex with HDMIB */
12770                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12771                         if (!found)
12772                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12773                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12774                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12775                 }
12776
12777                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12778                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12779
12780                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12781                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12782
12783                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12784                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12785
12786                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12787                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12788         } else if (IS_VALLEYVIEW(dev)) {
12789                 /*
12790                  * The DP_DETECTED bit is the latched state of the DDC
12791                  * SDA pin at boot. However since eDP doesn't require DDC
12792                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12793                  * eDP ports may have been muxed to an alternate function.
12794                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12795                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12796                  * detect eDP ports.
12797                  */
12798                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12799                     !intel_dp_is_edp(dev, PORT_B))
12800                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12801                                         PORT_B);
12802                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12803                     intel_dp_is_edp(dev, PORT_B))
12804                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12805
12806                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12807                     !intel_dp_is_edp(dev, PORT_C))
12808                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12809                                         PORT_C);
12810                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12811                     intel_dp_is_edp(dev, PORT_C))
12812                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12813
12814                 if (IS_CHERRYVIEW(dev)) {
12815                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12816                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12817                                                 PORT_D);
12818                         /* eDP not supported on port D, so don't check VBT */
12819                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12820                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12821                 }
12822
12823                 intel_dsi_init(dev);
12824         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12825                 bool found = false;
12826
12827                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12828                         DRM_DEBUG_KMS("probing SDVOB\n");
12829                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12830                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12831                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12832                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12833                         }
12834
12835                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12836                                 intel_dp_init(dev, DP_B, PORT_B);
12837                 }
12838
12839                 /* Before G4X SDVOC doesn't have its own detect register */
12840
12841                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12842                         DRM_DEBUG_KMS("probing SDVOC\n");
12843                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12844                 }
12845
12846                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12847
12848                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12849                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12850                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12851                         }
12852                         if (SUPPORTS_INTEGRATED_DP(dev))
12853                                 intel_dp_init(dev, DP_C, PORT_C);
12854                 }
12855
12856                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12857                     (I915_READ(DP_D) & DP_DETECTED))
12858                         intel_dp_init(dev, DP_D, PORT_D);
12859         } else if (IS_GEN2(dev))
12860                 intel_dvo_init(dev);
12861
12862         if (SUPPORTS_TV(dev))
12863                 intel_tv_init(dev);
12864
12865         /*
12866          * FIXME:  We don't have full atomic support yet, but we want to be
12867          * able to enable/test plane updates via the atomic interface in the
12868          * meantime.  However as soon as we flip DRIVER_ATOMIC on, the DRM core
12869          * will take some atomic codepaths to lookup properties during
12870          * drmModeGetConnector() that unconditionally dereference
12871          * connector->state.
12872          *
12873          * We create a dummy connector state here for each connector to ensure
12874          * the DRM core doesn't try to dereference a NULL connector->state.
12875          * The actual connector properties will never be updated or contain
12876          * useful information, but since we're doing this specifically for
12877          * testing/debug of the plane operations (and only when a specific
12878          * kernel module option is given), that shouldn't really matter.
12879          *
12880          * Once atomic support for crtc's + connectors lands, this loop should
12881          * be removed since we'll be setting up real connector state, which
12882          * will contain Intel-specific properties.
12883          */
12884         if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12885                 list_for_each_entry(connector,
12886                                     &dev->mode_config.connector_list,
12887                                     head) {
12888                         if (!WARN_ON(connector->state)) {
12889                                 connector->state =
12890                                         kzalloc(sizeof(*connector->state),
12891                                                 GFP_KERNEL);
12892                         }
12893                 }
12894         }
12895
12896         intel_psr_init(dev);
12897
12898         for_each_intel_encoder(dev, encoder) {
12899                 encoder->base.possible_crtcs = encoder->crtc_mask;
12900                 encoder->base.possible_clones =
12901                         intel_encoder_clones(encoder);
12902         }
12903
12904         intel_init_pch_refclk(dev);
12905
12906         drm_helper_move_panel_connectors_to_head(dev);
12907 }
12908
12909 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12910 {
12911         struct drm_device *dev = fb->dev;
12912         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12913
12914         drm_framebuffer_cleanup(fb);
12915         mutex_lock(&dev->struct_mutex);
12916         WARN_ON(!intel_fb->obj->framebuffer_references--);
12917         drm_gem_object_unreference(&intel_fb->obj->base);
12918         mutex_unlock(&dev->struct_mutex);
12919         kfree(intel_fb);
12920 }
12921
12922 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12923                                                 struct drm_file *file,
12924                                                 unsigned int *handle)
12925 {
12926         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12927         struct drm_i915_gem_object *obj = intel_fb->obj;
12928
12929         return drm_gem_handle_create(file, &obj->base, handle);
12930 }
12931
12932 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12933         .destroy = intel_user_framebuffer_destroy,
12934         .create_handle = intel_user_framebuffer_create_handle,
12935 };
12936
12937 static
12938 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12939                          uint32_t pixel_format)
12940 {
12941         u32 gen = INTEL_INFO(dev)->gen;
12942
12943         if (gen >= 9) {
12944                 /* "The stride in bytes must not exceed the of the size of 8K
12945                  *  pixels and 32K bytes."
12946                  */
12947                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12948         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12949                 return 32*1024;
12950         } else if (gen >= 4) {
12951                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12952                         return 16*1024;
12953                 else
12954                         return 32*1024;
12955         } else if (gen >= 3) {
12956                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12957                         return 8*1024;
12958                 else
12959                         return 16*1024;
12960         } else {
12961                 /* XXX DSPC is limited to 4k tiled */
12962                 return 8*1024;
12963         }
12964 }
12965
12966 static int intel_framebuffer_init(struct drm_device *dev,
12967                                   struct intel_framebuffer *intel_fb,
12968                                   struct drm_mode_fb_cmd2 *mode_cmd,
12969                                   struct drm_i915_gem_object *obj)
12970 {
12971         unsigned int aligned_height;
12972         int ret;
12973         u32 pitch_limit, stride_alignment;
12974
12975         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12976
12977         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12978                 /* Enforce that fb modifier and tiling mode match, but only for
12979                  * X-tiled. This is needed for FBC. */
12980                 if (!!(obj->tiling_mode == I915_TILING_X) !=
12981                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12982                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12983                         return -EINVAL;
12984                 }
12985         } else {
12986                 if (obj->tiling_mode == I915_TILING_X)
12987                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12988                 else if (obj->tiling_mode == I915_TILING_Y) {
12989                         DRM_DEBUG("No Y tiling for legacy addfb\n");
12990                         return -EINVAL;
12991                 }
12992         }
12993
12994         /* Passed in modifier sanity checking. */
12995         switch (mode_cmd->modifier[0]) {
12996         case I915_FORMAT_MOD_Y_TILED:
12997         case I915_FORMAT_MOD_Yf_TILED:
12998                 if (INTEL_INFO(dev)->gen < 9) {
12999                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13000                                   mode_cmd->modifier[0]);
13001                         return -EINVAL;
13002                 }
13003         case DRM_FORMAT_MOD_NONE:
13004         case I915_FORMAT_MOD_X_TILED:
13005                 break;
13006         default:
13007                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13008                           mode_cmd->modifier[0]);
13009                 return -EINVAL;
13010         }
13011
13012         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13013                                                      mode_cmd->pixel_format);
13014         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13015                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13016                           mode_cmd->pitches[0], stride_alignment);
13017                 return -EINVAL;
13018         }
13019
13020         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13021                                            mode_cmd->pixel_format);
13022         if (mode_cmd->pitches[0] > pitch_limit) {
13023                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13024                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13025                           "tiled" : "linear",
13026                           mode_cmd->pitches[0], pitch_limit);
13027                 return -EINVAL;
13028         }
13029
13030         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13031             mode_cmd->pitches[0] != obj->stride) {
13032                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13033                           mode_cmd->pitches[0], obj->stride);
13034                 return -EINVAL;
13035         }
13036
13037         /* Reject formats not supported by any plane early. */
13038         switch (mode_cmd->pixel_format) {
13039         case DRM_FORMAT_C8:
13040         case DRM_FORMAT_RGB565:
13041         case DRM_FORMAT_XRGB8888:
13042         case DRM_FORMAT_ARGB8888:
13043                 break;
13044         case DRM_FORMAT_XRGB1555:
13045         case DRM_FORMAT_ARGB1555:
13046                 if (INTEL_INFO(dev)->gen > 3) {
13047                         DRM_DEBUG("unsupported pixel format: %s\n",
13048                                   drm_get_format_name(mode_cmd->pixel_format));
13049                         return -EINVAL;
13050                 }
13051                 break;
13052         case DRM_FORMAT_XBGR8888:
13053         case DRM_FORMAT_ABGR8888:
13054         case DRM_FORMAT_XRGB2101010:
13055         case DRM_FORMAT_ARGB2101010:
13056         case DRM_FORMAT_XBGR2101010:
13057         case DRM_FORMAT_ABGR2101010:
13058                 if (INTEL_INFO(dev)->gen < 4) {
13059                         DRM_DEBUG("unsupported pixel format: %s\n",
13060                                   drm_get_format_name(mode_cmd->pixel_format));
13061                         return -EINVAL;
13062                 }
13063                 break;
13064         case DRM_FORMAT_YUYV:
13065         case DRM_FORMAT_UYVY:
13066         case DRM_FORMAT_YVYU:
13067         case DRM_FORMAT_VYUY:
13068                 if (INTEL_INFO(dev)->gen < 5) {
13069                         DRM_DEBUG("unsupported pixel format: %s\n",
13070                                   drm_get_format_name(mode_cmd->pixel_format));
13071                         return -EINVAL;
13072                 }
13073                 break;
13074         default:
13075                 DRM_DEBUG("unsupported pixel format: %s\n",
13076                           drm_get_format_name(mode_cmd->pixel_format));
13077                 return -EINVAL;
13078         }
13079
13080         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13081         if (mode_cmd->offsets[0] != 0)
13082                 return -EINVAL;
13083
13084         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13085                                                mode_cmd->pixel_format,
13086                                                mode_cmd->modifier[0]);
13087         /* FIXME drm helper for size checks (especially planar formats)? */
13088         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13089                 return -EINVAL;
13090
13091         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13092         intel_fb->obj = obj;
13093         intel_fb->obj->framebuffer_references++;
13094
13095         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13096         if (ret) {
13097                 DRM_ERROR("framebuffer init failed %d\n", ret);
13098                 return ret;
13099         }
13100
13101         return 0;
13102 }
13103
13104 static struct drm_framebuffer *
13105 intel_user_framebuffer_create(struct drm_device *dev,
13106                               struct drm_file *filp,
13107                               struct drm_mode_fb_cmd2 *mode_cmd)
13108 {
13109         struct drm_i915_gem_object *obj;
13110
13111         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13112                                                 mode_cmd->handles[0]));
13113         if (&obj->base == NULL)
13114                 return ERR_PTR(-ENOENT);
13115
13116         return intel_framebuffer_create(dev, mode_cmd, obj);
13117 }
13118
13119 #ifndef CONFIG_DRM_I915_FBDEV
13120 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13121 {
13122 }
13123 #endif
13124
13125 static const struct drm_mode_config_funcs intel_mode_funcs = {
13126         .fb_create = intel_user_framebuffer_create,
13127         .output_poll_changed = intel_fbdev_output_poll_changed,
13128         .atomic_check = intel_atomic_check,
13129         .atomic_commit = intel_atomic_commit,
13130 };
13131
13132 /* Set up chip specific display functions */
13133 static void intel_init_display(struct drm_device *dev)
13134 {
13135         struct drm_i915_private *dev_priv = dev->dev_private;
13136
13137         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13138                 dev_priv->display.find_dpll = g4x_find_best_dpll;
13139         else if (IS_CHERRYVIEW(dev))
13140                 dev_priv->display.find_dpll = chv_find_best_dpll;
13141         else if (IS_VALLEYVIEW(dev))
13142                 dev_priv->display.find_dpll = vlv_find_best_dpll;
13143         else if (IS_PINEVIEW(dev))
13144                 dev_priv->display.find_dpll = pnv_find_best_dpll;
13145         else
13146                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13147
13148         if (INTEL_INFO(dev)->gen >= 9) {
13149                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13150                 dev_priv->display.get_initial_plane_config =
13151                         skylake_get_initial_plane_config;
13152                 dev_priv->display.crtc_compute_clock =
13153                         haswell_crtc_compute_clock;
13154                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13155                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13156                 dev_priv->display.off = ironlake_crtc_off;
13157                 dev_priv->display.update_primary_plane =
13158                         skylake_update_primary_plane;
13159         } else if (HAS_DDI(dev)) {
13160                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13161                 dev_priv->display.get_initial_plane_config =
13162                         ironlake_get_initial_plane_config;
13163                 dev_priv->display.crtc_compute_clock =
13164                         haswell_crtc_compute_clock;
13165                 dev_priv->display.crtc_enable = haswell_crtc_enable;
13166                 dev_priv->display.crtc_disable = haswell_crtc_disable;
13167                 dev_priv->display.off = ironlake_crtc_off;
13168                 dev_priv->display.update_primary_plane =
13169                         ironlake_update_primary_plane;
13170         } else if (HAS_PCH_SPLIT(dev)) {
13171                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13172                 dev_priv->display.get_initial_plane_config =
13173                         ironlake_get_initial_plane_config;
13174                 dev_priv->display.crtc_compute_clock =
13175                         ironlake_crtc_compute_clock;
13176                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13177                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13178                 dev_priv->display.off = ironlake_crtc_off;
13179                 dev_priv->display.update_primary_plane =
13180                         ironlake_update_primary_plane;
13181         } else if (IS_VALLEYVIEW(dev)) {
13182                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13183                 dev_priv->display.get_initial_plane_config =
13184                         i9xx_get_initial_plane_config;
13185                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13186                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13187                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13188                 dev_priv->display.off = i9xx_crtc_off;
13189                 dev_priv->display.update_primary_plane =
13190                         i9xx_update_primary_plane;
13191         } else {
13192                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13193                 dev_priv->display.get_initial_plane_config =
13194                         i9xx_get_initial_plane_config;
13195                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13196                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13197                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13198                 dev_priv->display.off = i9xx_crtc_off;
13199                 dev_priv->display.update_primary_plane =
13200                         i9xx_update_primary_plane;
13201         }
13202
13203         /* Returns the core display clock speed */
13204         if (IS_VALLEYVIEW(dev))
13205                 dev_priv->display.get_display_clock_speed =
13206                         valleyview_get_display_clock_speed;
13207         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13208                 dev_priv->display.get_display_clock_speed =
13209                         i945_get_display_clock_speed;
13210         else if (IS_I915G(dev))
13211                 dev_priv->display.get_display_clock_speed =
13212                         i915_get_display_clock_speed;
13213         else if (IS_I945GM(dev) || IS_845G(dev))
13214                 dev_priv->display.get_display_clock_speed =
13215                         i9xx_misc_get_display_clock_speed;
13216         else if (IS_PINEVIEW(dev))
13217                 dev_priv->display.get_display_clock_speed =
13218                         pnv_get_display_clock_speed;
13219         else if (IS_I915GM(dev))
13220                 dev_priv->display.get_display_clock_speed =
13221                         i915gm_get_display_clock_speed;
13222         else if (IS_I865G(dev))
13223                 dev_priv->display.get_display_clock_speed =
13224                         i865_get_display_clock_speed;
13225         else if (IS_I85X(dev))
13226                 dev_priv->display.get_display_clock_speed =
13227                         i855_get_display_clock_speed;
13228         else /* 852, 830 */
13229                 dev_priv->display.get_display_clock_speed =
13230                         i830_get_display_clock_speed;
13231
13232         if (IS_GEN5(dev)) {
13233                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13234         } else if (IS_GEN6(dev)) {
13235                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13236         } else if (IS_IVYBRIDGE(dev)) {
13237                 /* FIXME: detect B0+ stepping and use auto training */
13238                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13239         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13240                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13241         } else if (IS_VALLEYVIEW(dev)) {
13242                 dev_priv->display.modeset_global_resources =
13243                         valleyview_modeset_global_resources;
13244         }
13245
13246         switch (INTEL_INFO(dev)->gen) {
13247         case 2:
13248                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13249                 break;
13250
13251         case 3:
13252                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13253                 break;
13254
13255         case 4:
13256         case 5:
13257                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13258                 break;
13259
13260         case 6:
13261                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13262                 break;
13263         case 7:
13264         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13265                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13266                 break;
13267         case 9:
13268                 /* Drop through - unsupported since execlist only. */
13269         default:
13270                 /* Default just returns -ENODEV to indicate unsupported */
13271                 dev_priv->display.queue_flip = intel_default_queue_flip;
13272         }
13273
13274         intel_panel_init_backlight_funcs(dev);
13275
13276         mutex_init(&dev_priv->pps_mutex);
13277 }
13278
13279 /*
13280  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13281  * resume, or other times.  This quirk makes sure that's the case for
13282  * affected systems.
13283  */
13284 static void quirk_pipea_force(struct drm_device *dev)
13285 {
13286         struct drm_i915_private *dev_priv = dev->dev_private;
13287
13288         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13289         DRM_INFO("applying pipe a force quirk\n");
13290 }
13291
13292 static void quirk_pipeb_force(struct drm_device *dev)
13293 {
13294         struct drm_i915_private *dev_priv = dev->dev_private;
13295
13296         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13297         DRM_INFO("applying pipe b force quirk\n");
13298 }
13299
13300 /*
13301  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13302  */
13303 static void quirk_ssc_force_disable(struct drm_device *dev)
13304 {
13305         struct drm_i915_private *dev_priv = dev->dev_private;
13306         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13307         DRM_INFO("applying lvds SSC disable quirk\n");
13308 }
13309
13310 /*
13311  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13312  * brightness value
13313  */
13314 static void quirk_invert_brightness(struct drm_device *dev)
13315 {
13316         struct drm_i915_private *dev_priv = dev->dev_private;
13317         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13318         DRM_INFO("applying inverted panel brightness quirk\n");
13319 }
13320
13321 /* Some VBT's incorrectly indicate no backlight is present */
13322 static void quirk_backlight_present(struct drm_device *dev)
13323 {
13324         struct drm_i915_private *dev_priv = dev->dev_private;
13325         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13326         DRM_INFO("applying backlight present quirk\n");
13327 }
13328
13329 struct intel_quirk {
13330         int device;
13331         int subsystem_vendor;
13332         int subsystem_device;
13333         void (*hook)(struct drm_device *dev);
13334 };
13335
13336 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13337 struct intel_dmi_quirk {
13338         void (*hook)(struct drm_device *dev);
13339         const struct dmi_system_id (*dmi_id_list)[];
13340 };
13341
13342 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13343 {
13344         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13345         return 1;
13346 }
13347
13348 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13349         {
13350                 .dmi_id_list = &(const struct dmi_system_id[]) {
13351                         {
13352                                 .callback = intel_dmi_reverse_brightness,
13353                                 .ident = "NCR Corporation",
13354                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13355                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
13356                                 },
13357                         },
13358                         { }  /* terminating entry */
13359                 },
13360                 .hook = quirk_invert_brightness,
13361         },
13362 };
13363
13364 static struct intel_quirk intel_quirks[] = {
13365         /* HP Mini needs pipe A force quirk (LP: #322104) */
13366         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13367
13368         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13369         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13370
13371         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13372         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13373
13374         /* 830 needs to leave pipe A & dpll A up */
13375         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13376
13377         /* 830 needs to leave pipe B & dpll B up */
13378         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13379
13380         /* Lenovo U160 cannot use SSC on LVDS */
13381         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13382
13383         /* Sony Vaio Y cannot use SSC on LVDS */
13384         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13385
13386         /* Acer Aspire 5734Z must invert backlight brightness */
13387         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13388
13389         /* Acer/eMachines G725 */
13390         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13391
13392         /* Acer/eMachines e725 */
13393         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13394
13395         /* Acer/Packard Bell NCL20 */
13396         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13397
13398         /* Acer Aspire 4736Z */
13399         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13400
13401         /* Acer Aspire 5336 */
13402         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13403
13404         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13405         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13406
13407         /* Acer C720 Chromebook (Core i3 4005U) */
13408         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13409
13410         /* Apple Macbook 2,1 (Core 2 T7400) */
13411         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13412
13413         /* Toshiba CB35 Chromebook (Celeron 2955U) */
13414         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13415
13416         /* HP Chromebook 14 (Celeron 2955U) */
13417         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13418
13419         /* Dell Chromebook 11 */
13420         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13421 };
13422
13423 static void intel_init_quirks(struct drm_device *dev)
13424 {
13425         struct pci_dev *d = dev->pdev;
13426         int i;
13427
13428         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13429                 struct intel_quirk *q = &intel_quirks[i];
13430
13431                 if (d->device == q->device &&
13432                     (d->subsystem_vendor == q->subsystem_vendor ||
13433                      q->subsystem_vendor == PCI_ANY_ID) &&
13434                     (d->subsystem_device == q->subsystem_device ||
13435                      q->subsystem_device == PCI_ANY_ID))
13436                         q->hook(dev);
13437         }
13438         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13439                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13440                         intel_dmi_quirks[i].hook(dev);
13441         }
13442 }
13443
13444 /* Disable the VGA plane that we never use */
13445 static void i915_disable_vga(struct drm_device *dev)
13446 {
13447         struct drm_i915_private *dev_priv = dev->dev_private;
13448         u8 sr1;
13449         u32 vga_reg = i915_vgacntrl_reg(dev);
13450
13451         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13452         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13453         outb(SR01, VGA_SR_INDEX);
13454         sr1 = inb(VGA_SR_DATA);
13455         outb(sr1 | 1<<5, VGA_SR_DATA);
13456         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13457         udelay(300);
13458
13459         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13460         POSTING_READ(vga_reg);
13461 }
13462
13463 void intel_modeset_init_hw(struct drm_device *dev)
13464 {
13465         intel_prepare_ddi(dev);
13466
13467         if (IS_VALLEYVIEW(dev))
13468                 vlv_update_cdclk(dev);
13469
13470         intel_init_clock_gating(dev);
13471
13472         intel_enable_gt_powersave(dev);
13473 }
13474
13475 void intel_modeset_init(struct drm_device *dev)
13476 {
13477         struct drm_i915_private *dev_priv = dev->dev_private;
13478         int sprite, ret;
13479         enum pipe pipe;
13480         struct intel_crtc *crtc;
13481
13482         drm_mode_config_init(dev);
13483
13484         dev->mode_config.min_width = 0;
13485         dev->mode_config.min_height = 0;
13486
13487         dev->mode_config.preferred_depth = 24;
13488         dev->mode_config.prefer_shadow = 1;
13489
13490         dev->mode_config.allow_fb_modifiers = true;
13491
13492         dev->mode_config.funcs = &intel_mode_funcs;
13493
13494         intel_init_quirks(dev);
13495
13496         intel_init_pm(dev);
13497
13498         if (INTEL_INFO(dev)->num_pipes == 0)
13499                 return;
13500
13501         intel_init_display(dev);
13502         intel_init_audio(dev);
13503
13504         if (IS_GEN2(dev)) {
13505                 dev->mode_config.max_width = 2048;
13506                 dev->mode_config.max_height = 2048;
13507         } else if (IS_GEN3(dev)) {
13508                 dev->mode_config.max_width = 4096;
13509                 dev->mode_config.max_height = 4096;
13510         } else {
13511                 dev->mode_config.max_width = 8192;
13512                 dev->mode_config.max_height = 8192;
13513         }
13514
13515         if (IS_845G(dev) || IS_I865G(dev)) {
13516                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13517                 dev->mode_config.cursor_height = 1023;
13518         } else if (IS_GEN2(dev)) {
13519                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13520                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13521         } else {
13522                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13523                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13524         }
13525
13526         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13527
13528         DRM_DEBUG_KMS("%d display pipe%s available.\n",
13529                       INTEL_INFO(dev)->num_pipes,
13530                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13531
13532         for_each_pipe(dev_priv, pipe) {
13533                 intel_crtc_init(dev, pipe);
13534                 for_each_sprite(dev_priv, pipe, sprite) {
13535                         ret = intel_plane_init(dev, pipe, sprite);
13536                         if (ret)
13537                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13538                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
13539                 }
13540         }
13541
13542         intel_init_dpio(dev);
13543
13544         intel_shared_dpll_init(dev);
13545
13546         /* Just disable it once at startup */
13547         i915_disable_vga(dev);
13548         intel_setup_outputs(dev);
13549
13550         /* Just in case the BIOS is doing something questionable. */
13551         intel_fbc_disable(dev);
13552
13553         drm_modeset_lock_all(dev);
13554         intel_modeset_setup_hw_state(dev, false);
13555         drm_modeset_unlock_all(dev);
13556
13557         for_each_intel_crtc(dev, crtc) {
13558                 if (!crtc->active)
13559                         continue;
13560
13561                 /*
13562                  * Note that reserving the BIOS fb up front prevents us
13563                  * from stuffing other stolen allocations like the ring
13564                  * on top.  This prevents some ugliness at boot time, and
13565                  * can even allow for smooth boot transitions if the BIOS
13566                  * fb is large enough for the active pipe configuration.
13567                  */
13568                 if (dev_priv->display.get_initial_plane_config) {
13569                         dev_priv->display.get_initial_plane_config(crtc,
13570                                                            &crtc->plane_config);
13571                         /*
13572                          * If the fb is shared between multiple heads, we'll
13573                          * just get the first one.
13574                          */
13575                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13576                 }
13577         }
13578 }
13579
13580 static void intel_enable_pipe_a(struct drm_device *dev)
13581 {
13582         struct intel_connector *connector;
13583         struct drm_connector *crt = NULL;
13584         struct intel_load_detect_pipe load_detect_temp;
13585         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13586
13587         /* We can't just switch on the pipe A, we need to set things up with a
13588          * proper mode and output configuration. As a gross hack, enable pipe A
13589          * by enabling the load detect pipe once. */
13590         for_each_intel_connector(dev, connector) {
13591                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13592                         crt = &connector->base;
13593                         break;
13594                 }
13595         }
13596
13597         if (!crt)
13598                 return;
13599
13600         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13601                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13602 }
13603
13604 static bool
13605 intel_check_plane_mapping(struct intel_crtc *crtc)
13606 {
13607         struct drm_device *dev = crtc->base.dev;
13608         struct drm_i915_private *dev_priv = dev->dev_private;
13609         u32 reg, val;
13610
13611         if (INTEL_INFO(dev)->num_pipes == 1)
13612                 return true;
13613
13614         reg = DSPCNTR(!crtc->plane);
13615         val = I915_READ(reg);
13616
13617         if ((val & DISPLAY_PLANE_ENABLE) &&
13618             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13619                 return false;
13620
13621         return true;
13622 }
13623
13624 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13625 {
13626         struct drm_device *dev = crtc->base.dev;
13627         struct drm_i915_private *dev_priv = dev->dev_private;
13628         u32 reg;
13629
13630         /* Clear any frame start delays used for debugging left by the BIOS */
13631         reg = PIPECONF(crtc->config->cpu_transcoder);
13632         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13633
13634         /* restore vblank interrupts to correct state */
13635         drm_crtc_vblank_reset(&crtc->base);
13636         if (crtc->active) {
13637                 update_scanline_offset(crtc);
13638                 drm_crtc_vblank_on(&crtc->base);
13639         }
13640
13641         /* We need to sanitize the plane -> pipe mapping first because this will
13642          * disable the crtc (and hence change the state) if it is wrong. Note
13643          * that gen4+ has a fixed plane -> pipe mapping.  */
13644         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13645                 struct intel_connector *connector;
13646                 bool plane;
13647
13648                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13649                               crtc->base.base.id);
13650
13651                 /* Pipe has the wrong plane attached and the plane is active.
13652                  * Temporarily change the plane mapping and disable everything
13653                  * ...  */
13654                 plane = crtc->plane;
13655                 crtc->plane = !plane;
13656                 crtc->primary_enabled = true;
13657                 dev_priv->display.crtc_disable(&crtc->base);
13658                 crtc->plane = plane;
13659
13660                 /* ... and break all links. */
13661                 for_each_intel_connector(dev, connector) {
13662                         if (connector->encoder->base.crtc != &crtc->base)
13663                                 continue;
13664
13665                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13666                         connector->base.encoder = NULL;
13667                 }
13668                 /* multiple connectors may have the same encoder:
13669                  *  handle them and break crtc link separately */
13670                 for_each_intel_connector(dev, connector)
13671                         if (connector->encoder->base.crtc == &crtc->base) {
13672                                 connector->encoder->base.crtc = NULL;
13673                                 connector->encoder->connectors_active = false;
13674                         }
13675
13676                 WARN_ON(crtc->active);
13677                 crtc->base.state->enable = false;
13678                 crtc->base.enabled = false;
13679         }
13680
13681         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13682             crtc->pipe == PIPE_A && !crtc->active) {
13683                 /* BIOS forgot to enable pipe A, this mostly happens after
13684                  * resume. Force-enable the pipe to fix this, the update_dpms
13685                  * call below we restore the pipe to the right state, but leave
13686                  * the required bits on. */
13687                 intel_enable_pipe_a(dev);
13688         }
13689
13690         /* Adjust the state of the output pipe according to whether we
13691          * have active connectors/encoders. */
13692         intel_crtc_update_dpms(&crtc->base);
13693
13694         if (crtc->active != crtc->base.state->enable) {
13695                 struct intel_encoder *encoder;
13696
13697                 /* This can happen either due to bugs in the get_hw_state
13698                  * functions or because the pipe is force-enabled due to the
13699                  * pipe A quirk. */
13700                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13701                               crtc->base.base.id,
13702                               crtc->base.state->enable ? "enabled" : "disabled",
13703                               crtc->active ? "enabled" : "disabled");
13704
13705                 crtc->base.state->enable = crtc->active;
13706                 crtc->base.enabled = crtc->active;
13707
13708                 /* Because we only establish the connector -> encoder ->
13709                  * crtc links if something is active, this means the
13710                  * crtc is now deactivated. Break the links. connector
13711                  * -> encoder links are only establish when things are
13712                  *  actually up, hence no need to break them. */
13713                 WARN_ON(crtc->active);
13714
13715                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13716                         WARN_ON(encoder->connectors_active);
13717                         encoder->base.crtc = NULL;
13718                 }
13719         }
13720
13721         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13722                 /*
13723                  * We start out with underrun reporting disabled to avoid races.
13724                  * For correct bookkeeping mark this on active crtcs.
13725                  *
13726                  * Also on gmch platforms we dont have any hardware bits to
13727                  * disable the underrun reporting. Which means we need to start
13728                  * out with underrun reporting disabled also on inactive pipes,
13729                  * since otherwise we'll complain about the garbage we read when
13730                  * e.g. coming up after runtime pm.
13731                  *
13732                  * No protection against concurrent access is required - at
13733                  * worst a fifo underrun happens which also sets this to false.
13734                  */
13735                 crtc->cpu_fifo_underrun_disabled = true;
13736                 crtc->pch_fifo_underrun_disabled = true;
13737         }
13738 }
13739
13740 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13741 {
13742         struct intel_connector *connector;
13743         struct drm_device *dev = encoder->base.dev;
13744
13745         /* We need to check both for a crtc link (meaning that the
13746          * encoder is active and trying to read from a pipe) and the
13747          * pipe itself being active. */
13748         bool has_active_crtc = encoder->base.crtc &&
13749                 to_intel_crtc(encoder->base.crtc)->active;
13750
13751         if (encoder->connectors_active && !has_active_crtc) {
13752                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13753                               encoder->base.base.id,
13754                               encoder->base.name);
13755
13756                 /* Connector is active, but has no active pipe. This is
13757                  * fallout from our resume register restoring. Disable
13758                  * the encoder manually again. */
13759                 if (encoder->base.crtc) {
13760                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13761                                       encoder->base.base.id,
13762                                       encoder->base.name);
13763                         encoder->disable(encoder);
13764                         if (encoder->post_disable)
13765                                 encoder->post_disable(encoder);
13766                 }
13767                 encoder->base.crtc = NULL;
13768                 encoder->connectors_active = false;
13769
13770                 /* Inconsistent output/port/pipe state happens presumably due to
13771                  * a bug in one of the get_hw_state functions. Or someplace else
13772                  * in our code, like the register restore mess on resume. Clamp
13773                  * things to off as a safer default. */
13774                 for_each_intel_connector(dev, connector) {
13775                         if (connector->encoder != encoder)
13776                                 continue;
13777                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13778                         connector->base.encoder = NULL;
13779                 }
13780         }
13781         /* Enabled encoders without active connectors will be fixed in
13782          * the crtc fixup. */
13783 }
13784
13785 void i915_redisable_vga_power_on(struct drm_device *dev)
13786 {
13787         struct drm_i915_private *dev_priv = dev->dev_private;
13788         u32 vga_reg = i915_vgacntrl_reg(dev);
13789
13790         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13791                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13792                 i915_disable_vga(dev);
13793         }
13794 }
13795
13796 void i915_redisable_vga(struct drm_device *dev)
13797 {
13798         struct drm_i915_private *dev_priv = dev->dev_private;
13799
13800         /* This function can be called both from intel_modeset_setup_hw_state or
13801          * at a very early point in our resume sequence, where the power well
13802          * structures are not yet restored. Since this function is at a very
13803          * paranoid "someone might have enabled VGA while we were not looking"
13804          * level, just check if the power well is enabled instead of trying to
13805          * follow the "don't touch the power well if we don't need it" policy
13806          * the rest of the driver uses. */
13807         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13808                 return;
13809
13810         i915_redisable_vga_power_on(dev);
13811 }
13812
13813 static bool primary_get_hw_state(struct intel_crtc *crtc)
13814 {
13815         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13816
13817         if (!crtc->active)
13818                 return false;
13819
13820         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13821 }
13822
13823 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13824 {
13825         struct drm_i915_private *dev_priv = dev->dev_private;
13826         enum pipe pipe;
13827         struct intel_crtc *crtc;
13828         struct intel_encoder *encoder;
13829         struct intel_connector *connector;
13830         int i;
13831
13832         for_each_intel_crtc(dev, crtc) {
13833                 memset(crtc->config, 0, sizeof(*crtc->config));
13834
13835                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13836
13837                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13838                                                                  crtc->config);
13839
13840                 crtc->base.state->enable = crtc->active;
13841                 crtc->base.enabled = crtc->active;
13842                 crtc->primary_enabled = primary_get_hw_state(crtc);
13843
13844                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13845                               crtc->base.base.id,
13846                               crtc->active ? "enabled" : "disabled");
13847         }
13848
13849         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13850                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13851
13852                 pll->on = pll->get_hw_state(dev_priv, pll,
13853                                             &pll->config.hw_state);
13854                 pll->active = 0;
13855                 pll->config.crtc_mask = 0;
13856                 for_each_intel_crtc(dev, crtc) {
13857                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13858                                 pll->active++;
13859                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13860                         }
13861                 }
13862
13863                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13864                               pll->name, pll->config.crtc_mask, pll->on);
13865
13866                 if (pll->config.crtc_mask)
13867                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13868         }
13869
13870         for_each_intel_encoder(dev, encoder) {
13871                 pipe = 0;
13872
13873                 if (encoder->get_hw_state(encoder, &pipe)) {
13874                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13875                         encoder->base.crtc = &crtc->base;
13876                         encoder->get_config(encoder, crtc->config);
13877                 } else {
13878                         encoder->base.crtc = NULL;
13879                 }
13880
13881                 encoder->connectors_active = false;
13882                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13883                               encoder->base.base.id,
13884                               encoder->base.name,
13885                               encoder->base.crtc ? "enabled" : "disabled",
13886                               pipe_name(pipe));
13887         }
13888
13889         for_each_intel_connector(dev, connector) {
13890                 if (connector->get_hw_state(connector)) {
13891                         connector->base.dpms = DRM_MODE_DPMS_ON;
13892                         connector->encoder->connectors_active = true;
13893                         connector->base.encoder = &connector->encoder->base;
13894                 } else {
13895                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13896                         connector->base.encoder = NULL;
13897                 }
13898                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13899                               connector->base.base.id,
13900                               connector->base.name,
13901                               connector->base.encoder ? "enabled" : "disabled");
13902         }
13903 }
13904
13905 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13906  * and i915 state tracking structures. */
13907 void intel_modeset_setup_hw_state(struct drm_device *dev,
13908                                   bool force_restore)
13909 {
13910         struct drm_i915_private *dev_priv = dev->dev_private;
13911         enum pipe pipe;
13912         struct intel_crtc *crtc;
13913         struct intel_encoder *encoder;
13914         int i;
13915
13916         intel_modeset_readout_hw_state(dev);
13917
13918         /*
13919          * Now that we have the config, copy it to each CRTC struct
13920          * Note that this could go away if we move to using crtc_config
13921          * checking everywhere.
13922          */
13923         for_each_intel_crtc(dev, crtc) {
13924                 if (crtc->active && i915.fastboot) {
13925                         intel_mode_from_pipe_config(&crtc->base.mode,
13926                                                     crtc->config);
13927                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13928                                       crtc->base.base.id);
13929                         drm_mode_debug_printmodeline(&crtc->base.mode);
13930                 }
13931         }
13932
13933         /* HW state is read out, now we need to sanitize this mess. */
13934         for_each_intel_encoder(dev, encoder) {
13935                 intel_sanitize_encoder(encoder);
13936         }
13937
13938         for_each_pipe(dev_priv, pipe) {
13939                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13940                 intel_sanitize_crtc(crtc);
13941                 intel_dump_pipe_config(crtc, crtc->config,
13942                                        "[setup_hw_state]");
13943         }
13944
13945         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13946                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13947
13948                 if (!pll->on || pll->active)
13949                         continue;
13950
13951                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13952
13953                 pll->disable(dev_priv, pll);
13954                 pll->on = false;
13955         }
13956
13957         if (IS_GEN9(dev))
13958                 skl_wm_get_hw_state(dev);
13959         else if (HAS_PCH_SPLIT(dev))
13960                 ilk_wm_get_hw_state(dev);
13961
13962         if (force_restore) {
13963                 i915_redisable_vga(dev);
13964
13965                 /*
13966                  * We need to use raw interfaces for restoring state to avoid
13967                  * checking (bogus) intermediate states.
13968                  */
13969                 for_each_pipe(dev_priv, pipe) {
13970                         struct drm_crtc *crtc =
13971                                 dev_priv->pipe_to_crtc_mapping[pipe];
13972
13973                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13974                                        crtc->primary->fb);
13975                 }
13976         } else {
13977                 intel_modeset_update_staged_output_state(dev);
13978         }
13979
13980         intel_modeset_check_state(dev);
13981 }
13982
13983 void intel_modeset_gem_init(struct drm_device *dev)
13984 {
13985         struct drm_i915_private *dev_priv = dev->dev_private;
13986         struct drm_crtc *c;
13987         struct drm_i915_gem_object *obj;
13988
13989         mutex_lock(&dev->struct_mutex);
13990         intel_init_gt_powersave(dev);
13991         mutex_unlock(&dev->struct_mutex);
13992
13993         /*
13994          * There may be no VBT; and if the BIOS enabled SSC we can
13995          * just keep using it to avoid unnecessary flicker.  Whereas if the
13996          * BIOS isn't using it, don't assume it will work even if the VBT
13997          * indicates as much.
13998          */
13999         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14000                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14001                                                 DREF_SSC1_ENABLE);
14002
14003         intel_modeset_init_hw(dev);
14004
14005         intel_setup_overlay(dev);
14006
14007         /*
14008          * Make sure any fbs we allocated at startup are properly
14009          * pinned & fenced.  When we do the allocation it's too early
14010          * for this.
14011          */
14012         mutex_lock(&dev->struct_mutex);
14013         for_each_crtc(dev, c) {
14014                 obj = intel_fb_obj(c->primary->fb);
14015                 if (obj == NULL)
14016                         continue;
14017
14018                 if (intel_pin_and_fence_fb_obj(c->primary,
14019                                                c->primary->fb,
14020                                                c->primary->state,
14021                                                NULL)) {
14022                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
14023                                   to_intel_crtc(c)->pipe);
14024                         drm_framebuffer_unreference(c->primary->fb);
14025                         c->primary->fb = NULL;
14026                         update_state_fb(c->primary);
14027                 }
14028         }
14029         mutex_unlock(&dev->struct_mutex);
14030
14031         intel_backlight_register(dev);
14032 }
14033
14034 void intel_connector_unregister(struct intel_connector *intel_connector)
14035 {
14036         struct drm_connector *connector = &intel_connector->base;
14037
14038         intel_panel_destroy_backlight(connector);
14039         drm_connector_unregister(connector);
14040 }
14041
14042 void intel_modeset_cleanup(struct drm_device *dev)
14043 {
14044         struct drm_i915_private *dev_priv = dev->dev_private;
14045         struct drm_connector *connector;
14046
14047         intel_disable_gt_powersave(dev);
14048
14049         intel_backlight_unregister(dev);
14050
14051         /*
14052          * Interrupts and polling as the first thing to avoid creating havoc.
14053          * Too much stuff here (turning of connectors, ...) would
14054          * experience fancy races otherwise.
14055          */
14056         intel_irq_uninstall(dev_priv);
14057
14058         /*
14059          * Due to the hpd irq storm handling the hotplug work can re-arm the
14060          * poll handlers. Hence disable polling after hpd handling is shut down.
14061          */
14062         drm_kms_helper_poll_fini(dev);
14063
14064         mutex_lock(&dev->struct_mutex);
14065
14066         intel_unregister_dsm_handler();
14067
14068         intel_fbc_disable(dev);
14069
14070         mutex_unlock(&dev->struct_mutex);
14071
14072         /* flush any delayed tasks or pending work */
14073         flush_scheduled_work();
14074
14075         /* destroy the backlight and sysfs files before encoders/connectors */
14076         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14077                 struct intel_connector *intel_connector;
14078
14079                 intel_connector = to_intel_connector(connector);
14080                 intel_connector->unregister(intel_connector);
14081         }
14082
14083         drm_mode_config_cleanup(dev);
14084
14085         intel_cleanup_overlay(dev);
14086
14087         mutex_lock(&dev->struct_mutex);
14088         intel_cleanup_gt_powersave(dev);
14089         mutex_unlock(&dev->struct_mutex);
14090 }
14091
14092 /*
14093  * Return which encoder is currently attached for connector.
14094  */
14095 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14096 {
14097         return &intel_attached_encoder(connector)->base;
14098 }
14099
14100 void intel_connector_attach_encoder(struct intel_connector *connector,
14101                                     struct intel_encoder *encoder)
14102 {
14103         connector->encoder = encoder;
14104         drm_mode_connector_attach_encoder(&connector->base,
14105                                           &encoder->base);
14106 }
14107
14108 /*
14109  * set vga decode state - true == enable VGA decode
14110  */
14111 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14112 {
14113         struct drm_i915_private *dev_priv = dev->dev_private;
14114         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14115         u16 gmch_ctrl;
14116
14117         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14118                 DRM_ERROR("failed to read control word\n");
14119                 return -EIO;
14120         }
14121
14122         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14123                 return 0;
14124
14125         if (state)
14126                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14127         else
14128                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14129
14130         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14131                 DRM_ERROR("failed to write control word\n");
14132                 return -EIO;
14133         }
14134
14135         return 0;
14136 }
14137
14138 struct intel_display_error_state {
14139
14140         u32 power_well_driver;
14141
14142         int num_transcoders;
14143
14144         struct intel_cursor_error_state {
14145                 u32 control;
14146                 u32 position;
14147                 u32 base;
14148                 u32 size;
14149         } cursor[I915_MAX_PIPES];
14150
14151         struct intel_pipe_error_state {
14152                 bool power_domain_on;
14153                 u32 source;
14154                 u32 stat;
14155         } pipe[I915_MAX_PIPES];
14156
14157         struct intel_plane_error_state {
14158                 u32 control;
14159                 u32 stride;
14160                 u32 size;
14161                 u32 pos;
14162                 u32 addr;
14163                 u32 surface;
14164                 u32 tile_offset;
14165         } plane[I915_MAX_PIPES];
14166
14167         struct intel_transcoder_error_state {
14168                 bool power_domain_on;
14169                 enum transcoder cpu_transcoder;
14170
14171                 u32 conf;
14172
14173                 u32 htotal;
14174                 u32 hblank;
14175                 u32 hsync;
14176                 u32 vtotal;
14177                 u32 vblank;
14178                 u32 vsync;
14179         } transcoder[4];
14180 };
14181
14182 struct intel_display_error_state *
14183 intel_display_capture_error_state(struct drm_device *dev)
14184 {
14185         struct drm_i915_private *dev_priv = dev->dev_private;
14186         struct intel_display_error_state *error;
14187         int transcoders[] = {
14188                 TRANSCODER_A,
14189                 TRANSCODER_B,
14190                 TRANSCODER_C,
14191                 TRANSCODER_EDP,
14192         };
14193         int i;
14194
14195         if (INTEL_INFO(dev)->num_pipes == 0)
14196                 return NULL;
14197
14198         error = kzalloc(sizeof(*error), GFP_ATOMIC);
14199         if (error == NULL)
14200                 return NULL;
14201
14202         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14203                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14204
14205         for_each_pipe(dev_priv, i) {
14206                 error->pipe[i].power_domain_on =
14207                         __intel_display_power_is_enabled(dev_priv,
14208                                                          POWER_DOMAIN_PIPE(i));
14209                 if (!error->pipe[i].power_domain_on)
14210                         continue;
14211
14212                 error->cursor[i].control = I915_READ(CURCNTR(i));
14213                 error->cursor[i].position = I915_READ(CURPOS(i));
14214                 error->cursor[i].base = I915_READ(CURBASE(i));
14215
14216                 error->plane[i].control = I915_READ(DSPCNTR(i));
14217                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14218                 if (INTEL_INFO(dev)->gen <= 3) {
14219                         error->plane[i].size = I915_READ(DSPSIZE(i));
14220                         error->plane[i].pos = I915_READ(DSPPOS(i));
14221                 }
14222                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14223                         error->plane[i].addr = I915_READ(DSPADDR(i));
14224                 if (INTEL_INFO(dev)->gen >= 4) {
14225                         error->plane[i].surface = I915_READ(DSPSURF(i));
14226                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14227                 }
14228
14229                 error->pipe[i].source = I915_READ(PIPESRC(i));
14230
14231                 if (HAS_GMCH_DISPLAY(dev))
14232                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
14233         }
14234
14235         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14236         if (HAS_DDI(dev_priv->dev))
14237                 error->num_transcoders++; /* Account for eDP. */
14238
14239         for (i = 0; i < error->num_transcoders; i++) {
14240                 enum transcoder cpu_transcoder = transcoders[i];
14241
14242                 error->transcoder[i].power_domain_on =
14243                         __intel_display_power_is_enabled(dev_priv,
14244                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14245                 if (!error->transcoder[i].power_domain_on)
14246                         continue;
14247
14248                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14249
14250                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14251                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14252                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14253                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14254                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14255                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14256                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14257         }
14258
14259         return error;
14260 }
14261
14262 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14263
14264 void
14265 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14266                                 struct drm_device *dev,
14267                                 struct intel_display_error_state *error)
14268 {
14269         struct drm_i915_private *dev_priv = dev->dev_private;
14270         int i;
14271
14272         if (!error)
14273                 return;
14274
14275         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14276         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14277                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14278                            error->power_well_driver);
14279         for_each_pipe(dev_priv, i) {
14280                 err_printf(m, "Pipe [%d]:\n", i);
14281                 err_printf(m, "  Power: %s\n",
14282                            error->pipe[i].power_domain_on ? "on" : "off");
14283                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
14284                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
14285
14286                 err_printf(m, "Plane [%d]:\n", i);
14287                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
14288                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
14289                 if (INTEL_INFO(dev)->gen <= 3) {
14290                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
14291                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
14292                 }
14293                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14294                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
14295                 if (INTEL_INFO(dev)->gen >= 4) {
14296                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
14297                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
14298                 }
14299
14300                 err_printf(m, "Cursor [%d]:\n", i);
14301                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
14302                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
14303                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
14304         }
14305
14306         for (i = 0; i < error->num_transcoders; i++) {
14307                 err_printf(m, "CPU transcoder: %c\n",
14308                            transcoder_name(error->transcoder[i].cpu_transcoder));
14309                 err_printf(m, "  Power: %s\n",
14310                            error->transcoder[i].power_domain_on ? "on" : "off");
14311                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
14312                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
14313                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
14314                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
14315                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
14316                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
14317                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
14318         }
14319 }
14320
14321 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14322 {
14323         struct intel_crtc *crtc;
14324
14325         for_each_intel_crtc(dev, crtc) {
14326                 struct intel_unpin_work *work;
14327
14328                 spin_lock_irq(&dev->event_lock);
14329
14330                 work = crtc->unpin_work;
14331
14332                 if (work && work->event &&
14333                     work->event->base.file_priv == file) {
14334                         kfree(work->event);
14335                         work->event = NULL;
14336                 }
14337
14338                 spin_unlock_irq(&dev->event_lock);
14339         }
14340 }