drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 8, .max = 18 },
 158         .m2 = { .min = 3, .max = 7 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 8, .max = 18 },
 172         .m2 = { .min = 3, .max = 7 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 420
 421         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 422                 DRM_ERROR("DPIO idle wait timed out\n");
 423                 return 0;
 424         }
 425
 426         I915_WRITE(DPIO_REG, reg);
 427         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 428                    DPIO_BYTE);
 429         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 430                 DRM_ERROR("DPIO read wait timed out\n");
 431                 return 0;
 432         }
 433
 434         return I915_READ(DPIO_DATA);
 435 }
 436
 437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 438                              u32 val)
 439 {
 440         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 441
 442         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 443                 DRM_ERROR("DPIO idle wait timed out\n");
 444                 return;
 445         }
 446
 447         I915_WRITE(DPIO_DATA, val);
 448         I915_WRITE(DPIO_REG, reg);
 449         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 450                    DPIO_BYTE);
 451         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 452                 DRM_ERROR("DPIO write wait timed out\n");
 453 }
 454
 455 static void vlv_init_dpio(struct drm_device *dev)
 456 {
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458
 459         /* Reset the DPIO config */
 460         I915_WRITE(DPIO_CTL, 0);
 461         POSTING_READ(DPIO_CTL);
 462         I915_WRITE(DPIO_CTL, 1);
 463         POSTING_READ(DPIO_CTL);
 464 }
 465
 466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 467                                                 int refclk)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         const intel_limit_t *limit;
 471
 472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 473                 if (intel_is_dual_link_lvds(dev)) {
 474                         /* LVDS dual channel */
 475                         if (refclk == 100000)
 476                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 477                         else
 478                                 limit = &intel_limits_ironlake_dual_lvds;
 479                 } else {
 480                         if (refclk == 100000)
 481                                 limit = &intel_limits_ironlake_single_lvds_100m;
 482                         else
 483                                 limit = &intel_limits_ironlake_single_lvds;
 484                 }
 485         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 486                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 487                 limit = &intel_limits_ironlake_display_port;
 488         else
 489                 limit = &intel_limits_ironlake_dac;
 490
 491         return limit;
 492 }
 493
 494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         const intel_limit_t *limit;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 if (intel_is_dual_link_lvds(dev))
 501                         /* LVDS with dual channel */
 502                         limit = &intel_limits_g4x_dual_channel_lvds;
 503                 else
 504                         /* LVDS with dual channel */
 505                         limit = &intel_limits_g4x_single_channel_lvds;
 506         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 507                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 508                 limit = &intel_limits_g4x_hdmi;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 510                 limit = &intel_limits_g4x_sdvo;
 511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 512                 limit = &intel_limits_g4x_display_port;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         const intel_limit_t *limit;
 523
 524         if (HAS_PCH_SPLIT(dev))
 525                 limit = intel_ironlake_limit(crtc, refclk);
 526         else if (IS_G4X(dev)) {
 527                 limit = intel_g4x_limit(crtc);
 528         } else if (IS_PINEVIEW(dev)) {
 529                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 530                         limit = &intel_limits_pineview_lvds;
 531                 else
 532                         limit = &intel_limits_pineview_sdvo;
 533         } else if (IS_VALLEYVIEW(dev)) {
 534                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 535                         limit = &intel_limits_vlv_dac;
 536                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 537                         limit = &intel_limits_vlv_hdmi;
 538                 else
 539                         limit = &intel_limits_vlv_dp;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else
 549                         limit = &intel_limits_i8xx_dvo;
 550         }
 551         return limit;
 552 }
 553
 554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 555 static void pineview_clock(int refclk, intel_clock_t *clock)
 556 {
 557         clock->m = clock->m2 + 2;
 558         clock->p = clock->p1 * clock->p2;
 559         clock->vco = refclk * clock->m / clock->n;
 560         clock->dot = clock->vco / clock->p;
 561 }
 562
 563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 564 {
 565         if (IS_PINEVIEW(dev)) {
 566                 pineview_clock(refclk, clock);
 567                 return;
 568         }
 569         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 570         clock->p = clock->p1 * clock->p2;
 571         clock->vco = refclk * clock->m / (clock->n + 2);
 572         clock->dot = clock->vco / clock->p;
 573 }
 574
 575 /**
 576  * Returns whether any output on the specified pipe is of the specified type
 577  */
 578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         struct intel_encoder *encoder;
 582
 583         for_each_encoder_on_crtc(dev, crtc, encoder)
 584                 if (encoder->type == type)
 585                         return true;
 586
 587         return false;
 588 }
 589
 590 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 591 /**
 592  * Returns whether the given set of divisors are valid for a given refclk with
 593  * the given connectors.
 594  */
 595
 596 static bool intel_PLL_is_valid(struct drm_device *dev,
 597                                const intel_limit_t *limit,
 598                                const intel_clock_t *clock)
 599 {
 600         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 601                 INTELPllInvalid("p1 out of range\n");
 602         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 603                 INTELPllInvalid("p out of range\n");
 604         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 605                 INTELPllInvalid("m2 out of range\n");
 606         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 607                 INTELPllInvalid("m1 out of range\n");
 608         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 609                 INTELPllInvalid("m1 <= m2\n");
 610         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 611                 INTELPllInvalid("m out of range\n");
 612         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 613                 INTELPllInvalid("n out of range\n");
 614         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 615                 INTELPllInvalid("vco out of range\n");
 616         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 617          * connector, etc., rather than just a single range.
 618          */
 619         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 620                 INTELPllInvalid("dot out of range\n");
 621
 622         return true;
 623 }
 624
 625 static bool
 626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                     int target, int refclk, intel_clock_t *match_clock,
 628                     intel_clock_t *best_clock)
 629
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int err = target;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 /*
 637                  * For LVDS just rely on its current settings for dual-channel.
 638                  * We haven't figured out how to reliably set up different
 639                  * single/dual channel state, if we even can.
 640                  */
 641                 if (intel_is_dual_link_lvds(dev))
 642                         clock.p2 = limit->p2.p2_fast;
 643                 else
 644                         clock.p2 = limit->p2.p2_slow;
 645         } else {
 646                 if (target < limit->p2.dot_limit)
 647                         clock.p2 = limit->p2.p2_slow;
 648                 else
 649                         clock.p2 = limit->p2.p2_fast;
 650         }
 651
 652         memset(best_clock, 0, sizeof(*best_clock));
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         /* m1 is always 0 in Pineview */
 659                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 660                                 break;
 661                         for (clock.n = limit->n.min;
 662                              clock.n <= limit->n.max; clock.n++) {
 663                                 for (clock.p1 = limit->p1.min;
 664                                         clock.p1 <= limit->p1.max; clock.p1++) {
 665                                         int this_err;
 666
 667                                         intel_clock(dev, refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 static bool
 689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                         int target, int refclk, intel_clock_t *match_clock,
 691                         intel_clock_t *best_clock)
 692 {
 693         struct drm_device *dev = crtc->dev;
 694         intel_clock_t clock;
 695         int max_n;
 696         bool found;
 697         /* approximately equals target * 0.00585 */
 698         int err_most = (target >> 8) + (target >> 9);
 699         found = false;
 700
 701         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 702                 int lvds_reg;
 703
 704                 if (HAS_PCH_SPLIT(dev))
 705                         lvds_reg = PCH_LVDS;
 706                 else
 707                         lvds_reg = LVDS;
 708                 if (intel_is_dual_link_lvds(dev))
 709                         clock.p2 = limit->p2.p2_fast;
 710                 else
 711                         clock.p2 = limit->p2.p2_slow;
 712         } else {
 713                 if (target < limit->p2.dot_limit)
 714                         clock.p2 = limit->p2.p2_slow;
 715                 else
 716                         clock.p2 = limit->p2.p2_fast;
 717         }
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720         max_n = limit->n.max;
 721         /* based on hardware requirement, prefer smaller n to precision */
 722         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 723                 /* based on hardware requirement, prefere larger m1,m2 */
 724                 for (clock.m1 = limit->m1.max;
 725                      clock.m1 >= limit->m1.min; clock.m1--) {
 726                         for (clock.m2 = limit->m2.max;
 727                              clock.m2 >= limit->m2.min; clock.m2--) {
 728                                 for (clock.p1 = limit->p1.max;
 729                                      clock.p1 >= limit->p1.min; clock.p1--) {
 730                                         int this_err;
 731
 732                                         intel_clock(dev, refclk, &clock);
 733                                         if (!intel_PLL_is_valid(dev, limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                            int target, int refclk, intel_clock_t *match_clock,
 757                            intel_clock_t *best_clock)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         intel_clock_t clock;
 761
 762         if (target < 200000) {
 763                 clock.n = 1;
 764                 clock.p1 = 2;
 765                 clock.p2 = 10;
 766                 clock.m1 = 12;
 767                 clock.m2 = 9;
 768         } else {
 769                 clock.n = 2;
 770                 clock.p1 = 1;
 771                 clock.p2 = 10;
 772                 clock.m1 = 14;
 773                 clock.m2 = 8;
 774         }
 775         intel_clock(dev, refclk, &clock);
 776         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 777         return true;
 778 }
 779
 780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 781 static bool
 782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 783                       int target, int refclk, intel_clock_t *match_clock,
 784                       intel_clock_t *best_clock)
 785 {
 786         intel_clock_t clock;
 787         if (target < 200000) {
 788                 clock.p1 = 2;
 789                 clock.p2 = 10;
 790                 clock.n = 2;
 791                 clock.m1 = 23;
 792                 clock.m2 = 8;
 793         } else {
 794                 clock.p1 = 1;
 795                 clock.p2 = 10;
 796                 clock.n = 1;
 797                 clock.m1 = 14;
 798                 clock.m2 = 2;
 799         }
 800         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 801         clock.p = (clock.p1 * clock.p2);
 802         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 803         clock.vco = 0;
 804         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 805         return true;
 806 }
 807 static bool
 808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 809                         int target, int refclk, intel_clock_t *match_clock,
 810                         intel_clock_t *best_clock)
 811 {
 812         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 813         u32 m, n, fastclk;
 814         u32 updrate, minupdate, fracbits, p;
 815         unsigned long bestppm, ppm, absppm;
 816         int dotclk, flag;
 817
 818         flag = 0;
 819         dotclk = target * 1000;
 820         bestppm = 1000000;
 821         ppm = absppm = 0;
 822         fastclk = dotclk / (2*100);
 823         updrate = 0;
 824         minupdate = 19200;
 825         fracbits = 1;
 826         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 827         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 828
 829         /* based on hardware requirement, prefer smaller n to precision */
 830         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 831                 updrate = refclk / n;
 832                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 833                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 834                                 if (p2 > 10)
 835                                         p2 = p2 - 1;
 836                                 p = p1 * p2;
 837                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 838                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 839                                         m2 = (((2*(fastclk * p * n / m1 )) +
 840                                                refclk) / (2*refclk));
 841                                         m = m1 * m2;
 842                                         vco = updrate * m;
 843                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 844                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 845                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 846                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 847                                                         bestppm = 0;
 848                                                         flag = 1;
 849                                                 }
 850                                                 if (absppm < bestppm - 10) {
 851                                                         bestppm = absppm;
 852                                                         flag = 1;
 853                                                 }
 854                                                 if (flag) {
 855                                                         bestn = n;
 856                                                         bestm1 = m1;
 857                                                         bestm2 = m2;
 858                                                         bestp1 = p1;
 859                                                         bestp2 = p2;
 860                                                         flag = 0;
 861                                                 }
 862                                         }
 863                                 }
 864                         }
 865                 }
 866         }
 867         best_clock->n = bestn;
 868         best_clock->m1 = bestm1;
 869         best_clock->m2 = bestm2;
 870         best_clock->p1 = bestp1;
 871         best_clock->p2 = bestp2;
 872
 873         return true;
 874 }
 875
 876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 877                                              enum pipe pipe)
 878 {
 879         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 881
 882         return intel_crtc->cpu_transcoder;
 883 }
 884
 885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 886 {
 887         struct drm_i915_private *dev_priv = dev->dev_private;
 888         u32 frame, frame_reg = PIPEFRAME(pipe);
 889
 890         frame = I915_READ(frame_reg);
 891
 892         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 /**
 897  * intel_wait_for_vblank - wait for vblank on a given pipe
 898  * @dev: drm device
 899  * @pipe: pipe to wait for
 900  *
 901  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 902  * mode setting code.
 903  */
 904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 905 {
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         int pipestat_reg = PIPESTAT(pipe);
 908
 909         if (INTEL_INFO(dev)->gen >= 5) {
 910                 ironlake_wait_for_vblank(dev, pipe);
 911                 return;
 912         }
 913
 914         /* Clear existing vblank status. Note this will clear any other
 915          * sticky status fields as well.
 916          *
 917          * This races with i915_driver_irq_handler() with the result
 918          * that either function could miss a vblank event.  Here it is not
 919          * fatal, as we will either wait upon the next vblank interrupt or
 920          * timeout.  Generally speaking intel_wait_for_vblank() is only
 921          * called during modeset at which time the GPU should be idle and
 922          * should *not* be performing page flips and thus not waiting on
 923          * vblanks...
 924          * Currently, the result of us stealing a vblank from the irq
 925          * handler is that a single frame will be skipped during swapbuffers.
 926          */
 927         I915_WRITE(pipestat_reg,
 928                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 929
 930         /* Wait for vblank interrupt bit to set */
 931         if (wait_for(I915_READ(pipestat_reg) &
 932                      PIPE_VBLANK_INTERRUPT_STATUS,
 933                      50))
 934                 DRM_DEBUG_KMS("vblank wait timed out\n");
 935 }
 936
 937 /*
 938  * intel_wait_for_pipe_off - wait for pipe to turn off
 939  * @dev: drm device
 940  * @pipe: pipe to wait for
 941  *
 942  * After disabling a pipe, we can't wait for vblank in the usual way,
 943  * spinning on the vblank interrupt status bit, since we won't actually
 944  * see an interrupt when the pipe is disabled.
 945  *
 946  * On Gen4 and above:
 947  *   wait for the pipe register state bit to turn off
 948  *
 949  * Otherwise:
 950  *   wait for the display line value to settle (it usually
 951  *   ends up stopping at the start of the next frame).
 952  *
 953  */
 954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 955 {
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 958                                                                       pipe);
 959
 960         if (INTEL_INFO(dev)->gen >= 4) {
 961                 int reg = PIPECONF(cpu_transcoder);
 962
 963                 /* Wait for the Pipe State to go off */
 964                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 965                              100))
 966                         WARN(1, "pipe_off wait timed out\n");
 967         } else {
 968                 u32 last_line, line_mask;
 969                 int reg = PIPEDSL(pipe);
 970                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 971
 972                 if (IS_GEN2(dev))
 973                         line_mask = DSL_LINEMASK_GEN2;
 974                 else
 975                         line_mask = DSL_LINEMASK_GEN3;
 976
 977                 /* Wait for the display line to settle */
 978                 do {
 979                         last_line = I915_READ(reg) & line_mask;
 980                         mdelay(5);
 981                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 982                          time_after(timeout, jiffies));
 983                 if (time_after(jiffies, timeout))
 984                         WARN(1, "pipe_off wait timed out\n");
 985         }
 986 }
 987
 988 /*
 989  * ibx_digital_port_connected - is the specified port connected?
 990  * @dev_priv: i915 private structure
 991  * @port: the port to test
 992  *
 993  * Returns true if @port is connected, false otherwise.
 994  */
 995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 996                                 struct intel_digital_port *port)
 997 {
 998         u32 bit;
 999
1000         if (HAS_PCH_IBX(dev_priv->dev)) {
1001                 switch(port->port) {
1002                 case PORT_B:
1003                         bit = SDE_PORTB_HOTPLUG;
1004                         break;
1005                 case PORT_C:
1006                         bit = SDE_PORTC_HOTPLUG;
1007                         break;
1008                 case PORT_D:
1009                         bit = SDE_PORTD_HOTPLUG;
1010                         break;
1011                 default:
1012                         return true;
1013                 }
1014         } else {
1015                 switch(port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG_CPT;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG_CPT;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG_CPT;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         }
1029
1030         return I915_READ(SDEISR) & bit;
1031 }
1032
1033 static const char *state_string(bool enabled)
1034 {
1035         return enabled ? "on" : "off";
1036 }
1037
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = DPLL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & DPLL_VCO_ENABLE);
1049         WARN(cur_state != state,
1050              "PLL state assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056 /* For ILK+ */
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058                            struct intel_pch_pll *pll,
1059                            struct intel_crtc *crtc,
1060                            bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         if (HAS_PCH_LPT(dev_priv->dev)) {
1066                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067                 return;
1068         }
1069
1070         if (WARN (!pll,
1071                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072                 return;
1073
1074         val = I915_READ(pll->pll_reg);
1075         cur_state = !!(val & DPLL_VCO_ENABLE);
1076         WARN(cur_state != state,
1077              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078              pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080         /* Make sure the selected PLL is correctly attached to the transcoder */
1081         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082                 u32 pch_dpll;
1083
1084                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1088                           cur_state, crtc->pipe, pch_dpll)) {
1089                         cur_state = !!(val >> (4*crtc->pipe + 3));
1090                         WARN(cur_state != state,
1091                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1092                              pll->pll_reg == _PCH_DPLL_B,
1093                              state_string(state),
1094                              crtc->pipe,
1095                              val);
1096                 }
1097         }
1098 }
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109                                                                       pipe);
1110
1111         if (HAS_DDI(dev_priv->dev)) {
1112                 /* DDI does not have a specific FDI_TX register */
1113                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116         } else {
1117                 reg = FDI_TX_CTL(pipe);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & FDI_TX_ENABLE);
1120         }
1121         WARN(cur_state != state,
1122              "FDI TX state assertion failure (expected %s, current %s)\n",
1123              state_string(state), state_string(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         int reg;
1132         u32 val;
1133         bool cur_state;
1134
1135         reg = FDI_RX_CTL(pipe);
1136         val = I915_READ(reg);
1137         cur_state = !!(val & FDI_RX_ENABLE);
1138         WARN(cur_state != state,
1139              "FDI RX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146                                       enum pipe pipe)
1147 {
1148         int reg;
1149         u32 val;
1150
1151         /* ILK FDI PLL is always enabled */
1152         if (dev_priv->info->gen == 5)
1153                 return;
1154
1155         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156         if (HAS_DDI(dev_priv->dev))
1157                 return;
1158
1159         reg = FDI_TX_CTL(pipe);
1160         val = I915_READ(reg);
1161         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162 }
1163
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165                                       enum pipe pipe)
1166 {
1167         int reg;
1168         u32 val;
1169
1170         reg = FDI_RX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176                                   enum pipe pipe)
1177 {
1178         int pp_reg, lvds_reg;
1179         u32 val;
1180         enum pipe panel_pipe = PIPE_A;
1181         bool locked = true;
1182
1183         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184                 pp_reg = PCH_PP_CONTROL;
1185                 lvds_reg = PCH_LVDS;
1186         } else {
1187                 pp_reg = PP_CONTROL;
1188                 lvds_reg = LVDS;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197                 panel_pipe = PIPE_B;
1198
1199         WARN(panel_pipe == pipe && locked,
1200              "panel assertion failure, pipe %c regs locked\n",
1201              pipe_name(pipe));
1202 }
1203
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205                  enum pipe pipe, bool state)
1206 {
1207         int reg;
1208         u32 val;
1209         bool cur_state;
1210         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211                                                                       pipe);
1212
1213         /* if we need the pipe A quirk it must be always on */
1214         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215                 state = true;
1216
1217         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219                 cur_state = false;
1220         } else {
1221                 reg = PIPECONF(cpu_transcoder);
1222                 val = I915_READ(reg);
1223                 cur_state = !!(val & PIPECONF_ENABLE);
1224         }
1225
1226         WARN(cur_state != state,
1227              "pipe %c assertion failure (expected %s, current %s)\n",
1228              pipe_name(pipe), state_string(state), state_string(cur_state));
1229 }
1230
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232                          enum plane plane, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = DSPCNTR(plane);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241         WARN(cur_state != state,
1242              "plane %c assertion failure (expected %s, current %s)\n",
1243              plane_name(plane), state_string(state), state_string(cur_state));
1244 }
1245
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe)
1251 {
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Planes are fixed to pipes on ILK+ */
1257         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN((val & DISPLAY_PLANE_ENABLE),
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for (i = 0; i < 2; i++) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279 {
1280         u32 val;
1281         bool enabled;
1282
1283         if (HAS_PCH_LPT(dev_priv->dev)) {
1284                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285                 return;
1286         }
1287
1288         val = I915_READ(PCH_DREF_CONTROL);
1289         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290                             DREF_SUPERSPREAD_SOURCE_MASK));
1291         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292 }
1293
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                        enum pipe pipe)
1296 {
1297         int reg;
1298         u32 val;
1299         bool enabled;
1300
1301         reg = TRANSCONF(pipe);
1302         val = I915_READ(reg);
1303         enabled = !!(val & TRANS_ENABLE);
1304         WARN(enabled,
1305              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310                             enum pipe pipe, u32 port_sel, u32 val)
1311 {
1312         if ((val & DP_PORT_EN) == 0)
1313                 return false;
1314
1315         if (HAS_PCH_CPT(dev_priv->dev)) {
1316                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & PORT_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv->dev)) {
1334                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335                         return false;
1336         } else {
1337                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & LVDS_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & ADPA_DAC_ENABLE) == 0)
1363                 return false;
1364         if (HAS_PCH_CPT(dev_priv->dev)) {
1365                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366                         return false;
1367         } else {
1368                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369                         return false;
1370         }
1371         return true;
1372 }
1373
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375                                    enum pipe pipe, int reg, u32 port_sel)
1376 {
1377         u32 val = I915_READ(reg);
1378         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380              reg, pipe_name(pipe));
1381
1382         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383              && (val & DP_PIPEB_SELECT),
1384              "IBX PCH dp port still using transcoder B\n");
1385 }
1386
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388                                      enum pipe pipe, int reg)
1389 {
1390         u32 val = I915_READ(reg);
1391         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393              reg, pipe_name(pipe));
1394
1395         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396              && (val & SDVO_PIPE_B_SELECT),
1397              "IBX PCH hdmi port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401                                       enum pipe pipe)
1402 {
1403         int reg;
1404         u32 val;
1405
1406         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1409
1410         reg = PCH_ADPA;
1411         val = I915_READ(reg);
1412         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413              "PCH VGA enabled on transcoder %c, should be disabled\n",
1414              pipe_name(pipe));
1415
1416         reg = PCH_LVDS;
1417         val = I915_READ(reg);
1418         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420              pipe_name(pipe));
1421
1422         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 }
1426
1427 /**
1428  * intel_enable_pll - enable a PLL
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe PLL to enable
1431  *
1432  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1433  * make sure the PLL reg is writable first though, since the panel write
1434  * protect mechanism may be enabled.
1435  *
1436  * Note!  This is for pre-ILK only.
1437  *
1438  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1439  */
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441 {
1442         int reg;
1443         u32 val;
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450                 assert_panel_unlocked(dev_priv, pipe);
1451
1452         reg = DPLL(pipe);
1453         val = I915_READ(reg);
1454         val |= DPLL_VCO_ENABLE;
1455
1456         /* We do this three times for luck */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463         I915_WRITE(reg, val);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469  * intel_disable_pll - disable a PLL
1470  * @dev_priv: i915 private structure
1471  * @pipe: pipe PLL to disable
1472  *
1473  * Disable the PLL for @pipe, making sure the pipe is off first.
1474  *
1475  * Note!  This is for pre-ILK only.
1476  */
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479         int reg;
1480         u32 val;
1481
1482         /* Don't disable pipe A or pipe A PLLs if needed */
1483         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484                 return;
1485
1486         /* Make sure the pipe isn't still relying on us */
1487         assert_pipe_disabled(dev_priv, pipe);
1488
1489         reg = DPLL(pipe);
1490         val = I915_READ(reg);
1491         val &= ~DPLL_VCO_ENABLE;
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494 }
1495
1496 /* SBI access */
1497 static void
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499                 enum intel_sbi_destination destination)
1500 {
1501         u32 tmp;
1502
1503         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1504
1505         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1506                                 100)) {
1507                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1508                 return;
1509         }
1510
1511         I915_WRITE(SBI_ADDR, (reg << 16));
1512         I915_WRITE(SBI_DATA, value);
1513
1514         if (destination == SBI_ICLK)
1515                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516         else
1517                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1519
1520         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1521                                 100)) {
1522                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1523                 return;
1524         }
1525 }
1526
1527 static u32
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529                enum intel_sbi_destination destination)
1530 {
1531         u32 value = 0;
1532         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1533
1534         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1535                                 100)) {
1536                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537                 return 0;
1538         }
1539
1540         I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542         if (destination == SBI_ICLK)
1543                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544         else
1545                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1547
1548         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1549                                 100)) {
1550                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1551                 return 0;
1552         }
1553
1554         return I915_READ(SBI_DATA);
1555 }
1556
1557 /**
1558  * ironlake_enable_pch_pll - enable PCH PLL
1559  * @dev_priv: i915 private structure
1560  * @pipe: pipe PLL to enable
1561  *
1562  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563  * drives the transcoder clock.
1564  */
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH PLLs only available on ILK, SNB and IVB */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         pll = intel_crtc->pch_pll;
1575         if (pll == NULL)
1576                 return;
1577
1578         if (WARN_ON(pll->refcount == 0))
1579                 return;
1580
1581         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582                       pll->pll_reg, pll->active, pll->on,
1583                       intel_crtc->base.base.id);
1584
1585         /* PCH refclock must be enabled first */
1586         assert_pch_refclk_enabled(dev_priv);
1587
1588         if (pll->active++ && pll->on) {
1589                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590                 return;
1591         }
1592
1593         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595         reg = pll->pll_reg;
1596         val = I915_READ(reg);
1597         val |= DPLL_VCO_ENABLE;
1598         I915_WRITE(reg, val);
1599         POSTING_READ(reg);
1600         udelay(200);
1601
1602         pll->on = true;
1603 }
1604
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 {
1607         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609         int reg;
1610         u32 val;
1611
1612         /* PCH only available on ILK+ */
1613         BUG_ON(dev_priv->info->gen < 5);
1614         if (pll == NULL)
1615                return;
1616
1617         if (WARN_ON(pll->refcount == 0))
1618                 return;
1619
1620         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621                       pll->pll_reg, pll->active, pll->on,
1622                       intel_crtc->base.base.id);
1623
1624         if (WARN_ON(pll->active == 0)) {
1625                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         if (--pll->active) {
1630                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631                 return;
1632         }
1633
1634         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636         /* Make sure transcoder isn't still depending on us */
1637         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1638
1639         reg = pll->pll_reg;
1640         val = I915_READ(reg);
1641         val &= ~DPLL_VCO_ENABLE;
1642         I915_WRITE(reg, val);
1643         POSTING_READ(reg);
1644         udelay(200);
1645
1646         pll->on = false;
1647 }
1648
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650                                            enum pipe pipe)
1651 {
1652         struct drm_device *dev = dev_priv->dev;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654         uint32_t reg, val, pipeconf_val;
1655
1656         /* PCH only available on ILK+ */
1657         BUG_ON(dev_priv->info->gen < 5);
1658
1659         /* Make sure PCH DPLL is enabled */
1660         assert_pch_pll_enabled(dev_priv,
1661                                to_intel_crtc(crtc)->pch_pll,
1662                                to_intel_crtc(crtc));
1663
1664         /* FDI must be feeding us bits for PCH ports */
1665         assert_fdi_tx_enabled(dev_priv, pipe);
1666         assert_fdi_rx_enabled(dev_priv, pipe);
1667
1668         if (HAS_PCH_CPT(dev)) {
1669                 /* Workaround: Set the timing override bit before enabling the
1670                  * pch transcoder. */
1671                 reg = TRANS_CHICKEN2(pipe);
1672                 val = I915_READ(reg);
1673                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674                 I915_WRITE(reg, val);
1675         }
1676
1677         reg = TRANSCONF(pipe);
1678         val = I915_READ(reg);
1679         pipeconf_val = I915_READ(PIPECONF(pipe));
1680
1681         if (HAS_PCH_IBX(dev_priv->dev)) {
1682                 /*
1683                  * make the BPC in transcoder be consistent with
1684                  * that in pipeconf reg.
1685                  */
1686                 val &= ~PIPECONF_BPC_MASK;
1687                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1688         }
1689
1690         val &= ~TRANS_INTERLACE_MASK;
1691         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692                 if (HAS_PCH_IBX(dev_priv->dev) &&
1693                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694                         val |= TRANS_LEGACY_INTERLACED_ILK;
1695                 else
1696                         val |= TRANS_INTERLACED;
1697         else
1698                 val |= TRANS_PROGRESSIVE;
1699
1700         I915_WRITE(reg, val | TRANS_ENABLE);
1701         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703 }
1704
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706                                       enum transcoder cpu_transcoder)
1707 {
1708         u32 val, pipeconf_val;
1709
1710         /* PCH only available on ILK+ */
1711         BUG_ON(dev_priv->info->gen < 5);
1712
1713         /* FDI must be feeding us bits for PCH ports */
1714         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1716
1717         /* Workaround: set timing override bit. */
1718         val = I915_READ(_TRANSA_CHICKEN2);
1719         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720         I915_WRITE(_TRANSA_CHICKEN2, val);
1721
1722         val = TRANS_ENABLE;
1723         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1724
1725         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726             PIPECONF_INTERLACED_ILK)
1727                 val |= TRANS_INTERLACED;
1728         else
1729                 val |= TRANS_PROGRESSIVE;
1730
1731         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733                 DRM_ERROR("Failed to enable PCH transcoder\n");
1734 }
1735
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737                                             enum pipe pipe)
1738 {
1739         struct drm_device *dev = dev_priv->dev;
1740         uint32_t reg, val;
1741
1742         /* FDI relies on the transcoder */
1743         assert_fdi_tx_disabled(dev_priv, pipe);
1744         assert_fdi_rx_disabled(dev_priv, pipe);
1745
1746         /* Ports must be off as well */
1747         assert_pch_ports_disabled(dev_priv, pipe);
1748
1749         reg = TRANSCONF(pipe);
1750         val = I915_READ(reg);
1751         val &= ~TRANS_ENABLE;
1752         I915_WRITE(reg, val);
1753         /* wait for PCH transcoder off, transcoder state */
1754         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1756
1757         if (!HAS_PCH_IBX(dev)) {
1758                 /* Workaround: Clear the timing override chicken bit again. */
1759                 reg = TRANS_CHICKEN2(pipe);
1760                 val = I915_READ(reg);
1761                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762                 I915_WRITE(reg, val);
1763         }
1764 }
1765
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1767 {
1768         u32 val;
1769
1770         val = I915_READ(_TRANSACONF);
1771         val &= ~TRANS_ENABLE;
1772         I915_WRITE(_TRANSACONF, val);
1773         /* wait for PCH transcoder off, transcoder state */
1774         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775                 DRM_ERROR("Failed to disable PCH transcoder\n");
1776
1777         /* Workaround: clear timing override bit. */
1778         val = I915_READ(_TRANSA_CHICKEN2);
1779         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780         I915_WRITE(_TRANSA_CHICKEN2, val);
1781 }
1782
1783 /**
1784  * intel_enable_pipe - enable a pipe, asserting requirements
1785  * @dev_priv: i915 private structure
1786  * @pipe: pipe to enable
1787  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1788  *
1789  * Enable @pipe, making sure that various hardware specific requirements
1790  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791  *
1792  * @pipe should be %PIPE_A or %PIPE_B.
1793  *
1794  * Will wait until the pipe is actually running (i.e. first vblank) before
1795  * returning.
1796  */
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798                               bool pch_port)
1799 {
1800         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801                                                                       pipe);
1802         enum pipe pch_transcoder;
1803         int reg;
1804         u32 val;
1805
1806         if (HAS_PCH_LPT(dev_priv->dev))
1807                 pch_transcoder = TRANSCODER_A;
1808         else
1809                 pch_transcoder = pipe;
1810
1811         /*
1812          * A pipe without a PLL won't actually be able to drive bits from
1813          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1814          * need the check.
1815          */
1816         if (!HAS_PCH_SPLIT(dev_priv->dev))
1817                 assert_pll_enabled(dev_priv, pipe);
1818         else {
1819                 if (pch_port) {
1820                         /* if driving the PCH, we need FDI enabled */
1821                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822                         assert_fdi_tx_pll_enabled(dev_priv,
1823                                                   (enum pipe) cpu_transcoder);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2005                                              unsigned int tiling_mode,
2006                                              unsigned int cpp,
2007                                              unsigned int pitch)
2008 {
2009         if (tiling_mode != I915_TILING_NONE) {
2010                 unsigned int tile_rows, tiles;
2011
2012                 tile_rows = *y / 8;
2013                 *y %= 8;
2014
2015                 tiles = *x / (512/cpp);
2016                 *x %= 512/cpp;
2017
2018                 return tile_rows * pitch * 8 + tiles * 4096;
2019         } else {
2020                 unsigned int offset;
2021
2022                 offset = *y * pitch + *x * cpp;
2023                 *y = 0;
2024                 *x = (offset & 4095) / cpp;
2025                 return offset & -4096;
2026         }
2027 }
2028
2029 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2030                              int x, int y)
2031 {
2032         struct drm_device *dev = crtc->dev;
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2035         struct intel_framebuffer *intel_fb;
2036         struct drm_i915_gem_object *obj;
2037         int plane = intel_crtc->plane;
2038         unsigned long linear_offset;
2039         u32 dspcntr;
2040         u32 reg;
2041
2042         switch (plane) {
2043         case 0:
2044         case 1:
2045                 break;
2046         default:
2047                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2048                 return -EINVAL;
2049         }
2050
2051         intel_fb = to_intel_framebuffer(fb);
2052         obj = intel_fb->obj;
2053
2054         reg = DSPCNTR(plane);
2055         dspcntr = I915_READ(reg);
2056         /* Mask out pixel format bits in case we change it */
2057         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2058         switch (fb->pixel_format) {
2059         case DRM_FORMAT_C8:
2060                 dspcntr |= DISPPLANE_8BPP;
2061                 break;
2062         case DRM_FORMAT_XRGB1555:
2063         case DRM_FORMAT_ARGB1555:
2064                 dspcntr |= DISPPLANE_BGRX555;
2065                 break;
2066         case DRM_FORMAT_RGB565:
2067                 dspcntr |= DISPPLANE_BGRX565;
2068                 break;
2069         case DRM_FORMAT_XRGB8888:
2070         case DRM_FORMAT_ARGB8888:
2071                 dspcntr |= DISPPLANE_BGRX888;
2072                 break;
2073         case DRM_FORMAT_XBGR8888:
2074         case DRM_FORMAT_ABGR8888:
2075                 dspcntr |= DISPPLANE_RGBX888;
2076                 break;
2077         case DRM_FORMAT_XRGB2101010:
2078         case DRM_FORMAT_ARGB2101010:
2079                 dspcntr |= DISPPLANE_BGRX101010;
2080                 break;
2081         case DRM_FORMAT_XBGR2101010:
2082         case DRM_FORMAT_ABGR2101010:
2083                 dspcntr |= DISPPLANE_RGBX101010;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2087                 return -EINVAL;
2088         }
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 if (obj->tiling_mode != I915_TILING_NONE)
2092                         dspcntr |= DISPPLANE_TILED;
2093                 else
2094                         dspcntr &= ~DISPPLANE_TILED;
2095         }
2096
2097         I915_WRITE(reg, dspcntr);
2098
2099         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2100
2101         if (INTEL_INFO(dev)->gen >= 4) {
2102                 intel_crtc->dspaddr_offset =
2103                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2104                                                        fb->bits_per_pixel / 8,
2105                                                        fb->pitches[0]);
2106                 linear_offset -= intel_crtc->dspaddr_offset;
2107         } else {
2108                 intel_crtc->dspaddr_offset = linear_offset;
2109         }
2110
2111         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2112                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2113         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2114         if (INTEL_INFO(dev)->gen >= 4) {
2115                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2116                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2117                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2118                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2119         } else
2120                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2121         POSTING_READ(reg);
2122
2123         return 0;
2124 }
2125
2126 static int ironlake_update_plane(struct drm_crtc *crtc,
2127                                  struct drm_framebuffer *fb, int x, int y)
2128 {
2129         struct drm_device *dev = crtc->dev;
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132         struct intel_framebuffer *intel_fb;
2133         struct drm_i915_gem_object *obj;
2134         int plane = intel_crtc->plane;
2135         unsigned long linear_offset;
2136         u32 dspcntr;
2137         u32 reg;
2138
2139         switch (plane) {
2140         case 0:
2141         case 1:
2142         case 2:
2143                 break;
2144         default:
2145                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2146                 return -EINVAL;
2147         }
2148
2149         intel_fb = to_intel_framebuffer(fb);
2150         obj = intel_fb->obj;
2151
2152         reg = DSPCNTR(plane);
2153         dspcntr = I915_READ(reg);
2154         /* Mask out pixel format bits in case we change it */
2155         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2156         switch (fb->pixel_format) {
2157         case DRM_FORMAT_C8:
2158                 dspcntr |= DISPPLANE_8BPP;
2159                 break;
2160         case DRM_FORMAT_RGB565:
2161                 dspcntr |= DISPPLANE_BGRX565;
2162                 break;
2163         case DRM_FORMAT_XRGB8888:
2164         case DRM_FORMAT_ARGB8888:
2165                 dspcntr |= DISPPLANE_BGRX888;
2166                 break;
2167         case DRM_FORMAT_XBGR8888:
2168         case DRM_FORMAT_ABGR8888:
2169                 dspcntr |= DISPPLANE_RGBX888;
2170                 break;
2171         case DRM_FORMAT_XRGB2101010:
2172         case DRM_FORMAT_ARGB2101010:
2173                 dspcntr |= DISPPLANE_BGRX101010;
2174                 break;
2175         case DRM_FORMAT_XBGR2101010:
2176         case DRM_FORMAT_ABGR2101010:
2177                 dspcntr |= DISPPLANE_RGBX101010;
2178                 break;
2179         default:
2180                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2181                 return -EINVAL;
2182         }
2183
2184         if (obj->tiling_mode != I915_TILING_NONE)
2185                 dspcntr |= DISPPLANE_TILED;
2186         else
2187                 dspcntr &= ~DISPPLANE_TILED;
2188
2189         /* must disable */
2190         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2191
2192         I915_WRITE(reg, dspcntr);
2193
2194         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2195         intel_crtc->dspaddr_offset =
2196                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2197                                                fb->bits_per_pixel / 8,
2198                                                fb->pitches[0]);
2199         linear_offset -= intel_crtc->dspaddr_offset;
2200
2201         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2202                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2203         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204         I915_MODIFY_DISPBASE(DSPSURF(plane),
2205                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2206         if (IS_HASWELL(dev)) {
2207                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208         } else {
2209                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211         }
2212         POSTING_READ(reg);
2213
2214         return 0;
2215 }
2216
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2218 static int
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220                            int x, int y, enum mode_set_atomic state)
2221 {
2222         struct drm_device *dev = crtc->dev;
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225         if (dev_priv->display.disable_fbc)
2226                 dev_priv->display.disable_fbc(dev);
2227         intel_increase_pllclock(crtc);
2228
2229         return dev_priv->display.update_plane(crtc, fb, x, y);
2230 }
2231
2232 static int
2233 intel_finish_fb(struct drm_framebuffer *old_fb)
2234 {
2235         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2236         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2237         bool was_interruptible = dev_priv->mm.interruptible;
2238         int ret;
2239
2240         /* Big Hammer, we also need to ensure that any pending
2241          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2242          * current scanout is retired before unpinning the old
2243          * framebuffer.
2244          *
2245          * This should only fail upon a hung GPU, in which case we
2246          * can safely continue.
2247          */
2248         dev_priv->mm.interruptible = false;
2249         ret = i915_gem_object_finish_gpu(obj);
2250         dev_priv->mm.interruptible = was_interruptible;
2251
2252         return ret;
2253 }
2254
2255 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2256 {
2257         struct drm_device *dev = crtc->dev;
2258         struct drm_i915_master_private *master_priv;
2259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260
2261         if (!dev->primary->master)
2262                 return;
2263
2264         master_priv = dev->primary->master->driver_priv;
2265         if (!master_priv->sarea_priv)
2266                 return;
2267
2268         switch (intel_crtc->pipe) {
2269         case 0:
2270                 master_priv->sarea_priv->pipeA_x = x;
2271                 master_priv->sarea_priv->pipeA_y = y;
2272                 break;
2273         case 1:
2274                 master_priv->sarea_priv->pipeB_x = x;
2275                 master_priv->sarea_priv->pipeB_y = y;
2276                 break;
2277         default:
2278                 break;
2279         }
2280 }
2281
2282 static int
2283 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2284                     struct drm_framebuffer *fb)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         struct drm_framebuffer *old_fb;
2290         int ret;
2291
2292         /* no fb bound */
2293         if (!fb) {
2294                 DRM_ERROR("No FB bound\n");
2295                 return 0;
2296         }
2297
2298         if(intel_crtc->plane > dev_priv->num_pipe) {
2299                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2300                                 intel_crtc->plane,
2301                                 dev_priv->num_pipe);
2302                 return -EINVAL;
2303         }
2304
2305         mutex_lock(&dev->struct_mutex);
2306         ret = intel_pin_and_fence_fb_obj(dev,
2307                                          to_intel_framebuffer(fb)->obj,
2308                                          NULL);
2309         if (ret != 0) {
2310                 mutex_unlock(&dev->struct_mutex);
2311                 DRM_ERROR("pin & fence failed\n");
2312                 return ret;
2313         }
2314
2315         if (crtc->fb)
2316                 intel_finish_fb(crtc->fb);
2317
2318         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2319         if (ret) {
2320                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("failed to update base address\n");
2323                 return ret;
2324         }
2325
2326         old_fb = crtc->fb;
2327         crtc->fb = fb;
2328         crtc->x = x;
2329         crtc->y = y;
2330
2331         if (old_fb) {
2332                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2333                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2334         }
2335
2336         intel_update_fbc(dev);
2337         mutex_unlock(&dev->struct_mutex);
2338
2339         intel_crtc_update_sarea_pos(crtc, x, y);
2340
2341         return 0;
2342 }
2343
2344 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2345 {
2346         struct drm_device *dev = crtc->dev;
2347         struct drm_i915_private *dev_priv = dev->dev_private;
2348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2349         int pipe = intel_crtc->pipe;
2350         u32 reg, temp;
2351
2352         /* enable normal train */
2353         reg = FDI_TX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (IS_IVYBRIDGE(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2357                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2361         }
2362         I915_WRITE(reg, temp);
2363
2364         reg = FDI_RX_CTL(pipe);
2365         temp = I915_READ(reg);
2366         if (HAS_PCH_CPT(dev)) {
2367                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2368                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2369         } else {
2370                 temp &= ~FDI_LINK_TRAIN_NONE;
2371                 temp |= FDI_LINK_TRAIN_NONE;
2372         }
2373         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2374
2375         /* wait one idle pattern time */
2376         POSTING_READ(reg);
2377         udelay(1000);
2378
2379         /* IVB wants error correction enabled */
2380         if (IS_IVYBRIDGE(dev))
2381                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2382                            FDI_FE_ERRC_ENABLE);
2383 }
2384
2385 static void ivb_modeset_global_resources(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct intel_crtc *pipe_B_crtc =
2389                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2390         struct intel_crtc *pipe_C_crtc =
2391                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2392         uint32_t temp;
2393
2394         /* When everything is off disable fdi C so that we could enable fdi B
2395          * with all lanes. XXX: This misses the case where a pipe is not using
2396          * any pch resources and so doesn't need any fdi lanes. */
2397         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2398                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2399                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2400
2401                 temp = I915_READ(SOUTH_CHICKEN1);
2402                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2403                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2404                 I915_WRITE(SOUTH_CHICKEN1, temp);
2405         }
2406 }
2407
2408 /* The FDI link training functions for ILK/Ibexpeak. */
2409 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2410 {
2411         struct drm_device *dev = crtc->dev;
2412         struct drm_i915_private *dev_priv = dev->dev_private;
2413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414         int pipe = intel_crtc->pipe;
2415         int plane = intel_crtc->plane;
2416         u32 reg, temp, tries;
2417
2418         /* FDI needs bits from pipe & plane first */
2419         assert_pipe_enabled(dev_priv, pipe);
2420         assert_plane_enabled(dev_priv, plane);
2421
2422         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2423            for train result */
2424         reg = FDI_RX_IMR(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_RX_SYMBOL_LOCK;
2427         temp &= ~FDI_RX_BIT_LOCK;
2428         I915_WRITE(reg, temp);
2429         I915_READ(reg);
2430         udelay(150);
2431
2432         /* enable CPU FDI TX and PCH FDI RX */
2433         reg = FDI_TX_CTL(pipe);
2434         temp = I915_READ(reg);
2435         temp &= ~(7 << 19);
2436         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2437         temp &= ~FDI_LINK_TRAIN_NONE;
2438         temp |= FDI_LINK_TRAIN_PATTERN_1;
2439         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_LINK_TRAIN_NONE;
2444         temp |= FDI_LINK_TRAIN_PATTERN_1;
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         /* Ironlake workaround, enable clock pointer after FDI enable*/
2451         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2452         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2453                    FDI_RX_PHASE_SYNC_POINTER_EN);
2454
2455         reg = FDI_RX_IIR(pipe);
2456         for (tries = 0; tries < 5; tries++) {
2457                 temp = I915_READ(reg);
2458                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460                 if ((temp & FDI_RX_BIT_LOCK)) {
2461                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2462                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2463                         break;
2464                 }
2465         }
2466         if (tries == 5)
2467                 DRM_ERROR("FDI train 1 fail!\n");
2468
2469         /* Train 2 */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_LINK_TRAIN_NONE;
2473         temp |= FDI_LINK_TRAIN_PATTERN_2;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_NONE;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         reg = FDI_RX_IIR(pipe);
2486         for (tries = 0; tries < 5; tries++) {
2487                 temp = I915_READ(reg);
2488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490                 if (temp & FDI_RX_SYMBOL_LOCK) {
2491                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2492                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2493                         break;
2494                 }
2495         }
2496         if (tries == 5)
2497                 DRM_ERROR("FDI train 2 fail!\n");
2498
2499         DRM_DEBUG_KMS("FDI train done\n");
2500
2501 }
2502
2503 static const int snb_b_fdi_train_param[] = {
2504         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 };
2509
2510 /* The FDI link training functions for SNB/Cougarpoint. */
2511 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp, i, retry;
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         /* enable CPU FDI TX and PCH FDI RX */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         temp &= ~(7 << 19);
2534         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538         /* SNB-B */
2539         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         I915_WRITE(FDI_RX_MISC(pipe),
2543                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
2545         reg = FDI_RX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         if (HAS_PCH_CPT(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550         } else {
2551                 temp &= ~FDI_LINK_TRAIN_NONE;
2552                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553         }
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         for (i = 0; i < 4; i++) {
2560                 reg = FDI_TX_CTL(pipe);
2561                 temp = I915_READ(reg);
2562                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563                 temp |= snb_b_fdi_train_param[i];
2564                 I915_WRITE(reg, temp);
2565
2566                 POSTING_READ(reg);
2567                 udelay(500);
2568
2569                 for (retry = 0; retry < 5; retry++) {
2570                         reg = FDI_RX_IIR(pipe);
2571                         temp = I915_READ(reg);
2572                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2573                         if (temp & FDI_RX_BIT_LOCK) {
2574                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2575                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2576                                 break;
2577                         }
2578                         udelay(50);
2579                 }
2580                 if (retry < 5)
2581                         break;
2582         }
2583         if (i == 4)
2584                 DRM_ERROR("FDI train 1 fail!\n");
2585
2586         /* Train 2 */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_2;
2591         if (IS_GEN6(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2593                 /* SNB-B */
2594                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595         }
2596         I915_WRITE(reg, temp);
2597
2598         reg = FDI_RX_CTL(pipe);
2599         temp = I915_READ(reg);
2600         if (HAS_PCH_CPT(dev)) {
2601                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2602                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2603         } else {
2604                 temp &= ~FDI_LINK_TRAIN_NONE;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2606         }
2607         I915_WRITE(reg, temp);
2608
2609         POSTING_READ(reg);
2610         udelay(150);
2611
2612         for (i = 0; i < 4; i++) {
2613                 reg = FDI_TX_CTL(pipe);
2614                 temp = I915_READ(reg);
2615                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616                 temp |= snb_b_fdi_train_param[i];
2617                 I915_WRITE(reg, temp);
2618
2619                 POSTING_READ(reg);
2620                 udelay(500);
2621
2622                 for (retry = 0; retry < 5; retry++) {
2623                         reg = FDI_RX_IIR(pipe);
2624                         temp = I915_READ(reg);
2625                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626                         if (temp & FDI_RX_SYMBOL_LOCK) {
2627                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2628                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2629                                 break;
2630                         }
2631                         udelay(50);
2632                 }
2633                 if (retry < 5)
2634                         break;
2635         }
2636         if (i == 4)
2637                 DRM_ERROR("FDI train 2 fail!\n");
2638
2639         DRM_DEBUG_KMS("FDI train done.\n");
2640 }
2641
2642 /* Manual link training for Ivy Bridge A0 parts */
2643 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2644 {
2645         struct drm_device *dev = crtc->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         int pipe = intel_crtc->pipe;
2649         u32 reg, temp, i;
2650
2651         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2652            for train result */
2653         reg = FDI_RX_IMR(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_RX_SYMBOL_LOCK;
2656         temp &= ~FDI_RX_BIT_LOCK;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2663                       I915_READ(FDI_RX_IIR(pipe)));
2664
2665         /* enable CPU FDI TX and PCH FDI RX */
2666         reg = FDI_TX_CTL(pipe);
2667         temp = I915_READ(reg);
2668         temp &= ~(7 << 19);
2669         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2670         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2671         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2672         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674         temp |= FDI_COMPOSITE_SYNC;
2675         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2676
2677         I915_WRITE(FDI_RX_MISC(pipe),
2678                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2679
2680         reg = FDI_RX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         temp &= ~FDI_LINK_TRAIN_AUTO;
2683         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2685         temp |= FDI_COMPOSITE_SYNC;
2686         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2687
2688         POSTING_READ(reg);
2689         udelay(150);
2690
2691         for (i = 0; i < 4; i++) {
2692                 reg = FDI_TX_CTL(pipe);
2693                 temp = I915_READ(reg);
2694                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2695                 temp |= snb_b_fdi_train_param[i];
2696                 I915_WRITE(reg, temp);
2697
2698                 POSTING_READ(reg);
2699                 udelay(500);
2700
2701                 reg = FDI_RX_IIR(pipe);
2702                 temp = I915_READ(reg);
2703                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704
2705                 if (temp & FDI_RX_BIT_LOCK ||
2706                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2707                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2708                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2709                         break;
2710                 }
2711         }
2712         if (i == 4)
2713                 DRM_ERROR("FDI train 1 fail!\n");
2714
2715         /* Train 2 */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2719         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2720         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2721         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2722         I915_WRITE(reg, temp);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2728         I915_WRITE(reg, temp);
2729
2730         POSTING_READ(reg);
2731         udelay(150);
2732
2733         for (i = 0; i < 4; i++) {
2734                 reg = FDI_TX_CTL(pipe);
2735                 temp = I915_READ(reg);
2736                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2737                 temp |= snb_b_fdi_train_param[i];
2738                 I915_WRITE(reg, temp);
2739
2740                 POSTING_READ(reg);
2741                 udelay(500);
2742
2743                 reg = FDI_RX_IIR(pipe);
2744                 temp = I915_READ(reg);
2745                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2746
2747                 if (temp & FDI_RX_SYMBOL_LOCK) {
2748                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2749                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2750                         break;
2751                 }
2752         }
2753         if (i == 4)
2754                 DRM_ERROR("FDI train 2 fail!\n");
2755
2756         DRM_DEBUG_KMS("FDI train done.\n");
2757 }
2758
2759 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2760 {
2761         struct drm_device *dev = intel_crtc->base.dev;
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763         int pipe = intel_crtc->pipe;
2764         u32 reg, temp;
2765
2766
2767         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         temp &= ~((0x7 << 19) | (0x7 << 16));
2771         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2772         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2773         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2774
2775         POSTING_READ(reg);
2776         udelay(200);
2777
2778         /* Switch from Rawclk to PCDclk */
2779         temp = I915_READ(reg);
2780         I915_WRITE(reg, temp | FDI_PCDCLK);
2781
2782         POSTING_READ(reg);
2783         udelay(200);
2784
2785         /* Enable CPU FDI TX PLL, always on for Ironlake */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2789                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2790
2791                 POSTING_READ(reg);
2792                 udelay(100);
2793         }
2794 }
2795
2796 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2797 {
2798         struct drm_device *dev = intel_crtc->base.dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         int pipe = intel_crtc->pipe;
2801         u32 reg, temp;
2802
2803         /* Switch from PCDclk to Rawclk */
2804         reg = FDI_RX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2807
2808         /* Disable CPU FDI TX PLL */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2812
2813         POSTING_READ(reg);
2814         udelay(100);
2815
2816         reg = FDI_RX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2819
2820         /* Wait for the clocks to turn off. */
2821         POSTING_READ(reg);
2822         udelay(100);
2823 }
2824
2825 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2826 {
2827         struct drm_device *dev = crtc->dev;
2828         struct drm_i915_private *dev_priv = dev->dev_private;
2829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830         int pipe = intel_crtc->pipe;
2831         u32 reg, temp;
2832
2833         /* disable CPU FDI tx and PCH FDI rx */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2837         POSTING_READ(reg);
2838
2839         reg = FDI_RX_CTL(pipe);
2840         temp = I915_READ(reg);
2841         temp &= ~(0x7 << 16);
2842         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2843         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2844
2845         POSTING_READ(reg);
2846         udelay(100);
2847
2848         /* Ironlake workaround, disable clock pointer after downing FDI */
2849         if (HAS_PCH_IBX(dev)) {
2850                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2851         }
2852
2853         /* still set train pattern 1 */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         temp &= ~FDI_LINK_TRAIN_NONE;
2857         temp |= FDI_LINK_TRAIN_PATTERN_1;
2858         I915_WRITE(reg, temp);
2859
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         if (HAS_PCH_CPT(dev)) {
2863                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2864                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2865         } else {
2866                 temp &= ~FDI_LINK_TRAIN_NONE;
2867                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2868         }
2869         /* BPC in FDI rx is consistent with that in PIPECONF */
2870         temp &= ~(0x07 << 16);
2871         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2872         I915_WRITE(reg, temp);
2873
2874         POSTING_READ(reg);
2875         udelay(100);
2876 }
2877
2878 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2879 {
2880         struct drm_device *dev = crtc->dev;
2881         struct drm_i915_private *dev_priv = dev->dev_private;
2882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2883         unsigned long flags;
2884         bool pending;
2885
2886         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2887             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2888                 return false;
2889
2890         spin_lock_irqsave(&dev->event_lock, flags);
2891         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2892         spin_unlock_irqrestore(&dev->event_lock, flags);
2893
2894         return pending;
2895 }
2896
2897 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2898 {
2899         struct drm_device *dev = crtc->dev;
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901
2902         if (crtc->fb == NULL)
2903                 return;
2904
2905         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2906
2907         wait_event(dev_priv->pending_flip_queue,
2908                    !intel_crtc_has_pending_flip(crtc));
2909
2910         mutex_lock(&dev->struct_mutex);
2911         intel_finish_fb(crtc->fb);
2912         mutex_unlock(&dev->struct_mutex);
2913 }
2914
2915 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2916 {
2917         struct drm_device *dev = crtc->dev;
2918         struct intel_encoder *intel_encoder;
2919
2920         /*
2921          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2922          * must be driven by its own crtc; no sharing is possible.
2923          */
2924         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2925                 switch (intel_encoder->type) {
2926                 case INTEL_OUTPUT_EDP:
2927                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2928                                 return false;
2929                         continue;
2930                 }
2931         }
2932
2933         return true;
2934 }
2935
2936 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2937 {
2938         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2939 }
2940
2941 /* Program iCLKIP clock to the desired frequency */
2942 static void lpt_program_iclkip(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2947         u32 temp;
2948
2949         mutex_lock(&dev_priv->dpio_lock);
2950
2951         /* It is necessary to ungate the pixclk gate prior to programming
2952          * the divisors, and gate it back when it is done.
2953          */
2954         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2955
2956         /* Disable SSCCTL */
2957         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2958                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2959                                 SBI_SSCCTL_DISABLE,
2960                         SBI_ICLK);
2961
2962         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2963         if (crtc->mode.clock == 20000) {
2964                 auxdiv = 1;
2965                 divsel = 0x41;
2966                 phaseinc = 0x20;
2967         } else {
2968                 /* The iCLK virtual clock root frequency is in MHz,
2969                  * but the crtc->mode.clock in in KHz. To get the divisors,
2970                  * it is necessary to divide one by another, so we
2971                  * convert the virtual clock precision to KHz here for higher
2972                  * precision.
2973                  */
2974                 u32 iclk_virtual_root_freq = 172800 * 1000;
2975                 u32 iclk_pi_range = 64;
2976                 u32 desired_divisor, msb_divisor_value, pi_value;
2977
2978                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2979                 msb_divisor_value = desired_divisor / iclk_pi_range;
2980                 pi_value = desired_divisor % iclk_pi_range;
2981
2982                 auxdiv = 0;
2983                 divsel = msb_divisor_value - 2;
2984                 phaseinc = pi_value;
2985         }
2986
2987         /* This should not happen with any sane values */
2988         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2989                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2990         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2991                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2992
2993         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2994                         crtc->mode.clock,
2995                         auxdiv,
2996                         divsel,
2997                         phasedir,
2998                         phaseinc);
2999
3000         /* Program SSCDIVINTPHASE6 */
3001         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3002         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3003         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3004         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3005         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3006         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3007         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3008         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3009
3010         /* Program SSCAUXDIV */
3011         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3012         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3013         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3014         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3015
3016         /* Enable modulator and associated divider */
3017         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3018         temp &= ~SBI_SSCCTL_DISABLE;
3019         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3020
3021         /* Wait for initialization time */
3022         udelay(24);
3023
3024         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3025
3026         mutex_unlock(&dev_priv->dpio_lock);
3027 }
3028
3029 /*
3030  * Enable PCH resources required for PCH ports:
3031  *   - PCH PLLs
3032  *   - FDI training & RX/TX
3033  *   - update transcoder timings
3034  *   - DP transcoding bits
3035  *   - transcoder
3036  */
3037 static void ironlake_pch_enable(struct drm_crtc *crtc)
3038 {
3039         struct drm_device *dev = crtc->dev;
3040         struct drm_i915_private *dev_priv = dev->dev_private;
3041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042         int pipe = intel_crtc->pipe;
3043         u32 reg, temp;
3044
3045         assert_transcoder_disabled(dev_priv, pipe);
3046
3047         /* Write the TU size bits before fdi link training, so that error
3048          * detection works. */
3049         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3050                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3051
3052         /* For PCH output, training FDI link */
3053         dev_priv->display.fdi_link_train(crtc);
3054
3055         /* XXX: pch pll's can be enabled any time before we enable the PCH
3056          * transcoder, and we actually should do this to not upset any PCH
3057          * transcoder that already use the clock when we share it.
3058          *
3059          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3060          * unconditionally resets the pll - we need that to have the right LVDS
3061          * enable sequence. */
3062         ironlake_enable_pch_pll(intel_crtc);
3063
3064         if (HAS_PCH_CPT(dev)) {
3065                 u32 sel;
3066
3067                 temp = I915_READ(PCH_DPLL_SEL);
3068                 switch (pipe) {
3069                 default:
3070                 case 0:
3071                         temp |= TRANSA_DPLL_ENABLE;
3072                         sel = TRANSA_DPLLB_SEL;
3073                         break;
3074                 case 1:
3075                         temp |= TRANSB_DPLL_ENABLE;
3076                         sel = TRANSB_DPLLB_SEL;
3077                         break;
3078                 case 2:
3079                         temp |= TRANSC_DPLL_ENABLE;
3080                         sel = TRANSC_DPLLB_SEL;
3081                         break;
3082                 }
3083                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3084                         temp |= sel;
3085                 else
3086                         temp &= ~sel;
3087                 I915_WRITE(PCH_DPLL_SEL, temp);
3088         }
3089
3090         /* set transcoder timing, panel must allow it */
3091         assert_panel_unlocked(dev_priv, pipe);
3092         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3093         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3094         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3095
3096         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3097         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3098         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3099         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3100
3101         intel_fdi_normal_train(crtc);
3102
3103         /* For PCH DP, enable TRANS_DP_CTL */
3104         if (HAS_PCH_CPT(dev) &&
3105             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3106              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3107                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3108                 reg = TRANS_DP_CTL(pipe);
3109                 temp = I915_READ(reg);
3110                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3111                           TRANS_DP_SYNC_MASK |
3112                           TRANS_DP_BPC_MASK);
3113                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3114                          TRANS_DP_ENH_FRAMING);
3115                 temp |= bpc << 9; /* same format but at 11:9 */
3116
3117                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3118                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3119                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3120                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3121
3122                 switch (intel_trans_dp_port_sel(crtc)) {
3123                 case PCH_DP_B:
3124                         temp |= TRANS_DP_PORT_SEL_B;
3125                         break;
3126                 case PCH_DP_C:
3127                         temp |= TRANS_DP_PORT_SEL_C;
3128                         break;
3129                 case PCH_DP_D:
3130                         temp |= TRANS_DP_PORT_SEL_D;
3131                         break;
3132                 default:
3133                         BUG();
3134                 }
3135
3136                 I915_WRITE(reg, temp);
3137         }
3138
3139         ironlake_enable_pch_transcoder(dev_priv, pipe);
3140 }
3141
3142 static void lpt_pch_enable(struct drm_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3147         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3148
3149         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3150
3151         lpt_program_iclkip(crtc);
3152
3153         /* Set transcoder timing. */
3154         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3155         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3156         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3157
3158         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3159         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3160         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3161         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3162
3163         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3164 }
3165
3166 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3167 {
3168         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3169
3170         if (pll == NULL)
3171                 return;
3172
3173         if (pll->refcount == 0) {
3174                 WARN(1, "bad PCH PLL refcount\n");
3175                 return;
3176         }
3177
3178         --pll->refcount;
3179         intel_crtc->pch_pll = NULL;
3180 }
3181
3182 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3183 {
3184         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3185         struct intel_pch_pll *pll;
3186         int i;
3187
3188         pll = intel_crtc->pch_pll;
3189         if (pll) {
3190                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3191                               intel_crtc->base.base.id, pll->pll_reg);
3192                 goto prepare;
3193         }
3194
3195         if (HAS_PCH_IBX(dev_priv->dev)) {
3196                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3197                 i = intel_crtc->pipe;
3198                 pll = &dev_priv->pch_plls[i];
3199
3200                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3201                               intel_crtc->base.base.id, pll->pll_reg);
3202
3203                 goto found;
3204         }
3205
3206         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3207                 pll = &dev_priv->pch_plls[i];
3208
3209                 /* Only want to check enabled timings first */
3210                 if (pll->refcount == 0)
3211                         continue;
3212
3213                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3214                     fp == I915_READ(pll->fp0_reg)) {
3215                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3216                                       intel_crtc->base.base.id,
3217                                       pll->pll_reg, pll->refcount, pll->active);
3218
3219                         goto found;
3220                 }
3221         }
3222
3223         /* Ok no matching timings, maybe there's a free one? */
3224         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3225                 pll = &dev_priv->pch_plls[i];
3226                 if (pll->refcount == 0) {
3227                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3228                                       intel_crtc->base.base.id, pll->pll_reg);
3229                         goto found;
3230                 }
3231         }
3232
3233         return NULL;
3234
3235 found:
3236         intel_crtc->pch_pll = pll;
3237         pll->refcount++;
3238         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3239 prepare: /* separate function? */
3240         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3241
3242         /* Wait for the clocks to stabilize before rewriting the regs */
3243         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3244         POSTING_READ(pll->pll_reg);
3245         udelay(150);
3246
3247         I915_WRITE(pll->fp0_reg, fp);
3248         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3249         pll->on = false;
3250         return pll;
3251 }
3252
3253 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3254 {
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         int dslreg = PIPEDSL(pipe);
3257         u32 temp;
3258
3259         temp = I915_READ(dslreg);
3260         udelay(500);
3261         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3262                 if (wait_for(I915_READ(dslreg) != temp, 5))
3263                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3264         }
3265 }
3266
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3268 {
3269         struct drm_device *dev = crtc->dev;
3270         struct drm_i915_private *dev_priv = dev->dev_private;
3271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272         struct intel_encoder *encoder;
3273         int pipe = intel_crtc->pipe;
3274         int plane = intel_crtc->plane;
3275         u32 temp;
3276         bool is_pch_port;
3277
3278         WARN_ON(!crtc->enabled);
3279
3280         if (intel_crtc->active)
3281                 return;
3282
3283         intel_crtc->active = true;
3284         intel_update_watermarks(dev);
3285
3286         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3287                 temp = I915_READ(PCH_LVDS);
3288                 if ((temp & LVDS_PORT_EN) == 0)
3289                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3290         }
3291
3292         is_pch_port = ironlake_crtc_driving_pch(crtc);
3293
3294         if (is_pch_port) {
3295                 /* Note: FDI PLL enabling _must_ be done before we enable the
3296                  * cpu pipes, hence this is separate from all the other fdi/pch
3297                  * enabling. */
3298                 ironlake_fdi_pll_enable(intel_crtc);
3299         } else {
3300                 assert_fdi_tx_disabled(dev_priv, pipe);
3301                 assert_fdi_rx_disabled(dev_priv, pipe);
3302         }
3303
3304         for_each_encoder_on_crtc(dev, crtc, encoder)
3305                 if (encoder->pre_enable)
3306                         encoder->pre_enable(encoder);
3307
3308         /* Enable panel fitting for LVDS */
3309         if (dev_priv->pch_pf_size &&
3310             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3311              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3312                 /* Force use of hard-coded filter coefficients
3313                  * as some pre-programmed values are broken,
3314                  * e.g. x201.
3315                  */
3316                 if (IS_IVYBRIDGE(dev))
3317                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3318                                                  PF_PIPE_SEL_IVB(pipe));
3319                 else
3320                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3321                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3322                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3323         }
3324
3325         /*
3326          * On ILK+ LUT must be loaded before the pipe is running but with
3327          * clocks enabled
3328          */
3329         intel_crtc_load_lut(crtc);
3330
3331         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333
3334         if (is_pch_port)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         intel_crtc_update_cursor(crtc, true);
3342
3343         for_each_encoder_on_crtc(dev, crtc, encoder)
3344                 encoder->enable(encoder);
3345
3346         if (HAS_PCH_CPT(dev))
3347                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3348
3349         /*
3350          * There seems to be a race in PCH platform hw (at least on some
3351          * outputs) where an enabled pipe still completes any pageflip right
3352          * away (as if the pipe is off) instead of waiting for vblank. As soon
3353          * as the first vblank happend, everything works as expected. Hence just
3354          * wait for one vblank before returning to avoid strange things
3355          * happening.
3356          */
3357         intel_wait_for_vblank(dev, intel_crtc->pipe);
3358 }
3359
3360 static void haswell_crtc_enable(struct drm_crtc *crtc)
3361 {
3362         struct drm_device *dev = crtc->dev;
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         struct intel_encoder *encoder;
3366         int pipe = intel_crtc->pipe;
3367         int plane = intel_crtc->plane;
3368         bool is_pch_port;
3369
3370         WARN_ON(!crtc->enabled);
3371
3372         if (intel_crtc->active)
3373                 return;
3374
3375         intel_crtc->active = true;
3376         intel_update_watermarks(dev);
3377
3378         is_pch_port = haswell_crtc_driving_pch(crtc);
3379
3380         if (is_pch_port)
3381                 dev_priv->display.fdi_link_train(crtc);
3382
3383         for_each_encoder_on_crtc(dev, crtc, encoder)
3384                 if (encoder->pre_enable)
3385                         encoder->pre_enable(encoder);
3386
3387         intel_ddi_enable_pipe_clock(intel_crtc);
3388
3389         /* Enable panel fitting for eDP */
3390         if (dev_priv->pch_pf_size &&
3391             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3392                 /* Force use of hard-coded filter coefficients
3393                  * as some pre-programmed values are broken,
3394                  * e.g. x201.
3395                  */
3396                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3397                                          PF_PIPE_SEL_IVB(pipe));
3398                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3400         }
3401
3402         /*
3403          * On ILK+ LUT must be loaded before the pipe is running but with
3404          * clocks enabled
3405          */
3406         intel_crtc_load_lut(crtc);
3407
3408         intel_ddi_set_pipe_settings(crtc);
3409         intel_ddi_enable_pipe_func(crtc);
3410
3411         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3412         intel_enable_plane(dev_priv, plane, pipe);
3413
3414         if (is_pch_port)
3415                 lpt_pch_enable(crtc);
3416
3417         mutex_lock(&dev->struct_mutex);
3418         intel_update_fbc(dev);
3419         mutex_unlock(&dev->struct_mutex);
3420
3421         intel_crtc_update_cursor(crtc, true);
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 encoder->enable(encoder);
3425
3426         /*
3427          * There seems to be a race in PCH platform hw (at least on some
3428          * outputs) where an enabled pipe still completes any pageflip right
3429          * away (as if the pipe is off) instead of waiting for vblank. As soon
3430          * as the first vblank happend, everything works as expected. Hence just
3431          * wait for one vblank before returning to avoid strange things
3432          * happening.
3433          */
3434         intel_wait_for_vblank(dev, intel_crtc->pipe);
3435 }
3436
3437 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         struct intel_encoder *encoder;
3443         int pipe = intel_crtc->pipe;
3444         int plane = intel_crtc->plane;
3445         u32 reg, temp;
3446
3447
3448         if (!intel_crtc->active)
3449                 return;
3450
3451         for_each_encoder_on_crtc(dev, crtc, encoder)
3452                 encoder->disable(encoder);
3453
3454         intel_crtc_wait_for_pending_flips(crtc);
3455         drm_vblank_off(dev, pipe);
3456         intel_crtc_update_cursor(crtc, false);
3457
3458         intel_disable_plane(dev_priv, plane, pipe);
3459
3460         if (dev_priv->cfb_plane == plane)
3461                 intel_disable_fbc(dev);
3462
3463         intel_disable_pipe(dev_priv, pipe);
3464
3465         /* Disable PF */
3466         I915_WRITE(PF_CTL(pipe), 0);
3467         I915_WRITE(PF_WIN_SZ(pipe), 0);
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 if (encoder->post_disable)
3471                         encoder->post_disable(encoder);
3472
3473         ironlake_fdi_disable(crtc);
3474
3475         ironlake_disable_pch_transcoder(dev_priv, pipe);
3476
3477         if (HAS_PCH_CPT(dev)) {
3478                 /* disable TRANS_DP_CTL */
3479                 reg = TRANS_DP_CTL(pipe);
3480                 temp = I915_READ(reg);
3481                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3482                 temp |= TRANS_DP_PORT_SEL_NONE;
3483                 I915_WRITE(reg, temp);
3484
3485                 /* disable DPLL_SEL */
3486                 temp = I915_READ(PCH_DPLL_SEL);
3487                 switch (pipe) {
3488                 case 0:
3489                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3490                         break;
3491                 case 1:
3492                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3493                         break;
3494                 case 2:
3495                         /* C shares PLL A or B */
3496                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3497                         break;
3498                 default:
3499                         BUG(); /* wtf */
3500                 }
3501                 I915_WRITE(PCH_DPLL_SEL, temp);
3502         }
3503
3504         /* disable PCH DPLL */
3505         intel_disable_pch_pll(intel_crtc);
3506
3507         ironlake_fdi_pll_disable(intel_crtc);
3508
3509         intel_crtc->active = false;
3510         intel_update_watermarks(dev);
3511
3512         mutex_lock(&dev->struct_mutex);
3513         intel_update_fbc(dev);
3514         mutex_unlock(&dev->struct_mutex);
3515 }
3516
3517 static void haswell_crtc_disable(struct drm_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         struct intel_encoder *encoder;
3523         int pipe = intel_crtc->pipe;
3524         int plane = intel_crtc->plane;
3525         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3526         bool is_pch_port;
3527
3528         if (!intel_crtc->active)
3529                 return;
3530
3531         is_pch_port = haswell_crtc_driving_pch(crtc);
3532
3533         for_each_encoder_on_crtc(dev, crtc, encoder)
3534                 encoder->disable(encoder);
3535
3536         intel_crtc_wait_for_pending_flips(crtc);
3537         drm_vblank_off(dev, pipe);
3538         intel_crtc_update_cursor(crtc, false);
3539
3540         intel_disable_plane(dev_priv, plane, pipe);
3541
3542         if (dev_priv->cfb_plane == plane)
3543                 intel_disable_fbc(dev);
3544
3545         intel_disable_pipe(dev_priv, pipe);
3546
3547         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3548
3549         /* Disable PF */
3550         I915_WRITE(PF_CTL(pipe), 0);
3551         I915_WRITE(PF_WIN_SZ(pipe), 0);
3552
3553         intel_ddi_disable_pipe_clock(intel_crtc);
3554
3555         for_each_encoder_on_crtc(dev, crtc, encoder)
3556                 if (encoder->post_disable)
3557                         encoder->post_disable(encoder);
3558
3559         if (is_pch_port) {
3560                 lpt_disable_pch_transcoder(dev_priv);
3561                 intel_ddi_fdi_disable(crtc);
3562         }
3563
3564         intel_crtc->active = false;
3565         intel_update_watermarks(dev);
3566
3567         mutex_lock(&dev->struct_mutex);
3568         intel_update_fbc(dev);
3569         mutex_unlock(&dev->struct_mutex);
3570 }
3571
3572 static void ironlake_crtc_off(struct drm_crtc *crtc)
3573 {
3574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575         intel_put_pch_pll(intel_crtc);
3576 }
3577
3578 static void haswell_crtc_off(struct drm_crtc *crtc)
3579 {
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581
3582         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3583          * start using it. */
3584         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3585
3586         intel_ddi_put_crtc_pll(crtc);
3587 }
3588
3589 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3590 {
3591         if (!enable && intel_crtc->overlay) {
3592                 struct drm_device *dev = intel_crtc->base.dev;
3593                 struct drm_i915_private *dev_priv = dev->dev_private;
3594
3595                 mutex_lock(&dev->struct_mutex);
3596                 dev_priv->mm.interruptible = false;
3597                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3598                 dev_priv->mm.interruptible = true;
3599                 mutex_unlock(&dev->struct_mutex);
3600         }
3601
3602         /* Let userspace switch the overlay on again. In most cases userspace
3603          * has to recompute where to put it anyway.
3604          */
3605 }
3606
3607 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3608 {
3609         struct drm_device *dev = crtc->dev;
3610         struct drm_i915_private *dev_priv = dev->dev_private;
3611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612         struct intel_encoder *encoder;
3613         int pipe = intel_crtc->pipe;
3614         int plane = intel_crtc->plane;
3615
3616         WARN_ON(!crtc->enabled);
3617
3618         if (intel_crtc->active)
3619                 return;
3620
3621         intel_crtc->active = true;
3622         intel_update_watermarks(dev);
3623
3624         intel_enable_pll(dev_priv, pipe);
3625
3626         for_each_encoder_on_crtc(dev, crtc, encoder)
3627                 if (encoder->pre_enable)
3628                         encoder->pre_enable(encoder);
3629
3630         intel_enable_pipe(dev_priv, pipe, false);
3631         intel_enable_plane(dev_priv, plane, pipe);
3632
3633         intel_crtc_load_lut(crtc);
3634         intel_update_fbc(dev);
3635
3636         /* Give the overlay scaler a chance to enable if it's on this pipe */
3637         intel_crtc_dpms_overlay(intel_crtc, true);
3638         intel_crtc_update_cursor(crtc, true);
3639
3640         for_each_encoder_on_crtc(dev, crtc, encoder)
3641                 encoder->enable(encoder);
3642 }
3643
3644 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3645 {
3646         struct drm_device *dev = crtc->dev;
3647         struct drm_i915_private *dev_priv = dev->dev_private;
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         struct intel_encoder *encoder;
3650         int pipe = intel_crtc->pipe;
3651         int plane = intel_crtc->plane;
3652         u32 pctl;
3653
3654
3655         if (!intel_crtc->active)
3656                 return;
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 encoder->disable(encoder);
3660
3661         /* Give the overlay scaler a chance to disable if it's on this pipe */
3662         intel_crtc_wait_for_pending_flips(crtc);
3663         drm_vblank_off(dev, pipe);
3664         intel_crtc_dpms_overlay(intel_crtc, false);
3665         intel_crtc_update_cursor(crtc, false);
3666
3667         if (dev_priv->cfb_plane == plane)
3668                 intel_disable_fbc(dev);
3669
3670         intel_disable_plane(dev_priv, plane, pipe);
3671         intel_disable_pipe(dev_priv, pipe);
3672
3673         /* Disable pannel fitter if it is on this pipe. */
3674         pctl = I915_READ(PFIT_CONTROL);
3675         if ((pctl & PFIT_ENABLE) &&
3676             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3677                 I915_WRITE(PFIT_CONTROL, 0);
3678
3679         intel_disable_pll(dev_priv, pipe);
3680
3681         intel_crtc->active = false;
3682         intel_update_fbc(dev);
3683         intel_update_watermarks(dev);
3684 }
3685
3686 static void i9xx_crtc_off(struct drm_crtc *crtc)
3687 {
3688 }
3689
3690 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3691                                     bool enabled)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_master_private *master_priv;
3695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696         int pipe = intel_crtc->pipe;
3697
3698         if (!dev->primary->master)
3699                 return;
3700
3701         master_priv = dev->primary->master->driver_priv;
3702         if (!master_priv->sarea_priv)
3703                 return;
3704
3705         switch (pipe) {
3706         case 0:
3707                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3708                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3709                 break;
3710         case 1:
3711                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3712                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3713                 break;
3714         default:
3715                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3716                 break;
3717         }
3718 }
3719
3720 /**
3721  * Sets the power management mode of the pipe and plane.
3722  */
3723 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727         struct intel_encoder *intel_encoder;
3728         bool enable = false;
3729
3730         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3731                 enable |= intel_encoder->connectors_active;
3732
3733         if (enable)
3734                 dev_priv->display.crtc_enable(crtc);
3735         else
3736                 dev_priv->display.crtc_disable(crtc);
3737
3738         intel_crtc_update_sarea(crtc, enable);
3739 }
3740
3741 static void intel_crtc_disable(struct drm_crtc *crtc)
3742 {
3743         struct drm_device *dev = crtc->dev;
3744         struct drm_connector *connector;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747
3748         /* crtc should still be enabled when we disable it. */
3749         WARN_ON(!crtc->enabled);
3750
3751         intel_crtc->eld_vld = false;
3752         dev_priv->display.crtc_disable(crtc);
3753         intel_crtc_update_sarea(crtc, false);
3754         dev_priv->display.off(crtc);
3755
3756         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3757         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3758
3759         if (crtc->fb) {
3760                 mutex_lock(&dev->struct_mutex);
3761                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3762                 mutex_unlock(&dev->struct_mutex);
3763                 crtc->fb = NULL;
3764         }
3765
3766         /* Update computed state. */
3767         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3768                 if (!connector->encoder || !connector->encoder->crtc)
3769                         continue;
3770
3771                 if (connector->encoder->crtc != crtc)
3772                         continue;
3773
3774                 connector->dpms = DRM_MODE_DPMS_OFF;
3775                 to_intel_encoder(connector->encoder)->connectors_active = false;
3776         }
3777 }
3778
3779 void intel_modeset_disable(struct drm_device *dev)
3780 {
3781         struct drm_crtc *crtc;
3782
3783         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3784                 if (crtc->enabled)
3785                         intel_crtc_disable(crtc);
3786         }
3787 }
3788
3789 void intel_encoder_destroy(struct drm_encoder *encoder)
3790 {
3791         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3792
3793         drm_encoder_cleanup(encoder);
3794         kfree(intel_encoder);
3795 }
3796
3797 /* Simple dpms helper for encodres with just one connector, no cloning and only
3798  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3799  * state of the entire output pipe. */
3800 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3801 {
3802         if (mode == DRM_MODE_DPMS_ON) {
3803                 encoder->connectors_active = true;
3804
3805                 intel_crtc_update_dpms(encoder->base.crtc);
3806         } else {
3807                 encoder->connectors_active = false;
3808
3809                 intel_crtc_update_dpms(encoder->base.crtc);
3810         }
3811 }
3812
3813 /* Cross check the actual hw state with our own modeset state tracking (and it's
3814  * internal consistency). */
3815 static void intel_connector_check_state(struct intel_connector *connector)
3816 {
3817         if (connector->get_hw_state(connector)) {
3818                 struct intel_encoder *encoder = connector->encoder;
3819                 struct drm_crtc *crtc;
3820                 bool encoder_enabled;
3821                 enum pipe pipe;
3822
3823                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3824                               connector->base.base.id,
3825                               drm_get_connector_name(&connector->base));
3826
3827                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3828                      "wrong connector dpms state\n");
3829                 WARN(connector->base.encoder != &encoder->base,
3830                      "active connector not linked to encoder\n");
3831                 WARN(!encoder->connectors_active,
3832                      "encoder->connectors_active not set\n");
3833
3834                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3835                 WARN(!encoder_enabled, "encoder not enabled\n");
3836                 if (WARN_ON(!encoder->base.crtc))
3837                         return;
3838
3839                 crtc = encoder->base.crtc;
3840
3841                 WARN(!crtc->enabled, "crtc not enabled\n");
3842                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3843                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3844                      "encoder active on the wrong pipe\n");
3845         }
3846 }
3847
3848 /* Even simpler default implementation, if there's really no special case to
3849  * consider. */
3850 void intel_connector_dpms(struct drm_connector *connector, int mode)
3851 {
3852         struct intel_encoder *encoder = intel_attached_encoder(connector);
3853
3854         /* All the simple cases only support two dpms states. */
3855         if (mode != DRM_MODE_DPMS_ON)
3856                 mode = DRM_MODE_DPMS_OFF;
3857
3858         if (mode == connector->dpms)
3859                 return;
3860
3861         connector->dpms = mode;
3862
3863         /* Only need to change hw state when actually enabled */
3864         if (encoder->base.crtc)
3865                 intel_encoder_dpms(encoder, mode);
3866         else
3867                 WARN_ON(encoder->connectors_active != false);
3868
3869         intel_modeset_check_state(connector->dev);
3870 }
3871
3872 /* Simple connector->get_hw_state implementation for encoders that support only
3873  * one connector and no cloning and hence the encoder state determines the state
3874  * of the connector. */
3875 bool intel_connector_get_hw_state(struct intel_connector *connector)
3876 {
3877         enum pipe pipe = 0;
3878         struct intel_encoder *encoder = connector->encoder;
3879
3880         return encoder->get_hw_state(encoder, &pipe);
3881 }
3882
3883 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3884                                   const struct drm_display_mode *mode,
3885                                   struct drm_display_mode *adjusted_mode)
3886 {
3887         struct drm_device *dev = crtc->dev;
3888
3889         if (HAS_PCH_SPLIT(dev)) {
3890                 /* FDI link clock is fixed at 2.7G */
3891                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3892                         return false;
3893         }
3894
3895         /* All interlaced capable intel hw wants timings in frames. Note though
3896          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3897          * timings, so we need to be careful not to clobber these.*/
3898         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3899                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3900
3901         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3902          * with a hsync front porch of 0.
3903          */
3904         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3905                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3906                 return false;
3907
3908         return true;
3909 }
3910
3911 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3912 {
3913         return 400000; /* FIXME */
3914 }
3915
3916 static int i945_get_display_clock_speed(struct drm_device *dev)
3917 {
3918         return 400000;
3919 }
3920
3921 static int i915_get_display_clock_speed(struct drm_device *dev)
3922 {
3923         return 333000;
3924 }
3925
3926 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3927 {
3928         return 200000;
3929 }
3930
3931 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3932 {
3933         u16 gcfgc = 0;
3934
3935         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3936
3937         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3938                 return 133000;
3939         else {
3940                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3941                 case GC_DISPLAY_CLOCK_333_MHZ:
3942                         return 333000;
3943                 default:
3944                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3945                         return 190000;
3946                 }
3947         }
3948 }
3949
3950 static int i865_get_display_clock_speed(struct drm_device *dev)
3951 {
3952         return 266000;
3953 }
3954
3955 static int i855_get_display_clock_speed(struct drm_device *dev)
3956 {
3957         u16 hpllcc = 0;
3958         /* Assume that the hardware is in the high speed state.  This
3959          * should be the default.
3960          */
3961         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3962         case GC_CLOCK_133_200:
3963         case GC_CLOCK_100_200:
3964                 return 200000;
3965         case GC_CLOCK_166_250:
3966                 return 250000;
3967         case GC_CLOCK_100_133:
3968                 return 133000;
3969         }
3970
3971         /* Shouldn't happen */
3972         return 0;
3973 }
3974
3975 static int i830_get_display_clock_speed(struct drm_device *dev)
3976 {
3977         return 133000;
3978 }
3979
3980 static void
3981 intel_reduce_ratio(uint32_t *num, uint32_t *den)
3982 {
3983         while (*num > 0xffffff || *den > 0xffffff) {
3984                 *num >>= 1;
3985                 *den >>= 1;
3986         }
3987 }
3988
3989 void
3990 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3991                        int pixel_clock, int link_clock,
3992                        struct intel_link_m_n *m_n)
3993 {
3994         m_n->tu = 64;
3995         m_n->gmch_m = bits_per_pixel * pixel_clock;
3996         m_n->gmch_n = link_clock * nlanes * 8;
3997         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3998         m_n->link_m = pixel_clock;
3999         m_n->link_n = link_clock;
4000         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4001 }
4002
4003 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4004 {
4005         if (i915_panel_use_ssc >= 0)
4006                 return i915_panel_use_ssc != 0;
4007         return dev_priv->lvds_use_ssc
4008                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4009 }
4010
4011 /**
4012  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4013  * @crtc: CRTC structure
4014  * @mode: requested mode
4015  *
4016  * A pipe may be connected to one or more outputs.  Based on the depth of the
4017  * attached framebuffer, choose a good color depth to use on the pipe.
4018  *
4019  * If possible, match the pipe depth to the fb depth.  In some cases, this
4020  * isn't ideal, because the connected output supports a lesser or restricted
4021  * set of depths.  Resolve that here:
4022  *    LVDS typically supports only 6bpc, so clamp down in that case
4023  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4024  *    Displays may support a restricted set as well, check EDID and clamp as
4025  *      appropriate.
4026  *    DP may want to dither down to 6bpc to fit larger modes
4027  *
4028  * RETURNS:
4029  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4030  * true if they don't match).
4031  */
4032 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4033                                          struct drm_framebuffer *fb,
4034                                          unsigned int *pipe_bpp,
4035                                          struct drm_display_mode *mode)
4036 {
4037         struct drm_device *dev = crtc->dev;
4038         struct drm_i915_private *dev_priv = dev->dev_private;
4039         struct drm_connector *connector;
4040         struct intel_encoder *intel_encoder;
4041         unsigned int display_bpc = UINT_MAX, bpc;
4042
4043         /* Walk the encoders & connectors on this crtc, get min bpc */
4044         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4045
4046                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4047                         unsigned int lvds_bpc;
4048
4049                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4050                             LVDS_A3_POWER_UP)
4051                                 lvds_bpc = 8;
4052                         else
4053                                 lvds_bpc = 6;
4054
4055                         if (lvds_bpc < display_bpc) {
4056                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4057                                 display_bpc = lvds_bpc;
4058                         }
4059                         continue;
4060                 }
4061
4062                 /* Not one of the known troublemakers, check the EDID */
4063                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4064                                     head) {
4065                         if (connector->encoder != &intel_encoder->base)
4066                                 continue;
4067
4068                         /* Don't use an invalid EDID bpc value */
4069                         if (connector->display_info.bpc &&
4070                             connector->display_info.bpc < display_bpc) {
4071                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4072                                 display_bpc = connector->display_info.bpc;
4073                         }
4074                 }
4075
4076                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4077                         /* Use VBT settings if we have an eDP panel */
4078                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4079
4080                         if (edp_bpc && edp_bpc < display_bpc) {
4081                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4082                                 display_bpc = edp_bpc;
4083                         }
4084                         continue;
4085                 }
4086
4087                 /*
4088                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4089                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4090                  */
4091                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4092                         if (display_bpc > 8 && display_bpc < 12) {
4093                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4094                                 display_bpc = 12;
4095                         } else {
4096                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4097                                 display_bpc = 8;
4098                         }
4099                 }
4100         }
4101
4102         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4103                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4104                 display_bpc = 6;
4105         }
4106
4107         /*
4108          * We could just drive the pipe at the highest bpc all the time and
4109          * enable dithering as needed, but that costs bandwidth.  So choose
4110          * the minimum value that expresses the full color range of the fb but
4111          * also stays within the max display bpc discovered above.
4112          */
4113
4114         switch (fb->depth) {
4115         case 8:
4116                 bpc = 8; /* since we go through a colormap */
4117                 break;
4118         case 15:
4119         case 16:
4120                 bpc = 6; /* min is 18bpp */
4121                 break;
4122         case 24:
4123                 bpc = 8;
4124                 break;
4125         case 30:
4126                 bpc = 10;
4127                 break;
4128         case 48:
4129                 bpc = 12;
4130                 break;
4131         default:
4132                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4133                 bpc = min((unsigned int)8, display_bpc);
4134                 break;
4135         }
4136
4137         display_bpc = min(display_bpc, bpc);
4138
4139         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4140                       bpc, display_bpc);
4141
4142         *pipe_bpp = display_bpc * 3;
4143
4144         return display_bpc != bpc;
4145 }
4146
4147 static int vlv_get_refclk(struct drm_crtc *crtc)
4148 {
4149         struct drm_device *dev = crtc->dev;
4150         struct drm_i915_private *dev_priv = dev->dev_private;
4151         int refclk = 27000; /* for DP & HDMI */
4152
4153         return 100000; /* only one validated so far */
4154
4155         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4156                 refclk = 96000;
4157         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4158                 if (intel_panel_use_ssc(dev_priv))
4159                         refclk = 100000;
4160                 else
4161                         refclk = 96000;
4162         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4163                 refclk = 100000;
4164         }
4165
4166         return refclk;
4167 }
4168
4169 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4170 {
4171         struct drm_device *dev = crtc->dev;
4172         struct drm_i915_private *dev_priv = dev->dev_private;
4173         int refclk;
4174
4175         if (IS_VALLEYVIEW(dev)) {
4176                 refclk = vlv_get_refclk(crtc);
4177         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4178             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4179                 refclk = dev_priv->lvds_ssc_freq * 1000;
4180                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4181                               refclk / 1000);
4182         } else if (!IS_GEN2(dev)) {
4183                 refclk = 96000;
4184         } else {
4185                 refclk = 48000;
4186         }
4187
4188         return refclk;
4189 }
4190
4191 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4192                                       intel_clock_t *clock)
4193 {
4194         /* SDVO TV has fixed PLL values depend on its clock range,
4195            this mirrors vbios setting. */
4196         if (adjusted_mode->clock >= 100000
4197             && adjusted_mode->clock < 140500) {
4198                 clock->p1 = 2;
4199                 clock->p2 = 10;
4200                 clock->n = 3;
4201                 clock->m1 = 16;
4202                 clock->m2 = 8;
4203         } else if (adjusted_mode->clock >= 140500
4204                    && adjusted_mode->clock <= 200000) {
4205                 clock->p1 = 1;
4206                 clock->p2 = 10;
4207                 clock->n = 6;
4208                 clock->m1 = 12;
4209                 clock->m2 = 8;
4210         }
4211 }
4212
4213 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4214                                      intel_clock_t *clock,
4215                                      intel_clock_t *reduced_clock)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220         int pipe = intel_crtc->pipe;
4221         u32 fp, fp2 = 0;
4222
4223         if (IS_PINEVIEW(dev)) {
4224                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4225                 if (reduced_clock)
4226                         fp2 = (1 << reduced_clock->n) << 16 |
4227                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4228         } else {
4229                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4230                 if (reduced_clock)
4231                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4232                                 reduced_clock->m2;
4233         }
4234
4235         I915_WRITE(FP0(pipe), fp);
4236
4237         intel_crtc->lowfreq_avail = false;
4238         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4239             reduced_clock && i915_powersave) {
4240                 I915_WRITE(FP1(pipe), fp2);
4241                 intel_crtc->lowfreq_avail = true;
4242         } else {
4243                 I915_WRITE(FP1(pipe), fp);
4244         }
4245 }
4246
4247 static void vlv_update_pll(struct drm_crtc *crtc,
4248                            struct drm_display_mode *mode,
4249                            struct drm_display_mode *adjusted_mode,
4250                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4251                            int num_connectors)
4252 {
4253         struct drm_device *dev = crtc->dev;
4254         struct drm_i915_private *dev_priv = dev->dev_private;
4255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4256         int pipe = intel_crtc->pipe;
4257         u32 dpll, mdiv, pdiv;
4258         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4259         bool is_sdvo;
4260         u32 temp;
4261
4262         mutex_lock(&dev_priv->dpio_lock);
4263
4264         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4265                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4266
4267         dpll = DPLL_VGA_MODE_DIS;
4268         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4269         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4270         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4271
4272         I915_WRITE(DPLL(pipe), dpll);
4273         POSTING_READ(DPLL(pipe));
4274
4275         bestn = clock->n;
4276         bestm1 = clock->m1;
4277         bestm2 = clock->m2;
4278         bestp1 = clock->p1;
4279         bestp2 = clock->p2;
4280
4281         /*
4282          * In Valleyview PLL and program lane counter registers are exposed
4283          * through DPIO interface
4284          */
4285         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4286         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4287         mdiv |= ((bestn << DPIO_N_SHIFT));
4288         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4289         mdiv |= (1 << DPIO_K_SHIFT);
4290         mdiv |= DPIO_ENABLE_CALIBRATION;
4291         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4292
4293         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4294
4295         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4296                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4297                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4298                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4299         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4300
4301         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4302
4303         dpll |= DPLL_VCO_ENABLE;
4304         I915_WRITE(DPLL(pipe), dpll);
4305         POSTING_READ(DPLL(pipe));
4306         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4307                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4308
4309         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4310
4311         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4312                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4313
4314         I915_WRITE(DPLL(pipe), dpll);
4315
4316         /* Wait for the clocks to stabilize. */
4317         POSTING_READ(DPLL(pipe));
4318         udelay(150);
4319
4320         temp = 0;
4321         if (is_sdvo) {
4322                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4323                 if (temp > 1)
4324                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4325                 else
4326                         temp = 0;
4327         }
4328         I915_WRITE(DPLL_MD(pipe), temp);
4329         POSTING_READ(DPLL_MD(pipe));
4330
4331         /* Now program lane control registers */
4332         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4333                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4334         {
4335                 temp = 0x1000C4;
4336                 if(pipe == 1)
4337                         temp |= (1 << 21);
4338                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4339         }
4340         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4341         {
4342                 temp = 0x1000C4;
4343                 if(pipe == 1)
4344                         temp |= (1 << 21);
4345                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4346         }
4347
4348         mutex_unlock(&dev_priv->dpio_lock);
4349 }
4350
4351 static void i9xx_update_pll(struct drm_crtc *crtc,
4352                             struct drm_display_mode *mode,
4353                             struct drm_display_mode *adjusted_mode,
4354                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4355                             int num_connectors)
4356 {
4357         struct drm_device *dev = crtc->dev;
4358         struct drm_i915_private *dev_priv = dev->dev_private;
4359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360         struct intel_encoder *encoder;
4361         int pipe = intel_crtc->pipe;
4362         u32 dpll;
4363         bool is_sdvo;
4364
4365         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4366
4367         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4368                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4369
4370         dpll = DPLL_VGA_MODE_DIS;
4371
4372         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4373                 dpll |= DPLLB_MODE_LVDS;
4374         else
4375                 dpll |= DPLLB_MODE_DAC_SERIAL;
4376         if (is_sdvo) {
4377                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4378                 if (pixel_multiplier > 1) {
4379                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4380                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4381                 }
4382                 dpll |= DPLL_DVO_HIGH_SPEED;
4383         }
4384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4385                 dpll |= DPLL_DVO_HIGH_SPEED;
4386
4387         /* compute bitmask from p1 value */
4388         if (IS_PINEVIEW(dev))
4389                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4390         else {
4391                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4392                 if (IS_G4X(dev) && reduced_clock)
4393                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4394         }
4395         switch (clock->p2) {
4396         case 5:
4397                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4398                 break;
4399         case 7:
4400                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4401                 break;
4402         case 10:
4403                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4404                 break;
4405         case 14:
4406                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4407                 break;
4408         }
4409         if (INTEL_INFO(dev)->gen >= 4)
4410                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4411
4412         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4413                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4414         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4415                 /* XXX: just matching BIOS for now */
4416                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4417                 dpll |= 3;
4418         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4419                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4420                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4421         else
4422                 dpll |= PLL_REF_INPUT_DREFCLK;
4423
4424         dpll |= DPLL_VCO_ENABLE;
4425         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4426         POSTING_READ(DPLL(pipe));
4427         udelay(150);
4428
4429         for_each_encoder_on_crtc(dev, crtc, encoder)
4430                 if (encoder->pre_pll_enable)
4431                         encoder->pre_pll_enable(encoder);
4432
4433         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4434                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4435
4436         I915_WRITE(DPLL(pipe), dpll);
4437
4438         /* Wait for the clocks to stabilize. */
4439         POSTING_READ(DPLL(pipe));
4440         udelay(150);
4441
4442         if (INTEL_INFO(dev)->gen >= 4) {
4443                 u32 temp = 0;
4444                 if (is_sdvo) {
4445                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4446                         if (temp > 1)
4447                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4448                         else
4449                                 temp = 0;
4450                 }
4451                 I915_WRITE(DPLL_MD(pipe), temp);
4452         } else {
4453                 /* The pixel multiplier can only be updated once the
4454                  * DPLL is enabled and the clocks are stable.
4455                  *
4456                  * So write it again.
4457                  */
4458                 I915_WRITE(DPLL(pipe), dpll);
4459         }
4460 }
4461
4462 static void i8xx_update_pll(struct drm_crtc *crtc,
4463                             struct drm_display_mode *adjusted_mode,
4464                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4465                             int num_connectors)
4466 {
4467         struct drm_device *dev = crtc->dev;
4468         struct drm_i915_private *dev_priv = dev->dev_private;
4469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4470         struct intel_encoder *encoder;
4471         int pipe = intel_crtc->pipe;
4472         u32 dpll;
4473
4474         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4475
4476         dpll = DPLL_VGA_MODE_DIS;
4477
4478         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4479                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4480         } else {
4481                 if (clock->p1 == 2)
4482                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4483                 else
4484                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4485                 if (clock->p2 == 4)
4486                         dpll |= PLL_P2_DIVIDE_BY_4;
4487         }
4488
4489         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4490                 /* XXX: just matching BIOS for now */
4491                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4492                 dpll |= 3;
4493         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4494                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4495                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4496         else
4497                 dpll |= PLL_REF_INPUT_DREFCLK;
4498
4499         dpll |= DPLL_VCO_ENABLE;
4500         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4501         POSTING_READ(DPLL(pipe));
4502         udelay(150);
4503
4504         for_each_encoder_on_crtc(dev, crtc, encoder)
4505                 if (encoder->pre_pll_enable)
4506                         encoder->pre_pll_enable(encoder);
4507
4508         I915_WRITE(DPLL(pipe), dpll);
4509
4510         /* Wait for the clocks to stabilize. */
4511         POSTING_READ(DPLL(pipe));
4512         udelay(150);
4513
4514         /* The pixel multiplier can only be updated once the
4515          * DPLL is enabled and the clocks are stable.
4516          *
4517          * So write it again.
4518          */
4519         I915_WRITE(DPLL(pipe), dpll);
4520 }
4521
4522 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4523                                    struct drm_display_mode *mode,
4524                                    struct drm_display_mode *adjusted_mode)
4525 {
4526         struct drm_device *dev = intel_crtc->base.dev;
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         enum pipe pipe = intel_crtc->pipe;
4529         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4530         uint32_t vsyncshift;
4531
4532         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4533                 /* the chip adds 2 halflines automatically */
4534                 adjusted_mode->crtc_vtotal -= 1;
4535                 adjusted_mode->crtc_vblank_end -= 1;
4536                 vsyncshift = adjusted_mode->crtc_hsync_start
4537                              - adjusted_mode->crtc_htotal / 2;
4538         } else {
4539                 vsyncshift = 0;
4540         }
4541
4542         if (INTEL_INFO(dev)->gen > 3)
4543                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4544
4545         I915_WRITE(HTOTAL(cpu_transcoder),
4546                    (adjusted_mode->crtc_hdisplay - 1) |
4547                    ((adjusted_mode->crtc_htotal - 1) << 16));
4548         I915_WRITE(HBLANK(cpu_transcoder),
4549                    (adjusted_mode->crtc_hblank_start - 1) |
4550                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4551         I915_WRITE(HSYNC(cpu_transcoder),
4552                    (adjusted_mode->crtc_hsync_start - 1) |
4553                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4554
4555         I915_WRITE(VTOTAL(cpu_transcoder),
4556                    (adjusted_mode->crtc_vdisplay - 1) |
4557                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4558         I915_WRITE(VBLANK(cpu_transcoder),
4559                    (adjusted_mode->crtc_vblank_start - 1) |
4560                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4561         I915_WRITE(VSYNC(cpu_transcoder),
4562                    (adjusted_mode->crtc_vsync_start - 1) |
4563                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4564
4565         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4566          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4567          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4568          * bits. */
4569         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4570             (pipe == PIPE_B || pipe == PIPE_C))
4571                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4572
4573         /* pipesrc controls the size that is scaled from, which should
4574          * always be the user's requested size.
4575          */
4576         I915_WRITE(PIPESRC(pipe),
4577                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4578 }
4579
4580 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4581                               struct drm_display_mode *mode,
4582                               struct drm_display_mode *adjusted_mode,
4583                               int x, int y,
4584                               struct drm_framebuffer *fb)
4585 {
4586         struct drm_device *dev = crtc->dev;
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4589         int pipe = intel_crtc->pipe;
4590         int plane = intel_crtc->plane;
4591         int refclk, num_connectors = 0;
4592         intel_clock_t clock, reduced_clock;
4593         u32 dspcntr, pipeconf;
4594         bool ok, has_reduced_clock = false, is_sdvo = false;
4595         bool is_lvds = false, is_tv = false, is_dp = false;
4596         struct intel_encoder *encoder;
4597         const intel_limit_t *limit;
4598         int ret;
4599
4600         for_each_encoder_on_crtc(dev, crtc, encoder) {
4601                 switch (encoder->type) {
4602                 case INTEL_OUTPUT_LVDS:
4603                         is_lvds = true;
4604                         break;
4605                 case INTEL_OUTPUT_SDVO:
4606                 case INTEL_OUTPUT_HDMI:
4607                         is_sdvo = true;
4608                         if (encoder->needs_tv_clock)
4609                                 is_tv = true;
4610                         break;
4611                 case INTEL_OUTPUT_TVOUT:
4612                         is_tv = true;
4613                         break;
4614                 case INTEL_OUTPUT_DISPLAYPORT:
4615                         is_dp = true;
4616                         break;
4617                 }
4618
4619                 num_connectors++;
4620         }
4621
4622         refclk = i9xx_get_refclk(crtc, num_connectors);
4623
4624         /*
4625          * Returns a set of divisors for the desired target clock with the given
4626          * refclk, or FALSE.  The returned values represent the clock equation:
4627          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4628          */
4629         limit = intel_limit(crtc, refclk);
4630         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4631                              &clock);
4632         if (!ok) {
4633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4634                 return -EINVAL;
4635         }
4636
4637         /* Ensure that the cursor is valid for the new mode before changing... */
4638         intel_crtc_update_cursor(crtc, true);
4639
4640         if (is_lvds && dev_priv->lvds_downclock_avail) {
4641                 /*
4642                  * Ensure we match the reduced clock's P to the target clock.
4643                  * If the clocks don't match, we can't switch the display clock
4644                  * by using the FP0/FP1. In such case we will disable the LVDS
4645                  * downclock feature.
4646                 */
4647                 has_reduced_clock = limit->find_pll(limit, crtc,
4648                                                     dev_priv->lvds_downclock,
4649                                                     refclk,
4650                                                     &clock,
4651                                                     &reduced_clock);
4652         }
4653
4654         if (is_sdvo && is_tv)
4655                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4656
4657         if (IS_GEN2(dev))
4658                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4659                                 has_reduced_clock ? &reduced_clock : NULL,
4660                                 num_connectors);
4661         else if (IS_VALLEYVIEW(dev))
4662                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4663                                 has_reduced_clock ? &reduced_clock : NULL,
4664                                 num_connectors);
4665         else
4666                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4667                                 has_reduced_clock ? &reduced_clock : NULL,
4668                                 num_connectors);
4669
4670         /* setup pipeconf */
4671         pipeconf = I915_READ(PIPECONF(pipe));
4672
4673         /* Set up the display plane register */
4674         dspcntr = DISPPLANE_GAMMA_ENABLE;
4675
4676         if (pipe == 0)
4677                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4678         else
4679                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4680
4681         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4682                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4683                  * core speed.
4684                  *
4685                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4686                  * pipe == 0 check?
4687                  */
4688                 if (mode->clock >
4689                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4690                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4691                 else
4692                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4693         }
4694
4695         /* default to 8bpc */
4696         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4697         if (is_dp) {
4698                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4699                         pipeconf |= PIPECONF_6BPC |
4700                                     PIPECONF_DITHER_EN |
4701                                     PIPECONF_DITHER_TYPE_SP;
4702                 }
4703         }
4704
4705         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4706                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4707                         pipeconf |= PIPECONF_6BPC |
4708                                         PIPECONF_ENABLE |
4709                                         I965_PIPECONF_ACTIVE;
4710                 }
4711         }
4712
4713         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4714         drm_mode_debug_printmodeline(mode);
4715
4716         if (HAS_PIPE_CXSR(dev)) {
4717                 if (intel_crtc->lowfreq_avail) {
4718                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4719                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4720                 } else {
4721                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4722                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4723                 }
4724         }
4725
4726         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4727         if (!IS_GEN2(dev) &&
4728             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4729                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4730         else
4731                 pipeconf |= PIPECONF_PROGRESSIVE;
4732
4733         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4734
4735         /* pipesrc and dspsize control the size that is scaled from,
4736          * which should always be the user's requested size.
4737          */
4738         I915_WRITE(DSPSIZE(plane),
4739                    ((mode->vdisplay - 1) << 16) |
4740                    (mode->hdisplay - 1));
4741         I915_WRITE(DSPPOS(plane), 0);
4742
4743         I915_WRITE(PIPECONF(pipe), pipeconf);
4744         POSTING_READ(PIPECONF(pipe));
4745         intel_enable_pipe(dev_priv, pipe, false);
4746
4747         intel_wait_for_vblank(dev, pipe);
4748
4749         I915_WRITE(DSPCNTR(plane), dspcntr);
4750         POSTING_READ(DSPCNTR(plane));
4751
4752         ret = intel_pipe_set_base(crtc, x, y, fb);
4753
4754         intel_update_watermarks(dev);
4755
4756         return ret;
4757 }
4758
4759 static void ironlake_init_pch_refclk(struct drm_device *dev)
4760 {
4761         struct drm_i915_private *dev_priv = dev->dev_private;
4762         struct drm_mode_config *mode_config = &dev->mode_config;
4763         struct intel_encoder *encoder;
4764         u32 temp;
4765         bool has_lvds = false;
4766         bool has_cpu_edp = false;
4767         bool has_pch_edp = false;
4768         bool has_panel = false;
4769         bool has_ck505 = false;
4770         bool can_ssc = false;
4771
4772         /* We need to take the global config into account */
4773         list_for_each_entry(encoder, &mode_config->encoder_list,
4774                             base.head) {
4775                 switch (encoder->type) {
4776                 case INTEL_OUTPUT_LVDS:
4777                         has_panel = true;
4778                         has_lvds = true;
4779                         break;
4780                 case INTEL_OUTPUT_EDP:
4781                         has_panel = true;
4782                         if (intel_encoder_is_pch_edp(&encoder->base))
4783                                 has_pch_edp = true;
4784                         else
4785                                 has_cpu_edp = true;
4786                         break;
4787                 }
4788         }
4789
4790         if (HAS_PCH_IBX(dev)) {
4791                 has_ck505 = dev_priv->display_clock_mode;
4792                 can_ssc = has_ck505;
4793         } else {
4794                 has_ck505 = false;
4795                 can_ssc = true;
4796         }
4797
4798         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4799                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4800                       has_ck505);
4801
4802         /* Ironlake: try to setup display ref clock before DPLL
4803          * enabling. This is only under driver's control after
4804          * PCH B stepping, previous chipset stepping should be
4805          * ignoring this setting.
4806          */
4807         temp = I915_READ(PCH_DREF_CONTROL);
4808         /* Always enable nonspread source */
4809         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4810
4811         if (has_ck505)
4812                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4813         else
4814                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4815
4816         if (has_panel) {
4817                 temp &= ~DREF_SSC_SOURCE_MASK;
4818                 temp |= DREF_SSC_SOURCE_ENABLE;
4819
4820                 /* SSC must be turned on before enabling the CPU output  */
4821                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4822                         DRM_DEBUG_KMS("Using SSC on panel\n");
4823                         temp |= DREF_SSC1_ENABLE;
4824                 } else
4825                         temp &= ~DREF_SSC1_ENABLE;
4826
4827                 /* Get SSC going before enabling the outputs */
4828                 I915_WRITE(PCH_DREF_CONTROL, temp);
4829                 POSTING_READ(PCH_DREF_CONTROL);
4830                 udelay(200);
4831
4832                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4833
4834                 /* Enable CPU source on CPU attached eDP */
4835                 if (has_cpu_edp) {
4836                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4837                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4838                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4839                         }
4840                         else
4841                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4842                 } else
4843                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4844
4845                 I915_WRITE(PCH_DREF_CONTROL, temp);
4846                 POSTING_READ(PCH_DREF_CONTROL);
4847                 udelay(200);
4848         } else {
4849                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4850
4851                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4852
4853                 /* Turn off CPU output */
4854                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4855
4856                 I915_WRITE(PCH_DREF_CONTROL, temp);
4857                 POSTING_READ(PCH_DREF_CONTROL);
4858                 udelay(200);
4859
4860                 /* Turn off the SSC source */
4861                 temp &= ~DREF_SSC_SOURCE_MASK;
4862                 temp |= DREF_SSC_SOURCE_DISABLE;
4863
4864                 /* Turn off SSC1 */
4865                 temp &= ~ DREF_SSC1_ENABLE;
4866
4867                 I915_WRITE(PCH_DREF_CONTROL, temp);
4868                 POSTING_READ(PCH_DREF_CONTROL);
4869                 udelay(200);
4870         }
4871 }
4872
4873 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4874 static void lpt_init_pch_refclk(struct drm_device *dev)
4875 {
4876         struct drm_i915_private *dev_priv = dev->dev_private;
4877         struct drm_mode_config *mode_config = &dev->mode_config;
4878         struct intel_encoder *encoder;
4879         bool has_vga = false;
4880         bool is_sdv = false;
4881         u32 tmp;
4882
4883         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4884                 switch (encoder->type) {
4885                 case INTEL_OUTPUT_ANALOG:
4886                         has_vga = true;
4887                         break;
4888                 }
4889         }
4890
4891         if (!has_vga)
4892                 return;
4893
4894         mutex_lock(&dev_priv->dpio_lock);
4895
4896         /* XXX: Rip out SDV support once Haswell ships for real. */
4897         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4898                 is_sdv = true;
4899
4900         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4901         tmp &= ~SBI_SSCCTL_DISABLE;
4902         tmp |= SBI_SSCCTL_PATHALT;
4903         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4904
4905         udelay(24);
4906
4907         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4908         tmp &= ~SBI_SSCCTL_PATHALT;
4909         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4910
4911         if (!is_sdv) {
4912                 tmp = I915_READ(SOUTH_CHICKEN2);
4913                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4914                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4915
4916                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4917                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4918                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4919
4920                 tmp = I915_READ(SOUTH_CHICKEN2);
4921                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4922                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4923
4924                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4925                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4926                                        100))
4927                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4928         }
4929
4930         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4931         tmp &= ~(0xFF << 24);
4932         tmp |= (0x12 << 24);
4933         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4934
4935         if (!is_sdv) {
4936                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4937                 tmp &= ~(0x3 << 6);
4938                 tmp |= (1 << 6) | (1 << 0);
4939                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4940         }
4941
4942         if (is_sdv) {
4943                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4944                 tmp |= 0x7FFF;
4945                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4946         }
4947
4948         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4949         tmp |= (1 << 11);
4950         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4951
4952         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4953         tmp |= (1 << 11);
4954         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4955
4956         if (is_sdv) {
4957                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4958                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4959                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4960
4961                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4962                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4963                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4964
4965                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4966                 tmp |= (0x3F << 8);
4967                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4968
4969                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4970                 tmp |= (0x3F << 8);
4971                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4972         }
4973
4974         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4975         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4976         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4977
4978         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4979         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4980         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4981
4982         if (!is_sdv) {
4983                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4984                 tmp &= ~(7 << 13);
4985                 tmp |= (5 << 13);
4986                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4987
4988                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4989                 tmp &= ~(7 << 13);
4990                 tmp |= (5 << 13);
4991                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4992         }
4993
4994         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4995         tmp &= ~0xFF;
4996         tmp |= 0x1C;
4997         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4998
4999         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5000         tmp &= ~0xFF;
5001         tmp |= 0x1C;
5002         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5003
5004         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5005         tmp &= ~(0xFF << 16);
5006         tmp |= (0x1C << 16);
5007         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5008
5009         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5010         tmp &= ~(0xFF << 16);
5011         tmp |= (0x1C << 16);
5012         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5013
5014         if (!is_sdv) {
5015                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5016                 tmp |= (1 << 27);
5017                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5018
5019                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5020                 tmp |= (1 << 27);
5021                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5022
5023                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5024                 tmp &= ~(0xF << 28);
5025                 tmp |= (4 << 28);
5026                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5027
5028                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5029                 tmp &= ~(0xF << 28);
5030                 tmp |= (4 << 28);
5031                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5032         }
5033
5034         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5035         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5036         tmp |= SBI_DBUFF0_ENABLE;
5037         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5038
5039         mutex_unlock(&dev_priv->dpio_lock);
5040 }
5041
5042 /*
5043  * Initialize reference clocks when the driver loads
5044  */
5045 void intel_init_pch_refclk(struct drm_device *dev)
5046 {
5047         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5048                 ironlake_init_pch_refclk(dev);
5049         else if (HAS_PCH_LPT(dev))
5050                 lpt_init_pch_refclk(dev);
5051 }
5052
5053 static int ironlake_get_refclk(struct drm_crtc *crtc)
5054 {
5055         struct drm_device *dev = crtc->dev;
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         struct intel_encoder *encoder;
5058         struct intel_encoder *edp_encoder = NULL;
5059         int num_connectors = 0;
5060         bool is_lvds = false;
5061
5062         for_each_encoder_on_crtc(dev, crtc, encoder) {
5063                 switch (encoder->type) {
5064                 case INTEL_OUTPUT_LVDS:
5065                         is_lvds = true;
5066                         break;
5067                 case INTEL_OUTPUT_EDP:
5068                         edp_encoder = encoder;
5069                         break;
5070                 }
5071                 num_connectors++;
5072         }
5073
5074         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5075                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5076                               dev_priv->lvds_ssc_freq);
5077                 return dev_priv->lvds_ssc_freq * 1000;
5078         }
5079
5080         return 120000;
5081 }
5082
5083 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5084                                   struct drm_display_mode *adjusted_mode,
5085                                   bool dither)
5086 {
5087         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5089         int pipe = intel_crtc->pipe;
5090         uint32_t val;
5091
5092         val = I915_READ(PIPECONF(pipe));
5093
5094         val &= ~PIPECONF_BPC_MASK;
5095         switch (intel_crtc->bpp) {
5096         case 18:
5097                 val |= PIPECONF_6BPC;
5098                 break;
5099         case 24:
5100                 val |= PIPECONF_8BPC;
5101                 break;
5102         case 30:
5103                 val |= PIPECONF_10BPC;
5104                 break;
5105         case 36:
5106                 val |= PIPECONF_12BPC;
5107                 break;
5108         default:
5109                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5110                 BUG();
5111         }
5112
5113         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5114         if (dither)
5115                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5116
5117         val &= ~PIPECONF_INTERLACE_MASK;
5118         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5119                 val |= PIPECONF_INTERLACED_ILK;
5120         else
5121                 val |= PIPECONF_PROGRESSIVE;
5122
5123         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5124                 val |= PIPECONF_COLOR_RANGE_SELECT;
5125         else
5126                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5127
5128         I915_WRITE(PIPECONF(pipe), val);
5129         POSTING_READ(PIPECONF(pipe));
5130 }
5131
5132 /*
5133  * Set up the pipe CSC unit.
5134  *
5135  * Currently only full range RGB to limited range RGB conversion
5136  * is supported, but eventually this should handle various
5137  * RGB<->YCbCr scenarios as well.
5138  */
5139 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5140                                const struct drm_display_mode *adjusted_mode)
5141 {
5142         struct drm_device *dev = crtc->dev;
5143         struct drm_i915_private *dev_priv = dev->dev_private;
5144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5145         int pipe = intel_crtc->pipe;
5146         uint16_t coeff = 0x7800; /* 1.0 */
5147
5148         /*
5149          * TODO: Check what kind of values actually come out of the pipe
5150          * with these coeff/postoff values and adjust to get the best
5151          * accuracy. Perhaps we even need to take the bpc value into
5152          * consideration.
5153          */
5154
5155         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5156                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5157
5158         /*
5159          * GY/GU and RY/RU should be the other way around according
5160          * to BSpec, but reality doesn't agree. Just set them up in
5161          * a way that results in the correct picture.
5162          */
5163         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5164         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5165
5166         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5167         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5168
5169         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5170         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5171
5172         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5173         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5174         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5175
5176         if (INTEL_INFO(dev)->gen > 6) {
5177                 uint16_t postoff = 0;
5178
5179                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5180                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5181
5182                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5183                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5184                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5185
5186                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5187         } else {
5188                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5189
5190                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5191                         mode |= CSC_BLACK_SCREEN_OFFSET;
5192
5193                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5194         }
5195 }
5196
5197 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5198                                  struct drm_display_mode *adjusted_mode,
5199                                  bool dither)
5200 {
5201         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5204         uint32_t val;
5205
5206         val = I915_READ(PIPECONF(cpu_transcoder));
5207
5208         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5209         if (dither)
5210                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5211
5212         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5213         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5214                 val |= PIPECONF_INTERLACED_ILK;
5215         else
5216                 val |= PIPECONF_PROGRESSIVE;
5217
5218         I915_WRITE(PIPECONF(cpu_transcoder), val);
5219         POSTING_READ(PIPECONF(cpu_transcoder));
5220 }
5221
5222 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5223                                     struct drm_display_mode *adjusted_mode,
5224                                     intel_clock_t *clock,
5225                                     bool *has_reduced_clock,
5226                                     intel_clock_t *reduced_clock)
5227 {
5228         struct drm_device *dev = crtc->dev;
5229         struct drm_i915_private *dev_priv = dev->dev_private;
5230         struct intel_encoder *intel_encoder;
5231         int refclk;
5232         const intel_limit_t *limit;
5233         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5234
5235         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5236                 switch (intel_encoder->type) {
5237                 case INTEL_OUTPUT_LVDS:
5238                         is_lvds = true;
5239                         break;
5240                 case INTEL_OUTPUT_SDVO:
5241                 case INTEL_OUTPUT_HDMI:
5242                         is_sdvo = true;
5243                         if (intel_encoder->needs_tv_clock)
5244                                 is_tv = true;
5245                         break;
5246                 case INTEL_OUTPUT_TVOUT:
5247                         is_tv = true;
5248                         break;
5249                 }
5250         }
5251
5252         refclk = ironlake_get_refclk(crtc);
5253
5254         /*
5255          * Returns a set of divisors for the desired target clock with the given
5256          * refclk, or FALSE.  The returned values represent the clock equation:
5257          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5258          */
5259         limit = intel_limit(crtc, refclk);
5260         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5261                               clock);
5262         if (!ret)
5263                 return false;
5264
5265         if (is_lvds && dev_priv->lvds_downclock_avail) {
5266                 /*
5267                  * Ensure we match the reduced clock's P to the target clock.
5268                  * If the clocks don't match, we can't switch the display clock
5269                  * by using the FP0/FP1. In such case we will disable the LVDS
5270                  * downclock feature.
5271                 */
5272                 *has_reduced_clock = limit->find_pll(limit, crtc,
5273                                                      dev_priv->lvds_downclock,
5274                                                      refclk,
5275                                                      clock,
5276                                                      reduced_clock);
5277         }
5278
5279         if (is_sdvo && is_tv)
5280                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5281
5282         return true;
5283 }
5284
5285 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5286 {
5287         struct drm_i915_private *dev_priv = dev->dev_private;
5288         uint32_t temp;
5289
5290         temp = I915_READ(SOUTH_CHICKEN1);
5291         if (temp & FDI_BC_BIFURCATION_SELECT)
5292                 return;
5293
5294         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5295         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5296
5297         temp |= FDI_BC_BIFURCATION_SELECT;
5298         DRM_DEBUG_KMS("enabling fdi C rx\n");
5299         I915_WRITE(SOUTH_CHICKEN1, temp);
5300         POSTING_READ(SOUTH_CHICKEN1);
5301 }
5302
5303 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5304 {
5305         struct drm_device *dev = intel_crtc->base.dev;
5306         struct drm_i915_private *dev_priv = dev->dev_private;
5307         struct intel_crtc *pipe_B_crtc =
5308                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5309
5310         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5311                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5312         if (intel_crtc->fdi_lanes > 4) {
5313                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5314                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5315                 /* Clamp lanes to avoid programming the hw with bogus values. */
5316                 intel_crtc->fdi_lanes = 4;
5317
5318                 return false;
5319         }
5320
5321         if (dev_priv->num_pipe == 2)
5322                 return true;
5323
5324         switch (intel_crtc->pipe) {
5325         case PIPE_A:
5326                 return true;
5327         case PIPE_B:
5328                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5329                     intel_crtc->fdi_lanes > 2) {
5330                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5331                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5332                         /* Clamp lanes to avoid programming the hw with bogus values. */
5333                         intel_crtc->fdi_lanes = 2;
5334
5335                         return false;
5336                 }
5337
5338                 if (intel_crtc->fdi_lanes > 2)
5339                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5340                 else
5341                         cpt_enable_fdi_bc_bifurcation(dev);
5342
5343                 return true;
5344         case PIPE_C:
5345                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5346                         if (intel_crtc->fdi_lanes > 2) {
5347                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5348                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5349                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5350                                 intel_crtc->fdi_lanes = 2;
5351
5352                                 return false;
5353                         }
5354                 } else {
5355                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5356                         return false;
5357                 }
5358
5359                 cpt_enable_fdi_bc_bifurcation(dev);
5360
5361                 return true;
5362         default:
5363                 BUG();
5364         }
5365 }
5366
5367 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5368 {
5369         /*
5370          * Account for spread spectrum to avoid
5371          * oversubscribing the link. Max center spread
5372          * is 2.5%; use 5% for safety's sake.
5373          */
5374         u32 bps = target_clock * bpp * 21 / 20;
5375         return bps / (link_bw * 8) + 1;
5376 }
5377
5378 static void ironlake_set_m_n(struct drm_crtc *crtc,
5379                              struct drm_display_mode *mode,
5380                              struct drm_display_mode *adjusted_mode)
5381 {
5382         struct drm_device *dev = crtc->dev;
5383         struct drm_i915_private *dev_priv = dev->dev_private;
5384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5386         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5387         struct intel_link_m_n m_n = {0};
5388         int target_clock, pixel_multiplier, lane, link_bw;
5389         bool is_dp = false, is_cpu_edp = false;
5390
5391         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5392                 switch (intel_encoder->type) {
5393                 case INTEL_OUTPUT_DISPLAYPORT:
5394                         is_dp = true;
5395                         break;
5396                 case INTEL_OUTPUT_EDP:
5397                         is_dp = true;
5398                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5399                                 is_cpu_edp = true;
5400                         edp_encoder = intel_encoder;
5401                         break;
5402                 }
5403         }
5404
5405         /* FDI link */
5406         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5407         lane = 0;
5408         /* CPU eDP doesn't require FDI link, so just set DP M/N
5409            according to current link config */
5410         if (is_cpu_edp) {
5411                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5412         } else {
5413                 /* FDI is a binary signal running at ~2.7GHz, encoding
5414                  * each output octet as 10 bits. The actual frequency
5415                  * is stored as a divider into a 100MHz clock, and the
5416                  * mode pixel clock is stored in units of 1KHz.
5417                  * Hence the bw of each lane in terms of the mode signal
5418                  * is:
5419                  */
5420                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5421         }
5422
5423         /* [e]DP over FDI requires target mode clock instead of link clock. */
5424         if (edp_encoder)
5425                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5426         else if (is_dp)
5427                 target_clock = mode->clock;
5428         else
5429                 target_clock = adjusted_mode->clock;
5430
5431         if (!lane)
5432                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5433                                                    intel_crtc->bpp);
5434
5435         intel_crtc->fdi_lanes = lane;
5436
5437         if (pixel_multiplier > 1)
5438                 link_bw *= pixel_multiplier;
5439         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5440
5441         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5442         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5443         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5444         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5445 }
5446
5447 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5448                                       struct drm_display_mode *adjusted_mode,
5449                                       intel_clock_t *clock, u32 fp)
5450 {
5451         struct drm_crtc *crtc = &intel_crtc->base;
5452         struct drm_device *dev = crtc->dev;
5453         struct drm_i915_private *dev_priv = dev->dev_private;
5454         struct intel_encoder *intel_encoder;
5455         uint32_t dpll;
5456         int factor, pixel_multiplier, num_connectors = 0;
5457         bool is_lvds = false, is_sdvo = false, is_tv = false;
5458         bool is_dp = false, is_cpu_edp = false;
5459
5460         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5461                 switch (intel_encoder->type) {
5462                 case INTEL_OUTPUT_LVDS:
5463                         is_lvds = true;
5464                         break;
5465                 case INTEL_OUTPUT_SDVO:
5466                 case INTEL_OUTPUT_HDMI:
5467                         is_sdvo = true;
5468                         if (intel_encoder->needs_tv_clock)
5469                                 is_tv = true;
5470                         break;
5471                 case INTEL_OUTPUT_TVOUT:
5472                         is_tv = true;
5473                         break;
5474                 case INTEL_OUTPUT_DISPLAYPORT:
5475                         is_dp = true;
5476                         break;
5477                 case INTEL_OUTPUT_EDP:
5478                         is_dp = true;
5479                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5480                                 is_cpu_edp = true;
5481                         break;
5482                 }
5483
5484                 num_connectors++;
5485         }
5486
5487         /* Enable autotuning of the PLL clock (if permissible) */
5488         factor = 21;
5489         if (is_lvds) {
5490                 if ((intel_panel_use_ssc(dev_priv) &&
5491                      dev_priv->lvds_ssc_freq == 100) ||
5492                     intel_is_dual_link_lvds(dev))
5493                         factor = 25;
5494         } else if (is_sdvo && is_tv)
5495                 factor = 20;
5496
5497         if (clock->m < factor * clock->n)
5498                 fp |= FP_CB_TUNE;
5499
5500         dpll = 0;
5501
5502         if (is_lvds)
5503                 dpll |= DPLLB_MODE_LVDS;
5504         else
5505                 dpll |= DPLLB_MODE_DAC_SERIAL;
5506         if (is_sdvo) {
5507                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5508                 if (pixel_multiplier > 1) {
5509                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5510                 }
5511                 dpll |= DPLL_DVO_HIGH_SPEED;
5512         }
5513         if (is_dp && !is_cpu_edp)
5514                 dpll |= DPLL_DVO_HIGH_SPEED;
5515
5516         /* compute bitmask from p1 value */
5517         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5518         /* also FPA1 */
5519         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5520
5521         switch (clock->p2) {
5522         case 5:
5523                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5524                 break;
5525         case 7:
5526                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5527                 break;
5528         case 10:
5529                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5530                 break;
5531         case 14:
5532                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5533                 break;
5534         }
5535
5536         if (is_sdvo && is_tv)
5537                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5538         else if (is_tv)
5539                 /* XXX: just matching BIOS for now */
5540                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5541                 dpll |= 3;
5542         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5543                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5544         else
5545                 dpll |= PLL_REF_INPUT_DREFCLK;
5546
5547         return dpll;
5548 }
5549
5550 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5551                                   struct drm_display_mode *mode,
5552                                   struct drm_display_mode *adjusted_mode,
5553                                   int x, int y,
5554                                   struct drm_framebuffer *fb)
5555 {
5556         struct drm_device *dev = crtc->dev;
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559         int pipe = intel_crtc->pipe;
5560         int plane = intel_crtc->plane;
5561         int num_connectors = 0;
5562         intel_clock_t clock, reduced_clock;
5563         u32 dpll, fp = 0, fp2 = 0;
5564         bool ok, has_reduced_clock = false;
5565         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5566         struct intel_encoder *encoder;
5567         int ret;
5568         bool dither, fdi_config_ok;
5569
5570         for_each_encoder_on_crtc(dev, crtc, encoder) {
5571                 switch (encoder->type) {
5572                 case INTEL_OUTPUT_LVDS:
5573                         is_lvds = true;
5574                         break;
5575                 case INTEL_OUTPUT_DISPLAYPORT:
5576                         is_dp = true;
5577                         break;
5578                 case INTEL_OUTPUT_EDP:
5579                         is_dp = true;
5580                         if (!intel_encoder_is_pch_edp(&encoder->base))
5581                                 is_cpu_edp = true;
5582                         break;
5583                 }
5584
5585                 num_connectors++;
5586         }
5587
5588         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5589              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5590
5591         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5592                                      &has_reduced_clock, &reduced_clock);
5593         if (!ok) {
5594                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5595                 return -EINVAL;
5596         }
5597
5598         /* Ensure that the cursor is valid for the new mode before changing... */
5599         intel_crtc_update_cursor(crtc, true);
5600
5601         /* determine panel color depth */
5602         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5603                                               adjusted_mode);
5604         if (is_lvds && dev_priv->lvds_dither)
5605                 dither = true;
5606
5607         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5608         if (has_reduced_clock)
5609                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5610                         reduced_clock.m2;
5611
5612         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5613
5614         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5615         drm_mode_debug_printmodeline(mode);
5616
5617         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5618         if (!is_cpu_edp) {
5619                 struct intel_pch_pll *pll;
5620
5621                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5622                 if (pll == NULL) {
5623                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5624                                          pipe);
5625                         return -EINVAL;
5626                 }
5627         } else
5628                 intel_put_pch_pll(intel_crtc);
5629
5630         if (is_dp && !is_cpu_edp)
5631                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5632
5633         for_each_encoder_on_crtc(dev, crtc, encoder)
5634                 if (encoder->pre_pll_enable)
5635                         encoder->pre_pll_enable(encoder);
5636
5637         if (intel_crtc->pch_pll) {
5638                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5639
5640                 /* Wait for the clocks to stabilize. */
5641                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5642                 udelay(150);
5643
5644                 /* The pixel multiplier can only be updated once the
5645                  * DPLL is enabled and the clocks are stable.
5646                  *
5647                  * So write it again.
5648                  */
5649                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5650         }
5651
5652         intel_crtc->lowfreq_avail = false;
5653         if (intel_crtc->pch_pll) {
5654                 if (is_lvds && has_reduced_clock && i915_powersave) {
5655                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5656                         intel_crtc->lowfreq_avail = true;
5657                 } else {
5658                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5659                 }
5660         }
5661
5662         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5663
5664         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5665          * ironlake_check_fdi_lanes. */
5666         ironlake_set_m_n(crtc, mode, adjusted_mode);
5667
5668         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5669
5670         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5671
5672         intel_wait_for_vblank(dev, pipe);
5673
5674         /* Set up the display plane register */
5675         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5676         POSTING_READ(DSPCNTR(plane));
5677
5678         ret = intel_pipe_set_base(crtc, x, y, fb);
5679
5680         intel_update_watermarks(dev);
5681
5682         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5683
5684         return fdi_config_ok ? ret : -EINVAL;
5685 }
5686
5687 static void haswell_modeset_global_resources(struct drm_device *dev)
5688 {
5689         struct drm_i915_private *dev_priv = dev->dev_private;
5690         bool enable = false;
5691         struct intel_crtc *crtc;
5692         struct intel_encoder *encoder;
5693
5694         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5695                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5696                         enable = true;
5697                 /* XXX: Should check for edp transcoder here, but thanks to init
5698                  * sequence that's not yet available. Just in case desktop eDP
5699                  * on PORT D is possible on haswell, too. */
5700         }
5701
5702         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5703                             base.head) {
5704                 if (encoder->type != INTEL_OUTPUT_EDP &&
5705                     encoder->connectors_active)
5706                         enable = true;
5707         }
5708
5709         /* Even the eDP panel fitter is outside the always-on well. */
5710         if (dev_priv->pch_pf_size)
5711                 enable = true;
5712
5713         intel_set_power_well(dev, enable);
5714 }
5715
5716 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5717                                  struct drm_display_mode *mode,
5718                                  struct drm_display_mode *adjusted_mode,
5719                                  int x, int y,
5720                                  struct drm_framebuffer *fb)
5721 {
5722         struct drm_device *dev = crtc->dev;
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725         int pipe = intel_crtc->pipe;
5726         int plane = intel_crtc->plane;
5727         int num_connectors = 0;
5728         bool is_dp = false, is_cpu_edp = false;
5729         struct intel_encoder *encoder;
5730         int ret;
5731         bool dither;
5732
5733         for_each_encoder_on_crtc(dev, crtc, encoder) {
5734                 switch (encoder->type) {
5735                 case INTEL_OUTPUT_DISPLAYPORT:
5736                         is_dp = true;
5737                         break;
5738                 case INTEL_OUTPUT_EDP:
5739                         is_dp = true;
5740                         if (!intel_encoder_is_pch_edp(&encoder->base))
5741                                 is_cpu_edp = true;
5742                         break;
5743                 }
5744
5745                 num_connectors++;
5746         }
5747
5748         /* We are not sure yet this won't happen. */
5749         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5750              INTEL_PCH_TYPE(dev));
5751
5752         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5753              num_connectors, pipe_name(pipe));
5754
5755         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5756                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5757
5758         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5759
5760         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5761                 return -EINVAL;
5762
5763         /* Ensure that the cursor is valid for the new mode before changing... */
5764         intel_crtc_update_cursor(crtc, true);
5765
5766         /* determine panel color depth */
5767         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5768                                               adjusted_mode);
5769
5770         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5771         drm_mode_debug_printmodeline(mode);
5772
5773         if (is_dp && !is_cpu_edp)
5774                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5775
5776         intel_crtc->lowfreq_avail = false;
5777
5778         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5779
5780         if (!is_dp || is_cpu_edp)
5781                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5782
5783         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5784
5785         intel_set_pipe_csc(crtc, adjusted_mode);
5786
5787         /* Set up the display plane register */
5788         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5789         POSTING_READ(DSPCNTR(plane));
5790
5791         ret = intel_pipe_set_base(crtc, x, y, fb);
5792
5793         intel_update_watermarks(dev);
5794
5795         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5796
5797         return ret;
5798 }
5799
5800 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5801                                struct drm_display_mode *mode,
5802                                struct drm_display_mode *adjusted_mode,
5803                                int x, int y,
5804                                struct drm_framebuffer *fb)
5805 {
5806         struct drm_device *dev = crtc->dev;
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         struct drm_encoder_helper_funcs *encoder_funcs;
5809         struct intel_encoder *encoder;
5810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5811         int pipe = intel_crtc->pipe;
5812         int ret;
5813
5814         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5815                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5816         else
5817                 intel_crtc->cpu_transcoder = pipe;
5818
5819         drm_vblank_pre_modeset(dev, pipe);
5820
5821         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5822                                               x, y, fb);
5823         drm_vblank_post_modeset(dev, pipe);
5824
5825         if (ret != 0)
5826                 return ret;
5827
5828         for_each_encoder_on_crtc(dev, crtc, encoder) {
5829                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5830                         encoder->base.base.id,
5831                         drm_get_encoder_name(&encoder->base),
5832                         mode->base.id, mode->name);
5833                 encoder_funcs = encoder->base.helper_private;
5834                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5835         }
5836
5837         return 0;
5838 }
5839
5840 static bool intel_eld_uptodate(struct drm_connector *connector,
5841                                int reg_eldv, uint32_t bits_eldv,
5842                                int reg_elda, uint32_t bits_elda,
5843                                int reg_edid)
5844 {
5845         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5846         uint8_t *eld = connector->eld;
5847         uint32_t i;
5848
5849         i = I915_READ(reg_eldv);
5850         i &= bits_eldv;
5851
5852         if (!eld[0])
5853                 return !i;
5854
5855         if (!i)
5856                 return false;
5857
5858         i = I915_READ(reg_elda);
5859         i &= ~bits_elda;
5860         I915_WRITE(reg_elda, i);
5861
5862         for (i = 0; i < eld[2]; i++)
5863                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5864                         return false;
5865
5866         return true;
5867 }
5868
5869 static void g4x_write_eld(struct drm_connector *connector,
5870                           struct drm_crtc *crtc)
5871 {
5872         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5873         uint8_t *eld = connector->eld;
5874         uint32_t eldv;
5875         uint32_t len;
5876         uint32_t i;
5877
5878         i = I915_READ(G4X_AUD_VID_DID);
5879
5880         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5881                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5882         else
5883                 eldv = G4X_ELDV_DEVCTG;
5884
5885         if (intel_eld_uptodate(connector,
5886                                G4X_AUD_CNTL_ST, eldv,
5887                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5888                                G4X_HDMIW_HDMIEDID))
5889                 return;
5890
5891         i = I915_READ(G4X_AUD_CNTL_ST);
5892         i &= ~(eldv | G4X_ELD_ADDR);
5893         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5894         I915_WRITE(G4X_AUD_CNTL_ST, i);
5895
5896         if (!eld[0])
5897                 return;
5898
5899         len = min_t(uint8_t, eld[2], len);
5900         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5901         for (i = 0; i < len; i++)
5902                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5903
5904         i = I915_READ(G4X_AUD_CNTL_ST);
5905         i |= eldv;
5906         I915_WRITE(G4X_AUD_CNTL_ST, i);
5907 }
5908
5909 static void haswell_write_eld(struct drm_connector *connector,
5910                                      struct drm_crtc *crtc)
5911 {
5912         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5913         uint8_t *eld = connector->eld;
5914         struct drm_device *dev = crtc->dev;
5915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5916         uint32_t eldv;
5917         uint32_t i;
5918         int len;
5919         int pipe = to_intel_crtc(crtc)->pipe;
5920         int tmp;
5921
5922         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5923         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5924         int aud_config = HSW_AUD_CFG(pipe);
5925         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5926
5927
5928         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5929
5930         /* Audio output enable */
5931         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5932         tmp = I915_READ(aud_cntrl_st2);
5933         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5934         I915_WRITE(aud_cntrl_st2, tmp);
5935
5936         /* Wait for 1 vertical blank */
5937         intel_wait_for_vblank(dev, pipe);
5938
5939         /* Set ELD valid state */
5940         tmp = I915_READ(aud_cntrl_st2);
5941         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5942         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5943         I915_WRITE(aud_cntrl_st2, tmp);
5944         tmp = I915_READ(aud_cntrl_st2);
5945         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5946
5947         /* Enable HDMI mode */
5948         tmp = I915_READ(aud_config);
5949         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5950         /* clear N_programing_enable and N_value_index */
5951         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5952         I915_WRITE(aud_config, tmp);
5953
5954         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5955
5956         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5957         intel_crtc->eld_vld = true;
5958
5959         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5960                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5961                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5962                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5963         } else
5964                 I915_WRITE(aud_config, 0);
5965
5966         if (intel_eld_uptodate(connector,
5967                                aud_cntrl_st2, eldv,
5968                                aud_cntl_st, IBX_ELD_ADDRESS,
5969                                hdmiw_hdmiedid))
5970                 return;
5971
5972         i = I915_READ(aud_cntrl_st2);
5973         i &= ~eldv;
5974         I915_WRITE(aud_cntrl_st2, i);
5975
5976         if (!eld[0])
5977                 return;
5978
5979         i = I915_READ(aud_cntl_st);
5980         i &= ~IBX_ELD_ADDRESS;
5981         I915_WRITE(aud_cntl_st, i);
5982         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5983         DRM_DEBUG_DRIVER("port num:%d\n", i);
5984
5985         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5986         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5987         for (i = 0; i < len; i++)
5988                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5989
5990         i = I915_READ(aud_cntrl_st2);
5991         i |= eldv;
5992         I915_WRITE(aud_cntrl_st2, i);
5993
5994 }
5995
5996 static void ironlake_write_eld(struct drm_connector *connector,
5997                                      struct drm_crtc *crtc)
5998 {
5999         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6000         uint8_t *eld = connector->eld;
6001         uint32_t eldv;
6002         uint32_t i;
6003         int len;
6004         int hdmiw_hdmiedid;
6005         int aud_config;
6006         int aud_cntl_st;
6007         int aud_cntrl_st2;
6008         int pipe = to_intel_crtc(crtc)->pipe;
6009
6010         if (HAS_PCH_IBX(connector->dev)) {
6011                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6012                 aud_config = IBX_AUD_CFG(pipe);
6013                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6014                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6015         } else {
6016                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6017                 aud_config = CPT_AUD_CFG(pipe);
6018                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6019                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6020         }
6021
6022         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6023
6024         i = I915_READ(aud_cntl_st);
6025         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6026         if (!i) {
6027                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6028                 /* operate blindly on all ports */
6029                 eldv = IBX_ELD_VALIDB;
6030                 eldv |= IBX_ELD_VALIDB << 4;
6031                 eldv |= IBX_ELD_VALIDB << 8;
6032         } else {
6033                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6034                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6035         }
6036
6037         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6038                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6039                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6040                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6041         } else
6042                 I915_WRITE(aud_config, 0);
6043
6044         if (intel_eld_uptodate(connector,
6045                                aud_cntrl_st2, eldv,
6046                                aud_cntl_st, IBX_ELD_ADDRESS,
6047                                hdmiw_hdmiedid))
6048                 return;
6049
6050         i = I915_READ(aud_cntrl_st2);
6051         i &= ~eldv;
6052         I915_WRITE(aud_cntrl_st2, i);
6053
6054         if (!eld[0])
6055                 return;
6056
6057         i = I915_READ(aud_cntl_st);
6058         i &= ~IBX_ELD_ADDRESS;
6059         I915_WRITE(aud_cntl_st, i);
6060
6061         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6062         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6063         for (i = 0; i < len; i++)
6064                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6065
6066         i = I915_READ(aud_cntrl_st2);
6067         i |= eldv;
6068         I915_WRITE(aud_cntrl_st2, i);
6069 }
6070
6071 void intel_write_eld(struct drm_encoder *encoder,
6072                      struct drm_display_mode *mode)
6073 {
6074         struct drm_crtc *crtc = encoder->crtc;
6075         struct drm_connector *connector;
6076         struct drm_device *dev = encoder->dev;
6077         struct drm_i915_private *dev_priv = dev->dev_private;
6078
6079         connector = drm_select_eld(encoder, mode);
6080         if (!connector)
6081                 return;
6082
6083         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6084                          connector->base.id,
6085                          drm_get_connector_name(connector),
6086                          connector->encoder->base.id,
6087                          drm_get_encoder_name(connector->encoder));
6088
6089         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6090
6091         if (dev_priv->display.write_eld)
6092                 dev_priv->display.write_eld(connector, crtc);
6093 }
6094
6095 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6096 void intel_crtc_load_lut(struct drm_crtc *crtc)
6097 {
6098         struct drm_device *dev = crtc->dev;
6099         struct drm_i915_private *dev_priv = dev->dev_private;
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101         int palreg = PALETTE(intel_crtc->pipe);
6102         int i;
6103
6104         /* The clocks have to be on to load the palette. */
6105         if (!crtc->enabled || !intel_crtc->active)
6106                 return;
6107
6108         /* use legacy palette for Ironlake */
6109         if (HAS_PCH_SPLIT(dev))
6110                 palreg = LGC_PALETTE(intel_crtc->pipe);
6111
6112         for (i = 0; i < 256; i++) {
6113                 I915_WRITE(palreg + 4 * i,
6114                            (intel_crtc->lut_r[i] << 16) |
6115                            (intel_crtc->lut_g[i] << 8) |
6116                            intel_crtc->lut_b[i]);
6117         }
6118 }
6119
6120 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6121 {
6122         struct drm_device *dev = crtc->dev;
6123         struct drm_i915_private *dev_priv = dev->dev_private;
6124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125         bool visible = base != 0;
6126         u32 cntl;
6127
6128         if (intel_crtc->cursor_visible == visible)
6129                 return;
6130
6131         cntl = I915_READ(_CURACNTR);
6132         if (visible) {
6133                 /* On these chipsets we can only modify the base whilst
6134                  * the cursor is disabled.
6135                  */
6136                 I915_WRITE(_CURABASE, base);
6137
6138                 cntl &= ~(CURSOR_FORMAT_MASK);
6139                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6140                 cntl |= CURSOR_ENABLE |
6141                         CURSOR_GAMMA_ENABLE |
6142                         CURSOR_FORMAT_ARGB;
6143         } else
6144                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6145         I915_WRITE(_CURACNTR, cntl);
6146
6147         intel_crtc->cursor_visible = visible;
6148 }
6149
6150 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6151 {
6152         struct drm_device *dev = crtc->dev;
6153         struct drm_i915_private *dev_priv = dev->dev_private;
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         int pipe = intel_crtc->pipe;
6156         bool visible = base != 0;
6157
6158         if (intel_crtc->cursor_visible != visible) {
6159                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6160                 if (base) {
6161                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6162                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6163                         cntl |= pipe << 28; /* Connect to correct pipe */
6164                 } else {
6165                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6166                         cntl |= CURSOR_MODE_DISABLE;
6167                 }
6168                 I915_WRITE(CURCNTR(pipe), cntl);
6169
6170                 intel_crtc->cursor_visible = visible;
6171         }
6172         /* and commit changes on next vblank */
6173         I915_WRITE(CURBASE(pipe), base);
6174 }
6175
6176 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6177 {
6178         struct drm_device *dev = crtc->dev;
6179         struct drm_i915_private *dev_priv = dev->dev_private;
6180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181         int pipe = intel_crtc->pipe;
6182         bool visible = base != 0;
6183
6184         if (intel_crtc->cursor_visible != visible) {
6185                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6186                 if (base) {
6187                         cntl &= ~CURSOR_MODE;
6188                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6189                 } else {
6190                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6191                         cntl |= CURSOR_MODE_DISABLE;
6192                 }
6193                 if (IS_HASWELL(dev))
6194                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6195                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6196
6197                 intel_crtc->cursor_visible = visible;
6198         }
6199         /* and commit changes on next vblank */
6200         I915_WRITE(CURBASE_IVB(pipe), base);
6201 }
6202
6203 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6204 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6205                                      bool on)
6206 {
6207         struct drm_device *dev = crtc->dev;
6208         struct drm_i915_private *dev_priv = dev->dev_private;
6209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210         int pipe = intel_crtc->pipe;
6211         int x = intel_crtc->cursor_x;
6212         int y = intel_crtc->cursor_y;
6213         u32 base, pos;
6214         bool visible;
6215
6216         pos = 0;
6217
6218         if (on && crtc->enabled && crtc->fb) {
6219                 base = intel_crtc->cursor_addr;
6220                 if (x > (int) crtc->fb->width)
6221                         base = 0;
6222
6223                 if (y > (int) crtc->fb->height)
6224                         base = 0;
6225         } else
6226                 base = 0;
6227
6228         if (x < 0) {
6229                 if (x + intel_crtc->cursor_width < 0)
6230                         base = 0;
6231
6232                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6233                 x = -x;
6234         }
6235         pos |= x << CURSOR_X_SHIFT;
6236
6237         if (y < 0) {
6238                 if (y + intel_crtc->cursor_height < 0)
6239                         base = 0;
6240
6241                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6242                 y = -y;
6243         }
6244         pos |= y << CURSOR_Y_SHIFT;
6245
6246         visible = base != 0;
6247         if (!visible && !intel_crtc->cursor_visible)
6248                 return;
6249
6250         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6251                 I915_WRITE(CURPOS_IVB(pipe), pos);
6252                 ivb_update_cursor(crtc, base);
6253         } else {
6254                 I915_WRITE(CURPOS(pipe), pos);
6255                 if (IS_845G(dev) || IS_I865G(dev))
6256                         i845_update_cursor(crtc, base);
6257                 else
6258                         i9xx_update_cursor(crtc, base);
6259         }
6260 }
6261
6262 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6263                                  struct drm_file *file,
6264                                  uint32_t handle,
6265                                  uint32_t width, uint32_t height)
6266 {
6267         struct drm_device *dev = crtc->dev;
6268         struct drm_i915_private *dev_priv = dev->dev_private;
6269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270         struct drm_i915_gem_object *obj;
6271         uint32_t addr;
6272         int ret;
6273
6274         /* if we want to turn off the cursor ignore width and height */
6275         if (!handle) {
6276                 DRM_DEBUG_KMS("cursor off\n");
6277                 addr = 0;
6278                 obj = NULL;
6279                 mutex_lock(&dev->struct_mutex);
6280                 goto finish;
6281         }
6282
6283         /* Currently we only support 64x64 cursors */
6284         if (width != 64 || height != 64) {
6285                 DRM_ERROR("we currently only support 64x64 cursors\n");
6286                 return -EINVAL;
6287         }
6288
6289         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6290         if (&obj->base == NULL)
6291                 return -ENOENT;
6292
6293         if (obj->base.size < width * height * 4) {
6294                 DRM_ERROR("buffer is to small\n");
6295                 ret = -ENOMEM;
6296                 goto fail;
6297         }
6298
6299         /* we only need to pin inside GTT if cursor is non-phy */
6300         mutex_lock(&dev->struct_mutex);
6301         if (!dev_priv->info->cursor_needs_physical) {
6302                 if (obj->tiling_mode) {
6303                         DRM_ERROR("cursor cannot be tiled\n");
6304                         ret = -EINVAL;
6305                         goto fail_locked;
6306                 }
6307
6308                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6309                 if (ret) {
6310                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6311                         goto fail_locked;
6312                 }
6313
6314                 ret = i915_gem_object_put_fence(obj);
6315                 if (ret) {
6316                         DRM_ERROR("failed to release fence for cursor");
6317                         goto fail_unpin;
6318                 }
6319
6320                 addr = obj->gtt_offset;
6321         } else {
6322                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6323                 ret = i915_gem_attach_phys_object(dev, obj,
6324                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6325                                                   align);
6326                 if (ret) {
6327                         DRM_ERROR("failed to attach phys object\n");
6328                         goto fail_locked;
6329                 }
6330                 addr = obj->phys_obj->handle->busaddr;
6331         }
6332
6333         if (IS_GEN2(dev))
6334                 I915_WRITE(CURSIZE, (height << 12) | width);
6335
6336  finish:
6337         if (intel_crtc->cursor_bo) {
6338                 if (dev_priv->info->cursor_needs_physical) {
6339                         if (intel_crtc->cursor_bo != obj)
6340                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6341                 } else
6342                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6343                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6344         }
6345
6346         mutex_unlock(&dev->struct_mutex);
6347
6348         intel_crtc->cursor_addr = addr;
6349         intel_crtc->cursor_bo = obj;
6350         intel_crtc->cursor_width = width;
6351         intel_crtc->cursor_height = height;
6352
6353         intel_crtc_update_cursor(crtc, true);
6354
6355         return 0;
6356 fail_unpin:
6357         i915_gem_object_unpin(obj);
6358 fail_locked:
6359         mutex_unlock(&dev->struct_mutex);
6360 fail:
6361         drm_gem_object_unreference_unlocked(&obj->base);
6362         return ret;
6363 }
6364
6365 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6366 {
6367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6368
6369         intel_crtc->cursor_x = x;
6370         intel_crtc->cursor_y = y;
6371
6372         intel_crtc_update_cursor(crtc, true);
6373
6374         return 0;
6375 }
6376
6377 /** Sets the color ramps on behalf of RandR */
6378 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6379                                  u16 blue, int regno)
6380 {
6381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382
6383         intel_crtc->lut_r[regno] = red >> 8;
6384         intel_crtc->lut_g[regno] = green >> 8;
6385         intel_crtc->lut_b[regno] = blue >> 8;
6386 }
6387
6388 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6389                              u16 *blue, int regno)
6390 {
6391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6392
6393         *red = intel_crtc->lut_r[regno] << 8;
6394         *green = intel_crtc->lut_g[regno] << 8;
6395         *blue = intel_crtc->lut_b[regno] << 8;
6396 }
6397
6398 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6399                                  u16 *blue, uint32_t start, uint32_t size)
6400 {
6401         int end = (start + size > 256) ? 256 : start + size, i;
6402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403
6404         for (i = start; i < end; i++) {
6405                 intel_crtc->lut_r[i] = red[i] >> 8;
6406                 intel_crtc->lut_g[i] = green[i] >> 8;
6407                 intel_crtc->lut_b[i] = blue[i] >> 8;
6408         }
6409
6410         intel_crtc_load_lut(crtc);
6411 }
6412
6413 /**
6414  * Get a pipe with a simple mode set on it for doing load-based monitor
6415  * detection.
6416  *
6417  * It will be up to the load-detect code to adjust the pipe as appropriate for
6418  * its requirements.  The pipe will be connected to no other encoders.
6419  *
6420  * Currently this code will only succeed if there is a pipe with no encoders
6421  * configured for it.  In the future, it could choose to temporarily disable
6422  * some outputs to free up a pipe for its use.
6423  *
6424  * \return crtc, or NULL if no pipes are available.
6425  */
6426
6427 /* VESA 640x480x72Hz mode to set on the pipe */
6428 static struct drm_display_mode load_detect_mode = {
6429         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6430                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6431 };
6432
6433 static struct drm_framebuffer *
6434 intel_framebuffer_create(struct drm_device *dev,
6435                          struct drm_mode_fb_cmd2 *mode_cmd,
6436                          struct drm_i915_gem_object *obj)
6437 {
6438         struct intel_framebuffer *intel_fb;
6439         int ret;
6440
6441         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6442         if (!intel_fb) {
6443                 drm_gem_object_unreference_unlocked(&obj->base);
6444                 return ERR_PTR(-ENOMEM);
6445         }
6446
6447         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6448         if (ret) {
6449                 drm_gem_object_unreference_unlocked(&obj->base);
6450                 kfree(intel_fb);
6451                 return ERR_PTR(ret);
6452         }
6453
6454         return &intel_fb->base;
6455 }
6456
6457 static u32
6458 intel_framebuffer_pitch_for_width(int width, int bpp)
6459 {
6460         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6461         return ALIGN(pitch, 64);
6462 }
6463
6464 static u32
6465 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6466 {
6467         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6468         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6469 }
6470
6471 static struct drm_framebuffer *
6472 intel_framebuffer_create_for_mode(struct drm_device *dev,
6473                                   struct drm_display_mode *mode,
6474                                   int depth, int bpp)
6475 {
6476         struct drm_i915_gem_object *obj;
6477         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6478
6479         obj = i915_gem_alloc_object(dev,
6480                                     intel_framebuffer_size_for_mode(mode, bpp));
6481         if (obj == NULL)
6482                 return ERR_PTR(-ENOMEM);
6483
6484         mode_cmd.width = mode->hdisplay;
6485         mode_cmd.height = mode->vdisplay;
6486         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6487                                                                 bpp);
6488         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6489
6490         return intel_framebuffer_create(dev, &mode_cmd, obj);
6491 }
6492
6493 static struct drm_framebuffer *
6494 mode_fits_in_fbdev(struct drm_device *dev,
6495                    struct drm_display_mode *mode)
6496 {
6497         struct drm_i915_private *dev_priv = dev->dev_private;
6498         struct drm_i915_gem_object *obj;
6499         struct drm_framebuffer *fb;
6500
6501         if (dev_priv->fbdev == NULL)
6502                 return NULL;
6503
6504         obj = dev_priv->fbdev->ifb.obj;
6505         if (obj == NULL)
6506                 return NULL;
6507
6508         fb = &dev_priv->fbdev->ifb.base;
6509         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6510                                                                fb->bits_per_pixel))
6511                 return NULL;
6512
6513         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6514                 return NULL;
6515
6516         return fb;
6517 }
6518
6519 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6520                                 struct drm_display_mode *mode,
6521                                 struct intel_load_detect_pipe *old)
6522 {
6523         struct intel_crtc *intel_crtc;
6524         struct intel_encoder *intel_encoder =
6525                 intel_attached_encoder(connector);
6526         struct drm_crtc *possible_crtc;
6527         struct drm_encoder *encoder = &intel_encoder->base;
6528         struct drm_crtc *crtc = NULL;
6529         struct drm_device *dev = encoder->dev;
6530         struct drm_framebuffer *fb;
6531         int i = -1;
6532
6533         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6534                       connector->base.id, drm_get_connector_name(connector),
6535                       encoder->base.id, drm_get_encoder_name(encoder));
6536
6537         /*
6538          * Algorithm gets a little messy:
6539          *
6540          *   - if the connector already has an assigned crtc, use it (but make
6541          *     sure it's on first)
6542          *
6543          *   - try to find the first unused crtc that can drive this connector,
6544          *     and use that if we find one
6545          */
6546
6547         /* See if we already have a CRTC for this connector */
6548         if (encoder->crtc) {
6549                 crtc = encoder->crtc;
6550
6551                 mutex_lock(&crtc->mutex);
6552
6553                 old->dpms_mode = connector->dpms;
6554                 old->load_detect_temp = false;
6555
6556                 /* Make sure the crtc and connector are running */
6557                 if (connector->dpms != DRM_MODE_DPMS_ON)
6558                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6559
6560                 return true;
6561         }
6562
6563         /* Find an unused one (if possible) */
6564         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6565                 i++;
6566                 if (!(encoder->possible_crtcs & (1 << i)))
6567                         continue;
6568                 if (!possible_crtc->enabled) {
6569                         crtc = possible_crtc;
6570                         break;
6571                 }
6572         }
6573
6574         /*
6575          * If we didn't find an unused CRTC, don't use any.
6576          */
6577         if (!crtc) {
6578                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6579                 return false;
6580         }
6581
6582         mutex_lock(&crtc->mutex);
6583         intel_encoder->new_crtc = to_intel_crtc(crtc);
6584         to_intel_connector(connector)->new_encoder = intel_encoder;
6585
6586         intel_crtc = to_intel_crtc(crtc);
6587         old->dpms_mode = connector->dpms;
6588         old->load_detect_temp = true;
6589         old->release_fb = NULL;
6590
6591         if (!mode)
6592                 mode = &load_detect_mode;
6593
6594         /* We need a framebuffer large enough to accommodate all accesses
6595          * that the plane may generate whilst we perform load detection.
6596          * We can not rely on the fbcon either being present (we get called
6597          * during its initialisation to detect all boot displays, or it may
6598          * not even exist) or that it is large enough to satisfy the
6599          * requested mode.
6600          */
6601         fb = mode_fits_in_fbdev(dev, mode);
6602         if (fb == NULL) {
6603                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6604                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6605                 old->release_fb = fb;
6606         } else
6607                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6608         if (IS_ERR(fb)) {
6609                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6610                 mutex_unlock(&crtc->mutex);
6611                 return false;
6612         }
6613
6614         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6615                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6616                 if (old->release_fb)
6617                         old->release_fb->funcs->destroy(old->release_fb);
6618                 mutex_unlock(&crtc->mutex);
6619                 return false;
6620         }
6621
6622         /* let the connector get through one full cycle before testing */
6623         intel_wait_for_vblank(dev, intel_crtc->pipe);
6624         return true;
6625 }
6626
6627 void intel_release_load_detect_pipe(struct drm_connector *connector,
6628                                     struct intel_load_detect_pipe *old)
6629 {
6630         struct intel_encoder *intel_encoder =
6631                 intel_attached_encoder(connector);
6632         struct drm_encoder *encoder = &intel_encoder->base;
6633         struct drm_crtc *crtc = encoder->crtc;
6634
6635         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6636                       connector->base.id, drm_get_connector_name(connector),
6637                       encoder->base.id, drm_get_encoder_name(encoder));
6638
6639         if (old->load_detect_temp) {
6640                 to_intel_connector(connector)->new_encoder = NULL;
6641                 intel_encoder->new_crtc = NULL;
6642                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6643
6644                 if (old->release_fb) {
6645                         drm_framebuffer_unregister_private(old->release_fb);
6646                         drm_framebuffer_unreference(old->release_fb);
6647                 }
6648
6649                 mutex_unlock(&crtc->mutex);
6650                 return;
6651         }
6652
6653         /* Switch crtc and encoder back off if necessary */
6654         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6655                 connector->funcs->dpms(connector, old->dpms_mode);
6656
6657         mutex_unlock(&crtc->mutex);
6658 }
6659
6660 /* Returns the clock of the currently programmed mode of the given pipe. */
6661 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6662 {
6663         struct drm_i915_private *dev_priv = dev->dev_private;
6664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665         int pipe = intel_crtc->pipe;
6666         u32 dpll = I915_READ(DPLL(pipe));
6667         u32 fp;
6668         intel_clock_t clock;
6669
6670         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6671                 fp = I915_READ(FP0(pipe));
6672         else
6673                 fp = I915_READ(FP1(pipe));
6674
6675         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6676         if (IS_PINEVIEW(dev)) {
6677                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6678                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6679         } else {
6680                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6681                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6682         }
6683
6684         if (!IS_GEN2(dev)) {
6685                 if (IS_PINEVIEW(dev))
6686                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6687                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6688                 else
6689                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6690                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6691
6692                 switch (dpll & DPLL_MODE_MASK) {
6693                 case DPLLB_MODE_DAC_SERIAL:
6694                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6695                                 5 : 10;
6696                         break;
6697                 case DPLLB_MODE_LVDS:
6698                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6699                                 7 : 14;
6700                         break;
6701                 default:
6702                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6703                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6704                         return 0;
6705                 }
6706
6707                 /* XXX: Handle the 100Mhz refclk */
6708                 intel_clock(dev, 96000, &clock);
6709         } else {
6710                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6711
6712                 if (is_lvds) {
6713                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6714                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6715                         clock.p2 = 14;
6716
6717                         if ((dpll & PLL_REF_INPUT_MASK) ==
6718                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6719                                 /* XXX: might not be 66MHz */
6720                                 intel_clock(dev, 66000, &clock);
6721                         } else
6722                                 intel_clock(dev, 48000, &clock);
6723                 } else {
6724                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6725                                 clock.p1 = 2;
6726                         else {
6727                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6728                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6729                         }
6730                         if (dpll & PLL_P2_DIVIDE_BY_4)
6731                                 clock.p2 = 4;
6732                         else
6733                                 clock.p2 = 2;
6734
6735                         intel_clock(dev, 48000, &clock);
6736                 }
6737         }
6738
6739         /* XXX: It would be nice to validate the clocks, but we can't reuse
6740          * i830PllIsValid() because it relies on the xf86_config connector
6741          * configuration being accurate, which it isn't necessarily.
6742          */
6743
6744         return clock.dot;
6745 }
6746
6747 /** Returns the currently programmed mode of the given pipe. */
6748 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6749                                              struct drm_crtc *crtc)
6750 {
6751         struct drm_i915_private *dev_priv = dev->dev_private;
6752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6753         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6754         struct drm_display_mode *mode;
6755         int htot = I915_READ(HTOTAL(cpu_transcoder));
6756         int hsync = I915_READ(HSYNC(cpu_transcoder));
6757         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6758         int vsync = I915_READ(VSYNC(cpu_transcoder));
6759
6760         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6761         if (!mode)
6762                 return NULL;
6763
6764         mode->clock = intel_crtc_clock_get(dev, crtc);
6765         mode->hdisplay = (htot & 0xffff) + 1;
6766         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6767         mode->hsync_start = (hsync & 0xffff) + 1;
6768         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6769         mode->vdisplay = (vtot & 0xffff) + 1;
6770         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6771         mode->vsync_start = (vsync & 0xffff) + 1;
6772         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6773
6774         drm_mode_set_name(mode);
6775
6776         return mode;
6777 }
6778
6779 static void intel_increase_pllclock(struct drm_crtc *crtc)
6780 {
6781         struct drm_device *dev = crtc->dev;
6782         drm_i915_private_t *dev_priv = dev->dev_private;
6783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784         int pipe = intel_crtc->pipe;
6785         int dpll_reg = DPLL(pipe);
6786         int dpll;
6787
6788         if (HAS_PCH_SPLIT(dev))
6789                 return;
6790
6791         if (!dev_priv->lvds_downclock_avail)
6792                 return;
6793
6794         dpll = I915_READ(dpll_reg);
6795         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6796                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6797
6798                 assert_panel_unlocked(dev_priv, pipe);
6799
6800                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6801                 I915_WRITE(dpll_reg, dpll);
6802                 intel_wait_for_vblank(dev, pipe);
6803
6804                 dpll = I915_READ(dpll_reg);
6805                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6806                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6807         }
6808 }
6809
6810 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6811 {
6812         struct drm_device *dev = crtc->dev;
6813         drm_i915_private_t *dev_priv = dev->dev_private;
6814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6815
6816         if (HAS_PCH_SPLIT(dev))
6817                 return;
6818
6819         if (!dev_priv->lvds_downclock_avail)
6820                 return;
6821
6822         /*
6823          * Since this is called by a timer, we should never get here in
6824          * the manual case.
6825          */
6826         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6827                 int pipe = intel_crtc->pipe;
6828                 int dpll_reg = DPLL(pipe);
6829                 int dpll;
6830
6831                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6832
6833                 assert_panel_unlocked(dev_priv, pipe);
6834
6835                 dpll = I915_READ(dpll_reg);
6836                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6837                 I915_WRITE(dpll_reg, dpll);
6838                 intel_wait_for_vblank(dev, pipe);
6839                 dpll = I915_READ(dpll_reg);
6840                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6841                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6842         }
6843
6844 }
6845
6846 void intel_mark_busy(struct drm_device *dev)
6847 {
6848         i915_update_gfx_val(dev->dev_private);
6849 }
6850
6851 void intel_mark_idle(struct drm_device *dev)
6852 {
6853         struct drm_crtc *crtc;
6854
6855         if (!i915_powersave)
6856                 return;
6857
6858         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6859                 if (!crtc->fb)
6860                         continue;
6861
6862                 intel_decrease_pllclock(crtc);
6863         }
6864 }
6865
6866 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6867 {
6868         struct drm_device *dev = obj->base.dev;
6869         struct drm_crtc *crtc;
6870
6871         if (!i915_powersave)
6872                 return;
6873
6874         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6875                 if (!crtc->fb)
6876                         continue;
6877
6878                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6879                         intel_increase_pllclock(crtc);
6880         }
6881 }
6882
6883 static void intel_crtc_destroy(struct drm_crtc *crtc)
6884 {
6885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6886         struct drm_device *dev = crtc->dev;
6887         struct intel_unpin_work *work;
6888         unsigned long flags;
6889
6890         spin_lock_irqsave(&dev->event_lock, flags);
6891         work = intel_crtc->unpin_work;
6892         intel_crtc->unpin_work = NULL;
6893         spin_unlock_irqrestore(&dev->event_lock, flags);
6894
6895         if (work) {
6896                 cancel_work_sync(&work->work);
6897                 kfree(work);
6898         }
6899
6900         drm_crtc_cleanup(crtc);
6901
6902         kfree(intel_crtc);
6903 }
6904
6905 static void intel_unpin_work_fn(struct work_struct *__work)
6906 {
6907         struct intel_unpin_work *work =
6908                 container_of(__work, struct intel_unpin_work, work);
6909         struct drm_device *dev = work->crtc->dev;
6910
6911         mutex_lock(&dev->struct_mutex);
6912         intel_unpin_fb_obj(work->old_fb_obj);
6913         drm_gem_object_unreference(&work->pending_flip_obj->base);
6914         drm_gem_object_unreference(&work->old_fb_obj->base);
6915
6916         intel_update_fbc(dev);
6917         mutex_unlock(&dev->struct_mutex);
6918
6919         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6920         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6921
6922         kfree(work);
6923 }
6924
6925 static void do_intel_finish_page_flip(struct drm_device *dev,
6926                                       struct drm_crtc *crtc)
6927 {
6928         drm_i915_private_t *dev_priv = dev->dev_private;
6929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6930         struct intel_unpin_work *work;
6931         struct drm_i915_gem_object *obj;
6932         unsigned long flags;
6933
6934         /* Ignore early vblank irqs */
6935         if (intel_crtc == NULL)
6936                 return;
6937
6938         spin_lock_irqsave(&dev->event_lock, flags);
6939         work = intel_crtc->unpin_work;
6940
6941         /* Ensure we don't miss a work->pending update ... */
6942         smp_rmb();
6943
6944         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6945                 spin_unlock_irqrestore(&dev->event_lock, flags);
6946                 return;
6947         }
6948
6949         /* and that the unpin work is consistent wrt ->pending. */
6950         smp_rmb();
6951
6952         intel_crtc->unpin_work = NULL;
6953
6954         if (work->event)
6955                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6956
6957         drm_vblank_put(dev, intel_crtc->pipe);
6958
6959         spin_unlock_irqrestore(&dev->event_lock, flags);
6960
6961         obj = work->old_fb_obj;
6962
6963         wake_up_all(&dev_priv->pending_flip_queue);
6964
6965         queue_work(dev_priv->wq, &work->work);
6966
6967         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6968 }
6969
6970 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6971 {
6972         drm_i915_private_t *dev_priv = dev->dev_private;
6973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6974
6975         do_intel_finish_page_flip(dev, crtc);
6976 }
6977
6978 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6979 {
6980         drm_i915_private_t *dev_priv = dev->dev_private;
6981         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6982
6983         do_intel_finish_page_flip(dev, crtc);
6984 }
6985
6986 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6987 {
6988         drm_i915_private_t *dev_priv = dev->dev_private;
6989         struct intel_crtc *intel_crtc =
6990                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6991         unsigned long flags;
6992
6993         /* NB: An MMIO update of the plane base pointer will also
6994          * generate a page-flip completion irq, i.e. every modeset
6995          * is also accompanied by a spurious intel_prepare_page_flip().
6996          */
6997         spin_lock_irqsave(&dev->event_lock, flags);
6998         if (intel_crtc->unpin_work)
6999                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7000         spin_unlock_irqrestore(&dev->event_lock, flags);
7001 }
7002
7003 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7004 {
7005         /* Ensure that the work item is consistent when activating it ... */
7006         smp_wmb();
7007         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7008         /* and that it is marked active as soon as the irq could fire. */
7009         smp_wmb();
7010 }
7011
7012 static int intel_gen2_queue_flip(struct drm_device *dev,
7013                                  struct drm_crtc *crtc,
7014                                  struct drm_framebuffer *fb,
7015                                  struct drm_i915_gem_object *obj)
7016 {
7017         struct drm_i915_private *dev_priv = dev->dev_private;
7018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019         u32 flip_mask;
7020         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7021         int ret;
7022
7023         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7024         if (ret)
7025                 goto err;
7026
7027         ret = intel_ring_begin(ring, 6);
7028         if (ret)
7029                 goto err_unpin;
7030
7031         /* Can't queue multiple flips, so wait for the previous
7032          * one to finish before executing the next.
7033          */
7034         if (intel_crtc->plane)
7035                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7036         else
7037                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7038         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7039         intel_ring_emit(ring, MI_NOOP);
7040         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7041                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7042         intel_ring_emit(ring, fb->pitches[0]);
7043         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7044         intel_ring_emit(ring, 0); /* aux display base address, unused */
7045
7046         intel_mark_page_flip_active(intel_crtc);
7047         intel_ring_advance(ring);
7048         return 0;
7049
7050 err_unpin:
7051         intel_unpin_fb_obj(obj);
7052 err:
7053         return ret;
7054 }
7055
7056 static int intel_gen3_queue_flip(struct drm_device *dev,
7057                                  struct drm_crtc *crtc,
7058                                  struct drm_framebuffer *fb,
7059                                  struct drm_i915_gem_object *obj)
7060 {
7061         struct drm_i915_private *dev_priv = dev->dev_private;
7062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7063         u32 flip_mask;
7064         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7065         int ret;
7066
7067         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7068         if (ret)
7069                 goto err;
7070
7071         ret = intel_ring_begin(ring, 6);
7072         if (ret)
7073                 goto err_unpin;
7074
7075         if (intel_crtc->plane)
7076                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7077         else
7078                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7079         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7080         intel_ring_emit(ring, MI_NOOP);
7081         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7082                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7083         intel_ring_emit(ring, fb->pitches[0]);
7084         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7085         intel_ring_emit(ring, MI_NOOP);
7086
7087         intel_mark_page_flip_active(intel_crtc);
7088         intel_ring_advance(ring);
7089         return 0;
7090
7091 err_unpin:
7092         intel_unpin_fb_obj(obj);
7093 err:
7094         return ret;
7095 }
7096
7097 static int intel_gen4_queue_flip(struct drm_device *dev,
7098                                  struct drm_crtc *crtc,
7099                                  struct drm_framebuffer *fb,
7100                                  struct drm_i915_gem_object *obj)
7101 {
7102         struct drm_i915_private *dev_priv = dev->dev_private;
7103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104         uint32_t pf, pipesrc;
7105         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7106         int ret;
7107
7108         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7109         if (ret)
7110                 goto err;
7111
7112         ret = intel_ring_begin(ring, 4);
7113         if (ret)
7114                 goto err_unpin;
7115
7116         /* i965+ uses the linear or tiled offsets from the
7117          * Display Registers (which do not change across a page-flip)
7118          * so we need only reprogram the base address.
7119          */
7120         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7121                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7122         intel_ring_emit(ring, fb->pitches[0]);
7123         intel_ring_emit(ring,
7124                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7125                         obj->tiling_mode);
7126
7127         /* XXX Enabling the panel-fitter across page-flip is so far
7128          * untested on non-native modes, so ignore it for now.
7129          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7130          */
7131         pf = 0;
7132         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7133         intel_ring_emit(ring, pf | pipesrc);
7134
7135         intel_mark_page_flip_active(intel_crtc);
7136         intel_ring_advance(ring);
7137         return 0;
7138
7139 err_unpin:
7140         intel_unpin_fb_obj(obj);
7141 err:
7142         return ret;
7143 }
7144
7145 static int intel_gen6_queue_flip(struct drm_device *dev,
7146                                  struct drm_crtc *crtc,
7147                                  struct drm_framebuffer *fb,
7148                                  struct drm_i915_gem_object *obj)
7149 {
7150         struct drm_i915_private *dev_priv = dev->dev_private;
7151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7152         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7153         uint32_t pf, pipesrc;
7154         int ret;
7155
7156         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7157         if (ret)
7158                 goto err;
7159
7160         ret = intel_ring_begin(ring, 4);
7161         if (ret)
7162                 goto err_unpin;
7163
7164         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7165                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7166         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7167         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7168
7169         /* Contrary to the suggestions in the documentation,
7170          * "Enable Panel Fitter" does not seem to be required when page
7171          * flipping with a non-native mode, and worse causes a normal
7172          * modeset to fail.
7173          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7174          */
7175         pf = 0;
7176         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7177         intel_ring_emit(ring, pf | pipesrc);
7178
7179         intel_mark_page_flip_active(intel_crtc);
7180         intel_ring_advance(ring);
7181         return 0;
7182
7183 err_unpin:
7184         intel_unpin_fb_obj(obj);
7185 err:
7186         return ret;
7187 }
7188
7189 /*
7190  * On gen7 we currently use the blit ring because (in early silicon at least)
7191  * the render ring doesn't give us interrpts for page flip completion, which
7192  * means clients will hang after the first flip is queued.  Fortunately the
7193  * blit ring generates interrupts properly, so use it instead.
7194  */
7195 static int intel_gen7_queue_flip(struct drm_device *dev,
7196                                  struct drm_crtc *crtc,
7197                                  struct drm_framebuffer *fb,
7198                                  struct drm_i915_gem_object *obj)
7199 {
7200         struct drm_i915_private *dev_priv = dev->dev_private;
7201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7203         uint32_t plane_bit = 0;
7204         int ret;
7205
7206         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7207         if (ret)
7208                 goto err;
7209
7210         switch(intel_crtc->plane) {
7211         case PLANE_A:
7212                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7213                 break;
7214         case PLANE_B:
7215                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7216                 break;
7217         case PLANE_C:
7218                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7219                 break;
7220         default:
7221                 WARN_ONCE(1, "unknown plane in flip command\n");
7222                 ret = -ENODEV;
7223                 goto err_unpin;
7224         }
7225
7226         ret = intel_ring_begin(ring, 4);
7227         if (ret)
7228                 goto err_unpin;
7229
7230         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7231         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7232         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7233         intel_ring_emit(ring, (MI_NOOP));
7234
7235         intel_mark_page_flip_active(intel_crtc);
7236         intel_ring_advance(ring);
7237         return 0;
7238
7239 err_unpin:
7240         intel_unpin_fb_obj(obj);
7241 err:
7242         return ret;
7243 }
7244
7245 static int intel_default_queue_flip(struct drm_device *dev,
7246                                     struct drm_crtc *crtc,
7247                                     struct drm_framebuffer *fb,
7248                                     struct drm_i915_gem_object *obj)
7249 {
7250         return -ENODEV;
7251 }
7252
7253 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7254                                 struct drm_framebuffer *fb,
7255                                 struct drm_pending_vblank_event *event)
7256 {
7257         struct drm_device *dev = crtc->dev;
7258         struct drm_i915_private *dev_priv = dev->dev_private;
7259         struct intel_framebuffer *intel_fb;
7260         struct drm_i915_gem_object *obj;
7261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7262         struct intel_unpin_work *work;
7263         unsigned long flags;
7264         int ret;
7265
7266         /* Can't change pixel format via MI display flips. */
7267         if (fb->pixel_format != crtc->fb->pixel_format)
7268                 return -EINVAL;
7269
7270         /*
7271          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7272          * Note that pitch changes could also affect these register.
7273          */
7274         if (INTEL_INFO(dev)->gen > 3 &&
7275             (fb->offsets[0] != crtc->fb->offsets[0] ||
7276              fb->pitches[0] != crtc->fb->pitches[0]))
7277                 return -EINVAL;
7278
7279         work = kzalloc(sizeof *work, GFP_KERNEL);
7280         if (work == NULL)
7281                 return -ENOMEM;
7282
7283         work->event = event;
7284         work->crtc = crtc;
7285         intel_fb = to_intel_framebuffer(crtc->fb);
7286         work->old_fb_obj = intel_fb->obj;
7287         INIT_WORK(&work->work, intel_unpin_work_fn);
7288
7289         ret = drm_vblank_get(dev, intel_crtc->pipe);
7290         if (ret)
7291                 goto free_work;
7292
7293         /* We borrow the event spin lock for protecting unpin_work */
7294         spin_lock_irqsave(&dev->event_lock, flags);
7295         if (intel_crtc->unpin_work) {
7296                 spin_unlock_irqrestore(&dev->event_lock, flags);
7297                 kfree(work);
7298                 drm_vblank_put(dev, intel_crtc->pipe);
7299
7300                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7301                 return -EBUSY;
7302         }
7303         intel_crtc->unpin_work = work;
7304         spin_unlock_irqrestore(&dev->event_lock, flags);
7305
7306         intel_fb = to_intel_framebuffer(fb);
7307         obj = intel_fb->obj;
7308
7309         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7310                 flush_workqueue(dev_priv->wq);
7311
7312         ret = i915_mutex_lock_interruptible(dev);
7313         if (ret)
7314                 goto cleanup;
7315
7316         /* Reference the objects for the scheduled work. */
7317         drm_gem_object_reference(&work->old_fb_obj->base);
7318         drm_gem_object_reference(&obj->base);
7319
7320         crtc->fb = fb;
7321
7322         work->pending_flip_obj = obj;
7323
7324         work->enable_stall_check = true;
7325
7326         atomic_inc(&intel_crtc->unpin_work_count);
7327         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7328
7329         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7330         if (ret)
7331                 goto cleanup_pending;
7332
7333         intel_disable_fbc(dev);
7334         intel_mark_fb_busy(obj);
7335         mutex_unlock(&dev->struct_mutex);
7336
7337         trace_i915_flip_request(intel_crtc->plane, obj);
7338
7339         return 0;
7340
7341 cleanup_pending:
7342         atomic_dec(&intel_crtc->unpin_work_count);
7343         drm_gem_object_unreference(&work->old_fb_obj->base);
7344         drm_gem_object_unreference(&obj->base);
7345         mutex_unlock(&dev->struct_mutex);
7346
7347 cleanup:
7348         spin_lock_irqsave(&dev->event_lock, flags);
7349         intel_crtc->unpin_work = NULL;
7350         spin_unlock_irqrestore(&dev->event_lock, flags);
7351
7352         drm_vblank_put(dev, intel_crtc->pipe);
7353 free_work:
7354         kfree(work);
7355
7356         return ret;
7357 }
7358
7359 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7360         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7361         .load_lut = intel_crtc_load_lut,
7362 };
7363
7364 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7365 {
7366         struct intel_encoder *other_encoder;
7367         struct drm_crtc *crtc = &encoder->new_crtc->base;
7368
7369         if (WARN_ON(!crtc))
7370                 return false;
7371
7372         list_for_each_entry(other_encoder,
7373                             &crtc->dev->mode_config.encoder_list,
7374                             base.head) {
7375
7376                 if (&other_encoder->new_crtc->base != crtc ||
7377                     encoder == other_encoder)
7378                         continue;
7379                 else
7380                         return true;
7381         }
7382
7383         return false;
7384 }
7385
7386 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7387                                   struct drm_crtc *crtc)
7388 {
7389         struct drm_device *dev;
7390         struct drm_crtc *tmp;
7391         int crtc_mask = 1;
7392
7393         WARN(!crtc, "checking null crtc?\n");
7394
7395         dev = crtc->dev;
7396
7397         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7398                 if (tmp == crtc)
7399                         break;
7400                 crtc_mask <<= 1;
7401         }
7402
7403         if (encoder->possible_crtcs & crtc_mask)
7404                 return true;
7405         return false;
7406 }
7407
7408 /**
7409  * intel_modeset_update_staged_output_state
7410  *
7411  * Updates the staged output configuration state, e.g. after we've read out the
7412  * current hw state.
7413  */
7414 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7415 {
7416         struct intel_encoder *encoder;
7417         struct intel_connector *connector;
7418
7419         list_for_each_entry(connector, &dev->mode_config.connector_list,
7420                             base.head) {
7421                 connector->new_encoder =
7422                         to_intel_encoder(connector->base.encoder);
7423         }
7424
7425         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426                             base.head) {
7427                 encoder->new_crtc =
7428                         to_intel_crtc(encoder->base.crtc);
7429         }
7430 }
7431
7432 /**
7433  * intel_modeset_commit_output_state
7434  *
7435  * This function copies the stage display pipe configuration to the real one.
7436  */
7437 static void intel_modeset_commit_output_state(struct drm_device *dev)
7438 {
7439         struct intel_encoder *encoder;
7440         struct intel_connector *connector;
7441
7442         list_for_each_entry(connector, &dev->mode_config.connector_list,
7443                             base.head) {
7444                 connector->base.encoder = &connector->new_encoder->base;
7445         }
7446
7447         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7448                             base.head) {
7449                 encoder->base.crtc = &encoder->new_crtc->base;
7450         }
7451 }
7452
7453 static struct drm_display_mode *
7454 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7455                             struct drm_display_mode *mode)
7456 {
7457         struct drm_device *dev = crtc->dev;
7458         struct drm_display_mode *adjusted_mode;
7459         struct drm_encoder_helper_funcs *encoder_funcs;
7460         struct intel_encoder *encoder;
7461
7462         adjusted_mode = drm_mode_duplicate(dev, mode);
7463         if (!adjusted_mode)
7464                 return ERR_PTR(-ENOMEM);
7465
7466         /* Pass our mode to the connectors and the CRTC to give them a chance to
7467          * adjust it according to limitations or connector properties, and also
7468          * a chance to reject the mode entirely.
7469          */
7470         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7471                             base.head) {
7472
7473                 if (&encoder->new_crtc->base != crtc)
7474                         continue;
7475                 encoder_funcs = encoder->base.helper_private;
7476                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7477                                                 adjusted_mode))) {
7478                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7479                         goto fail;
7480                 }
7481         }
7482
7483         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7484                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7485                 goto fail;
7486         }
7487         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7488
7489         return adjusted_mode;
7490 fail:
7491         drm_mode_destroy(dev, adjusted_mode);
7492         return ERR_PTR(-EINVAL);
7493 }
7494
7495 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7496  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7497 static void
7498 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7499                              unsigned *prepare_pipes, unsigned *disable_pipes)
7500 {
7501         struct intel_crtc *intel_crtc;
7502         struct drm_device *dev = crtc->dev;
7503         struct intel_encoder *encoder;
7504         struct intel_connector *connector;
7505         struct drm_crtc *tmp_crtc;
7506
7507         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7508
7509         /* Check which crtcs have changed outputs connected to them, these need
7510          * to be part of the prepare_pipes mask. We don't (yet) support global
7511          * modeset across multiple crtcs, so modeset_pipes will only have one
7512          * bit set at most. */
7513         list_for_each_entry(connector, &dev->mode_config.connector_list,
7514                             base.head) {
7515                 if (connector->base.encoder == &connector->new_encoder->base)
7516                         continue;
7517
7518                 if (connector->base.encoder) {
7519                         tmp_crtc = connector->base.encoder->crtc;
7520
7521                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7522                 }
7523
7524                 if (connector->new_encoder)
7525                         *prepare_pipes |=
7526                                 1 << connector->new_encoder->new_crtc->pipe;
7527         }
7528
7529         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7530                             base.head) {
7531                 if (encoder->base.crtc == &encoder->new_crtc->base)
7532                         continue;
7533
7534                 if (encoder->base.crtc) {
7535                         tmp_crtc = encoder->base.crtc;
7536
7537                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7538                 }
7539
7540                 if (encoder->new_crtc)
7541                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7542         }
7543
7544         /* Check for any pipes that will be fully disabled ... */
7545         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7546                             base.head) {
7547                 bool used = false;
7548
7549                 /* Don't try to disable disabled crtcs. */
7550                 if (!intel_crtc->base.enabled)
7551                         continue;
7552
7553                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7554                                     base.head) {
7555                         if (encoder->new_crtc == intel_crtc)
7556                                 used = true;
7557                 }
7558
7559                 if (!used)
7560                         *disable_pipes |= 1 << intel_crtc->pipe;
7561         }
7562
7563
7564         /* set_mode is also used to update properties on life display pipes. */
7565         intel_crtc = to_intel_crtc(crtc);
7566         if (crtc->enabled)
7567                 *prepare_pipes |= 1 << intel_crtc->pipe;
7568
7569         /* We only support modeset on one single crtc, hence we need to do that
7570          * only for the passed in crtc iff we change anything else than just
7571          * disable crtcs.
7572          *
7573          * This is actually not true, to be fully compatible with the old crtc
7574          * helper we automatically disable _any_ output (i.e. doesn't need to be
7575          * connected to the crtc we're modesetting on) if it's disconnected.
7576          * Which is a rather nutty api (since changed the output configuration
7577          * without userspace's explicit request can lead to confusion), but
7578          * alas. Hence we currently need to modeset on all pipes we prepare. */
7579         if (*prepare_pipes)
7580                 *modeset_pipes = *prepare_pipes;
7581
7582         /* ... and mask these out. */
7583         *modeset_pipes &= ~(*disable_pipes);
7584         *prepare_pipes &= ~(*disable_pipes);
7585 }
7586
7587 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7588 {
7589         struct drm_encoder *encoder;
7590         struct drm_device *dev = crtc->dev;
7591
7592         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7593                 if (encoder->crtc == crtc)
7594                         return true;
7595
7596         return false;
7597 }
7598
7599 static void
7600 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7601 {
7602         struct intel_encoder *intel_encoder;
7603         struct intel_crtc *intel_crtc;
7604         struct drm_connector *connector;
7605
7606         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7607                             base.head) {
7608                 if (!intel_encoder->base.crtc)
7609                         continue;
7610
7611                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7612
7613                 if (prepare_pipes & (1 << intel_crtc->pipe))
7614                         intel_encoder->connectors_active = false;
7615         }
7616
7617         intel_modeset_commit_output_state(dev);
7618
7619         /* Update computed state. */
7620         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7621                             base.head) {
7622                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7623         }
7624
7625         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7626                 if (!connector->encoder || !connector->encoder->crtc)
7627                         continue;
7628
7629                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7630
7631                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7632                         struct drm_property *dpms_property =
7633                                 dev->mode_config.dpms_property;
7634
7635                         connector->dpms = DRM_MODE_DPMS_ON;
7636                         drm_object_property_set_value(&connector->base,
7637                                                          dpms_property,
7638                                                          DRM_MODE_DPMS_ON);
7639
7640                         intel_encoder = to_intel_encoder(connector->encoder);
7641                         intel_encoder->connectors_active = true;
7642                 }
7643         }
7644
7645 }
7646
7647 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7648         list_for_each_entry((intel_crtc), \
7649                             &(dev)->mode_config.crtc_list, \
7650                             base.head) \
7651                 if (mask & (1 <<(intel_crtc)->pipe)) \
7652
7653 void
7654 intel_modeset_check_state(struct drm_device *dev)
7655 {
7656         struct intel_crtc *crtc;
7657         struct intel_encoder *encoder;
7658         struct intel_connector *connector;
7659
7660         list_for_each_entry(connector, &dev->mode_config.connector_list,
7661                             base.head) {
7662                 /* This also checks the encoder/connector hw state with the
7663                  * ->get_hw_state callbacks. */
7664                 intel_connector_check_state(connector);
7665
7666                 WARN(&connector->new_encoder->base != connector->base.encoder,
7667                      "connector's staged encoder doesn't match current encoder\n");
7668         }
7669
7670         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7671                             base.head) {
7672                 bool enabled = false;
7673                 bool active = false;
7674                 enum pipe pipe, tracked_pipe;
7675
7676                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7677                               encoder->base.base.id,
7678                               drm_get_encoder_name(&encoder->base));
7679
7680                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7681                      "encoder's stage crtc doesn't match current crtc\n");
7682                 WARN(encoder->connectors_active && !encoder->base.crtc,
7683                      "encoder's active_connectors set, but no crtc\n");
7684
7685                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7686                                     base.head) {
7687                         if (connector->base.encoder != &encoder->base)
7688                                 continue;
7689                         enabled = true;
7690                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7691                                 active = true;
7692                 }
7693                 WARN(!!encoder->base.crtc != enabled,
7694                      "encoder's enabled state mismatch "
7695                      "(expected %i, found %i)\n",
7696                      !!encoder->base.crtc, enabled);
7697                 WARN(active && !encoder->base.crtc,
7698                      "active encoder with no crtc\n");
7699
7700                 WARN(encoder->connectors_active != active,
7701                      "encoder's computed active state doesn't match tracked active state "
7702                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7703
7704                 active = encoder->get_hw_state(encoder, &pipe);
7705                 WARN(active != encoder->connectors_active,
7706                      "encoder's hw state doesn't match sw tracking "
7707                      "(expected %i, found %i)\n",
7708                      encoder->connectors_active, active);
7709
7710                 if (!encoder->base.crtc)
7711                         continue;
7712
7713                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7714                 WARN(active && pipe != tracked_pipe,
7715                      "active encoder's pipe doesn't match"
7716                      "(expected %i, found %i)\n",
7717                      tracked_pipe, pipe);
7718
7719         }
7720
7721         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7722                             base.head) {
7723                 bool enabled = false;
7724                 bool active = false;
7725
7726                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7727                               crtc->base.base.id);
7728
7729                 WARN(crtc->active && !crtc->base.enabled,
7730                      "active crtc, but not enabled in sw tracking\n");
7731
7732                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7733                                     base.head) {
7734                         if (encoder->base.crtc != &crtc->base)
7735                                 continue;
7736                         enabled = true;
7737                         if (encoder->connectors_active)
7738                                 active = true;
7739                 }
7740                 WARN(active != crtc->active,
7741                      "crtc's computed active state doesn't match tracked active state "
7742                      "(expected %i, found %i)\n", active, crtc->active);
7743                 WARN(enabled != crtc->base.enabled,
7744                      "crtc's computed enabled state doesn't match tracked enabled state "
7745                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7746
7747                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7748         }
7749 }
7750
7751 int intel_set_mode(struct drm_crtc *crtc,
7752                    struct drm_display_mode *mode,
7753                    int x, int y, struct drm_framebuffer *fb)
7754 {
7755         struct drm_device *dev = crtc->dev;
7756         drm_i915_private_t *dev_priv = dev->dev_private;
7757         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7758         struct intel_crtc *intel_crtc;
7759         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7760         int ret = 0;
7761
7762         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7763         if (!saved_mode)
7764                 return -ENOMEM;
7765         saved_hwmode = saved_mode + 1;
7766
7767         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7768                                      &prepare_pipes, &disable_pipes);
7769
7770         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7771                       modeset_pipes, prepare_pipes, disable_pipes);
7772
7773         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7774                 intel_crtc_disable(&intel_crtc->base);
7775
7776         *saved_hwmode = crtc->hwmode;
7777         *saved_mode = crtc->mode;
7778
7779         /* Hack: Because we don't (yet) support global modeset on multiple
7780          * crtcs, we don't keep track of the new mode for more than one crtc.
7781          * Hence simply check whether any bit is set in modeset_pipes in all the
7782          * pieces of code that are not yet converted to deal with mutliple crtcs
7783          * changing their mode at the same time. */
7784         adjusted_mode = NULL;
7785         if (modeset_pipes) {
7786                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7787                 if (IS_ERR(adjusted_mode)) {
7788                         ret = PTR_ERR(adjusted_mode);
7789                         goto out;
7790                 }
7791         }
7792
7793         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7794                 if (intel_crtc->base.enabled)
7795                         dev_priv->display.crtc_disable(&intel_crtc->base);
7796         }
7797
7798         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7799          * to set it here already despite that we pass it down the callchain.
7800          */
7801         if (modeset_pipes)
7802                 crtc->mode = *mode;
7803
7804         /* Only after disabling all output pipelines that will be changed can we
7805          * update the the output configuration. */
7806         intel_modeset_update_state(dev, prepare_pipes);
7807
7808         if (dev_priv->display.modeset_global_resources)
7809                 dev_priv->display.modeset_global_resources(dev);
7810
7811         /* Set up the DPLL and any encoders state that needs to adjust or depend
7812          * on the DPLL.
7813          */
7814         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7815                 ret = intel_crtc_mode_set(&intel_crtc->base,
7816                                           mode, adjusted_mode,
7817                                           x, y, fb);
7818                 if (ret)
7819                         goto done;
7820         }
7821
7822         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7823         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7824                 dev_priv->display.crtc_enable(&intel_crtc->base);
7825
7826         if (modeset_pipes) {
7827                 /* Store real post-adjustment hardware mode. */
7828                 crtc->hwmode = *adjusted_mode;
7829
7830                 /* Calculate and store various constants which
7831                  * are later needed by vblank and swap-completion
7832                  * timestamping. They are derived from true hwmode.
7833                  */
7834                 drm_calc_timestamping_constants(crtc);
7835         }
7836
7837         /* FIXME: add subpixel order */
7838 done:
7839         drm_mode_destroy(dev, adjusted_mode);
7840         if (ret && crtc->enabled) {
7841                 crtc->hwmode = *saved_hwmode;
7842                 crtc->mode = *saved_mode;
7843         } else {
7844                 intel_modeset_check_state(dev);
7845         }
7846
7847 out:
7848         kfree(saved_mode);
7849         return ret;
7850 }
7851
7852 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7853 {
7854         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7855 }
7856
7857 #undef for_each_intel_crtc_masked
7858
7859 static void intel_set_config_free(struct intel_set_config *config)
7860 {
7861         if (!config)
7862                 return;
7863
7864         kfree(config->save_connector_encoders);
7865         kfree(config->save_encoder_crtcs);
7866         kfree(config);
7867 }
7868
7869 static int intel_set_config_save_state(struct drm_device *dev,
7870                                        struct intel_set_config *config)
7871 {
7872         struct drm_encoder *encoder;
7873         struct drm_connector *connector;
7874         int count;
7875
7876         config->save_encoder_crtcs =
7877                 kcalloc(dev->mode_config.num_encoder,
7878                         sizeof(struct drm_crtc *), GFP_KERNEL);
7879         if (!config->save_encoder_crtcs)
7880                 return -ENOMEM;
7881
7882         config->save_connector_encoders =
7883                 kcalloc(dev->mode_config.num_connector,
7884                         sizeof(struct drm_encoder *), GFP_KERNEL);
7885         if (!config->save_connector_encoders)
7886                 return -ENOMEM;
7887
7888         /* Copy data. Note that driver private data is not affected.
7889          * Should anything bad happen only the expected state is
7890          * restored, not the drivers personal bookkeeping.
7891          */
7892         count = 0;
7893         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7894                 config->save_encoder_crtcs[count++] = encoder->crtc;
7895         }
7896
7897         count = 0;
7898         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7899                 config->save_connector_encoders[count++] = connector->encoder;
7900         }
7901
7902         return 0;
7903 }
7904
7905 static void intel_set_config_restore_state(struct drm_device *dev,
7906                                            struct intel_set_config *config)
7907 {
7908         struct intel_encoder *encoder;
7909         struct intel_connector *connector;
7910         int count;
7911
7912         count = 0;
7913         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7914                 encoder->new_crtc =
7915                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7916         }
7917
7918         count = 0;
7919         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7920                 connector->new_encoder =
7921                         to_intel_encoder(config->save_connector_encoders[count++]);
7922         }
7923 }
7924
7925 static void
7926 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7927                                       struct intel_set_config *config)
7928 {
7929
7930         /* We should be able to check here if the fb has the same properties
7931          * and then just flip_or_move it */
7932         if (set->crtc->fb != set->fb) {
7933                 /* If we have no fb then treat it as a full mode set */
7934                 if (set->crtc->fb == NULL) {
7935                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7936                         config->mode_changed = true;
7937                 } else if (set->fb == NULL) {
7938                         config->mode_changed = true;
7939                 } else if (set->fb->depth != set->crtc->fb->depth) {
7940                         config->mode_changed = true;
7941                 } else if (set->fb->bits_per_pixel !=
7942                            set->crtc->fb->bits_per_pixel) {
7943                         config->mode_changed = true;
7944                 } else
7945                         config->fb_changed = true;
7946         }
7947
7948         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7949                 config->fb_changed = true;
7950
7951         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7952                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7953                 drm_mode_debug_printmodeline(&set->crtc->mode);
7954                 drm_mode_debug_printmodeline(set->mode);
7955                 config->mode_changed = true;
7956         }
7957 }
7958
7959 static int
7960 intel_modeset_stage_output_state(struct drm_device *dev,
7961                                  struct drm_mode_set *set,
7962                                  struct intel_set_config *config)
7963 {
7964         struct drm_crtc *new_crtc;
7965         struct intel_connector *connector;
7966         struct intel_encoder *encoder;
7967         int count, ro;
7968
7969         /* The upper layers ensure that we either disable a crtc or have a list
7970          * of connectors. For paranoia, double-check this. */
7971         WARN_ON(!set->fb && (set->num_connectors != 0));
7972         WARN_ON(set->fb && (set->num_connectors == 0));
7973
7974         count = 0;
7975         list_for_each_entry(connector, &dev->mode_config.connector_list,
7976                             base.head) {
7977                 /* Otherwise traverse passed in connector list and get encoders
7978                  * for them. */
7979                 for (ro = 0; ro < set->num_connectors; ro++) {
7980                         if (set->connectors[ro] == &connector->base) {
7981                                 connector->new_encoder = connector->encoder;
7982                                 break;
7983                         }
7984                 }
7985
7986                 /* If we disable the crtc, disable all its connectors. Also, if
7987                  * the connector is on the changing crtc but not on the new
7988                  * connector list, disable it. */
7989                 if ((!set->fb || ro == set->num_connectors) &&
7990                     connector->base.encoder &&
7991                     connector->base.encoder->crtc == set->crtc) {
7992                         connector->new_encoder = NULL;
7993
7994                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7995                                 connector->base.base.id,
7996                                 drm_get_connector_name(&connector->base));
7997                 }
7998
7999
8000                 if (&connector->new_encoder->base != connector->base.encoder) {
8001                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8002                         config->mode_changed = true;
8003                 }
8004         }
8005         /* connector->new_encoder is now updated for all connectors. */
8006
8007         /* Update crtc of enabled connectors. */
8008         count = 0;
8009         list_for_each_entry(connector, &dev->mode_config.connector_list,
8010                             base.head) {
8011                 if (!connector->new_encoder)
8012                         continue;
8013
8014                 new_crtc = connector->new_encoder->base.crtc;
8015
8016                 for (ro = 0; ro < set->num_connectors; ro++) {
8017                         if (set->connectors[ro] == &connector->base)
8018                                 new_crtc = set->crtc;
8019                 }
8020
8021                 /* Make sure the new CRTC will work with the encoder */
8022                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8023                                            new_crtc)) {
8024                         return -EINVAL;
8025                 }
8026                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8027
8028                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8029                         connector->base.base.id,
8030                         drm_get_connector_name(&connector->base),
8031                         new_crtc->base.id);
8032         }
8033
8034         /* Check for any encoders that needs to be disabled. */
8035         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8036                             base.head) {
8037                 list_for_each_entry(connector,
8038                                     &dev->mode_config.connector_list,
8039                                     base.head) {
8040                         if (connector->new_encoder == encoder) {
8041                                 WARN_ON(!connector->new_encoder->new_crtc);
8042
8043                                 goto next_encoder;
8044                         }
8045                 }
8046                 encoder->new_crtc = NULL;
8047 next_encoder:
8048                 /* Only now check for crtc changes so we don't miss encoders
8049                  * that will be disabled. */
8050                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8051                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8052                         config->mode_changed = true;
8053                 }
8054         }
8055         /* Now we've also updated encoder->new_crtc for all encoders. */
8056
8057         return 0;
8058 }
8059
8060 static int intel_crtc_set_config(struct drm_mode_set *set)
8061 {
8062         struct drm_device *dev;
8063         struct drm_mode_set save_set;
8064         struct intel_set_config *config;
8065         int ret;
8066
8067         BUG_ON(!set);
8068         BUG_ON(!set->crtc);
8069         BUG_ON(!set->crtc->helper_private);
8070
8071         /* Enforce sane interface api - has been abused by the fb helper. */
8072         BUG_ON(!set->mode && set->fb);
8073         BUG_ON(set->fb && set->num_connectors == 0);
8074
8075         if (set->fb) {
8076                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8077                                 set->crtc->base.id, set->fb->base.id,
8078                                 (int)set->num_connectors, set->x, set->y);
8079         } else {
8080                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8081         }
8082
8083         dev = set->crtc->dev;
8084
8085         ret = -ENOMEM;
8086         config = kzalloc(sizeof(*config), GFP_KERNEL);
8087         if (!config)
8088                 goto out_config;
8089
8090         ret = intel_set_config_save_state(dev, config);
8091         if (ret)
8092                 goto out_config;
8093
8094         save_set.crtc = set->crtc;
8095         save_set.mode = &set->crtc->mode;
8096         save_set.x = set->crtc->x;
8097         save_set.y = set->crtc->y;
8098         save_set.fb = set->crtc->fb;
8099
8100         /* Compute whether we need a full modeset, only an fb base update or no
8101          * change at all. In the future we might also check whether only the
8102          * mode changed, e.g. for LVDS where we only change the panel fitter in
8103          * such cases. */
8104         intel_set_config_compute_mode_changes(set, config);
8105
8106         ret = intel_modeset_stage_output_state(dev, set, config);
8107         if (ret)
8108                 goto fail;
8109
8110         if (config->mode_changed) {
8111                 if (set->mode) {
8112                         DRM_DEBUG_KMS("attempting to set mode from"
8113                                         " userspace\n");
8114                         drm_mode_debug_printmodeline(set->mode);
8115                 }
8116
8117                 ret = intel_set_mode(set->crtc, set->mode,
8118                                      set->x, set->y, set->fb);
8119                 if (ret) {
8120                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8121                                   set->crtc->base.id, ret);
8122                         goto fail;
8123                 }
8124         } else if (config->fb_changed) {
8125                 ret = intel_pipe_set_base(set->crtc,
8126                                           set->x, set->y, set->fb);
8127         }
8128
8129         intel_set_config_free(config);
8130
8131         return 0;
8132
8133 fail:
8134         intel_set_config_restore_state(dev, config);
8135
8136         /* Try to restore the config */
8137         if (config->mode_changed &&
8138             intel_set_mode(save_set.crtc, save_set.mode,
8139                            save_set.x, save_set.y, save_set.fb))
8140                 DRM_ERROR("failed to restore config after modeset failure\n");
8141
8142 out_config:
8143         intel_set_config_free(config);
8144         return ret;
8145 }
8146
8147 static const struct drm_crtc_funcs intel_crtc_funcs = {
8148         .cursor_set = intel_crtc_cursor_set,
8149         .cursor_move = intel_crtc_cursor_move,
8150         .gamma_set = intel_crtc_gamma_set,
8151         .set_config = intel_crtc_set_config,
8152         .destroy = intel_crtc_destroy,
8153         .page_flip = intel_crtc_page_flip,
8154 };
8155
8156 static void intel_cpu_pll_init(struct drm_device *dev)
8157 {
8158         if (HAS_DDI(dev))
8159                 intel_ddi_pll_init(dev);
8160 }
8161
8162 static void intel_pch_pll_init(struct drm_device *dev)
8163 {
8164         drm_i915_private_t *dev_priv = dev->dev_private;
8165         int i;
8166
8167         if (dev_priv->num_pch_pll == 0) {
8168                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8169                 return;
8170         }
8171
8172         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8173                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8174                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8175                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8176         }
8177 }
8178
8179 static void intel_crtc_init(struct drm_device *dev, int pipe)
8180 {
8181         drm_i915_private_t *dev_priv = dev->dev_private;
8182         struct intel_crtc *intel_crtc;
8183         int i;
8184
8185         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8186         if (intel_crtc == NULL)
8187                 return;
8188
8189         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8190
8191         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8192         for (i = 0; i < 256; i++) {
8193                 intel_crtc->lut_r[i] = i;
8194                 intel_crtc->lut_g[i] = i;
8195                 intel_crtc->lut_b[i] = i;
8196         }
8197
8198         /* Swap pipes & planes for FBC on pre-965 */
8199         intel_crtc->pipe = pipe;
8200         intel_crtc->plane = pipe;
8201         intel_crtc->cpu_transcoder = pipe;
8202         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8203                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8204                 intel_crtc->plane = !pipe;
8205         }
8206
8207         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8208                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8209         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8210         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8211
8212         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8213
8214         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8215 }
8216
8217 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8218                                 struct drm_file *file)
8219 {
8220         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8221         struct drm_mode_object *drmmode_obj;
8222         struct intel_crtc *crtc;
8223
8224         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8225                 return -ENODEV;
8226
8227         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8228                         DRM_MODE_OBJECT_CRTC);
8229
8230         if (!drmmode_obj) {
8231                 DRM_ERROR("no such CRTC id\n");
8232                 return -EINVAL;
8233         }
8234
8235         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8236         pipe_from_crtc_id->pipe = crtc->pipe;
8237
8238         return 0;
8239 }
8240
8241 static int intel_encoder_clones(struct intel_encoder *encoder)
8242 {
8243         struct drm_device *dev = encoder->base.dev;
8244         struct intel_encoder *source_encoder;
8245         int index_mask = 0;
8246         int entry = 0;
8247
8248         list_for_each_entry(source_encoder,
8249                             &dev->mode_config.encoder_list, base.head) {
8250
8251                 if (encoder == source_encoder)
8252                         index_mask |= (1 << entry);
8253
8254                 /* Intel hw has only one MUX where enocoders could be cloned. */
8255                 if (encoder->cloneable && source_encoder->cloneable)
8256                         index_mask |= (1 << entry);
8257
8258                 entry++;
8259         }
8260
8261         return index_mask;
8262 }
8263
8264 static bool has_edp_a(struct drm_device *dev)
8265 {
8266         struct drm_i915_private *dev_priv = dev->dev_private;
8267
8268         if (!IS_MOBILE(dev))
8269                 return false;
8270
8271         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8272                 return false;
8273
8274         if (IS_GEN5(dev) &&
8275             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8276                 return false;
8277
8278         return true;
8279 }
8280
8281 static void intel_setup_outputs(struct drm_device *dev)
8282 {
8283         struct drm_i915_private *dev_priv = dev->dev_private;
8284         struct intel_encoder *encoder;
8285         bool dpd_is_edp = false;
8286         bool has_lvds;
8287
8288         has_lvds = intel_lvds_init(dev);
8289         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8290                 /* disable the panel fitter on everything but LVDS */
8291                 I915_WRITE(PFIT_CONTROL, 0);
8292         }
8293
8294         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8295                 intel_crt_init(dev);
8296
8297         if (HAS_DDI(dev)) {
8298                 int found;
8299
8300                 /* Haswell uses DDI functions to detect digital outputs */
8301                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8302                 /* DDI A only supports eDP */
8303                 if (found)
8304                         intel_ddi_init(dev, PORT_A);
8305
8306                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8307                  * register */
8308                 found = I915_READ(SFUSE_STRAP);
8309
8310                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8311                         intel_ddi_init(dev, PORT_B);
8312                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8313                         intel_ddi_init(dev, PORT_C);
8314                 if (found & SFUSE_STRAP_DDID_DETECTED)
8315                         intel_ddi_init(dev, PORT_D);
8316         } else if (HAS_PCH_SPLIT(dev)) {
8317                 int found;
8318                 dpd_is_edp = intel_dpd_is_edp(dev);
8319
8320                 if (has_edp_a(dev))
8321                         intel_dp_init(dev, DP_A, PORT_A);
8322
8323                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8324                         /* PCH SDVOB multiplex with HDMIB */
8325                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8326                         if (!found)
8327                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8328                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8329                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8330                 }
8331
8332                 if (I915_READ(HDMIC) & PORT_DETECTED)
8333                         intel_hdmi_init(dev, HDMIC, PORT_C);
8334
8335                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8336                         intel_hdmi_init(dev, HDMID, PORT_D);
8337
8338                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8339                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8340
8341                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8342                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8343         } else if (IS_VALLEYVIEW(dev)) {
8344                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8345                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8346                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8347
8348                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8349                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8350                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8351                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8352                 }
8353
8354                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8355                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8356
8357         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8358                 bool found = false;
8359
8360                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8361                         DRM_DEBUG_KMS("probing SDVOB\n");
8362                         found = intel_sdvo_init(dev, SDVOB, true);
8363                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8364                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8365                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8366                         }
8367
8368                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8369                                 DRM_DEBUG_KMS("probing DP_B\n");
8370                                 intel_dp_init(dev, DP_B, PORT_B);
8371                         }
8372                 }
8373
8374                 /* Before G4X SDVOC doesn't have its own detect register */
8375
8376                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8377                         DRM_DEBUG_KMS("probing SDVOC\n");
8378                         found = intel_sdvo_init(dev, SDVOC, false);
8379                 }
8380
8381                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8382
8383                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8384                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8385                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8386                         }
8387                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8388                                 DRM_DEBUG_KMS("probing DP_C\n");
8389                                 intel_dp_init(dev, DP_C, PORT_C);
8390                         }
8391                 }
8392
8393                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8394                     (I915_READ(DP_D) & DP_DETECTED)) {
8395                         DRM_DEBUG_KMS("probing DP_D\n");
8396                         intel_dp_init(dev, DP_D, PORT_D);
8397                 }
8398         } else if (IS_GEN2(dev))
8399                 intel_dvo_init(dev);
8400
8401         if (SUPPORTS_TV(dev))
8402                 intel_tv_init(dev);
8403
8404         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8405                 encoder->base.possible_crtcs = encoder->crtc_mask;
8406                 encoder->base.possible_clones =
8407                         intel_encoder_clones(encoder);
8408         }
8409
8410         intel_init_pch_refclk(dev);
8411
8412         drm_helper_move_panel_connectors_to_head(dev);
8413 }
8414
8415 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8416 {
8417         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8418
8419         drm_framebuffer_cleanup(fb);
8420         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8421
8422         kfree(intel_fb);
8423 }
8424
8425 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8426                                                 struct drm_file *file,
8427                                                 unsigned int *handle)
8428 {
8429         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8430         struct drm_i915_gem_object *obj = intel_fb->obj;
8431
8432         return drm_gem_handle_create(file, &obj->base, handle);
8433 }
8434
8435 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8436         .destroy = intel_user_framebuffer_destroy,
8437         .create_handle = intel_user_framebuffer_create_handle,
8438 };
8439
8440 int intel_framebuffer_init(struct drm_device *dev,
8441                            struct intel_framebuffer *intel_fb,
8442                            struct drm_mode_fb_cmd2 *mode_cmd,
8443                            struct drm_i915_gem_object *obj)
8444 {
8445         int ret;
8446
8447         if (obj->tiling_mode == I915_TILING_Y) {
8448                 DRM_DEBUG("hardware does not support tiling Y\n");
8449                 return -EINVAL;
8450         }
8451
8452         if (mode_cmd->pitches[0] & 63) {
8453                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8454                           mode_cmd->pitches[0]);
8455                 return -EINVAL;
8456         }
8457
8458         /* FIXME <= Gen4 stride limits are bit unclear */
8459         if (mode_cmd->pitches[0] > 32768) {
8460                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8461                           mode_cmd->pitches[0]);
8462                 return -EINVAL;
8463         }
8464
8465         if (obj->tiling_mode != I915_TILING_NONE &&
8466             mode_cmd->pitches[0] != obj->stride) {
8467                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8468                           mode_cmd->pitches[0], obj->stride);
8469                 return -EINVAL;
8470         }
8471
8472         /* Reject formats not supported by any plane early. */
8473         switch (mode_cmd->pixel_format) {
8474         case DRM_FORMAT_C8:
8475         case DRM_FORMAT_RGB565:
8476         case DRM_FORMAT_XRGB8888:
8477         case DRM_FORMAT_ARGB8888:
8478                 break;
8479         case DRM_FORMAT_XRGB1555:
8480         case DRM_FORMAT_ARGB1555:
8481                 if (INTEL_INFO(dev)->gen > 3) {
8482                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8483                         return -EINVAL;
8484                 }
8485                 break;
8486         case DRM_FORMAT_XBGR8888:
8487         case DRM_FORMAT_ABGR8888:
8488         case DRM_FORMAT_XRGB2101010:
8489         case DRM_FORMAT_ARGB2101010:
8490         case DRM_FORMAT_XBGR2101010:
8491         case DRM_FORMAT_ABGR2101010:
8492                 if (INTEL_INFO(dev)->gen < 4) {
8493                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8494                         return -EINVAL;
8495                 }
8496                 break;
8497         case DRM_FORMAT_YUYV:
8498         case DRM_FORMAT_UYVY:
8499         case DRM_FORMAT_YVYU:
8500         case DRM_FORMAT_VYUY:
8501                 if (INTEL_INFO(dev)->gen < 5) {
8502                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8503                         return -EINVAL;
8504                 }
8505                 break;
8506         default:
8507                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8508                 return -EINVAL;
8509         }
8510
8511         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8512         if (mode_cmd->offsets[0] != 0)
8513                 return -EINVAL;
8514
8515         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8516         intel_fb->obj = obj;
8517
8518         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8519         if (ret) {
8520                 DRM_ERROR("framebuffer init failed %d\n", ret);
8521                 return ret;
8522         }
8523
8524         return 0;
8525 }
8526
8527 static struct drm_framebuffer *
8528 intel_user_framebuffer_create(struct drm_device *dev,
8529                               struct drm_file *filp,
8530                               struct drm_mode_fb_cmd2 *mode_cmd)
8531 {
8532         struct drm_i915_gem_object *obj;
8533
8534         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8535                                                 mode_cmd->handles[0]));
8536         if (&obj->base == NULL)
8537                 return ERR_PTR(-ENOENT);
8538
8539         return intel_framebuffer_create(dev, mode_cmd, obj);
8540 }
8541
8542 static const struct drm_mode_config_funcs intel_mode_funcs = {
8543         .fb_create = intel_user_framebuffer_create,
8544         .output_poll_changed = intel_fb_output_poll_changed,
8545 };
8546
8547 /* Set up chip specific display functions */
8548 static void intel_init_display(struct drm_device *dev)
8549 {
8550         struct drm_i915_private *dev_priv = dev->dev_private;
8551
8552         /* We always want a DPMS function */
8553         if (HAS_DDI(dev)) {
8554                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8555                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8556                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8557                 dev_priv->display.off = haswell_crtc_off;
8558                 dev_priv->display.update_plane = ironlake_update_plane;
8559         } else if (HAS_PCH_SPLIT(dev)) {
8560                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8561                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8562                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8563                 dev_priv->display.off = ironlake_crtc_off;
8564                 dev_priv->display.update_plane = ironlake_update_plane;
8565         } else {
8566                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8567                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8568                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8569                 dev_priv->display.off = i9xx_crtc_off;
8570                 dev_priv->display.update_plane = i9xx_update_plane;
8571         }
8572
8573         /* Returns the core display clock speed */
8574         if (IS_VALLEYVIEW(dev))
8575                 dev_priv->display.get_display_clock_speed =
8576                         valleyview_get_display_clock_speed;
8577         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8578                 dev_priv->display.get_display_clock_speed =
8579                         i945_get_display_clock_speed;
8580         else if (IS_I915G(dev))
8581                 dev_priv->display.get_display_clock_speed =
8582                         i915_get_display_clock_speed;
8583         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8584                 dev_priv->display.get_display_clock_speed =
8585                         i9xx_misc_get_display_clock_speed;
8586         else if (IS_I915GM(dev))
8587                 dev_priv->display.get_display_clock_speed =
8588                         i915gm_get_display_clock_speed;
8589         else if (IS_I865G(dev))
8590                 dev_priv->display.get_display_clock_speed =
8591                         i865_get_display_clock_speed;
8592         else if (IS_I85X(dev))
8593                 dev_priv->display.get_display_clock_speed =
8594                         i855_get_display_clock_speed;
8595         else /* 852, 830 */
8596                 dev_priv->display.get_display_clock_speed =
8597                         i830_get_display_clock_speed;
8598
8599         if (HAS_PCH_SPLIT(dev)) {
8600                 if (IS_GEN5(dev)) {
8601                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8602                         dev_priv->display.write_eld = ironlake_write_eld;
8603                 } else if (IS_GEN6(dev)) {
8604                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8605                         dev_priv->display.write_eld = ironlake_write_eld;
8606                 } else if (IS_IVYBRIDGE(dev)) {
8607                         /* FIXME: detect B0+ stepping and use auto training */
8608                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8609                         dev_priv->display.write_eld = ironlake_write_eld;
8610                         dev_priv->display.modeset_global_resources =
8611                                 ivb_modeset_global_resources;
8612                 } else if (IS_HASWELL(dev)) {
8613                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8614                         dev_priv->display.write_eld = haswell_write_eld;
8615                         dev_priv->display.modeset_global_resources =
8616                                 haswell_modeset_global_resources;
8617                 }
8618         } else if (IS_G4X(dev)) {
8619                 dev_priv->display.write_eld = g4x_write_eld;
8620         }
8621
8622         /* Default just returns -ENODEV to indicate unsupported */
8623         dev_priv->display.queue_flip = intel_default_queue_flip;
8624
8625         switch (INTEL_INFO(dev)->gen) {
8626         case 2:
8627                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8628                 break;
8629
8630         case 3:
8631                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8632                 break;
8633
8634         case 4:
8635         case 5:
8636                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8637                 break;
8638
8639         case 6:
8640                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8641                 break;
8642         case 7:
8643                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8644                 break;
8645         }
8646 }
8647
8648 /*
8649  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8650  * resume, or other times.  This quirk makes sure that's the case for
8651  * affected systems.
8652  */
8653 static void quirk_pipea_force(struct drm_device *dev)
8654 {
8655         struct drm_i915_private *dev_priv = dev->dev_private;
8656
8657         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8658         DRM_INFO("applying pipe a force quirk\n");
8659 }
8660
8661 /*
8662  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8663  */
8664 static void quirk_ssc_force_disable(struct drm_device *dev)
8665 {
8666         struct drm_i915_private *dev_priv = dev->dev_private;
8667         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8668         DRM_INFO("applying lvds SSC disable quirk\n");
8669 }
8670
8671 /*
8672  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8673  * brightness value
8674  */
8675 static void quirk_invert_brightness(struct drm_device *dev)
8676 {
8677         struct drm_i915_private *dev_priv = dev->dev_private;
8678         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8679         DRM_INFO("applying inverted panel brightness quirk\n");
8680 }
8681
8682 struct intel_quirk {
8683         int device;
8684         int subsystem_vendor;
8685         int subsystem_device;
8686         void (*hook)(struct drm_device *dev);
8687 };
8688
8689 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8690 struct intel_dmi_quirk {
8691         void (*hook)(struct drm_device *dev);
8692         const struct dmi_system_id (*dmi_id_list)[];
8693 };
8694
8695 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8696 {
8697         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8698         return 1;
8699 }
8700
8701 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8702         {
8703                 .dmi_id_list = &(const struct dmi_system_id[]) {
8704                         {
8705                                 .callback = intel_dmi_reverse_brightness,
8706                                 .ident = "NCR Corporation",
8707                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8708                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8709                                 },
8710                         },
8711                         { }  /* terminating entry */
8712                 },
8713                 .hook = quirk_invert_brightness,
8714         },
8715 };
8716
8717 static struct intel_quirk intel_quirks[] = {
8718         /* HP Mini needs pipe A force quirk (LP: #322104) */
8719         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8720
8721         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8722         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8723
8724         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8725         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8726
8727         /* 830/845 need to leave pipe A & dpll A up */
8728         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8729         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8730
8731         /* Lenovo U160 cannot use SSC on LVDS */
8732         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8733
8734         /* Sony Vaio Y cannot use SSC on LVDS */
8735         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8736
8737         /* Acer Aspire 5734Z must invert backlight brightness */
8738         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8739
8740         /* Acer/eMachines G725 */
8741         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8742
8743         /* Acer/eMachines e725 */
8744         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8745
8746         /* Acer/Packard Bell NCL20 */
8747         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8748
8749         /* Acer Aspire 4736Z */
8750         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8751 };
8752
8753 static void intel_init_quirks(struct drm_device *dev)
8754 {
8755         struct pci_dev *d = dev->pdev;
8756         int i;
8757
8758         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8759                 struct intel_quirk *q = &intel_quirks[i];
8760
8761                 if (d->device == q->device &&
8762                     (d->subsystem_vendor == q->subsystem_vendor ||
8763                      q->subsystem_vendor == PCI_ANY_ID) &&
8764                     (d->subsystem_device == q->subsystem_device ||
8765                      q->subsystem_device == PCI_ANY_ID))
8766                         q->hook(dev);
8767         }
8768         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8769                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8770                         intel_dmi_quirks[i].hook(dev);
8771         }
8772 }
8773
8774 /* Disable the VGA plane that we never use */
8775 static void i915_disable_vga(struct drm_device *dev)
8776 {
8777         struct drm_i915_private *dev_priv = dev->dev_private;
8778         u8 sr1;
8779         u32 vga_reg = i915_vgacntrl_reg(dev);
8780
8781         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8782         outb(SR01, VGA_SR_INDEX);
8783         sr1 = inb(VGA_SR_DATA);
8784         outb(sr1 | 1<<5, VGA_SR_DATA);
8785         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8786         udelay(300);
8787
8788         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8789         POSTING_READ(vga_reg);
8790 }
8791
8792 void intel_modeset_init_hw(struct drm_device *dev)
8793 {
8794         intel_init_power_well(dev);
8795
8796         intel_prepare_ddi(dev);
8797
8798         intel_init_clock_gating(dev);
8799
8800         mutex_lock(&dev->struct_mutex);
8801         intel_enable_gt_powersave(dev);
8802         mutex_unlock(&dev->struct_mutex);
8803 }
8804
8805 void intel_modeset_init(struct drm_device *dev)
8806 {
8807         struct drm_i915_private *dev_priv = dev->dev_private;
8808         int i, ret;
8809
8810         drm_mode_config_init(dev);
8811
8812         dev->mode_config.min_width = 0;
8813         dev->mode_config.min_height = 0;
8814
8815         dev->mode_config.preferred_depth = 24;
8816         dev->mode_config.prefer_shadow = 1;
8817
8818         dev->mode_config.funcs = &intel_mode_funcs;
8819
8820         intel_init_quirks(dev);
8821
8822         intel_init_pm(dev);
8823
8824         intel_init_display(dev);
8825
8826         if (IS_GEN2(dev)) {
8827                 dev->mode_config.max_width = 2048;
8828                 dev->mode_config.max_height = 2048;
8829         } else if (IS_GEN3(dev)) {
8830                 dev->mode_config.max_width = 4096;
8831                 dev->mode_config.max_height = 4096;
8832         } else {
8833                 dev->mode_config.max_width = 8192;
8834                 dev->mode_config.max_height = 8192;
8835         }
8836         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8837
8838         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8839                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8840
8841         for (i = 0; i < dev_priv->num_pipe; i++) {
8842                 intel_crtc_init(dev, i);
8843                 ret = intel_plane_init(dev, i);
8844                 if (ret)
8845                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8846         }
8847
8848         intel_cpu_pll_init(dev);
8849         intel_pch_pll_init(dev);
8850
8851         /* Just disable it once at startup */
8852         i915_disable_vga(dev);
8853         intel_setup_outputs(dev);
8854
8855         /* Just in case the BIOS is doing something questionable. */
8856         intel_disable_fbc(dev);
8857 }
8858
8859 static void
8860 intel_connector_break_all_links(struct intel_connector *connector)
8861 {
8862         connector->base.dpms = DRM_MODE_DPMS_OFF;
8863         connector->base.encoder = NULL;
8864         connector->encoder->connectors_active = false;
8865         connector->encoder->base.crtc = NULL;
8866 }
8867
8868 static void intel_enable_pipe_a(struct drm_device *dev)
8869 {
8870         struct intel_connector *connector;
8871         struct drm_connector *crt = NULL;
8872         struct intel_load_detect_pipe load_detect_temp;
8873
8874         /* We can't just switch on the pipe A, we need to set things up with a
8875          * proper mode and output configuration. As a gross hack, enable pipe A
8876          * by enabling the load detect pipe once. */
8877         list_for_each_entry(connector,
8878                             &dev->mode_config.connector_list,
8879                             base.head) {
8880                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8881                         crt = &connector->base;
8882                         break;
8883                 }
8884         }
8885
8886         if (!crt)
8887                 return;
8888
8889         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8890                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8891
8892
8893 }
8894
8895 static bool
8896 intel_check_plane_mapping(struct intel_crtc *crtc)
8897 {
8898         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8899         u32 reg, val;
8900
8901         if (dev_priv->num_pipe == 1)
8902                 return true;
8903
8904         reg = DSPCNTR(!crtc->plane);
8905         val = I915_READ(reg);
8906
8907         if ((val & DISPLAY_PLANE_ENABLE) &&
8908             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8909                 return false;
8910
8911         return true;
8912 }
8913
8914 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8915 {
8916         struct drm_device *dev = crtc->base.dev;
8917         struct drm_i915_private *dev_priv = dev->dev_private;
8918         u32 reg;
8919
8920         /* Clear any frame start delays used for debugging left by the BIOS */
8921         reg = PIPECONF(crtc->cpu_transcoder);
8922         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8923
8924         /* We need to sanitize the plane -> pipe mapping first because this will
8925          * disable the crtc (and hence change the state) if it is wrong. Note
8926          * that gen4+ has a fixed plane -> pipe mapping.  */
8927         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8928                 struct intel_connector *connector;
8929                 bool plane;
8930
8931                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8932                               crtc->base.base.id);
8933
8934                 /* Pipe has the wrong plane attached and the plane is active.
8935                  * Temporarily change the plane mapping and disable everything
8936                  * ...  */
8937                 plane = crtc->plane;
8938                 crtc->plane = !plane;
8939                 dev_priv->display.crtc_disable(&crtc->base);
8940                 crtc->plane = plane;
8941
8942                 /* ... and break all links. */
8943                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8944                                     base.head) {
8945                         if (connector->encoder->base.crtc != &crtc->base)
8946                                 continue;
8947
8948                         intel_connector_break_all_links(connector);
8949                 }
8950
8951                 WARN_ON(crtc->active);
8952                 crtc->base.enabled = false;
8953         }
8954
8955         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8956             crtc->pipe == PIPE_A && !crtc->active) {
8957                 /* BIOS forgot to enable pipe A, this mostly happens after
8958                  * resume. Force-enable the pipe to fix this, the update_dpms
8959                  * call below we restore the pipe to the right state, but leave
8960                  * the required bits on. */
8961                 intel_enable_pipe_a(dev);
8962         }
8963
8964         /* Adjust the state of the output pipe according to whether we
8965          * have active connectors/encoders. */
8966         intel_crtc_update_dpms(&crtc->base);
8967
8968         if (crtc->active != crtc->base.enabled) {
8969                 struct intel_encoder *encoder;
8970
8971                 /* This can happen either due to bugs in the get_hw_state
8972                  * functions or because the pipe is force-enabled due to the
8973                  * pipe A quirk. */
8974                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8975                               crtc->base.base.id,
8976                               crtc->base.enabled ? "enabled" : "disabled",
8977                               crtc->active ? "enabled" : "disabled");
8978
8979                 crtc->base.enabled = crtc->active;
8980
8981                 /* Because we only establish the connector -> encoder ->
8982                  * crtc links if something is active, this means the
8983                  * crtc is now deactivated. Break the links. connector
8984                  * -> encoder links are only establish when things are
8985                  *  actually up, hence no need to break them. */
8986                 WARN_ON(crtc->active);
8987
8988                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8989                         WARN_ON(encoder->connectors_active);
8990                         encoder->base.crtc = NULL;
8991                 }
8992         }
8993 }
8994
8995 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8996 {
8997         struct intel_connector *connector;
8998         struct drm_device *dev = encoder->base.dev;
8999
9000         /* We need to check both for a crtc link (meaning that the
9001          * encoder is active and trying to read from a pipe) and the
9002          * pipe itself being active. */
9003         bool has_active_crtc = encoder->base.crtc &&
9004                 to_intel_crtc(encoder->base.crtc)->active;
9005
9006         if (encoder->connectors_active && !has_active_crtc) {
9007                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9008                               encoder->base.base.id,
9009                               drm_get_encoder_name(&encoder->base));
9010
9011                 /* Connector is active, but has no active pipe. This is
9012                  * fallout from our resume register restoring. Disable
9013                  * the encoder manually again. */
9014                 if (encoder->base.crtc) {
9015                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9016                                       encoder->base.base.id,
9017                                       drm_get_encoder_name(&encoder->base));
9018                         encoder->disable(encoder);
9019                 }
9020
9021                 /* Inconsistent output/port/pipe state happens presumably due to
9022                  * a bug in one of the get_hw_state functions. Or someplace else
9023                  * in our code, like the register restore mess on resume. Clamp
9024                  * things to off as a safer default. */
9025                 list_for_each_entry(connector,
9026                                     &dev->mode_config.connector_list,
9027                                     base.head) {
9028                         if (connector->encoder != encoder)
9029                                 continue;
9030
9031                         intel_connector_break_all_links(connector);
9032                 }
9033         }
9034         /* Enabled encoders without active connectors will be fixed in
9035          * the crtc fixup. */
9036 }
9037
9038 void i915_redisable_vga(struct drm_device *dev)
9039 {
9040         struct drm_i915_private *dev_priv = dev->dev_private;
9041         u32 vga_reg = i915_vgacntrl_reg(dev);
9042
9043         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9044                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9045                 i915_disable_vga(dev);
9046         }
9047 }
9048
9049 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9050  * and i915 state tracking structures. */
9051 void intel_modeset_setup_hw_state(struct drm_device *dev,
9052                                   bool force_restore)
9053 {
9054         struct drm_i915_private *dev_priv = dev->dev_private;
9055         enum pipe pipe;
9056         u32 tmp;
9057         struct intel_crtc *crtc;
9058         struct intel_encoder *encoder;
9059         struct intel_connector *connector;
9060
9061         if (HAS_DDI(dev)) {
9062                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9063
9064                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9065                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9066                         case TRANS_DDI_EDP_INPUT_A_ON:
9067                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9068                                 pipe = PIPE_A;
9069                                 break;
9070                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9071                                 pipe = PIPE_B;
9072                                 break;
9073                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9074                                 pipe = PIPE_C;
9075                                 break;
9076                         }
9077
9078                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9079                         crtc->cpu_transcoder = TRANSCODER_EDP;
9080
9081                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9082                                       pipe_name(pipe));
9083                 }
9084         }
9085
9086         for_each_pipe(pipe) {
9087                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9088
9089                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9090                 if (tmp & PIPECONF_ENABLE)
9091                         crtc->active = true;
9092                 else
9093                         crtc->active = false;
9094
9095                 crtc->base.enabled = crtc->active;
9096
9097                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9098                               crtc->base.base.id,
9099                               crtc->active ? "enabled" : "disabled");
9100         }
9101
9102         if (HAS_DDI(dev))
9103                 intel_ddi_setup_hw_pll_state(dev);
9104
9105         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9106                             base.head) {
9107                 pipe = 0;
9108
9109                 if (encoder->get_hw_state(encoder, &pipe)) {
9110                         encoder->base.crtc =
9111                                 dev_priv->pipe_to_crtc_mapping[pipe];
9112                 } else {
9113                         encoder->base.crtc = NULL;
9114                 }
9115
9116                 encoder->connectors_active = false;
9117                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9118                               encoder->base.base.id,
9119                               drm_get_encoder_name(&encoder->base),
9120                               encoder->base.crtc ? "enabled" : "disabled",
9121                               pipe);
9122         }
9123
9124         list_for_each_entry(connector, &dev->mode_config.connector_list,
9125                             base.head) {
9126                 if (connector->get_hw_state(connector)) {
9127                         connector->base.dpms = DRM_MODE_DPMS_ON;
9128                         connector->encoder->connectors_active = true;
9129                         connector->base.encoder = &connector->encoder->base;
9130                 } else {
9131                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9132                         connector->base.encoder = NULL;
9133                 }
9134                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9135                               connector->base.base.id,
9136                               drm_get_connector_name(&connector->base),
9137                               connector->base.encoder ? "enabled" : "disabled");
9138         }
9139
9140         /* HW state is read out, now we need to sanitize this mess. */
9141         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9142                             base.head) {
9143                 intel_sanitize_encoder(encoder);
9144         }
9145
9146         for_each_pipe(pipe) {
9147                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9148                 intel_sanitize_crtc(crtc);
9149         }
9150
9151         if (force_restore) {
9152                 for_each_pipe(pipe) {
9153                         intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9154                 }
9155
9156                 i915_redisable_vga(dev);
9157         } else {
9158                 intel_modeset_update_staged_output_state(dev);
9159         }
9160
9161         intel_modeset_check_state(dev);
9162
9163         drm_mode_config_reset(dev);
9164 }
9165
9166 void intel_modeset_gem_init(struct drm_device *dev)
9167 {
9168         intel_modeset_init_hw(dev);
9169
9170         intel_setup_overlay(dev);
9171
9172         intel_modeset_setup_hw_state(dev, false);
9173 }
9174
9175 void intel_modeset_cleanup(struct drm_device *dev)
9176 {
9177         struct drm_i915_private *dev_priv = dev->dev_private;
9178         struct drm_crtc *crtc;
9179         struct intel_crtc *intel_crtc;
9180
9181         drm_kms_helper_poll_fini(dev);
9182         mutex_lock(&dev->struct_mutex);
9183
9184         intel_unregister_dsm_handler();
9185
9186
9187         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9188                 /* Skip inactive CRTCs */
9189                 if (!crtc->fb)
9190                         continue;
9191
9192                 intel_crtc = to_intel_crtc(crtc);
9193                 intel_increase_pllclock(crtc);
9194         }
9195
9196         intel_disable_fbc(dev);
9197
9198         intel_disable_gt_powersave(dev);
9199
9200         ironlake_teardown_rc6(dev);
9201
9202         if (IS_VALLEYVIEW(dev))
9203                 vlv_init_dpio(dev);
9204
9205         mutex_unlock(&dev->struct_mutex);
9206
9207         /* Disable the irq before mode object teardown, for the irq might
9208          * enqueue unpin/hotplug work. */
9209         drm_irq_uninstall(dev);
9210         cancel_work_sync(&dev_priv->hotplug_work);
9211         cancel_work_sync(&dev_priv->rps.work);
9212
9213         /* flush any delayed tasks or pending work */
9214         flush_scheduled_work();
9215
9216         drm_mode_config_cleanup(dev);
9217
9218         intel_cleanup_overlay(dev);
9219 }
9220
9221 /*
9222  * Return which encoder is currently attached for connector.
9223  */
9224 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9225 {
9226         return &intel_attached_encoder(connector)->base;
9227 }
9228
9229 void intel_connector_attach_encoder(struct intel_connector *connector,
9230                                     struct intel_encoder *encoder)
9231 {
9232         connector->encoder = encoder;
9233         drm_mode_connector_attach_encoder(&connector->base,
9234                                           &encoder->base);
9235 }
9236
9237 /*
9238  * set vga decode state - true == enable VGA decode
9239  */
9240 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9241 {
9242         struct drm_i915_private *dev_priv = dev->dev_private;
9243         u16 gmch_ctrl;
9244
9245         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9246         if (state)
9247                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9248         else
9249                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9250         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9251         return 0;
9252 }
9253
9254 #ifdef CONFIG_DEBUG_FS
9255 #include <linux/seq_file.h>
9256
9257 struct intel_display_error_state {
9258         struct intel_cursor_error_state {
9259                 u32 control;
9260                 u32 position;
9261                 u32 base;
9262                 u32 size;
9263         } cursor[I915_MAX_PIPES];
9264
9265         struct intel_pipe_error_state {
9266                 u32 conf;
9267                 u32 source;
9268
9269                 u32 htotal;
9270                 u32 hblank;
9271                 u32 hsync;
9272                 u32 vtotal;
9273                 u32 vblank;
9274                 u32 vsync;
9275         } pipe[I915_MAX_PIPES];
9276
9277         struct intel_plane_error_state {
9278                 u32 control;
9279                 u32 stride;
9280                 u32 size;
9281                 u32 pos;
9282                 u32 addr;
9283                 u32 surface;
9284                 u32 tile_offset;
9285         } plane[I915_MAX_PIPES];
9286 };
9287
9288 struct intel_display_error_state *
9289 intel_display_capture_error_state(struct drm_device *dev)
9290 {
9291         drm_i915_private_t *dev_priv = dev->dev_private;
9292         struct intel_display_error_state *error;
9293         enum transcoder cpu_transcoder;
9294         int i;
9295
9296         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9297         if (error == NULL)
9298                 return NULL;
9299
9300         for_each_pipe(i) {
9301                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9302
9303                 error->cursor[i].control = I915_READ(CURCNTR(i));
9304                 error->cursor[i].position = I915_READ(CURPOS(i));
9305                 error->cursor[i].base = I915_READ(CURBASE(i));
9306
9307                 error->plane[i].control = I915_READ(DSPCNTR(i));
9308                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9309                 error->plane[i].size = I915_READ(DSPSIZE(i));
9310                 error->plane[i].pos = I915_READ(DSPPOS(i));
9311                 error->plane[i].addr = I915_READ(DSPADDR(i));
9312                 if (INTEL_INFO(dev)->gen >= 4) {
9313                         error->plane[i].surface = I915_READ(DSPSURF(i));
9314                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9315                 }
9316
9317                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9318                 error->pipe[i].source = I915_READ(PIPESRC(i));
9319                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9320                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9321                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9322                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9323                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9324                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9325         }
9326
9327         return error;
9328 }
9329
9330 void
9331 intel_display_print_error_state(struct seq_file *m,
9332                                 struct drm_device *dev,
9333                                 struct intel_display_error_state *error)
9334 {
9335         drm_i915_private_t *dev_priv = dev->dev_private;
9336         int i;
9337
9338         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9339         for_each_pipe(i) {
9340                 seq_printf(m, "Pipe [%d]:\n", i);
9341                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9342                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9343                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9344                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9345                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9346                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9347                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9348                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9349
9350                 seq_printf(m, "Plane [%d]:\n", i);
9351                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9352                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9353                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9354                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9355                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9356                 if (INTEL_INFO(dev)->gen >= 4) {
9357                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9358                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9359                 }
9360
9361                 seq_printf(m, "Cursor [%d]:\n", i);
9362                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9363                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9364                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9365         }
9366 }
9367 #endif