2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_clflush.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 /* Primary plane formats for gen <= 3 */
53 static const uint32_t i8xx_primary_formats[] = {
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_XBGR2101010,
70 static const uint64_t i9xx_format_modifiers[] = {
71 I915_FORMAT_MOD_X_TILED,
72 DRM_FORMAT_MOD_LINEAR,
73 DRM_FORMAT_MOD_INVALID
76 static const uint32_t skl_primary_formats[] = {
83 DRM_FORMAT_XRGB2101010,
84 DRM_FORMAT_XBGR2101010,
91 static const uint32_t skl_pri_planar_formats[] = {
98 DRM_FORMAT_XRGB2101010,
99 DRM_FORMAT_XBGR2101010,
107 static const uint64_t skl_format_modifiers_noccs[] = {
108 I915_FORMAT_MOD_Yf_TILED,
109 I915_FORMAT_MOD_Y_TILED,
110 I915_FORMAT_MOD_X_TILED,
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_INVALID
115 static const uint64_t skl_format_modifiers_ccs[] = {
116 I915_FORMAT_MOD_Yf_TILED_CCS,
117 I915_FORMAT_MOD_Y_TILED_CCS,
118 I915_FORMAT_MOD_Yf_TILED,
119 I915_FORMAT_MOD_Y_TILED,
120 I915_FORMAT_MOD_X_TILED,
121 DRM_FORMAT_MOD_LINEAR,
122 DRM_FORMAT_MOD_INVALID
126 static const uint32_t intel_cursor_formats[] = {
130 static const uint64_t cursor_format_modifiers[] = {
131 DRM_FORMAT_MOD_LINEAR,
132 DRM_FORMAT_MOD_INVALID
135 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
136 struct intel_crtc_state *pipe_config);
137 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
138 struct intel_crtc_state *pipe_config);
140 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
141 struct drm_i915_gem_object *obj,
142 struct drm_mode_fb_cmd2 *mode_cmd);
143 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
145 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
147 struct intel_link_m_n *m_n,
148 struct intel_link_m_n *m2_n2);
149 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
150 static void haswell_set_pipeconf(struct drm_crtc *crtc);
151 static void haswell_set_pipemisc(struct drm_crtc *crtc);
152 static void vlv_prepare_pll(struct intel_crtc *crtc,
153 const struct intel_crtc_state *pipe_config);
154 static void chv_prepare_pll(struct intel_crtc *crtc,
155 const struct intel_crtc_state *pipe_config);
156 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
157 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
158 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
159 struct intel_crtc_state *crtc_state);
160 static void skylake_pfit_enable(struct intel_crtc *crtc);
161 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
162 static void ironlake_pfit_enable(struct intel_crtc *crtc);
163 static void intel_modeset_setup_hw_state(struct drm_device *dev,
164 struct drm_modeset_acquire_ctx *ctx);
165 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
170 } dot, vco, n, m, m1, m2, p, p1;
174 int p2_slow, p2_fast;
178 /* returns HPLL frequency in kHz */
179 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
181 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
183 /* Obtain SKU information */
184 mutex_lock(&dev_priv->sb_lock);
185 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
186 CCK_FUSE_HPLL_FREQ_MASK;
187 mutex_unlock(&dev_priv->sb_lock);
189 return vco_freq[hpll_freq] * 1000;
192 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
193 const char *name, u32 reg, int ref_freq)
198 mutex_lock(&dev_priv->sb_lock);
199 val = vlv_cck_read(dev_priv, reg);
200 mutex_unlock(&dev_priv->sb_lock);
202 divider = val & CCK_FREQUENCY_VALUES;
204 WARN((val & CCK_FREQUENCY_STATUS) !=
205 (divider << CCK_FREQUENCY_STATUS_SHIFT),
206 "%s change in progress\n", name);
208 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
211 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
212 const char *name, u32 reg)
214 if (dev_priv->hpll_freq == 0)
215 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
217 return vlv_get_cck_clock(dev_priv, name, reg,
218 dev_priv->hpll_freq);
221 static void intel_update_czclk(struct drm_i915_private *dev_priv)
223 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
226 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
227 CCK_CZ_CLOCK_CONTROL);
229 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
232 static inline u32 /* units of 100MHz */
233 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
234 const struct intel_crtc_state *pipe_config)
236 if (HAS_DDI(dev_priv))
237 return pipe_config->port_clock; /* SPLL */
239 return dev_priv->fdi_pll_freq;
242 static const struct intel_limit intel_limits_i8xx_dac = {
243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 908000, .max = 1512000 },
245 .n = { .min = 2, .max = 16 },
246 .m = { .min = 96, .max = 140 },
247 .m1 = { .min = 18, .max = 26 },
248 .m2 = { .min = 6, .max = 16 },
249 .p = { .min = 4, .max = 128 },
250 .p1 = { .min = 2, .max = 33 },
251 .p2 = { .dot_limit = 165000,
252 .p2_slow = 4, .p2_fast = 2 },
255 static const struct intel_limit intel_limits_i8xx_dvo = {
256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 908000, .max = 1512000 },
258 .n = { .min = 2, .max = 16 },
259 .m = { .min = 96, .max = 140 },
260 .m1 = { .min = 18, .max = 26 },
261 .m2 = { .min = 6, .max = 16 },
262 .p = { .min = 4, .max = 128 },
263 .p1 = { .min = 2, .max = 33 },
264 .p2 = { .dot_limit = 165000,
265 .p2_slow = 4, .p2_fast = 4 },
268 static const struct intel_limit intel_limits_i8xx_lvds = {
269 .dot = { .min = 25000, .max = 350000 },
270 .vco = { .min = 908000, .max = 1512000 },
271 .n = { .min = 2, .max = 16 },
272 .m = { .min = 96, .max = 140 },
273 .m1 = { .min = 18, .max = 26 },
274 .m2 = { .min = 6, .max = 16 },
275 .p = { .min = 4, .max = 128 },
276 .p1 = { .min = 1, .max = 6 },
277 .p2 = { .dot_limit = 165000,
278 .p2_slow = 14, .p2_fast = 7 },
281 static const struct intel_limit intel_limits_i9xx_sdvo = {
282 .dot = { .min = 20000, .max = 400000 },
283 .vco = { .min = 1400000, .max = 2800000 },
284 .n = { .min = 1, .max = 6 },
285 .m = { .min = 70, .max = 120 },
286 .m1 = { .min = 8, .max = 18 },
287 .m2 = { .min = 3, .max = 7 },
288 .p = { .min = 5, .max = 80 },
289 .p1 = { .min = 1, .max = 8 },
290 .p2 = { .dot_limit = 200000,
291 .p2_slow = 10, .p2_fast = 5 },
294 static const struct intel_limit intel_limits_i9xx_lvds = {
295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1400000, .max = 2800000 },
297 .n = { .min = 1, .max = 6 },
298 .m = { .min = 70, .max = 120 },
299 .m1 = { .min = 8, .max = 18 },
300 .m2 = { .min = 3, .max = 7 },
301 .p = { .min = 7, .max = 98 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 112000,
304 .p2_slow = 14, .p2_fast = 7 },
308 static const struct intel_limit intel_limits_g4x_sdvo = {
309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 1750000, .max = 3500000},
311 .n = { .min = 1, .max = 4 },
312 .m = { .min = 104, .max = 138 },
313 .m1 = { .min = 17, .max = 23 },
314 .m2 = { .min = 5, .max = 11 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 1, .max = 3},
317 .p2 = { .dot_limit = 270000,
323 static const struct intel_limit intel_limits_g4x_hdmi = {
324 .dot = { .min = 22000, .max = 400000 },
325 .vco = { .min = 1750000, .max = 3500000},
326 .n = { .min = 1, .max = 4 },
327 .m = { .min = 104, .max = 138 },
328 .m1 = { .min = 16, .max = 23 },
329 .m2 = { .min = 5, .max = 11 },
330 .p = { .min = 5, .max = 80 },
331 .p1 = { .min = 1, .max = 8},
332 .p2 = { .dot_limit = 165000,
333 .p2_slow = 10, .p2_fast = 5 },
336 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
337 .dot = { .min = 20000, .max = 115000 },
338 .vco = { .min = 1750000, .max = 3500000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 104, .max = 138 },
341 .m1 = { .min = 17, .max = 23 },
342 .m2 = { .min = 5, .max = 11 },
343 .p = { .min = 28, .max = 112 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 0,
346 .p2_slow = 14, .p2_fast = 14
350 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
351 .dot = { .min = 80000, .max = 224000 },
352 .vco = { .min = 1750000, .max = 3500000 },
353 .n = { .min = 1, .max = 3 },
354 .m = { .min = 104, .max = 138 },
355 .m1 = { .min = 17, .max = 23 },
356 .m2 = { .min = 5, .max = 11 },
357 .p = { .min = 14, .max = 42 },
358 .p1 = { .min = 2, .max = 6 },
359 .p2 = { .dot_limit = 0,
360 .p2_slow = 7, .p2_fast = 7
364 static const struct intel_limit intel_limits_pineview_sdvo = {
365 .dot = { .min = 20000, .max = 400000},
366 .vco = { .min = 1700000, .max = 3500000 },
367 /* Pineview's Ncounter is a ring counter */
368 .n = { .min = 3, .max = 6 },
369 .m = { .min = 2, .max = 256 },
370 /* Pineview only has one combined m divider, which we treat as m2. */
371 .m1 = { .min = 0, .max = 0 },
372 .m2 = { .min = 0, .max = 254 },
373 .p = { .min = 5, .max = 80 },
374 .p1 = { .min = 1, .max = 8 },
375 .p2 = { .dot_limit = 200000,
376 .p2_slow = 10, .p2_fast = 5 },
379 static const struct intel_limit intel_limits_pineview_lvds = {
380 .dot = { .min = 20000, .max = 400000 },
381 .vco = { .min = 1700000, .max = 3500000 },
382 .n = { .min = 3, .max = 6 },
383 .m = { .min = 2, .max = 256 },
384 .m1 = { .min = 0, .max = 0 },
385 .m2 = { .min = 0, .max = 254 },
386 .p = { .min = 7, .max = 112 },
387 .p1 = { .min = 1, .max = 8 },
388 .p2 = { .dot_limit = 112000,
389 .p2_slow = 14, .p2_fast = 14 },
392 /* Ironlake / Sandybridge
394 * We calculate clock using (register_value + 2) for N/M1/M2, so here
395 * the range value for them is (actual_value - 2).
397 static const struct intel_limit intel_limits_ironlake_dac = {
398 .dot = { .min = 25000, .max = 350000 },
399 .vco = { .min = 1760000, .max = 3510000 },
400 .n = { .min = 1, .max = 5 },
401 .m = { .min = 79, .max = 127 },
402 .m1 = { .min = 12, .max = 22 },
403 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = 5, .max = 80 },
405 .p1 = { .min = 1, .max = 8 },
406 .p2 = { .dot_limit = 225000,
407 .p2_slow = 10, .p2_fast = 5 },
410 static const struct intel_limit intel_limits_ironlake_single_lvds = {
411 .dot = { .min = 25000, .max = 350000 },
412 .vco = { .min = 1760000, .max = 3510000 },
413 .n = { .min = 1, .max = 3 },
414 .m = { .min = 79, .max = 118 },
415 .m1 = { .min = 12, .max = 22 },
416 .m2 = { .min = 5, .max = 9 },
417 .p = { .min = 28, .max = 112 },
418 .p1 = { .min = 2, .max = 8 },
419 .p2 = { .dot_limit = 225000,
420 .p2_slow = 14, .p2_fast = 14 },
423 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
424 .dot = { .min = 25000, .max = 350000 },
425 .vco = { .min = 1760000, .max = 3510000 },
426 .n = { .min = 1, .max = 3 },
427 .m = { .min = 79, .max = 127 },
428 .m1 = { .min = 12, .max = 22 },
429 .m2 = { .min = 5, .max = 9 },
430 .p = { .min = 14, .max = 56 },
431 .p1 = { .min = 2, .max = 8 },
432 .p2 = { .dot_limit = 225000,
433 .p2_slow = 7, .p2_fast = 7 },
436 /* LVDS 100mhz refclk limits. */
437 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
438 .dot = { .min = 25000, .max = 350000 },
439 .vco = { .min = 1760000, .max = 3510000 },
440 .n = { .min = 1, .max = 2 },
441 .m = { .min = 79, .max = 126 },
442 .m1 = { .min = 12, .max = 22 },
443 .m2 = { .min = 5, .max = 9 },
444 .p = { .min = 28, .max = 112 },
445 .p1 = { .min = 2, .max = 8 },
446 .p2 = { .dot_limit = 225000,
447 .p2_slow = 14, .p2_fast = 14 },
450 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
451 .dot = { .min = 25000, .max = 350000 },
452 .vco = { .min = 1760000, .max = 3510000 },
453 .n = { .min = 1, .max = 3 },
454 .m = { .min = 79, .max = 126 },
455 .m1 = { .min = 12, .max = 22 },
456 .m2 = { .min = 5, .max = 9 },
457 .p = { .min = 14, .max = 42 },
458 .p1 = { .min = 2, .max = 6 },
459 .p2 = { .dot_limit = 225000,
460 .p2_slow = 7, .p2_fast = 7 },
463 static const struct intel_limit intel_limits_vlv = {
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
470 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
471 .vco = { .min = 4000000, .max = 6000000 },
472 .n = { .min = 1, .max = 7 },
473 .m1 = { .min = 2, .max = 3 },
474 .m2 = { .min = 11, .max = 156 },
475 .p1 = { .min = 2, .max = 3 },
476 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
479 static const struct intel_limit intel_limits_chv = {
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
486 .dot = { .min = 25000 * 5, .max = 540000 * 5},
487 .vco = { .min = 4800000, .max = 6480000 },
488 .n = { .min = 1, .max = 1 },
489 .m1 = { .min = 2, .max = 2 },
490 .m2 = { .min = 24 << 22, .max = 175 << 22 },
491 .p1 = { .min = 2, .max = 4 },
492 .p2 = { .p2_slow = 1, .p2_fast = 14 },
495 static const struct intel_limit intel_limits_bxt = {
496 /* FIXME: find real dot limits */
497 .dot = { .min = 0, .max = INT_MAX },
498 .vco = { .min = 4800000, .max = 6700000 },
499 .n = { .min = 1, .max = 1 },
500 .m1 = { .min = 2, .max = 2 },
501 /* FIXME: find real m2 limits */
502 .m2 = { .min = 2 << 22, .max = 255 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 20 },
508 skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)
510 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
514 I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);
516 I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);
520 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
522 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
526 I915_WRITE(CLKGATE_DIS_PSL(pipe),
527 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
529 I915_WRITE(CLKGATE_DIS_PSL(pipe),
530 I915_READ(CLKGATE_DIS_PSL(pipe)) &
531 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
535 needs_modeset(const struct drm_crtc_state *state)
537 return drm_atomic_crtc_needs_modeset(state);
541 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
542 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
543 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
544 * The helpers' return value is the rate of the clock that is fed to the
545 * display engine's pipe which can be the above fast dot clock rate or a
546 * divided-down version of it.
548 /* m1 is reserved as 0 in Pineview, n is a ring counter */
549 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
551 clock->m = clock->m2 + 2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
561 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
563 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
566 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
568 clock->m = i9xx_dpll_compute_m(clock);
569 clock->p = clock->p1 * clock->p2;
570 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
572 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
573 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m1 * clock->m2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 return clock->dot / 5;
590 int chv_calc_dpll_params(int refclk, struct dpll *clock)
592 clock->m = clock->m1 * clock->m2;
593 clock->p = clock->p1 * clock->p2;
594 if (WARN_ON(clock->n == 0 || clock->p == 0))
596 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
598 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
600 return clock->dot / 5;
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 * Returns whether the given set of divisors are valid for a given refclk with
607 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
610 const struct intel_limit *limit,
611 const struct dpll *clock)
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
622 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
623 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
624 if (clock->m1 <= clock->m2)
625 INTELPllInvalid("m1 <= m2\n");
627 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
628 !IS_GEN9_LP(dev_priv)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
647 i9xx_select_p2_div(const struct intel_limit *limit,
648 const struct intel_crtc_state *crtc_state,
651 struct drm_device *dev = crtc_state->base.crtc->dev;
653 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev))
660 return limit->p2.p2_fast;
662 return limit->p2.p2_slow;
664 if (target < limit->p2.dot_limit)
665 return limit->p2.p2_slow;
667 return limit->p2.p2_fast;
672 * Returns a set of divisors for the desired target clock with the given
673 * refclk, or FALSE. The returned values represent the clock equation:
674 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
676 * Target and reference clocks are specified in kHz.
678 * If match_clock is provided, then best_clock P divider must match the P
679 * divider from @match_clock used for LVDS downclocking.
682 i9xx_find_best_dpll(const struct intel_limit *limit,
683 struct intel_crtc_state *crtc_state,
684 int target, int refclk, struct dpll *match_clock,
685 struct dpll *best_clock)
687 struct drm_device *dev = crtc_state->base.crtc->dev;
691 memset(best_clock, 0, sizeof(*best_clock));
693 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
695 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
697 for (clock.m2 = limit->m2.min;
698 clock.m2 <= limit->m2.max; clock.m2++) {
699 if (clock.m2 >= clock.m1)
701 for (clock.n = limit->n.min;
702 clock.n <= limit->n.max; clock.n++) {
703 for (clock.p1 = limit->p1.min;
704 clock.p1 <= limit->p1.max; clock.p1++) {
707 i9xx_calc_dpll_params(refclk, &clock);
708 if (!intel_PLL_is_valid(to_i915(dev),
713 clock.p != match_clock->p)
716 this_err = abs(clock.dot - target);
717 if (this_err < err) {
726 return (err != target);
730 * Returns a set of divisors for the desired target clock with the given
731 * refclk, or FALSE. The returned values represent the clock equation:
732 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
734 * Target and reference clocks are specified in kHz.
736 * If match_clock is provided, then best_clock P divider must match the P
737 * divider from @match_clock used for LVDS downclocking.
740 pnv_find_best_dpll(const struct intel_limit *limit,
741 struct intel_crtc_state *crtc_state,
742 int target, int refclk, struct dpll *match_clock,
743 struct dpll *best_clock)
745 struct drm_device *dev = crtc_state->base.crtc->dev;
749 memset(best_clock, 0, sizeof(*best_clock));
751 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
753 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
755 for (clock.m2 = limit->m2.min;
756 clock.m2 <= limit->m2.max; clock.m2++) {
757 for (clock.n = limit->n.min;
758 clock.n <= limit->n.max; clock.n++) {
759 for (clock.p1 = limit->p1.min;
760 clock.p1 <= limit->p1.max; clock.p1++) {
763 pnv_calc_dpll_params(refclk, &clock);
764 if (!intel_PLL_is_valid(to_i915(dev),
769 clock.p != match_clock->p)
772 this_err = abs(clock.dot - target);
773 if (this_err < err) {
782 return (err != target);
786 * Returns a set of divisors for the desired target clock with the given
787 * refclk, or FALSE. The returned values represent the clock equation:
788 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
790 * Target and reference clocks are specified in kHz.
792 * If match_clock is provided, then best_clock P divider must match the P
793 * divider from @match_clock used for LVDS downclocking.
796 g4x_find_best_dpll(const struct intel_limit *limit,
797 struct intel_crtc_state *crtc_state,
798 int target, int refclk, struct dpll *match_clock,
799 struct dpll *best_clock)
801 struct drm_device *dev = crtc_state->base.crtc->dev;
805 /* approximately equals target * 0.00585 */
806 int err_most = (target >> 8) + (target >> 9);
808 memset(best_clock, 0, sizeof(*best_clock));
810 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
812 max_n = limit->n.max;
813 /* based on hardware requirement, prefer smaller n to precision */
814 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
815 /* based on hardware requirement, prefere larger m1,m2 */
816 for (clock.m1 = limit->m1.max;
817 clock.m1 >= limit->m1.min; clock.m1--) {
818 for (clock.m2 = limit->m2.max;
819 clock.m2 >= limit->m2.min; clock.m2--) {
820 for (clock.p1 = limit->p1.max;
821 clock.p1 >= limit->p1.min; clock.p1--) {
824 i9xx_calc_dpll_params(refclk, &clock);
825 if (!intel_PLL_is_valid(to_i915(dev),
830 this_err = abs(clock.dot - target);
831 if (this_err < err_most) {
845 * Check if the calculated PLL configuration is more optimal compared to the
846 * best configuration and error found so far. Return the calculated error.
848 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
849 const struct dpll *calculated_clock,
850 const struct dpll *best_clock,
851 unsigned int best_error_ppm,
852 unsigned int *error_ppm)
855 * For CHV ignore the error and consider only the P value.
856 * Prefer a bigger P value based on HW requirements.
858 if (IS_CHERRYVIEW(to_i915(dev))) {
861 return calculated_clock->p > best_clock->p;
864 if (WARN_ON_ONCE(!target_freq))
867 *error_ppm = div_u64(1000000ULL *
868 abs(target_freq - calculated_clock->dot),
871 * Prefer a better P value over a better (smaller) error if the error
872 * is small. Ensure this preference for future configurations too by
873 * setting the error to 0.
875 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
881 return *error_ppm + 10 < best_error_ppm;
885 * Returns a set of divisors for the desired target clock with the given
886 * refclk, or FALSE. The returned values represent the clock equation:
887 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
890 vlv_find_best_dpll(const struct intel_limit *limit,
891 struct intel_crtc_state *crtc_state,
892 int target, int refclk, struct dpll *match_clock,
893 struct dpll *best_clock)
895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
896 struct drm_device *dev = crtc->base.dev;
898 unsigned int bestppm = 1000000;
899 /* min update 19.2 MHz */
900 int max_n = min(limit->n.max, refclk / 19200);
903 target *= 5; /* fast clock */
905 memset(best_clock, 0, sizeof(*best_clock));
907 /* based on hardware requirement, prefer smaller n to precision */
908 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
909 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
910 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
911 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
912 clock.p = clock.p1 * clock.p2;
913 /* based on hardware requirement, prefer bigger m1,m2 values */
914 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
917 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
920 vlv_calc_dpll_params(refclk, &clock);
922 if (!intel_PLL_is_valid(to_i915(dev),
927 if (!vlv_PLL_is_optimal(dev, target,
945 * Returns a set of divisors for the desired target clock with the given
946 * refclk, or FALSE. The returned values represent the clock equation:
947 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
950 chv_find_best_dpll(const struct intel_limit *limit,
951 struct intel_crtc_state *crtc_state,
952 int target, int refclk, struct dpll *match_clock,
953 struct dpll *best_clock)
955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
956 struct drm_device *dev = crtc->base.dev;
957 unsigned int best_error_ppm;
962 memset(best_clock, 0, sizeof(*best_clock));
963 best_error_ppm = 1000000;
966 * Based on hardware doc, the n always set to 1, and m1 always
967 * set to 2. If requires to support 200Mhz refclk, we need to
968 * revisit this because n may not 1 anymore.
970 clock.n = 1, clock.m1 = 2;
971 target *= 5; /* fast clock */
973 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
974 for (clock.p2 = limit->p2.p2_fast;
975 clock.p2 >= limit->p2.p2_slow;
976 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
977 unsigned int error_ppm;
979 clock.p = clock.p1 * clock.p2;
981 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
982 clock.n) << 22, refclk * clock.m1);
984 if (m2 > INT_MAX/clock.m1)
989 chv_calc_dpll_params(refclk, &clock);
991 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
994 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
995 best_error_ppm, &error_ppm))
999 best_error_ppm = error_ppm;
1007 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1008 struct dpll *best_clock)
1010 int refclk = 100000;
1011 const struct intel_limit *limit = &intel_limits_bxt;
1013 return chv_find_best_dpll(limit, crtc_state,
1014 target_clock, refclk, NULL, best_clock);
1017 bool intel_crtc_active(struct intel_crtc *crtc)
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1022 * We can ditch the adjusted_mode.crtc_clock check as soon
1023 * as Haswell has gained clock readout/fastboot support.
1025 * We can ditch the crtc->primary->state->fb check as soon as we can
1026 * properly reconstruct framebuffers.
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1032 return crtc->active && crtc->base.primary->state->fb &&
1033 crtc->config->base.adjusted_mode.crtc_clock;
1036 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1039 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1041 return crtc->config->cpu_transcoder;
1044 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1047 i915_reg_t reg = PIPEDSL(pipe);
1051 if (IS_GEN2(dev_priv))
1052 line_mask = DSL_LINEMASK_GEN2;
1054 line_mask = DSL_LINEMASK_GEN3;
1056 line1 = I915_READ(reg) & line_mask;
1058 line2 = I915_READ(reg) & line_mask;
1060 return line1 != line2;
1063 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066 enum pipe pipe = crtc->pipe;
1068 /* Wait for the display line to settle/start moving */
1069 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1070 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1071 pipe_name(pipe), onoff(state));
1074 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1076 wait_for_pipe_scanline_moving(crtc, false);
1079 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1081 wait_for_pipe_scanline_moving(crtc, true);
1085 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1087 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1088 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1090 if (INTEL_GEN(dev_priv) >= 4) {
1091 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1092 i915_reg_t reg = PIPECONF(cpu_transcoder);
1094 /* Wait for the Pipe State to go off */
1095 if (intel_wait_for_register(dev_priv,
1096 reg, I965_PIPECONF_ACTIVE, 0,
1098 WARN(1, "pipe_off wait timed out\n");
1100 intel_wait_for_pipe_scanline_stopped(crtc);
1104 /* Only for pre-ILK configs */
1105 void assert_pll(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1111 val = I915_READ(DPLL(pipe));
1112 cur_state = !!(val & DPLL_VCO_ENABLE);
1113 I915_STATE_WARN(cur_state != state,
1114 "PLL state assertion failure (expected %s, current %s)\n",
1115 onoff(state), onoff(cur_state));
1118 /* XXX: the dsi pll is shared between MIPI DSI ports */
1119 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 mutex_lock(&dev_priv->sb_lock);
1125 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1126 mutex_unlock(&dev_priv->sb_lock);
1128 cur_state = val & DSI_PLL_VCO_EN;
1129 I915_STATE_WARN(cur_state != state,
1130 "DSI PLL state assertion failure (expected %s, current %s)\n",
1131 onoff(state), onoff(cur_state));
1134 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1138 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1141 if (HAS_DDI(dev_priv)) {
1142 /* DDI does not have a specific FDI_TX register */
1143 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1146 u32 val = I915_READ(FDI_TX_CTL(pipe));
1147 cur_state = !!(val & FDI_TX_ENABLE);
1149 I915_STATE_WARN(cur_state != state,
1150 "FDI TX state assertion failure (expected %s, current %s)\n",
1151 onoff(state), onoff(cur_state));
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157 enum pipe pipe, bool state)
1162 val = I915_READ(FDI_RX_CTL(pipe));
1163 cur_state = !!(val & FDI_RX_ENABLE);
1164 I915_STATE_WARN(cur_state != state,
1165 "FDI RX state assertion failure (expected %s, current %s)\n",
1166 onoff(state), onoff(cur_state));
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1176 /* ILK FDI PLL is always enabled */
1177 if (IS_GEN5(dev_priv))
1180 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181 if (HAS_DDI(dev_priv))
1184 val = I915_READ(FDI_TX_CTL(pipe));
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1194 val = I915_READ(FDI_RX_CTL(pipe));
1195 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198 onoff(state), onoff(cur_state));
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1205 enum pipe panel_pipe = INVALID_PIPE;
1208 if (WARN_ON(HAS_DDI(dev_priv)))
1211 if (HAS_PCH_SPLIT(dev_priv)) {
1214 pp_reg = PP_CONTROL(0);
1215 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1218 case PANEL_PORT_SELECT_LVDS:
1219 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1221 case PANEL_PORT_SELECT_DPA:
1222 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1224 case PANEL_PORT_SELECT_DPC:
1225 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1227 case PANEL_PORT_SELECT_DPD:
1228 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1231 MISSING_CASE(port_sel);
1234 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1235 /* presumably write lock depends on pipe, not port select */
1236 pp_reg = PP_CONTROL(pipe);
1241 pp_reg = PP_CONTROL(0);
1242 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1244 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1245 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1248 val = I915_READ(pp_reg);
1249 if (!(val & PANEL_POWER_ON) ||
1250 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1253 I915_STATE_WARN(panel_pipe == pipe && locked,
1254 "panel assertion failure, pipe %c regs locked\n",
1258 void assert_pipe(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, bool state)
1262 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1264 enum intel_display_power_domain power_domain;
1266 /* we keep both pipes enabled on 830 */
1267 if (IS_I830(dev_priv))
1270 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1271 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1272 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1273 cur_state = !!(val & PIPECONF_ENABLE);
1275 intel_display_power_put(dev_priv, power_domain);
1280 I915_STATE_WARN(cur_state != state,
1281 "pipe %c assertion failure (expected %s, current %s)\n",
1282 pipe_name(pipe), onoff(state), onoff(cur_state));
1285 static void assert_plane(struct intel_plane *plane, bool state)
1290 cur_state = plane->get_hw_state(plane, &pipe);
1292 I915_STATE_WARN(cur_state != state,
1293 "%s assertion failure (expected %s, current %s)\n",
1294 plane->base.name, onoff(state), onoff(cur_state));
1297 #define assert_plane_enabled(p) assert_plane(p, true)
1298 #define assert_plane_disabled(p) assert_plane(p, false)
1300 static void assert_planes_disabled(struct intel_crtc *crtc)
1302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1303 struct intel_plane *plane;
1305 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1306 assert_plane_disabled(plane);
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312 drm_crtc_vblank_put(crtc);
1315 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 val = I915_READ(PCH_TRANSCONF(pipe));
1322 enabled = !!(val & TRANS_ENABLE);
1323 I915_STATE_WARN(enabled,
1324 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1329 enum pipe pipe, enum port port,
1332 enum pipe port_pipe;
1335 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1337 I915_STATE_WARN(state && port_pipe == pipe,
1338 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1339 port_name(port), pipe_name(pipe));
1341 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1342 "IBX PCH DP %c still using transcoder B\n",
1346 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, enum port port,
1348 i915_reg_t hdmi_reg)
1350 enum pipe port_pipe;
1353 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1355 I915_STATE_WARN(state && port_pipe == pipe,
1356 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1357 port_name(port), pipe_name(pipe));
1359 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1360 "IBX PCH HDMI %c still using transcoder B\n",
1364 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1367 enum pipe port_pipe;
1369 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1370 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1371 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1373 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1375 "PCH VGA enabled on transcoder %c, should be disabled\n",
1378 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1380 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1383 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1384 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1385 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1388 static void _vlv_enable_pll(struct intel_crtc *crtc,
1389 const struct intel_crtc_state *pipe_config)
1391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1392 enum pipe pipe = crtc->pipe;
1394 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1395 POSTING_READ(DPLL(pipe));
1398 if (intel_wait_for_register(dev_priv,
1403 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1406 static void vlv_enable_pll(struct intel_crtc *crtc,
1407 const struct intel_crtc_state *pipe_config)
1409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1410 enum pipe pipe = crtc->pipe;
1412 assert_pipe_disabled(dev_priv, pipe);
1414 /* PLL is protected by panel, make sure we can write it */
1415 assert_panel_unlocked(dev_priv, pipe);
1417 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1418 _vlv_enable_pll(crtc, pipe_config);
1420 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(pipe));
1425 static void _chv_enable_pll(struct intel_crtc *crtc,
1426 const struct intel_crtc_state *pipe_config)
1428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 enum pipe pipe = crtc->pipe;
1430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1433 mutex_lock(&dev_priv->sb_lock);
1435 /* Enable back the 10bit clock to display controller */
1436 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1437 tmp |= DPIO_DCLKP_EN;
1438 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1440 mutex_unlock(&dev_priv->sb_lock);
1443 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1448 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1450 /* Check PLL is locked */
1451 if (intel_wait_for_register(dev_priv,
1452 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1454 DRM_ERROR("PLL %d failed to lock\n", pipe);
1457 static void chv_enable_pll(struct intel_crtc *crtc,
1458 const struct intel_crtc_state *pipe_config)
1460 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1461 enum pipe pipe = crtc->pipe;
1463 assert_pipe_disabled(dev_priv, pipe);
1465 /* PLL is protected by panel, make sure we can write it */
1466 assert_panel_unlocked(dev_priv, pipe);
1468 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1469 _chv_enable_pll(crtc, pipe_config);
1471 if (pipe != PIPE_A) {
1473 * WaPixelRepeatModeFixForC0:chv
1475 * DPLLCMD is AWOL. Use chicken bits to propagate
1476 * the value from DPLLBMD to either pipe B or C.
1478 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1479 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1480 I915_WRITE(CBR4_VLV, 0);
1481 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1484 * DPLLB VGA mode also seems to cause problems.
1485 * We should always have it disabled.
1487 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1489 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1490 POSTING_READ(DPLL_MD(pipe));
1494 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1496 struct intel_crtc *crtc;
1499 for_each_intel_crtc(&dev_priv->drm, crtc) {
1500 count += crtc->base.state->active &&
1501 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1507 static void i9xx_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_state *crtc_state)
1510 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511 i915_reg_t reg = DPLL(crtc->pipe);
1512 u32 dpll = crtc_state->dpll_hw_state.dpll;
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1517 /* PLL is protected by panel, make sure we can write it */
1518 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1519 assert_panel_unlocked(dev_priv, crtc->pipe);
1521 /* Enable DVO 2x clock on both PLLs if necessary */
1522 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1524 * It appears to be important that we don't enable this
1525 * for the current pipe before otherwise configuring the
1526 * PLL. No idea how this should be handled if multiple
1527 * DVO outputs are enabled simultaneosly.
1529 dpll |= DPLL_DVO_2X_MODE;
1530 I915_WRITE(DPLL(!crtc->pipe),
1531 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1535 * Apparently we need to have VGA mode enabled prior to changing
1536 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1537 * dividers, even though the register value does change.
1541 I915_WRITE(reg, dpll);
1543 /* Wait for the clocks to stabilize. */
1547 if (INTEL_GEN(dev_priv) >= 4) {
1548 I915_WRITE(DPLL_MD(crtc->pipe),
1549 crtc_state->dpll_hw_state.dpll_md);
1551 /* The pixel multiplier can only be updated once the
1552 * DPLL is enabled and the clocks are stable.
1554 * So write it again.
1556 I915_WRITE(reg, dpll);
1559 /* We do this three times for luck */
1560 for (i = 0; i < 3; i++) {
1561 I915_WRITE(reg, dpll);
1563 udelay(150); /* wait for warmup */
1567 static void i9xx_disable_pll(struct intel_crtc *crtc)
1569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1570 enum pipe pipe = crtc->pipe;
1572 /* Disable DVO 2x clock on both PLLs if necessary */
1573 if (IS_I830(dev_priv) &&
1574 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1575 !intel_num_dvo_pipes(dev_priv)) {
1576 I915_WRITE(DPLL(PIPE_B),
1577 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1578 I915_WRITE(DPLL(PIPE_A),
1579 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1582 /* Don't disable pipe or pipe PLLs if needed */
1583 if (IS_I830(dev_priv))
1586 /* Make sure the pipe isn't still relying on us */
1587 assert_pipe_disabled(dev_priv, pipe);
1589 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1590 POSTING_READ(DPLL(pipe));
1593 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1597 /* Make sure the pipe isn't still relying on us */
1598 assert_pipe_disabled(dev_priv, pipe);
1600 val = DPLL_INTEGRATED_REF_CLK_VLV |
1601 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1603 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1605 I915_WRITE(DPLL(pipe), val);
1606 POSTING_READ(DPLL(pipe));
1609 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1611 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1614 /* Make sure the pipe isn't still relying on us */
1615 assert_pipe_disabled(dev_priv, pipe);
1617 val = DPLL_SSC_REF_CLK_CHV |
1618 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1620 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1622 I915_WRITE(DPLL(pipe), val);
1623 POSTING_READ(DPLL(pipe));
1625 mutex_lock(&dev_priv->sb_lock);
1627 /* Disable 10bit clock to display controller */
1628 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1629 val &= ~DPIO_DCLKP_EN;
1630 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1632 mutex_unlock(&dev_priv->sb_lock);
1635 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1636 struct intel_digital_port *dport,
1637 unsigned int expected_mask)
1640 i915_reg_t dpll_reg;
1642 switch (dport->base.port) {
1644 port_mask = DPLL_PORTB_READY_MASK;
1648 port_mask = DPLL_PORTC_READY_MASK;
1650 expected_mask <<= 4;
1653 port_mask = DPLL_PORTD_READY_MASK;
1654 dpll_reg = DPIO_PHY_STATUS;
1660 if (intel_wait_for_register(dev_priv,
1661 dpll_reg, port_mask, expected_mask,
1663 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1664 port_name(dport->base.port),
1665 I915_READ(dpll_reg) & port_mask, expected_mask);
1668 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1671 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1674 uint32_t val, pipeconf_val;
1676 /* Make sure PCH DPLL is enabled */
1677 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1679 /* FDI must be feeding us bits for PCH ports */
1680 assert_fdi_tx_enabled(dev_priv, pipe);
1681 assert_fdi_rx_enabled(dev_priv, pipe);
1683 if (HAS_PCH_CPT(dev_priv)) {
1684 /* Workaround: Set the timing override bit before enabling the
1685 * pch transcoder. */
1686 reg = TRANS_CHICKEN2(pipe);
1687 val = I915_READ(reg);
1688 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689 I915_WRITE(reg, val);
1692 reg = PCH_TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1696 if (HAS_PCH_IBX(dev_priv)) {
1698 * Make the BPC in transcoder be consistent with
1699 * that in pipeconf reg. For HDMI we must use 8bpc
1700 * here for both 8bpc and 12bpc.
1702 val &= ~PIPECONF_BPC_MASK;
1703 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1704 val |= PIPECONF_8BPC;
1706 val |= pipeconf_val & PIPECONF_BPC_MASK;
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711 if (HAS_PCH_IBX(dev_priv) &&
1712 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1715 val |= TRANS_INTERLACED;
1717 val |= TRANS_PROGRESSIVE;
1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (intel_wait_for_register(dev_priv,
1721 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1723 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1726 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1727 enum transcoder cpu_transcoder)
1729 u32 val, pipeconf_val;
1731 /* FDI must be feeding us bits for PCH ports */
1732 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1733 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1735 /* Workaround: set timing override bit. */
1736 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1737 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1741 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1743 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1744 PIPECONF_INTERLACED_ILK)
1745 val |= TRANS_INTERLACED;
1747 val |= TRANS_PROGRESSIVE;
1749 I915_WRITE(LPT_TRANSCONF, val);
1750 if (intel_wait_for_register(dev_priv,
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1771 reg = PCH_TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (intel_wait_for_register(dev_priv,
1777 reg, TRANS_STATE_ENABLE, 0,
1779 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1781 if (HAS_PCH_CPT(dev_priv)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1790 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1794 val = I915_READ(LPT_TRANSCONF);
1795 val &= ~TRANS_ENABLE;
1796 I915_WRITE(LPT_TRANSCONF, val);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (intel_wait_for_register(dev_priv,
1799 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1801 DRM_ERROR("Failed to disable PCH transcoder\n");
1803 /* Workaround: clear timing override bit. */
1804 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1805 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1806 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1809 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1813 if (HAS_PCH_LPT(dev_priv))
1819 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1821 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1824 enum pipe pipe = crtc->pipe;
1828 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1830 assert_planes_disabled(crtc);
1833 * A pipe without a PLL won't actually be able to drive bits from
1834 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1837 if (HAS_GMCH_DISPLAY(dev_priv)) {
1838 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1839 assert_dsi_pll_enabled(dev_priv);
1841 assert_pll_enabled(dev_priv, pipe);
1843 if (new_crtc_state->has_pch_encoder) {
1844 /* if driving the PCH, we need FDI enabled */
1845 assert_fdi_rx_pll_enabled(dev_priv,
1846 intel_crtc_pch_transcoder(crtc));
1847 assert_fdi_tx_pll_enabled(dev_priv,
1848 (enum pipe) cpu_transcoder);
1850 /* FIXME: assert CPU port conditions for SNB+ */
1853 reg = PIPECONF(cpu_transcoder);
1854 val = I915_READ(reg);
1855 if (val & PIPECONF_ENABLE) {
1856 /* we keep both pipes enabled on 830 */
1857 WARN_ON(!IS_I830(dev_priv));
1861 I915_WRITE(reg, val | PIPECONF_ENABLE);
1865 * Until the pipe starts PIPEDSL reads will return a stale value,
1866 * which causes an apparent vblank timestamp jump when PIPEDSL
1867 * resets to its proper value. That also messes up the frame count
1868 * when it's derived from the timestamps. So let's wait for the
1869 * pipe to start properly before we call drm_crtc_vblank_on()
1871 if (dev_priv->drm.max_vblank_count == 0)
1872 intel_wait_for_pipe_scanline_moving(crtc);
1875 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1877 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1879 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1880 enum pipe pipe = crtc->pipe;
1884 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1887 * Make sure planes won't keep trying to pump pixels to us,
1888 * or we might hang the display.
1890 assert_planes_disabled(crtc);
1892 reg = PIPECONF(cpu_transcoder);
1893 val = I915_READ(reg);
1894 if ((val & PIPECONF_ENABLE) == 0)
1898 * Double wide has implications for planes
1899 * so best keep it disabled when not needed.
1901 if (old_crtc_state->double_wide)
1902 val &= ~PIPECONF_DOUBLE_WIDE;
1904 /* Don't disable pipe or pipe PLLs if needed */
1905 if (!IS_I830(dev_priv))
1906 val &= ~PIPECONF_ENABLE;
1908 I915_WRITE(reg, val);
1909 if ((val & PIPECONF_ENABLE) == 0)
1910 intel_wait_for_pipe_off(old_crtc_state);
1913 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1915 return IS_GEN2(dev_priv) ? 2048 : 4096;
1919 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1921 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1922 unsigned int cpp = fb->format->cpp[plane];
1924 switch (fb->modifier) {
1925 case DRM_FORMAT_MOD_LINEAR:
1927 case I915_FORMAT_MOD_X_TILED:
1928 if (IS_GEN2(dev_priv))
1932 case I915_FORMAT_MOD_Y_TILED_CCS:
1936 case I915_FORMAT_MOD_Y_TILED:
1937 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1941 case I915_FORMAT_MOD_Yf_TILED_CCS:
1945 case I915_FORMAT_MOD_Yf_TILED:
1961 MISSING_CASE(fb->modifier);
1967 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1969 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1972 return intel_tile_size(to_i915(fb->dev)) /
1973 intel_tile_width_bytes(fb, plane);
1976 /* Return the tile dimensions in pixel units */
1977 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1978 unsigned int *tile_width,
1979 unsigned int *tile_height)
1981 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1982 unsigned int cpp = fb->format->cpp[plane];
1984 *tile_width = tile_width_bytes / cpp;
1985 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1989 intel_fb_align_height(const struct drm_framebuffer *fb,
1990 int plane, unsigned int height)
1992 unsigned int tile_height = intel_tile_height(fb, plane);
1994 return ALIGN(height, tile_height);
1997 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1999 unsigned int size = 0;
2002 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2003 size += rot_info->plane[i].width * rot_info->plane[i].height;
2009 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2010 const struct drm_framebuffer *fb,
2011 unsigned int rotation)
2013 view->type = I915_GGTT_VIEW_NORMAL;
2014 if (drm_rotation_90_or_270(rotation)) {
2015 view->type = I915_GGTT_VIEW_ROTATED;
2016 view->rotated = to_intel_framebuffer(fb)->rot_info;
2020 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2022 if (IS_I830(dev_priv))
2024 else if (IS_I85X(dev_priv))
2026 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2032 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2034 if (INTEL_GEN(dev_priv) >= 9)
2036 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2037 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2039 else if (INTEL_GEN(dev_priv) >= 4)
2045 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2048 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2050 /* AUX_DIST needs only 4K alignment */
2054 switch (fb->modifier) {
2055 case DRM_FORMAT_MOD_LINEAR:
2056 return intel_linear_alignment(dev_priv);
2057 case I915_FORMAT_MOD_X_TILED:
2058 if (INTEL_GEN(dev_priv) >= 9)
2061 case I915_FORMAT_MOD_Y_TILED_CCS:
2062 case I915_FORMAT_MOD_Yf_TILED_CCS:
2063 case I915_FORMAT_MOD_Y_TILED:
2064 case I915_FORMAT_MOD_Yf_TILED:
2065 return 1 * 1024 * 1024;
2067 MISSING_CASE(fb->modifier);
2072 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2074 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2077 return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2081 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2082 unsigned int rotation,
2084 unsigned long *out_flags)
2086 struct drm_device *dev = fb->dev;
2087 struct drm_i915_private *dev_priv = to_i915(dev);
2088 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2089 struct i915_ggtt_view view;
2090 struct i915_vma *vma;
2091 unsigned int pinctl;
2094 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2096 alignment = intel_surf_alignment(fb, 0);
2098 intel_fill_fb_ggtt_view(&view, fb, rotation);
2100 /* Note that the w/a also requires 64 PTE of padding following the
2101 * bo. We currently fill all unused PTE with the shadow page and so
2102 * we should always have valid PTE following the scanout preventing
2105 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2106 alignment = 256 * 1024;
2109 * Global gtt pte registers are special registers which actually forward
2110 * writes to a chunk of system memory. Which means that there is no risk
2111 * that the register values disappear as soon as we call
2112 * intel_runtime_pm_put(), so it is correct to wrap only the
2113 * pin/unpin/fence and not more.
2115 intel_runtime_pm_get(dev_priv);
2117 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2121 /* Valleyview is definitely limited to scanning out the first
2122 * 512MiB. Lets presume this behaviour was inherited from the
2123 * g4x display engine and that all earlier gen are similarly
2124 * limited. Testing suggests that it is a little more
2125 * complicated than this. For example, Cherryview appears quite
2126 * happy to scanout from anywhere within its global aperture.
2128 if (HAS_GMCH_DISPLAY(dev_priv))
2129 pinctl |= PIN_MAPPABLE;
2131 vma = i915_gem_object_pin_to_display_plane(obj,
2132 alignment, &view, pinctl);
2136 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2139 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2140 * fence, whereas 965+ only requires a fence if using
2141 * framebuffer compression. For simplicity, we always, when
2142 * possible, install a fence as the cost is not that onerous.
2144 * If we fail to fence the tiled scanout, then either the
2145 * modeset will reject the change (which is highly unlikely as
2146 * the affected systems, all but one, do not have unmappable
2147 * space) or we will not be able to enable full powersaving
2148 * techniques (also likely not to apply due to various limits
2149 * FBC and the like impose on the size of the buffer, which
2150 * presumably we violated anyway with this unmappable buffer).
2151 * Anyway, it is presumably better to stumble onwards with
2152 * something and try to run the system in a "less than optimal"
2153 * mode that matches the user configuration.
2155 ret = i915_vma_pin_fence(vma);
2156 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2157 i915_gem_object_unpin_from_display_plane(vma);
2162 if (ret == 0 && vma->fence)
2163 *out_flags |= PLANE_HAS_FENCE;
2168 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2170 intel_runtime_pm_put(dev_priv);
2174 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2176 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2178 if (flags & PLANE_HAS_FENCE)
2179 i915_vma_unpin_fence(vma);
2180 i915_gem_object_unpin_from_display_plane(vma);
2184 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2185 unsigned int rotation)
2187 if (drm_rotation_90_or_270(rotation))
2188 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2190 return fb->pitches[plane];
2194 * Convert the x/y offsets into a linear offset.
2195 * Only valid with 0/180 degree rotation, which is fine since linear
2196 * offset is only used with linear buffers on pre-hsw and tiled buffers
2197 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2199 u32 intel_fb_xy_to_linear(int x, int y,
2200 const struct intel_plane_state *state,
2203 const struct drm_framebuffer *fb = state->base.fb;
2204 unsigned int cpp = fb->format->cpp[plane];
2205 unsigned int pitch = fb->pitches[plane];
2207 return y * pitch + x * cpp;
2211 * Add the x/y offsets derived from fb->offsets[] to the user
2212 * specified plane src x/y offsets. The resulting x/y offsets
2213 * specify the start of scanout from the beginning of the gtt mapping.
2215 void intel_add_fb_offsets(int *x, int *y,
2216 const struct intel_plane_state *state,
2220 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2221 unsigned int rotation = state->base.rotation;
2223 if (drm_rotation_90_or_270(rotation)) {
2224 *x += intel_fb->rotated[plane].x;
2225 *y += intel_fb->rotated[plane].y;
2227 *x += intel_fb->normal[plane].x;
2228 *y += intel_fb->normal[plane].y;
2232 static u32 __intel_adjust_tile_offset(int *x, int *y,
2233 unsigned int tile_width,
2234 unsigned int tile_height,
2235 unsigned int tile_size,
2236 unsigned int pitch_tiles,
2240 unsigned int pitch_pixels = pitch_tiles * tile_width;
2243 WARN_ON(old_offset & (tile_size - 1));
2244 WARN_ON(new_offset & (tile_size - 1));
2245 WARN_ON(new_offset > old_offset);
2247 tiles = (old_offset - new_offset) / tile_size;
2249 *y += tiles / pitch_tiles * tile_height;
2250 *x += tiles % pitch_tiles * tile_width;
2252 /* minimize x in case it got needlessly big */
2253 *y += *x / pitch_pixels * tile_height;
2259 static u32 _intel_adjust_tile_offset(int *x, int *y,
2260 const struct drm_framebuffer *fb, int plane,
2261 unsigned int rotation,
2262 u32 old_offset, u32 new_offset)
2264 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2265 unsigned int cpp = fb->format->cpp[plane];
2266 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2268 WARN_ON(new_offset > old_offset);
2270 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2271 unsigned int tile_size, tile_width, tile_height;
2272 unsigned int pitch_tiles;
2274 tile_size = intel_tile_size(dev_priv);
2275 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2277 if (drm_rotation_90_or_270(rotation)) {
2278 pitch_tiles = pitch / tile_height;
2279 swap(tile_width, tile_height);
2281 pitch_tiles = pitch / (tile_width * cpp);
2284 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2285 tile_size, pitch_tiles,
2286 old_offset, new_offset);
2288 old_offset += *y * pitch + *x * cpp;
2290 *y = (old_offset - new_offset) / pitch;
2291 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2298 * Adjust the tile offset by moving the difference into
2301 static u32 intel_adjust_tile_offset(int *x, int *y,
2302 const struct intel_plane_state *state, int plane,
2303 u32 old_offset, u32 new_offset)
2305 return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2306 state->base.rotation,
2307 old_offset, new_offset);
2311 * Computes the linear offset to the base tile and adjusts
2312 * x, y. bytes per pixel is assumed to be a power-of-two.
2314 * In the 90/270 rotated case, x and y are assumed
2315 * to be already rotated to match the rotated GTT view, and
2316 * pitch is the tile_height aligned framebuffer height.
2318 * This function is used when computing the derived information
2319 * under intel_framebuffer, so using any of that information
2320 * here is not allowed. Anything under drm_framebuffer can be
2321 * used. This is why the user has to pass in the pitch since it
2322 * is specified in the rotated orientation.
2324 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2326 const struct drm_framebuffer *fb, int plane,
2328 unsigned int rotation,
2331 uint64_t fb_modifier = fb->modifier;
2332 unsigned int cpp = fb->format->cpp[plane];
2333 u32 offset, offset_aligned;
2338 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2339 unsigned int tile_size, tile_width, tile_height;
2340 unsigned int tile_rows, tiles, pitch_tiles;
2342 tile_size = intel_tile_size(dev_priv);
2343 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2345 if (drm_rotation_90_or_270(rotation)) {
2346 pitch_tiles = pitch / tile_height;
2347 swap(tile_width, tile_height);
2349 pitch_tiles = pitch / (tile_width * cpp);
2352 tile_rows = *y / tile_height;
2355 tiles = *x / tile_width;
2358 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2359 offset_aligned = offset & ~alignment;
2361 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2362 tile_size, pitch_tiles,
2363 offset, offset_aligned);
2365 offset = *y * pitch + *x * cpp;
2366 offset_aligned = offset & ~alignment;
2368 *y = (offset & alignment) / pitch;
2369 *x = ((offset & alignment) - *y * pitch) / cpp;
2372 return offset_aligned;
2375 u32 intel_compute_tile_offset(int *x, int *y,
2376 const struct intel_plane_state *state,
2379 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2380 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2381 const struct drm_framebuffer *fb = state->base.fb;
2382 unsigned int rotation = state->base.rotation;
2383 int pitch = intel_fb_pitch(fb, plane, rotation);
2386 if (intel_plane->id == PLANE_CURSOR)
2387 alignment = intel_cursor_alignment(dev_priv);
2389 alignment = intel_surf_alignment(fb, plane);
2391 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2392 rotation, alignment);
2395 /* Convert the fb->offset[] into x/y offsets */
2396 static int intel_fb_offset_to_xy(int *x, int *y,
2397 const struct drm_framebuffer *fb, int plane)
2399 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2401 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2402 fb->offsets[plane] % intel_tile_size(dev_priv))
2408 _intel_adjust_tile_offset(x, y,
2409 fb, plane, DRM_MODE_ROTATE_0,
2410 fb->offsets[plane], 0);
2415 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2417 switch (fb_modifier) {
2418 case I915_FORMAT_MOD_X_TILED:
2419 return I915_TILING_X;
2420 case I915_FORMAT_MOD_Y_TILED:
2421 case I915_FORMAT_MOD_Y_TILED_CCS:
2422 return I915_TILING_Y;
2424 return I915_TILING_NONE;
2429 * From the Sky Lake PRM:
2430 * "The Color Control Surface (CCS) contains the compression status of
2431 * the cache-line pairs. The compression state of the cache-line pair
2432 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2433 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2434 * cache-line-pairs. CCS is always Y tiled."
2436 * Since cache line pairs refers to horizontally adjacent cache lines,
2437 * each cache line in the CCS corresponds to an area of 32x16 cache
2438 * lines on the main surface. Since each pixel is 4 bytes, this gives
2439 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2442 static const struct drm_format_info ccs_formats[] = {
2443 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2444 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2445 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2446 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2449 static const struct drm_format_info *
2450 lookup_format_info(const struct drm_format_info formats[],
2451 int num_formats, u32 format)
2455 for (i = 0; i < num_formats; i++) {
2456 if (formats[i].format == format)
2463 static const struct drm_format_info *
2464 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2466 switch (cmd->modifier[0]) {
2467 case I915_FORMAT_MOD_Y_TILED_CCS:
2468 case I915_FORMAT_MOD_Yf_TILED_CCS:
2469 return lookup_format_info(ccs_formats,
2470 ARRAY_SIZE(ccs_formats),
2478 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2479 struct drm_framebuffer *fb)
2481 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2482 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2483 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2484 u32 gtt_offset_rotated = 0;
2485 unsigned int max_size = 0;
2486 int i, num_planes = fb->format->num_planes;
2487 unsigned int tile_size = intel_tile_size(dev_priv);
2489 for (i = 0; i < num_planes; i++) {
2490 unsigned int width, height;
2491 unsigned int cpp, size;
2496 cpp = fb->format->cpp[i];
2497 width = drm_framebuffer_plane_width(fb->width, fb, i);
2498 height = drm_framebuffer_plane_height(fb->height, fb, i);
2500 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2502 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2507 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2508 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2509 int hsub = fb->format->hsub;
2510 int vsub = fb->format->vsub;
2511 int tile_width, tile_height;
2515 intel_tile_dims(fb, i, &tile_width, &tile_height);
2517 tile_height *= vsub;
2519 ccs_x = (x * hsub) % tile_width;
2520 ccs_y = (y * vsub) % tile_height;
2521 main_x = intel_fb->normal[0].x % tile_width;
2522 main_y = intel_fb->normal[0].y % tile_height;
2525 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2526 * x/y offsets must match between CCS and the main surface.
2528 if (main_x != ccs_x || main_y != ccs_y) {
2529 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2532 intel_fb->normal[0].x,
2533 intel_fb->normal[0].y,
2540 * The fence (if used) is aligned to the start of the object
2541 * so having the framebuffer wrap around across the edge of the
2542 * fenced region doesn't really work. We have no API to configure
2543 * the fence start offset within the object (nor could we probably
2544 * on gen2/3). So it's just easier if we just require that the
2545 * fb layout agrees with the fence layout. We already check that the
2546 * fb stride matches the fence stride elsewhere.
2548 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2549 (x + width) * cpp > fb->pitches[i]) {
2550 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2556 * First pixel of the framebuffer from
2557 * the start of the normal gtt mapping.
2559 intel_fb->normal[i].x = x;
2560 intel_fb->normal[i].y = y;
2562 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2563 fb, i, fb->pitches[i],
2564 DRM_MODE_ROTATE_0, tile_size);
2565 offset /= tile_size;
2567 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2568 unsigned int tile_width, tile_height;
2569 unsigned int pitch_tiles;
2572 intel_tile_dims(fb, i, &tile_width, &tile_height);
2574 rot_info->plane[i].offset = offset;
2575 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2576 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2577 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2579 intel_fb->rotated[i].pitch =
2580 rot_info->plane[i].height * tile_height;
2582 /* how many tiles does this plane need */
2583 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2585 * If the plane isn't horizontally tile aligned,
2586 * we need one more tile.
2591 /* rotate the x/y offsets to match the GTT view */
2597 rot_info->plane[i].width * tile_width,
2598 rot_info->plane[i].height * tile_height,
2599 DRM_MODE_ROTATE_270);
2603 /* rotate the tile dimensions to match the GTT view */
2604 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2605 swap(tile_width, tile_height);
2608 * We only keep the x/y offsets, so push all of the
2609 * gtt offset into the x/y offsets.
2611 __intel_adjust_tile_offset(&x, &y,
2612 tile_width, tile_height,
2613 tile_size, pitch_tiles,
2614 gtt_offset_rotated * tile_size, 0);
2616 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2619 * First pixel of the framebuffer from
2620 * the start of the rotated gtt mapping.
2622 intel_fb->rotated[i].x = x;
2623 intel_fb->rotated[i].y = y;
2625 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2626 x * cpp, tile_size);
2629 /* how many tiles in total needed in the bo */
2630 max_size = max(max_size, offset + size);
2633 if (max_size * tile_size > obj->base.size) {
2634 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2635 max_size * tile_size, obj->base.size);
2642 static int i9xx_format_to_fourcc(int format)
2645 case DISPPLANE_8BPP:
2646 return DRM_FORMAT_C8;
2647 case DISPPLANE_BGRX555:
2648 return DRM_FORMAT_XRGB1555;
2649 case DISPPLANE_BGRX565:
2650 return DRM_FORMAT_RGB565;
2652 case DISPPLANE_BGRX888:
2653 return DRM_FORMAT_XRGB8888;
2654 case DISPPLANE_RGBX888:
2655 return DRM_FORMAT_XBGR8888;
2656 case DISPPLANE_BGRX101010:
2657 return DRM_FORMAT_XRGB2101010;
2658 case DISPPLANE_RGBX101010:
2659 return DRM_FORMAT_XBGR2101010;
2663 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2666 case PLANE_CTL_FORMAT_RGB_565:
2667 return DRM_FORMAT_RGB565;
2668 case PLANE_CTL_FORMAT_NV12:
2669 return DRM_FORMAT_NV12;
2671 case PLANE_CTL_FORMAT_XRGB_8888:
2674 return DRM_FORMAT_ABGR8888;
2676 return DRM_FORMAT_XBGR8888;
2679 return DRM_FORMAT_ARGB8888;
2681 return DRM_FORMAT_XRGB8888;
2683 case PLANE_CTL_FORMAT_XRGB_2101010:
2685 return DRM_FORMAT_XBGR2101010;
2687 return DRM_FORMAT_XRGB2101010;
2692 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2693 struct intel_initial_plane_config *plane_config)
2695 struct drm_device *dev = crtc->base.dev;
2696 struct drm_i915_private *dev_priv = to_i915(dev);
2697 struct drm_i915_gem_object *obj = NULL;
2698 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2699 struct drm_framebuffer *fb = &plane_config->fb->base;
2700 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2701 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2704 size_aligned -= base_aligned;
2706 if (plane_config->size == 0)
2709 /* If the FB is too big, just don't use it since fbdev is not very
2710 * important and we should probably use that space with FBC or other
2712 if (size_aligned * 2 > dev_priv->stolen_usable_size)
2715 mutex_lock(&dev->struct_mutex);
2716 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2720 mutex_unlock(&dev->struct_mutex);
2724 if (plane_config->tiling == I915_TILING_X)
2725 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2727 mode_cmd.pixel_format = fb->format->format;
2728 mode_cmd.width = fb->width;
2729 mode_cmd.height = fb->height;
2730 mode_cmd.pitches[0] = fb->pitches[0];
2731 mode_cmd.modifier[0] = fb->modifier;
2732 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2734 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2735 DRM_DEBUG_KMS("intel fb init failed\n");
2740 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2744 i915_gem_object_put(obj);
2749 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2750 struct intel_plane_state *plane_state,
2753 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2755 plane_state->base.visible = visible;
2757 /* FIXME pre-g4x don't work like this */
2759 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
2760 crtc_state->active_planes |= BIT(plane->id);
2762 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
2763 crtc_state->active_planes &= ~BIT(plane->id);
2766 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2767 crtc_state->base.crtc->name,
2768 crtc_state->active_planes);
2771 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2772 struct intel_plane *plane)
2774 struct intel_crtc_state *crtc_state =
2775 to_intel_crtc_state(crtc->base.state);
2776 struct intel_plane_state *plane_state =
2777 to_intel_plane_state(plane->base.state);
2779 intel_set_plane_visible(crtc_state, plane_state, false);
2781 if (plane->id == PLANE_PRIMARY)
2782 intel_pre_disable_primary_noatomic(&crtc->base);
2784 trace_intel_disable_plane(&plane->base, crtc);
2785 plane->disable_plane(plane, crtc);
2789 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2790 struct intel_initial_plane_config *plane_config)
2792 struct drm_device *dev = intel_crtc->base.dev;
2793 struct drm_i915_private *dev_priv = to_i915(dev);
2795 struct drm_i915_gem_object *obj;
2796 struct drm_plane *primary = intel_crtc->base.primary;
2797 struct drm_plane_state *plane_state = primary->state;
2798 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2799 struct intel_plane *intel_plane = to_intel_plane(primary);
2800 struct intel_plane_state *intel_state =
2801 to_intel_plane_state(plane_state);
2802 struct drm_framebuffer *fb;
2804 if (!plane_config->fb)
2807 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2808 fb = &plane_config->fb->base;
2812 kfree(plane_config->fb);
2815 * Failed to alloc the obj, check to see if we should share
2816 * an fb with another CRTC instead
2818 for_each_crtc(dev, c) {
2819 struct intel_plane_state *state;
2821 if (c == &intel_crtc->base)
2824 if (!to_intel_crtc(c)->active)
2827 state = to_intel_plane_state(c->primary->state);
2831 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2832 fb = state->base.fb;
2833 drm_framebuffer_get(fb);
2839 * We've failed to reconstruct the BIOS FB. Current display state
2840 * indicates that the primary plane is visible, but has a NULL FB,
2841 * which will lead to problems later if we don't fix it up. The
2842 * simplest solution is to just disable the primary plane now and
2843 * pretend the BIOS never had it enabled.
2845 intel_plane_disable_noatomic(intel_crtc, intel_plane);
2850 mutex_lock(&dev->struct_mutex);
2852 intel_pin_and_fence_fb_obj(fb,
2853 primary->state->rotation,
2854 intel_plane_uses_fence(intel_state),
2855 &intel_state->flags);
2856 mutex_unlock(&dev->struct_mutex);
2857 if (IS_ERR(intel_state->vma)) {
2858 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2859 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2861 intel_state->vma = NULL;
2862 drm_framebuffer_put(fb);
2866 obj = intel_fb_obj(fb);
2867 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2869 plane_state->src_x = 0;
2870 plane_state->src_y = 0;
2871 plane_state->src_w = fb->width << 16;
2872 plane_state->src_h = fb->height << 16;
2874 plane_state->crtc_x = 0;
2875 plane_state->crtc_y = 0;
2876 plane_state->crtc_w = fb->width;
2877 plane_state->crtc_h = fb->height;
2879 intel_state->base.src = drm_plane_state_src(plane_state);
2880 intel_state->base.dst = drm_plane_state_dest(plane_state);
2882 if (i915_gem_object_is_tiled(obj))
2883 dev_priv->preserve_bios_swizzle = true;
2885 plane_state->fb = fb;
2886 plane_state->crtc = &intel_crtc->base;
2888 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2889 to_intel_plane_state(plane_state),
2892 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2893 &obj->frontbuffer_bits);
2896 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2897 unsigned int rotation)
2899 int cpp = fb->format->cpp[plane];
2901 switch (fb->modifier) {
2902 case DRM_FORMAT_MOD_LINEAR:
2903 case I915_FORMAT_MOD_X_TILED:
2916 case I915_FORMAT_MOD_Y_TILED_CCS:
2917 case I915_FORMAT_MOD_Yf_TILED_CCS:
2918 /* FIXME AUX plane? */
2919 case I915_FORMAT_MOD_Y_TILED:
2920 case I915_FORMAT_MOD_Yf_TILED:
2935 MISSING_CASE(fb->modifier);
2941 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2942 int main_x, int main_y, u32 main_offset)
2944 const struct drm_framebuffer *fb = plane_state->base.fb;
2945 int hsub = fb->format->hsub;
2946 int vsub = fb->format->vsub;
2947 int aux_x = plane_state->aux.x;
2948 int aux_y = plane_state->aux.y;
2949 u32 aux_offset = plane_state->aux.offset;
2950 u32 alignment = intel_surf_alignment(fb, 1);
2952 while (aux_offset >= main_offset && aux_y <= main_y) {
2955 if (aux_x == main_x && aux_y == main_y)
2958 if (aux_offset == 0)
2963 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2964 aux_offset, aux_offset - alignment);
2965 aux_x = x * hsub + aux_x % hsub;
2966 aux_y = y * vsub + aux_y % vsub;
2969 if (aux_x != main_x || aux_y != main_y)
2972 plane_state->aux.offset = aux_offset;
2973 plane_state->aux.x = aux_x;
2974 plane_state->aux.y = aux_y;
2979 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
2980 struct intel_plane_state *plane_state)
2982 struct drm_i915_private *dev_priv =
2983 to_i915(plane_state->base.plane->dev);
2984 const struct drm_framebuffer *fb = plane_state->base.fb;
2985 unsigned int rotation = plane_state->base.rotation;
2986 int x = plane_state->base.src.x1 >> 16;
2987 int y = plane_state->base.src.y1 >> 16;
2988 int w = drm_rect_width(&plane_state->base.src) >> 16;
2989 int h = drm_rect_height(&plane_state->base.src) >> 16;
2990 int dst_x = plane_state->base.dst.x1;
2991 int pipe_src_w = crtc_state->pipe_src_w;
2992 int max_width = skl_max_plane_width(fb, 0, rotation);
2993 int max_height = 4096;
2994 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2996 if (w > max_width || h > max_height) {
2997 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2998 w, h, max_width, max_height);
3003 * Display WA #1175: cnl,glk
3004 * Planes other than the cursor may cause FIFO underflow and display
3005 * corruption if starting less than 4 pixels from the right edge of
3007 * Besides the above WA fix the similar problem, where planes other
3008 * than the cursor ending less than 4 pixels from the left edge of the
3009 * screen may cause FIFO underflow and display corruption.
3011 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3012 (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
3013 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3014 dst_x + w < 4 ? "end" : "start",
3015 dst_x + w < 4 ? dst_x + w : dst_x,
3020 intel_add_fb_offsets(&x, &y, plane_state, 0);
3021 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3022 alignment = intel_surf_alignment(fb, 0);
3025 * AUX surface offset is specified as the distance from the
3026 * main surface offset, and it must be non-negative. Make
3027 * sure that is what we will get.
3029 if (offset > aux_offset)
3030 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3031 offset, aux_offset & ~(alignment - 1));
3034 * When using an X-tiled surface, the plane blows up
3035 * if the x offset + width exceed the stride.
3037 * TODO: linear and Y-tiled seem fine, Yf untested,
3039 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3040 int cpp = fb->format->cpp[0];
3042 while ((x + w) * cpp > fb->pitches[0]) {
3044 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3048 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3049 offset, offset - alignment);
3054 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3055 * they match with the main surface x/y offsets.
3057 if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3058 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3059 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3063 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3064 offset, offset - alignment);
3067 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3068 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3073 plane_state->main.offset = offset;
3074 plane_state->main.x = x;
3075 plane_state->main.y = y;
3081 skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
3082 struct intel_plane_state *plane_state)
3084 /* Display WA #1106 */
3085 if (plane_state->base.rotation !=
3086 (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90) &&
3087 plane_state->base.rotation != DRM_MODE_ROTATE_270)
3091 * src coordinates are rotated here.
3092 * We check height but report it as width
3094 if (((drm_rect_height(&plane_state->base.src) >> 16) % 4) != 0) {
3095 DRM_DEBUG_KMS("src width must be multiple "
3096 "of 4 for rotated NV12\n");
3103 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3105 const struct drm_framebuffer *fb = plane_state->base.fb;
3106 unsigned int rotation = plane_state->base.rotation;
3107 int max_width = skl_max_plane_width(fb, 1, rotation);
3108 int max_height = 4096;
3109 int x = plane_state->base.src.x1 >> 17;
3110 int y = plane_state->base.src.y1 >> 17;
3111 int w = drm_rect_width(&plane_state->base.src) >> 17;
3112 int h = drm_rect_height(&plane_state->base.src) >> 17;
3115 intel_add_fb_offsets(&x, &y, plane_state, 1);
3116 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3118 /* FIXME not quite sure how/if these apply to the chroma plane */
3119 if (w > max_width || h > max_height) {
3120 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3121 w, h, max_width, max_height);
3125 plane_state->aux.offset = offset;
3126 plane_state->aux.x = x;
3127 plane_state->aux.y = y;
3132 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3134 const struct drm_framebuffer *fb = plane_state->base.fb;
3135 int src_x = plane_state->base.src.x1 >> 16;
3136 int src_y = plane_state->base.src.y1 >> 16;
3137 int hsub = fb->format->hsub;
3138 int vsub = fb->format->vsub;
3139 int x = src_x / hsub;
3140 int y = src_y / vsub;
3143 if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3144 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3145 plane_state->base.rotation);
3149 intel_add_fb_offsets(&x, &y, plane_state, 1);
3150 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3152 plane_state->aux.offset = offset;
3153 plane_state->aux.x = x * hsub + src_x % hsub;
3154 plane_state->aux.y = y * vsub + src_y % vsub;
3159 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3160 struct intel_plane_state *plane_state)
3162 const struct drm_framebuffer *fb = plane_state->base.fb;
3163 unsigned int rotation = plane_state->base.rotation;
3166 if (rotation & DRM_MODE_REFLECT_X &&
3167 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3168 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3172 if (!plane_state->base.visible)
3175 /* Rotate src coordinates to match rotated GTT view */
3176 if (drm_rotation_90_or_270(rotation))
3177 drm_rect_rotate(&plane_state->base.src,
3178 fb->width << 16, fb->height << 16,
3179 DRM_MODE_ROTATE_270);
3182 * Handle the AUX surface first since
3183 * the main surface setup depends on it.
3185 if (fb->format->format == DRM_FORMAT_NV12) {
3186 ret = skl_check_nv12_surface(crtc_state, plane_state);
3189 ret = skl_check_nv12_aux_surface(plane_state);
3192 } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3193 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3194 ret = skl_check_ccs_aux_surface(plane_state);
3198 plane_state->aux.offset = ~0xfff;
3199 plane_state->aux.x = 0;
3200 plane_state->aux.y = 0;
3203 ret = skl_check_main_surface(crtc_state, plane_state);
3210 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3211 const struct intel_plane_state *plane_state)
3213 struct drm_i915_private *dev_priv =
3214 to_i915(plane_state->base.plane->dev);
3215 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3216 const struct drm_framebuffer *fb = plane_state->base.fb;
3217 unsigned int rotation = plane_state->base.rotation;
3220 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3222 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3223 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3224 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3226 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3227 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3229 if (INTEL_GEN(dev_priv) < 5)
3230 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3232 switch (fb->format->format) {
3234 dspcntr |= DISPPLANE_8BPP;
3236 case DRM_FORMAT_XRGB1555:
3237 dspcntr |= DISPPLANE_BGRX555;
3239 case DRM_FORMAT_RGB565:
3240 dspcntr |= DISPPLANE_BGRX565;
3242 case DRM_FORMAT_XRGB8888:
3243 dspcntr |= DISPPLANE_BGRX888;
3245 case DRM_FORMAT_XBGR8888:
3246 dspcntr |= DISPPLANE_RGBX888;
3248 case DRM_FORMAT_XRGB2101010:
3249 dspcntr |= DISPPLANE_BGRX101010;
3251 case DRM_FORMAT_XBGR2101010:
3252 dspcntr |= DISPPLANE_RGBX101010;
3255 MISSING_CASE(fb->format->format);
3259 if (INTEL_GEN(dev_priv) >= 4 &&
3260 fb->modifier == I915_FORMAT_MOD_X_TILED)
3261 dspcntr |= DISPPLANE_TILED;
3263 if (rotation & DRM_MODE_ROTATE_180)
3264 dspcntr |= DISPPLANE_ROTATE_180;
3266 if (rotation & DRM_MODE_REFLECT_X)
3267 dspcntr |= DISPPLANE_MIRROR;
3272 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3274 struct drm_i915_private *dev_priv =
3275 to_i915(plane_state->base.plane->dev);
3276 int src_x = plane_state->base.src.x1 >> 16;
3277 int src_y = plane_state->base.src.y1 >> 16;
3280 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3282 if (INTEL_GEN(dev_priv) >= 4)
3283 offset = intel_compute_tile_offset(&src_x, &src_y,
3288 /* HSW/BDW do this automagically in hardware */
3289 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3290 unsigned int rotation = plane_state->base.rotation;
3291 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3292 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3294 if (rotation & DRM_MODE_ROTATE_180) {
3297 } else if (rotation & DRM_MODE_REFLECT_X) {
3302 plane_state->main.offset = offset;
3303 plane_state->main.x = src_x;
3304 plane_state->main.y = src_y;
3309 static void i9xx_update_plane(struct intel_plane *plane,
3310 const struct intel_crtc_state *crtc_state,
3311 const struct intel_plane_state *plane_state)
3313 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3314 const struct drm_framebuffer *fb = plane_state->base.fb;
3315 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3317 u32 dspcntr = plane_state->ctl;
3318 i915_reg_t reg = DSPCNTR(i9xx_plane);
3319 int x = plane_state->main.x;
3320 int y = plane_state->main.y;
3321 unsigned long irqflags;
3324 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3326 if (INTEL_GEN(dev_priv) >= 4)
3327 dspaddr_offset = plane_state->main.offset;
3329 dspaddr_offset = linear_offset;
3331 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3333 if (INTEL_GEN(dev_priv) < 4) {
3334 /* pipesrc and dspsize control the size that is scaled from,
3335 * which should always be the user's requested size.
3337 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3338 ((crtc_state->pipe_src_h - 1) << 16) |
3339 (crtc_state->pipe_src_w - 1));
3340 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3341 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3342 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3343 ((crtc_state->pipe_src_h - 1) << 16) |
3344 (crtc_state->pipe_src_w - 1));
3345 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3346 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3349 I915_WRITE_FW(reg, dspcntr);
3351 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3352 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3353 I915_WRITE_FW(DSPSURF(i9xx_plane),
3354 intel_plane_ggtt_offset(plane_state) +
3356 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3357 } else if (INTEL_GEN(dev_priv) >= 4) {
3358 I915_WRITE_FW(DSPSURF(i9xx_plane),
3359 intel_plane_ggtt_offset(plane_state) +
3361 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3362 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3364 I915_WRITE_FW(DSPADDR(i9xx_plane),
3365 intel_plane_ggtt_offset(plane_state) +
3368 POSTING_READ_FW(reg);
3370 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3373 static void i9xx_disable_plane(struct intel_plane *plane,
3374 struct intel_crtc *crtc)
3376 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3377 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3378 unsigned long irqflags;
3380 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3382 I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3383 if (INTEL_GEN(dev_priv) >= 4)
3384 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3386 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3387 POSTING_READ_FW(DSPCNTR(i9xx_plane));
3389 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3392 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3395 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3396 enum intel_display_power_domain power_domain;
3397 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3402 * Not 100% correct for planes that can move between pipes,
3403 * but that's only the case for gen2-4 which don't have any
3404 * display power wells.
3406 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3407 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3410 val = I915_READ(DSPCNTR(i9xx_plane));
3412 ret = val & DISPLAY_PLANE_ENABLE;
3414 if (INTEL_GEN(dev_priv) >= 5)
3415 *pipe = plane->pipe;
3417 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3418 DISPPLANE_SEL_PIPE_SHIFT;
3420 intel_display_power_put(dev_priv, power_domain);
3426 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3428 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3431 return intel_tile_width_bytes(fb, plane);
3434 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3436 struct drm_device *dev = intel_crtc->base.dev;
3437 struct drm_i915_private *dev_priv = to_i915(dev);
3439 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3440 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3441 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3445 * This function detaches (aka. unbinds) unused scalers in hardware
3447 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3449 struct intel_crtc_scaler_state *scaler_state;
3452 scaler_state = &intel_crtc->config->scaler_state;
3454 /* loop through and disable scalers that aren't in use */
3455 for (i = 0; i < intel_crtc->num_scalers; i++) {
3456 if (!scaler_state->scalers[i].in_use)
3457 skl_detach_scaler(intel_crtc, i);
3461 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3462 unsigned int rotation)
3466 if (plane >= fb->format->num_planes)
3469 stride = intel_fb_pitch(fb, plane, rotation);
3472 * The stride is either expressed as a multiple of 64 bytes chunks for
3473 * linear buffers or in number of tiles for tiled buffers.
3475 if (drm_rotation_90_or_270(rotation))
3476 stride /= intel_tile_height(fb, plane);
3478 stride /= intel_fb_stride_alignment(fb, plane);
3483 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3485 switch (pixel_format) {
3487 return PLANE_CTL_FORMAT_INDEXED;
3488 case DRM_FORMAT_RGB565:
3489 return PLANE_CTL_FORMAT_RGB_565;
3490 case DRM_FORMAT_XBGR8888:
3491 case DRM_FORMAT_ABGR8888:
3492 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3493 case DRM_FORMAT_XRGB8888:
3494 case DRM_FORMAT_ARGB8888:
3495 return PLANE_CTL_FORMAT_XRGB_8888;
3496 case DRM_FORMAT_XRGB2101010:
3497 return PLANE_CTL_FORMAT_XRGB_2101010;
3498 case DRM_FORMAT_XBGR2101010:
3499 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3500 case DRM_FORMAT_YUYV:
3501 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3502 case DRM_FORMAT_YVYU:
3503 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3504 case DRM_FORMAT_UYVY:
3505 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3506 case DRM_FORMAT_VYUY:
3507 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3508 case DRM_FORMAT_NV12:
3509 return PLANE_CTL_FORMAT_NV12;
3511 MISSING_CASE(pixel_format);
3518 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3519 * to be already pre-multiplied. We need to add a knob (or a different
3520 * DRM_FORMAT) for user-space to configure that.
3522 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3524 switch (pixel_format) {
3525 case DRM_FORMAT_ABGR8888:
3526 case DRM_FORMAT_ARGB8888:
3527 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3529 return PLANE_CTL_ALPHA_DISABLE;
3533 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3535 switch (pixel_format) {
3536 case DRM_FORMAT_ABGR8888:
3537 case DRM_FORMAT_ARGB8888:
3538 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3540 return PLANE_COLOR_ALPHA_DISABLE;
3544 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3546 switch (fb_modifier) {
3547 case DRM_FORMAT_MOD_LINEAR:
3549 case I915_FORMAT_MOD_X_TILED:
3550 return PLANE_CTL_TILED_X;
3551 case I915_FORMAT_MOD_Y_TILED:
3552 return PLANE_CTL_TILED_Y;
3553 case I915_FORMAT_MOD_Y_TILED_CCS:
3554 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3555 case I915_FORMAT_MOD_Yf_TILED:
3556 return PLANE_CTL_TILED_YF;
3557 case I915_FORMAT_MOD_Yf_TILED_CCS:
3558 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3560 MISSING_CASE(fb_modifier);
3566 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3569 case DRM_MODE_ROTATE_0:
3572 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3573 * while i915 HW rotation is clockwise, thats why this swapping.
3575 case DRM_MODE_ROTATE_90:
3576 return PLANE_CTL_ROTATE_270;
3577 case DRM_MODE_ROTATE_180:
3578 return PLANE_CTL_ROTATE_180;
3579 case DRM_MODE_ROTATE_270:
3580 return PLANE_CTL_ROTATE_90;
3582 MISSING_CASE(rotate);
3588 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3593 case DRM_MODE_REFLECT_X:
3594 return PLANE_CTL_FLIP_HORIZONTAL;
3595 case DRM_MODE_REFLECT_Y:
3597 MISSING_CASE(reflect);
3603 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3604 const struct intel_plane_state *plane_state)
3606 struct drm_i915_private *dev_priv =
3607 to_i915(plane_state->base.plane->dev);
3608 const struct drm_framebuffer *fb = plane_state->base.fb;
3609 unsigned int rotation = plane_state->base.rotation;
3610 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3613 plane_ctl = PLANE_CTL_ENABLE;
3615 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3616 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3618 PLANE_CTL_PIPE_GAMMA_ENABLE |
3619 PLANE_CTL_PIPE_CSC_ENABLE |
3620 PLANE_CTL_PLANE_GAMMA_DISABLE;
3622 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3623 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3625 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3626 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3629 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3630 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3631 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3633 if (INTEL_GEN(dev_priv) >= 10)
3634 plane_ctl |= cnl_plane_ctl_flip(rotation &
3635 DRM_MODE_REFLECT_MASK);
3637 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3638 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3639 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3640 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3645 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3646 const struct intel_plane_state *plane_state)
3648 struct drm_i915_private *dev_priv =
3649 to_i915(plane_state->base.plane->dev);
3650 const struct drm_framebuffer *fb = plane_state->base.fb;
3651 u32 plane_color_ctl = 0;
3653 if (INTEL_GEN(dev_priv) < 11) {
3654 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3655 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3657 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3658 plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3660 if (fb->format->is_yuv) {
3661 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3662 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3664 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3666 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3667 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3670 return plane_color_ctl;
3674 __intel_display_resume(struct drm_device *dev,
3675 struct drm_atomic_state *state,
3676 struct drm_modeset_acquire_ctx *ctx)
3678 struct drm_crtc_state *crtc_state;
3679 struct drm_crtc *crtc;
3682 intel_modeset_setup_hw_state(dev, ctx);
3683 i915_redisable_vga(to_i915(dev));
3689 * We've duplicated the state, pointers to the old state are invalid.
3691 * Don't attempt to use the old state until we commit the duplicated state.
3693 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3695 * Force recalculation even if we restore
3696 * current state. With fast modeset this may not result
3697 * in a modeset when the state is compatible.
3699 crtc_state->mode_changed = true;
3702 /* ignore any reset values/BIOS leftovers in the WM registers */
3703 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3704 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3706 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3708 WARN_ON(ret == -EDEADLK);
3712 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3714 return intel_has_gpu_reset(dev_priv) &&
3715 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3718 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3720 struct drm_device *dev = &dev_priv->drm;
3721 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3722 struct drm_atomic_state *state;
3725 /* reset doesn't touch the display */
3726 if (!i915_modparams.force_reset_modeset_test &&
3727 !gpu_reset_clobbers_display(dev_priv))
3730 /* We have a modeset vs reset deadlock, defensively unbreak it. */
3731 set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3732 wake_up_all(&dev_priv->gpu_error.wait_queue);
3734 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3735 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3736 i915_gem_set_wedged(dev_priv);
3740 * Need mode_config.mutex so that we don't
3741 * trample ongoing ->detect() and whatnot.
3743 mutex_lock(&dev->mode_config.mutex);
3744 drm_modeset_acquire_init(ctx, 0);
3746 ret = drm_modeset_lock_all_ctx(dev, ctx);
3747 if (ret != -EDEADLK)
3750 drm_modeset_backoff(ctx);
3753 * Disabling the crtcs gracefully seems nicer. Also the
3754 * g33 docs say we should at least disable all the planes.
3756 state = drm_atomic_helper_duplicate_state(dev, ctx);
3757 if (IS_ERR(state)) {
3758 ret = PTR_ERR(state);
3759 DRM_ERROR("Duplicating state failed with %i\n", ret);
3763 ret = drm_atomic_helper_disable_all(dev, ctx);
3765 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3766 drm_atomic_state_put(state);
3770 dev_priv->modeset_restore_state = state;
3771 state->acquire_ctx = ctx;
3774 void intel_finish_reset(struct drm_i915_private *dev_priv)
3776 struct drm_device *dev = &dev_priv->drm;
3777 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3778 struct drm_atomic_state *state;
3781 /* reset doesn't touch the display */
3782 if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3785 state = fetch_and_zero(&dev_priv->modeset_restore_state);
3789 /* reset doesn't touch the display */
3790 if (!gpu_reset_clobbers_display(dev_priv)) {
3791 /* for testing only restore the display */
3792 ret = __intel_display_resume(dev, state, ctx);
3794 DRM_ERROR("Restoring old state failed with %i\n", ret);
3797 * The display has been reset as well,
3798 * so need a full re-initialization.
3800 intel_runtime_pm_disable_interrupts(dev_priv);
3801 intel_runtime_pm_enable_interrupts(dev_priv);
3803 intel_pps_unlock_regs_wa(dev_priv);
3804 intel_modeset_init_hw(dev);
3805 intel_init_clock_gating(dev_priv);
3807 spin_lock_irq(&dev_priv->irq_lock);
3808 if (dev_priv->display.hpd_irq_setup)
3809 dev_priv->display.hpd_irq_setup(dev_priv);
3810 spin_unlock_irq(&dev_priv->irq_lock);
3812 ret = __intel_display_resume(dev, state, ctx);
3814 DRM_ERROR("Restoring old state failed with %i\n", ret);
3816 intel_hpd_init(dev_priv);
3819 drm_atomic_state_put(state);
3821 drm_modeset_drop_locks(ctx);
3822 drm_modeset_acquire_fini(ctx);
3823 mutex_unlock(&dev->mode_config.mutex);
3825 clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3828 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3829 const struct intel_crtc_state *new_crtc_state)
3831 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3834 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3835 crtc->base.mode = new_crtc_state->base.mode;
3838 * Update pipe size and adjust fitter if needed: the reason for this is
3839 * that in compute_mode_changes we check the native mode (not the pfit
3840 * mode) to see if we can flip rather than do a full mode set. In the
3841 * fastboot case, we'll flip, but if we don't update the pipesrc and
3842 * pfit state, we'll end up with a big fb scanned out into the wrong
3846 I915_WRITE(PIPESRC(crtc->pipe),
3847 ((new_crtc_state->pipe_src_w - 1) << 16) |
3848 (new_crtc_state->pipe_src_h - 1));
3850 /* on skylake this is done by detaching scalers */
3851 if (INTEL_GEN(dev_priv) >= 9) {
3852 skl_detach_scalers(crtc);
3854 if (new_crtc_state->pch_pfit.enabled)
3855 skylake_pfit_enable(crtc);
3856 } else if (HAS_PCH_SPLIT(dev_priv)) {
3857 if (new_crtc_state->pch_pfit.enabled)
3858 ironlake_pfit_enable(crtc);
3859 else if (old_crtc_state->pch_pfit.enabled)
3860 ironlake_pfit_disable(crtc, true);
3864 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3866 struct drm_device *dev = crtc->base.dev;
3867 struct drm_i915_private *dev_priv = to_i915(dev);
3868 int pipe = crtc->pipe;
3872 /* enable normal train */
3873 reg = FDI_TX_CTL(pipe);
3874 temp = I915_READ(reg);
3875 if (IS_IVYBRIDGE(dev_priv)) {
3876 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3877 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3879 temp &= ~FDI_LINK_TRAIN_NONE;
3880 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3882 I915_WRITE(reg, temp);
3884 reg = FDI_RX_CTL(pipe);
3885 temp = I915_READ(reg);
3886 if (HAS_PCH_CPT(dev_priv)) {
3887 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3888 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3890 temp &= ~FDI_LINK_TRAIN_NONE;
3891 temp |= FDI_LINK_TRAIN_NONE;
3893 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3895 /* wait one idle pattern time */
3899 /* IVB wants error correction enabled */
3900 if (IS_IVYBRIDGE(dev_priv))
3901 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3902 FDI_FE_ERRC_ENABLE);
3905 /* The FDI link training functions for ILK/Ibexpeak. */
3906 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3907 const struct intel_crtc_state *crtc_state)
3909 struct drm_device *dev = crtc->base.dev;
3910 struct drm_i915_private *dev_priv = to_i915(dev);
3911 int pipe = crtc->pipe;
3915 /* FDI needs bits from pipe first */
3916 assert_pipe_enabled(dev_priv, pipe);
3918 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3920 reg = FDI_RX_IMR(pipe);
3921 temp = I915_READ(reg);
3922 temp &= ~FDI_RX_SYMBOL_LOCK;
3923 temp &= ~FDI_RX_BIT_LOCK;
3924 I915_WRITE(reg, temp);
3928 /* enable CPU FDI TX and PCH FDI RX */
3929 reg = FDI_TX_CTL(pipe);
3930 temp = I915_READ(reg);
3931 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3932 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3933 temp &= ~FDI_LINK_TRAIN_NONE;
3934 temp |= FDI_LINK_TRAIN_PATTERN_1;
3935 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3937 reg = FDI_RX_CTL(pipe);
3938 temp = I915_READ(reg);
3939 temp &= ~FDI_LINK_TRAIN_NONE;
3940 temp |= FDI_LINK_TRAIN_PATTERN_1;
3941 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3946 /* Ironlake workaround, enable clock pointer after FDI enable*/
3947 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3948 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3949 FDI_RX_PHASE_SYNC_POINTER_EN);
3951 reg = FDI_RX_IIR(pipe);
3952 for (tries = 0; tries < 5; tries++) {
3953 temp = I915_READ(reg);
3954 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3956 if ((temp & FDI_RX_BIT_LOCK)) {
3957 DRM_DEBUG_KMS("FDI train 1 done.\n");
3958 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3963 DRM_ERROR("FDI train 1 fail!\n");
3966 reg = FDI_TX_CTL(pipe);
3967 temp = I915_READ(reg);
3968 temp &= ~FDI_LINK_TRAIN_NONE;
3969 temp |= FDI_LINK_TRAIN_PATTERN_2;
3970 I915_WRITE(reg, temp);
3972 reg = FDI_RX_CTL(pipe);
3973 temp = I915_READ(reg);
3974 temp &= ~FDI_LINK_TRAIN_NONE;
3975 temp |= FDI_LINK_TRAIN_PATTERN_2;
3976 I915_WRITE(reg, temp);
3981 reg = FDI_RX_IIR(pipe);
3982 for (tries = 0; tries < 5; tries++) {
3983 temp = I915_READ(reg);
3984 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3986 if (temp & FDI_RX_SYMBOL_LOCK) {
3987 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3988 DRM_DEBUG_KMS("FDI train 2 done.\n");
3993 DRM_ERROR("FDI train 2 fail!\n");
3995 DRM_DEBUG_KMS("FDI train done\n");
3999 static const int snb_b_fdi_train_param[] = {
4000 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4001 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4002 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4003 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4006 /* The FDI link training functions for SNB/Cougarpoint. */
4007 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4008 const struct intel_crtc_state *crtc_state)
4010 struct drm_device *dev = crtc->base.dev;
4011 struct drm_i915_private *dev_priv = to_i915(dev);
4012 int pipe = crtc->pipe;
4016 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4018 reg = FDI_RX_IMR(pipe);
4019 temp = I915_READ(reg);
4020 temp &= ~FDI_RX_SYMBOL_LOCK;
4021 temp &= ~FDI_RX_BIT_LOCK;
4022 I915_WRITE(reg, temp);
4027 /* enable CPU FDI TX and PCH FDI RX */
4028 reg = FDI_TX_CTL(pipe);
4029 temp = I915_READ(reg);
4030 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4031 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4032 temp &= ~FDI_LINK_TRAIN_NONE;
4033 temp |= FDI_LINK_TRAIN_PATTERN_1;
4034 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4036 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4037 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4039 I915_WRITE(FDI_RX_MISC(pipe),
4040 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4042 reg = FDI_RX_CTL(pipe);
4043 temp = I915_READ(reg);
4044 if (HAS_PCH_CPT(dev_priv)) {
4045 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4046 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4048 temp &= ~FDI_LINK_TRAIN_NONE;
4049 temp |= FDI_LINK_TRAIN_PATTERN_1;
4051 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4056 for (i = 0; i < 4; i++) {
4057 reg = FDI_TX_CTL(pipe);
4058 temp = I915_READ(reg);
4059 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4060 temp |= snb_b_fdi_train_param[i];
4061 I915_WRITE(reg, temp);
4066 for (retry = 0; retry < 5; retry++) {
4067 reg = FDI_RX_IIR(pipe);
4068 temp = I915_READ(reg);
4069 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4070 if (temp & FDI_RX_BIT_LOCK) {
4071 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4072 DRM_DEBUG_KMS("FDI train 1 done.\n");
4081 DRM_ERROR("FDI train 1 fail!\n");
4084 reg = FDI_TX_CTL(pipe);
4085 temp = I915_READ(reg);
4086 temp &= ~FDI_LINK_TRAIN_NONE;
4087 temp |= FDI_LINK_TRAIN_PATTERN_2;
4088 if (IS_GEN6(dev_priv)) {
4089 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4091 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4093 I915_WRITE(reg, temp);
4095 reg = FDI_RX_CTL(pipe);
4096 temp = I915_READ(reg);
4097 if (HAS_PCH_CPT(dev_priv)) {
4098 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4099 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4101 temp &= ~FDI_LINK_TRAIN_NONE;
4102 temp |= FDI_LINK_TRAIN_PATTERN_2;
4104 I915_WRITE(reg, temp);
4109 for (i = 0; i < 4; i++) {
4110 reg = FDI_TX_CTL(pipe);
4111 temp = I915_READ(reg);
4112 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4113 temp |= snb_b_fdi_train_param[i];
4114 I915_WRITE(reg, temp);
4119 for (retry = 0; retry < 5; retry++) {
4120 reg = FDI_RX_IIR(pipe);
4121 temp = I915_READ(reg);
4122 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4123 if (temp & FDI_RX_SYMBOL_LOCK) {
4124 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4125 DRM_DEBUG_KMS("FDI train 2 done.\n");
4134 DRM_ERROR("FDI train 2 fail!\n");
4136 DRM_DEBUG_KMS("FDI train done.\n");
4139 /* Manual link training for Ivy Bridge A0 parts */
4140 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4141 const struct intel_crtc_state *crtc_state)
4143 struct drm_device *dev = crtc->base.dev;
4144 struct drm_i915_private *dev_priv = to_i915(dev);
4145 int pipe = crtc->pipe;
4149 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4151 reg = FDI_RX_IMR(pipe);
4152 temp = I915_READ(reg);
4153 temp &= ~FDI_RX_SYMBOL_LOCK;
4154 temp &= ~FDI_RX_BIT_LOCK;
4155 I915_WRITE(reg, temp);
4160 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4161 I915_READ(FDI_RX_IIR(pipe)));
4163 /* Try each vswing and preemphasis setting twice before moving on */
4164 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4165 /* disable first in case we need to retry */
4166 reg = FDI_TX_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4169 temp &= ~FDI_TX_ENABLE;
4170 I915_WRITE(reg, temp);
4172 reg = FDI_RX_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~FDI_LINK_TRAIN_AUTO;
4175 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4176 temp &= ~FDI_RX_ENABLE;
4177 I915_WRITE(reg, temp);
4179 /* enable CPU FDI TX and PCH FDI RX */
4180 reg = FDI_TX_CTL(pipe);
4181 temp = I915_READ(reg);
4182 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4183 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4184 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4186 temp |= snb_b_fdi_train_param[j/2];
4187 temp |= FDI_COMPOSITE_SYNC;
4188 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4190 I915_WRITE(FDI_RX_MISC(pipe),
4191 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4193 reg = FDI_RX_CTL(pipe);
4194 temp = I915_READ(reg);
4195 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4196 temp |= FDI_COMPOSITE_SYNC;
4197 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4200 udelay(1); /* should be 0.5us */
4202 for (i = 0; i < 4; i++) {
4203 reg = FDI_RX_IIR(pipe);
4204 temp = I915_READ(reg);
4205 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4207 if (temp & FDI_RX_BIT_LOCK ||
4208 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4209 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4210 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4214 udelay(1); /* should be 0.5us */
4217 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4222 reg = FDI_TX_CTL(pipe);
4223 temp = I915_READ(reg);
4224 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4225 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4226 I915_WRITE(reg, temp);
4228 reg = FDI_RX_CTL(pipe);
4229 temp = I915_READ(reg);
4230 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4231 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4232 I915_WRITE(reg, temp);
4235 udelay(2); /* should be 1.5us */
4237 for (i = 0; i < 4; i++) {
4238 reg = FDI_RX_IIR(pipe);
4239 temp = I915_READ(reg);
4240 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4242 if (temp & FDI_RX_SYMBOL_LOCK ||
4243 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4244 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4245 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4249 udelay(2); /* should be 1.5us */
4252 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4256 DRM_DEBUG_KMS("FDI train done.\n");
4259 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4261 struct drm_device *dev = intel_crtc->base.dev;
4262 struct drm_i915_private *dev_priv = to_i915(dev);
4263 int pipe = intel_crtc->pipe;
4267 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4268 reg = FDI_RX_CTL(pipe);
4269 temp = I915_READ(reg);
4270 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4271 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4272 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4273 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4278 /* Switch from Rawclk to PCDclk */
4279 temp = I915_READ(reg);
4280 I915_WRITE(reg, temp | FDI_PCDCLK);
4285 /* Enable CPU FDI TX PLL, always on for Ironlake */
4286 reg = FDI_TX_CTL(pipe);
4287 temp = I915_READ(reg);
4288 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4289 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4296 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4298 struct drm_device *dev = intel_crtc->base.dev;
4299 struct drm_i915_private *dev_priv = to_i915(dev);
4300 int pipe = intel_crtc->pipe;
4304 /* Switch from PCDclk to Rawclk */
4305 reg = FDI_RX_CTL(pipe);
4306 temp = I915_READ(reg);
4307 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4309 /* Disable CPU FDI TX PLL */
4310 reg = FDI_TX_CTL(pipe);
4311 temp = I915_READ(reg);
4312 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4317 reg = FDI_RX_CTL(pipe);
4318 temp = I915_READ(reg);
4319 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4321 /* Wait for the clocks to turn off. */
4326 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4328 struct drm_device *dev = crtc->dev;
4329 struct drm_i915_private *dev_priv = to_i915(dev);
4330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4331 int pipe = intel_crtc->pipe;
4335 /* disable CPU FDI tx and PCH FDI rx */
4336 reg = FDI_TX_CTL(pipe);
4337 temp = I915_READ(reg);
4338 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4341 reg = FDI_RX_CTL(pipe);
4342 temp = I915_READ(reg);
4343 temp &= ~(0x7 << 16);
4344 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4345 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4350 /* Ironlake workaround, disable clock pointer after downing FDI */
4351 if (HAS_PCH_IBX(dev_priv))
4352 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4354 /* still set train pattern 1 */
4355 reg = FDI_TX_CTL(pipe);
4356 temp = I915_READ(reg);
4357 temp &= ~FDI_LINK_TRAIN_NONE;
4358 temp |= FDI_LINK_TRAIN_PATTERN_1;
4359 I915_WRITE(reg, temp);
4361 reg = FDI_RX_CTL(pipe);
4362 temp = I915_READ(reg);
4363 if (HAS_PCH_CPT(dev_priv)) {
4364 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4365 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4367 temp &= ~FDI_LINK_TRAIN_NONE;
4368 temp |= FDI_LINK_TRAIN_PATTERN_1;
4370 /* BPC in FDI rx is consistent with that in PIPECONF */
4371 temp &= ~(0x07 << 16);
4372 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4373 I915_WRITE(reg, temp);
4379 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4381 struct drm_crtc *crtc;
4384 drm_for_each_crtc(crtc, &dev_priv->drm) {
4385 struct drm_crtc_commit *commit;
4386 spin_lock(&crtc->commit_lock);
4387 commit = list_first_entry_or_null(&crtc->commit_list,
4388 struct drm_crtc_commit, commit_entry);
4389 cleanup_done = commit ?
4390 try_wait_for_completion(&commit->cleanup_done) : true;
4391 spin_unlock(&crtc->commit_lock);
4396 drm_crtc_wait_one_vblank(crtc);
4404 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4408 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4410 mutex_lock(&dev_priv->sb_lock);
4412 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4413 temp |= SBI_SSCCTL_DISABLE;
4414 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4416 mutex_unlock(&dev_priv->sb_lock);
4419 /* Program iCLKIP clock to the desired frequency */
4420 static void lpt_program_iclkip(struct intel_crtc *crtc)
4422 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4423 int clock = crtc->config->base.adjusted_mode.crtc_clock;
4424 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4427 lpt_disable_iclkip(dev_priv);
4429 /* The iCLK virtual clock root frequency is in MHz,
4430 * but the adjusted_mode->crtc_clock in in KHz. To get the
4431 * divisors, it is necessary to divide one by another, so we
4432 * convert the virtual clock precision to KHz here for higher
4435 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4436 u32 iclk_virtual_root_freq = 172800 * 1000;
4437 u32 iclk_pi_range = 64;
4438 u32 desired_divisor;
4440 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4442 divsel = (desired_divisor / iclk_pi_range) - 2;
4443 phaseinc = desired_divisor % iclk_pi_range;
4446 * Near 20MHz is a corner case which is
4447 * out of range for the 7-bit divisor
4453 /* This should not happen with any sane values */
4454 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4455 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4456 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4457 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4459 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4466 mutex_lock(&dev_priv->sb_lock);
4468 /* Program SSCDIVINTPHASE6 */
4469 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4470 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4471 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4472 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4473 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4474 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4475 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4476 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4478 /* Program SSCAUXDIV */
4479 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4480 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4481 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4482 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4484 /* Enable modulator and associated divider */
4485 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4486 temp &= ~SBI_SSCCTL_DISABLE;
4487 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4489 mutex_unlock(&dev_priv->sb_lock);
4491 /* Wait for initialization time */
4494 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4497 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4499 u32 divsel, phaseinc, auxdiv;
4500 u32 iclk_virtual_root_freq = 172800 * 1000;
4501 u32 iclk_pi_range = 64;
4502 u32 desired_divisor;
4505 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4508 mutex_lock(&dev_priv->sb_lock);
4510 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4511 if (temp & SBI_SSCCTL_DISABLE) {
4512 mutex_unlock(&dev_priv->sb_lock);
4516 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4517 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4518 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4519 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4520 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4522 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4523 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4524 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4526 mutex_unlock(&dev_priv->sb_lock);
4528 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4530 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4531 desired_divisor << auxdiv);
4534 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4535 enum pipe pch_transcoder)
4537 struct drm_device *dev = crtc->base.dev;
4538 struct drm_i915_private *dev_priv = to_i915(dev);
4539 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4541 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4542 I915_READ(HTOTAL(cpu_transcoder)));
4543 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4544 I915_READ(HBLANK(cpu_transcoder)));
4545 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4546 I915_READ(HSYNC(cpu_transcoder)));
4548 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4549 I915_READ(VTOTAL(cpu_transcoder)));
4550 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4551 I915_READ(VBLANK(cpu_transcoder)));
4552 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4553 I915_READ(VSYNC(cpu_transcoder)));
4554 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4555 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4558 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4560 struct drm_i915_private *dev_priv = to_i915(dev);
4563 temp = I915_READ(SOUTH_CHICKEN1);
4564 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4567 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4570 temp &= ~FDI_BC_BIFURCATION_SELECT;
4572 temp |= FDI_BC_BIFURCATION_SELECT;
4574 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4575 I915_WRITE(SOUTH_CHICKEN1, temp);
4576 POSTING_READ(SOUTH_CHICKEN1);
4579 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4581 struct drm_device *dev = intel_crtc->base.dev;
4583 switch (intel_crtc->pipe) {
4587 if (intel_crtc->config->fdi_lanes > 2)
4588 cpt_set_fdi_bc_bifurcation(dev, false);
4590 cpt_set_fdi_bc_bifurcation(dev, true);
4594 cpt_set_fdi_bc_bifurcation(dev, true);
4603 * Finds the encoder associated with the given CRTC. This can only be
4604 * used when we know that the CRTC isn't feeding multiple encoders!
4606 static struct intel_encoder *
4607 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
4608 const struct intel_crtc_state *crtc_state)
4610 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4611 const struct drm_connector_state *connector_state;
4612 const struct drm_connector *connector;
4613 struct intel_encoder *encoder = NULL;
4614 int num_encoders = 0;
4617 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4618 if (connector_state->crtc != &crtc->base)
4621 encoder = to_intel_encoder(connector_state->best_encoder);
4625 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
4626 num_encoders, pipe_name(crtc->pipe));
4632 * Enable PCH resources required for PCH ports:
4634 * - FDI training & RX/TX
4635 * - update transcoder timings
4636 * - DP transcoding bits
4639 static void ironlake_pch_enable(const struct intel_atomic_state *state,
4640 const struct intel_crtc_state *crtc_state)
4642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4643 struct drm_device *dev = crtc->base.dev;
4644 struct drm_i915_private *dev_priv = to_i915(dev);
4645 int pipe = crtc->pipe;
4648 assert_pch_transcoder_disabled(dev_priv, pipe);
4650 if (IS_IVYBRIDGE(dev_priv))
4651 ivybridge_update_fdi_bc_bifurcation(crtc);
4653 /* Write the TU size bits before fdi link training, so that error
4654 * detection works. */
4655 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4656 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4658 /* For PCH output, training FDI link */
4659 dev_priv->display.fdi_link_train(crtc, crtc_state);
4661 /* We need to program the right clock selection before writing the pixel
4662 * mutliplier into the DPLL. */
4663 if (HAS_PCH_CPT(dev_priv)) {
4666 temp = I915_READ(PCH_DPLL_SEL);
4667 temp |= TRANS_DPLL_ENABLE(pipe);
4668 sel = TRANS_DPLLB_SEL(pipe);
4669 if (crtc_state->shared_dpll ==
4670 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4674 I915_WRITE(PCH_DPLL_SEL, temp);
4677 /* XXX: pch pll's can be enabled any time before we enable the PCH
4678 * transcoder, and we actually should do this to not upset any PCH
4679 * transcoder that already use the clock when we share it.
4681 * Note that enable_shared_dpll tries to do the right thing, but
4682 * get_shared_dpll unconditionally resets the pll - we need that to have
4683 * the right LVDS enable sequence. */
4684 intel_enable_shared_dpll(crtc);
4686 /* set transcoder timing, panel must allow it */
4687 assert_panel_unlocked(dev_priv, pipe);
4688 ironlake_pch_transcoder_set_timings(crtc, pipe);
4690 intel_fdi_normal_train(crtc);
4692 /* For PCH DP, enable TRANS_DP_CTL */
4693 if (HAS_PCH_CPT(dev_priv) &&
4694 intel_crtc_has_dp_encoder(crtc_state)) {
4695 const struct drm_display_mode *adjusted_mode =
4696 &crtc_state->base.adjusted_mode;
4697 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4698 i915_reg_t reg = TRANS_DP_CTL(pipe);
4701 temp = I915_READ(reg);
4702 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4703 TRANS_DP_SYNC_MASK |
4705 temp |= TRANS_DP_OUTPUT_ENABLE;
4706 temp |= bpc << 9; /* same format but at 11:9 */
4708 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4709 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4710 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4711 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4713 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
4714 WARN_ON(port < PORT_B || port > PORT_D);
4715 temp |= TRANS_DP_PORT_SEL(port);
4717 I915_WRITE(reg, temp);
4720 ironlake_enable_pch_transcoder(dev_priv, pipe);
4723 static void lpt_pch_enable(const struct intel_atomic_state *state,
4724 const struct intel_crtc_state *crtc_state)
4726 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4727 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4728 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4730 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4732 lpt_program_iclkip(crtc);
4734 /* Set transcoder timing. */
4735 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4737 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4740 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4742 struct drm_i915_private *dev_priv = to_i915(dev);
4743 i915_reg_t dslreg = PIPEDSL(pipe);
4746 temp = I915_READ(dslreg);
4748 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4749 if (wait_for(I915_READ(dslreg) != temp, 5))
4750 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4755 * The hardware phase 0.0 refers to the center of the pixel.
4756 * We want to start from the top/left edge which is phase
4757 * -0.5. That matches how the hardware calculates the scaling
4758 * factors (from top-left of the first pixel to bottom-right
4759 * of the last pixel, as opposed to the pixel centers).
4761 * For 4:2:0 subsampled chroma planes we obviously have to
4762 * adjust that so that the chroma sample position lands in
4765 * Note that for packed YCbCr 4:2:2 formats there is no way to
4766 * control chroma siting. The hardware simply replicates the
4767 * chroma samples for both of the luma samples, and thus we don't
4768 * actually get the expected MPEG2 chroma siting convention :(
4769 * The same behaviour is observed on pre-SKL platforms as well.
4771 u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
4773 int phase = -0x8000;
4777 phase += (sub - 1) * 0x8000 / sub;
4780 phase = 0x10000 + phase;
4782 trip = PS_PHASE_TRIP;
4784 return ((phase >> 2) & PS_PHASE_MASK) | trip;
4788 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4789 unsigned int scaler_user, int *scaler_id,
4790 int src_w, int src_h, int dst_w, int dst_h,
4791 bool plane_scaler_check,
4792 uint32_t pixel_format)
4794 struct intel_crtc_scaler_state *scaler_state =
4795 &crtc_state->scaler_state;
4796 struct intel_crtc *intel_crtc =
4797 to_intel_crtc(crtc_state->base.crtc);
4798 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4799 const struct drm_display_mode *adjusted_mode =
4800 &crtc_state->base.adjusted_mode;
4804 * Src coordinates are already rotated by 270 degrees for
4805 * the 90/270 degree plane rotation cases (to match the
4806 * GTT mapping), hence no need to account for rotation here.
4808 need_scaling = src_w != dst_w || src_h != dst_h;
4810 if (plane_scaler_check)
4811 if (pixel_format == DRM_FORMAT_NV12)
4812 need_scaling = true;
4814 if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4815 need_scaling = true;
4818 * Scaling/fitting not supported in IF-ID mode in GEN9+
4819 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4820 * Once NV12 is enabled, handle it here while allocating scaler
4823 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4824 need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4825 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4830 * if plane is being disabled or scaler is no more required or force detach
4831 * - free scaler binded to this plane/crtc
4832 * - in order to do this, update crtc->scaler_usage
4834 * Here scaler state in crtc_state is set free so that
4835 * scaler can be assigned to other user. Actual register
4836 * update to free the scaler is done in plane/panel-fit programming.
4837 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4839 if (force_detach || !need_scaling) {
4840 if (*scaler_id >= 0) {
4841 scaler_state->scaler_users &= ~(1 << scaler_user);
4842 scaler_state->scalers[*scaler_id].in_use = 0;
4844 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4845 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4846 intel_crtc->pipe, scaler_user, *scaler_id,
4847 scaler_state->scaler_users);
4853 if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4854 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
4855 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4860 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4861 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4862 (IS_GEN11(dev_priv) &&
4863 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4864 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4865 (!IS_GEN11(dev_priv) &&
4866 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4867 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4868 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4869 "size is out of scaler range\n",
4870 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4874 /* mark this plane as a scaler user in crtc_state */
4875 scaler_state->scaler_users |= (1 << scaler_user);
4876 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4877 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4878 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4879 scaler_state->scaler_users);
4885 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4887 * @state: crtc's scaler state
4890 * 0 - scaler_usage updated successfully
4891 * error - requested scaling cannot be supported or other error condition
4893 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4895 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4897 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4898 &state->scaler_state.scaler_id,
4899 state->pipe_src_w, state->pipe_src_h,
4900 adjusted_mode->crtc_hdisplay,
4901 adjusted_mode->crtc_vdisplay, false, 0);
4905 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4906 * @crtc_state: crtc's scaler state
4907 * @plane_state: atomic plane state to update
4910 * 0 - scaler_usage updated successfully
4911 * error - requested scaling cannot be supported or other error condition
4913 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4914 struct intel_plane_state *plane_state)
4917 struct intel_plane *intel_plane =
4918 to_intel_plane(plane_state->base.plane);
4919 struct drm_framebuffer *fb = plane_state->base.fb;
4922 bool force_detach = !fb || !plane_state->base.visible;
4924 ret = skl_update_scaler(crtc_state, force_detach,
4925 drm_plane_index(&intel_plane->base),
4926 &plane_state->scaler_id,
4927 drm_rect_width(&plane_state->base.src) >> 16,
4928 drm_rect_height(&plane_state->base.src) >> 16,
4929 drm_rect_width(&plane_state->base.dst),
4930 drm_rect_height(&plane_state->base.dst),
4931 fb ? true : false, fb ? fb->format->format : 0);
4933 if (ret || plane_state->scaler_id < 0)
4936 /* check colorkey */
4937 if (plane_state->ckey.flags) {
4938 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4939 intel_plane->base.base.id,
4940 intel_plane->base.name);
4944 /* Check src format */
4945 switch (fb->format->format) {
4946 case DRM_FORMAT_RGB565:
4947 case DRM_FORMAT_XBGR8888:
4948 case DRM_FORMAT_XRGB8888:
4949 case DRM_FORMAT_ABGR8888:
4950 case DRM_FORMAT_ARGB8888:
4951 case DRM_FORMAT_XRGB2101010:
4952 case DRM_FORMAT_XBGR2101010:
4953 case DRM_FORMAT_YUYV:
4954 case DRM_FORMAT_YVYU:
4955 case DRM_FORMAT_UYVY:
4956 case DRM_FORMAT_VYUY:
4957 case DRM_FORMAT_NV12:
4960 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4961 intel_plane->base.base.id, intel_plane->base.name,
4962 fb->base.id, fb->format->format);
4969 static void skylake_scaler_disable(struct intel_crtc *crtc)
4973 for (i = 0; i < crtc->num_scalers; i++)
4974 skl_detach_scaler(crtc, i);
4977 static void skylake_pfit_enable(struct intel_crtc *crtc)
4979 struct drm_device *dev = crtc->base.dev;
4980 struct drm_i915_private *dev_priv = to_i915(dev);
4981 int pipe = crtc->pipe;
4982 struct intel_crtc_scaler_state *scaler_state =
4983 &crtc->config->scaler_state;
4985 if (crtc->config->pch_pfit.enabled) {
4986 u16 uv_rgb_hphase, uv_rgb_vphase;
4989 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4992 uv_rgb_hphase = skl_scaler_calc_phase(1, false);
4993 uv_rgb_vphase = skl_scaler_calc_phase(1, false);
4995 id = scaler_state->scaler_id;
4996 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4997 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4998 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
4999 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5000 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5001 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5002 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
5003 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
5007 static void ironlake_pfit_enable(struct intel_crtc *crtc)
5009 struct drm_device *dev = crtc->base.dev;
5010 struct drm_i915_private *dev_priv = to_i915(dev);
5011 int pipe = crtc->pipe;
5013 if (crtc->config->pch_pfit.enabled) {
5014 /* Force use of hard-coded filter coefficients
5015 * as some pre-programmed values are broken,
5018 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5019 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5020 PF_PIPE_SEL_IVB(pipe));
5022 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5023 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
5024 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
5028 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5030 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5031 struct drm_device *dev = crtc->base.dev;
5032 struct drm_i915_private *dev_priv = to_i915(dev);
5034 if (!crtc_state->ips_enabled)
5038 * We can only enable IPS after we enable a plane and wait for a vblank
5039 * This function is called from post_plane_update, which is run after
5042 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5044 if (IS_BROADWELL(dev_priv)) {
5045 mutex_lock(&dev_priv->pcu_lock);
5046 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5047 IPS_ENABLE | IPS_PCODE_CONTROL));
5048 mutex_unlock(&dev_priv->pcu_lock);
5049 /* Quoting Art Runyan: "its not safe to expect any particular
5050 * value in IPS_CTL bit 31 after enabling IPS through the
5051 * mailbox." Moreover, the mailbox may return a bogus state,
5052 * so we need to just enable it and continue on.
5055 I915_WRITE(IPS_CTL, IPS_ENABLE);
5056 /* The bit only becomes 1 in the next vblank, so this wait here
5057 * is essentially intel_wait_for_vblank. If we don't have this
5058 * and don't wait for vblanks until the end of crtc_enable, then
5059 * the HW state readout code will complain that the expected
5060 * IPS_CTL value is not the one we read. */
5061 if (intel_wait_for_register(dev_priv,
5062 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
5064 DRM_ERROR("Timed out waiting for IPS enable\n");
5068 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5071 struct drm_device *dev = crtc->base.dev;
5072 struct drm_i915_private *dev_priv = to_i915(dev);
5074 if (!crtc_state->ips_enabled)
5077 if (IS_BROADWELL(dev_priv)) {
5078 mutex_lock(&dev_priv->pcu_lock);
5079 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5080 mutex_unlock(&dev_priv->pcu_lock);
5081 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
5082 if (intel_wait_for_register(dev_priv,
5083 IPS_CTL, IPS_ENABLE, 0,
5085 DRM_ERROR("Timed out waiting for IPS disable\n");
5087 I915_WRITE(IPS_CTL, 0);
5088 POSTING_READ(IPS_CTL);
5091 /* We need to wait for a vblank before we can disable the plane. */
5092 intel_wait_for_vblank(dev_priv, crtc->pipe);
5095 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5097 if (intel_crtc->overlay) {
5098 struct drm_device *dev = intel_crtc->base.dev;
5100 mutex_lock(&dev->struct_mutex);
5101 (void) intel_overlay_switch_off(intel_crtc->overlay);
5102 mutex_unlock(&dev->struct_mutex);
5105 /* Let userspace switch the overlay on again. In most cases userspace
5106 * has to recompute where to put it anyway.
5111 * intel_post_enable_primary - Perform operations after enabling primary plane
5112 * @crtc: the CRTC whose primary plane was just enabled
5113 * @new_crtc_state: the enabling state
5115 * Performs potentially sleeping operations that must be done after the primary
5116 * plane is enabled, such as updating FBC and IPS. Note that this may be
5117 * called due to an explicit primary plane update, or due to an implicit
5118 * re-enable that is caused when a sprite plane is updated to no longer
5119 * completely hide the primary plane.
5122 intel_post_enable_primary(struct drm_crtc *crtc,
5123 const struct intel_crtc_state *new_crtc_state)
5125 struct drm_device *dev = crtc->dev;
5126 struct drm_i915_private *dev_priv = to_i915(dev);
5127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128 int pipe = intel_crtc->pipe;
5131 * Gen2 reports pipe underruns whenever all planes are disabled.
5132 * So don't enable underrun reporting before at least some planes
5134 * FIXME: Need to fix the logic to work when we turn off all planes
5135 * but leave the pipe running.
5137 if (IS_GEN2(dev_priv))
5138 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5140 /* Underruns don't always raise interrupts, so check manually. */
5141 intel_check_cpu_fifo_underruns(dev_priv);
5142 intel_check_pch_fifo_underruns(dev_priv);
5145 /* FIXME get rid of this and use pre_plane_update */
5147 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5149 struct drm_device *dev = crtc->dev;
5150 struct drm_i915_private *dev_priv = to_i915(dev);
5151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5152 int pipe = intel_crtc->pipe;
5155 * Gen2 reports pipe underruns whenever all planes are disabled.
5156 * So disable underrun reporting before all the planes get disabled.
5158 if (IS_GEN2(dev_priv))
5159 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5161 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5164 * Vblank time updates from the shadow to live plane control register
5165 * are blocked if the memory self-refresh mode is active at that
5166 * moment. So to make sure the plane gets truly disabled, disable
5167 * first the self-refresh mode. The self-refresh enable bit in turn
5168 * will be checked/applied by the HW only at the next frame start
5169 * event which is after the vblank start event, so we need to have a
5170 * wait-for-vblank between disabling the plane and the pipe.
5172 if (HAS_GMCH_DISPLAY(dev_priv) &&
5173 intel_set_memory_cxsr(dev_priv, false))
5174 intel_wait_for_vblank(dev_priv, pipe);
5177 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5178 const struct intel_crtc_state *new_crtc_state)
5180 if (!old_crtc_state->ips_enabled)
5183 if (needs_modeset(&new_crtc_state->base))
5186 return !new_crtc_state->ips_enabled;
5189 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5190 const struct intel_crtc_state *new_crtc_state)
5192 if (!new_crtc_state->ips_enabled)
5195 if (needs_modeset(&new_crtc_state->base))
5199 * We can't read out IPS on broadwell, assume the worst and
5200 * forcibly enable IPS on the first fastset.
5202 if (new_crtc_state->update_pipe &&
5203 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5206 return !old_crtc_state->ips_enabled;
5209 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5210 const struct intel_crtc_state *crtc_state)
5212 if (!crtc_state->nv12_planes)
5215 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
5218 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5219 IS_CANNONLAKE(dev_priv))
5225 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5227 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5228 struct drm_device *dev = crtc->base.dev;
5229 struct drm_i915_private *dev_priv = to_i915(dev);
5230 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5231 struct intel_crtc_state *pipe_config =
5232 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5234 struct drm_plane *primary = crtc->base.primary;
5235 struct drm_plane_state *old_primary_state =
5236 drm_atomic_get_old_plane_state(old_state, primary);
5238 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5240 if (pipe_config->update_wm_post && pipe_config->base.active)
5241 intel_update_watermarks(crtc);
5243 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5244 hsw_enable_ips(pipe_config);
5246 if (old_primary_state) {
5247 struct drm_plane_state *new_primary_state =
5248 drm_atomic_get_new_plane_state(old_state, primary);
5250 intel_fbc_post_update(crtc);
5252 if (new_primary_state->visible &&
5253 (needs_modeset(&pipe_config->base) ||
5254 !old_primary_state->visible))
5255 intel_post_enable_primary(&crtc->base, pipe_config);
5258 /* Display WA 827 */
5259 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5260 !needs_nv12_wa(dev_priv, pipe_config)) {
5261 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5262 skl_wa_528(dev_priv, crtc->pipe, false);
5266 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5267 struct intel_crtc_state *pipe_config)
5269 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5270 struct drm_device *dev = crtc->base.dev;
5271 struct drm_i915_private *dev_priv = to_i915(dev);
5272 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5273 struct drm_plane *primary = crtc->base.primary;
5274 struct drm_plane_state *old_primary_state =
5275 drm_atomic_get_old_plane_state(old_state, primary);
5276 bool modeset = needs_modeset(&pipe_config->base);
5277 struct intel_atomic_state *old_intel_state =
5278 to_intel_atomic_state(old_state);
5280 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5281 hsw_disable_ips(old_crtc_state);
5283 if (old_primary_state) {
5284 struct intel_plane_state *new_primary_state =
5285 intel_atomic_get_new_plane_state(old_intel_state,
5286 to_intel_plane(primary));
5288 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5290 * Gen2 reports pipe underruns whenever all planes are disabled.
5291 * So disable underrun reporting before all the planes get disabled.
5293 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5294 (modeset || !new_primary_state->base.visible))
5295 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5298 /* Display WA 827 */
5299 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5300 needs_nv12_wa(dev_priv, pipe_config)) {
5301 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5302 skl_wa_528(dev_priv, crtc->pipe, true);
5306 * Vblank time updates from the shadow to live plane control register
5307 * are blocked if the memory self-refresh mode is active at that
5308 * moment. So to make sure the plane gets truly disabled, disable
5309 * first the self-refresh mode. The self-refresh enable bit in turn
5310 * will be checked/applied by the HW only at the next frame start
5311 * event which is after the vblank start event, so we need to have a
5312 * wait-for-vblank between disabling the plane and the pipe.
5314 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5315 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5316 intel_wait_for_vblank(dev_priv, crtc->pipe);
5319 * IVB workaround: must disable low power watermarks for at least
5320 * one frame before enabling scaling. LP watermarks can be re-enabled
5321 * when scaling is disabled.
5323 * WaCxSRDisabledForSpriteScaling:ivb
5325 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5326 intel_wait_for_vblank(dev_priv, crtc->pipe);
5329 * If we're doing a modeset, we're done. No need to do any pre-vblank
5330 * watermark programming here.
5332 if (needs_modeset(&pipe_config->base))
5336 * For platforms that support atomic watermarks, program the
5337 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5338 * will be the intermediate values that are safe for both pre- and
5339 * post- vblank; when vblank happens, the 'active' values will be set
5340 * to the final 'target' values and we'll do this again to get the
5341 * optimal watermarks. For gen9+ platforms, the values we program here
5342 * will be the final target values which will get automatically latched
5343 * at vblank time; no further programming will be necessary.
5345 * If a platform hasn't been transitioned to atomic watermarks yet,
5346 * we'll continue to update watermarks the old way, if flags tell
5349 if (dev_priv->display.initial_watermarks != NULL)
5350 dev_priv->display.initial_watermarks(old_intel_state,
5352 else if (pipe_config->update_wm_pre)
5353 intel_update_watermarks(crtc);
5356 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5358 struct drm_device *dev = crtc->dev;
5359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5360 struct drm_plane *p;
5361 int pipe = intel_crtc->pipe;
5363 intel_crtc_dpms_overlay_disable(intel_crtc);
5365 drm_for_each_plane_mask(p, dev, plane_mask)
5366 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5369 * FIXME: Once we grow proper nuclear flip support out of this we need
5370 * to compute the mask of flip planes precisely. For the time being
5371 * consider this a flip to a NULL plane.
5373 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5376 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5377 struct intel_crtc_state *crtc_state,
5378 struct drm_atomic_state *old_state)
5380 struct drm_connector_state *conn_state;
5381 struct drm_connector *conn;
5384 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5385 struct intel_encoder *encoder =
5386 to_intel_encoder(conn_state->best_encoder);
5388 if (conn_state->crtc != crtc)
5391 if (encoder->pre_pll_enable)
5392 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5396 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5397 struct intel_crtc_state *crtc_state,
5398 struct drm_atomic_state *old_state)
5400 struct drm_connector_state *conn_state;
5401 struct drm_connector *conn;
5404 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5405 struct intel_encoder *encoder =
5406 to_intel_encoder(conn_state->best_encoder);
5408 if (conn_state->crtc != crtc)
5411 if (encoder->pre_enable)
5412 encoder->pre_enable(encoder, crtc_state, conn_state);
5416 static void intel_encoders_enable(struct drm_crtc *crtc,
5417 struct intel_crtc_state *crtc_state,
5418 struct drm_atomic_state *old_state)
5420 struct drm_connector_state *conn_state;
5421 struct drm_connector *conn;
5424 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5425 struct intel_encoder *encoder =
5426 to_intel_encoder(conn_state->best_encoder);
5428 if (conn_state->crtc != crtc)
5431 encoder->enable(encoder, crtc_state, conn_state);
5432 intel_opregion_notify_encoder(encoder, true);
5436 static void intel_encoders_disable(struct drm_crtc *crtc,
5437 struct intel_crtc_state *old_crtc_state,
5438 struct drm_atomic_state *old_state)
5440 struct drm_connector_state *old_conn_state;
5441 struct drm_connector *conn;
5444 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5445 struct intel_encoder *encoder =
5446 to_intel_encoder(old_conn_state->best_encoder);
5448 if (old_conn_state->crtc != crtc)
5451 intel_opregion_notify_encoder(encoder, false);
5452 encoder->disable(encoder, old_crtc_state, old_conn_state);
5456 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5457 struct intel_crtc_state *old_crtc_state,
5458 struct drm_atomic_state *old_state)
5460 struct drm_connector_state *old_conn_state;
5461 struct drm_connector *conn;
5464 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5465 struct intel_encoder *encoder =
5466 to_intel_encoder(old_conn_state->best_encoder);
5468 if (old_conn_state->crtc != crtc)
5471 if (encoder->post_disable)
5472 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5476 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5477 struct intel_crtc_state *old_crtc_state,
5478 struct drm_atomic_state *old_state)
5480 struct drm_connector_state *old_conn_state;
5481 struct drm_connector *conn;
5484 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5485 struct intel_encoder *encoder =
5486 to_intel_encoder(old_conn_state->best_encoder);
5488 if (old_conn_state->crtc != crtc)
5491 if (encoder->post_pll_disable)
5492 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5496 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5497 struct drm_atomic_state *old_state)
5499 struct drm_crtc *crtc = pipe_config->base.crtc;
5500 struct drm_device *dev = crtc->dev;
5501 struct drm_i915_private *dev_priv = to_i915(dev);
5502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5503 int pipe = intel_crtc->pipe;
5504 struct intel_atomic_state *old_intel_state =
5505 to_intel_atomic_state(old_state);
5507 if (WARN_ON(intel_crtc->active))
5511 * Sometimes spurious CPU pipe underruns happen during FDI
5512 * training, at least with VGA+HDMI cloning. Suppress them.
5514 * On ILK we get an occasional spurious CPU pipe underruns
5515 * between eDP port A enable and vdd enable. Also PCH port
5516 * enable seems to result in the occasional CPU pipe underrun.
5518 * Spurious PCH underruns also occur during PCH enabling.
5520 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5521 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5523 if (intel_crtc->config->has_pch_encoder)
5524 intel_prepare_shared_dpll(intel_crtc);
5526 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5527 intel_dp_set_m_n(intel_crtc, M1_N1);
5529 intel_set_pipe_timings(intel_crtc);
5530 intel_set_pipe_src_size(intel_crtc);
5532 if (intel_crtc->config->has_pch_encoder) {
5533 intel_cpu_transcoder_set_m_n(intel_crtc,
5534 &intel_crtc->config->fdi_m_n, NULL);
5537 ironlake_set_pipeconf(crtc);
5539 intel_crtc->active = true;
5541 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5543 if (intel_crtc->config->has_pch_encoder) {
5544 /* Note: FDI PLL enabling _must_ be done before we enable the
5545 * cpu pipes, hence this is separate from all the other fdi/pch
5547 ironlake_fdi_pll_enable(intel_crtc);
5549 assert_fdi_tx_disabled(dev_priv, pipe);
5550 assert_fdi_rx_disabled(dev_priv, pipe);
5553 ironlake_pfit_enable(intel_crtc);
5556 * On ILK+ LUT must be loaded before the pipe is running but with
5559 intel_color_load_luts(&pipe_config->base);
5561 if (dev_priv->display.initial_watermarks != NULL)
5562 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5563 intel_enable_pipe(pipe_config);
5565 if (intel_crtc->config->has_pch_encoder)
5566 ironlake_pch_enable(old_intel_state, pipe_config);
5568 assert_vblank_disabled(crtc);
5569 drm_crtc_vblank_on(crtc);
5571 intel_encoders_enable(crtc, pipe_config, old_state);
5573 if (HAS_PCH_CPT(dev_priv))
5574 cpt_verify_modeset(dev, intel_crtc->pipe);
5577 * Must wait for vblank to avoid spurious PCH FIFO underruns.
5578 * And a second vblank wait is needed at least on ILK with
5579 * some interlaced HDMI modes. Let's do the double wait always
5580 * in case there are more corner cases we don't know about.
5582 if (intel_crtc->config->has_pch_encoder) {
5583 intel_wait_for_vblank(dev_priv, pipe);
5584 intel_wait_for_vblank(dev_priv, pipe);
5586 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5587 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5590 /* IPS only exists on ULT machines and is tied to pipe A. */
5591 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5593 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5596 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5597 enum pipe pipe, bool apply)
5599 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5600 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5607 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5610 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5612 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5613 enum pipe pipe = crtc->pipe;
5616 val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5618 /* Program B credit equally to all pipes */
5619 val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5621 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5624 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5625 struct drm_atomic_state *old_state)
5627 struct drm_crtc *crtc = pipe_config->base.crtc;
5628 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5631 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5632 struct intel_atomic_state *old_intel_state =
5633 to_intel_atomic_state(old_state);
5634 bool psl_clkgate_wa;
5637 if (WARN_ON(intel_crtc->active))
5640 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5642 if (intel_crtc->config->shared_dpll)
5643 intel_enable_shared_dpll(intel_crtc);
5645 if (INTEL_GEN(dev_priv) >= 11)
5646 icl_map_plls_to_ports(crtc, pipe_config, old_state);
5648 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5650 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5651 intel_dp_set_m_n(intel_crtc, M1_N1);
5653 if (!transcoder_is_dsi(cpu_transcoder))
5654 intel_set_pipe_timings(intel_crtc);
5656 intel_set_pipe_src_size(intel_crtc);
5658 if (cpu_transcoder != TRANSCODER_EDP &&
5659 !transcoder_is_dsi(cpu_transcoder)) {
5660 I915_WRITE(PIPE_MULT(cpu_transcoder),
5661 intel_crtc->config->pixel_multiplier - 1);
5664 if (intel_crtc->config->has_pch_encoder) {
5665 intel_cpu_transcoder_set_m_n(intel_crtc,
5666 &intel_crtc->config->fdi_m_n, NULL);
5669 if (!transcoder_is_dsi(cpu_transcoder))
5670 haswell_set_pipeconf(crtc);
5672 haswell_set_pipemisc(crtc);
5674 intel_color_set_csc(&pipe_config->base);
5676 intel_crtc->active = true;
5678 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5679 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5680 intel_crtc->config->pch_pfit.enabled;
5682 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5684 if (INTEL_GEN(dev_priv) >= 9)
5685 skylake_pfit_enable(intel_crtc);
5687 ironlake_pfit_enable(intel_crtc);
5690 * On ILK+ LUT must be loaded before the pipe is running but with
5693 intel_color_load_luts(&pipe_config->base);
5696 * Display WA #1153: enable hardware to bypass the alpha math
5697 * and rounding for per-pixel values 00 and 0xff
5699 if (INTEL_GEN(dev_priv) >= 11) {
5700 pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
5701 if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
5702 I915_WRITE_FW(PIPE_CHICKEN(pipe),
5703 pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
5706 intel_ddi_set_pipe_settings(pipe_config);
5707 if (!transcoder_is_dsi(cpu_transcoder))
5708 intel_ddi_enable_transcoder_func(pipe_config);
5710 if (dev_priv->display.initial_watermarks != NULL)
5711 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5713 if (INTEL_GEN(dev_priv) >= 11)
5714 icl_pipe_mbus_enable(intel_crtc);
5716 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5717 if (!transcoder_is_dsi(cpu_transcoder))
5718 intel_enable_pipe(pipe_config);
5720 if (intel_crtc->config->has_pch_encoder)
5721 lpt_pch_enable(old_intel_state, pipe_config);
5723 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5724 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5726 assert_vblank_disabled(crtc);
5727 drm_crtc_vblank_on(crtc);
5729 intel_encoders_enable(crtc, pipe_config, old_state);
5731 if (psl_clkgate_wa) {
5732 intel_wait_for_vblank(dev_priv, pipe);
5733 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5736 /* If we change the relative order between pipe/planes enabling, we need
5737 * to change the workaround. */
5738 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5739 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5740 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5741 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5745 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5747 struct drm_device *dev = crtc->base.dev;
5748 struct drm_i915_private *dev_priv = to_i915(dev);
5749 int pipe = crtc->pipe;
5751 /* To avoid upsetting the power well on haswell only disable the pfit if
5752 * it's in use. The hw state code will make sure we get this right. */
5753 if (force || crtc->config->pch_pfit.enabled) {
5754 I915_WRITE(PF_CTL(pipe), 0);
5755 I915_WRITE(PF_WIN_POS(pipe), 0);
5756 I915_WRITE(PF_WIN_SZ(pipe), 0);
5760 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5761 struct drm_atomic_state *old_state)
5763 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5764 struct drm_device *dev = crtc->dev;
5765 struct drm_i915_private *dev_priv = to_i915(dev);
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 int pipe = intel_crtc->pipe;
5770 * Sometimes spurious CPU pipe underruns happen when the
5771 * pipe is already disabled, but FDI RX/TX is still enabled.
5772 * Happens at least with VGA+HDMI cloning. Suppress them.
5774 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5775 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5777 intel_encoders_disable(crtc, old_crtc_state, old_state);
5779 drm_crtc_vblank_off(crtc);
5780 assert_vblank_disabled(crtc);
5782 intel_disable_pipe(old_crtc_state);
5784 ironlake_pfit_disable(intel_crtc, false);
5786 if (intel_crtc->config->has_pch_encoder)
5787 ironlake_fdi_disable(crtc);
5789 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5791 if (intel_crtc->config->has_pch_encoder) {
5792 ironlake_disable_pch_transcoder(dev_priv, pipe);
5794 if (HAS_PCH_CPT(dev_priv)) {
5798 /* disable TRANS_DP_CTL */
5799 reg = TRANS_DP_CTL(pipe);
5800 temp = I915_READ(reg);
5801 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5802 TRANS_DP_PORT_SEL_MASK);
5803 temp |= TRANS_DP_PORT_SEL_NONE;
5804 I915_WRITE(reg, temp);
5806 /* disable DPLL_SEL */
5807 temp = I915_READ(PCH_DPLL_SEL);
5808 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5809 I915_WRITE(PCH_DPLL_SEL, temp);
5812 ironlake_fdi_pll_disable(intel_crtc);
5815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5816 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5819 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5820 struct drm_atomic_state *old_state)
5822 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5823 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5825 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
5827 intel_encoders_disable(crtc, old_crtc_state, old_state);
5829 drm_crtc_vblank_off(crtc);
5830 assert_vblank_disabled(crtc);
5832 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5833 if (!transcoder_is_dsi(cpu_transcoder))
5834 intel_disable_pipe(old_crtc_state);
5836 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
5837 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
5839 if (!transcoder_is_dsi(cpu_transcoder))
5840 intel_ddi_disable_transcoder_func(old_crtc_state);
5842 if (INTEL_GEN(dev_priv) >= 9)
5843 skylake_scaler_disable(intel_crtc);
5845 ironlake_pfit_disable(intel_crtc, false);
5847 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5849 if (INTEL_GEN(dev_priv) >= 11)
5850 icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
5853 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5855 struct drm_device *dev = crtc->base.dev;
5856 struct drm_i915_private *dev_priv = to_i915(dev);
5857 struct intel_crtc_state *pipe_config = crtc->config;
5859 if (!pipe_config->gmch_pfit.control)
5863 * The panel fitter should only be adjusted whilst the pipe is disabled,
5864 * according to register description and PRM.
5866 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5867 assert_pipe_disabled(dev_priv, crtc->pipe);
5869 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5870 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5872 /* Border color in case we don't scale up to the full screen. Black by
5873 * default, change to something else for debugging. */
5874 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5877 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
5879 if (IS_ICELAKE(dev_priv))
5880 return port >= PORT_C && port <= PORT_F;
5885 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
5887 if (!intel_port_is_tc(dev_priv, port))
5888 return PORT_TC_NONE;
5890 return port - PORT_C;
5893 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5897 return POWER_DOMAIN_PORT_DDI_A_LANES;
5899 return POWER_DOMAIN_PORT_DDI_B_LANES;
5901 return POWER_DOMAIN_PORT_DDI_C_LANES;
5903 return POWER_DOMAIN_PORT_DDI_D_LANES;
5905 return POWER_DOMAIN_PORT_DDI_E_LANES;
5907 return POWER_DOMAIN_PORT_DDI_F_LANES;
5910 return POWER_DOMAIN_PORT_OTHER;
5914 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5915 struct intel_crtc_state *crtc_state)
5917 struct drm_device *dev = crtc->dev;
5918 struct drm_i915_private *dev_priv = to_i915(dev);
5919 struct drm_encoder *encoder;
5920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5921 enum pipe pipe = intel_crtc->pipe;
5923 enum transcoder transcoder = crtc_state->cpu_transcoder;
5925 if (!crtc_state->base.active)
5928 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5929 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5930 if (crtc_state->pch_pfit.enabled ||
5931 crtc_state->pch_pfit.force_thru)
5932 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5934 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5937 mask |= BIT_ULL(intel_encoder->power_domain);
5940 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5941 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5943 if (crtc_state->shared_dpll)
5944 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5950 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5951 struct intel_crtc_state *crtc_state)
5953 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955 enum intel_display_power_domain domain;
5956 u64 domains, new_domains, old_domains;
5958 old_domains = intel_crtc->enabled_power_domains;
5959 intel_crtc->enabled_power_domains = new_domains =
5960 get_crtc_power_domains(crtc, crtc_state);
5962 domains = new_domains & ~old_domains;
5964 for_each_power_domain(domain, domains)
5965 intel_display_power_get(dev_priv, domain);
5967 return old_domains & ~new_domains;
5970 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5973 enum intel_display_power_domain domain;
5975 for_each_power_domain(domain, domains)
5976 intel_display_power_put(dev_priv, domain);
5979 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5980 struct drm_atomic_state *old_state)
5982 struct intel_atomic_state *old_intel_state =
5983 to_intel_atomic_state(old_state);
5984 struct drm_crtc *crtc = pipe_config->base.crtc;
5985 struct drm_device *dev = crtc->dev;
5986 struct drm_i915_private *dev_priv = to_i915(dev);
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
5990 if (WARN_ON(intel_crtc->active))
5993 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5994 intel_dp_set_m_n(intel_crtc, M1_N1);
5996 intel_set_pipe_timings(intel_crtc);
5997 intel_set_pipe_src_size(intel_crtc);
5999 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6000 struct drm_i915_private *dev_priv = to_i915(dev);
6002 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6003 I915_WRITE(CHV_CANVAS(pipe), 0);
6006 i9xx_set_pipeconf(intel_crtc);
6008 intel_crtc->active = true;
6010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6012 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6014 if (IS_CHERRYVIEW(dev_priv)) {
6015 chv_prepare_pll(intel_crtc, intel_crtc->config);
6016 chv_enable_pll(intel_crtc, intel_crtc->config);
6018 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6019 vlv_enable_pll(intel_crtc, intel_crtc->config);
6022 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6024 i9xx_pfit_enable(intel_crtc);
6026 intel_color_load_luts(&pipe_config->base);
6028 dev_priv->display.initial_watermarks(old_intel_state,
6030 intel_enable_pipe(pipe_config);
6032 assert_vblank_disabled(crtc);
6033 drm_crtc_vblank_on(crtc);
6035 intel_encoders_enable(crtc, pipe_config, old_state);
6038 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6040 struct drm_device *dev = crtc->base.dev;
6041 struct drm_i915_private *dev_priv = to_i915(dev);
6043 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6044 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6047 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6048 struct drm_atomic_state *old_state)
6050 struct intel_atomic_state *old_intel_state =
6051 to_intel_atomic_state(old_state);
6052 struct drm_crtc *crtc = pipe_config->base.crtc;
6053 struct drm_device *dev = crtc->dev;
6054 struct drm_i915_private *dev_priv = to_i915(dev);
6055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6056 enum pipe pipe = intel_crtc->pipe;
6058 if (WARN_ON(intel_crtc->active))
6061 i9xx_set_pll_dividers(intel_crtc);
6063 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6064 intel_dp_set_m_n(intel_crtc, M1_N1);
6066 intel_set_pipe_timings(intel_crtc);
6067 intel_set_pipe_src_size(intel_crtc);
6069 i9xx_set_pipeconf(intel_crtc);
6071 intel_crtc->active = true;
6073 if (!IS_GEN2(dev_priv))
6074 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6076 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6078 i9xx_enable_pll(intel_crtc, pipe_config);
6080 i9xx_pfit_enable(intel_crtc);
6082 intel_color_load_luts(&pipe_config->base);
6084 if (dev_priv->display.initial_watermarks != NULL)
6085 dev_priv->display.initial_watermarks(old_intel_state,
6086 intel_crtc->config);
6088 intel_update_watermarks(intel_crtc);
6089 intel_enable_pipe(pipe_config);
6091 assert_vblank_disabled(crtc);
6092 drm_crtc_vblank_on(crtc);
6094 intel_encoders_enable(crtc, pipe_config, old_state);
6097 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6099 struct drm_device *dev = crtc->base.dev;
6100 struct drm_i915_private *dev_priv = to_i915(dev);
6102 if (!crtc->config->gmch_pfit.control)
6105 assert_pipe_disabled(dev_priv, crtc->pipe);
6107 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6108 I915_READ(PFIT_CONTROL));
6109 I915_WRITE(PFIT_CONTROL, 0);
6112 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6113 struct drm_atomic_state *old_state)
6115 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6116 struct drm_device *dev = crtc->dev;
6117 struct drm_i915_private *dev_priv = to_i915(dev);
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119 int pipe = intel_crtc->pipe;
6122 * On gen2 planes are double buffered but the pipe isn't, so we must
6123 * wait for planes to fully turn off before disabling the pipe.
6125 if (IS_GEN2(dev_priv))
6126 intel_wait_for_vblank(dev_priv, pipe);
6128 intel_encoders_disable(crtc, old_crtc_state, old_state);
6130 drm_crtc_vblank_off(crtc);
6131 assert_vblank_disabled(crtc);
6133 intel_disable_pipe(old_crtc_state);
6135 i9xx_pfit_disable(intel_crtc);
6137 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6139 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6140 if (IS_CHERRYVIEW(dev_priv))
6141 chv_disable_pll(dev_priv, pipe);
6142 else if (IS_VALLEYVIEW(dev_priv))
6143 vlv_disable_pll(dev_priv, pipe);
6145 i9xx_disable_pll(intel_crtc);
6148 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6150 if (!IS_GEN2(dev_priv))
6151 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6153 if (!dev_priv->display.initial_watermarks)
6154 intel_update_watermarks(intel_crtc);
6156 /* clock the pipe down to 640x480@60 to potentially save power */
6157 if (IS_I830(dev_priv))
6158 i830_enable_pipe(dev_priv, pipe);
6161 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6162 struct drm_modeset_acquire_ctx *ctx)
6164 struct intel_encoder *encoder;
6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6167 enum intel_display_power_domain domain;
6168 struct intel_plane *plane;
6170 struct drm_atomic_state *state;
6171 struct intel_crtc_state *crtc_state;
6174 if (!intel_crtc->active)
6177 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6178 const struct intel_plane_state *plane_state =
6179 to_intel_plane_state(plane->base.state);
6181 if (plane_state->base.visible)
6182 intel_plane_disable_noatomic(intel_crtc, plane);
6185 state = drm_atomic_state_alloc(crtc->dev);
6187 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6188 crtc->base.id, crtc->name);
6192 state->acquire_ctx = ctx;
6194 /* Everything's already locked, -EDEADLK can't happen. */
6195 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6196 ret = drm_atomic_add_affected_connectors(state, crtc);
6198 WARN_ON(IS_ERR(crtc_state) || ret);
6200 dev_priv->display.crtc_disable(crtc_state, state);
6202 drm_atomic_state_put(state);
6204 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6205 crtc->base.id, crtc->name);
6207 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6208 crtc->state->active = false;
6209 intel_crtc->active = false;
6210 crtc->enabled = false;
6211 crtc->state->connector_mask = 0;
6212 crtc->state->encoder_mask = 0;
6214 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6215 encoder->base.crtc = NULL;
6217 intel_fbc_disable(intel_crtc);
6218 intel_update_watermarks(intel_crtc);
6219 intel_disable_shared_dpll(intel_crtc);
6221 domains = intel_crtc->enabled_power_domains;
6222 for_each_power_domain(domain, domains)
6223 intel_display_power_put(dev_priv, domain);
6224 intel_crtc->enabled_power_domains = 0;
6226 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6227 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6228 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6232 * turn all crtc's off, but do not adjust state
6233 * This has to be paired with a call to intel_modeset_setup_hw_state.
6235 int intel_display_suspend(struct drm_device *dev)
6237 struct drm_i915_private *dev_priv = to_i915(dev);
6238 struct drm_atomic_state *state;
6241 state = drm_atomic_helper_suspend(dev);
6242 ret = PTR_ERR_OR_ZERO(state);
6244 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6246 dev_priv->modeset_restore_state = state;
6250 void intel_encoder_destroy(struct drm_encoder *encoder)
6252 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6254 drm_encoder_cleanup(encoder);
6255 kfree(intel_encoder);
6258 /* Cross check the actual hw state with our own modeset state tracking (and it's
6259 * internal consistency). */
6260 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6261 struct drm_connector_state *conn_state)
6263 struct intel_connector *connector = to_intel_connector(conn_state->connector);
6265 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6266 connector->base.base.id,
6267 connector->base.name);
6269 if (connector->get_hw_state(connector)) {
6270 struct intel_encoder *encoder = connector->encoder;
6272 I915_STATE_WARN(!crtc_state,
6273 "connector enabled without attached crtc\n");
6278 I915_STATE_WARN(!crtc_state->active,
6279 "connector is active, but attached crtc isn't\n");
6281 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6284 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6285 "atomic encoder doesn't match attached encoder\n");
6287 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6288 "attached encoder crtc differs from connector crtc\n");
6290 I915_STATE_WARN(crtc_state && crtc_state->active,
6291 "attached crtc is active, but connector isn't\n");
6292 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6293 "best encoder set without crtc!\n");
6297 int intel_connector_init(struct intel_connector *connector)
6299 struct intel_digital_connector_state *conn_state;
6302 * Allocate enough memory to hold intel_digital_connector_state,
6303 * This might be a few bytes too many, but for connectors that don't
6304 * need it we'll free the state and allocate a smaller one on the first
6305 * succesful commit anyway.
6307 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6311 __drm_atomic_helper_connector_reset(&connector->base,
6317 struct intel_connector *intel_connector_alloc(void)
6319 struct intel_connector *connector;
6321 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6325 if (intel_connector_init(connector) < 0) {
6334 * Free the bits allocated by intel_connector_alloc.
6335 * This should only be used after intel_connector_alloc has returned
6336 * successfully, and before drm_connector_init returns successfully.
6337 * Otherwise the destroy callbacks for the connector and the state should
6338 * take care of proper cleanup/free
6340 void intel_connector_free(struct intel_connector *connector)
6342 kfree(to_intel_digital_connector_state(connector->base.state));
6346 /* Simple connector->get_hw_state implementation for encoders that support only
6347 * one connector and no cloning and hence the encoder state determines the state
6348 * of the connector. */
6349 bool intel_connector_get_hw_state(struct intel_connector *connector)
6352 struct intel_encoder *encoder = connector->encoder;
6354 return encoder->get_hw_state(encoder, &pipe);
6357 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6359 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6360 return crtc_state->fdi_lanes;
6365 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6366 struct intel_crtc_state *pipe_config)
6368 struct drm_i915_private *dev_priv = to_i915(dev);
6369 struct drm_atomic_state *state = pipe_config->base.state;
6370 struct intel_crtc *other_crtc;
6371 struct intel_crtc_state *other_crtc_state;
6373 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6374 pipe_name(pipe), pipe_config->fdi_lanes);
6375 if (pipe_config->fdi_lanes > 4) {
6376 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6377 pipe_name(pipe), pipe_config->fdi_lanes);
6381 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6382 if (pipe_config->fdi_lanes > 2) {
6383 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6384 pipe_config->fdi_lanes);
6391 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6394 /* Ivybridge 3 pipe is really complicated */
6399 if (pipe_config->fdi_lanes <= 2)
6402 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6404 intel_atomic_get_crtc_state(state, other_crtc);
6405 if (IS_ERR(other_crtc_state))
6406 return PTR_ERR(other_crtc_state);
6408 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6409 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6410 pipe_name(pipe), pipe_config->fdi_lanes);
6415 if (pipe_config->fdi_lanes > 2) {
6416 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6417 pipe_name(pipe), pipe_config->fdi_lanes);
6421 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6423 intel_atomic_get_crtc_state(state, other_crtc);
6424 if (IS_ERR(other_crtc_state))
6425 return PTR_ERR(other_crtc_state);
6427 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6428 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6438 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6439 struct intel_crtc_state *pipe_config)
6441 struct drm_device *dev = intel_crtc->base.dev;
6442 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6443 int lane, link_bw, fdi_dotclock, ret;
6444 bool needs_recompute = false;
6447 /* FDI is a binary signal running at ~2.7GHz, encoding
6448 * each output octet as 10 bits. The actual frequency
6449 * is stored as a divider into a 100MHz clock, and the
6450 * mode pixel clock is stored in units of 1KHz.
6451 * Hence the bw of each lane in terms of the mode signal
6454 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6456 fdi_dotclock = adjusted_mode->crtc_clock;
6458 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6459 pipe_config->pipe_bpp);
6461 pipe_config->fdi_lanes = lane;
6463 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6464 link_bw, &pipe_config->fdi_m_n, false);
6466 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6467 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6468 pipe_config->pipe_bpp -= 2*3;
6469 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6470 pipe_config->pipe_bpp);
6471 needs_recompute = true;
6472 pipe_config->bw_constrained = true;
6477 if (needs_recompute)
6483 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6485 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6488 /* IPS only exists on ULT machines and is tied to pipe A. */
6489 if (!hsw_crtc_supports_ips(crtc))
6492 if (!i915_modparams.enable_ips)
6495 if (crtc_state->pipe_bpp > 24)
6499 * We compare against max which means we must take
6500 * the increased cdclk requirement into account when
6501 * calculating the new cdclk.
6503 * Should measure whether using a lower cdclk w/o IPS
6505 if (IS_BROADWELL(dev_priv) &&
6506 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6512 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6514 struct drm_i915_private *dev_priv =
6515 to_i915(crtc_state->base.crtc->dev);
6516 struct intel_atomic_state *intel_state =
6517 to_intel_atomic_state(crtc_state->base.state);
6519 if (!hsw_crtc_state_ips_capable(crtc_state))
6522 if (crtc_state->ips_force_disable)
6525 /* IPS should be fine as long as at least one plane is enabled. */
6526 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6529 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6530 if (IS_BROADWELL(dev_priv) &&
6531 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6537 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6539 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6541 /* GDG double wide on either pipe, otherwise pipe A only */
6542 return INTEL_GEN(dev_priv) < 4 &&
6543 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6546 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6548 uint32_t pixel_rate;
6550 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6553 * We only use IF-ID interlacing. If we ever use
6554 * PF-ID we'll need to adjust the pixel_rate here.
6557 if (pipe_config->pch_pfit.enabled) {
6558 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6559 uint32_t pfit_size = pipe_config->pch_pfit.size;
6561 pipe_w = pipe_config->pipe_src_w;
6562 pipe_h = pipe_config->pipe_src_h;
6564 pfit_w = (pfit_size >> 16) & 0xFFFF;
6565 pfit_h = pfit_size & 0xFFFF;
6566 if (pipe_w < pfit_w)
6568 if (pipe_h < pfit_h)
6571 if (WARN_ON(!pfit_w || !pfit_h))
6574 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6581 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6583 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6585 if (HAS_GMCH_DISPLAY(dev_priv))
6586 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6587 crtc_state->pixel_rate =
6588 crtc_state->base.adjusted_mode.crtc_clock;
6590 crtc_state->pixel_rate =
6591 ilk_pipe_pixel_rate(crtc_state);
6594 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6595 struct intel_crtc_state *pipe_config)
6597 struct drm_device *dev = crtc->base.dev;
6598 struct drm_i915_private *dev_priv = to_i915(dev);
6599 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6600 int clock_limit = dev_priv->max_dotclk_freq;
6602 if (INTEL_GEN(dev_priv) < 4) {
6603 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6606 * Enable double wide mode when the dot clock
6607 * is > 90% of the (display) core speed.
6609 if (intel_crtc_supports_double_wide(crtc) &&
6610 adjusted_mode->crtc_clock > clock_limit) {
6611 clock_limit = dev_priv->max_dotclk_freq;
6612 pipe_config->double_wide = true;
6616 if (adjusted_mode->crtc_clock > clock_limit) {
6617 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6618 adjusted_mode->crtc_clock, clock_limit,
6619 yesno(pipe_config->double_wide));
6623 if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6625 * There is only one pipe CSC unit per pipe, and we need that
6626 * for output conversion from RGB->YCBCR. So if CTM is already
6627 * applied we can't support YCBCR420 output.
6629 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6634 * Pipe horizontal size must be even in:
6636 * - LVDS dual channel mode
6637 * - Double wide pipe
6639 if (pipe_config->pipe_src_w & 1) {
6640 if (pipe_config->double_wide) {
6641 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6645 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6646 intel_is_dual_link_lvds(dev)) {
6647 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6652 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6653 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6655 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6656 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6659 intel_crtc_compute_pixel_rate(pipe_config);
6661 if (pipe_config->has_pch_encoder)
6662 return ironlake_fdi_compute_config(crtc, pipe_config);
6668 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6670 while (*num > DATA_LINK_M_N_MASK ||
6671 *den > DATA_LINK_M_N_MASK) {
6677 static void compute_m_n(unsigned int m, unsigned int n,
6678 uint32_t *ret_m, uint32_t *ret_n,
6682 * Reduce M/N as much as possible without loss in precision. Several DP
6683 * dongles in particular seem to be fussy about too large *link* M/N
6684 * values. The passed in values are more likely to have the least
6685 * significant bits zero than M after rounding below, so do this first.
6688 while ((m & 1) == 0 && (n & 1) == 0) {
6694 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6695 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6696 intel_reduce_m_n_ratio(ret_m, ret_n);
6700 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6701 int pixel_clock, int link_clock,
6702 struct intel_link_m_n *m_n,
6707 compute_m_n(bits_per_pixel * pixel_clock,
6708 link_clock * nlanes * 8,
6709 &m_n->gmch_m, &m_n->gmch_n,
6712 compute_m_n(pixel_clock, link_clock,
6713 &m_n->link_m, &m_n->link_n,
6717 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6719 if (i915_modparams.panel_use_ssc >= 0)
6720 return i915_modparams.panel_use_ssc != 0;
6721 return dev_priv->vbt.lvds_use_ssc
6722 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6725 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6727 return (1 << dpll->n) << 16 | dpll->m2;
6730 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6732 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6735 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6736 struct intel_crtc_state *crtc_state,
6737 struct dpll *reduced_clock)
6739 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6742 if (IS_PINEVIEW(dev_priv)) {
6743 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6745 fp2 = pnv_dpll_compute_fp(reduced_clock);
6747 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6749 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6752 crtc_state->dpll_hw_state.fp0 = fp;
6754 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6756 crtc_state->dpll_hw_state.fp1 = fp2;
6758 crtc_state->dpll_hw_state.fp1 = fp;
6762 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6768 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6769 * and set it to a reasonable value instead.
6771 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6772 reg_val &= 0xffffff00;
6773 reg_val |= 0x00000030;
6774 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6777 reg_val &= 0x00ffffff;
6778 reg_val |= 0x8c000000;
6779 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6781 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6782 reg_val &= 0xffffff00;
6783 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6785 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6786 reg_val &= 0x00ffffff;
6787 reg_val |= 0xb0000000;
6788 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6791 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6792 struct intel_link_m_n *m_n)
6794 struct drm_device *dev = crtc->base.dev;
6795 struct drm_i915_private *dev_priv = to_i915(dev);
6796 int pipe = crtc->pipe;
6798 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6799 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6800 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6801 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6804 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6805 struct intel_link_m_n *m_n,
6806 struct intel_link_m_n *m2_n2)
6808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6809 int pipe = crtc->pipe;
6810 enum transcoder transcoder = crtc->config->cpu_transcoder;
6812 if (INTEL_GEN(dev_priv) >= 5) {
6813 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6814 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6815 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6816 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6817 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6818 * for gen < 8) and if DRRS is supported (to make sure the
6819 * registers are not unnecessarily accessed).
6821 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6822 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6823 I915_WRITE(PIPE_DATA_M2(transcoder),
6824 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6825 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6826 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6827 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6830 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6831 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6832 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6833 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6837 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6839 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6842 dp_m_n = &crtc->config->dp_m_n;
6843 dp_m2_n2 = &crtc->config->dp_m2_n2;
6844 } else if (m_n == M2_N2) {
6847 * M2_N2 registers are not supported. Hence m2_n2 divider value
6848 * needs to be programmed into M1_N1.
6850 dp_m_n = &crtc->config->dp_m2_n2;
6852 DRM_ERROR("Unsupported divider value\n");
6856 if (crtc->config->has_pch_encoder)
6857 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6859 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6862 static void vlv_compute_dpll(struct intel_crtc *crtc,
6863 struct intel_crtc_state *pipe_config)
6865 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6866 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6867 if (crtc->pipe != PIPE_A)
6868 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6870 /* DPLL not used with DSI, but still need the rest set up */
6871 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6872 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6873 DPLL_EXT_BUFFER_ENABLE_VLV;
6875 pipe_config->dpll_hw_state.dpll_md =
6876 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6879 static void chv_compute_dpll(struct intel_crtc *crtc,
6880 struct intel_crtc_state *pipe_config)
6882 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6883 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6884 if (crtc->pipe != PIPE_A)
6885 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6887 /* DPLL not used with DSI, but still need the rest set up */
6888 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6889 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6891 pipe_config->dpll_hw_state.dpll_md =
6892 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6895 static void vlv_prepare_pll(struct intel_crtc *crtc,
6896 const struct intel_crtc_state *pipe_config)
6898 struct drm_device *dev = crtc->base.dev;
6899 struct drm_i915_private *dev_priv = to_i915(dev);
6900 enum pipe pipe = crtc->pipe;
6902 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6903 u32 coreclk, reg_val;
6906 I915_WRITE(DPLL(pipe),
6907 pipe_config->dpll_hw_state.dpll &
6908 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6910 /* No need to actually set up the DPLL with DSI */
6911 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6914 mutex_lock(&dev_priv->sb_lock);
6916 bestn = pipe_config->dpll.n;
6917 bestm1 = pipe_config->dpll.m1;
6918 bestm2 = pipe_config->dpll.m2;
6919 bestp1 = pipe_config->dpll.p1;
6920 bestp2 = pipe_config->dpll.p2;
6922 /* See eDP HDMI DPIO driver vbios notes doc */
6924 /* PLL B needs special handling */
6926 vlv_pllb_recal_opamp(dev_priv, pipe);
6928 /* Set up Tx target for periodic Rcomp update */
6929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6931 /* Disable target IRef on PLL */
6932 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6933 reg_val &= 0x00ffffff;
6934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6936 /* Disable fast lock */
6937 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6939 /* Set idtafcrecal before PLL is enabled */
6940 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6941 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6942 mdiv |= ((bestn << DPIO_N_SHIFT));
6943 mdiv |= (1 << DPIO_K_SHIFT);
6946 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6947 * but we don't support that).
6948 * Note: don't use the DAC post divider as it seems unstable.
6950 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6953 mdiv |= DPIO_ENABLE_CALIBRATION;
6954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6956 /* Set HBR and RBR LPF coefficients */
6957 if (pipe_config->port_clock == 162000 ||
6958 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6959 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6966 if (intel_crtc_has_dp_encoder(pipe_config)) {
6967 /* Use SSC source */
6969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6974 } else { /* HDMI or VGA */
6975 /* Use bend source */
6977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6984 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6985 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6986 if (intel_crtc_has_dp_encoder(crtc->config))
6987 coreclk |= 0x01000000;
6988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6990 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6991 mutex_unlock(&dev_priv->sb_lock);
6994 static void chv_prepare_pll(struct intel_crtc *crtc,
6995 const struct intel_crtc_state *pipe_config)
6997 struct drm_device *dev = crtc->base.dev;
6998 struct drm_i915_private *dev_priv = to_i915(dev);
6999 enum pipe pipe = crtc->pipe;
7000 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7001 u32 loopfilter, tribuf_calcntr;
7002 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7006 /* Enable Refclk and SSC */
7007 I915_WRITE(DPLL(pipe),
7008 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7010 /* No need to actually set up the DPLL with DSI */
7011 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7014 bestn = pipe_config->dpll.n;
7015 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7016 bestm1 = pipe_config->dpll.m1;
7017 bestm2 = pipe_config->dpll.m2 >> 22;
7018 bestp1 = pipe_config->dpll.p1;
7019 bestp2 = pipe_config->dpll.p2;
7020 vco = pipe_config->dpll.vco;
7024 mutex_lock(&dev_priv->sb_lock);
7026 /* p1 and p2 divider */
7027 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7028 5 << DPIO_CHV_S1_DIV_SHIFT |
7029 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7030 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7031 1 << DPIO_CHV_K_DIV_SHIFT);
7033 /* Feedback post-divider - m2 */
7034 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7036 /* Feedback refclk divider - n and m1 */
7037 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7038 DPIO_CHV_M1_DIV_BY_2 |
7039 1 << DPIO_CHV_N_DIV_SHIFT);
7041 /* M2 fraction division */
7042 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7044 /* M2 fraction division enable */
7045 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7046 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7047 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7049 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7050 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7052 /* Program digital lock detect threshold */
7053 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7054 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7055 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7056 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7058 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7059 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7062 if (vco == 5400000) {
7063 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7064 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7065 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7066 tribuf_calcntr = 0x9;
7067 } else if (vco <= 6200000) {
7068 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7069 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7070 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7071 tribuf_calcntr = 0x9;
7072 } else if (vco <= 6480000) {
7073 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7074 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7075 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7076 tribuf_calcntr = 0x8;
7078 /* Not supported. Apply the same limits as in the max case */
7079 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7080 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7081 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7084 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7086 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7087 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7088 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7089 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7092 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7093 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7096 mutex_unlock(&dev_priv->sb_lock);
7100 * vlv_force_pll_on - forcibly enable just the PLL
7101 * @dev_priv: i915 private structure
7102 * @pipe: pipe PLL to enable
7103 * @dpll: PLL configuration
7105 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7106 * in cases where we need the PLL enabled even when @pipe is not going to
7109 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7110 const struct dpll *dpll)
7112 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7113 struct intel_crtc_state *pipe_config;
7115 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7119 pipe_config->base.crtc = &crtc->base;
7120 pipe_config->pixel_multiplier = 1;
7121 pipe_config->dpll = *dpll;
7123 if (IS_CHERRYVIEW(dev_priv)) {
7124 chv_compute_dpll(crtc, pipe_config);
7125 chv_prepare_pll(crtc, pipe_config);
7126 chv_enable_pll(crtc, pipe_config);
7128 vlv_compute_dpll(crtc, pipe_config);
7129 vlv_prepare_pll(crtc, pipe_config);
7130 vlv_enable_pll(crtc, pipe_config);
7139 * vlv_force_pll_off - forcibly disable just the PLL
7140 * @dev_priv: i915 private structure
7141 * @pipe: pipe PLL to disable
7143 * Disable the PLL for @pipe. To be used in cases where we need
7144 * the PLL enabled even when @pipe is not going to be enabled.
7146 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7148 if (IS_CHERRYVIEW(dev_priv))
7149 chv_disable_pll(dev_priv, pipe);
7151 vlv_disable_pll(dev_priv, pipe);
7154 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7155 struct intel_crtc_state *crtc_state,
7156 struct dpll *reduced_clock)
7158 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7160 struct dpll *clock = &crtc_state->dpll;
7162 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7164 dpll = DPLL_VGA_MODE_DIS;
7166 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7167 dpll |= DPLLB_MODE_LVDS;
7169 dpll |= DPLLB_MODE_DAC_SERIAL;
7171 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7172 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7173 dpll |= (crtc_state->pixel_multiplier - 1)
7174 << SDVO_MULTIPLIER_SHIFT_HIRES;
7177 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7178 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7179 dpll |= DPLL_SDVO_HIGH_SPEED;
7181 if (intel_crtc_has_dp_encoder(crtc_state))
7182 dpll |= DPLL_SDVO_HIGH_SPEED;
7184 /* compute bitmask from p1 value */
7185 if (IS_PINEVIEW(dev_priv))
7186 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7188 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7189 if (IS_G4X(dev_priv) && reduced_clock)
7190 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7192 switch (clock->p2) {
7194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7206 if (INTEL_GEN(dev_priv) >= 4)
7207 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7209 if (crtc_state->sdvo_tv_clock)
7210 dpll |= PLL_REF_INPUT_TVCLKINBC;
7211 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7212 intel_panel_use_ssc(dev_priv))
7213 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7215 dpll |= PLL_REF_INPUT_DREFCLK;
7217 dpll |= DPLL_VCO_ENABLE;
7218 crtc_state->dpll_hw_state.dpll = dpll;
7220 if (INTEL_GEN(dev_priv) >= 4) {
7221 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7222 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7223 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7227 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7228 struct intel_crtc_state *crtc_state,
7229 struct dpll *reduced_clock)
7231 struct drm_device *dev = crtc->base.dev;
7232 struct drm_i915_private *dev_priv = to_i915(dev);
7234 struct dpll *clock = &crtc_state->dpll;
7236 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7238 dpll = DPLL_VGA_MODE_DIS;
7240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7241 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7244 dpll |= PLL_P1_DIVIDE_BY_TWO;
7246 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7248 dpll |= PLL_P2_DIVIDE_BY_4;
7251 if (!IS_I830(dev_priv) &&
7252 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7253 dpll |= DPLL_DVO_2X_MODE;
7255 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7256 intel_panel_use_ssc(dev_priv))
7257 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7259 dpll |= PLL_REF_INPUT_DREFCLK;
7261 dpll |= DPLL_VCO_ENABLE;
7262 crtc_state->dpll_hw_state.dpll = dpll;
7265 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7267 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7268 enum pipe pipe = intel_crtc->pipe;
7269 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7270 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7271 uint32_t crtc_vtotal, crtc_vblank_end;
7274 /* We need to be careful not to changed the adjusted mode, for otherwise
7275 * the hw state checker will get angry at the mismatch. */
7276 crtc_vtotal = adjusted_mode->crtc_vtotal;
7277 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7279 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7280 /* the chip adds 2 halflines automatically */
7282 crtc_vblank_end -= 1;
7284 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7285 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7287 vsyncshift = adjusted_mode->crtc_hsync_start -
7288 adjusted_mode->crtc_htotal / 2;
7290 vsyncshift += adjusted_mode->crtc_htotal;
7293 if (INTEL_GEN(dev_priv) > 3)
7294 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7296 I915_WRITE(HTOTAL(cpu_transcoder),
7297 (adjusted_mode->crtc_hdisplay - 1) |
7298 ((adjusted_mode->crtc_htotal - 1) << 16));
7299 I915_WRITE(HBLANK(cpu_transcoder),
7300 (adjusted_mode->crtc_hblank_start - 1) |
7301 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7302 I915_WRITE(HSYNC(cpu_transcoder),
7303 (adjusted_mode->crtc_hsync_start - 1) |
7304 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7306 I915_WRITE(VTOTAL(cpu_transcoder),
7307 (adjusted_mode->crtc_vdisplay - 1) |
7308 ((crtc_vtotal - 1) << 16));
7309 I915_WRITE(VBLANK(cpu_transcoder),
7310 (adjusted_mode->crtc_vblank_start - 1) |
7311 ((crtc_vblank_end - 1) << 16));
7312 I915_WRITE(VSYNC(cpu_transcoder),
7313 (adjusted_mode->crtc_vsync_start - 1) |
7314 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7316 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7317 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7318 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7320 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7321 (pipe == PIPE_B || pipe == PIPE_C))
7322 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7326 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7328 struct drm_device *dev = intel_crtc->base.dev;
7329 struct drm_i915_private *dev_priv = to_i915(dev);
7330 enum pipe pipe = intel_crtc->pipe;
7332 /* pipesrc controls the size that is scaled from, which should
7333 * always be the user's requested size.
7335 I915_WRITE(PIPESRC(pipe),
7336 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7337 (intel_crtc->config->pipe_src_h - 1));
7340 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7341 struct intel_crtc_state *pipe_config)
7343 struct drm_device *dev = crtc->base.dev;
7344 struct drm_i915_private *dev_priv = to_i915(dev);
7345 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7348 tmp = I915_READ(HTOTAL(cpu_transcoder));
7349 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7351 tmp = I915_READ(HBLANK(cpu_transcoder));
7352 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7354 tmp = I915_READ(HSYNC(cpu_transcoder));
7355 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7358 tmp = I915_READ(VTOTAL(cpu_transcoder));
7359 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7360 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7361 tmp = I915_READ(VBLANK(cpu_transcoder));
7362 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7363 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7364 tmp = I915_READ(VSYNC(cpu_transcoder));
7365 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7366 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7368 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7369 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7370 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7371 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7375 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7376 struct intel_crtc_state *pipe_config)
7378 struct drm_device *dev = crtc->base.dev;
7379 struct drm_i915_private *dev_priv = to_i915(dev);
7382 tmp = I915_READ(PIPESRC(crtc->pipe));
7383 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7384 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7386 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7387 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7390 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7391 struct intel_crtc_state *pipe_config)
7393 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7394 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7395 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7396 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7398 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7399 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7400 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7401 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7403 mode->flags = pipe_config->base.adjusted_mode.flags;
7404 mode->type = DRM_MODE_TYPE_DRIVER;
7406 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7408 mode->hsync = drm_mode_hsync(mode);
7409 mode->vrefresh = drm_mode_vrefresh(mode);
7410 drm_mode_set_name(mode);
7413 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7415 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7420 /* we keep both pipes enabled on 830 */
7421 if (IS_I830(dev_priv))
7422 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7424 if (intel_crtc->config->double_wide)
7425 pipeconf |= PIPECONF_DOUBLE_WIDE;
7427 /* only g4x and later have fancy bpc/dither controls */
7428 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7429 IS_CHERRYVIEW(dev_priv)) {
7430 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7431 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7432 pipeconf |= PIPECONF_DITHER_EN |
7433 PIPECONF_DITHER_TYPE_SP;
7435 switch (intel_crtc->config->pipe_bpp) {
7437 pipeconf |= PIPECONF_6BPC;
7440 pipeconf |= PIPECONF_8BPC;
7443 pipeconf |= PIPECONF_10BPC;
7446 /* Case prevented by intel_choose_pipe_bpp_dither. */
7451 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7452 if (INTEL_GEN(dev_priv) < 4 ||
7453 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7454 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7456 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7458 pipeconf |= PIPECONF_PROGRESSIVE;
7460 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7461 intel_crtc->config->limited_color_range)
7462 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7464 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7465 POSTING_READ(PIPECONF(intel_crtc->pipe));
7468 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7469 struct intel_crtc_state *crtc_state)
7471 struct drm_device *dev = crtc->base.dev;
7472 struct drm_i915_private *dev_priv = to_i915(dev);
7473 const struct intel_limit *limit;
7476 memset(&crtc_state->dpll_hw_state, 0,
7477 sizeof(crtc_state->dpll_hw_state));
7479 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7480 if (intel_panel_use_ssc(dev_priv)) {
7481 refclk = dev_priv->vbt.lvds_ssc_freq;
7482 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7485 limit = &intel_limits_i8xx_lvds;
7486 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7487 limit = &intel_limits_i8xx_dvo;
7489 limit = &intel_limits_i8xx_dac;
7492 if (!crtc_state->clock_set &&
7493 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7494 refclk, NULL, &crtc_state->dpll)) {
7495 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7499 i8xx_compute_dpll(crtc, crtc_state, NULL);
7504 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7505 struct intel_crtc_state *crtc_state)
7507 struct drm_device *dev = crtc->base.dev;
7508 struct drm_i915_private *dev_priv = to_i915(dev);
7509 const struct intel_limit *limit;
7512 memset(&crtc_state->dpll_hw_state, 0,
7513 sizeof(crtc_state->dpll_hw_state));
7515 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7516 if (intel_panel_use_ssc(dev_priv)) {
7517 refclk = dev_priv->vbt.lvds_ssc_freq;
7518 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7521 if (intel_is_dual_link_lvds(dev))
7522 limit = &intel_limits_g4x_dual_channel_lvds;
7524 limit = &intel_limits_g4x_single_channel_lvds;
7525 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7526 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7527 limit = &intel_limits_g4x_hdmi;
7528 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7529 limit = &intel_limits_g4x_sdvo;
7531 /* The option is for other outputs */
7532 limit = &intel_limits_i9xx_sdvo;
7535 if (!crtc_state->clock_set &&
7536 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7537 refclk, NULL, &crtc_state->dpll)) {
7538 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7542 i9xx_compute_dpll(crtc, crtc_state, NULL);
7547 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7548 struct intel_crtc_state *crtc_state)
7550 struct drm_device *dev = crtc->base.dev;
7551 struct drm_i915_private *dev_priv = to_i915(dev);
7552 const struct intel_limit *limit;
7555 memset(&crtc_state->dpll_hw_state, 0,
7556 sizeof(crtc_state->dpll_hw_state));
7558 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7559 if (intel_panel_use_ssc(dev_priv)) {
7560 refclk = dev_priv->vbt.lvds_ssc_freq;
7561 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7564 limit = &intel_limits_pineview_lvds;
7566 limit = &intel_limits_pineview_sdvo;
7569 if (!crtc_state->clock_set &&
7570 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7571 refclk, NULL, &crtc_state->dpll)) {
7572 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7576 i9xx_compute_dpll(crtc, crtc_state, NULL);
7581 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7582 struct intel_crtc_state *crtc_state)
7584 struct drm_device *dev = crtc->base.dev;
7585 struct drm_i915_private *dev_priv = to_i915(dev);
7586 const struct intel_limit *limit;
7589 memset(&crtc_state->dpll_hw_state, 0,
7590 sizeof(crtc_state->dpll_hw_state));
7592 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7593 if (intel_panel_use_ssc(dev_priv)) {
7594 refclk = dev_priv->vbt.lvds_ssc_freq;
7595 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7598 limit = &intel_limits_i9xx_lvds;
7600 limit = &intel_limits_i9xx_sdvo;
7603 if (!crtc_state->clock_set &&
7604 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7605 refclk, NULL, &crtc_state->dpll)) {
7606 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7610 i9xx_compute_dpll(crtc, crtc_state, NULL);
7615 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7616 struct intel_crtc_state *crtc_state)
7618 int refclk = 100000;
7619 const struct intel_limit *limit = &intel_limits_chv;
7621 memset(&crtc_state->dpll_hw_state, 0,
7622 sizeof(crtc_state->dpll_hw_state));
7624 if (!crtc_state->clock_set &&
7625 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7626 refclk, NULL, &crtc_state->dpll)) {
7627 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7631 chv_compute_dpll(crtc, crtc_state);
7636 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7637 struct intel_crtc_state *crtc_state)
7639 int refclk = 100000;
7640 const struct intel_limit *limit = &intel_limits_vlv;
7642 memset(&crtc_state->dpll_hw_state, 0,
7643 sizeof(crtc_state->dpll_hw_state));
7645 if (!crtc_state->clock_set &&
7646 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7647 refclk, NULL, &crtc_state->dpll)) {
7648 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7652 vlv_compute_dpll(crtc, crtc_state);
7657 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7658 struct intel_crtc_state *pipe_config)
7660 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7663 if (INTEL_GEN(dev_priv) <= 3 &&
7664 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7667 tmp = I915_READ(PFIT_CONTROL);
7668 if (!(tmp & PFIT_ENABLE))
7671 /* Check whether the pfit is attached to our pipe. */
7672 if (INTEL_GEN(dev_priv) < 4) {
7673 if (crtc->pipe != PIPE_B)
7676 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7680 pipe_config->gmch_pfit.control = tmp;
7681 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7684 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7685 struct intel_crtc_state *pipe_config)
7687 struct drm_device *dev = crtc->base.dev;
7688 struct drm_i915_private *dev_priv = to_i915(dev);
7689 int pipe = pipe_config->cpu_transcoder;
7692 int refclk = 100000;
7694 /* In case of DSI, DPLL will not be used */
7695 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7698 mutex_lock(&dev_priv->sb_lock);
7699 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7700 mutex_unlock(&dev_priv->sb_lock);
7702 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7703 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7704 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7705 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7706 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7708 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7712 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7713 struct intel_initial_plane_config *plane_config)
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = to_i915(dev);
7717 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7718 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7720 u32 val, base, offset;
7721 int fourcc, pixel_format;
7722 unsigned int aligned_height;
7723 struct drm_framebuffer *fb;
7724 struct intel_framebuffer *intel_fb;
7726 if (!plane->get_hw_state(plane, &pipe))
7729 WARN_ON(pipe != crtc->pipe);
7731 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7733 DRM_DEBUG_KMS("failed to alloc fb\n");
7737 fb = &intel_fb->base;
7741 val = I915_READ(DSPCNTR(i9xx_plane));
7743 if (INTEL_GEN(dev_priv) >= 4) {
7744 if (val & DISPPLANE_TILED) {
7745 plane_config->tiling = I915_TILING_X;
7746 fb->modifier = I915_FORMAT_MOD_X_TILED;
7750 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7751 fourcc = i9xx_format_to_fourcc(pixel_format);
7752 fb->format = drm_format_info(fourcc);
7754 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7755 offset = I915_READ(DSPOFFSET(i9xx_plane));
7756 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7757 } else if (INTEL_GEN(dev_priv) >= 4) {
7758 if (plane_config->tiling)
7759 offset = I915_READ(DSPTILEOFF(i9xx_plane));
7761 offset = I915_READ(DSPLINOFF(i9xx_plane));
7762 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7764 base = I915_READ(DSPADDR(i9xx_plane));
7766 plane_config->base = base;
7768 val = I915_READ(PIPESRC(pipe));
7769 fb->width = ((val >> 16) & 0xfff) + 1;
7770 fb->height = ((val >> 0) & 0xfff) + 1;
7772 val = I915_READ(DSPSTRIDE(i9xx_plane));
7773 fb->pitches[0] = val & 0xffffffc0;
7775 aligned_height = intel_fb_align_height(fb, 0, fb->height);
7777 plane_config->size = fb->pitches[0] * aligned_height;
7779 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7780 crtc->base.name, plane->base.name, fb->width, fb->height,
7781 fb->format->cpp[0] * 8, base, fb->pitches[0],
7782 plane_config->size);
7784 plane_config->fb = intel_fb;
7787 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7788 struct intel_crtc_state *pipe_config)
7790 struct drm_device *dev = crtc->base.dev;
7791 struct drm_i915_private *dev_priv = to_i915(dev);
7792 int pipe = pipe_config->cpu_transcoder;
7793 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7795 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7796 int refclk = 100000;
7798 /* In case of DSI, DPLL will not be used */
7799 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7802 mutex_lock(&dev_priv->sb_lock);
7803 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7804 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7805 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7806 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7807 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7808 mutex_unlock(&dev_priv->sb_lock);
7810 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7811 clock.m2 = (pll_dw0 & 0xff) << 22;
7812 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7813 clock.m2 |= pll_dw2 & 0x3fffff;
7814 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7815 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7816 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7818 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7821 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7822 struct intel_crtc_state *pipe_config)
7824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7825 enum intel_display_power_domain power_domain;
7829 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7830 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7833 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7834 pipe_config->shared_dpll = NULL;
7838 tmp = I915_READ(PIPECONF(crtc->pipe));
7839 if (!(tmp & PIPECONF_ENABLE))
7842 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7843 IS_CHERRYVIEW(dev_priv)) {
7844 switch (tmp & PIPECONF_BPC_MASK) {
7846 pipe_config->pipe_bpp = 18;
7849 pipe_config->pipe_bpp = 24;
7851 case PIPECONF_10BPC:
7852 pipe_config->pipe_bpp = 30;
7859 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7860 (tmp & PIPECONF_COLOR_RANGE_SELECT))
7861 pipe_config->limited_color_range = true;
7863 if (INTEL_GEN(dev_priv) < 4)
7864 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7866 intel_get_pipe_timings(crtc, pipe_config);
7867 intel_get_pipe_src_size(crtc, pipe_config);
7869 i9xx_get_pfit_config(crtc, pipe_config);
7871 if (INTEL_GEN(dev_priv) >= 4) {
7872 /* No way to read it out on pipes B and C */
7873 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7874 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7876 tmp = I915_READ(DPLL_MD(crtc->pipe));
7877 pipe_config->pixel_multiplier =
7878 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7879 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7880 pipe_config->dpll_hw_state.dpll_md = tmp;
7881 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7882 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7883 tmp = I915_READ(DPLL(crtc->pipe));
7884 pipe_config->pixel_multiplier =
7885 ((tmp & SDVO_MULTIPLIER_MASK)
7886 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7888 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7889 * port and will be fixed up in the encoder->get_config
7891 pipe_config->pixel_multiplier = 1;
7893 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7894 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7896 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7897 * on 830. Filter it out here so that we don't
7898 * report errors due to that.
7900 if (IS_I830(dev_priv))
7901 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7903 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7904 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7906 /* Mask out read-only status bits. */
7907 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7908 DPLL_PORTC_READY_MASK |
7909 DPLL_PORTB_READY_MASK);
7912 if (IS_CHERRYVIEW(dev_priv))
7913 chv_crtc_clock_get(crtc, pipe_config);
7914 else if (IS_VALLEYVIEW(dev_priv))
7915 vlv_crtc_clock_get(crtc, pipe_config);
7917 i9xx_crtc_clock_get(crtc, pipe_config);
7920 * Normally the dotclock is filled in by the encoder .get_config()
7921 * but in case the pipe is enabled w/o any ports we need a sane
7924 pipe_config->base.adjusted_mode.crtc_clock =
7925 pipe_config->port_clock / pipe_config->pixel_multiplier;
7930 intel_display_power_put(dev_priv, power_domain);
7935 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7937 struct intel_encoder *encoder;
7940 bool has_lvds = false;
7941 bool has_cpu_edp = false;
7942 bool has_panel = false;
7943 bool has_ck505 = false;
7944 bool can_ssc = false;
7945 bool using_ssc_source = false;
7947 /* We need to take the global config into account */
7948 for_each_intel_encoder(&dev_priv->drm, encoder) {
7949 switch (encoder->type) {
7950 case INTEL_OUTPUT_LVDS:
7954 case INTEL_OUTPUT_EDP:
7956 if (encoder->port == PORT_A)
7964 if (HAS_PCH_IBX(dev_priv)) {
7965 has_ck505 = dev_priv->vbt.display_clock_mode;
7966 can_ssc = has_ck505;
7972 /* Check if any DPLLs are using the SSC source */
7973 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7974 u32 temp = I915_READ(PCH_DPLL(i));
7976 if (!(temp & DPLL_VCO_ENABLE))
7979 if ((temp & PLL_REF_INPUT_MASK) ==
7980 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7981 using_ssc_source = true;
7986 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7987 has_panel, has_lvds, has_ck505, using_ssc_source);
7989 /* Ironlake: try to setup display ref clock before DPLL
7990 * enabling. This is only under driver's control after
7991 * PCH B stepping, previous chipset stepping should be
7992 * ignoring this setting.
7994 val = I915_READ(PCH_DREF_CONTROL);
7996 /* As we must carefully and slowly disable/enable each source in turn,
7997 * compute the final state we want first and check if we need to
7998 * make any changes at all.
8001 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8003 final |= DREF_NONSPREAD_CK505_ENABLE;
8005 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8007 final &= ~DREF_SSC_SOURCE_MASK;
8008 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8009 final &= ~DREF_SSC1_ENABLE;
8012 final |= DREF_SSC_SOURCE_ENABLE;
8014 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8015 final |= DREF_SSC1_ENABLE;
8018 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8019 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8021 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8023 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8024 } else if (using_ssc_source) {
8025 final |= DREF_SSC_SOURCE_ENABLE;
8026 final |= DREF_SSC1_ENABLE;
8032 /* Always enable nonspread source */
8033 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8036 val |= DREF_NONSPREAD_CK505_ENABLE;
8038 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8041 val &= ~DREF_SSC_SOURCE_MASK;
8042 val |= DREF_SSC_SOURCE_ENABLE;
8044 /* SSC must be turned on before enabling the CPU output */
8045 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8046 DRM_DEBUG_KMS("Using SSC on panel\n");
8047 val |= DREF_SSC1_ENABLE;
8049 val &= ~DREF_SSC1_ENABLE;
8051 /* Get SSC going before enabling the outputs */
8052 I915_WRITE(PCH_DREF_CONTROL, val);
8053 POSTING_READ(PCH_DREF_CONTROL);
8056 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8058 /* Enable CPU source on CPU attached eDP */
8060 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8061 DRM_DEBUG_KMS("Using SSC on eDP\n");
8062 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8064 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8066 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8068 I915_WRITE(PCH_DREF_CONTROL, val);
8069 POSTING_READ(PCH_DREF_CONTROL);
8072 DRM_DEBUG_KMS("Disabling CPU source output\n");
8074 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8076 /* Turn off CPU output */
8077 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8079 I915_WRITE(PCH_DREF_CONTROL, val);
8080 POSTING_READ(PCH_DREF_CONTROL);
8083 if (!using_ssc_source) {
8084 DRM_DEBUG_KMS("Disabling SSC source\n");
8086 /* Turn off the SSC source */
8087 val &= ~DREF_SSC_SOURCE_MASK;
8088 val |= DREF_SSC_SOURCE_DISABLE;
8091 val &= ~DREF_SSC1_ENABLE;
8093 I915_WRITE(PCH_DREF_CONTROL, val);
8094 POSTING_READ(PCH_DREF_CONTROL);
8099 BUG_ON(val != final);
8102 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8106 tmp = I915_READ(SOUTH_CHICKEN2);
8107 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8108 I915_WRITE(SOUTH_CHICKEN2, tmp);
8110 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8111 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8112 DRM_ERROR("FDI mPHY reset assert timeout\n");
8114 tmp = I915_READ(SOUTH_CHICKEN2);
8115 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8116 I915_WRITE(SOUTH_CHICKEN2, tmp);
8118 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8119 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8120 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8123 /* WaMPhyProgramming:hsw */
8124 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8128 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8129 tmp &= ~(0xFF << 24);
8130 tmp |= (0x12 << 24);
8131 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8133 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8135 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8137 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8139 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8141 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8142 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8143 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8145 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8146 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8147 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8149 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8152 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8154 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8157 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8159 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8162 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8164 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8167 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8169 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8170 tmp &= ~(0xFF << 16);
8171 tmp |= (0x1C << 16);
8172 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8174 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8175 tmp &= ~(0xFF << 16);
8176 tmp |= (0x1C << 16);
8177 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8179 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8181 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8183 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8185 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8187 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8188 tmp &= ~(0xF << 28);
8190 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8192 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8193 tmp &= ~(0xF << 28);
8195 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8198 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8199 * Programming" based on the parameters passed:
8200 * - Sequence to enable CLKOUT_DP
8201 * - Sequence to enable CLKOUT_DP without spread
8202 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8204 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8205 bool with_spread, bool with_fdi)
8209 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8211 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8212 with_fdi, "LP PCH doesn't have FDI\n"))
8215 mutex_lock(&dev_priv->sb_lock);
8217 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8218 tmp &= ~SBI_SSCCTL_DISABLE;
8219 tmp |= SBI_SSCCTL_PATHALT;
8220 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8225 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8226 tmp &= ~SBI_SSCCTL_PATHALT;
8227 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8230 lpt_reset_fdi_mphy(dev_priv);
8231 lpt_program_fdi_mphy(dev_priv);
8235 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8236 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8237 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8238 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8240 mutex_unlock(&dev_priv->sb_lock);
8243 /* Sequence to disable CLKOUT_DP */
8244 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8248 mutex_lock(&dev_priv->sb_lock);
8250 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8251 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8252 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8253 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8255 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8256 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8257 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8258 tmp |= SBI_SSCCTL_PATHALT;
8259 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8262 tmp |= SBI_SSCCTL_DISABLE;
8263 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8266 mutex_unlock(&dev_priv->sb_lock);
8269 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8271 static const uint16_t sscdivintphase[] = {
8272 [BEND_IDX( 50)] = 0x3B23,
8273 [BEND_IDX( 45)] = 0x3B23,
8274 [BEND_IDX( 40)] = 0x3C23,
8275 [BEND_IDX( 35)] = 0x3C23,
8276 [BEND_IDX( 30)] = 0x3D23,
8277 [BEND_IDX( 25)] = 0x3D23,
8278 [BEND_IDX( 20)] = 0x3E23,
8279 [BEND_IDX( 15)] = 0x3E23,
8280 [BEND_IDX( 10)] = 0x3F23,
8281 [BEND_IDX( 5)] = 0x3F23,
8282 [BEND_IDX( 0)] = 0x0025,
8283 [BEND_IDX( -5)] = 0x0025,
8284 [BEND_IDX(-10)] = 0x0125,
8285 [BEND_IDX(-15)] = 0x0125,
8286 [BEND_IDX(-20)] = 0x0225,
8287 [BEND_IDX(-25)] = 0x0225,
8288 [BEND_IDX(-30)] = 0x0325,
8289 [BEND_IDX(-35)] = 0x0325,
8290 [BEND_IDX(-40)] = 0x0425,
8291 [BEND_IDX(-45)] = 0x0425,
8292 [BEND_IDX(-50)] = 0x0525,
8297 * steps -50 to 50 inclusive, in steps of 5
8298 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8299 * change in clock period = -(steps / 10) * 5.787 ps
8301 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8304 int idx = BEND_IDX(steps);
8306 if (WARN_ON(steps % 5 != 0))
8309 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8312 mutex_lock(&dev_priv->sb_lock);
8314 if (steps % 10 != 0)
8318 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8320 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8322 tmp |= sscdivintphase[idx];
8323 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8325 mutex_unlock(&dev_priv->sb_lock);
8330 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8332 struct intel_encoder *encoder;
8333 bool has_vga = false;
8335 for_each_intel_encoder(&dev_priv->drm, encoder) {
8336 switch (encoder->type) {
8337 case INTEL_OUTPUT_ANALOG:
8346 lpt_bend_clkout_dp(dev_priv, 0);
8347 lpt_enable_clkout_dp(dev_priv, true, true);
8349 lpt_disable_clkout_dp(dev_priv);
8354 * Initialize reference clocks when the driver loads
8356 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8358 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8359 ironlake_init_pch_refclk(dev_priv);
8360 else if (HAS_PCH_LPT(dev_priv))
8361 lpt_init_pch_refclk(dev_priv);
8364 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8366 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8368 int pipe = intel_crtc->pipe;
8373 switch (intel_crtc->config->pipe_bpp) {
8375 val |= PIPECONF_6BPC;
8378 val |= PIPECONF_8BPC;
8381 val |= PIPECONF_10BPC;
8384 val |= PIPECONF_12BPC;
8387 /* Case prevented by intel_choose_pipe_bpp_dither. */
8391 if (intel_crtc->config->dither)
8392 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8394 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8395 val |= PIPECONF_INTERLACED_ILK;
8397 val |= PIPECONF_PROGRESSIVE;
8399 if (intel_crtc->config->limited_color_range)
8400 val |= PIPECONF_COLOR_RANGE_SELECT;
8402 I915_WRITE(PIPECONF(pipe), val);
8403 POSTING_READ(PIPECONF(pipe));
8406 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8408 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8410 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8413 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8414 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8416 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8417 val |= PIPECONF_INTERLACED_ILK;
8419 val |= PIPECONF_PROGRESSIVE;
8421 I915_WRITE(PIPECONF(cpu_transcoder), val);
8422 POSTING_READ(PIPECONF(cpu_transcoder));
8425 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8427 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8429 struct intel_crtc_state *config = intel_crtc->config;
8431 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8434 switch (intel_crtc->config->pipe_bpp) {
8436 val |= PIPEMISC_DITHER_6_BPC;
8439 val |= PIPEMISC_DITHER_8_BPC;
8442 val |= PIPEMISC_DITHER_10_BPC;
8445 val |= PIPEMISC_DITHER_12_BPC;
8448 /* Case prevented by pipe_config_set_bpp. */
8452 if (intel_crtc->config->dither)
8453 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8455 if (config->ycbcr420) {
8456 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8457 PIPEMISC_YUV420_ENABLE |
8458 PIPEMISC_YUV420_MODE_FULL_BLEND;
8461 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8465 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8468 * Account for spread spectrum to avoid
8469 * oversubscribing the link. Max center spread
8470 * is 2.5%; use 5% for safety's sake.
8472 u32 bps = target_clock * bpp * 21 / 20;
8473 return DIV_ROUND_UP(bps, link_bw * 8);
8476 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8478 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8481 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8482 struct intel_crtc_state *crtc_state,
8483 struct dpll *reduced_clock)
8485 struct drm_crtc *crtc = &intel_crtc->base;
8486 struct drm_device *dev = crtc->dev;
8487 struct drm_i915_private *dev_priv = to_i915(dev);
8491 /* Enable autotuning of the PLL clock (if permissible) */
8493 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8494 if ((intel_panel_use_ssc(dev_priv) &&
8495 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8496 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8498 } else if (crtc_state->sdvo_tv_clock)
8501 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8503 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8506 if (reduced_clock) {
8507 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8509 if (reduced_clock->m < factor * reduced_clock->n)
8517 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8518 dpll |= DPLLB_MODE_LVDS;
8520 dpll |= DPLLB_MODE_DAC_SERIAL;
8522 dpll |= (crtc_state->pixel_multiplier - 1)
8523 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8525 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8526 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8527 dpll |= DPLL_SDVO_HIGH_SPEED;
8529 if (intel_crtc_has_dp_encoder(crtc_state))
8530 dpll |= DPLL_SDVO_HIGH_SPEED;
8533 * The high speed IO clock is only really required for
8534 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8535 * possible to share the DPLL between CRT and HDMI. Enabling
8536 * the clock needlessly does no real harm, except use up a
8537 * bit of power potentially.
8539 * We'll limit this to IVB with 3 pipes, since it has only two
8540 * DPLLs and so DPLL sharing is the only way to get three pipes
8541 * driving PCH ports at the same time. On SNB we could do this,
8542 * and potentially avoid enabling the second DPLL, but it's not
8543 * clear if it''s a win or loss power wise. No point in doing
8544 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8546 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8547 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8548 dpll |= DPLL_SDVO_HIGH_SPEED;
8550 /* compute bitmask from p1 value */
8551 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8553 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8555 switch (crtc_state->dpll.p2) {
8557 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8560 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8563 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8566 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8570 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8571 intel_panel_use_ssc(dev_priv))
8572 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8574 dpll |= PLL_REF_INPUT_DREFCLK;
8576 dpll |= DPLL_VCO_ENABLE;
8578 crtc_state->dpll_hw_state.dpll = dpll;
8579 crtc_state->dpll_hw_state.fp0 = fp;
8580 crtc_state->dpll_hw_state.fp1 = fp2;
8583 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8584 struct intel_crtc_state *crtc_state)
8586 struct drm_device *dev = crtc->base.dev;
8587 struct drm_i915_private *dev_priv = to_i915(dev);
8588 const struct intel_limit *limit;
8589 int refclk = 120000;
8591 memset(&crtc_state->dpll_hw_state, 0,
8592 sizeof(crtc_state->dpll_hw_state));
8594 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8595 if (!crtc_state->has_pch_encoder)
8598 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8599 if (intel_panel_use_ssc(dev_priv)) {
8600 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8601 dev_priv->vbt.lvds_ssc_freq);
8602 refclk = dev_priv->vbt.lvds_ssc_freq;
8605 if (intel_is_dual_link_lvds(dev)) {
8606 if (refclk == 100000)
8607 limit = &intel_limits_ironlake_dual_lvds_100m;
8609 limit = &intel_limits_ironlake_dual_lvds;
8611 if (refclk == 100000)
8612 limit = &intel_limits_ironlake_single_lvds_100m;
8614 limit = &intel_limits_ironlake_single_lvds;
8617 limit = &intel_limits_ironlake_dac;
8620 if (!crtc_state->clock_set &&
8621 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8622 refclk, NULL, &crtc_state->dpll)) {
8623 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8627 ironlake_compute_dpll(crtc, crtc_state, NULL);
8629 if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8630 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8631 pipe_name(crtc->pipe));
8638 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8639 struct intel_link_m_n *m_n)
8641 struct drm_device *dev = crtc->base.dev;
8642 struct drm_i915_private *dev_priv = to_i915(dev);
8643 enum pipe pipe = crtc->pipe;
8645 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8646 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8647 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8649 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8650 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8651 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8654 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8655 enum transcoder transcoder,
8656 struct intel_link_m_n *m_n,
8657 struct intel_link_m_n *m2_n2)
8659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8660 enum pipe pipe = crtc->pipe;
8662 if (INTEL_GEN(dev_priv) >= 5) {
8663 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8664 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8665 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8667 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8668 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8669 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8670 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8671 * gen < 8) and if DRRS is supported (to make sure the
8672 * registers are not unnecessarily read).
8674 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8675 crtc->config->has_drrs) {
8676 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8677 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8678 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8680 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8681 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8682 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8685 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8686 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8687 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8689 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8690 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8691 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8695 void intel_dp_get_m_n(struct intel_crtc *crtc,
8696 struct intel_crtc_state *pipe_config)
8698 if (pipe_config->has_pch_encoder)
8699 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8701 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8702 &pipe_config->dp_m_n,
8703 &pipe_config->dp_m2_n2);
8706 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8707 struct intel_crtc_state *pipe_config)
8709 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8710 &pipe_config->fdi_m_n, NULL);
8713 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8714 struct intel_crtc_state *pipe_config)
8716 struct drm_device *dev = crtc->base.dev;
8717 struct drm_i915_private *dev_priv = to_i915(dev);
8718 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8719 uint32_t ps_ctrl = 0;
8723 /* find scaler attached to this pipe */
8724 for (i = 0; i < crtc->num_scalers; i++) {
8725 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8726 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8728 pipe_config->pch_pfit.enabled = true;
8729 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8730 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8735 scaler_state->scaler_id = id;
8737 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8739 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8744 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8745 struct intel_initial_plane_config *plane_config)
8747 struct drm_device *dev = crtc->base.dev;
8748 struct drm_i915_private *dev_priv = to_i915(dev);
8749 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8750 enum plane_id plane_id = plane->id;
8752 u32 val, base, offset, stride_mult, tiling, alpha;
8753 int fourcc, pixel_format;
8754 unsigned int aligned_height;
8755 struct drm_framebuffer *fb;
8756 struct intel_framebuffer *intel_fb;
8758 if (!plane->get_hw_state(plane, &pipe))
8761 WARN_ON(pipe != crtc->pipe);
8763 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8765 DRM_DEBUG_KMS("failed to alloc fb\n");
8769 fb = &intel_fb->base;
8773 val = I915_READ(PLANE_CTL(pipe, plane_id));
8775 if (INTEL_GEN(dev_priv) >= 11)
8776 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8778 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8780 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8781 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8782 alpha &= PLANE_COLOR_ALPHA_MASK;
8784 alpha = val & PLANE_CTL_ALPHA_MASK;
8787 fourcc = skl_format_to_fourcc(pixel_format,
8788 val & PLANE_CTL_ORDER_RGBX, alpha);
8789 fb->format = drm_format_info(fourcc);
8791 tiling = val & PLANE_CTL_TILED_MASK;
8793 case PLANE_CTL_TILED_LINEAR:
8794 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8796 case PLANE_CTL_TILED_X:
8797 plane_config->tiling = I915_TILING_X;
8798 fb->modifier = I915_FORMAT_MOD_X_TILED;
8800 case PLANE_CTL_TILED_Y:
8801 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8802 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8804 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8806 case PLANE_CTL_TILED_YF:
8807 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8808 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8810 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8813 MISSING_CASE(tiling);
8817 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8818 plane_config->base = base;
8820 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8822 val = I915_READ(PLANE_SIZE(pipe, plane_id));
8823 fb->height = ((val >> 16) & 0xfff) + 1;
8824 fb->width = ((val >> 0) & 0x1fff) + 1;
8826 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8827 stride_mult = intel_fb_stride_alignment(fb, 0);
8828 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8830 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8832 plane_config->size = fb->pitches[0] * aligned_height;
8834 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8835 crtc->base.name, plane->base.name, fb->width, fb->height,
8836 fb->format->cpp[0] * 8, base, fb->pitches[0],
8837 plane_config->size);
8839 plane_config->fb = intel_fb;
8846 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8847 struct intel_crtc_state *pipe_config)
8849 struct drm_device *dev = crtc->base.dev;
8850 struct drm_i915_private *dev_priv = to_i915(dev);
8853 tmp = I915_READ(PF_CTL(crtc->pipe));
8855 if (tmp & PF_ENABLE) {
8856 pipe_config->pch_pfit.enabled = true;
8857 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8858 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8860 /* We currently do not free assignements of panel fitters on
8861 * ivb/hsw (since we don't use the higher upscaling modes which
8862 * differentiates them) so just WARN about this case for now. */
8863 if (IS_GEN7(dev_priv)) {
8864 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8865 PF_PIPE_SEL_IVB(crtc->pipe));
8870 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8871 struct intel_crtc_state *pipe_config)
8873 struct drm_device *dev = crtc->base.dev;
8874 struct drm_i915_private *dev_priv = to_i915(dev);
8875 enum intel_display_power_domain power_domain;
8879 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8880 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8883 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8884 pipe_config->shared_dpll = NULL;
8887 tmp = I915_READ(PIPECONF(crtc->pipe));
8888 if (!(tmp & PIPECONF_ENABLE))
8891 switch (tmp & PIPECONF_BPC_MASK) {
8893 pipe_config->pipe_bpp = 18;
8896 pipe_config->pipe_bpp = 24;
8898 case PIPECONF_10BPC:
8899 pipe_config->pipe_bpp = 30;
8901 case PIPECONF_12BPC:
8902 pipe_config->pipe_bpp = 36;
8908 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8909 pipe_config->limited_color_range = true;
8911 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8912 struct intel_shared_dpll *pll;
8913 enum intel_dpll_id pll_id;
8915 pipe_config->has_pch_encoder = true;
8917 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8918 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8919 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8921 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8923 if (HAS_PCH_IBX(dev_priv)) {
8925 * The pipe->pch transcoder and pch transcoder->pll
8928 pll_id = (enum intel_dpll_id) crtc->pipe;
8930 tmp = I915_READ(PCH_DPLL_SEL);
8931 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8932 pll_id = DPLL_ID_PCH_PLL_B;
8934 pll_id= DPLL_ID_PCH_PLL_A;
8937 pipe_config->shared_dpll =
8938 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8939 pll = pipe_config->shared_dpll;
8941 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8942 &pipe_config->dpll_hw_state));
8944 tmp = pipe_config->dpll_hw_state.dpll;
8945 pipe_config->pixel_multiplier =
8946 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8947 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8949 ironlake_pch_clock_get(crtc, pipe_config);
8951 pipe_config->pixel_multiplier = 1;
8954 intel_get_pipe_timings(crtc, pipe_config);
8955 intel_get_pipe_src_size(crtc, pipe_config);
8957 ironlake_get_pfit_config(crtc, pipe_config);
8962 intel_display_power_put(dev_priv, power_domain);
8967 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8969 struct drm_device *dev = &dev_priv->drm;
8970 struct intel_crtc *crtc;
8972 for_each_intel_crtc(dev, crtc)
8973 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8974 pipe_name(crtc->pipe));
8976 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8977 "Display power well on\n");
8978 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8979 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8980 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8981 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8982 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8983 "CPU PWM1 enabled\n");
8984 if (IS_HASWELL(dev_priv))
8985 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8986 "CPU PWM2 enabled\n");
8987 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8988 "PCH PWM1 enabled\n");
8989 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8990 "Utility pin enabled\n");
8991 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8994 * In theory we can still leave IRQs enabled, as long as only the HPD
8995 * interrupts remain enabled. We used to check for that, but since it's
8996 * gen-specific and since we only disable LCPLL after we fully disable
8997 * the interrupts, the check below should be enough.
8999 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9002 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9004 if (IS_HASWELL(dev_priv))
9005 return I915_READ(D_COMP_HSW);
9007 return I915_READ(D_COMP_BDW);
9010 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9012 if (IS_HASWELL(dev_priv)) {
9013 mutex_lock(&dev_priv->pcu_lock);
9014 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9016 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
9017 mutex_unlock(&dev_priv->pcu_lock);
9019 I915_WRITE(D_COMP_BDW, val);
9020 POSTING_READ(D_COMP_BDW);
9025 * This function implements pieces of two sequences from BSpec:
9026 * - Sequence for display software to disable LCPLL
9027 * - Sequence for display software to allow package C8+
9028 * The steps implemented here are just the steps that actually touch the LCPLL
9029 * register. Callers should take care of disabling all the display engine
9030 * functions, doing the mode unset, fixing interrupts, etc.
9032 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9033 bool switch_to_fclk, bool allow_power_down)
9037 assert_can_disable_lcpll(dev_priv);
9039 val = I915_READ(LCPLL_CTL);
9041 if (switch_to_fclk) {
9042 val |= LCPLL_CD_SOURCE_FCLK;
9043 I915_WRITE(LCPLL_CTL, val);
9045 if (wait_for_us(I915_READ(LCPLL_CTL) &
9046 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9047 DRM_ERROR("Switching to FCLK failed\n");
9049 val = I915_READ(LCPLL_CTL);
9052 val |= LCPLL_PLL_DISABLE;
9053 I915_WRITE(LCPLL_CTL, val);
9054 POSTING_READ(LCPLL_CTL);
9056 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9057 DRM_ERROR("LCPLL still locked\n");
9059 val = hsw_read_dcomp(dev_priv);
9060 val |= D_COMP_COMP_DISABLE;
9061 hsw_write_dcomp(dev_priv, val);
9064 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9066 DRM_ERROR("D_COMP RCOMP still in progress\n");
9068 if (allow_power_down) {
9069 val = I915_READ(LCPLL_CTL);
9070 val |= LCPLL_POWER_DOWN_ALLOW;
9071 I915_WRITE(LCPLL_CTL, val);
9072 POSTING_READ(LCPLL_CTL);
9077 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9080 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9084 val = I915_READ(LCPLL_CTL);
9086 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9087 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9091 * Make sure we're not on PC8 state before disabling PC8, otherwise
9092 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9094 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9096 if (val & LCPLL_POWER_DOWN_ALLOW) {
9097 val &= ~LCPLL_POWER_DOWN_ALLOW;
9098 I915_WRITE(LCPLL_CTL, val);
9099 POSTING_READ(LCPLL_CTL);
9102 val = hsw_read_dcomp(dev_priv);
9103 val |= D_COMP_COMP_FORCE;
9104 val &= ~D_COMP_COMP_DISABLE;
9105 hsw_write_dcomp(dev_priv, val);
9107 val = I915_READ(LCPLL_CTL);
9108 val &= ~LCPLL_PLL_DISABLE;
9109 I915_WRITE(LCPLL_CTL, val);
9111 if (intel_wait_for_register(dev_priv,
9112 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9114 DRM_ERROR("LCPLL not locked yet\n");
9116 if (val & LCPLL_CD_SOURCE_FCLK) {
9117 val = I915_READ(LCPLL_CTL);
9118 val &= ~LCPLL_CD_SOURCE_FCLK;
9119 I915_WRITE(LCPLL_CTL, val);
9121 if (wait_for_us((I915_READ(LCPLL_CTL) &
9122 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9123 DRM_ERROR("Switching back to LCPLL failed\n");
9126 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9128 intel_update_cdclk(dev_priv);
9129 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9133 * Package states C8 and deeper are really deep PC states that can only be
9134 * reached when all the devices on the system allow it, so even if the graphics
9135 * device allows PC8+, it doesn't mean the system will actually get to these
9136 * states. Our driver only allows PC8+ when going into runtime PM.
9138 * The requirements for PC8+ are that all the outputs are disabled, the power
9139 * well is disabled and most interrupts are disabled, and these are also
9140 * requirements for runtime PM. When these conditions are met, we manually do
9141 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9142 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9145 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9146 * the state of some registers, so when we come back from PC8+ we need to
9147 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9148 * need to take care of the registers kept by RC6. Notice that this happens even
9149 * if we don't put the device in PCI D3 state (which is what currently happens
9150 * because of the runtime PM support).
9152 * For more, read "Display Sequences for Package C8" on the hardware
9155 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9159 DRM_DEBUG_KMS("Enabling package C8+\n");
9161 if (HAS_PCH_LPT_LP(dev_priv)) {
9162 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9163 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9164 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9167 lpt_disable_clkout_dp(dev_priv);
9168 hsw_disable_lcpll(dev_priv, true, true);
9171 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9175 DRM_DEBUG_KMS("Disabling package C8+\n");
9177 hsw_restore_lcpll(dev_priv);
9178 lpt_init_pch_refclk(dev_priv);
9180 if (HAS_PCH_LPT_LP(dev_priv)) {
9181 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9182 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9183 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9187 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9188 struct intel_crtc_state *crtc_state)
9190 struct intel_atomic_state *state =
9191 to_intel_atomic_state(crtc_state->base.state);
9193 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9194 struct intel_encoder *encoder =
9195 intel_get_crtc_new_encoder(state, crtc_state);
9197 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9198 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9199 pipe_name(crtc->pipe));
9207 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9209 struct intel_crtc_state *pipe_config)
9211 enum intel_dpll_id id;
9214 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9215 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9217 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9220 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9223 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
9225 struct intel_crtc_state *pipe_config)
9227 enum intel_dpll_id id;
9230 /* TODO: TBT pll not implemented. */
9234 temp = I915_READ(DPCLKA_CFGCR0_ICL) &
9235 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9236 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9238 if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
9242 id = DPLL_ID_ICL_MGPLL1;
9245 id = DPLL_ID_ICL_MGPLL2;
9248 id = DPLL_ID_ICL_MGPLL3;
9251 id = DPLL_ID_ICL_MGPLL4;
9258 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9261 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9263 struct intel_crtc_state *pipe_config)
9265 enum intel_dpll_id id;
9269 id = DPLL_ID_SKL_DPLL0;
9272 id = DPLL_ID_SKL_DPLL1;
9275 id = DPLL_ID_SKL_DPLL2;
9278 DRM_ERROR("Incorrect port type\n");
9282 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9285 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9287 struct intel_crtc_state *pipe_config)
9289 enum intel_dpll_id id;
9292 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9293 id = temp >> (port * 3 + 1);
9295 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9298 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9301 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9303 struct intel_crtc_state *pipe_config)
9305 enum intel_dpll_id id;
9306 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9308 switch (ddi_pll_sel) {
9309 case PORT_CLK_SEL_WRPLL1:
9310 id = DPLL_ID_WRPLL1;
9312 case PORT_CLK_SEL_WRPLL2:
9313 id = DPLL_ID_WRPLL2;
9315 case PORT_CLK_SEL_SPLL:
9318 case PORT_CLK_SEL_LCPLL_810:
9319 id = DPLL_ID_LCPLL_810;
9321 case PORT_CLK_SEL_LCPLL_1350:
9322 id = DPLL_ID_LCPLL_1350;
9324 case PORT_CLK_SEL_LCPLL_2700:
9325 id = DPLL_ID_LCPLL_2700;
9328 MISSING_CASE(ddi_pll_sel);
9330 case PORT_CLK_SEL_NONE:
9334 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9337 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9338 struct intel_crtc_state *pipe_config,
9339 u64 *power_domain_mask)
9341 struct drm_device *dev = crtc->base.dev;
9342 struct drm_i915_private *dev_priv = to_i915(dev);
9343 enum intel_display_power_domain power_domain;
9347 * The pipe->transcoder mapping is fixed with the exception of the eDP
9348 * transcoder handled below.
9350 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9353 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9354 * consistency and less surprising code; it's in always on power).
9356 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9357 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9358 enum pipe trans_edp_pipe;
9359 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9361 WARN(1, "unknown pipe linked to edp transcoder\n");
9363 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9364 case TRANS_DDI_EDP_INPUT_A_ON:
9365 trans_edp_pipe = PIPE_A;
9367 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9368 trans_edp_pipe = PIPE_B;
9370 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9371 trans_edp_pipe = PIPE_C;
9375 if (trans_edp_pipe == crtc->pipe)
9376 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9379 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9380 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9382 *power_domain_mask |= BIT_ULL(power_domain);
9384 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9386 return tmp & PIPECONF_ENABLE;
9389 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9390 struct intel_crtc_state *pipe_config,
9391 u64 *power_domain_mask)
9393 struct drm_device *dev = crtc->base.dev;
9394 struct drm_i915_private *dev_priv = to_i915(dev);
9395 enum intel_display_power_domain power_domain;
9397 enum transcoder cpu_transcoder;
9400 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9402 cpu_transcoder = TRANSCODER_DSI_A;
9404 cpu_transcoder = TRANSCODER_DSI_C;
9406 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9407 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9409 *power_domain_mask |= BIT_ULL(power_domain);
9412 * The PLL needs to be enabled with a valid divider
9413 * configuration, otherwise accessing DSI registers will hang
9414 * the machine. See BSpec North Display Engine
9415 * registers/MIPI[BXT]. We can break out here early, since we
9416 * need the same DSI PLL to be enabled for both DSI ports.
9418 if (!bxt_dsi_pll_is_enabled(dev_priv))
9421 /* XXX: this works for video mode only */
9422 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9423 if (!(tmp & DPI_ENABLE))
9426 tmp = I915_READ(MIPI_CTRL(port));
9427 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9430 pipe_config->cpu_transcoder = cpu_transcoder;
9434 return transcoder_is_dsi(pipe_config->cpu_transcoder);
9437 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9438 struct intel_crtc_state *pipe_config)
9440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9441 struct intel_shared_dpll *pll;
9445 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9447 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9449 if (IS_ICELAKE(dev_priv))
9450 icelake_get_ddi_pll(dev_priv, port, pipe_config);
9451 else if (IS_CANNONLAKE(dev_priv))
9452 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9453 else if (IS_GEN9_BC(dev_priv))
9454 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9455 else if (IS_GEN9_LP(dev_priv))
9456 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9458 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9460 pll = pipe_config->shared_dpll;
9462 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9463 &pipe_config->dpll_hw_state));
9467 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9468 * DDI E. So just check whether this pipe is wired to DDI E and whether
9469 * the PCH transcoder is on.
9471 if (INTEL_GEN(dev_priv) < 9 &&
9472 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9473 pipe_config->has_pch_encoder = true;
9475 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9476 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9477 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9479 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9483 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9484 struct intel_crtc_state *pipe_config)
9486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9487 enum intel_display_power_domain power_domain;
9488 u64 power_domain_mask;
9491 intel_crtc_init_scalers(crtc, pipe_config);
9493 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9494 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9496 power_domain_mask = BIT_ULL(power_domain);
9498 pipe_config->shared_dpll = NULL;
9500 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9502 if (IS_GEN9_LP(dev_priv) &&
9503 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9511 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9512 haswell_get_ddi_port_state(crtc, pipe_config);
9513 intel_get_pipe_timings(crtc, pipe_config);
9516 intel_get_pipe_src_size(crtc, pipe_config);
9518 pipe_config->gamma_mode =
9519 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9521 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9522 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9523 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9525 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9526 bool blend_mode_420 = tmp &
9527 PIPEMISC_YUV420_MODE_FULL_BLEND;
9529 pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9530 if (pipe_config->ycbcr420 != clrspace_yuv ||
9531 pipe_config->ycbcr420 != blend_mode_420)
9532 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9533 } else if (clrspace_yuv) {
9534 DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9538 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9539 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9540 power_domain_mask |= BIT_ULL(power_domain);
9541 if (INTEL_GEN(dev_priv) >= 9)
9542 skylake_get_pfit_config(crtc, pipe_config);
9544 ironlake_get_pfit_config(crtc, pipe_config);
9547 if (hsw_crtc_supports_ips(crtc)) {
9548 if (IS_HASWELL(dev_priv))
9549 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9552 * We cannot readout IPS state on broadwell, set to
9553 * true so we can set it to a defined state on first
9556 pipe_config->ips_enabled = true;
9560 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9561 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9562 pipe_config->pixel_multiplier =
9563 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9565 pipe_config->pixel_multiplier = 1;
9569 for_each_power_domain(power_domain, power_domain_mask)
9570 intel_display_power_put(dev_priv, power_domain);
9575 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9577 struct drm_i915_private *dev_priv =
9578 to_i915(plane_state->base.plane->dev);
9579 const struct drm_framebuffer *fb = plane_state->base.fb;
9580 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9583 if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9584 base = obj->phys_handle->busaddr;
9586 base = intel_plane_ggtt_offset(plane_state);
9588 base += plane_state->main.offset;
9590 /* ILK+ do this automagically */
9591 if (HAS_GMCH_DISPLAY(dev_priv) &&
9592 plane_state->base.rotation & DRM_MODE_ROTATE_180)
9593 base += (plane_state->base.crtc_h *
9594 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9599 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9601 int x = plane_state->base.crtc_x;
9602 int y = plane_state->base.crtc_y;
9606 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9609 pos |= x << CURSOR_X_SHIFT;
9612 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9615 pos |= y << CURSOR_Y_SHIFT;
9620 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9622 const struct drm_mode_config *config =
9623 &plane_state->base.plane->dev->mode_config;
9624 int width = plane_state->base.crtc_w;
9625 int height = plane_state->base.crtc_h;
9627 return width > 0 && width <= config->cursor_width &&
9628 height > 0 && height <= config->cursor_height;
9631 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9632 struct intel_plane_state *plane_state)
9634 const struct drm_framebuffer *fb = plane_state->base.fb;
9639 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9641 DRM_PLANE_HELPER_NO_SCALING,
9642 DRM_PLANE_HELPER_NO_SCALING,
9650 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9651 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9655 src_x = plane_state->base.src_x >> 16;
9656 src_y = plane_state->base.src_y >> 16;
9658 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9659 offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9661 if (src_x != 0 || src_y != 0) {
9662 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9666 plane_state->main.offset = offset;
9671 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9672 const struct intel_plane_state *plane_state)
9674 const struct drm_framebuffer *fb = plane_state->base.fb;
9676 return CURSOR_ENABLE |
9677 CURSOR_GAMMA_ENABLE |
9678 CURSOR_FORMAT_ARGB |
9679 CURSOR_STRIDE(fb->pitches[0]);
9682 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9684 int width = plane_state->base.crtc_w;
9687 * 845g/865g are only limited by the width of their cursors,
9688 * the height is arbitrary up to the precision of the register.
9690 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9693 static int i845_check_cursor(struct intel_plane *plane,
9694 struct intel_crtc_state *crtc_state,
9695 struct intel_plane_state *plane_state)
9697 const struct drm_framebuffer *fb = plane_state->base.fb;
9700 ret = intel_check_cursor(crtc_state, plane_state);
9704 /* if we want to turn off the cursor ignore width and height */
9708 /* Check for which cursor types we support */
9709 if (!i845_cursor_size_ok(plane_state)) {
9710 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9711 plane_state->base.crtc_w,
9712 plane_state->base.crtc_h);
9716 switch (fb->pitches[0]) {
9723 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9728 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9733 static void i845_update_cursor(struct intel_plane *plane,
9734 const struct intel_crtc_state *crtc_state,
9735 const struct intel_plane_state *plane_state)
9737 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9738 u32 cntl = 0, base = 0, pos = 0, size = 0;
9739 unsigned long irqflags;
9741 if (plane_state && plane_state->base.visible) {
9742 unsigned int width = plane_state->base.crtc_w;
9743 unsigned int height = plane_state->base.crtc_h;
9745 cntl = plane_state->ctl;
9746 size = (height << 12) | width;
9748 base = intel_cursor_base(plane_state);
9749 pos = intel_cursor_position(plane_state);
9752 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9754 /* On these chipsets we can only modify the base/size/stride
9755 * whilst the cursor is disabled.
9757 if (plane->cursor.base != base ||
9758 plane->cursor.size != size ||
9759 plane->cursor.cntl != cntl) {
9760 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9761 I915_WRITE_FW(CURBASE(PIPE_A), base);
9762 I915_WRITE_FW(CURSIZE, size);
9763 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9764 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9766 plane->cursor.base = base;
9767 plane->cursor.size = size;
9768 plane->cursor.cntl = cntl;
9770 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9773 POSTING_READ_FW(CURCNTR(PIPE_A));
9775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9778 static void i845_disable_cursor(struct intel_plane *plane,
9779 struct intel_crtc *crtc)
9781 i845_update_cursor(plane, NULL, NULL);
9784 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
9787 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9788 enum intel_display_power_domain power_domain;
9791 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9792 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9795 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9799 intel_display_power_put(dev_priv, power_domain);
9804 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9805 const struct intel_plane_state *plane_state)
9807 struct drm_i915_private *dev_priv =
9808 to_i915(plane_state->base.plane->dev);
9809 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9812 if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
9813 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
9815 if (INTEL_GEN(dev_priv) <= 10) {
9816 cntl |= MCURSOR_GAMMA_ENABLE;
9818 if (HAS_DDI(dev_priv))
9819 cntl |= MCURSOR_PIPE_CSC_ENABLE;
9822 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9823 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9825 switch (plane_state->base.crtc_w) {
9827 cntl |= MCURSOR_MODE_64_ARGB_AX;
9830 cntl |= MCURSOR_MODE_128_ARGB_AX;
9833 cntl |= MCURSOR_MODE_256_ARGB_AX;
9836 MISSING_CASE(plane_state->base.crtc_w);
9840 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9841 cntl |= MCURSOR_ROTATE_180;
9846 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9848 struct drm_i915_private *dev_priv =
9849 to_i915(plane_state->base.plane->dev);
9850 int width = plane_state->base.crtc_w;
9851 int height = plane_state->base.crtc_h;
9853 if (!intel_cursor_size_ok(plane_state))
9856 /* Cursor width is limited to a few power-of-two sizes */
9867 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9868 * height from 8 lines up to the cursor width, when the
9869 * cursor is not rotated. Everything else requires square
9872 if (HAS_CUR_FBC(dev_priv) &&
9873 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9874 if (height < 8 || height > width)
9877 if (height != width)
9884 static int i9xx_check_cursor(struct intel_plane *plane,
9885 struct intel_crtc_state *crtc_state,
9886 struct intel_plane_state *plane_state)
9888 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9889 const struct drm_framebuffer *fb = plane_state->base.fb;
9890 enum pipe pipe = plane->pipe;
9893 ret = intel_check_cursor(crtc_state, plane_state);
9897 /* if we want to turn off the cursor ignore width and height */
9901 /* Check for which cursor types we support */
9902 if (!i9xx_cursor_size_ok(plane_state)) {
9903 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9904 plane_state->base.crtc_w,
9905 plane_state->base.crtc_h);
9909 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9910 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9911 fb->pitches[0], plane_state->base.crtc_w);
9916 * There's something wrong with the cursor on CHV pipe C.
9917 * If it straddles the left edge of the screen then
9918 * moving it away from the edge or disabling it often
9919 * results in a pipe underrun, and often that can lead to
9920 * dead pipe (constant underrun reported, and it scans
9921 * out just a solid color). To recover from that, the
9922 * display power well must be turned off and on again.
9923 * Refuse the put the cursor into that compromised position.
9925 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9926 plane_state->base.visible && plane_state->base.crtc_x < 0) {
9927 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9931 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9936 static void i9xx_update_cursor(struct intel_plane *plane,
9937 const struct intel_crtc_state *crtc_state,
9938 const struct intel_plane_state *plane_state)
9940 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9941 enum pipe pipe = plane->pipe;
9942 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9943 unsigned long irqflags;
9945 if (plane_state && plane_state->base.visible) {
9946 cntl = plane_state->ctl;
9948 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9949 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9951 base = intel_cursor_base(plane_state);
9952 pos = intel_cursor_position(plane_state);
9955 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9958 * On some platforms writing CURCNTR first will also
9959 * cause CURPOS to be armed by the CURBASE write.
9960 * Without the CURCNTR write the CURPOS write would
9961 * arm itself. Thus we always start the full update
9962 * with a CURCNTR write.
9964 * On other platforms CURPOS always requires the
9965 * CURBASE write to arm the update. Additonally
9966 * a write to any of the cursor register will cancel
9967 * an already armed cursor update. Thus leaving out
9968 * the CURBASE write after CURPOS could lead to a
9969 * cursor that doesn't appear to move, or even change
9970 * shape. Thus we always write CURBASE.
9972 * CURCNTR and CUR_FBC_CTL are always
9973 * armed by the CURBASE write only.
9975 if (plane->cursor.base != base ||
9976 plane->cursor.size != fbc_ctl ||
9977 plane->cursor.cntl != cntl) {
9978 I915_WRITE_FW(CURCNTR(pipe), cntl);
9979 if (HAS_CUR_FBC(dev_priv))
9980 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9981 I915_WRITE_FW(CURPOS(pipe), pos);
9982 I915_WRITE_FW(CURBASE(pipe), base);
9984 plane->cursor.base = base;
9985 plane->cursor.size = fbc_ctl;
9986 plane->cursor.cntl = cntl;
9988 I915_WRITE_FW(CURPOS(pipe), pos);
9989 I915_WRITE_FW(CURBASE(pipe), base);
9992 POSTING_READ_FW(CURBASE(pipe));
9994 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9997 static void i9xx_disable_cursor(struct intel_plane *plane,
9998 struct intel_crtc *crtc)
10000 i9xx_update_cursor(plane, NULL, NULL);
10003 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10006 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10007 enum intel_display_power_domain power_domain;
10012 * Not 100% correct for planes that can move between pipes,
10013 * but that's only the case for gen2-3 which don't have any
10014 * display power wells.
10016 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10017 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10020 val = I915_READ(CURCNTR(plane->pipe));
10022 ret = val & MCURSOR_MODE;
10024 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10025 *pipe = plane->pipe;
10027 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
10028 MCURSOR_PIPE_SELECT_SHIFT;
10030 intel_display_power_put(dev_priv, power_domain);
10035 /* VESA 640x480x72Hz mode to set on the pipe */
10036 static const struct drm_display_mode load_detect_mode = {
10037 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10038 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10041 struct drm_framebuffer *
10042 intel_framebuffer_create(struct drm_i915_gem_object *obj,
10043 struct drm_mode_fb_cmd2 *mode_cmd)
10045 struct intel_framebuffer *intel_fb;
10048 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10050 return ERR_PTR(-ENOMEM);
10052 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
10056 return &intel_fb->base;
10060 return ERR_PTR(ret);
10063 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
10064 struct drm_crtc *crtc)
10066 struct drm_plane *plane;
10067 struct drm_plane_state *plane_state;
10070 ret = drm_atomic_add_affected_planes(state, crtc);
10074 for_each_new_plane_in_state(state, plane, plane_state, i) {
10075 if (plane_state->crtc != crtc)
10078 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
10082 drm_atomic_set_fb_for_plane(plane_state, NULL);
10088 int intel_get_load_detect_pipe(struct drm_connector *connector,
10089 const struct drm_display_mode *mode,
10090 struct intel_load_detect_pipe *old,
10091 struct drm_modeset_acquire_ctx *ctx)
10093 struct intel_crtc *intel_crtc;
10094 struct intel_encoder *intel_encoder =
10095 intel_attached_encoder(connector);
10096 struct drm_crtc *possible_crtc;
10097 struct drm_encoder *encoder = &intel_encoder->base;
10098 struct drm_crtc *crtc = NULL;
10099 struct drm_device *dev = encoder->dev;
10100 struct drm_i915_private *dev_priv = to_i915(dev);
10101 struct drm_mode_config *config = &dev->mode_config;
10102 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10103 struct drm_connector_state *connector_state;
10104 struct intel_crtc_state *crtc_state;
10107 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10108 connector->base.id, connector->name,
10109 encoder->base.id, encoder->name);
10111 old->restore_state = NULL;
10113 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
10116 * Algorithm gets a little messy:
10118 * - if the connector already has an assigned crtc, use it (but make
10119 * sure it's on first)
10121 * - try to find the first unused crtc that can drive this connector,
10122 * and use that if we find one
10125 /* See if we already have a CRTC for this connector */
10126 if (connector->state->crtc) {
10127 crtc = connector->state->crtc;
10129 ret = drm_modeset_lock(&crtc->mutex, ctx);
10133 /* Make sure the crtc and connector are running */
10137 /* Find an unused one (if possible) */
10138 for_each_crtc(dev, possible_crtc) {
10140 if (!(encoder->possible_crtcs & (1 << i)))
10143 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10147 if (possible_crtc->state->enable) {
10148 drm_modeset_unlock(&possible_crtc->mutex);
10152 crtc = possible_crtc;
10157 * If we didn't find an unused CRTC, don't use any.
10160 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10166 intel_crtc = to_intel_crtc(crtc);
10168 state = drm_atomic_state_alloc(dev);
10169 restore_state = drm_atomic_state_alloc(dev);
10170 if (!state || !restore_state) {
10175 state->acquire_ctx = ctx;
10176 restore_state->acquire_ctx = ctx;
10178 connector_state = drm_atomic_get_connector_state(state, connector);
10179 if (IS_ERR(connector_state)) {
10180 ret = PTR_ERR(connector_state);
10184 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10188 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10189 if (IS_ERR(crtc_state)) {
10190 ret = PTR_ERR(crtc_state);
10194 crtc_state->base.active = crtc_state->base.enable = true;
10197 mode = &load_detect_mode;
10199 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10203 ret = intel_modeset_disable_planes(state, crtc);
10207 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10209 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10211 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10213 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10217 ret = drm_atomic_commit(state);
10219 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10223 old->restore_state = restore_state;
10224 drm_atomic_state_put(state);
10226 /* let the connector get through one full cycle before testing */
10227 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10232 drm_atomic_state_put(state);
10235 if (restore_state) {
10236 drm_atomic_state_put(restore_state);
10237 restore_state = NULL;
10240 if (ret == -EDEADLK)
10246 void intel_release_load_detect_pipe(struct drm_connector *connector,
10247 struct intel_load_detect_pipe *old,
10248 struct drm_modeset_acquire_ctx *ctx)
10250 struct intel_encoder *intel_encoder =
10251 intel_attached_encoder(connector);
10252 struct drm_encoder *encoder = &intel_encoder->base;
10253 struct drm_atomic_state *state = old->restore_state;
10256 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10257 connector->base.id, connector->name,
10258 encoder->base.id, encoder->name);
10263 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10265 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10266 drm_atomic_state_put(state);
10269 static int i9xx_pll_refclk(struct drm_device *dev,
10270 const struct intel_crtc_state *pipe_config)
10272 struct drm_i915_private *dev_priv = to_i915(dev);
10273 u32 dpll = pipe_config->dpll_hw_state.dpll;
10275 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10276 return dev_priv->vbt.lvds_ssc_freq;
10277 else if (HAS_PCH_SPLIT(dev_priv))
10279 else if (!IS_GEN2(dev_priv))
10285 /* Returns the clock of the currently programmed mode of the given pipe. */
10286 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10287 struct intel_crtc_state *pipe_config)
10289 struct drm_device *dev = crtc->base.dev;
10290 struct drm_i915_private *dev_priv = to_i915(dev);
10291 int pipe = pipe_config->cpu_transcoder;
10292 u32 dpll = pipe_config->dpll_hw_state.dpll;
10296 int refclk = i9xx_pll_refclk(dev, pipe_config);
10298 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10299 fp = pipe_config->dpll_hw_state.fp0;
10301 fp = pipe_config->dpll_hw_state.fp1;
10303 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10304 if (IS_PINEVIEW(dev_priv)) {
10305 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10306 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10308 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10309 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10312 if (!IS_GEN2(dev_priv)) {
10313 if (IS_PINEVIEW(dev_priv))
10314 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10315 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10317 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10318 DPLL_FPA01_P1_POST_DIV_SHIFT);
10320 switch (dpll & DPLL_MODE_MASK) {
10321 case DPLLB_MODE_DAC_SERIAL:
10322 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10325 case DPLLB_MODE_LVDS:
10326 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10330 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10331 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10335 if (IS_PINEVIEW(dev_priv))
10336 port_clock = pnv_calc_dpll_params(refclk, &clock);
10338 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10340 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10341 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10344 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10345 DPLL_FPA01_P1_POST_DIV_SHIFT);
10347 if (lvds & LVDS_CLKB_POWER_UP)
10352 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10355 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10356 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10358 if (dpll & PLL_P2_DIVIDE_BY_4)
10364 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10368 * This value includes pixel_multiplier. We will use
10369 * port_clock to compute adjusted_mode.crtc_clock in the
10370 * encoder's get_config() function.
10372 pipe_config->port_clock = port_clock;
10375 int intel_dotclock_calculate(int link_freq,
10376 const struct intel_link_m_n *m_n)
10379 * The calculation for the data clock is:
10380 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10381 * But we want to avoid losing precison if possible, so:
10382 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10384 * and the link clock is simpler:
10385 * link_clock = (m * link_clock) / n
10391 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10394 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10395 struct intel_crtc_state *pipe_config)
10397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10399 /* read out port_clock from the DPLL */
10400 i9xx_crtc_clock_get(crtc, pipe_config);
10403 * In case there is an active pipe without active ports,
10404 * we may need some idea for the dotclock anyway.
10405 * Calculate one based on the FDI configuration.
10407 pipe_config->base.adjusted_mode.crtc_clock =
10408 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10409 &pipe_config->fdi_m_n);
10412 /* Returns the currently programmed mode of the given encoder. */
10413 struct drm_display_mode *
10414 intel_encoder_current_mode(struct intel_encoder *encoder)
10416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10417 struct intel_crtc_state *crtc_state;
10418 struct drm_display_mode *mode;
10419 struct intel_crtc *crtc;
10422 if (!encoder->get_hw_state(encoder, &pipe))
10425 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10427 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10431 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10437 crtc_state->base.crtc = &crtc->base;
10439 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10445 encoder->get_config(encoder, crtc_state);
10447 intel_mode_from_pipe_config(mode, crtc_state);
10454 static void intel_crtc_destroy(struct drm_crtc *crtc)
10456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10458 drm_crtc_cleanup(crtc);
10463 * intel_wm_need_update - Check whether watermarks need updating
10464 * @plane: drm plane
10465 * @state: new plane state
10467 * Check current plane state versus the new one to determine whether
10468 * watermarks need to be recalculated.
10470 * Returns true or false.
10472 static bool intel_wm_need_update(struct drm_plane *plane,
10473 struct drm_plane_state *state)
10475 struct intel_plane_state *new = to_intel_plane_state(state);
10476 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10478 /* Update watermarks on tiling or size changes. */
10479 if (new->base.visible != cur->base.visible)
10482 if (!cur->base.fb || !new->base.fb)
10485 if (cur->base.fb->modifier != new->base.fb->modifier ||
10486 cur->base.rotation != new->base.rotation ||
10487 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10488 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10489 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10490 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10496 static bool needs_scaling(const struct intel_plane_state *state)
10498 int src_w = drm_rect_width(&state->base.src) >> 16;
10499 int src_h = drm_rect_height(&state->base.src) >> 16;
10500 int dst_w = drm_rect_width(&state->base.dst);
10501 int dst_h = drm_rect_height(&state->base.dst);
10503 return (src_w != dst_w || src_h != dst_h);
10506 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10507 struct drm_crtc_state *crtc_state,
10508 const struct intel_plane_state *old_plane_state,
10509 struct drm_plane_state *plane_state)
10511 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10512 struct drm_crtc *crtc = crtc_state->crtc;
10513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10514 struct intel_plane *plane = to_intel_plane(plane_state->plane);
10515 struct drm_device *dev = crtc->dev;
10516 struct drm_i915_private *dev_priv = to_i915(dev);
10517 bool mode_changed = needs_modeset(crtc_state);
10518 bool was_crtc_enabled = old_crtc_state->base.active;
10519 bool is_crtc_enabled = crtc_state->active;
10520 bool turn_off, turn_on, visible, was_visible;
10521 struct drm_framebuffer *fb = plane_state->fb;
10524 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10525 ret = skl_update_scaler_plane(
10526 to_intel_crtc_state(crtc_state),
10527 to_intel_plane_state(plane_state));
10532 was_visible = old_plane_state->base.visible;
10533 visible = plane_state->visible;
10535 if (!was_crtc_enabled && WARN_ON(was_visible))
10536 was_visible = false;
10539 * Visibility is calculated as if the crtc was on, but
10540 * after scaler setup everything depends on it being off
10541 * when the crtc isn't active.
10543 * FIXME this is wrong for watermarks. Watermarks should also
10544 * be computed as if the pipe would be active. Perhaps move
10545 * per-plane wm computation to the .check_plane() hook, and
10546 * only combine the results from all planes in the current place?
10548 if (!is_crtc_enabled) {
10549 plane_state->visible = visible = false;
10550 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10553 if (!was_visible && !visible)
10556 if (fb != old_plane_state->base.fb)
10557 pipe_config->fb_changed = true;
10559 turn_off = was_visible && (!visible || mode_changed);
10560 turn_on = visible && (!was_visible || mode_changed);
10562 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10563 intel_crtc->base.base.id, intel_crtc->base.name,
10564 plane->base.base.id, plane->base.name,
10565 fb ? fb->base.id : -1);
10567 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10568 plane->base.base.id, plane->base.name,
10569 was_visible, visible,
10570 turn_off, turn_on, mode_changed);
10573 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10574 pipe_config->update_wm_pre = true;
10576 /* must disable cxsr around plane enable/disable */
10577 if (plane->id != PLANE_CURSOR)
10578 pipe_config->disable_cxsr = true;
10579 } else if (turn_off) {
10580 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10581 pipe_config->update_wm_post = true;
10583 /* must disable cxsr around plane enable/disable */
10584 if (plane->id != PLANE_CURSOR)
10585 pipe_config->disable_cxsr = true;
10586 } else if (intel_wm_need_update(&plane->base, plane_state)) {
10587 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10588 /* FIXME bollocks */
10589 pipe_config->update_wm_pre = true;
10590 pipe_config->update_wm_post = true;
10594 if (visible || was_visible)
10595 pipe_config->fb_bits |= plane->frontbuffer_bit;
10598 * WaCxSRDisabledForSpriteScaling:ivb
10600 * cstate->update_wm was already set above, so this flag will
10601 * take effect when we commit and program watermarks.
10603 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10604 needs_scaling(to_intel_plane_state(plane_state)) &&
10605 !needs_scaling(old_plane_state))
10606 pipe_config->disable_lp_wm = true;
10611 static bool encoders_cloneable(const struct intel_encoder *a,
10612 const struct intel_encoder *b)
10614 /* masks could be asymmetric, so check both ways */
10615 return a == b || (a->cloneable & (1 << b->type) &&
10616 b->cloneable & (1 << a->type));
10619 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10620 struct intel_crtc *crtc,
10621 struct intel_encoder *encoder)
10623 struct intel_encoder *source_encoder;
10624 struct drm_connector *connector;
10625 struct drm_connector_state *connector_state;
10628 for_each_new_connector_in_state(state, connector, connector_state, i) {
10629 if (connector_state->crtc != &crtc->base)
10633 to_intel_encoder(connector_state->best_encoder);
10634 if (!encoders_cloneable(encoder, source_encoder))
10641 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10642 struct drm_crtc_state *crtc_state)
10644 struct drm_device *dev = crtc->dev;
10645 struct drm_i915_private *dev_priv = to_i915(dev);
10646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10647 struct intel_crtc_state *pipe_config =
10648 to_intel_crtc_state(crtc_state);
10649 struct drm_atomic_state *state = crtc_state->state;
10651 bool mode_changed = needs_modeset(crtc_state);
10653 if (mode_changed && !crtc_state->active)
10654 pipe_config->update_wm_post = true;
10656 if (mode_changed && crtc_state->enable &&
10657 dev_priv->display.crtc_compute_clock &&
10658 !WARN_ON(pipe_config->shared_dpll)) {
10659 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10665 if (crtc_state->color_mgmt_changed) {
10666 ret = intel_color_check(crtc, crtc_state);
10671 * Changing color management on Intel hardware is
10672 * handled as part of planes update.
10674 crtc_state->planes_changed = true;
10678 if (dev_priv->display.compute_pipe_wm) {
10679 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10681 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10686 if (dev_priv->display.compute_intermediate_wm &&
10687 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10688 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10692 * Calculate 'intermediate' watermarks that satisfy both the
10693 * old state and the new state. We can program these
10696 ret = dev_priv->display.compute_intermediate_wm(dev,
10700 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10703 } else if (dev_priv->display.compute_intermediate_wm) {
10704 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10705 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10708 if (INTEL_GEN(dev_priv) >= 9) {
10710 ret = skl_update_scaler_crtc(pipe_config);
10713 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10716 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10720 if (HAS_IPS(dev_priv))
10721 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10726 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10727 .atomic_begin = intel_begin_crtc_commit,
10728 .atomic_flush = intel_finish_crtc_commit,
10729 .atomic_check = intel_crtc_atomic_check,
10732 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10734 struct intel_connector *connector;
10735 struct drm_connector_list_iter conn_iter;
10737 drm_connector_list_iter_begin(dev, &conn_iter);
10738 for_each_intel_connector_iter(connector, &conn_iter) {
10739 if (connector->base.state->crtc)
10740 drm_connector_put(&connector->base);
10742 if (connector->base.encoder) {
10743 connector->base.state->best_encoder =
10744 connector->base.encoder;
10745 connector->base.state->crtc =
10746 connector->base.encoder->crtc;
10748 drm_connector_get(&connector->base);
10750 connector->base.state->best_encoder = NULL;
10751 connector->base.state->crtc = NULL;
10754 drm_connector_list_iter_end(&conn_iter);
10758 connected_sink_compute_bpp(struct intel_connector *connector,
10759 struct intel_crtc_state *pipe_config)
10761 const struct drm_display_info *info = &connector->base.display_info;
10762 int bpp = pipe_config->pipe_bpp;
10764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10765 connector->base.base.id,
10766 connector->base.name);
10768 /* Don't use an invalid EDID bpc value */
10769 if (info->bpc != 0 && info->bpc * 3 < bpp) {
10770 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10771 bpp, info->bpc * 3);
10772 pipe_config->pipe_bpp = info->bpc * 3;
10775 /* Clamp bpp to 8 on screens without EDID 1.4 */
10776 if (info->bpc == 0 && bpp > 24) {
10777 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10779 pipe_config->pipe_bpp = 24;
10784 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10785 struct intel_crtc_state *pipe_config)
10787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10788 struct drm_atomic_state *state;
10789 struct drm_connector *connector;
10790 struct drm_connector_state *connector_state;
10793 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10794 IS_CHERRYVIEW(dev_priv)))
10796 else if (INTEL_GEN(dev_priv) >= 5)
10802 pipe_config->pipe_bpp = bpp;
10804 state = pipe_config->base.state;
10806 /* Clamp display bpp to EDID value */
10807 for_each_new_connector_in_state(state, connector, connector_state, i) {
10808 if (connector_state->crtc != &crtc->base)
10811 connected_sink_compute_bpp(to_intel_connector(connector),
10818 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10820 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10821 "type: 0x%x flags: 0x%x\n",
10823 mode->crtc_hdisplay, mode->crtc_hsync_start,
10824 mode->crtc_hsync_end, mode->crtc_htotal,
10825 mode->crtc_vdisplay, mode->crtc_vsync_start,
10826 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10830 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10831 unsigned int lane_count, struct intel_link_m_n *m_n)
10833 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10835 m_n->gmch_m, m_n->gmch_n,
10836 m_n->link_m, m_n->link_n, m_n->tu);
10839 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10841 static const char * const output_type_str[] = {
10842 OUTPUT_TYPE(UNUSED),
10843 OUTPUT_TYPE(ANALOG),
10847 OUTPUT_TYPE(TVOUT),
10853 OUTPUT_TYPE(DP_MST),
10858 static void snprintf_output_types(char *buf, size_t len,
10859 unsigned int output_types)
10866 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10869 if ((output_types & BIT(i)) == 0)
10872 r = snprintf(str, len, "%s%s",
10873 str != buf ? "," : "", output_type_str[i]);
10879 output_types &= ~BIT(i);
10882 WARN_ON_ONCE(output_types != 0);
10885 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10886 struct intel_crtc_state *pipe_config,
10887 const char *context)
10889 struct drm_device *dev = crtc->base.dev;
10890 struct drm_i915_private *dev_priv = to_i915(dev);
10891 struct drm_plane *plane;
10892 struct intel_plane *intel_plane;
10893 struct intel_plane_state *state;
10894 struct drm_framebuffer *fb;
10897 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10898 crtc->base.base.id, crtc->base.name, context);
10900 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10901 DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10902 buf, pipe_config->output_types);
10904 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10905 transcoder_name(pipe_config->cpu_transcoder),
10906 pipe_config->pipe_bpp, pipe_config->dither);
10908 if (pipe_config->has_pch_encoder)
10909 intel_dump_m_n_config(pipe_config, "fdi",
10910 pipe_config->fdi_lanes,
10911 &pipe_config->fdi_m_n);
10913 if (pipe_config->ycbcr420)
10914 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10916 if (intel_crtc_has_dp_encoder(pipe_config)) {
10917 intel_dump_m_n_config(pipe_config, "dp m_n",
10918 pipe_config->lane_count, &pipe_config->dp_m_n);
10919 if (pipe_config->has_drrs)
10920 intel_dump_m_n_config(pipe_config, "dp m2_n2",
10921 pipe_config->lane_count,
10922 &pipe_config->dp_m2_n2);
10925 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10926 pipe_config->has_audio, pipe_config->has_infoframe);
10928 DRM_DEBUG_KMS("requested mode:\n");
10929 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10930 DRM_DEBUG_KMS("adjusted mode:\n");
10931 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10932 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10933 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10934 pipe_config->port_clock,
10935 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10936 pipe_config->pixel_rate);
10938 if (INTEL_GEN(dev_priv) >= 9)
10939 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10941 pipe_config->scaler_state.scaler_users,
10942 pipe_config->scaler_state.scaler_id);
10944 if (HAS_GMCH_DISPLAY(dev_priv))
10945 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10946 pipe_config->gmch_pfit.control,
10947 pipe_config->gmch_pfit.pgm_ratios,
10948 pipe_config->gmch_pfit.lvds_border_bits);
10950 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10951 pipe_config->pch_pfit.pos,
10952 pipe_config->pch_pfit.size,
10953 enableddisabled(pipe_config->pch_pfit.enabled));
10955 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10956 pipe_config->ips_enabled, pipe_config->double_wide);
10958 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10960 DRM_DEBUG_KMS("planes on this crtc\n");
10961 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10962 struct drm_format_name_buf format_name;
10963 intel_plane = to_intel_plane(plane);
10964 if (intel_plane->pipe != crtc->pipe)
10967 state = to_intel_plane_state(plane->state);
10968 fb = state->base.fb;
10970 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10971 plane->base.id, plane->name, state->scaler_id);
10975 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10976 plane->base.id, plane->name,
10977 fb->base.id, fb->width, fb->height,
10978 drm_get_format_name(fb->format->format, &format_name));
10979 if (INTEL_GEN(dev_priv) >= 9)
10980 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10982 state->base.src.x1 >> 16,
10983 state->base.src.y1 >> 16,
10984 drm_rect_width(&state->base.src) >> 16,
10985 drm_rect_height(&state->base.src) >> 16,
10986 state->base.dst.x1, state->base.dst.y1,
10987 drm_rect_width(&state->base.dst),
10988 drm_rect_height(&state->base.dst));
10992 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10994 struct drm_device *dev = state->dev;
10995 struct drm_connector *connector;
10996 struct drm_connector_list_iter conn_iter;
10997 unsigned int used_ports = 0;
10998 unsigned int used_mst_ports = 0;
11002 * Walk the connector list instead of the encoder
11003 * list to detect the problem on ddi platforms
11004 * where there's just one encoder per digital port.
11006 drm_connector_list_iter_begin(dev, &conn_iter);
11007 drm_for_each_connector_iter(connector, &conn_iter) {
11008 struct drm_connector_state *connector_state;
11009 struct intel_encoder *encoder;
11011 connector_state = drm_atomic_get_new_connector_state(state, connector);
11012 if (!connector_state)
11013 connector_state = connector->state;
11015 if (!connector_state->best_encoder)
11018 encoder = to_intel_encoder(connector_state->best_encoder);
11020 WARN_ON(!connector_state->crtc);
11022 switch (encoder->type) {
11023 unsigned int port_mask;
11024 case INTEL_OUTPUT_DDI:
11025 if (WARN_ON(!HAS_DDI(to_i915(dev))))
11027 /* else: fall through */
11028 case INTEL_OUTPUT_DP:
11029 case INTEL_OUTPUT_HDMI:
11030 case INTEL_OUTPUT_EDP:
11031 port_mask = 1 << encoder->port;
11033 /* the same port mustn't appear more than once */
11034 if (used_ports & port_mask)
11037 used_ports |= port_mask;
11039 case INTEL_OUTPUT_DP_MST:
11041 1 << encoder->port;
11047 drm_connector_list_iter_end(&conn_iter);
11049 /* can't mix MST and SST/HDMI on the same port */
11050 if (used_ports & used_mst_ports)
11057 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11059 struct drm_i915_private *dev_priv =
11060 to_i915(crtc_state->base.crtc->dev);
11061 struct intel_crtc_scaler_state scaler_state;
11062 struct intel_dpll_hw_state dpll_hw_state;
11063 struct intel_shared_dpll *shared_dpll;
11064 struct intel_crtc_wm_state wm_state;
11065 bool force_thru, ips_force_disable;
11067 /* FIXME: before the switch to atomic started, a new pipe_config was
11068 * kzalloc'd. Code that depends on any field being zero should be
11069 * fixed, so that the crtc_state can be safely duplicated. For now,
11070 * only fields that are know to not cause problems are preserved. */
11072 scaler_state = crtc_state->scaler_state;
11073 shared_dpll = crtc_state->shared_dpll;
11074 dpll_hw_state = crtc_state->dpll_hw_state;
11075 force_thru = crtc_state->pch_pfit.force_thru;
11076 ips_force_disable = crtc_state->ips_force_disable;
11077 if (IS_G4X(dev_priv) ||
11078 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11079 wm_state = crtc_state->wm;
11081 /* Keep base drm_crtc_state intact, only clear our extended struct */
11082 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11083 memset(&crtc_state->base + 1, 0,
11084 sizeof(*crtc_state) - sizeof(crtc_state->base));
11086 crtc_state->scaler_state = scaler_state;
11087 crtc_state->shared_dpll = shared_dpll;
11088 crtc_state->dpll_hw_state = dpll_hw_state;
11089 crtc_state->pch_pfit.force_thru = force_thru;
11090 crtc_state->ips_force_disable = ips_force_disable;
11091 if (IS_G4X(dev_priv) ||
11092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11093 crtc_state->wm = wm_state;
11097 intel_modeset_pipe_config(struct drm_crtc *crtc,
11098 struct intel_crtc_state *pipe_config)
11100 struct drm_atomic_state *state = pipe_config->base.state;
11101 struct intel_encoder *encoder;
11102 struct drm_connector *connector;
11103 struct drm_connector_state *connector_state;
11104 int base_bpp, ret = -EINVAL;
11108 clear_intel_crtc_state(pipe_config);
11110 pipe_config->cpu_transcoder =
11111 (enum transcoder) to_intel_crtc(crtc)->pipe;
11114 * Sanitize sync polarity flags based on requested ones. If neither
11115 * positive or negative polarity is requested, treat this as meaning
11116 * negative polarity.
11118 if (!(pipe_config->base.adjusted_mode.flags &
11119 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11120 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11122 if (!(pipe_config->base.adjusted_mode.flags &
11123 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11124 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11126 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11132 * Determine the real pipe dimensions. Note that stereo modes can
11133 * increase the actual pipe size due to the frame doubling and
11134 * insertion of additional space for blanks between the frame. This
11135 * is stored in the crtc timings. We use the requested mode to do this
11136 * computation to clearly distinguish it from the adjusted mode, which
11137 * can be changed by the connectors in the below retry loop.
11139 drm_mode_get_hv_timing(&pipe_config->base.mode,
11140 &pipe_config->pipe_src_w,
11141 &pipe_config->pipe_src_h);
11143 for_each_new_connector_in_state(state, connector, connector_state, i) {
11144 if (connector_state->crtc != crtc)
11147 encoder = to_intel_encoder(connector_state->best_encoder);
11149 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11150 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11155 * Determine output_types before calling the .compute_config()
11156 * hooks so that the hooks can use this information safely.
11158 if (encoder->compute_output_type)
11159 pipe_config->output_types |=
11160 BIT(encoder->compute_output_type(encoder, pipe_config,
11163 pipe_config->output_types |= BIT(encoder->type);
11167 /* Ensure the port clock defaults are reset when retrying. */
11168 pipe_config->port_clock = 0;
11169 pipe_config->pixel_multiplier = 1;
11171 /* Fill in default crtc timings, allow encoders to overwrite them. */
11172 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11173 CRTC_STEREO_DOUBLE);
11175 /* Pass our mode to the connectors and the CRTC to give them a chance to
11176 * adjust it according to limitations or connector properties, and also
11177 * a chance to reject the mode entirely.
11179 for_each_new_connector_in_state(state, connector, connector_state, i) {
11180 if (connector_state->crtc != crtc)
11183 encoder = to_intel_encoder(connector_state->best_encoder);
11185 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11186 DRM_DEBUG_KMS("Encoder config failure\n");
11191 /* Set default port clock if not overwritten by the encoder. Needs to be
11192 * done afterwards in case the encoder adjusts the mode. */
11193 if (!pipe_config->port_clock)
11194 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11195 * pipe_config->pixel_multiplier;
11197 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11199 DRM_DEBUG_KMS("CRTC fixup failed\n");
11203 if (ret == RETRY) {
11204 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11209 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11211 goto encoder_retry;
11214 /* Dithering seems to not pass-through bits correctly when it should, so
11215 * only enable it on 6bpc panels and when its not a compliance
11216 * test requesting 6bpc video pattern.
11218 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11219 !pipe_config->dither_force_disable;
11220 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11221 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11227 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11231 if (clock1 == clock2)
11234 if (!clock1 || !clock2)
11237 diff = abs(clock1 - clock2);
11239 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11246 intel_compare_m_n(unsigned int m, unsigned int n,
11247 unsigned int m2, unsigned int n2,
11250 if (m == m2 && n == n2)
11253 if (exact || !m || !n || !m2 || !n2)
11256 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11263 } else if (n < n2) {
11273 return intel_fuzzy_clock_check(m, m2);
11277 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11278 struct intel_link_m_n *m2_n2,
11281 if (m_n->tu == m2_n2->tu &&
11282 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11283 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11284 intel_compare_m_n(m_n->link_m, m_n->link_n,
11285 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11295 static void __printf(3, 4)
11296 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11298 struct va_format vaf;
11301 va_start(args, format);
11306 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11308 drm_err("mismatch in %s %pV", name, &vaf);
11314 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11315 struct intel_crtc_state *current_config,
11316 struct intel_crtc_state *pipe_config,
11320 bool fixup_inherited = adjust &&
11321 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11322 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11324 #define PIPE_CONF_CHECK_X(name) do { \
11325 if (current_config->name != pipe_config->name) { \
11326 pipe_config_err(adjust, __stringify(name), \
11327 "(expected 0x%08x, found 0x%08x)\n", \
11328 current_config->name, \
11329 pipe_config->name); \
11334 #define PIPE_CONF_CHECK_I(name) do { \
11335 if (current_config->name != pipe_config->name) { \
11336 pipe_config_err(adjust, __stringify(name), \
11337 "(expected %i, found %i)\n", \
11338 current_config->name, \
11339 pipe_config->name); \
11344 #define PIPE_CONF_CHECK_BOOL(name) do { \
11345 if (current_config->name != pipe_config->name) { \
11346 pipe_config_err(adjust, __stringify(name), \
11347 "(expected %s, found %s)\n", \
11348 yesno(current_config->name), \
11349 yesno(pipe_config->name)); \
11355 * Checks state where we only read out the enabling, but not the entire
11356 * state itself (like full infoframes or ELD for audio). These states
11357 * require a full modeset on bootup to fix up.
11359 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11360 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11361 PIPE_CONF_CHECK_BOOL(name); \
11363 pipe_config_err(adjust, __stringify(name), \
11364 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11365 yesno(current_config->name), \
11366 yesno(pipe_config->name)); \
11371 #define PIPE_CONF_CHECK_P(name) do { \
11372 if (current_config->name != pipe_config->name) { \
11373 pipe_config_err(adjust, __stringify(name), \
11374 "(expected %p, found %p)\n", \
11375 current_config->name, \
11376 pipe_config->name); \
11381 #define PIPE_CONF_CHECK_M_N(name) do { \
11382 if (!intel_compare_link_m_n(¤t_config->name, \
11383 &pipe_config->name,\
11385 pipe_config_err(adjust, __stringify(name), \
11386 "(expected tu %i gmch %i/%i link %i/%i, " \
11387 "found tu %i, gmch %i/%i link %i/%i)\n", \
11388 current_config->name.tu, \
11389 current_config->name.gmch_m, \
11390 current_config->name.gmch_n, \
11391 current_config->name.link_m, \
11392 current_config->name.link_n, \
11393 pipe_config->name.tu, \
11394 pipe_config->name.gmch_m, \
11395 pipe_config->name.gmch_n, \
11396 pipe_config->name.link_m, \
11397 pipe_config->name.link_n); \
11402 /* This is required for BDW+ where there is only one set of registers for
11403 * switching between high and low RR.
11404 * This macro can be used whenever a comparison has to be made between one
11405 * hw state and multiple sw state variables.
11407 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11408 if (!intel_compare_link_m_n(¤t_config->name, \
11409 &pipe_config->name, adjust) && \
11410 !intel_compare_link_m_n(¤t_config->alt_name, \
11411 &pipe_config->name, adjust)) { \
11412 pipe_config_err(adjust, __stringify(name), \
11413 "(expected tu %i gmch %i/%i link %i/%i, " \
11414 "or tu %i gmch %i/%i link %i/%i, " \
11415 "found tu %i, gmch %i/%i link %i/%i)\n", \
11416 current_config->name.tu, \
11417 current_config->name.gmch_m, \
11418 current_config->name.gmch_n, \
11419 current_config->name.link_m, \
11420 current_config->name.link_n, \
11421 current_config->alt_name.tu, \
11422 current_config->alt_name.gmch_m, \
11423 current_config->alt_name.gmch_n, \
11424 current_config->alt_name.link_m, \
11425 current_config->alt_name.link_n, \
11426 pipe_config->name.tu, \
11427 pipe_config->name.gmch_m, \
11428 pipe_config->name.gmch_n, \
11429 pipe_config->name.link_m, \
11430 pipe_config->name.link_n); \
11435 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11436 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11437 pipe_config_err(adjust, __stringify(name), \
11438 "(%x) (expected %i, found %i)\n", \
11440 current_config->name & (mask), \
11441 pipe_config->name & (mask)); \
11446 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11447 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11448 pipe_config_err(adjust, __stringify(name), \
11449 "(expected %i, found %i)\n", \
11450 current_config->name, \
11451 pipe_config->name); \
11456 #define PIPE_CONF_QUIRK(quirk) \
11457 ((current_config->quirks | pipe_config->quirks) & (quirk))
11459 PIPE_CONF_CHECK_I(cpu_transcoder);
11461 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11462 PIPE_CONF_CHECK_I(fdi_lanes);
11463 PIPE_CONF_CHECK_M_N(fdi_m_n);
11465 PIPE_CONF_CHECK_I(lane_count);
11466 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11468 if (INTEL_GEN(dev_priv) < 8) {
11469 PIPE_CONF_CHECK_M_N(dp_m_n);
11471 if (current_config->has_drrs)
11472 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11474 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11476 PIPE_CONF_CHECK_X(output_types);
11478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11492 PIPE_CONF_CHECK_I(pixel_multiplier);
11493 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11494 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11495 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11496 PIPE_CONF_CHECK_BOOL(limited_color_range);
11498 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11499 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11500 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11501 PIPE_CONF_CHECK_BOOL(ycbcr420);
11503 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11506 DRM_MODE_FLAG_INTERLACE);
11508 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11509 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11510 DRM_MODE_FLAG_PHSYNC);
11511 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11512 DRM_MODE_FLAG_NHSYNC);
11513 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11514 DRM_MODE_FLAG_PVSYNC);
11515 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11516 DRM_MODE_FLAG_NVSYNC);
11519 PIPE_CONF_CHECK_X(gmch_pfit.control);
11520 /* pfit ratios are autocomputed by the hw on gen4+ */
11521 if (INTEL_GEN(dev_priv) < 4)
11522 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11523 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11526 PIPE_CONF_CHECK_I(pipe_src_w);
11527 PIPE_CONF_CHECK_I(pipe_src_h);
11529 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11530 if (current_config->pch_pfit.enabled) {
11531 PIPE_CONF_CHECK_X(pch_pfit.pos);
11532 PIPE_CONF_CHECK_X(pch_pfit.size);
11535 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11536 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11539 PIPE_CONF_CHECK_BOOL(double_wide);
11541 PIPE_CONF_CHECK_P(shared_dpll);
11542 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11543 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11544 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11545 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11546 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11547 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11548 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11549 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11550 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11551 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11552 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11553 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11554 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11555 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11556 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11557 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11558 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11559 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11560 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11561 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11562 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11563 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
11564 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
11565 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
11566 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
11567 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
11568 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
11569 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
11570 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
11571 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
11572 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
11574 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11575 PIPE_CONF_CHECK_X(dsi_pll.div);
11577 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11578 PIPE_CONF_CHECK_I(pipe_bpp);
11580 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11581 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11583 PIPE_CONF_CHECK_I(min_voltage_level);
11585 #undef PIPE_CONF_CHECK_X
11586 #undef PIPE_CONF_CHECK_I
11587 #undef PIPE_CONF_CHECK_BOOL
11588 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11589 #undef PIPE_CONF_CHECK_P
11590 #undef PIPE_CONF_CHECK_FLAGS
11591 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11592 #undef PIPE_CONF_QUIRK
11597 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11598 const struct intel_crtc_state *pipe_config)
11600 if (pipe_config->has_pch_encoder) {
11601 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11602 &pipe_config->fdi_m_n);
11603 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11606 * FDI already provided one idea for the dotclock.
11607 * Yell if the encoder disagrees.
11609 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11610 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11611 fdi_dotclock, dotclock);
11615 static void verify_wm_state(struct drm_crtc *crtc,
11616 struct drm_crtc_state *new_state)
11618 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11619 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11620 struct skl_pipe_wm hw_wm, *sw_wm;
11621 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11622 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11624 const enum pipe pipe = intel_crtc->pipe;
11625 int plane, level, max_level = ilk_wm_max_level(dev_priv);
11627 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11630 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11631 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11633 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11634 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11636 if (INTEL_GEN(dev_priv) >= 11)
11637 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11638 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11639 sw_ddb->enabled_slices,
11640 hw_ddb.enabled_slices);
11642 for_each_universal_plane(dev_priv, pipe, plane) {
11643 hw_plane_wm = &hw_wm.planes[plane];
11644 sw_plane_wm = &sw_wm->planes[plane];
11647 for (level = 0; level <= max_level; level++) {
11648 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11649 &sw_plane_wm->wm[level]))
11652 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11653 pipe_name(pipe), plane + 1, level,
11654 sw_plane_wm->wm[level].plane_en,
11655 sw_plane_wm->wm[level].plane_res_b,
11656 sw_plane_wm->wm[level].plane_res_l,
11657 hw_plane_wm->wm[level].plane_en,
11658 hw_plane_wm->wm[level].plane_res_b,
11659 hw_plane_wm->wm[level].plane_res_l);
11662 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11663 &sw_plane_wm->trans_wm)) {
11664 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11665 pipe_name(pipe), plane + 1,
11666 sw_plane_wm->trans_wm.plane_en,
11667 sw_plane_wm->trans_wm.plane_res_b,
11668 sw_plane_wm->trans_wm.plane_res_l,
11669 hw_plane_wm->trans_wm.plane_en,
11670 hw_plane_wm->trans_wm.plane_res_b,
11671 hw_plane_wm->trans_wm.plane_res_l);
11675 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11676 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11678 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11679 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11680 pipe_name(pipe), plane + 1,
11681 sw_ddb_entry->start, sw_ddb_entry->end,
11682 hw_ddb_entry->start, hw_ddb_entry->end);
11688 * If the cursor plane isn't active, we may not have updated it's ddb
11689 * allocation. In that case since the ddb allocation will be updated
11690 * once the plane becomes visible, we can skip this check
11693 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11694 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11697 for (level = 0; level <= max_level; level++) {
11698 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11699 &sw_plane_wm->wm[level]))
11702 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11703 pipe_name(pipe), level,
11704 sw_plane_wm->wm[level].plane_en,
11705 sw_plane_wm->wm[level].plane_res_b,
11706 sw_plane_wm->wm[level].plane_res_l,
11707 hw_plane_wm->wm[level].plane_en,
11708 hw_plane_wm->wm[level].plane_res_b,
11709 hw_plane_wm->wm[level].plane_res_l);
11712 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11713 &sw_plane_wm->trans_wm)) {
11714 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11716 sw_plane_wm->trans_wm.plane_en,
11717 sw_plane_wm->trans_wm.plane_res_b,
11718 sw_plane_wm->trans_wm.plane_res_l,
11719 hw_plane_wm->trans_wm.plane_en,
11720 hw_plane_wm->trans_wm.plane_res_b,
11721 hw_plane_wm->trans_wm.plane_res_l);
11725 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11726 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11728 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11729 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11731 sw_ddb_entry->start, sw_ddb_entry->end,
11732 hw_ddb_entry->start, hw_ddb_entry->end);
11738 verify_connector_state(struct drm_device *dev,
11739 struct drm_atomic_state *state,
11740 struct drm_crtc *crtc)
11742 struct drm_connector *connector;
11743 struct drm_connector_state *new_conn_state;
11746 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11747 struct drm_encoder *encoder = connector->encoder;
11748 struct drm_crtc_state *crtc_state = NULL;
11750 if (new_conn_state->crtc != crtc)
11754 crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11756 intel_connector_verify_state(crtc_state, new_conn_state);
11758 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11759 "connector's atomic encoder doesn't match legacy encoder\n");
11764 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11766 struct intel_encoder *encoder;
11767 struct drm_connector *connector;
11768 struct drm_connector_state *old_conn_state, *new_conn_state;
11771 for_each_intel_encoder(dev, encoder) {
11772 bool enabled = false, found = false;
11775 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11776 encoder->base.base.id,
11777 encoder->base.name);
11779 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11780 new_conn_state, i) {
11781 if (old_conn_state->best_encoder == &encoder->base)
11784 if (new_conn_state->best_encoder != &encoder->base)
11786 found = enabled = true;
11788 I915_STATE_WARN(new_conn_state->crtc !=
11789 encoder->base.crtc,
11790 "connector's crtc doesn't match encoder crtc\n");
11796 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11797 "encoder's enabled state mismatch "
11798 "(expected %i, found %i)\n",
11799 !!encoder->base.crtc, enabled);
11801 if (!encoder->base.crtc) {
11804 active = encoder->get_hw_state(encoder, &pipe);
11805 I915_STATE_WARN(active,
11806 "encoder detached but still enabled on pipe %c.\n",
11813 verify_crtc_state(struct drm_crtc *crtc,
11814 struct drm_crtc_state *old_crtc_state,
11815 struct drm_crtc_state *new_crtc_state)
11817 struct drm_device *dev = crtc->dev;
11818 struct drm_i915_private *dev_priv = to_i915(dev);
11819 struct intel_encoder *encoder;
11820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11821 struct intel_crtc_state *pipe_config, *sw_config;
11822 struct drm_atomic_state *old_state;
11825 old_state = old_crtc_state->state;
11826 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11827 pipe_config = to_intel_crtc_state(old_crtc_state);
11828 memset(pipe_config, 0, sizeof(*pipe_config));
11829 pipe_config->base.crtc = crtc;
11830 pipe_config->base.state = old_state;
11832 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11834 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11836 /* we keep both pipes enabled on 830 */
11837 if (IS_I830(dev_priv))
11838 active = new_crtc_state->active;
11840 I915_STATE_WARN(new_crtc_state->active != active,
11841 "crtc active state doesn't match with hw state "
11842 "(expected %i, found %i)\n", new_crtc_state->active, active);
11844 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11845 "transitional active state does not match atomic hw state "
11846 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11848 for_each_encoder_on_crtc(dev, crtc, encoder) {
11851 active = encoder->get_hw_state(encoder, &pipe);
11852 I915_STATE_WARN(active != new_crtc_state->active,
11853 "[ENCODER:%i] active %i with crtc active %i\n",
11854 encoder->base.base.id, active, new_crtc_state->active);
11856 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11857 "Encoder connected to wrong pipe %c\n",
11861 encoder->get_config(encoder, pipe_config);
11864 intel_crtc_compute_pixel_rate(pipe_config);
11866 if (!new_crtc_state->active)
11869 intel_pipe_config_sanity_check(dev_priv, pipe_config);
11871 sw_config = to_intel_crtc_state(new_crtc_state);
11872 if (!intel_pipe_config_compare(dev_priv, sw_config,
11873 pipe_config, false)) {
11874 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11875 intel_dump_pipe_config(intel_crtc, pipe_config,
11877 intel_dump_pipe_config(intel_crtc, sw_config,
11883 intel_verify_planes(struct intel_atomic_state *state)
11885 struct intel_plane *plane;
11886 const struct intel_plane_state *plane_state;
11889 for_each_new_intel_plane_in_state(state, plane,
11891 assert_plane(plane, plane_state->base.visible);
11895 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11896 struct intel_shared_dpll *pll,
11897 struct drm_crtc *crtc,
11898 struct drm_crtc_state *new_state)
11900 struct intel_dpll_hw_state dpll_hw_state;
11901 unsigned int crtc_mask;
11904 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11906 DRM_DEBUG_KMS("%s\n", pll->info->name);
11908 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11910 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11911 I915_STATE_WARN(!pll->on && pll->active_mask,
11912 "pll in active use but not on in sw tracking\n");
11913 I915_STATE_WARN(pll->on && !pll->active_mask,
11914 "pll is on but not used by any active crtc\n");
11915 I915_STATE_WARN(pll->on != active,
11916 "pll on state mismatch (expected %i, found %i)\n",
11921 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11922 "more active pll users than references: %x vs %x\n",
11923 pll->active_mask, pll->state.crtc_mask);
11928 crtc_mask = drm_crtc_mask(crtc);
11930 if (new_state->active)
11931 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11932 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11933 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11935 I915_STATE_WARN(pll->active_mask & crtc_mask,
11936 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11937 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11939 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11940 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11941 crtc_mask, pll->state.crtc_mask);
11943 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11945 sizeof(dpll_hw_state)),
11946 "pll hw state mismatch\n");
11950 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11951 struct drm_crtc_state *old_crtc_state,
11952 struct drm_crtc_state *new_crtc_state)
11954 struct drm_i915_private *dev_priv = to_i915(dev);
11955 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11956 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11958 if (new_state->shared_dpll)
11959 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11961 if (old_state->shared_dpll &&
11962 old_state->shared_dpll != new_state->shared_dpll) {
11963 unsigned int crtc_mask = drm_crtc_mask(crtc);
11964 struct intel_shared_dpll *pll = old_state->shared_dpll;
11966 I915_STATE_WARN(pll->active_mask & crtc_mask,
11967 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11968 pipe_name(drm_crtc_index(crtc)));
11969 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11970 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11971 pipe_name(drm_crtc_index(crtc)));
11976 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11977 struct drm_atomic_state *state,
11978 struct drm_crtc_state *old_state,
11979 struct drm_crtc_state *new_state)
11981 if (!needs_modeset(new_state) &&
11982 !to_intel_crtc_state(new_state)->update_pipe)
11985 verify_wm_state(crtc, new_state);
11986 verify_connector_state(crtc->dev, state, crtc);
11987 verify_crtc_state(crtc, old_state, new_state);
11988 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11992 verify_disabled_dpll_state(struct drm_device *dev)
11994 struct drm_i915_private *dev_priv = to_i915(dev);
11997 for (i = 0; i < dev_priv->num_shared_dpll; i++)
11998 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12002 intel_modeset_verify_disabled(struct drm_device *dev,
12003 struct drm_atomic_state *state)
12005 verify_encoder_state(dev, state);
12006 verify_connector_state(dev, state, NULL);
12007 verify_disabled_dpll_state(dev);
12010 static void update_scanline_offset(struct intel_crtc *crtc)
12012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12015 * The scanline counter increments at the leading edge of hsync.
12017 * On most platforms it starts counting from vtotal-1 on the
12018 * first active line. That means the scanline counter value is
12019 * always one less than what we would expect. Ie. just after
12020 * start of vblank, which also occurs at start of hsync (on the
12021 * last active line), the scanline counter will read vblank_start-1.
12023 * On gen2 the scanline counter starts counting from 1 instead
12024 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12025 * to keep the value positive), instead of adding one.
12027 * On HSW+ the behaviour of the scanline counter depends on the output
12028 * type. For DP ports it behaves like most other platforms, but on HDMI
12029 * there's an extra 1 line difference. So we need to add two instead of
12030 * one to the value.
12032 * On VLV/CHV DSI the scanline counter would appear to increment
12033 * approx. 1/3 of a scanline before start of vblank. Unfortunately
12034 * that means we can't tell whether we're in vblank or not while
12035 * we're on that particular line. We must still set scanline_offset
12036 * to 1 so that the vblank timestamps come out correct when we query
12037 * the scanline counter from within the vblank interrupt handler.
12038 * However if queried just before the start of vblank we'll get an
12039 * answer that's slightly in the future.
12041 if (IS_GEN2(dev_priv)) {
12042 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12045 vtotal = adjusted_mode->crtc_vtotal;
12046 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12049 crtc->scanline_offset = vtotal - 1;
12050 } else if (HAS_DDI(dev_priv) &&
12051 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12052 crtc->scanline_offset = 2;
12054 crtc->scanline_offset = 1;
12057 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12059 struct drm_device *dev = state->dev;
12060 struct drm_i915_private *dev_priv = to_i915(dev);
12061 struct drm_crtc *crtc;
12062 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12065 if (!dev_priv->display.crtc_compute_clock)
12068 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12070 struct intel_shared_dpll *old_dpll =
12071 to_intel_crtc_state(old_crtc_state)->shared_dpll;
12073 if (!needs_modeset(new_crtc_state))
12076 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12081 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12086 * This implements the workaround described in the "notes" section of the mode
12087 * set sequence documentation. When going from no pipes or single pipe to
12088 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12089 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12091 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12093 struct drm_crtc_state *crtc_state;
12094 struct intel_crtc *intel_crtc;
12095 struct drm_crtc *crtc;
12096 struct intel_crtc_state *first_crtc_state = NULL;
12097 struct intel_crtc_state *other_crtc_state = NULL;
12098 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12101 /* look at all crtc's that are going to be enabled in during modeset */
12102 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12103 intel_crtc = to_intel_crtc(crtc);
12105 if (!crtc_state->active || !needs_modeset(crtc_state))
12108 if (first_crtc_state) {
12109 other_crtc_state = to_intel_crtc_state(crtc_state);
12112 first_crtc_state = to_intel_crtc_state(crtc_state);
12113 first_pipe = intel_crtc->pipe;
12117 /* No workaround needed? */
12118 if (!first_crtc_state)
12121 /* w/a possibly needed, check how many crtc's are already enabled. */
12122 for_each_intel_crtc(state->dev, intel_crtc) {
12123 struct intel_crtc_state *pipe_config;
12125 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12126 if (IS_ERR(pipe_config))
12127 return PTR_ERR(pipe_config);
12129 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12131 if (!pipe_config->base.active ||
12132 needs_modeset(&pipe_config->base))
12135 /* 2 or more enabled crtcs means no need for w/a */
12136 if (enabled_pipe != INVALID_PIPE)
12139 enabled_pipe = intel_crtc->pipe;
12142 if (enabled_pipe != INVALID_PIPE)
12143 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12144 else if (other_crtc_state)
12145 other_crtc_state->hsw_workaround_pipe = first_pipe;
12150 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12152 struct drm_crtc *crtc;
12154 /* Add all pipes to the state */
12155 for_each_crtc(state->dev, crtc) {
12156 struct drm_crtc_state *crtc_state;
12158 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12159 if (IS_ERR(crtc_state))
12160 return PTR_ERR(crtc_state);
12166 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12168 struct drm_crtc *crtc;
12171 * Add all pipes to the state, and force
12172 * a modeset on all the active ones.
12174 for_each_crtc(state->dev, crtc) {
12175 struct drm_crtc_state *crtc_state;
12178 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12179 if (IS_ERR(crtc_state))
12180 return PTR_ERR(crtc_state);
12182 if (!crtc_state->active || needs_modeset(crtc_state))
12185 crtc_state->mode_changed = true;
12187 ret = drm_atomic_add_affected_connectors(state, crtc);
12191 ret = drm_atomic_add_affected_planes(state, crtc);
12199 static int intel_modeset_checks(struct drm_atomic_state *state)
12201 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12202 struct drm_i915_private *dev_priv = to_i915(state->dev);
12203 struct drm_crtc *crtc;
12204 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12207 if (!check_digital_port_conflicts(state)) {
12208 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12212 intel_state->modeset = true;
12213 intel_state->active_crtcs = dev_priv->active_crtcs;
12214 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12215 intel_state->cdclk.actual = dev_priv->cdclk.actual;
12217 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12218 if (new_crtc_state->active)
12219 intel_state->active_crtcs |= 1 << i;
12221 intel_state->active_crtcs &= ~(1 << i);
12223 if (old_crtc_state->active != new_crtc_state->active)
12224 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12228 * See if the config requires any additional preparation, e.g.
12229 * to adjust global state with pipes off. We need to do this
12230 * here so we can get the modeset_pipe updated config for the new
12231 * mode set on this crtc. For other crtcs we need to use the
12232 * adjusted_mode bits in the crtc directly.
12234 if (dev_priv->display.modeset_calc_cdclk) {
12235 ret = dev_priv->display.modeset_calc_cdclk(state);
12240 * Writes to dev_priv->cdclk.logical must protected by
12241 * holding all the crtc locks, even if we don't end up
12242 * touching the hardware
12244 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12245 &intel_state->cdclk.logical)) {
12246 ret = intel_lock_all_pipes(state);
12251 /* All pipes must be switched off while we change the cdclk. */
12252 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12253 &intel_state->cdclk.actual)) {
12254 ret = intel_modeset_all_pipes(state);
12259 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12260 intel_state->cdclk.logical.cdclk,
12261 intel_state->cdclk.actual.cdclk);
12262 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12263 intel_state->cdclk.logical.voltage_level,
12264 intel_state->cdclk.actual.voltage_level);
12266 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12269 intel_modeset_clear_plls(state);
12271 if (IS_HASWELL(dev_priv))
12272 return haswell_mode_set_planes_workaround(state);
12278 * Handle calculation of various watermark data at the end of the atomic check
12279 * phase. The code here should be run after the per-crtc and per-plane 'check'
12280 * handlers to ensure that all derived state has been updated.
12282 static int calc_watermark_data(struct drm_atomic_state *state)
12284 struct drm_device *dev = state->dev;
12285 struct drm_i915_private *dev_priv = to_i915(dev);
12287 /* Is there platform-specific watermark information to calculate? */
12288 if (dev_priv->display.compute_global_watermarks)
12289 return dev_priv->display.compute_global_watermarks(state);
12295 * intel_atomic_check - validate state object
12297 * @state: state to validate
12299 static int intel_atomic_check(struct drm_device *dev,
12300 struct drm_atomic_state *state)
12302 struct drm_i915_private *dev_priv = to_i915(dev);
12303 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12304 struct drm_crtc *crtc;
12305 struct drm_crtc_state *old_crtc_state, *crtc_state;
12307 bool any_ms = false;
12309 /* Catch I915_MODE_FLAG_INHERITED */
12310 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12312 if (crtc_state->mode.private_flags !=
12313 old_crtc_state->mode.private_flags)
12314 crtc_state->mode_changed = true;
12317 ret = drm_atomic_helper_check_modeset(dev, state);
12321 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12322 struct intel_crtc_state *pipe_config =
12323 to_intel_crtc_state(crtc_state);
12325 if (!needs_modeset(crtc_state))
12328 if (!crtc_state->enable) {
12333 ret = intel_modeset_pipe_config(crtc, pipe_config);
12335 intel_dump_pipe_config(to_intel_crtc(crtc),
12336 pipe_config, "[failed]");
12340 if (i915_modparams.fastboot &&
12341 intel_pipe_config_compare(dev_priv,
12342 to_intel_crtc_state(old_crtc_state),
12343 pipe_config, true)) {
12344 crtc_state->mode_changed = false;
12345 pipe_config->update_pipe = true;
12348 if (needs_modeset(crtc_state))
12351 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12352 needs_modeset(crtc_state) ?
12353 "[modeset]" : "[fastset]");
12357 ret = intel_modeset_checks(state);
12362 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12365 ret = drm_atomic_helper_check_planes(dev, state);
12369 intel_fbc_choose_crtc(dev_priv, intel_state);
12370 return calc_watermark_data(state);
12373 static int intel_atomic_prepare_commit(struct drm_device *dev,
12374 struct drm_atomic_state *state)
12376 return drm_atomic_helper_prepare_planes(dev, state);
12379 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12381 struct drm_device *dev = crtc->base.dev;
12383 if (!dev->max_vblank_count)
12384 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12386 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12389 static void intel_update_crtc(struct drm_crtc *crtc,
12390 struct drm_atomic_state *state,
12391 struct drm_crtc_state *old_crtc_state,
12392 struct drm_crtc_state *new_crtc_state)
12394 struct drm_device *dev = crtc->dev;
12395 struct drm_i915_private *dev_priv = to_i915(dev);
12396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12397 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12398 bool modeset = needs_modeset(new_crtc_state);
12399 struct intel_plane_state *new_plane_state =
12400 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12401 to_intel_plane(crtc->primary));
12404 update_scanline_offset(intel_crtc);
12405 dev_priv->display.crtc_enable(pipe_config, state);
12407 /* vblanks work again, re-enable pipe CRC. */
12408 intel_crtc_enable_pipe_crc(intel_crtc);
12410 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12414 if (new_plane_state)
12415 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12417 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12420 static void intel_update_crtcs(struct drm_atomic_state *state)
12422 struct drm_crtc *crtc;
12423 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12426 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12427 if (!new_crtc_state->active)
12430 intel_update_crtc(crtc, state, old_crtc_state,
12435 static void skl_update_crtcs(struct drm_atomic_state *state)
12437 struct drm_i915_private *dev_priv = to_i915(state->dev);
12438 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12439 struct drm_crtc *crtc;
12440 struct intel_crtc *intel_crtc;
12441 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12442 struct intel_crtc_state *cstate;
12443 unsigned int updated = 0;
12447 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12448 u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12450 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12452 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12453 /* ignore allocations for crtc's that have been turned off. */
12454 if (new_crtc_state->active)
12455 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12457 /* If 2nd DBuf slice required, enable it here */
12458 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12459 icl_dbuf_slices_update(dev_priv, required_slices);
12462 * Whenever the number of active pipes changes, we need to make sure we
12463 * update the pipes in the right order so that their ddb allocations
12464 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12465 * cause pipe underruns and other bad stuff.
12470 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12471 bool vbl_wait = false;
12472 unsigned int cmask = drm_crtc_mask(crtc);
12474 intel_crtc = to_intel_crtc(crtc);
12475 cstate = to_intel_crtc_state(new_crtc_state);
12476 pipe = intel_crtc->pipe;
12478 if (updated & cmask || !cstate->base.active)
12481 if (skl_ddb_allocation_overlaps(dev_priv,
12483 &cstate->wm.skl.ddb,
12488 entries[i] = &cstate->wm.skl.ddb;
12491 * If this is an already active pipe, it's DDB changed,
12492 * and this isn't the last pipe that needs updating
12493 * then we need to wait for a vblank to pass for the
12494 * new ddb allocation to take effect.
12496 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12497 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12498 !new_crtc_state->active_changed &&
12499 intel_state->wm_results.dirty_pipes != updated)
12502 intel_update_crtc(crtc, state, old_crtc_state,
12506 intel_wait_for_vblank(dev_priv, pipe);
12510 } while (progress);
12512 /* If 2nd DBuf slice is no more required disable it */
12513 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12514 icl_dbuf_slices_update(dev_priv, required_slices);
12517 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12519 struct intel_atomic_state *state, *next;
12520 struct llist_node *freed;
12522 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12523 llist_for_each_entry_safe(state, next, freed, freed)
12524 drm_atomic_state_put(&state->base);
12527 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12529 struct drm_i915_private *dev_priv =
12530 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12532 intel_atomic_helper_free_state(dev_priv);
12535 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12537 struct wait_queue_entry wait_fence, wait_reset;
12538 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12540 init_wait_entry(&wait_fence, 0);
12541 init_wait_entry(&wait_reset, 0);
12543 prepare_to_wait(&intel_state->commit_ready.wait,
12544 &wait_fence, TASK_UNINTERRUPTIBLE);
12545 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12546 &wait_reset, TASK_UNINTERRUPTIBLE);
12549 if (i915_sw_fence_done(&intel_state->commit_ready)
12550 || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12555 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12556 finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12559 static void intel_atomic_cleanup_work(struct work_struct *work)
12561 struct drm_atomic_state *state =
12562 container_of(work, struct drm_atomic_state, commit_work);
12563 struct drm_i915_private *i915 = to_i915(state->dev);
12565 drm_atomic_helper_cleanup_planes(&i915->drm, state);
12566 drm_atomic_helper_commit_cleanup_done(state);
12567 drm_atomic_state_put(state);
12569 intel_atomic_helper_free_state(i915);
12572 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12574 struct drm_device *dev = state->dev;
12575 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12576 struct drm_i915_private *dev_priv = to_i915(dev);
12577 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12578 struct drm_crtc *crtc;
12579 struct intel_crtc_state *intel_cstate;
12580 u64 put_domains[I915_MAX_PIPES] = {};
12583 intel_atomic_commit_fence_wait(intel_state);
12585 drm_atomic_helper_wait_for_dependencies(state);
12587 if (intel_state->modeset)
12588 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12590 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12593 if (needs_modeset(new_crtc_state) ||
12594 to_intel_crtc_state(new_crtc_state)->update_pipe) {
12596 put_domains[to_intel_crtc(crtc)->pipe] =
12597 modeset_get_crtc_power_domains(crtc,
12598 to_intel_crtc_state(new_crtc_state));
12601 if (!needs_modeset(new_crtc_state))
12604 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12605 to_intel_crtc_state(new_crtc_state));
12607 if (old_crtc_state->active) {
12608 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12611 * We need to disable pipe CRC before disabling the pipe,
12612 * or we race against vblank off.
12614 intel_crtc_disable_pipe_crc(intel_crtc);
12616 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12617 intel_crtc->active = false;
12618 intel_fbc_disable(intel_crtc);
12619 intel_disable_shared_dpll(intel_crtc);
12622 * Underruns don't always raise
12623 * interrupts, so check manually.
12625 intel_check_cpu_fifo_underruns(dev_priv);
12626 intel_check_pch_fifo_underruns(dev_priv);
12628 if (!new_crtc_state->active) {
12630 * Make sure we don't call initial_watermarks
12631 * for ILK-style watermark updates.
12633 * No clue what this is supposed to achieve.
12635 if (INTEL_GEN(dev_priv) >= 9)
12636 dev_priv->display.initial_watermarks(intel_state,
12637 to_intel_crtc_state(new_crtc_state));
12642 /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12643 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12644 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12646 if (intel_state->modeset) {
12647 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12649 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12652 * SKL workaround: bspec recommends we disable the SAGV when we
12653 * have more then one pipe enabled
12655 if (!intel_can_enable_sagv(state))
12656 intel_disable_sagv(dev_priv);
12658 intel_modeset_verify_disabled(dev, state);
12661 /* Complete the events for pipes that have now been disabled */
12662 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12663 bool modeset = needs_modeset(new_crtc_state);
12665 /* Complete events for now disable pipes here. */
12666 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12667 spin_lock_irq(&dev->event_lock);
12668 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12669 spin_unlock_irq(&dev->event_lock);
12671 new_crtc_state->event = NULL;
12675 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12676 dev_priv->display.update_crtcs(state);
12678 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12679 * already, but still need the state for the delayed optimization. To
12681 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12682 * - schedule that vblank worker _before_ calling hw_done
12683 * - at the start of commit_tail, cancel it _synchrously
12684 * - switch over to the vblank wait helper in the core after that since
12685 * we don't need out special handling any more.
12687 drm_atomic_helper_wait_for_flip_done(dev, state);
12690 * Now that the vblank has passed, we can go ahead and program the
12691 * optimal watermarks on platforms that need two-step watermark
12694 * TODO: Move this (and other cleanup) to an async worker eventually.
12696 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12697 intel_cstate = to_intel_crtc_state(new_crtc_state);
12699 if (dev_priv->display.optimize_watermarks)
12700 dev_priv->display.optimize_watermarks(intel_state,
12704 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12705 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12707 if (put_domains[i])
12708 modeset_put_power_domains(dev_priv, put_domains[i]);
12710 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12713 if (intel_state->modeset)
12714 intel_verify_planes(intel_state);
12716 if (intel_state->modeset && intel_can_enable_sagv(state))
12717 intel_enable_sagv(dev_priv);
12719 drm_atomic_helper_commit_hw_done(state);
12721 if (intel_state->modeset) {
12722 /* As one of the primary mmio accessors, KMS has a high
12723 * likelihood of triggering bugs in unclaimed access. After we
12724 * finish modesetting, see if an error has been flagged, and if
12725 * so enable debugging for the next modeset - and hope we catch
12728 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12729 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12733 * Defer the cleanup of the old state to a separate worker to not
12734 * impede the current task (userspace for blocking modesets) that
12735 * are executed inline. For out-of-line asynchronous modesets/flips,
12736 * deferring to a new worker seems overkill, but we would place a
12737 * schedule point (cond_resched()) here anyway to keep latencies
12740 INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
12741 schedule_work(&state->commit_work);
12744 static void intel_atomic_commit_work(struct work_struct *work)
12746 struct drm_atomic_state *state =
12747 container_of(work, struct drm_atomic_state, commit_work);
12749 intel_atomic_commit_tail(state);
12752 static int __i915_sw_fence_call
12753 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12754 enum i915_sw_fence_notify notify)
12756 struct intel_atomic_state *state =
12757 container_of(fence, struct intel_atomic_state, commit_ready);
12760 case FENCE_COMPLETE:
12761 /* we do blocking waits in the worker, nothing to do here */
12765 struct intel_atomic_helper *helper =
12766 &to_i915(state->base.dev)->atomic_helper;
12768 if (llist_add(&state->freed, &helper->free_list))
12769 schedule_work(&helper->free_work);
12774 return NOTIFY_DONE;
12777 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12779 struct drm_plane_state *old_plane_state, *new_plane_state;
12780 struct drm_plane *plane;
12783 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12784 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12785 intel_fb_obj(new_plane_state->fb),
12786 to_intel_plane(plane)->frontbuffer_bit);
12790 * intel_atomic_commit - commit validated state object
12792 * @state: the top-level driver state object
12793 * @nonblock: nonblocking commit
12795 * This function commits a top-level state object that has been validated
12796 * with drm_atomic_helper_check().
12799 * Zero for success or -errno.
12801 static int intel_atomic_commit(struct drm_device *dev,
12802 struct drm_atomic_state *state,
12805 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12806 struct drm_i915_private *dev_priv = to_i915(dev);
12809 drm_atomic_state_get(state);
12810 i915_sw_fence_init(&intel_state->commit_ready,
12811 intel_atomic_commit_ready);
12814 * The intel_legacy_cursor_update() fast path takes care
12815 * of avoiding the vblank waits for simple cursor
12816 * movement and flips. For cursor on/off and size changes,
12817 * we want to perform the vblank waits so that watermark
12818 * updates happen during the correct frames. Gen9+ have
12819 * double buffered watermarks and so shouldn't need this.
12821 * Unset state->legacy_cursor_update before the call to
12822 * drm_atomic_helper_setup_commit() because otherwise
12823 * drm_atomic_helper_wait_for_flip_done() is a noop and
12824 * we get FIFO underruns because we didn't wait
12827 * FIXME doing watermarks and fb cleanup from a vblank worker
12828 * (assuming we had any) would solve these problems.
12830 if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12831 struct intel_crtc_state *new_crtc_state;
12832 struct intel_crtc *crtc;
12835 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12836 if (new_crtc_state->wm.need_postvbl_update ||
12837 new_crtc_state->update_wm_post)
12838 state->legacy_cursor_update = false;
12841 ret = intel_atomic_prepare_commit(dev, state);
12843 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12844 i915_sw_fence_commit(&intel_state->commit_ready);
12848 ret = drm_atomic_helper_setup_commit(state, nonblock);
12850 ret = drm_atomic_helper_swap_state(state, true);
12853 i915_sw_fence_commit(&intel_state->commit_ready);
12855 drm_atomic_helper_cleanup_planes(dev, state);
12858 dev_priv->wm.distrust_bios_wm = false;
12859 intel_shared_dpll_swap_state(state);
12860 intel_atomic_track_fbs(state);
12862 if (intel_state->modeset) {
12863 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12864 sizeof(intel_state->min_cdclk));
12865 memcpy(dev_priv->min_voltage_level,
12866 intel_state->min_voltage_level,
12867 sizeof(intel_state->min_voltage_level));
12868 dev_priv->active_crtcs = intel_state->active_crtcs;
12869 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12870 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12873 drm_atomic_state_get(state);
12874 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12876 i915_sw_fence_commit(&intel_state->commit_ready);
12877 if (nonblock && intel_state->modeset) {
12878 queue_work(dev_priv->modeset_wq, &state->commit_work);
12879 } else if (nonblock) {
12880 queue_work(system_unbound_wq, &state->commit_work);
12882 if (intel_state->modeset)
12883 flush_workqueue(dev_priv->modeset_wq);
12884 intel_atomic_commit_tail(state);
12890 static const struct drm_crtc_funcs intel_crtc_funcs = {
12891 .gamma_set = drm_atomic_helper_legacy_gamma_set,
12892 .set_config = drm_atomic_helper_set_config,
12893 .destroy = intel_crtc_destroy,
12894 .page_flip = drm_atomic_helper_page_flip,
12895 .atomic_duplicate_state = intel_crtc_duplicate_state,
12896 .atomic_destroy_state = intel_crtc_destroy_state,
12897 .set_crc_source = intel_crtc_set_crc_source,
12900 struct wait_rps_boost {
12901 struct wait_queue_entry wait;
12903 struct drm_crtc *crtc;
12904 struct i915_request *request;
12907 static int do_rps_boost(struct wait_queue_entry *_wait,
12908 unsigned mode, int sync, void *key)
12910 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12911 struct i915_request *rq = wait->request;
12914 * If we missed the vblank, but the request is already running it
12915 * is reasonable to assume that it will complete before the next
12916 * vblank without our intervention, so leave RPS alone.
12918 if (!i915_request_started(rq))
12919 gen6_rps_boost(rq, NULL);
12920 i915_request_put(rq);
12922 drm_crtc_vblank_put(wait->crtc);
12924 list_del(&wait->wait.entry);
12929 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12930 struct dma_fence *fence)
12932 struct wait_rps_boost *wait;
12934 if (!dma_fence_is_i915(fence))
12937 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12940 if (drm_crtc_vblank_get(crtc))
12943 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12945 drm_crtc_vblank_put(crtc);
12949 wait->request = to_request(dma_fence_get(fence));
12952 wait->wait.func = do_rps_boost;
12953 wait->wait.flags = 0;
12955 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12958 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12960 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12961 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12962 struct drm_framebuffer *fb = plane_state->base.fb;
12963 struct i915_vma *vma;
12965 if (plane->id == PLANE_CURSOR &&
12966 INTEL_INFO(dev_priv)->cursor_needs_physical) {
12967 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12968 const int align = intel_cursor_alignment(dev_priv);
12970 return i915_gem_object_attach_phys(obj, align);
12973 vma = intel_pin_and_fence_fb_obj(fb,
12974 plane_state->base.rotation,
12975 intel_plane_uses_fence(plane_state),
12976 &plane_state->flags);
12978 return PTR_ERR(vma);
12980 plane_state->vma = vma;
12985 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12987 struct i915_vma *vma;
12989 vma = fetch_and_zero(&old_plane_state->vma);
12991 intel_unpin_fb_vma(vma, old_plane_state->flags);
12994 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
12996 struct i915_sched_attr attr = {
12997 .priority = I915_PRIORITY_DISPLAY,
13000 i915_gem_object_wait_priority(obj, 0, &attr);
13004 * intel_prepare_plane_fb - Prepare fb for usage on plane
13005 * @plane: drm plane to prepare for
13006 * @new_state: the plane state being prepared
13008 * Prepares a framebuffer for usage on a display plane. Generally this
13009 * involves pinning the underlying object and updating the frontbuffer tracking
13010 * bits. Some older platforms need special physical address handling for
13013 * Must be called with struct_mutex held.
13015 * Returns 0 on success, negative error code on failure.
13018 intel_prepare_plane_fb(struct drm_plane *plane,
13019 struct drm_plane_state *new_state)
13021 struct intel_atomic_state *intel_state =
13022 to_intel_atomic_state(new_state->state);
13023 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13024 struct drm_framebuffer *fb = new_state->fb;
13025 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13026 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13030 struct drm_crtc_state *crtc_state =
13031 drm_atomic_get_new_crtc_state(new_state->state,
13032 plane->state->crtc);
13034 /* Big Hammer, we also need to ensure that any pending
13035 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13036 * current scanout is retired before unpinning the old
13037 * framebuffer. Note that we rely on userspace rendering
13038 * into the buffer attached to the pipe they are waiting
13039 * on. If not, userspace generates a GPU hang with IPEHR
13040 * point to the MI_WAIT_FOR_EVENT.
13042 * This should only fail upon a hung GPU, in which case we
13043 * can safely continue.
13045 if (needs_modeset(crtc_state)) {
13046 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13047 old_obj->resv, NULL,
13055 if (new_state->fence) { /* explicit fencing */
13056 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13058 I915_FENCE_TIMEOUT,
13067 ret = i915_gem_object_pin_pages(obj);
13071 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13073 i915_gem_object_unpin_pages(obj);
13077 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
13079 fb_obj_bump_render_priority(obj);
13081 mutex_unlock(&dev_priv->drm.struct_mutex);
13082 i915_gem_object_unpin_pages(obj);
13086 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13088 if (!new_state->fence) { /* implicit fencing */
13089 struct dma_fence *fence;
13091 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13093 false, I915_FENCE_TIMEOUT,
13098 fence = reservation_object_get_excl_rcu(obj->resv);
13100 add_rps_boost_after_vblank(new_state->crtc, fence);
13101 dma_fence_put(fence);
13104 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
13108 * We declare pageflips to be interactive and so merit a small bias
13109 * towards upclocking to deliver the frame on time. By only changing
13110 * the RPS thresholds to sample more regularly and aim for higher
13111 * clocks we can hopefully deliver low power workloads (like kodi)
13112 * that are not quite steady state without resorting to forcing
13113 * maximum clocks following a vblank miss (see do_rps_boost()).
13115 if (!intel_state->rps_interactive) {
13116 intel_rps_mark_interactive(dev_priv, true);
13117 intel_state->rps_interactive = true;
13124 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13125 * @plane: drm plane to clean up for
13126 * @old_state: the state from the previous modeset
13128 * Cleans up a framebuffer that has just been removed from a plane.
13130 * Must be called with struct_mutex held.
13133 intel_cleanup_plane_fb(struct drm_plane *plane,
13134 struct drm_plane_state *old_state)
13136 struct intel_atomic_state *intel_state =
13137 to_intel_atomic_state(old_state->state);
13138 struct drm_i915_private *dev_priv = to_i915(plane->dev);
13140 if (intel_state->rps_interactive) {
13141 intel_rps_mark_interactive(dev_priv, false);
13142 intel_state->rps_interactive = false;
13145 /* Should only be called after a successful intel_prepare_plane_fb()! */
13146 mutex_lock(&dev_priv->drm.struct_mutex);
13147 intel_plane_unpin_fb(to_intel_plane_state(old_state));
13148 mutex_unlock(&dev_priv->drm.struct_mutex);
13152 skl_max_scale(struct intel_crtc *intel_crtc,
13153 struct intel_crtc_state *crtc_state,
13154 uint32_t pixel_format)
13156 struct drm_i915_private *dev_priv;
13157 int max_scale, mult;
13158 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
13160 if (!intel_crtc || !crtc_state->base.enable)
13161 return DRM_PLANE_HELPER_NO_SCALING;
13163 dev_priv = to_i915(intel_crtc->base.dev);
13165 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13166 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13168 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
13171 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13172 return DRM_PLANE_HELPER_NO_SCALING;
13175 * skl max scale is lower of:
13176 * close to 3 but not 3, -1 is for that purpose
13180 mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
13181 tmpclk1 = (1 << 16) * mult - 1;
13182 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
13183 max_scale = min(tmpclk1, tmpclk2);
13189 intel_check_primary_plane(struct intel_plane *plane,
13190 struct intel_crtc_state *crtc_state,
13191 struct intel_plane_state *state)
13193 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
13194 struct drm_crtc *crtc = state->base.crtc;
13195 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13196 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13197 bool can_position = false;
13199 uint32_t pixel_format = 0;
13201 if (INTEL_GEN(dev_priv) >= 9) {
13202 /* use scaler when colorkey is not required */
13203 if (!state->ckey.flags) {
13205 if (state->base.fb)
13206 pixel_format = state->base.fb->format->format;
13207 max_scale = skl_max_scale(to_intel_crtc(crtc),
13208 crtc_state, pixel_format);
13210 can_position = true;
13213 ret = drm_atomic_helper_check_plane_state(&state->base,
13215 min_scale, max_scale,
13216 can_position, true);
13220 if (!state->base.fb)
13223 if (INTEL_GEN(dev_priv) >= 9) {
13224 ret = skl_check_plane_surface(crtc_state, state);
13228 state->ctl = skl_plane_ctl(crtc_state, state);
13230 ret = i9xx_check_plane_surface(state);
13234 state->ctl = i9xx_plane_ctl(crtc_state, state);
13237 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13238 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13243 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13244 struct drm_crtc_state *old_crtc_state)
13246 struct drm_device *dev = crtc->dev;
13247 struct drm_i915_private *dev_priv = to_i915(dev);
13248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13249 struct intel_crtc_state *old_intel_cstate =
13250 to_intel_crtc_state(old_crtc_state);
13251 struct intel_atomic_state *old_intel_state =
13252 to_intel_atomic_state(old_crtc_state->state);
13253 struct intel_crtc_state *intel_cstate =
13254 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13255 bool modeset = needs_modeset(&intel_cstate->base);
13258 (intel_cstate->base.color_mgmt_changed ||
13259 intel_cstate->update_pipe)) {
13260 intel_color_set_csc(&intel_cstate->base);
13261 intel_color_load_luts(&intel_cstate->base);
13264 /* Perform vblank evasion around commit operation */
13265 intel_pipe_update_start(intel_cstate);
13270 if (intel_cstate->update_pipe)
13271 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13272 else if (INTEL_GEN(dev_priv) >= 9)
13273 skl_detach_scalers(intel_crtc);
13276 if (dev_priv->display.atomic_update_watermarks)
13277 dev_priv->display.atomic_update_watermarks(old_intel_state,
13281 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13282 struct intel_crtc_state *crtc_state)
13284 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13286 if (!IS_GEN2(dev_priv))
13287 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13289 if (crtc_state->has_pch_encoder) {
13290 enum pipe pch_transcoder =
13291 intel_crtc_pch_transcoder(crtc);
13293 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13297 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13298 struct drm_crtc_state *old_crtc_state)
13300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13301 struct intel_atomic_state *old_intel_state =
13302 to_intel_atomic_state(old_crtc_state->state);
13303 struct intel_crtc_state *new_crtc_state =
13304 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13306 intel_pipe_update_end(new_crtc_state);
13308 if (new_crtc_state->update_pipe &&
13309 !needs_modeset(&new_crtc_state->base) &&
13310 old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13311 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13315 * intel_plane_destroy - destroy a plane
13316 * @plane: plane to destroy
13318 * Common destruction function for all types of planes (primary, cursor,
13321 void intel_plane_destroy(struct drm_plane *plane)
13323 drm_plane_cleanup(plane);
13324 kfree(to_intel_plane(plane));
13327 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
13328 u32 format, u64 modifier)
13330 switch (modifier) {
13331 case DRM_FORMAT_MOD_LINEAR:
13332 case I915_FORMAT_MOD_X_TILED:
13339 case DRM_FORMAT_C8:
13340 case DRM_FORMAT_RGB565:
13341 case DRM_FORMAT_XRGB1555:
13342 case DRM_FORMAT_XRGB8888:
13343 return modifier == DRM_FORMAT_MOD_LINEAR ||
13344 modifier == I915_FORMAT_MOD_X_TILED;
13350 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
13351 u32 format, u64 modifier)
13353 switch (modifier) {
13354 case DRM_FORMAT_MOD_LINEAR:
13355 case I915_FORMAT_MOD_X_TILED:
13362 case DRM_FORMAT_C8:
13363 case DRM_FORMAT_RGB565:
13364 case DRM_FORMAT_XRGB8888:
13365 case DRM_FORMAT_XBGR8888:
13366 case DRM_FORMAT_XRGB2101010:
13367 case DRM_FORMAT_XBGR2101010:
13368 return modifier == DRM_FORMAT_MOD_LINEAR ||
13369 modifier == I915_FORMAT_MOD_X_TILED;
13375 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
13376 u32 format, u64 modifier)
13378 struct intel_plane *plane = to_intel_plane(_plane);
13380 switch (modifier) {
13381 case DRM_FORMAT_MOD_LINEAR:
13382 case I915_FORMAT_MOD_X_TILED:
13383 case I915_FORMAT_MOD_Y_TILED:
13384 case I915_FORMAT_MOD_Yf_TILED:
13386 case I915_FORMAT_MOD_Y_TILED_CCS:
13387 case I915_FORMAT_MOD_Yf_TILED_CCS:
13388 if (!plane->has_ccs)
13396 case DRM_FORMAT_XRGB8888:
13397 case DRM_FORMAT_XBGR8888:
13398 case DRM_FORMAT_ARGB8888:
13399 case DRM_FORMAT_ABGR8888:
13400 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13401 modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13404 case DRM_FORMAT_RGB565:
13405 case DRM_FORMAT_XRGB2101010:
13406 case DRM_FORMAT_XBGR2101010:
13407 case DRM_FORMAT_YUYV:
13408 case DRM_FORMAT_YVYU:
13409 case DRM_FORMAT_UYVY:
13410 case DRM_FORMAT_VYUY:
13411 case DRM_FORMAT_NV12:
13412 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13415 case DRM_FORMAT_C8:
13416 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13417 modifier == I915_FORMAT_MOD_X_TILED ||
13418 modifier == I915_FORMAT_MOD_Y_TILED)
13426 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
13427 u32 format, u64 modifier)
13429 return modifier == DRM_FORMAT_MOD_LINEAR &&
13430 format == DRM_FORMAT_ARGB8888;
13433 static struct drm_plane_funcs skl_plane_funcs = {
13434 .update_plane = drm_atomic_helper_update_plane,
13435 .disable_plane = drm_atomic_helper_disable_plane,
13436 .destroy = intel_plane_destroy,
13437 .atomic_get_property = intel_plane_atomic_get_property,
13438 .atomic_set_property = intel_plane_atomic_set_property,
13439 .atomic_duplicate_state = intel_plane_duplicate_state,
13440 .atomic_destroy_state = intel_plane_destroy_state,
13441 .format_mod_supported = skl_plane_format_mod_supported,
13444 static struct drm_plane_funcs i965_plane_funcs = {
13445 .update_plane = drm_atomic_helper_update_plane,
13446 .disable_plane = drm_atomic_helper_disable_plane,
13447 .destroy = intel_plane_destroy,
13448 .atomic_get_property = intel_plane_atomic_get_property,
13449 .atomic_set_property = intel_plane_atomic_set_property,
13450 .atomic_duplicate_state = intel_plane_duplicate_state,
13451 .atomic_destroy_state = intel_plane_destroy_state,
13452 .format_mod_supported = i965_plane_format_mod_supported,
13455 static struct drm_plane_funcs i8xx_plane_funcs = {
13456 .update_plane = drm_atomic_helper_update_plane,
13457 .disable_plane = drm_atomic_helper_disable_plane,
13458 .destroy = intel_plane_destroy,
13459 .atomic_get_property = intel_plane_atomic_get_property,
13460 .atomic_set_property = intel_plane_atomic_set_property,
13461 .atomic_duplicate_state = intel_plane_duplicate_state,
13462 .atomic_destroy_state = intel_plane_destroy_state,
13463 .format_mod_supported = i8xx_plane_format_mod_supported,
13467 intel_legacy_cursor_update(struct drm_plane *plane,
13468 struct drm_crtc *crtc,
13469 struct drm_framebuffer *fb,
13470 int crtc_x, int crtc_y,
13471 unsigned int crtc_w, unsigned int crtc_h,
13472 uint32_t src_x, uint32_t src_y,
13473 uint32_t src_w, uint32_t src_h,
13474 struct drm_modeset_acquire_ctx *ctx)
13476 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13478 struct drm_plane_state *old_plane_state, *new_plane_state;
13479 struct intel_plane *intel_plane = to_intel_plane(plane);
13480 struct drm_framebuffer *old_fb;
13481 struct drm_crtc_state *crtc_state = crtc->state;
13484 * When crtc is inactive or there is a modeset pending,
13485 * wait for it to complete in the slowpath
13487 if (!crtc_state->active || needs_modeset(crtc_state) ||
13488 to_intel_crtc_state(crtc_state)->update_pipe)
13491 old_plane_state = plane->state;
13493 * Don't do an async update if there is an outstanding commit modifying
13494 * the plane. This prevents our async update's changes from getting
13495 * overridden by a previous synchronous update's state.
13497 if (old_plane_state->commit &&
13498 !try_wait_for_completion(&old_plane_state->commit->hw_done))
13502 * If any parameters change that may affect watermarks,
13503 * take the slowpath. Only changing fb or position should be
13506 if (old_plane_state->crtc != crtc ||
13507 old_plane_state->src_w != src_w ||
13508 old_plane_state->src_h != src_h ||
13509 old_plane_state->crtc_w != crtc_w ||
13510 old_plane_state->crtc_h != crtc_h ||
13511 !old_plane_state->fb != !fb)
13514 new_plane_state = intel_plane_duplicate_state(plane);
13515 if (!new_plane_state)
13518 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13520 new_plane_state->src_x = src_x;
13521 new_plane_state->src_y = src_y;
13522 new_plane_state->src_w = src_w;
13523 new_plane_state->src_h = src_h;
13524 new_plane_state->crtc_x = crtc_x;
13525 new_plane_state->crtc_y = crtc_y;
13526 new_plane_state->crtc_w = crtc_w;
13527 new_plane_state->crtc_h = crtc_h;
13529 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13530 to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13531 to_intel_plane_state(plane->state),
13532 to_intel_plane_state(new_plane_state));
13536 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13540 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13544 intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13546 old_fb = old_plane_state->fb;
13547 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13548 intel_plane->frontbuffer_bit);
13550 /* Swap plane state */
13551 plane->state = new_plane_state;
13553 if (plane->state->visible) {
13554 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13555 intel_plane->update_plane(intel_plane,
13556 to_intel_crtc_state(crtc->state),
13557 to_intel_plane_state(plane->state));
13559 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13560 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13563 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13566 mutex_unlock(&dev_priv->drm.struct_mutex);
13569 intel_plane_destroy_state(plane, new_plane_state);
13571 intel_plane_destroy_state(plane, old_plane_state);
13575 return drm_atomic_helper_update_plane(plane, crtc, fb,
13576 crtc_x, crtc_y, crtc_w, crtc_h,
13577 src_x, src_y, src_w, src_h, ctx);
13580 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13581 .update_plane = intel_legacy_cursor_update,
13582 .disable_plane = drm_atomic_helper_disable_plane,
13583 .destroy = intel_plane_destroy,
13584 .atomic_get_property = intel_plane_atomic_get_property,
13585 .atomic_set_property = intel_plane_atomic_set_property,
13586 .atomic_duplicate_state = intel_plane_duplicate_state,
13587 .atomic_destroy_state = intel_plane_destroy_state,
13588 .format_mod_supported = intel_cursor_format_mod_supported,
13591 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13592 enum i9xx_plane_id i9xx_plane)
13594 if (!HAS_FBC(dev_priv))
13597 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13598 return i9xx_plane == PLANE_A; /* tied to pipe A */
13599 else if (IS_IVYBRIDGE(dev_priv))
13600 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13601 i9xx_plane == PLANE_C;
13602 else if (INTEL_GEN(dev_priv) >= 4)
13603 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13605 return i9xx_plane == PLANE_A;
13608 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13609 enum pipe pipe, enum plane_id plane_id)
13611 if (!HAS_FBC(dev_priv))
13614 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13617 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
13618 enum pipe pipe, enum plane_id plane_id)
13620 if (plane_id == PLANE_PRIMARY) {
13621 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13623 else if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
13624 !IS_GEMINILAKE(dev_priv))
13626 } else if (plane_id >= PLANE_SPRITE0) {
13627 if (plane_id == PLANE_CURSOR)
13629 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
13630 if (plane_id != PLANE_SPRITE0)
13633 if (plane_id != PLANE_SPRITE0 || pipe == PIPE_C ||
13634 IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
13641 static struct intel_plane *
13642 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13644 struct intel_plane *primary = NULL;
13645 struct intel_plane_state *state = NULL;
13646 const struct drm_plane_funcs *plane_funcs;
13647 const uint32_t *intel_primary_formats;
13648 unsigned int supported_rotations;
13649 unsigned int num_formats;
13650 const uint64_t *modifiers;
13653 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13659 state = intel_create_plane_state(&primary->base);
13665 primary->base.state = &state->base;
13667 primary->can_scale = false;
13668 primary->max_downscale = 1;
13669 if (INTEL_GEN(dev_priv) >= 9) {
13670 primary->can_scale = true;
13671 state->scaler_id = -1;
13673 primary->pipe = pipe;
13675 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13676 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13678 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13679 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13681 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13682 primary->id = PLANE_PRIMARY;
13683 primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13685 if (INTEL_GEN(dev_priv) >= 9)
13686 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13690 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13691 primary->i9xx_plane);
13693 if (primary->has_fbc) {
13694 struct intel_fbc *fbc = &dev_priv->fbc;
13696 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13699 primary->check_plane = intel_check_primary_plane;
13701 if (INTEL_GEN(dev_priv) >= 9) {
13702 primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
13705 if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
13706 intel_primary_formats = skl_pri_planar_formats;
13707 num_formats = ARRAY_SIZE(skl_pri_planar_formats);
13709 intel_primary_formats = skl_primary_formats;
13710 num_formats = ARRAY_SIZE(skl_primary_formats);
13713 if (primary->has_ccs)
13714 modifiers = skl_format_modifiers_ccs;
13716 modifiers = skl_format_modifiers_noccs;
13718 primary->update_plane = skl_update_plane;
13719 primary->disable_plane = skl_disable_plane;
13720 primary->get_hw_state = skl_plane_get_hw_state;
13722 plane_funcs = &skl_plane_funcs;
13723 } else if (INTEL_GEN(dev_priv) >= 4) {
13724 intel_primary_formats = i965_primary_formats;
13725 num_formats = ARRAY_SIZE(i965_primary_formats);
13726 modifiers = i9xx_format_modifiers;
13728 primary->update_plane = i9xx_update_plane;
13729 primary->disable_plane = i9xx_disable_plane;
13730 primary->get_hw_state = i9xx_plane_get_hw_state;
13732 plane_funcs = &i965_plane_funcs;
13734 intel_primary_formats = i8xx_primary_formats;
13735 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13736 modifiers = i9xx_format_modifiers;
13738 primary->update_plane = i9xx_update_plane;
13739 primary->disable_plane = i9xx_disable_plane;
13740 primary->get_hw_state = i9xx_plane_get_hw_state;
13742 plane_funcs = &i8xx_plane_funcs;
13745 if (INTEL_GEN(dev_priv) >= 9)
13746 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13748 intel_primary_formats, num_formats,
13750 DRM_PLANE_TYPE_PRIMARY,
13751 "plane 1%c", pipe_name(pipe));
13752 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13753 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13755 intel_primary_formats, num_formats,
13757 DRM_PLANE_TYPE_PRIMARY,
13758 "primary %c", pipe_name(pipe));
13760 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13762 intel_primary_formats, num_formats,
13764 DRM_PLANE_TYPE_PRIMARY,
13766 plane_name(primary->i9xx_plane));
13770 if (INTEL_GEN(dev_priv) >= 10) {
13771 supported_rotations =
13772 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13773 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13774 DRM_MODE_REFLECT_X;
13775 } else if (INTEL_GEN(dev_priv) >= 9) {
13776 supported_rotations =
13777 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13778 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13779 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13780 supported_rotations =
13781 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13782 DRM_MODE_REFLECT_X;
13783 } else if (INTEL_GEN(dev_priv) >= 4) {
13784 supported_rotations =
13785 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13787 supported_rotations = DRM_MODE_ROTATE_0;
13790 if (INTEL_GEN(dev_priv) >= 4)
13791 drm_plane_create_rotation_property(&primary->base,
13793 supported_rotations);
13795 if (INTEL_GEN(dev_priv) >= 9)
13796 drm_plane_create_color_properties(&primary->base,
13797 BIT(DRM_COLOR_YCBCR_BT601) |
13798 BIT(DRM_COLOR_YCBCR_BT709),
13799 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13800 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13801 DRM_COLOR_YCBCR_BT709,
13802 DRM_COLOR_YCBCR_LIMITED_RANGE);
13804 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13812 return ERR_PTR(ret);
13815 static struct intel_plane *
13816 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13819 struct intel_plane *cursor = NULL;
13820 struct intel_plane_state *state = NULL;
13823 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13829 state = intel_create_plane_state(&cursor->base);
13835 cursor->base.state = &state->base;
13837 cursor->can_scale = false;
13838 cursor->max_downscale = 1;
13839 cursor->pipe = pipe;
13840 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13841 cursor->id = PLANE_CURSOR;
13842 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13844 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13845 cursor->update_plane = i845_update_cursor;
13846 cursor->disable_plane = i845_disable_cursor;
13847 cursor->get_hw_state = i845_cursor_get_hw_state;
13848 cursor->check_plane = i845_check_cursor;
13850 cursor->update_plane = i9xx_update_cursor;
13851 cursor->disable_plane = i9xx_disable_cursor;
13852 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13853 cursor->check_plane = i9xx_check_cursor;
13856 cursor->cursor.base = ~0;
13857 cursor->cursor.cntl = ~0;
13859 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13860 cursor->cursor.size = ~0;
13862 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13863 0, &intel_cursor_plane_funcs,
13864 intel_cursor_formats,
13865 ARRAY_SIZE(intel_cursor_formats),
13866 cursor_format_modifiers,
13867 DRM_PLANE_TYPE_CURSOR,
13868 "cursor %c", pipe_name(pipe));
13872 if (INTEL_GEN(dev_priv) >= 4)
13873 drm_plane_create_rotation_property(&cursor->base,
13875 DRM_MODE_ROTATE_0 |
13876 DRM_MODE_ROTATE_180);
13878 if (INTEL_GEN(dev_priv) >= 9)
13879 state->scaler_id = -1;
13881 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13889 return ERR_PTR(ret);
13892 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13893 struct intel_crtc_state *crtc_state)
13895 struct intel_crtc_scaler_state *scaler_state =
13896 &crtc_state->scaler_state;
13897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13900 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13901 if (!crtc->num_scalers)
13904 for (i = 0; i < crtc->num_scalers; i++) {
13905 struct intel_scaler *scaler = &scaler_state->scalers[i];
13907 scaler->in_use = 0;
13908 scaler->mode = PS_SCALER_MODE_DYN;
13911 scaler_state->scaler_id = -1;
13914 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13916 struct intel_crtc *intel_crtc;
13917 struct intel_crtc_state *crtc_state = NULL;
13918 struct intel_plane *primary = NULL;
13919 struct intel_plane *cursor = NULL;
13922 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13926 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13931 intel_crtc->config = crtc_state;
13932 intel_crtc->base.state = &crtc_state->base;
13933 crtc_state->base.crtc = &intel_crtc->base;
13935 primary = intel_primary_plane_create(dev_priv, pipe);
13936 if (IS_ERR(primary)) {
13937 ret = PTR_ERR(primary);
13940 intel_crtc->plane_ids_mask |= BIT(primary->id);
13942 for_each_sprite(dev_priv, pipe, sprite) {
13943 struct intel_plane *plane;
13945 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13946 if (IS_ERR(plane)) {
13947 ret = PTR_ERR(plane);
13950 intel_crtc->plane_ids_mask |= BIT(plane->id);
13953 cursor = intel_cursor_plane_create(dev_priv, pipe);
13954 if (IS_ERR(cursor)) {
13955 ret = PTR_ERR(cursor);
13958 intel_crtc->plane_ids_mask |= BIT(cursor->id);
13960 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13961 &primary->base, &cursor->base,
13963 "pipe %c", pipe_name(pipe));
13967 intel_crtc->pipe = pipe;
13969 /* initialize shared scalers */
13970 intel_crtc_init_scalers(intel_crtc, crtc_state);
13972 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13973 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13974 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13976 if (INTEL_GEN(dev_priv) < 9) {
13977 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13979 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13980 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13981 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13984 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13986 intel_color_init(&intel_crtc->base);
13988 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13994 * drm_mode_config_cleanup() will free up any
13995 * crtcs/planes already initialized.
14003 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14005 struct drm_device *dev = connector->base.dev;
14007 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14009 if (!connector->base.state->crtc)
14010 return INVALID_PIPE;
14012 return to_intel_crtc(connector->base.state->crtc)->pipe;
14015 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
14016 struct drm_file *file)
14018 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14019 struct drm_crtc *drmmode_crtc;
14020 struct intel_crtc *crtc;
14022 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
14026 crtc = to_intel_crtc(drmmode_crtc);
14027 pipe_from_crtc_id->pipe = crtc->pipe;
14032 static int intel_encoder_clones(struct intel_encoder *encoder)
14034 struct drm_device *dev = encoder->base.dev;
14035 struct intel_encoder *source_encoder;
14036 int index_mask = 0;
14039 for_each_intel_encoder(dev, source_encoder) {
14040 if (encoders_cloneable(encoder, source_encoder))
14041 index_mask |= (1 << entry);
14049 static bool has_edp_a(struct drm_i915_private *dev_priv)
14051 if (!IS_MOBILE(dev_priv))
14054 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14057 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14063 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14065 if (INTEL_GEN(dev_priv) >= 9)
14068 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14071 if (IS_CHERRYVIEW(dev_priv))
14074 if (HAS_PCH_LPT_H(dev_priv) &&
14075 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14078 /* DDI E can't be used if DDI A requires 4 lanes */
14079 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14082 if (!dev_priv->vbt.int_crt_support)
14088 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14093 if (HAS_DDI(dev_priv))
14096 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14097 * everywhere where registers can be write protected.
14099 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14104 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14105 u32 val = I915_READ(PP_CONTROL(pps_idx));
14107 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14108 I915_WRITE(PP_CONTROL(pps_idx), val);
14112 static void intel_pps_init(struct drm_i915_private *dev_priv)
14114 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14115 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14116 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14117 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14119 dev_priv->pps_mmio_base = PPS_BASE;
14121 intel_pps_unlock_regs_wa(dev_priv);
14124 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14126 struct intel_encoder *encoder;
14127 bool dpd_is_edp = false;
14129 intel_pps_init(dev_priv);
14132 * intel_edp_init_connector() depends on this completing first, to
14133 * prevent the registeration of both eDP and LVDS and the incorrect
14134 * sharing of the PPS.
14136 intel_lvds_init(dev_priv);
14138 if (intel_crt_present(dev_priv))
14139 intel_crt_init(dev_priv);
14141 if (IS_ICELAKE(dev_priv)) {
14142 intel_ddi_init(dev_priv, PORT_A);
14143 intel_ddi_init(dev_priv, PORT_B);
14144 intel_ddi_init(dev_priv, PORT_C);
14145 intel_ddi_init(dev_priv, PORT_D);
14146 intel_ddi_init(dev_priv, PORT_E);
14147 intel_ddi_init(dev_priv, PORT_F);
14148 } else if (IS_GEN9_LP(dev_priv)) {
14150 * FIXME: Broxton doesn't support port detection via the
14151 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14152 * detect the ports.
14154 intel_ddi_init(dev_priv, PORT_A);
14155 intel_ddi_init(dev_priv, PORT_B);
14156 intel_ddi_init(dev_priv, PORT_C);
14158 vlv_dsi_init(dev_priv);
14159 } else if (HAS_DDI(dev_priv)) {
14163 * Haswell uses DDI functions to detect digital outputs.
14164 * On SKL pre-D0 the strap isn't connected, so we assume
14167 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14168 /* WaIgnoreDDIAStrap: skl */
14169 if (found || IS_GEN9_BC(dev_priv))
14170 intel_ddi_init(dev_priv, PORT_A);
14172 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
14174 found = I915_READ(SFUSE_STRAP);
14176 if (found & SFUSE_STRAP_DDIB_DETECTED)
14177 intel_ddi_init(dev_priv, PORT_B);
14178 if (found & SFUSE_STRAP_DDIC_DETECTED)
14179 intel_ddi_init(dev_priv, PORT_C);
14180 if (found & SFUSE_STRAP_DDID_DETECTED)
14181 intel_ddi_init(dev_priv, PORT_D);
14182 if (found & SFUSE_STRAP_DDIF_DETECTED)
14183 intel_ddi_init(dev_priv, PORT_F);
14185 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14187 if (IS_GEN9_BC(dev_priv) &&
14188 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14189 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14190 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14191 intel_ddi_init(dev_priv, PORT_E);
14193 } else if (HAS_PCH_SPLIT(dev_priv)) {
14195 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
14197 if (has_edp_a(dev_priv))
14198 intel_dp_init(dev_priv, DP_A, PORT_A);
14200 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14201 /* PCH SDVOB multiplex with HDMIB */
14202 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14204 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14205 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14206 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14209 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14210 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14212 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14213 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14215 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14216 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14218 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14219 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14220 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14221 bool has_edp, has_port;
14224 * The DP_DETECTED bit is the latched state of the DDC
14225 * SDA pin at boot. However since eDP doesn't require DDC
14226 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14227 * eDP ports may have been muxed to an alternate function.
14228 * Thus we can't rely on the DP_DETECTED bit alone to detect
14229 * eDP ports. Consult the VBT as well as DP_DETECTED to
14230 * detect eDP ports.
14232 * Sadly the straps seem to be missing sometimes even for HDMI
14233 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14234 * and VBT for the presence of the port. Additionally we can't
14235 * trust the port type the VBT declares as we've seen at least
14236 * HDMI ports that the VBT claim are DP or eDP.
14238 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
14239 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14240 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14241 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14242 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14243 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14245 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
14246 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14247 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14248 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14249 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14250 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14252 if (IS_CHERRYVIEW(dev_priv)) {
14254 * eDP not supported on port D,
14255 * so no need to worry about it
14257 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14258 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14259 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14260 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14261 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14264 vlv_dsi_init(dev_priv);
14265 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14266 bool found = false;
14268 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14269 DRM_DEBUG_KMS("probing SDVOB\n");
14270 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14271 if (!found && IS_G4X(dev_priv)) {
14272 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14273 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14276 if (!found && IS_G4X(dev_priv))
14277 intel_dp_init(dev_priv, DP_B, PORT_B);
14280 /* Before G4X SDVOC doesn't have its own detect register */
14282 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14283 DRM_DEBUG_KMS("probing SDVOC\n");
14284 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14287 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14289 if (IS_G4X(dev_priv)) {
14290 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14291 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14293 if (IS_G4X(dev_priv))
14294 intel_dp_init(dev_priv, DP_C, PORT_C);
14297 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14298 intel_dp_init(dev_priv, DP_D, PORT_D);
14299 } else if (IS_GEN2(dev_priv))
14300 intel_dvo_init(dev_priv);
14302 if (SUPPORTS_TV(dev_priv))
14303 intel_tv_init(dev_priv);
14305 intel_psr_init(dev_priv);
14307 for_each_intel_encoder(&dev_priv->drm, encoder) {
14308 encoder->base.possible_crtcs = encoder->crtc_mask;
14309 encoder->base.possible_clones =
14310 intel_encoder_clones(encoder);
14313 intel_init_pch_refclk(dev_priv);
14315 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14318 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14320 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14321 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14323 drm_framebuffer_cleanup(fb);
14325 i915_gem_object_lock(obj);
14326 WARN_ON(!obj->framebuffer_references--);
14327 i915_gem_object_unlock(obj);
14329 i915_gem_object_put(obj);
14334 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14335 struct drm_file *file,
14336 unsigned int *handle)
14338 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14340 if (obj->userptr.mm) {
14341 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14345 return drm_gem_handle_create(file, &obj->base, handle);
14348 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14349 struct drm_file *file,
14350 unsigned flags, unsigned color,
14351 struct drm_clip_rect *clips,
14352 unsigned num_clips)
14354 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14356 i915_gem_object_flush_if_display(obj);
14357 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14362 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14363 .destroy = intel_user_framebuffer_destroy,
14364 .create_handle = intel_user_framebuffer_create_handle,
14365 .dirty = intel_user_framebuffer_dirty,
14369 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14370 uint64_t fb_modifier, uint32_t pixel_format)
14372 u32 gen = INTEL_GEN(dev_priv);
14375 int cpp = drm_format_plane_cpp(pixel_format, 0);
14377 /* "The stride in bytes must not exceed the of the size of 8K
14378 * pixels and 32K bytes."
14380 return min(8192 * cpp, 32768);
14381 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14383 } else if (gen >= 4) {
14384 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14388 } else if (gen >= 3) {
14389 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14394 /* XXX DSPC is limited to 4k tiled */
14399 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14400 struct drm_i915_gem_object *obj,
14401 struct drm_mode_fb_cmd2 *mode_cmd)
14403 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14404 struct drm_framebuffer *fb = &intel_fb->base;
14405 struct drm_format_name_buf format_name;
14407 unsigned int tiling, stride;
14411 i915_gem_object_lock(obj);
14412 obj->framebuffer_references++;
14413 tiling = i915_gem_object_get_tiling(obj);
14414 stride = i915_gem_object_get_stride(obj);
14415 i915_gem_object_unlock(obj);
14417 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14419 * If there's a fence, enforce that
14420 * the fb modifier and tiling mode match.
14422 if (tiling != I915_TILING_NONE &&
14423 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14424 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14428 if (tiling == I915_TILING_X) {
14429 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14430 } else if (tiling == I915_TILING_Y) {
14431 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14436 /* Passed in modifier sanity checking. */
14437 switch (mode_cmd->modifier[0]) {
14438 case I915_FORMAT_MOD_Y_TILED_CCS:
14439 case I915_FORMAT_MOD_Yf_TILED_CCS:
14440 switch (mode_cmd->pixel_format) {
14441 case DRM_FORMAT_XBGR8888:
14442 case DRM_FORMAT_ABGR8888:
14443 case DRM_FORMAT_XRGB8888:
14444 case DRM_FORMAT_ARGB8888:
14447 DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14451 case I915_FORMAT_MOD_Y_TILED:
14452 case I915_FORMAT_MOD_Yf_TILED:
14453 if (INTEL_GEN(dev_priv) < 9) {
14454 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14455 mode_cmd->modifier[0]);
14458 case DRM_FORMAT_MOD_LINEAR:
14459 case I915_FORMAT_MOD_X_TILED:
14462 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14463 mode_cmd->modifier[0]);
14468 * gen2/3 display engine uses the fence if present,
14469 * so the tiling mode must match the fb modifier exactly.
14471 if (INTEL_GEN(dev_priv) < 4 &&
14472 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14473 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14477 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14478 mode_cmd->pixel_format);
14479 if (mode_cmd->pitches[0] > pitch_limit) {
14480 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14481 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14482 "tiled" : "linear",
14483 mode_cmd->pitches[0], pitch_limit);
14488 * If there's a fence, enforce that
14489 * the fb pitch and fence stride match.
14491 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14492 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14493 mode_cmd->pitches[0], stride);
14497 /* Reject formats not supported by any plane early. */
14498 switch (mode_cmd->pixel_format) {
14499 case DRM_FORMAT_C8:
14500 case DRM_FORMAT_RGB565:
14501 case DRM_FORMAT_XRGB8888:
14502 case DRM_FORMAT_ARGB8888:
14504 case DRM_FORMAT_XRGB1555:
14505 if (INTEL_GEN(dev_priv) > 3) {
14506 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14507 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14511 case DRM_FORMAT_ABGR8888:
14512 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14513 INTEL_GEN(dev_priv) < 9) {
14514 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14515 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14519 case DRM_FORMAT_XBGR8888:
14520 case DRM_FORMAT_XRGB2101010:
14521 case DRM_FORMAT_XBGR2101010:
14522 if (INTEL_GEN(dev_priv) < 4) {
14523 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14524 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14528 case DRM_FORMAT_ABGR2101010:
14529 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14530 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14531 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14535 case DRM_FORMAT_YUYV:
14536 case DRM_FORMAT_UYVY:
14537 case DRM_FORMAT_YVYU:
14538 case DRM_FORMAT_VYUY:
14539 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14540 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14541 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14545 case DRM_FORMAT_NV12:
14546 if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) ||
14547 IS_BROXTON(dev_priv)) {
14548 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14549 drm_get_format_name(mode_cmd->pixel_format,
14555 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14556 drm_get_format_name(mode_cmd->pixel_format, &format_name));
14560 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14561 if (mode_cmd->offsets[0] != 0)
14564 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14566 if (fb->format->format == DRM_FORMAT_NV12 &&
14567 (fb->width < SKL_MIN_YUV_420_SRC_W ||
14568 fb->height < SKL_MIN_YUV_420_SRC_H ||
14569 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14570 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14574 for (i = 0; i < fb->format->num_planes; i++) {
14575 u32 stride_alignment;
14577 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14578 DRM_DEBUG_KMS("bad plane %d handle\n", i);
14582 stride_alignment = intel_fb_stride_alignment(fb, i);
14585 * Display WA #0531: skl,bxt,kbl,glk
14587 * Render decompression and plane width > 3840
14588 * combined with horizontal panning requires the
14589 * plane stride to be a multiple of 4. We'll just
14590 * require the entire fb to accommodate that to avoid
14591 * potential runtime errors at plane configuration time.
14593 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14594 (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14595 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14596 stride_alignment *= 4;
14598 if (fb->pitches[i] & (stride_alignment - 1)) {
14599 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14600 i, fb->pitches[i], stride_alignment);
14604 fb->obj[i] = &obj->base;
14607 ret = intel_fill_fb_info(dev_priv, fb);
14611 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14613 DRM_ERROR("framebuffer init failed %d\n", ret);
14620 i915_gem_object_lock(obj);
14621 obj->framebuffer_references--;
14622 i915_gem_object_unlock(obj);
14626 static struct drm_framebuffer *
14627 intel_user_framebuffer_create(struct drm_device *dev,
14628 struct drm_file *filp,
14629 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14631 struct drm_framebuffer *fb;
14632 struct drm_i915_gem_object *obj;
14633 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14635 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14637 return ERR_PTR(-ENOENT);
14639 fb = intel_framebuffer_create(obj, &mode_cmd);
14641 i915_gem_object_put(obj);
14646 static void intel_atomic_state_free(struct drm_atomic_state *state)
14648 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14650 drm_atomic_state_default_release(state);
14652 i915_sw_fence_fini(&intel_state->commit_ready);
14657 static enum drm_mode_status
14658 intel_mode_valid(struct drm_device *dev,
14659 const struct drm_display_mode *mode)
14661 struct drm_i915_private *dev_priv = to_i915(dev);
14662 int hdisplay_max, htotal_max;
14663 int vdisplay_max, vtotal_max;
14666 * Can't reject DBLSCAN here because Xorg ddxen can add piles
14667 * of DBLSCAN modes to the output's mode list when they detect
14668 * the scaling mode property on the connector. And they don't
14669 * ask the kernel to validate those modes in any way until
14670 * modeset time at which point the client gets a protocol error.
14671 * So in order to not upset those clients we silently ignore the
14672 * DBLSCAN flag on such connectors. For other connectors we will
14673 * reject modes with the DBLSCAN flag in encoder->compute_config().
14674 * And we always reject DBLSCAN modes in connector->mode_valid()
14675 * as we never want such modes on the connector's mode list.
14678 if (mode->vscan > 1)
14679 return MODE_NO_VSCAN;
14681 if (mode->flags & DRM_MODE_FLAG_HSKEW)
14682 return MODE_H_ILLEGAL;
14684 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14685 DRM_MODE_FLAG_NCSYNC |
14686 DRM_MODE_FLAG_PCSYNC))
14689 if (mode->flags & (DRM_MODE_FLAG_BCAST |
14690 DRM_MODE_FLAG_PIXMUX |
14691 DRM_MODE_FLAG_CLKDIV2))
14694 if (INTEL_GEN(dev_priv) >= 9 ||
14695 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
14696 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
14697 vdisplay_max = 4096;
14700 } else if (INTEL_GEN(dev_priv) >= 3) {
14701 hdisplay_max = 4096;
14702 vdisplay_max = 4096;
14706 hdisplay_max = 2048;
14707 vdisplay_max = 2048;
14712 if (mode->hdisplay > hdisplay_max ||
14713 mode->hsync_start > htotal_max ||
14714 mode->hsync_end > htotal_max ||
14715 mode->htotal > htotal_max)
14716 return MODE_H_ILLEGAL;
14718 if (mode->vdisplay > vdisplay_max ||
14719 mode->vsync_start > vtotal_max ||
14720 mode->vsync_end > vtotal_max ||
14721 mode->vtotal > vtotal_max)
14722 return MODE_V_ILLEGAL;
14727 static const struct drm_mode_config_funcs intel_mode_funcs = {
14728 .fb_create = intel_user_framebuffer_create,
14729 .get_format_info = intel_get_format_info,
14730 .output_poll_changed = intel_fbdev_output_poll_changed,
14731 .mode_valid = intel_mode_valid,
14732 .atomic_check = intel_atomic_check,
14733 .atomic_commit = intel_atomic_commit,
14734 .atomic_state_alloc = intel_atomic_state_alloc,
14735 .atomic_state_clear = intel_atomic_state_clear,
14736 .atomic_state_free = intel_atomic_state_free,
14740 * intel_init_display_hooks - initialize the display modesetting hooks
14741 * @dev_priv: device private
14743 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14745 intel_init_cdclk_hooks(dev_priv);
14747 if (INTEL_GEN(dev_priv) >= 9) {
14748 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14749 dev_priv->display.get_initial_plane_config =
14750 skylake_get_initial_plane_config;
14751 dev_priv->display.crtc_compute_clock =
14752 haswell_crtc_compute_clock;
14753 dev_priv->display.crtc_enable = haswell_crtc_enable;
14754 dev_priv->display.crtc_disable = haswell_crtc_disable;
14755 } else if (HAS_DDI(dev_priv)) {
14756 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14757 dev_priv->display.get_initial_plane_config =
14758 i9xx_get_initial_plane_config;
14759 dev_priv->display.crtc_compute_clock =
14760 haswell_crtc_compute_clock;
14761 dev_priv->display.crtc_enable = haswell_crtc_enable;
14762 dev_priv->display.crtc_disable = haswell_crtc_disable;
14763 } else if (HAS_PCH_SPLIT(dev_priv)) {
14764 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14765 dev_priv->display.get_initial_plane_config =
14766 i9xx_get_initial_plane_config;
14767 dev_priv->display.crtc_compute_clock =
14768 ironlake_crtc_compute_clock;
14769 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14770 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14771 } else if (IS_CHERRYVIEW(dev_priv)) {
14772 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14773 dev_priv->display.get_initial_plane_config =
14774 i9xx_get_initial_plane_config;
14775 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14776 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14777 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14778 } else if (IS_VALLEYVIEW(dev_priv)) {
14779 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14780 dev_priv->display.get_initial_plane_config =
14781 i9xx_get_initial_plane_config;
14782 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14783 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14784 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14785 } else if (IS_G4X(dev_priv)) {
14786 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14787 dev_priv->display.get_initial_plane_config =
14788 i9xx_get_initial_plane_config;
14789 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14790 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14791 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14792 } else if (IS_PINEVIEW(dev_priv)) {
14793 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14794 dev_priv->display.get_initial_plane_config =
14795 i9xx_get_initial_plane_config;
14796 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14797 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14798 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14799 } else if (!IS_GEN2(dev_priv)) {
14800 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14801 dev_priv->display.get_initial_plane_config =
14802 i9xx_get_initial_plane_config;
14803 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14804 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14805 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14807 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14808 dev_priv->display.get_initial_plane_config =
14809 i9xx_get_initial_plane_config;
14810 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14811 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14812 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14815 if (IS_GEN5(dev_priv)) {
14816 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14817 } else if (IS_GEN6(dev_priv)) {
14818 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14819 } else if (IS_IVYBRIDGE(dev_priv)) {
14820 /* FIXME: detect B0+ stepping and use auto training */
14821 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14822 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14823 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14826 if (INTEL_GEN(dev_priv) >= 9)
14827 dev_priv->display.update_crtcs = skl_update_crtcs;
14829 dev_priv->display.update_crtcs = intel_update_crtcs;
14833 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14835 static void quirk_ssc_force_disable(struct drm_device *dev)
14837 struct drm_i915_private *dev_priv = to_i915(dev);
14838 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14839 DRM_INFO("applying lvds SSC disable quirk\n");
14843 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14846 static void quirk_invert_brightness(struct drm_device *dev)
14848 struct drm_i915_private *dev_priv = to_i915(dev);
14849 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14850 DRM_INFO("applying inverted panel brightness quirk\n");
14853 /* Some VBT's incorrectly indicate no backlight is present */
14854 static void quirk_backlight_present(struct drm_device *dev)
14856 struct drm_i915_private *dev_priv = to_i915(dev);
14857 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14858 DRM_INFO("applying backlight present quirk\n");
14861 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14862 * which is 300 ms greater than eDP spec T12 min.
14864 static void quirk_increase_t12_delay(struct drm_device *dev)
14866 struct drm_i915_private *dev_priv = to_i915(dev);
14868 dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14869 DRM_INFO("Applying T12 delay quirk\n");
14873 * GeminiLake NUC HDMI outputs require additional off time
14874 * this allows the onboard retimer to correctly sync to signal
14876 static void quirk_increase_ddi_disabled_time(struct drm_device *dev)
14878 struct drm_i915_private *dev_priv = to_i915(dev);
14880 dev_priv->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
14881 DRM_INFO("Applying Increase DDI Disabled quirk\n");
14884 struct intel_quirk {
14886 int subsystem_vendor;
14887 int subsystem_device;
14888 void (*hook)(struct drm_device *dev);
14891 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14892 struct intel_dmi_quirk {
14893 void (*hook)(struct drm_device *dev);
14894 const struct dmi_system_id (*dmi_id_list)[];
14897 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14899 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14903 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14905 .dmi_id_list = &(const struct dmi_system_id[]) {
14907 .callback = intel_dmi_reverse_brightness,
14908 .ident = "NCR Corporation",
14909 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14910 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14913 { } /* terminating entry */
14915 .hook = quirk_invert_brightness,
14919 static struct intel_quirk intel_quirks[] = {
14920 /* Lenovo U160 cannot use SSC on LVDS */
14921 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14923 /* Sony Vaio Y cannot use SSC on LVDS */
14924 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14926 /* Acer Aspire 5734Z must invert backlight brightness */
14927 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14929 /* Acer/eMachines G725 */
14930 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14932 /* Acer/eMachines e725 */
14933 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14935 /* Acer/Packard Bell NCL20 */
14936 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14938 /* Acer Aspire 4736Z */
14939 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14941 /* Acer Aspire 5336 */
14942 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14944 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14945 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14947 /* Acer C720 Chromebook (Core i3 4005U) */
14948 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14950 /* Apple Macbook 2,1 (Core 2 T7400) */
14951 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14953 /* Apple Macbook 4,1 */
14954 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14956 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14957 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14959 /* HP Chromebook 14 (Celeron 2955U) */
14960 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14962 /* Dell Chromebook 11 */
14963 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14965 /* Dell Chromebook 11 (2015 version) */
14966 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14968 /* Toshiba Satellite P50-C-18C */
14969 { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14971 /* GeminiLake NUC */
14972 { 0x3185, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14973 { 0x3184, 0x8086, 0x2072, quirk_increase_ddi_disabled_time },
14975 { 0x3185, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14976 { 0x3184, 0x1849, 0x2212, quirk_increase_ddi_disabled_time },
14979 static void intel_init_quirks(struct drm_device *dev)
14981 struct pci_dev *d = dev->pdev;
14984 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14985 struct intel_quirk *q = &intel_quirks[i];
14987 if (d->device == q->device &&
14988 (d->subsystem_vendor == q->subsystem_vendor ||
14989 q->subsystem_vendor == PCI_ANY_ID) &&
14990 (d->subsystem_device == q->subsystem_device ||
14991 q->subsystem_device == PCI_ANY_ID))
14994 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14995 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14996 intel_dmi_quirks[i].hook(dev);
15000 /* Disable the VGA plane that we never use */
15001 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15003 struct pci_dev *pdev = dev_priv->drm.pdev;
15005 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15007 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15008 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
15009 outb(SR01, VGA_SR_INDEX);
15010 sr1 = inb(VGA_SR_DATA);
15011 outb(sr1 | 1<<5, VGA_SR_DATA);
15012 vga_put(pdev, VGA_RSRC_LEGACY_IO);
15015 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15016 POSTING_READ(vga_reg);
15019 void intel_modeset_init_hw(struct drm_device *dev)
15021 struct drm_i915_private *dev_priv = to_i915(dev);
15023 intel_update_cdclk(dev_priv);
15024 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
15025 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
15029 * Calculate what we think the watermarks should be for the state we've read
15030 * out of the hardware and then immediately program those watermarks so that
15031 * we ensure the hardware settings match our internal state.
15033 * We can calculate what we think WM's should be by creating a duplicate of the
15034 * current state (which was constructed during hardware readout) and running it
15035 * through the atomic check code to calculate new watermark values in the
15038 static void sanitize_watermarks(struct drm_device *dev)
15040 struct drm_i915_private *dev_priv = to_i915(dev);
15041 struct drm_atomic_state *state;
15042 struct intel_atomic_state *intel_state;
15043 struct drm_crtc *crtc;
15044 struct drm_crtc_state *cstate;
15045 struct drm_modeset_acquire_ctx ctx;
15049 /* Only supported on platforms that use atomic watermark design */
15050 if (!dev_priv->display.optimize_watermarks)
15054 * We need to hold connection_mutex before calling duplicate_state so
15055 * that the connector loop is protected.
15057 drm_modeset_acquire_init(&ctx, 0);
15059 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15060 if (ret == -EDEADLK) {
15061 drm_modeset_backoff(&ctx);
15063 } else if (WARN_ON(ret)) {
15067 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15068 if (WARN_ON(IS_ERR(state)))
15071 intel_state = to_intel_atomic_state(state);
15074 * Hardware readout is the only time we don't want to calculate
15075 * intermediate watermarks (since we don't trust the current
15078 if (!HAS_GMCH_DISPLAY(dev_priv))
15079 intel_state->skip_intermediate_wm = true;
15081 ret = intel_atomic_check(dev, state);
15084 * If we fail here, it means that the hardware appears to be
15085 * programmed in a way that shouldn't be possible, given our
15086 * understanding of watermark requirements. This might mean a
15087 * mistake in the hardware readout code or a mistake in the
15088 * watermark calculations for a given platform. Raise a WARN
15089 * so that this is noticeable.
15091 * If this actually happens, we'll have to just leave the
15092 * BIOS-programmed watermarks untouched and hope for the best.
15094 WARN(true, "Could not determine valid watermarks for inherited state\n");
15098 /* Write calculated watermark values back */
15099 for_each_new_crtc_in_state(state, crtc, cstate, i) {
15100 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15102 cs->wm.need_postvbl_update = true;
15103 dev_priv->display.optimize_watermarks(intel_state, cs);
15105 to_intel_crtc_state(crtc->state)->wm = cs->wm;
15109 drm_atomic_state_put(state);
15111 drm_modeset_drop_locks(&ctx);
15112 drm_modeset_acquire_fini(&ctx);
15115 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
15117 if (IS_GEN5(dev_priv)) {
15119 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
15121 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
15122 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
15123 dev_priv->fdi_pll_freq = 270000;
15128 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
15131 int intel_modeset_init(struct drm_device *dev)
15133 struct drm_i915_private *dev_priv = to_i915(dev);
15134 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15136 struct intel_crtc *crtc;
15138 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
15140 drm_mode_config_init(dev);
15142 dev->mode_config.min_width = 0;
15143 dev->mode_config.min_height = 0;
15145 dev->mode_config.preferred_depth = 24;
15146 dev->mode_config.prefer_shadow = 1;
15148 dev->mode_config.allow_fb_modifiers = true;
15150 dev->mode_config.funcs = &intel_mode_funcs;
15152 init_llist_head(&dev_priv->atomic_helper.free_list);
15153 INIT_WORK(&dev_priv->atomic_helper.free_work,
15154 intel_atomic_helper_free_state_worker);
15156 intel_init_quirks(dev);
15158 intel_init_pm(dev_priv);
15160 if (INTEL_INFO(dev_priv)->num_pipes == 0)
15164 * There may be no VBT; and if the BIOS enabled SSC we can
15165 * just keep using it to avoid unnecessary flicker. Whereas if the
15166 * BIOS isn't using it, don't assume it will work even if the VBT
15167 * indicates as much.
15169 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15170 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15173 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15174 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15175 bios_lvds_use_ssc ? "en" : "dis",
15176 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15177 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15181 /* maximum framebuffer dimensions */
15182 if (IS_GEN2(dev_priv)) {
15183 dev->mode_config.max_width = 2048;
15184 dev->mode_config.max_height = 2048;
15185 } else if (IS_GEN3(dev_priv)) {
15186 dev->mode_config.max_width = 4096;
15187 dev->mode_config.max_height = 4096;
15189 dev->mode_config.max_width = 8192;
15190 dev->mode_config.max_height = 8192;
15193 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15194 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15195 dev->mode_config.cursor_height = 1023;
15196 } else if (IS_GEN2(dev_priv)) {
15197 dev->mode_config.cursor_width = 64;
15198 dev->mode_config.cursor_height = 64;
15200 dev->mode_config.cursor_width = 256;
15201 dev->mode_config.cursor_height = 256;
15204 dev->mode_config.fb_base = ggtt->gmadr.start;
15206 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15207 INTEL_INFO(dev_priv)->num_pipes,
15208 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15210 for_each_pipe(dev_priv, pipe) {
15213 ret = intel_crtc_init(dev_priv, pipe);
15215 drm_mode_config_cleanup(dev);
15220 intel_shared_dpll_init(dev);
15221 intel_update_fdi_pll_freq(dev_priv);
15223 intel_update_czclk(dev_priv);
15224 intel_modeset_init_hw(dev);
15226 if (dev_priv->max_cdclk_freq == 0)
15227 intel_update_max_cdclk(dev_priv);
15229 /* Just disable it once at startup */
15230 i915_disable_vga(dev_priv);
15231 intel_setup_outputs(dev_priv);
15233 drm_modeset_lock_all(dev);
15234 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
15235 drm_modeset_unlock_all(dev);
15237 for_each_intel_crtc(dev, crtc) {
15238 struct intel_initial_plane_config plane_config = {};
15244 * Note that reserving the BIOS fb up front prevents us
15245 * from stuffing other stolen allocations like the ring
15246 * on top. This prevents some ugliness at boot time, and
15247 * can even allow for smooth boot transitions if the BIOS
15248 * fb is large enough for the active pipe configuration.
15250 dev_priv->display.get_initial_plane_config(crtc,
15254 * If the fb is shared between multiple heads, we'll
15255 * just get the first one.
15257 intel_find_initial_plane_obj(crtc, &plane_config);
15261 * Make sure hardware watermarks really match the state we read out.
15262 * Note that we need to do this after reconstructing the BIOS fb's
15263 * since the watermark calculation done here will use pstate->fb.
15265 if (!HAS_GMCH_DISPLAY(dev_priv))
15266 sanitize_watermarks(dev);
15271 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15273 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15274 /* 640x480@60Hz, ~25175 kHz */
15275 struct dpll clock = {
15285 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
15287 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
15288 pipe_name(pipe), clock.vco, clock.dot);
15290 fp = i9xx_dpll_compute_fp(&clock);
15291 dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
15292 DPLL_VGA_MODE_DIS |
15293 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
15294 PLL_P2_DIVIDE_BY_4 |
15295 PLL_REF_INPUT_DREFCLK |
15298 I915_WRITE(FP0(pipe), fp);
15299 I915_WRITE(FP1(pipe), fp);
15301 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
15302 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
15303 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
15304 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
15305 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
15306 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
15307 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
15310 * Apparently we need to have VGA mode enabled prior to changing
15311 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
15312 * dividers, even though the register value does change.
15314 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
15315 I915_WRITE(DPLL(pipe), dpll);
15317 /* Wait for the clocks to stabilize. */
15318 POSTING_READ(DPLL(pipe));
15321 /* The pixel multiplier can only be updated once the
15322 * DPLL is enabled and the clocks are stable.
15324 * So write it again.
15326 I915_WRITE(DPLL(pipe), dpll);
15328 /* We do this three times for luck */
15329 for (i = 0; i < 3 ; i++) {
15330 I915_WRITE(DPLL(pipe), dpll);
15331 POSTING_READ(DPLL(pipe));
15332 udelay(150); /* wait for warmup */
15335 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
15336 POSTING_READ(PIPECONF(pipe));
15338 intel_wait_for_pipe_scanline_moving(crtc);
15341 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
15343 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15345 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
15348 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
15349 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
15350 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
15351 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
15352 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
15354 I915_WRITE(PIPECONF(pipe), 0);
15355 POSTING_READ(PIPECONF(pipe));
15357 intel_wait_for_pipe_scanline_stopped(crtc);
15359 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
15360 POSTING_READ(DPLL(pipe));
15363 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
15364 struct intel_plane *plane)
15368 if (!plane->get_hw_state(plane, &pipe))
15371 return pipe == crtc->pipe;
15375 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
15377 struct intel_crtc *crtc;
15379 if (INTEL_GEN(dev_priv) >= 4)
15382 for_each_intel_crtc(&dev_priv->drm, crtc) {
15383 struct intel_plane *plane =
15384 to_intel_plane(crtc->base.primary);
15386 if (intel_plane_mapping_ok(crtc, plane))
15389 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15391 intel_plane_disable_noatomic(crtc, plane);
15395 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15397 struct drm_device *dev = crtc->base.dev;
15398 struct intel_encoder *encoder;
15400 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15406 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15408 struct drm_device *dev = encoder->base.dev;
15409 struct intel_connector *connector;
15411 for_each_connector_on_encoder(dev, &encoder->base, connector)
15417 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15418 enum pipe pch_transcoder)
15420 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15421 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15424 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15425 struct drm_modeset_acquire_ctx *ctx)
15427 struct drm_device *dev = crtc->base.dev;
15428 struct drm_i915_private *dev_priv = to_i915(dev);
15429 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15431 /* Clear any frame start delays used for debugging left by the BIOS */
15432 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15433 i915_reg_t reg = PIPECONF(cpu_transcoder);
15436 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15439 /* restore vblank interrupts to correct state */
15440 drm_crtc_vblank_reset(&crtc->base);
15441 if (crtc->active) {
15442 struct intel_plane *plane;
15444 drm_crtc_vblank_on(&crtc->base);
15446 /* Disable everything but the primary plane */
15447 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15448 const struct intel_plane_state *plane_state =
15449 to_intel_plane_state(plane->base.state);
15451 if (plane_state->base.visible &&
15452 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15453 intel_plane_disable_noatomic(crtc, plane);
15457 /* Adjust the state of the output pipe according to whether we
15458 * have active connectors/encoders. */
15459 if (crtc->active && !intel_crtc_has_encoders(crtc))
15460 intel_crtc_disable_noatomic(&crtc->base, ctx);
15462 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15464 * We start out with underrun reporting disabled to avoid races.
15465 * For correct bookkeeping mark this on active crtcs.
15467 * Also on gmch platforms we dont have any hardware bits to
15468 * disable the underrun reporting. Which means we need to start
15469 * out with underrun reporting disabled also on inactive pipes,
15470 * since otherwise we'll complain about the garbage we read when
15471 * e.g. coming up after runtime pm.
15473 * No protection against concurrent access is required - at
15474 * worst a fifo underrun happens which also sets this to false.
15476 crtc->cpu_fifo_underrun_disabled = true;
15478 * We track the PCH trancoder underrun reporting state
15479 * within the crtc. With crtc for pipe A housing the underrun
15480 * reporting state for PCH transcoder A, crtc for pipe B housing
15481 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15482 * and marking underrun reporting as disabled for the non-existing
15483 * PCH transcoders B and C would prevent enabling the south
15484 * error interrupt (see cpt_can_enable_serr_int()).
15486 if (has_pch_trancoder(dev_priv, crtc->pipe))
15487 crtc->pch_fifo_underrun_disabled = true;
15491 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15493 struct intel_connector *connector;
15495 /* We need to check both for a crtc link (meaning that the
15496 * encoder is active and trying to read from a pipe) and the
15497 * pipe itself being active. */
15498 bool has_active_crtc = encoder->base.crtc &&
15499 to_intel_crtc(encoder->base.crtc)->active;
15501 connector = intel_encoder_find_connector(encoder);
15502 if (connector && !has_active_crtc) {
15503 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15504 encoder->base.base.id,
15505 encoder->base.name);
15507 /* Connector is active, but has no active pipe. This is
15508 * fallout from our resume register restoring. Disable
15509 * the encoder manually again. */
15510 if (encoder->base.crtc) {
15511 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15513 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15514 encoder->base.base.id,
15515 encoder->base.name);
15516 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15517 if (encoder->post_disable)
15518 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15520 encoder->base.crtc = NULL;
15522 /* Inconsistent output/port/pipe state happens presumably due to
15523 * a bug in one of the get_hw_state functions. Or someplace else
15524 * in our code, like the register restore mess on resume. Clamp
15525 * things to off as a safer default. */
15527 connector->base.dpms = DRM_MODE_DPMS_OFF;
15528 connector->base.encoder = NULL;
15531 /* notify opregion of the sanitized encoder state */
15532 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
15535 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15537 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15539 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15540 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15541 i915_disable_vga(dev_priv);
15545 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15547 /* This function can be called both from intel_modeset_setup_hw_state or
15548 * at a very early point in our resume sequence, where the power well
15549 * structures are not yet restored. Since this function is at a very
15550 * paranoid "someone might have enabled VGA while we were not looking"
15551 * level, just check if the power well is enabled instead of trying to
15552 * follow the "don't touch the power well if we don't need it" policy
15553 * the rest of the driver uses. */
15554 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15557 i915_redisable_vga_power_on(dev_priv);
15559 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15562 /* FIXME read out full plane state for all planes */
15563 static void readout_plane_state(struct intel_crtc *crtc)
15565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15566 struct intel_crtc_state *crtc_state =
15567 to_intel_crtc_state(crtc->base.state);
15568 struct intel_plane *plane;
15570 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15571 struct intel_plane_state *plane_state =
15572 to_intel_plane_state(plane->base.state);
15576 visible = plane->get_hw_state(plane, &pipe);
15578 intel_set_plane_visible(crtc_state, plane_state, visible);
15582 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15584 struct drm_i915_private *dev_priv = to_i915(dev);
15586 struct intel_crtc *crtc;
15587 struct intel_encoder *encoder;
15588 struct intel_connector *connector;
15589 struct drm_connector_list_iter conn_iter;
15592 dev_priv->active_crtcs = 0;
15594 for_each_intel_crtc(dev, crtc) {
15595 struct intel_crtc_state *crtc_state =
15596 to_intel_crtc_state(crtc->base.state);
15598 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15599 memset(crtc_state, 0, sizeof(*crtc_state));
15600 crtc_state->base.crtc = &crtc->base;
15602 crtc_state->base.active = crtc_state->base.enable =
15603 dev_priv->display.get_pipe_config(crtc, crtc_state);
15605 crtc->base.enabled = crtc_state->base.enable;
15606 crtc->active = crtc_state->base.active;
15608 if (crtc_state->base.active)
15609 dev_priv->active_crtcs |= 1 << crtc->pipe;
15611 readout_plane_state(crtc);
15613 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15614 crtc->base.base.id, crtc->base.name,
15615 enableddisabled(crtc_state->base.active));
15618 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15619 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15621 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15622 &pll->state.hw_state);
15623 pll->state.crtc_mask = 0;
15624 for_each_intel_crtc(dev, crtc) {
15625 struct intel_crtc_state *crtc_state =
15626 to_intel_crtc_state(crtc->base.state);
15628 if (crtc_state->base.active &&
15629 crtc_state->shared_dpll == pll)
15630 pll->state.crtc_mask |= 1 << crtc->pipe;
15632 pll->active_mask = pll->state.crtc_mask;
15634 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15635 pll->info->name, pll->state.crtc_mask, pll->on);
15638 for_each_intel_encoder(dev, encoder) {
15641 if (encoder->get_hw_state(encoder, &pipe)) {
15642 struct intel_crtc_state *crtc_state;
15644 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15645 crtc_state = to_intel_crtc_state(crtc->base.state);
15647 encoder->base.crtc = &crtc->base;
15648 encoder->get_config(encoder, crtc_state);
15650 encoder->base.crtc = NULL;
15653 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15654 encoder->base.base.id, encoder->base.name,
15655 enableddisabled(encoder->base.crtc),
15659 drm_connector_list_iter_begin(dev, &conn_iter);
15660 for_each_intel_connector_iter(connector, &conn_iter) {
15661 if (connector->get_hw_state(connector)) {
15662 connector->base.dpms = DRM_MODE_DPMS_ON;
15664 encoder = connector->encoder;
15665 connector->base.encoder = &encoder->base;
15667 if (encoder->base.crtc &&
15668 encoder->base.crtc->state->active) {
15670 * This has to be done during hardware readout
15671 * because anything calling .crtc_disable may
15672 * rely on the connector_mask being accurate.
15674 encoder->base.crtc->state->connector_mask |=
15675 drm_connector_mask(&connector->base);
15676 encoder->base.crtc->state->encoder_mask |=
15677 drm_encoder_mask(&encoder->base);
15681 connector->base.dpms = DRM_MODE_DPMS_OFF;
15682 connector->base.encoder = NULL;
15684 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15685 connector->base.base.id, connector->base.name,
15686 enableddisabled(connector->base.encoder));
15688 drm_connector_list_iter_end(&conn_iter);
15690 for_each_intel_crtc(dev, crtc) {
15691 struct intel_crtc_state *crtc_state =
15692 to_intel_crtc_state(crtc->base.state);
15695 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15696 if (crtc_state->base.active) {
15697 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15698 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
15699 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
15700 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15701 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15704 * The initial mode needs to be set in order to keep
15705 * the atomic core happy. It wants a valid mode if the
15706 * crtc's enabled, so we do the above call.
15708 * But we don't set all the derived state fully, hence
15709 * set a flag to indicate that a full recalculation is
15710 * needed on the next commit.
15712 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15714 intel_crtc_compute_pixel_rate(crtc_state);
15716 if (dev_priv->display.modeset_calc_cdclk) {
15717 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15718 if (WARN_ON(min_cdclk < 0))
15722 drm_calc_timestamping_constants(&crtc->base,
15723 &crtc_state->base.adjusted_mode);
15724 update_scanline_offset(crtc);
15727 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15728 dev_priv->min_voltage_level[crtc->pipe] =
15729 crtc_state->min_voltage_level;
15731 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15736 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15738 struct intel_encoder *encoder;
15740 for_each_intel_encoder(&dev_priv->drm, encoder) {
15742 enum intel_display_power_domain domain;
15743 struct intel_crtc_state *crtc_state;
15745 if (!encoder->get_power_domains)
15749 * MST-primary and inactive encoders don't have a crtc state
15750 * and neither of these require any power domain references.
15752 if (!encoder->base.crtc)
15755 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
15756 get_domains = encoder->get_power_domains(encoder, crtc_state);
15757 for_each_power_domain(domain, get_domains)
15758 intel_display_power_get(dev_priv, domain);
15762 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15764 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15765 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15766 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15769 if (IS_HASWELL(dev_priv)) {
15771 * WaRsPkgCStateDisplayPMReq:hsw
15772 * System hang if this isn't done before disabling all planes!
15774 I915_WRITE(CHICKEN_PAR1_1,
15775 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15779 /* Scan out the current hw modeset state,
15780 * and sanitizes it to the current state
15783 intel_modeset_setup_hw_state(struct drm_device *dev,
15784 struct drm_modeset_acquire_ctx *ctx)
15786 struct drm_i915_private *dev_priv = to_i915(dev);
15788 struct intel_crtc *crtc;
15789 struct intel_encoder *encoder;
15792 intel_early_display_was(dev_priv);
15793 intel_modeset_readout_hw_state(dev);
15795 /* HW state is read out, now we need to sanitize this mess. */
15796 get_encoder_power_domains(dev_priv);
15798 intel_sanitize_plane_mapping(dev_priv);
15800 for_each_intel_encoder(dev, encoder) {
15801 intel_sanitize_encoder(encoder);
15804 for_each_pipe(dev_priv, pipe) {
15805 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15807 intel_sanitize_crtc(crtc, ctx);
15808 intel_dump_pipe_config(crtc, crtc->config,
15809 "[setup_hw_state]");
15812 intel_modeset_update_connector_atomic_state(dev);
15814 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15815 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15817 if (!pll->on || pll->active_mask)
15820 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15823 pll->info->funcs->disable(dev_priv, pll);
15827 if (IS_G4X(dev_priv)) {
15828 g4x_wm_get_hw_state(dev);
15829 g4x_wm_sanitize(dev_priv);
15830 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15831 vlv_wm_get_hw_state(dev);
15832 vlv_wm_sanitize(dev_priv);
15833 } else if (INTEL_GEN(dev_priv) >= 9) {
15834 skl_wm_get_hw_state(dev);
15835 } else if (HAS_PCH_SPLIT(dev_priv)) {
15836 ilk_wm_get_hw_state(dev);
15839 for_each_intel_crtc(dev, crtc) {
15842 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15843 if (WARN_ON(put_domains))
15844 modeset_put_power_domains(dev_priv, put_domains);
15846 intel_display_set_init_power(dev_priv, false);
15848 intel_power_domains_verify_state(dev_priv);
15850 intel_fbc_init_pipe_state(dev_priv);
15853 void intel_display_resume(struct drm_device *dev)
15855 struct drm_i915_private *dev_priv = to_i915(dev);
15856 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15857 struct drm_modeset_acquire_ctx ctx;
15860 dev_priv->modeset_restore_state = NULL;
15862 state->acquire_ctx = &ctx;
15864 drm_modeset_acquire_init(&ctx, 0);
15867 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15868 if (ret != -EDEADLK)
15871 drm_modeset_backoff(&ctx);
15875 ret = __intel_display_resume(dev, state, &ctx);
15877 intel_enable_ipc(dev_priv);
15878 drm_modeset_drop_locks(&ctx);
15879 drm_modeset_acquire_fini(&ctx);
15882 DRM_ERROR("Restoring old state failed with %i\n", ret);
15884 drm_atomic_state_put(state);
15887 int intel_connector_register(struct drm_connector *connector)
15889 struct intel_connector *intel_connector = to_intel_connector(connector);
15892 ret = intel_backlight_device_register(intel_connector);
15902 void intel_connector_unregister(struct drm_connector *connector)
15904 struct intel_connector *intel_connector = to_intel_connector(connector);
15906 intel_backlight_device_unregister(intel_connector);
15907 intel_panel_destroy_backlight(connector);
15910 static void intel_hpd_poll_fini(struct drm_device *dev)
15912 struct intel_connector *connector;
15913 struct drm_connector_list_iter conn_iter;
15915 /* Kill all the work that may have been queued by hpd. */
15916 drm_connector_list_iter_begin(dev, &conn_iter);
15917 for_each_intel_connector_iter(connector, &conn_iter) {
15918 if (connector->modeset_retry_work.func)
15919 cancel_work_sync(&connector->modeset_retry_work);
15920 if (connector->hdcp_shim) {
15921 cancel_delayed_work_sync(&connector->hdcp_check_work);
15922 cancel_work_sync(&connector->hdcp_prop_work);
15925 drm_connector_list_iter_end(&conn_iter);
15928 void intel_modeset_cleanup(struct drm_device *dev)
15930 struct drm_i915_private *dev_priv = to_i915(dev);
15932 flush_workqueue(dev_priv->modeset_wq);
15934 flush_work(&dev_priv->atomic_helper.free_work);
15935 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15937 intel_disable_gt_powersave(dev_priv);
15940 * Interrupts and polling as the first thing to avoid creating havoc.
15941 * Too much stuff here (turning of connectors, ...) would
15942 * experience fancy races otherwise.
15944 intel_irq_uninstall(dev_priv);
15947 * Due to the hpd irq storm handling the hotplug work can re-arm the
15948 * poll handlers. Hence disable polling after hpd handling is shut down.
15950 intel_hpd_poll_fini(dev);
15952 /* poll work can call into fbdev, hence clean that up afterwards */
15953 intel_fbdev_fini(dev_priv);
15955 intel_unregister_dsm_handler();
15957 intel_fbc_global_disable(dev_priv);
15959 /* flush any delayed tasks or pending work */
15960 flush_scheduled_work();
15962 drm_mode_config_cleanup(dev);
15964 intel_cleanup_overlay(dev_priv);
15966 intel_cleanup_gt_powersave(dev_priv);
15968 intel_teardown_gmbus(dev_priv);
15970 destroy_workqueue(dev_priv->modeset_wq);
15973 void intel_connector_attach_encoder(struct intel_connector *connector,
15974 struct intel_encoder *encoder)
15976 connector->encoder = encoder;
15977 drm_connector_attach_encoder(&connector->base, &encoder->base);
15981 * set vga decode state - true == enable VGA decode
15983 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15985 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15988 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15989 DRM_ERROR("failed to read control word\n");
15993 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15997 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15999 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16001 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16002 DRM_ERROR("failed to write control word\n");
16009 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
16011 struct intel_display_error_state {
16013 u32 power_well_driver;
16015 int num_transcoders;
16017 struct intel_cursor_error_state {
16022 } cursor[I915_MAX_PIPES];
16024 struct intel_pipe_error_state {
16025 bool power_domain_on;
16028 } pipe[I915_MAX_PIPES];
16030 struct intel_plane_error_state {
16038 } plane[I915_MAX_PIPES];
16040 struct intel_transcoder_error_state {
16041 bool power_domain_on;
16042 enum transcoder cpu_transcoder;
16055 struct intel_display_error_state *
16056 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16058 struct intel_display_error_state *error;
16059 int transcoders[] = {
16067 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16070 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16074 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16075 error->power_well_driver =
16076 I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
16078 for_each_pipe(dev_priv, i) {
16079 error->pipe[i].power_domain_on =
16080 __intel_display_power_is_enabled(dev_priv,
16081 POWER_DOMAIN_PIPE(i));
16082 if (!error->pipe[i].power_domain_on)
16085 error->cursor[i].control = I915_READ(CURCNTR(i));
16086 error->cursor[i].position = I915_READ(CURPOS(i));
16087 error->cursor[i].base = I915_READ(CURBASE(i));
16089 error->plane[i].control = I915_READ(DSPCNTR(i));
16090 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16091 if (INTEL_GEN(dev_priv) <= 3) {
16092 error->plane[i].size = I915_READ(DSPSIZE(i));
16093 error->plane[i].pos = I915_READ(DSPPOS(i));
16095 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16096 error->plane[i].addr = I915_READ(DSPADDR(i));
16097 if (INTEL_GEN(dev_priv) >= 4) {
16098 error->plane[i].surface = I915_READ(DSPSURF(i));
16099 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16102 error->pipe[i].source = I915_READ(PIPESRC(i));
16104 if (HAS_GMCH_DISPLAY(dev_priv))
16105 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16108 /* Note: this does not include DSI transcoders. */
16109 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16110 if (HAS_DDI(dev_priv))
16111 error->num_transcoders++; /* Account for eDP. */
16113 for (i = 0; i < error->num_transcoders; i++) {
16114 enum transcoder cpu_transcoder = transcoders[i];
16116 error->transcoder[i].power_domain_on =
16117 __intel_display_power_is_enabled(dev_priv,
16118 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16119 if (!error->transcoder[i].power_domain_on)
16122 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16124 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16125 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16126 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16127 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16128 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16129 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16130 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16136 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16139 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16140 struct intel_display_error_state *error)
16142 struct drm_i915_private *dev_priv = m->i915;
16148 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
16149 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16150 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16151 error->power_well_driver);
16152 for_each_pipe(dev_priv, i) {
16153 err_printf(m, "Pipe [%d]:\n", i);
16154 err_printf(m, " Power: %s\n",
16155 onoff(error->pipe[i].power_domain_on));
16156 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16157 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16159 err_printf(m, "Plane [%d]:\n", i);
16160 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16161 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16162 if (INTEL_GEN(dev_priv) <= 3) {
16163 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16164 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16166 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16167 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16168 if (INTEL_GEN(dev_priv) >= 4) {
16169 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16170 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16173 err_printf(m, "Cursor [%d]:\n", i);
16174 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16175 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16176 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16179 for (i = 0; i < error->num_transcoders; i++) {
16180 err_printf(m, "CPU transcoder: %s\n",
16181 transcoder_name(error->transcoder[i].cpu_transcoder));
16182 err_printf(m, " Power: %s\n",
16183 onoff(error->transcoder[i].power_domain_on));
16184 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16185 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16186 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16187 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16188 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16189 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16190 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);