drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_dmabuf.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct drm_device *dev,
 101                                   struct intel_framebuffer *ifb,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd,
 103                                   struct drm_i915_gem_object *obj);
 104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 108                                          struct intel_link_m_n *m_n,
 109                                          struct intel_link_m_n *m2_n2);
 110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 113 static void vlv_prepare_pll(struct intel_crtc *crtc,
 114                             const struct intel_crtc_state *pipe_config);
 115 static void chv_prepare_pll(struct intel_crtc *crtc,
 116                             const struct intel_crtc_state *pipe_config);
 117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 120         struct intel_crtc_state *crtc_state);
 121 static void skylake_pfit_enable(struct intel_crtc *crtc);
 122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 127 static int bxt_calc_cdclk(int max_pixclk);
 128
 129 struct intel_limit {
 130         struct {
 131                 int min, max;
 132         } dot, vco, n, m, m1, m2, p, p1;
 133
 134         struct {
 135                 int dot_limit;
 136                 int p2_slow, p2_fast;
 137         } p2;
 138 };
 139
 140 /* returns HPLL frequency in kHz */
 141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 142 {
 143         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 144
 145         /* Obtain SKU information */
 146         mutex_lock(&dev_priv->sb_lock);
 147         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 148                 CCK_FUSE_HPLL_FREQ_MASK;
 149         mutex_unlock(&dev_priv->sb_lock);
 150
 151         return vco_freq[hpll_freq] * 1000;
 152 }
 153
 154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 155                       const char *name, u32 reg, int ref_freq)
 156 {
 157         u32 val;
 158         int divider;
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 171 }
 172
 173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 174                                   const char *name, u32 reg)
 175 {
 176         if (dev_priv->hpll_freq == 0)
 177                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 178
 179         return vlv_get_cck_clock(dev_priv, name, reg,
 180                                  dev_priv->hpll_freq);
 181 }
 182
 183 static int
 184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 185 {
 186         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 187 }
 188
 189 static int
 190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 191 {
 192         /* RAWCLK_FREQ_VLV register updated from power well code */
 193         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 194                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 195 }
 196
 197 static int
 198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 199 {
 200         uint32_t clkcfg;
 201
 202         /* hrawclock is 1/4 the FSB frequency */
 203         clkcfg = I915_READ(CLKCFG);
 204         switch (clkcfg & CLKCFG_FSB_MASK) {
 205         case CLKCFG_FSB_400:
 206                 return 100000;
 207         case CLKCFG_FSB_533:
 208                 return 133333;
 209         case CLKCFG_FSB_667:
 210                 return 166667;
 211         case CLKCFG_FSB_800:
 212                 return 200000;
 213         case CLKCFG_FSB_1067:
 214                 return 266667;
 215         case CLKCFG_FSB_1333:
 216                 return 333333;
 217         /* these two are just a guess; one of them might be right */
 218         case CLKCFG_FSB_1600:
 219         case CLKCFG_FSB_1600_ALT:
 220                 return 400000;
 221         default:
 222                 return 133333;
 223         }
 224 }
 225
 226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 227 {
 228         if (HAS_PCH_SPLIT(dev_priv))
 229                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 230         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 231                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 232         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 233                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 234         else
 235                 return; /* no rawclk on other platforms, or no need to know it */
 236
 237         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 238 }
 239
 240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 241 {
 242         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 243                 return;
 244
 245         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 246                                                       CCK_CZ_CLOCK_CONTROL);
 247
 248         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 249 }
 250
 251 static inline u32 /* units of 100MHz */
 252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 253                     const struct intel_crtc_state *pipe_config)
 254 {
 255         if (HAS_DDI(dev_priv))
 256                 return pipe_config->port_clock; /* SPLL */
 257         else if (IS_GEN5(dev_priv))
 258                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 259         else
 260                 return 270000;
 261 }
 262
 263 static const struct intel_limit intel_limits_i8xx_dac = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 2, .max = 33 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 4, .p2_fast = 2 },
 274 };
 275
 276 static const struct intel_limit intel_limits_i8xx_dvo = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 908000, .max = 1512000 },
 279         .n = { .min = 2, .max = 16 },
 280         .m = { .min = 96, .max = 140 },
 281         .m1 = { .min = 18, .max = 26 },
 282         .m2 = { .min = 6, .max = 16 },
 283         .p = { .min = 4, .max = 128 },
 284         .p1 = { .min = 2, .max = 33 },
 285         .p2 = { .dot_limit = 165000,
 286                 .p2_slow = 4, .p2_fast = 4 },
 287 };
 288
 289 static const struct intel_limit intel_limits_i8xx_lvds = {
 290         .dot = { .min = 25000, .max = 350000 },
 291         .vco = { .min = 908000, .max = 1512000 },
 292         .n = { .min = 2, .max = 16 },
 293         .m = { .min = 96, .max = 140 },
 294         .m1 = { .min = 18, .max = 26 },
 295         .m2 = { .min = 6, .max = 16 },
 296         .p = { .min = 4, .max = 128 },
 297         .p1 = { .min = 1, .max = 6 },
 298         .p2 = { .dot_limit = 165000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302 static const struct intel_limit intel_limits_i9xx_sdvo = {
 303         .dot = { .min = 20000, .max = 400000 },
 304         .vco = { .min = 1400000, .max = 2800000 },
 305         .n = { .min = 1, .max = 6 },
 306         .m = { .min = 70, .max = 120 },
 307         .m1 = { .min = 8, .max = 18 },
 308         .m2 = { .min = 3, .max = 7 },
 309         .p = { .min = 5, .max = 80 },
 310         .p1 = { .min = 1, .max = 8 },
 311         .p2 = { .dot_limit = 200000,
 312                 .p2_slow = 10, .p2_fast = 5 },
 313 };
 314
 315 static const struct intel_limit intel_limits_i9xx_lvds = {
 316         .dot = { .min = 20000, .max = 400000 },
 317         .vco = { .min = 1400000, .max = 2800000 },
 318         .n = { .min = 1, .max = 6 },
 319         .m = { .min = 70, .max = 120 },
 320         .m1 = { .min = 8, .max = 18 },
 321         .m2 = { .min = 3, .max = 7 },
 322         .p = { .min = 7, .max = 98 },
 323         .p1 = { .min = 1, .max = 8 },
 324         .p2 = { .dot_limit = 112000,
 325                 .p2_slow = 14, .p2_fast = 7 },
 326 };
 327
 328
 329 static const struct intel_limit intel_limits_g4x_sdvo = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 1750000, .max = 3500000},
 332         .n = { .min = 1, .max = 4 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 1, .max = 3},
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 10,
 340                 .p2_fast = 10
 341         },
 342 };
 343
 344 static const struct intel_limit intel_limits_g4x_hdmi = {
 345         .dot = { .min = 22000, .max = 400000 },
 346         .vco = { .min = 1750000, .max = 3500000},
 347         .n = { .min = 1, .max = 4 },
 348         .m = { .min = 104, .max = 138 },
 349         .m1 = { .min = 16, .max = 23 },
 350         .m2 = { .min = 5, .max = 11 },
 351         .p = { .min = 5, .max = 80 },
 352         .p1 = { .min = 1, .max = 8},
 353         .p2 = { .dot_limit = 165000,
 354                 .p2_slow = 10, .p2_fast = 5 },
 355 };
 356
 357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 358         .dot = { .min = 20000, .max = 115000 },
 359         .vco = { .min = 1750000, .max = 3500000 },
 360         .n = { .min = 1, .max = 3 },
 361         .m = { .min = 104, .max = 138 },
 362         .m1 = { .min = 17, .max = 23 },
 363         .m2 = { .min = 5, .max = 11 },
 364         .p = { .min = 28, .max = 112 },
 365         .p1 = { .min = 2, .max = 8 },
 366         .p2 = { .dot_limit = 0,
 367                 .p2_slow = 14, .p2_fast = 14
 368         },
 369 };
 370
 371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 372         .dot = { .min = 80000, .max = 224000 },
 373         .vco = { .min = 1750000, .max = 3500000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 104, .max = 138 },
 376         .m1 = { .min = 17, .max = 23 },
 377         .m2 = { .min = 5, .max = 11 },
 378         .p = { .min = 14, .max = 42 },
 379         .p1 = { .min = 2, .max = 6 },
 380         .p2 = { .dot_limit = 0,
 381                 .p2_slow = 7, .p2_fast = 7
 382         },
 383 };
 384
 385 static const struct intel_limit intel_limits_pineview_sdvo = {
 386         .dot = { .min = 20000, .max = 400000},
 387         .vco = { .min = 1700000, .max = 3500000 },
 388         /* Pineview's Ncounter is a ring counter */
 389         .n = { .min = 3, .max = 6 },
 390         .m = { .min = 2, .max = 256 },
 391         /* Pineview only has one combined m divider, which we treat as m2. */
 392         .m1 = { .min = 0, .max = 0 },
 393         .m2 = { .min = 0, .max = 254 },
 394         .p = { .min = 5, .max = 80 },
 395         .p1 = { .min = 1, .max = 8 },
 396         .p2 = { .dot_limit = 200000,
 397                 .p2_slow = 10, .p2_fast = 5 },
 398 };
 399
 400 static const struct intel_limit intel_limits_pineview_lvds = {
 401         .dot = { .min = 20000, .max = 400000 },
 402         .vco = { .min = 1700000, .max = 3500000 },
 403         .n = { .min = 3, .max = 6 },
 404         .m = { .min = 2, .max = 256 },
 405         .m1 = { .min = 0, .max = 0 },
 406         .m2 = { .min = 0, .max = 254 },
 407         .p = { .min = 7, .max = 112 },
 408         .p1 = { .min = 1, .max = 8 },
 409         .p2 = { .dot_limit = 112000,
 410                 .p2_slow = 14, .p2_fast = 14 },
 411 };
 412
 413 /* Ironlake / Sandybridge
 414  *
 415  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 416  * the range value for them is (actual_value - 2).
 417  */
 418 static const struct intel_limit intel_limits_ironlake_dac = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 5 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 5, .max = 80 },
 426         .p1 = { .min = 1, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 10, .p2_fast = 5 },
 429 };
 430
 431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 432         .dot = { .min = 25000, .max = 350000 },
 433         .vco = { .min = 1760000, .max = 3510000 },
 434         .n = { .min = 1, .max = 3 },
 435         .m = { .min = 79, .max = 118 },
 436         .m1 = { .min = 12, .max = 22 },
 437         .m2 = { .min = 5, .max = 9 },
 438         .p = { .min = 28, .max = 112 },
 439         .p1 = { .min = 2, .max = 8 },
 440         .p2 = { .dot_limit = 225000,
 441                 .p2_slow = 14, .p2_fast = 14 },
 442 };
 443
 444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 445         .dot = { .min = 25000, .max = 350000 },
 446         .vco = { .min = 1760000, .max = 3510000 },
 447         .n = { .min = 1, .max = 3 },
 448         .m = { .min = 79, .max = 127 },
 449         .m1 = { .min = 12, .max = 22 },
 450         .m2 = { .min = 5, .max = 9 },
 451         .p = { .min = 14, .max = 56 },
 452         .p1 = { .min = 2, .max = 8 },
 453         .p2 = { .dot_limit = 225000,
 454                 .p2_slow = 7, .p2_fast = 7 },
 455 };
 456
 457 /* LVDS 100mhz refclk limits. */
 458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 459         .dot = { .min = 25000, .max = 350000 },
 460         .vco = { .min = 1760000, .max = 3510000 },
 461         .n = { .min = 1, .max = 2 },
 462         .m = { .min = 79, .max = 126 },
 463         .m1 = { .min = 12, .max = 22 },
 464         .m2 = { .min = 5, .max = 9 },
 465         .p = { .min = 28, .max = 112 },
 466         .p1 = { .min = 2, .max = 8 },
 467         .p2 = { .dot_limit = 225000,
 468                 .p2_slow = 14, .p2_fast = 14 },
 469 };
 470
 471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 472         .dot = { .min = 25000, .max = 350000 },
 473         .vco = { .min = 1760000, .max = 3510000 },
 474         .n = { .min = 1, .max = 3 },
 475         .m = { .min = 79, .max = 126 },
 476         .m1 = { .min = 12, .max = 22 },
 477         .m2 = { .min = 5, .max = 9 },
 478         .p = { .min = 14, .max = 42 },
 479         .p1 = { .min = 2, .max = 6 },
 480         .p2 = { .dot_limit = 225000,
 481                 .p2_slow = 7, .p2_fast = 7 },
 482 };
 483
 484 static const struct intel_limit intel_limits_vlv = {
 485          /*
 486           * These are the data rate limits (measured in fast clocks)
 487           * since those are the strictest limits we have. The fast
 488           * clock and actual rate limits are more relaxed, so checking
 489           * them would make no difference.
 490           */
 491         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 492         .vco = { .min = 4000000, .max = 6000000 },
 493         .n = { .min = 1, .max = 7 },
 494         .m1 = { .min = 2, .max = 3 },
 495         .m2 = { .min = 11, .max = 156 },
 496         .p1 = { .min = 2, .max = 3 },
 497         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 498 };
 499
 500 static const struct intel_limit intel_limits_chv = {
 501         /*
 502          * These are the data rate limits (measured in fast clocks)
 503          * since those are the strictest limits we have.  The fast
 504          * clock and actual rate limits are more relaxed, so checking
 505          * them would make no difference.
 506          */
 507         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 508         .vco = { .min = 4800000, .max = 6480000 },
 509         .n = { .min = 1, .max = 1 },
 510         .m1 = { .min = 2, .max = 2 },
 511         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 514 };
 515
 516 static const struct intel_limit intel_limits_bxt = {
 517         /* FIXME: find real dot limits */
 518         .dot = { .min = 0, .max = INT_MAX },
 519         .vco = { .min = 4800000, .max = 6700000 },
 520         .n = { .min = 1, .max = 1 },
 521         .m1 = { .min = 2, .max = 2 },
 522         /* FIXME: find real m2 limits */
 523         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 524         .p1 = { .min = 2, .max = 4 },
 525         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 526 };
 527
 528 static bool
 529 needs_modeset(struct drm_crtc_state *state)
 530 {
 531         return drm_atomic_crtc_needs_modeset(state);
 532 }
 533
 534 /*
 535  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 536  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 537  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 538  * The helpers' return value is the rate of the clock that is fed to the
 539  * display engine's pipe which can be the above fast dot clock rate or a
 540  * divided-down version of it.
 541  */
 542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 544 {
 545         clock->m = clock->m2 + 2;
 546         clock->p = clock->p1 * clock->p2;
 547         if (WARN_ON(clock->n == 0 || clock->p == 0))
 548                 return 0;
 549         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 550         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 551
 552         return clock->dot;
 553 }
 554
 555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 556 {
 557         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 558 }
 559
 560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 561 {
 562         clock->m = i9xx_dpll_compute_m(clock);
 563         clock->p = clock->p1 * clock->p2;
 564         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 565                 return 0;
 566         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 567         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 568
 569         return clock->dot;
 570 }
 571
 572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 573 {
 574         clock->m = clock->m1 * clock->m2;
 575         clock->p = clock->p1 * clock->p2;
 576         if (WARN_ON(clock->n == 0 || clock->p == 0))
 577                 return 0;
 578         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 579         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 580
 581         return clock->dot / 5;
 582 }
 583
 584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 585 {
 586         clock->m = clock->m1 * clock->m2;
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n == 0 || clock->p == 0))
 589                 return 0;
 590         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 591                         clock->n << 22);
 592         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 593
 594         return clock->dot / 5;
 595 }
 596
 597 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 598 /**
 599  * Returns whether the given set of divisors are valid for a given refclk with
 600  * the given connectors.
 601  */
 602
 603 static bool intel_PLL_is_valid(struct drm_device *dev,
 604                                const struct intel_limit *limit,
 605                                const struct dpll *clock)
 606 {
 607         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 608                 INTELPllInvalid("n out of range\n");
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 612                 INTELPllInvalid("m2 out of range\n");
 613         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 614                 INTELPllInvalid("m1 out of range\n");
 615
 616         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 617             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 618                 if (clock->m1 <= clock->m2)
 619                         INTELPllInvalid("m1 <= m2\n");
 620
 621         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 622                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 623                         INTELPllInvalid("p out of range\n");
 624                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 625                         INTELPllInvalid("m out of range\n");
 626         }
 627
 628         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 629                 INTELPllInvalid("vco out of range\n");
 630         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 631          * connector, etc., rather than just a single range.
 632          */
 633         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 634                 INTELPllInvalid("dot out of range\n");
 635
 636         return true;
 637 }
 638
 639 static int
 640 i9xx_select_p2_div(const struct intel_limit *limit,
 641                    const struct intel_crtc_state *crtc_state,
 642                    int target)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645
 646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 647                 /*
 648                  * For LVDS just rely on its current settings for dual-channel.
 649                  * We haven't figured out how to reliably set up different
 650                  * single/dual channel state, if we even can.
 651                  */
 652                 if (intel_is_dual_link_lvds(dev))
 653                         return limit->p2.p2_fast;
 654                 else
 655                         return limit->p2.p2_slow;
 656         } else {
 657                 if (target < limit->p2.dot_limit)
 658                         return limit->p2.p2_slow;
 659                 else
 660                         return limit->p2.p2_fast;
 661         }
 662 }
 663
 664 /*
 665  * Returns a set of divisors for the desired target clock with the given
 666  * refclk, or FALSE.  The returned values represent the clock equation:
 667  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 668  *
 669  * Target and reference clocks are specified in kHz.
 670  *
 671  * If match_clock is provided, then best_clock P divider must match the P
 672  * divider from @match_clock used for LVDS downclocking.
 673  */
 674 static bool
 675 i9xx_find_best_dpll(const struct intel_limit *limit,
 676                     struct intel_crtc_state *crtc_state,
 677                     int target, int refclk, struct dpll *match_clock,
 678                     struct dpll *best_clock)
 679 {
 680         struct drm_device *dev = crtc_state->base.crtc->dev;
 681         struct dpll clock;
 682         int err = target;
 683
 684         memset(best_clock, 0, sizeof(*best_clock));
 685
 686         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 687
 688         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 689              clock.m1++) {
 690                 for (clock.m2 = limit->m2.min;
 691                      clock.m2 <= limit->m2.max; clock.m2++) {
 692                         if (clock.m2 >= clock.m1)
 693                                 break;
 694                         for (clock.n = limit->n.min;
 695                              clock.n <= limit->n.max; clock.n++) {
 696                                 for (clock.p1 = limit->p1.min;
 697                                         clock.p1 <= limit->p1.max; clock.p1++) {
 698                                         int this_err;
 699
 700                                         i9xx_calc_dpll_params(refclk, &clock);
 701                                         if (!intel_PLL_is_valid(dev, limit,
 702                                                                 &clock))
 703                                                 continue;
 704                                         if (match_clock &&
 705                                             clock.p != match_clock->p)
 706                                                 continue;
 707
 708                                         this_err = abs(clock.dot - target);
 709                                         if (this_err < err) {
 710                                                 *best_clock = clock;
 711                                                 err = this_err;
 712                                         }
 713                                 }
 714                         }
 715                 }
 716         }
 717
 718         return (err != target);
 719 }
 720
 721 /*
 722  * Returns a set of divisors for the desired target clock with the given
 723  * refclk, or FALSE.  The returned values represent the clock equation:
 724  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 725  *
 726  * Target and reference clocks are specified in kHz.
 727  *
 728  * If match_clock is provided, then best_clock P divider must match the P
 729  * divider from @match_clock used for LVDS downclocking.
 730  */
 731 static bool
 732 pnv_find_best_dpll(const struct intel_limit *limit,
 733                    struct intel_crtc_state *crtc_state,
 734                    int target, int refclk, struct dpll *match_clock,
 735                    struct dpll *best_clock)
 736 {
 737         struct drm_device *dev = crtc_state->base.crtc->dev;
 738         struct dpll clock;
 739         int err = target;
 740
 741         memset(best_clock, 0, sizeof(*best_clock));
 742
 743         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 744
 745         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 746              clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      clock.m2 <= limit->m2.max; clock.m2++) {
 749                         for (clock.n = limit->n.min;
 750                              clock.n <= limit->n.max; clock.n++) {
 751                                 for (clock.p1 = limit->p1.min;
 752                                         clock.p1 <= limit->p1.max; clock.p1++) {
 753                                         int this_err;
 754
 755                                         pnv_calc_dpll_params(refclk, &clock);
 756                                         if (!intel_PLL_is_valid(dev, limit,
 757                                                                 &clock))
 758                                                 continue;
 759                                         if (match_clock &&
 760                                             clock.p != match_clock->p)
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return (err != target);
 774 }
 775
 776 /*
 777  * Returns a set of divisors for the desired target clock with the given
 778  * refclk, or FALSE.  The returned values represent the clock equation:
 779  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 780  *
 781  * Target and reference clocks are specified in kHz.
 782  *
 783  * If match_clock is provided, then best_clock P divider must match the P
 784  * divider from @match_clock used for LVDS downclocking.
 785  */
 786 static bool
 787 g4x_find_best_dpll(const struct intel_limit *limit,
 788                    struct intel_crtc_state *crtc_state,
 789                    int target, int refclk, struct dpll *match_clock,
 790                    struct dpll *best_clock)
 791 {
 792         struct drm_device *dev = crtc_state->base.crtc->dev;
 793         struct dpll clock;
 794         int max_n;
 795         bool found = false;
 796         /* approximately equals target * 0.00585 */
 797         int err_most = (target >> 8) + (target >> 9);
 798
 799         memset(best_clock, 0, sizeof(*best_clock));
 800
 801         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 802
 803         max_n = limit->n.max;
 804         /* based on hardware requirement, prefer smaller n to precision */
 805         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 806                 /* based on hardware requirement, prefere larger m1,m2 */
 807                 for (clock.m1 = limit->m1.max;
 808                      clock.m1 >= limit->m1.min; clock.m1--) {
 809                         for (clock.m2 = limit->m2.max;
 810                              clock.m2 >= limit->m2.min; clock.m2--) {
 811                                 for (clock.p1 = limit->p1.max;
 812                                      clock.p1 >= limit->p1.min; clock.p1--) {
 813                                         int this_err;
 814
 815                                         i9xx_calc_dpll_params(refclk, &clock);
 816                                         if (!intel_PLL_is_valid(dev, limit,
 817                                                                 &clock))
 818                                                 continue;
 819
 820                                         this_err = abs(clock.dot - target);
 821                                         if (this_err < err_most) {
 822                                                 *best_clock = clock;
 823                                                 err_most = this_err;
 824                                                 max_n = clock.n;
 825                                                 found = true;
 826                                         }
 827                                 }
 828                         }
 829                 }
 830         }
 831         return found;
 832 }
 833
 834 /*
 835  * Check if the calculated PLL configuration is more optimal compared to the
 836  * best configuration and error found so far. Return the calculated error.
 837  */
 838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 839                                const struct dpll *calculated_clock,
 840                                const struct dpll *best_clock,
 841                                unsigned int best_error_ppm,
 842                                unsigned int *error_ppm)
 843 {
 844         /*
 845          * For CHV ignore the error and consider only the P value.
 846          * Prefer a bigger P value based on HW requirements.
 847          */
 848         if (IS_CHERRYVIEW(dev)) {
 849                 *error_ppm = 0;
 850
 851                 return calculated_clock->p > best_clock->p;
 852         }
 853
 854         if (WARN_ON_ONCE(!target_freq))
 855                 return false;
 856
 857         *error_ppm = div_u64(1000000ULL *
 858                                 abs(target_freq - calculated_clock->dot),
 859                              target_freq);
 860         /*
 861          * Prefer a better P value over a better (smaller) error if the error
 862          * is small. Ensure this preference for future configurations too by
 863          * setting the error to 0.
 864          */
 865         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 866                 *error_ppm = 0;
 867
 868                 return true;
 869         }
 870
 871         return *error_ppm + 10 < best_error_ppm;
 872 }
 873
 874 /*
 875  * Returns a set of divisors for the desired target clock with the given
 876  * refclk, or FALSE.  The returned values represent the clock equation:
 877  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 878  */
 879 static bool
 880 vlv_find_best_dpll(const struct intel_limit *limit,
 881                    struct intel_crtc_state *crtc_state,
 882                    int target, int refclk, struct dpll *match_clock,
 883                    struct dpll *best_clock)
 884 {
 885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 886         struct drm_device *dev = crtc->base.dev;
 887         struct dpll clock;
 888         unsigned int bestppm = 1000000;
 889         /* min update 19.2 MHz */
 890         int max_n = min(limit->n.max, refclk / 19200);
 891         bool found = false;
 892
 893         target *= 5; /* fast clock */
 894
 895         memset(best_clock, 0, sizeof(*best_clock));
 896
 897         /* based on hardware requirement, prefer smaller n to precision */
 898         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 899                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 900                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 901                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 902                                 clock.p = clock.p1 * clock.p2;
 903                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 904                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 905                                         unsigned int ppm;
 906
 907                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 908                                                                      refclk * clock.m1);
 909
 910                                         vlv_calc_dpll_params(refclk, &clock);
 911
 912                                         if (!intel_PLL_is_valid(dev, limit,
 913                                                                 &clock))
 914                                                 continue;
 915
 916                                         if (!vlv_PLL_is_optimal(dev, target,
 917                                                                 &clock,
 918                                                                 best_clock,
 919                                                                 bestppm, &ppm))
 920                                                 continue;
 921
 922                                         *best_clock = clock;
 923                                         bestppm = ppm;
 924                                         found = true;
 925                                 }
 926                         }
 927                 }
 928         }
 929
 930         return found;
 931 }
 932
 933 /*
 934  * Returns a set of divisors for the desired target clock with the given
 935  * refclk, or FALSE.  The returned values represent the clock equation:
 936  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 937  */
 938 static bool
 939 chv_find_best_dpll(const struct intel_limit *limit,
 940                    struct intel_crtc_state *crtc_state,
 941                    int target, int refclk, struct dpll *match_clock,
 942                    struct dpll *best_clock)
 943 {
 944         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 945         struct drm_device *dev = crtc->base.dev;
 946         unsigned int best_error_ppm;
 947         struct dpll clock;
 948         uint64_t m2;
 949         int found = false;
 950
 951         memset(best_clock, 0, sizeof(*best_clock));
 952         best_error_ppm = 1000000;
 953
 954         /*
 955          * Based on hardware doc, the n always set to 1, and m1 always
 956          * set to 2.  If requires to support 200Mhz refclk, we need to
 957          * revisit this because n may not 1 anymore.
 958          */
 959         clock.n = 1, clock.m1 = 2;
 960         target *= 5;    /* fast clock */
 961
 962         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 963                 for (clock.p2 = limit->p2.p2_fast;
 964                                 clock.p2 >= limit->p2.p2_slow;
 965                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 966                         unsigned int error_ppm;
 967
 968                         clock.p = clock.p1 * clock.p2;
 969
 970                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 971                                         clock.n) << 22, refclk * clock.m1);
 972
 973                         if (m2 > INT_MAX/clock.m1)
 974                                 continue;
 975
 976                         clock.m2 = m2;
 977
 978                         chv_calc_dpll_params(refclk, &clock);
 979
 980                         if (!intel_PLL_is_valid(dev, limit, &clock))
 981                                 continue;
 982
 983                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 984                                                 best_error_ppm, &error_ppm))
 985                                 continue;
 986
 987                         *best_clock = clock;
 988                         best_error_ppm = error_ppm;
 989                         found = true;
 990                 }
 991         }
 992
 993         return found;
 994 }
 995
 996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 997                         struct dpll *best_clock)
 998 {
 999         int refclk = 100000;
1000         const struct intel_limit *limit = &intel_limits_bxt;
1001
1002         return chv_find_best_dpll(limit, crtc_state,
1003                                   target_clock, refclk, NULL, best_clock);
1004 }
1005
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1007 {
1008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
1010         /* Be paranoid as we can arrive here with only partial
1011          * state retrieved from the hardware during setup.
1012          *
1013          * We can ditch the adjusted_mode.crtc_clock check as soon
1014          * as Haswell has gained clock readout/fastboot support.
1015          *
1016          * We can ditch the crtc->primary->fb check as soon as we can
1017          * properly reconstruct framebuffers.
1018          *
1019          * FIXME: The intel_crtc->active here should be switched to
1020          * crtc->state->active once we have proper CRTC states wired up
1021          * for atomic.
1022          */
1023         return intel_crtc->active && crtc->primary->state->fb &&
1024                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1025 }
1026
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe)
1029 {
1030         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1032
1033         return intel_crtc->config->cpu_transcoder;
1034 }
1035
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(dev);
1039         i915_reg_t reg = PIPEDSL(pipe);
1040         u32 line1, line2;
1041         u32 line_mask;
1042
1043         if (IS_GEN2(dev))
1044                 line_mask = DSL_LINEMASK_GEN2;
1045         else
1046                 line_mask = DSL_LINEMASK_GEN3;
1047
1048         line1 = I915_READ(reg) & line_mask;
1049         msleep(5);
1050         line2 = I915_READ(reg) & line_mask;
1051
1052         return line1 == line2;
1053 }
1054
1055 /*
1056  * intel_wait_for_pipe_off - wait for pipe to turn off
1057  * @crtc: crtc whose pipe to wait for
1058  *
1059  * After disabling a pipe, we can't wait for vblank in the usual way,
1060  * spinning on the vblank interrupt status bit, since we won't actually
1061  * see an interrupt when the pipe is disabled.
1062  *
1063  * On Gen4 and above:
1064  *   wait for the pipe register state bit to turn off
1065  *
1066  * Otherwise:
1067  *   wait for the display line value to settle (it usually
1068  *   ends up stopping at the start of the next frame).
1069  *
1070  */
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1072 {
1073         struct drm_device *dev = crtc->base.dev;
1074         struct drm_i915_private *dev_priv = to_i915(dev);
1075         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076         enum pipe pipe = crtc->pipe;
1077
1078         if (INTEL_INFO(dev)->gen >= 4) {
1079                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1080
1081                 /* Wait for the Pipe State to go off */
1082                 if (intel_wait_for_register(dev_priv,
1083                                             reg, I965_PIPECONF_ACTIVE, 0,
1084                                             100))
1085                         WARN(1, "pipe_off wait timed out\n");
1086         } else {
1087                 /* Wait for the display line to settle */
1088                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089                         WARN(1, "pipe_off wait timed out\n");
1090         }
1091 }
1092
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095                 enum pipe pipe, bool state)
1096 {
1097         u32 val;
1098         bool cur_state;
1099
1100         val = I915_READ(DPLL(pipe));
1101         cur_state = !!(val & DPLL_VCO_ENABLE);
1102         I915_STATE_WARN(cur_state != state,
1103              "PLL state assertion failure (expected %s, current %s)\n",
1104                         onoff(state), onoff(cur_state));
1105 }
1106
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1109 {
1110         u32 val;
1111         bool cur_state;
1112
1113         mutex_lock(&dev_priv->sb_lock);
1114         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115         mutex_unlock(&dev_priv->sb_lock);
1116
1117         cur_state = val & DSI_PLL_VCO_EN;
1118         I915_STATE_WARN(cur_state != state,
1119              "DSI PLL state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124                           enum pipe pipe, bool state)
1125 {
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (HAS_DDI(dev_priv)) {
1131                 /* DDI does not have a specific FDI_TX register */
1132                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134         } else {
1135                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         I915_STATE_WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140                         onoff(state), onoff(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         u32 val;
1149         bool cur_state;
1150
1151         val = I915_READ(FDI_RX_CTL(pipe));
1152         cur_state = !!(val & FDI_RX_ENABLE);
1153         I915_STATE_WARN(cur_state != state,
1154              "FDI RX state assertion failure (expected %s, current %s)\n",
1155                         onoff(state), onoff(cur_state));
1156 }
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1159
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1161                                       enum pipe pipe)
1162 {
1163         u32 val;
1164
1165         /* ILK FDI PLL is always enabled */
1166         if (IS_GEN5(dev_priv))
1167                 return;
1168
1169         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170         if (HAS_DDI(dev_priv))
1171                 return;
1172
1173         val = I915_READ(FDI_TX_CTL(pipe));
1174         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178                        enum pipe pipe, bool state)
1179 {
1180         u32 val;
1181         bool cur_state;
1182
1183         val = I915_READ(FDI_RX_CTL(pipe));
1184         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185         I915_STATE_WARN(cur_state != state,
1186              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187                         onoff(state), onoff(cur_state));
1188 }
1189
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                            enum pipe pipe)
1192 {
1193         struct drm_device *dev = &dev_priv->drm;
1194         i915_reg_t pp_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (WARN_ON(HAS_DDI(dev)))
1200                 return;
1201
1202         if (HAS_PCH_SPLIT(dev)) {
1203                 u32 port_sel;
1204
1205                 pp_reg = PP_CONTROL(0);
1206                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1207
1208                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210                         panel_pipe = PIPE_B;
1211                 /* XXX: else fix for eDP */
1212         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213                 /* presumably write lock depends on pipe, not port select */
1214                 pp_reg = PP_CONTROL(pipe);
1215                 panel_pipe = pipe;
1216         } else {
1217                 pp_reg = PP_CONTROL(0);
1218                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219                         panel_pipe = PIPE_B;
1220         }
1221
1222         val = I915_READ(pp_reg);
1223         if (!(val & PANEL_POWER_ON) ||
1224             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1225                 locked = false;
1226
1227         I915_STATE_WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233                           enum pipe pipe, bool state)
1234 {
1235         struct drm_device *dev = &dev_priv->drm;
1236         bool cur_state;
1237
1238         if (IS_845G(dev) || IS_I865G(dev))
1239                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1240         else
1241                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1242
1243         I915_STATE_WARN(cur_state != state,
1244              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245                         pipe_name(pipe), onoff(state), onoff(cur_state));
1246 }
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1249
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251                  enum pipe pipe, bool state)
1252 {
1253         bool cur_state;
1254         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1255                                                                       pipe);
1256         enum intel_display_power_domain power_domain;
1257
1258         /* if we need the pipe quirk it must be always on */
1259         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261                 state = true;
1262
1263         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266                 cur_state = !!(val & PIPECONF_ENABLE);
1267
1268                 intel_display_power_put(dev_priv, power_domain);
1269         } else {
1270                 cur_state = false;
1271         }
1272
1273         I915_STATE_WARN(cur_state != state,
1274              "pipe %c assertion failure (expected %s, current %s)\n",
1275                         pipe_name(pipe), onoff(state), onoff(cur_state));
1276 }
1277
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279                          enum plane plane, bool state)
1280 {
1281         u32 val;
1282         bool cur_state;
1283
1284         val = I915_READ(DSPCNTR(plane));
1285         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286         I915_STATE_WARN(cur_state != state,
1287              "plane %c assertion failure (expected %s, current %s)\n",
1288                         plane_name(plane), onoff(state), onoff(cur_state));
1289 }
1290
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1293
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1295                                    enum pipe pipe)
1296 {
1297         struct drm_device *dev = &dev_priv->drm;
1298         int i;
1299
1300         /* Primary planes are fixed to pipes on gen4+ */
1301         if (INTEL_INFO(dev)->gen >= 4) {
1302                 u32 val = I915_READ(DSPCNTR(pipe));
1303                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304                      "plane %c assertion failure, should be disabled but not\n",
1305                      plane_name(pipe));
1306                 return;
1307         }
1308
1309         /* Need to check both planes against the pipe */
1310         for_each_pipe(dev_priv, i) {
1311                 u32 val = I915_READ(DSPCNTR(i));
1312                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313                         DISPPLANE_SEL_PIPE_SHIFT;
1314                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316                      plane_name(i), pipe_name(pipe));
1317         }
1318 }
1319
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1321                                     enum pipe pipe)
1322 {
1323         struct drm_device *dev = &dev_priv->drm;
1324         int sprite;
1325
1326         if (INTEL_INFO(dev)->gen >= 9) {
1327                 for_each_sprite(dev_priv, pipe, sprite) {
1328                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331                              sprite, pipe_name(pipe));
1332                 }
1333         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334                 for_each_sprite(dev_priv, pipe, sprite) {
1335                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1336                         I915_STATE_WARN(val & SP_ENABLE,
1337                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338                              sprite_name(pipe, sprite), pipe_name(pipe));
1339                 }
1340         } else if (INTEL_INFO(dev)->gen >= 7) {
1341                 u32 val = I915_READ(SPRCTL(pipe));
1342                 I915_STATE_WARN(val & SPRITE_ENABLE,
1343                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344                      plane_name(pipe), pipe_name(pipe));
1345         } else if (INTEL_INFO(dev)->gen >= 5) {
1346                 u32 val = I915_READ(DVSCNTR(pipe));
1347                 I915_STATE_WARN(val & DVS_ENABLE,
1348                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349                      plane_name(pipe), pipe_name(pipe));
1350         }
1351 }
1352
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1354 {
1355         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356                 drm_crtc_vblank_put(crtc);
1357 }
1358
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         u32 val;
1363         bool enabled;
1364
1365         val = I915_READ(PCH_TRANSCONF(pipe));
1366         enabled = !!(val & TRANS_ENABLE);
1367         I915_STATE_WARN(enabled,
1368              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1369              pipe_name(pipe));
1370 }
1371
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373                             enum pipe pipe, u32 port_sel, u32 val)
1374 {
1375         if ((val & DP_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv)) {
1379                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381                         return false;
1382         } else if (IS_CHERRYVIEW(dev_priv)) {
1383                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & SDVO_ENABLE) == 0)
1396                 return false;
1397
1398         if (HAS_PCH_CPT(dev_priv)) {
1399                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400                         return false;
1401         } else if (IS_CHERRYVIEW(dev_priv)) {
1402                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403                         return false;
1404         } else {
1405                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406                         return false;
1407         }
1408         return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412                               enum pipe pipe, u32 val)
1413 {
1414         if ((val & LVDS_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419                         return false;
1420         } else {
1421                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422                         return false;
1423         }
1424         return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428                               enum pipe pipe, u32 val)
1429 {
1430         if ((val & ADPA_DAC_ENABLE) == 0)
1431                 return false;
1432         if (HAS_PCH_CPT(dev_priv)) {
1433                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434                         return false;
1435         } else {
1436                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437                         return false;
1438         }
1439         return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443                                    enum pipe pipe, i915_reg_t reg,
1444                                    u32 port_sel)
1445 {
1446         u32 val = I915_READ(reg);
1447         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449              i915_mmio_reg_offset(reg), pipe_name(pipe));
1450
1451         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452              && (val & DP_PIPEB_SELECT),
1453              "IBX PCH dp port still using transcoder B\n");
1454 }
1455
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457                                      enum pipe pipe, i915_reg_t reg)
1458 {
1459         u32 val = I915_READ(reg);
1460         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462              i915_mmio_reg_offset(reg), pipe_name(pipe));
1463
1464         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465              && (val & SDVO_PIPE_B_SELECT),
1466              "IBX PCH hdmi port still using transcoder B\n");
1467 }
1468
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1470                                       enum pipe pipe)
1471 {
1472         u32 val;
1473
1474         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         val = I915_READ(PCH_ADPA);
1479         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480              "PCH VGA enabled on transcoder %c, should be disabled\n",
1481              pipe_name(pipe));
1482
1483         val = I915_READ(PCH_LVDS);
1484         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1486              pipe_name(pipe));
1487
1488         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1491 }
1492
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494                             const struct intel_crtc_state *pipe_config)
1495 {
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         enum pipe pipe = crtc->pipe;
1498
1499         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500         POSTING_READ(DPLL(pipe));
1501         udelay(150);
1502
1503         if (intel_wait_for_register(dev_priv,
1504                                     DPLL(pipe),
1505                                     DPLL_LOCK_VLV,
1506                                     DPLL_LOCK_VLV,
1507                                     1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1509 }
1510
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512                            const struct intel_crtc_state *pipe_config)
1513 {
1514         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515         enum pipe pipe = crtc->pipe;
1516
1517         assert_pipe_disabled(dev_priv, pipe);
1518
1519         /* PLL is protected by panel, make sure we can write it */
1520         assert_panel_unlocked(dev_priv, pipe);
1521
1522         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523                 _vlv_enable_pll(crtc, pipe_config);
1524
1525         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526         POSTING_READ(DPLL_MD(pipe));
1527 }
1528
1529
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531                             const struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534         enum pipe pipe = crtc->pipe;
1535         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1536         u32 tmp;
1537
1538         mutex_lock(&dev_priv->sb_lock);
1539
1540         /* Enable back the 10bit clock to display controller */
1541         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542         tmp |= DPIO_DCLKP_EN;
1543         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1544
1545         mutex_unlock(&dev_priv->sb_lock);
1546
1547         /*
1548          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1549          */
1550         udelay(1);
1551
1552         /* Enable PLL */
1553         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1554
1555         /* Check PLL is locked */
1556         if (intel_wait_for_register(dev_priv,
1557                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1558                                     1))
1559                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1560 }
1561
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563                            const struct intel_crtc_state *pipe_config)
1564 {
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567
1568         assert_pipe_disabled(dev_priv, pipe);
1569
1570         /* PLL is protected by panel, make sure we can write it */
1571         assert_panel_unlocked(dev_priv, pipe);
1572
1573         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574                 _chv_enable_pll(crtc, pipe_config);
1575
1576         if (pipe != PIPE_A) {
1577                 /*
1578                  * WaPixelRepeatModeFixForC0:chv
1579                  *
1580                  * DPLLCMD is AWOL. Use chicken bits to propagate
1581                  * the value from DPLLBMD to either pipe B or C.
1582                  */
1583                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585                 I915_WRITE(CBR4_VLV, 0);
1586                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1587
1588                 /*
1589                  * DPLLB VGA mode also seems to cause problems.
1590                  * We should always have it disabled.
1591                  */
1592                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1593         } else {
1594                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595                 POSTING_READ(DPLL_MD(pipe));
1596         }
1597 }
1598
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1600 {
1601         struct intel_crtc *crtc;
1602         int count = 0;
1603
1604         for_each_intel_crtc(dev, crtc) {
1605                 count += crtc->base.state->active &&
1606                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1607         }
1608
1609         return count;
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614         struct drm_device *dev = crtc->base.dev;
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         i915_reg_t reg = DPLL(crtc->pipe);
1617         u32 dpll = crtc->config->dpll_hw_state.dpll;
1618
1619         assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         /* Enable DVO 2x clock on both PLLs if necessary */
1626         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1627                 /*
1628                  * It appears to be important that we don't enable this
1629                  * for the current pipe before otherwise configuring the
1630                  * PLL. No idea how this should be handled if multiple
1631                  * DVO outputs are enabled simultaneosly.
1632                  */
1633                 dpll |= DPLL_DVO_2X_MODE;
1634                 I915_WRITE(DPLL(!crtc->pipe),
1635                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1636         }
1637
1638         /*
1639          * Apparently we need to have VGA mode enabled prior to changing
1640          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641          * dividers, even though the register value does change.
1642          */
1643         I915_WRITE(reg, 0);
1644
1645         I915_WRITE(reg, dpll);
1646
1647         /* Wait for the clocks to stabilize. */
1648         POSTING_READ(reg);
1649         udelay(150);
1650
1651         if (INTEL_INFO(dev)->gen >= 4) {
1652                 I915_WRITE(DPLL_MD(crtc->pipe),
1653                            crtc->config->dpll_hw_state.dpll_md);
1654         } else {
1655                 /* The pixel multiplier can only be updated once the
1656                  * DPLL is enabled and the clocks are stable.
1657                  *
1658                  * So write it again.
1659                  */
1660                 I915_WRITE(reg, dpll);
1661         }
1662
1663         /* We do this three times for luck */
1664         I915_WRITE(reg, dpll);
1665         POSTING_READ(reg);
1666         udelay(150); /* wait for warmup */
1667         I915_WRITE(reg, dpll);
1668         POSTING_READ(reg);
1669         udelay(150); /* wait for warmup */
1670         I915_WRITE(reg, dpll);
1671         POSTING_READ(reg);
1672         udelay(150); /* wait for warmup */
1673 }
1674
1675 /**
1676  * i9xx_disable_pll - disable a PLL
1677  * @dev_priv: i915 private structure
1678  * @pipe: pipe PLL to disable
1679  *
1680  * Disable the PLL for @pipe, making sure the pipe is off first.
1681  *
1682  * Note!  This is for pre-ILK only.
1683  */
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->base.dev;
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         enum pipe pipe = crtc->pipe;
1689
1690         /* Disable DVO 2x clock on both PLLs if necessary */
1691         if (IS_I830(dev) &&
1692             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693             !intel_num_dvo_pipes(dev)) {
1694                 I915_WRITE(DPLL(PIPE_B),
1695                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696                 I915_WRITE(DPLL(PIPE_A),
1697                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1698         }
1699
1700         /* Don't disable pipe or pipe PLLs if needed */
1701         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1703                 return;
1704
1705         /* Make sure the pipe isn't still relying on us */
1706         assert_pipe_disabled(dev_priv, pipe);
1707
1708         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709         POSTING_READ(DPLL(pipe));
1710 }
1711
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714         u32 val;
1715
1716         /* Make sure the pipe isn't still relying on us */
1717         assert_pipe_disabled(dev_priv, pipe);
1718
1719         val = DPLL_INTEGRATED_REF_CLK_VLV |
1720                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1721         if (pipe != PIPE_A)
1722                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723
1724         I915_WRITE(DPLL(pipe), val);
1725         POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1731         u32 val;
1732
1733         /* Make sure the pipe isn't still relying on us */
1734         assert_pipe_disabled(dev_priv, pipe);
1735
1736         val = DPLL_SSC_REF_CLK_CHV |
1737                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738         if (pipe != PIPE_A)
1739                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
1741         I915_WRITE(DPLL(pipe), val);
1742         POSTING_READ(DPLL(pipe));
1743
1744         mutex_lock(&dev_priv->sb_lock);
1745
1746         /* Disable 10bit clock to display controller */
1747         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748         val &= ~DPIO_DCLKP_EN;
1749         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1750
1751         mutex_unlock(&dev_priv->sb_lock);
1752 }
1753
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755                          struct intel_digital_port *dport,
1756                          unsigned int expected_mask)
1757 {
1758         u32 port_mask;
1759         i915_reg_t dpll_reg;
1760
1761         switch (dport->port) {
1762         case PORT_B:
1763                 port_mask = DPLL_PORTB_READY_MASK;
1764                 dpll_reg = DPLL(0);
1765                 break;
1766         case PORT_C:
1767                 port_mask = DPLL_PORTC_READY_MASK;
1768                 dpll_reg = DPLL(0);
1769                 expected_mask <<= 4;
1770                 break;
1771         case PORT_D:
1772                 port_mask = DPLL_PORTD_READY_MASK;
1773                 dpll_reg = DPIO_PHY_STATUS;
1774                 break;
1775         default:
1776                 BUG();
1777         }
1778
1779         if (intel_wait_for_register(dev_priv,
1780                                     dpll_reg, port_mask, expected_mask,
1781                                     1000))
1782                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1784 }
1785
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1787                                            enum pipe pipe)
1788 {
1789         struct drm_device *dev = &dev_priv->drm;
1790         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1792         i915_reg_t reg;
1793         uint32_t val, pipeconf_val;
1794
1795         /* Make sure PCH DPLL is enabled */
1796         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1797
1798         /* FDI must be feeding us bits for PCH ports */
1799         assert_fdi_tx_enabled(dev_priv, pipe);
1800         assert_fdi_rx_enabled(dev_priv, pipe);
1801
1802         if (HAS_PCH_CPT(dev)) {
1803                 /* Workaround: Set the timing override bit before enabling the
1804                  * pch transcoder. */
1805                 reg = TRANS_CHICKEN2(pipe);
1806                 val = I915_READ(reg);
1807                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808                 I915_WRITE(reg, val);
1809         }
1810
1811         reg = PCH_TRANSCONF(pipe);
1812         val = I915_READ(reg);
1813         pipeconf_val = I915_READ(PIPECONF(pipe));
1814
1815         if (HAS_PCH_IBX(dev_priv)) {
1816                 /*
1817                  * Make the BPC in transcoder be consistent with
1818                  * that in pipeconf reg. For HDMI we must use 8bpc
1819                  * here for both 8bpc and 12bpc.
1820                  */
1821                 val &= ~PIPECONF_BPC_MASK;
1822                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823                         val |= PIPECONF_8BPC;
1824                 else
1825                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1826         }
1827
1828         val &= ~TRANS_INTERLACE_MASK;
1829         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830                 if (HAS_PCH_IBX(dev_priv) &&
1831                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832                         val |= TRANS_LEGACY_INTERLACED_ILK;
1833                 else
1834                         val |= TRANS_INTERLACED;
1835         else
1836                 val |= TRANS_PROGRESSIVE;
1837
1838         I915_WRITE(reg, val | TRANS_ENABLE);
1839         if (intel_wait_for_register(dev_priv,
1840                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1841                                     100))
1842                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1843 }
1844
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846                                       enum transcoder cpu_transcoder)
1847 {
1848         u32 val, pipeconf_val;
1849
1850         /* FDI must be feeding us bits for PCH ports */
1851         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1853
1854         /* Workaround: set timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858
1859         val = TRANS_ENABLE;
1860         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1861
1862         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863             PIPECONF_INTERLACED_ILK)
1864                 val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(LPT_TRANSCONF, val);
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF,
1871                                     TRANS_STATE_ENABLE,
1872                                     TRANS_STATE_ENABLE,
1873                                     100))
1874                 DRM_ERROR("Failed to enable PCH transcoder\n");
1875 }
1876
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1878                                             enum pipe pipe)
1879 {
1880         struct drm_device *dev = &dev_priv->drm;
1881         i915_reg_t reg;
1882         uint32_t val;
1883
1884         /* FDI relies on the transcoder */
1885         assert_fdi_tx_disabled(dev_priv, pipe);
1886         assert_fdi_rx_disabled(dev_priv, pipe);
1887
1888         /* Ports must be off as well */
1889         assert_pch_ports_disabled(dev_priv, pipe);
1890
1891         reg = PCH_TRANSCONF(pipe);
1892         val = I915_READ(reg);
1893         val &= ~TRANS_ENABLE;
1894         I915_WRITE(reg, val);
1895         /* wait for PCH transcoder off, transcoder state */
1896         if (intel_wait_for_register(dev_priv,
1897                                     reg, TRANS_STATE_ENABLE, 0,
1898                                     50))
1899                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1900
1901         if (HAS_PCH_CPT(dev)) {
1902                 /* Workaround: Clear the timing override chicken bit again. */
1903                 reg = TRANS_CHICKEN2(pipe);
1904                 val = I915_READ(reg);
1905                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906                 I915_WRITE(reg, val);
1907         }
1908 }
1909
1910 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1911 {
1912         u32 val;
1913
1914         val = I915_READ(LPT_TRANSCONF);
1915         val &= ~TRANS_ENABLE;
1916         I915_WRITE(LPT_TRANSCONF, val);
1917         /* wait for PCH transcoder off, transcoder state */
1918         if (intel_wait_for_register(dev_priv,
1919                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1920                                     50))
1921                 DRM_ERROR("Failed to disable PCH transcoder\n");
1922
1923         /* Workaround: clear timing override bit. */
1924         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1927 }
1928
1929 /**
1930  * intel_enable_pipe - enable a pipe, asserting requirements
1931  * @crtc: crtc responsible for the pipe
1932  *
1933  * Enable @crtc's pipe, making sure that various hardware specific requirements
1934  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1935  */
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1937 {
1938         struct drm_device *dev = crtc->base.dev;
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940         enum pipe pipe = crtc->pipe;
1941         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942         enum pipe pch_transcoder;
1943         i915_reg_t reg;
1944         u32 val;
1945
1946         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1947
1948         assert_planes_disabled(dev_priv, pipe);
1949         assert_cursor_disabled(dev_priv, pipe);
1950         assert_sprites_disabled(dev_priv, pipe);
1951
1952         if (HAS_PCH_LPT(dev_priv))
1953                 pch_transcoder = TRANSCODER_A;
1954         else
1955                 pch_transcoder = pipe;
1956
1957         /*
1958          * A pipe without a PLL won't actually be able to drive bits from
1959          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1960          * need the check.
1961          */
1962         if (HAS_GMCH_DISPLAY(dev_priv)) {
1963                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964                         assert_dsi_pll_enabled(dev_priv);
1965                 else
1966                         assert_pll_enabled(dev_priv, pipe);
1967         } else {
1968                 if (crtc->config->has_pch_encoder) {
1969                         /* if driving the PCH, we need FDI enabled */
1970                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971                         assert_fdi_tx_pll_enabled(dev_priv,
1972                                                   (enum pipe) cpu_transcoder);
1973                 }
1974                 /* FIXME: assert CPU port conditions for SNB+ */
1975         }
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if (val & PIPECONF_ENABLE) {
1980                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1982                 return;
1983         }
1984
1985         I915_WRITE(reg, val | PIPECONF_ENABLE);
1986         POSTING_READ(reg);
1987
1988         /*
1989          * Until the pipe starts DSL will read as 0, which would cause
1990          * an apparent vblank timestamp jump, which messes up also the
1991          * frame count when it's derived from the timestamps. So let's
1992          * wait for the pipe to start properly before we call
1993          * drm_crtc_vblank_on()
1994          */
1995         if (dev->max_vblank_count == 0 &&
1996             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @crtc: crtc whose pipes is to be disabled
2003  *
2004  * Disable the pipe of @crtc, making sure that various hardware
2005  * specific requirements are met, if applicable, e.g. plane
2006  * disabled, panel fitter off, etc.
2007  *
2008  * Will wait until the pipe has shut down before returning.
2009  */
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2011 {
2012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014         enum pipe pipe = crtc->pipe;
2015         i915_reg_t reg;
2016         u32 val;
2017
2018         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         reg = PIPECONF(cpu_transcoder);
2029         val = I915_READ(reg);
2030         if ((val & PIPECONF_ENABLE) == 0)
2031                 return;
2032
2033         /*
2034          * Double wide has implications for planes
2035          * so best keep it disabled when not needed.
2036          */
2037         if (crtc->config->double_wide)
2038                 val &= ~PIPECONF_DOUBLE_WIDE;
2039
2040         /* Don't disable pipe or pipe PLLs if needed */
2041         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043                 val &= ~PIPECONF_ENABLE;
2044
2045         I915_WRITE(reg, val);
2046         if ((val & PIPECONF_ENABLE) == 0)
2047                 intel_wait_for_pipe_off(crtc);
2048 }
2049
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2051 {
2052         return IS_GEN2(dev_priv) ? 2048 : 4096;
2053 }
2054
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056                                            uint64_t fb_modifier, unsigned int cpp)
2057 {
2058         switch (fb_modifier) {
2059         case DRM_FORMAT_MOD_NONE:
2060                 return cpp;
2061         case I915_FORMAT_MOD_X_TILED:
2062                 if (IS_GEN2(dev_priv))
2063                         return 128;
2064                 else
2065                         return 512;
2066         case I915_FORMAT_MOD_Y_TILED:
2067                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2068                         return 128;
2069                 else
2070                         return 512;
2071         case I915_FORMAT_MOD_Yf_TILED:
2072                 switch (cpp) {
2073                 case 1:
2074                         return 64;
2075                 case 2:
2076                 case 4:
2077                         return 128;
2078                 case 8:
2079                 case 16:
2080                         return 256;
2081                 default:
2082                         MISSING_CASE(cpp);
2083                         return cpp;
2084                 }
2085                 break;
2086         default:
2087                 MISSING_CASE(fb_modifier);
2088                 return cpp;
2089         }
2090 }
2091
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093                                uint64_t fb_modifier, unsigned int cpp)
2094 {
2095         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2096                 return 1;
2097         else
2098                 return intel_tile_size(dev_priv) /
2099                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2100 }
2101
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104                             unsigned int *tile_width,
2105                             unsigned int *tile_height,
2106                             uint64_t fb_modifier,
2107                             unsigned int cpp)
2108 {
2109         unsigned int tile_width_bytes =
2110                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2111
2112         *tile_width = tile_width_bytes / cpp;
2113         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2114 }
2115
2116 unsigned int
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118                       uint32_t pixel_format, uint64_t fb_modifier)
2119 {
2120         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2122
2123         return ALIGN(height, tile_height);
2124 }
2125
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2127 {
2128         unsigned int size = 0;
2129         int i;
2130
2131         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2133
2134         return size;
2135 }
2136
2137 static void
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139                         const struct drm_framebuffer *fb,
2140                         unsigned int rotation)
2141 {
2142         if (intel_rotation_90_or_270(rotation)) {
2143                 *view = i915_ggtt_view_rotated;
2144                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2145         } else {
2146                 *view = i915_ggtt_view_normal;
2147         }
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_INFO(dev_priv)->gen >= 9)
2153                 return 256 * 1024;
2154         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_INFO(dev_priv)->gen >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164                                          uint64_t fb_modifier)
2165 {
2166         switch (fb_modifier) {
2167         case DRM_FORMAT_MOD_NONE:
2168                 return intel_linear_alignment(dev_priv);
2169         case I915_FORMAT_MOD_X_TILED:
2170                 if (INTEL_INFO(dev_priv)->gen >= 9)
2171                         return 256 * 1024;
2172                 return 0;
2173         case I915_FORMAT_MOD_Y_TILED:
2174         case I915_FORMAT_MOD_Yf_TILED:
2175                 return 1 * 1024 * 1024;
2176         default:
2177                 MISSING_CASE(fb_modifier);
2178                 return 0;
2179         }
2180 }
2181
2182 int
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2184                            unsigned int rotation)
2185 {
2186         struct drm_device *dev = fb->dev;
2187         struct drm_i915_private *dev_priv = to_i915(dev);
2188         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2189         struct i915_ggtt_view view;
2190         u32 alignment;
2191         int ret;
2192
2193         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2194
2195         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2196
2197         intel_fill_fb_ggtt_view(&view, fb, rotation);
2198
2199         /* Note that the w/a also requires 64 PTE of padding following the
2200          * bo. We currently fill all unused PTE with the shadow page and so
2201          * we should always have valid PTE following the scanout preventing
2202          * the VT-d warning.
2203          */
2204         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2205                 alignment = 256 * 1024;
2206
2207         /*
2208          * Global gtt pte registers are special registers which actually forward
2209          * writes to a chunk of system memory. Which means that there is no risk
2210          * that the register values disappear as soon as we call
2211          * intel_runtime_pm_put(), so it is correct to wrap only the
2212          * pin/unpin/fence and not more.
2213          */
2214         intel_runtime_pm_get(dev_priv);
2215
2216         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2217                                                    &view);
2218         if (ret)
2219                 goto err_pm;
2220
2221         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2222          * fence, whereas 965+ only requires a fence if using
2223          * framebuffer compression.  For simplicity, we always install
2224          * a fence as the cost is not that onerous.
2225          */
2226         if (view.type == I915_GGTT_VIEW_NORMAL) {
2227                 ret = i915_gem_object_get_fence(obj);
2228                 if (ret == -EDEADLK) {
2229                         /*
2230                          * -EDEADLK means there are no free fences
2231                          * no pending flips.
2232                          *
2233                          * This is propagated to atomic, but it uses
2234                          * -EDEADLK to force a locking recovery, so
2235                          * change the returned error to -EBUSY.
2236                          */
2237                         ret = -EBUSY;
2238                         goto err_unpin;
2239                 } else if (ret)
2240                         goto err_unpin;
2241
2242                 i915_gem_object_pin_fence(obj);
2243         }
2244
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247
2248 err_unpin:
2249         i915_gem_object_unpin_from_display_plane(obj, &view);
2250 err_pm:
2251         intel_runtime_pm_put(dev_priv);
2252         return ret;
2253 }
2254
2255 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2256 {
2257         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2258         struct i915_ggtt_view view;
2259
2260         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2261
2262         intel_fill_fb_ggtt_view(&view, fb, rotation);
2263
2264         if (view.type == I915_GGTT_VIEW_NORMAL)
2265                 i915_gem_object_unpin_fence(obj);
2266
2267         i915_gem_object_unpin_from_display_plane(obj, &view);
2268 }
2269
2270 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2271                           unsigned int rotation)
2272 {
2273         if (intel_rotation_90_or_270(rotation))
2274                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2275         else
2276                 return fb->pitches[plane];
2277 }
2278
2279 /*
2280  * Convert the x/y offsets into a linear offset.
2281  * Only valid with 0/180 degree rotation, which is fine since linear
2282  * offset is only used with linear buffers on pre-hsw and tiled buffers
2283  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2284  */
2285 u32 intel_fb_xy_to_linear(int x, int y,
2286                           const struct intel_plane_state *state,
2287                           int plane)
2288 {
2289         const struct drm_framebuffer *fb = state->base.fb;
2290         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2291         unsigned int pitch = fb->pitches[plane];
2292
2293         return y * pitch + x * cpp;
2294 }
2295
2296 /*
2297  * Add the x/y offsets derived from fb->offsets[] to the user
2298  * specified plane src x/y offsets. The resulting x/y offsets
2299  * specify the start of scanout from the beginning of the gtt mapping.
2300  */
2301 void intel_add_fb_offsets(int *x, int *y,
2302                           const struct intel_plane_state *state,
2303                           int plane)
2304
2305 {
2306         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2307         unsigned int rotation = state->base.rotation;
2308
2309         if (intel_rotation_90_or_270(rotation)) {
2310                 *x += intel_fb->rotated[plane].x;
2311                 *y += intel_fb->rotated[plane].y;
2312         } else {
2313                 *x += intel_fb->normal[plane].x;
2314                 *y += intel_fb->normal[plane].y;
2315         }
2316 }
2317
2318 /*
2319  * Input tile dimensions and pitch must already be
2320  * rotated to match x and y, and in pixel units.
2321  */
2322 static u32 _intel_adjust_tile_offset(int *x, int *y,
2323                                      unsigned int tile_width,
2324                                      unsigned int tile_height,
2325                                      unsigned int tile_size,
2326                                      unsigned int pitch_tiles,
2327                                      u32 old_offset,
2328                                      u32 new_offset)
2329 {
2330         unsigned int pitch_pixels = pitch_tiles * tile_width;
2331         unsigned int tiles;
2332
2333         WARN_ON(old_offset & (tile_size - 1));
2334         WARN_ON(new_offset & (tile_size - 1));
2335         WARN_ON(new_offset > old_offset);
2336
2337         tiles = (old_offset - new_offset) / tile_size;
2338
2339         *y += tiles / pitch_tiles * tile_height;
2340         *x += tiles % pitch_tiles * tile_width;
2341
2342         /* minimize x in case it got needlessly big */
2343         *y += *x / pitch_pixels * tile_height;
2344         *x %= pitch_pixels;
2345
2346         return new_offset;
2347 }
2348
2349 /*
2350  * Adjust the tile offset by moving the difference into
2351  * the x/y offsets.
2352  */
2353 static u32 intel_adjust_tile_offset(int *x, int *y,
2354                                     const struct intel_plane_state *state, int plane,
2355                                     u32 old_offset, u32 new_offset)
2356 {
2357         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2358         const struct drm_framebuffer *fb = state->base.fb;
2359         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2360         unsigned int rotation = state->base.rotation;
2361         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2362
2363         WARN_ON(new_offset > old_offset);
2364
2365         if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2366                 unsigned int tile_size, tile_width, tile_height;
2367                 unsigned int pitch_tiles;
2368
2369                 tile_size = intel_tile_size(dev_priv);
2370                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2371                                 fb->modifier[plane], cpp);
2372
2373                 if (intel_rotation_90_or_270(rotation)) {
2374                         pitch_tiles = pitch / tile_height;
2375                         swap(tile_width, tile_height);
2376                 } else {
2377                         pitch_tiles = pitch / (tile_width * cpp);
2378                 }
2379
2380                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2381                                           tile_size, pitch_tiles,
2382                                           old_offset, new_offset);
2383         } else {
2384                 old_offset += *y * pitch + *x * cpp;
2385
2386                 *y = (old_offset - new_offset) / pitch;
2387                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2388         }
2389
2390         return new_offset;
2391 }
2392
2393 /*
2394  * Computes the linear offset to the base tile and adjusts
2395  * x, y. bytes per pixel is assumed to be a power-of-two.
2396  *
2397  * In the 90/270 rotated case, x and y are assumed
2398  * to be already rotated to match the rotated GTT view, and
2399  * pitch is the tile_height aligned framebuffer height.
2400  *
2401  * This function is used when computing the derived information
2402  * under intel_framebuffer, so using any of that information
2403  * here is not allowed. Anything under drm_framebuffer can be
2404  * used. This is why the user has to pass in the pitch since it
2405  * is specified in the rotated orientation.
2406  */
2407 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2408                                       int *x, int *y,
2409                                       const struct drm_framebuffer *fb, int plane,
2410                                       unsigned int pitch,
2411                                       unsigned int rotation,
2412                                       u32 alignment)
2413 {
2414         uint64_t fb_modifier = fb->modifier[plane];
2415         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2416         u32 offset, offset_aligned;
2417
2418         if (alignment)
2419                 alignment--;
2420
2421         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2422                 unsigned int tile_size, tile_width, tile_height;
2423                 unsigned int tile_rows, tiles, pitch_tiles;
2424
2425                 tile_size = intel_tile_size(dev_priv);
2426                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2427                                 fb_modifier, cpp);
2428
2429                 if (intel_rotation_90_or_270(rotation)) {
2430                         pitch_tiles = pitch / tile_height;
2431                         swap(tile_width, tile_height);
2432                 } else {
2433                         pitch_tiles = pitch / (tile_width * cpp);
2434                 }
2435
2436                 tile_rows = *y / tile_height;
2437                 *y %= tile_height;
2438
2439                 tiles = *x / tile_width;
2440                 *x %= tile_width;
2441
2442                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2443                 offset_aligned = offset & ~alignment;
2444
2445                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2446                                           tile_size, pitch_tiles,
2447                                           offset, offset_aligned);
2448         } else {
2449                 offset = *y * pitch + *x * cpp;
2450                 offset_aligned = offset & ~alignment;
2451
2452                 *y = (offset & alignment) / pitch;
2453                 *x = ((offset & alignment) - *y * pitch) / cpp;
2454         }
2455
2456         return offset_aligned;
2457 }
2458
2459 u32 intel_compute_tile_offset(int *x, int *y,
2460                               const struct intel_plane_state *state,
2461                               int plane)
2462 {
2463         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2464         const struct drm_framebuffer *fb = state->base.fb;
2465         unsigned int rotation = state->base.rotation;
2466         int pitch = intel_fb_pitch(fb, plane, rotation);
2467         u32 alignment;
2468
2469         /* AUX_DIST needs only 4K alignment */
2470         if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2471                 alignment = 4096;
2472         else
2473                 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2474
2475         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2476                                           rotation, alignment);
2477 }
2478
2479 /* Convert the fb->offset[] linear offset into x/y offsets */
2480 static void intel_fb_offset_to_xy(int *x, int *y,
2481                                   const struct drm_framebuffer *fb, int plane)
2482 {
2483         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2484         unsigned int pitch = fb->pitches[plane];
2485         u32 linear_offset = fb->offsets[plane];
2486
2487         *y = linear_offset / pitch;
2488         *x = linear_offset % pitch / cpp;
2489 }
2490
2491 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2492 {
2493         switch (fb_modifier) {
2494         case I915_FORMAT_MOD_X_TILED:
2495                 return I915_TILING_X;
2496         case I915_FORMAT_MOD_Y_TILED:
2497                 return I915_TILING_Y;
2498         default:
2499                 return I915_TILING_NONE;
2500         }
2501 }
2502
2503 static int
2504 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2505                    struct drm_framebuffer *fb)
2506 {
2507         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2508         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2509         u32 gtt_offset_rotated = 0;
2510         unsigned int max_size = 0;
2511         uint32_t format = fb->pixel_format;
2512         int i, num_planes = drm_format_num_planes(format);
2513         unsigned int tile_size = intel_tile_size(dev_priv);
2514
2515         for (i = 0; i < num_planes; i++) {
2516                 unsigned int width, height;
2517                 unsigned int cpp, size;
2518                 u32 offset;
2519                 int x, y;
2520
2521                 cpp = drm_format_plane_cpp(format, i);
2522                 width = drm_format_plane_width(fb->width, format, i);
2523                 height = drm_format_plane_height(fb->height, format, i);
2524
2525                 intel_fb_offset_to_xy(&x, &y, fb, i);
2526
2527                 /*
2528                  * The fence (if used) is aligned to the start of the object
2529                  * so having the framebuffer wrap around across the edge of the
2530                  * fenced region doesn't really work. We have no API to configure
2531                  * the fence start offset within the object (nor could we probably
2532                  * on gen2/3). So it's just easier if we just require that the
2533                  * fb layout agrees with the fence layout. We already check that the
2534                  * fb stride matches the fence stride elsewhere.
2535                  */
2536                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2537                     (x + width) * cpp > fb->pitches[i]) {
2538                         DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2539                                   i, fb->offsets[i]);
2540                         return -EINVAL;
2541                 }
2542
2543                 /*
2544                  * First pixel of the framebuffer from
2545                  * the start of the normal gtt mapping.
2546                  */
2547                 intel_fb->normal[i].x = x;
2548                 intel_fb->normal[i].y = y;
2549
2550                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2551                                                     fb, 0, fb->pitches[i],
2552                                                     DRM_ROTATE_0, tile_size);
2553                 offset /= tile_size;
2554
2555                 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2556                         unsigned int tile_width, tile_height;
2557                         unsigned int pitch_tiles;
2558                         struct drm_rect r;
2559
2560                         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2561                                         fb->modifier[i], cpp);
2562
2563                         rot_info->plane[i].offset = offset;
2564                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2565                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2566                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2567
2568                         intel_fb->rotated[i].pitch =
2569                                 rot_info->plane[i].height * tile_height;
2570
2571                         /* how many tiles does this plane need */
2572                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2573                         /*
2574                          * If the plane isn't horizontally tile aligned,
2575                          * we need one more tile.
2576                          */
2577                         if (x != 0)
2578                                 size++;
2579
2580                         /* rotate the x/y offsets to match the GTT view */
2581                         r.x1 = x;
2582                         r.y1 = y;
2583                         r.x2 = x + width;
2584                         r.y2 = y + height;
2585                         drm_rect_rotate(&r,
2586                                         rot_info->plane[i].width * tile_width,
2587                                         rot_info->plane[i].height * tile_height,
2588                                         DRM_ROTATE_270);
2589                         x = r.x1;
2590                         y = r.y1;
2591
2592                         /* rotate the tile dimensions to match the GTT view */
2593                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2594                         swap(tile_width, tile_height);
2595
2596                         /*
2597                          * We only keep the x/y offsets, so push all of the
2598                          * gtt offset into the x/y offsets.
2599                          */
2600                         _intel_adjust_tile_offset(&x, &y, tile_size,
2601                                                   tile_width, tile_height, pitch_tiles,
2602                                                   gtt_offset_rotated * tile_size, 0);
2603
2604                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2605
2606                         /*
2607                          * First pixel of the framebuffer from
2608                          * the start of the rotated gtt mapping.
2609                          */
2610                         intel_fb->rotated[i].x = x;
2611                         intel_fb->rotated[i].y = y;
2612                 } else {
2613                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2614                                             x * cpp, tile_size);
2615                 }
2616
2617                 /* how many tiles in total needed in the bo */
2618                 max_size = max(max_size, offset + size);
2619         }
2620
2621         if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2622                 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2623                           max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2624                 return -EINVAL;
2625         }
2626
2627         return 0;
2628 }
2629
2630 static int i9xx_format_to_fourcc(int format)
2631 {
2632         switch (format) {
2633         case DISPPLANE_8BPP:
2634                 return DRM_FORMAT_C8;
2635         case DISPPLANE_BGRX555:
2636                 return DRM_FORMAT_XRGB1555;
2637         case DISPPLANE_BGRX565:
2638                 return DRM_FORMAT_RGB565;
2639         default:
2640         case DISPPLANE_BGRX888:
2641                 return DRM_FORMAT_XRGB8888;
2642         case DISPPLANE_RGBX888:
2643                 return DRM_FORMAT_XBGR8888;
2644         case DISPPLANE_BGRX101010:
2645                 return DRM_FORMAT_XRGB2101010;
2646         case DISPPLANE_RGBX101010:
2647                 return DRM_FORMAT_XBGR2101010;
2648         }
2649 }
2650
2651 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2652 {
2653         switch (format) {
2654         case PLANE_CTL_FORMAT_RGB_565:
2655                 return DRM_FORMAT_RGB565;
2656         default:
2657         case PLANE_CTL_FORMAT_XRGB_8888:
2658                 if (rgb_order) {
2659                         if (alpha)
2660                                 return DRM_FORMAT_ABGR8888;
2661                         else
2662                                 return DRM_FORMAT_XBGR8888;
2663                 } else {
2664                         if (alpha)
2665                                 return DRM_FORMAT_ARGB8888;
2666                         else
2667                                 return DRM_FORMAT_XRGB8888;
2668                 }
2669         case PLANE_CTL_FORMAT_XRGB_2101010:
2670                 if (rgb_order)
2671                         return DRM_FORMAT_XBGR2101010;
2672                 else
2673                         return DRM_FORMAT_XRGB2101010;
2674         }
2675 }
2676
2677 static bool
2678 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2679                               struct intel_initial_plane_config *plane_config)
2680 {
2681         struct drm_device *dev = crtc->base.dev;
2682         struct drm_i915_private *dev_priv = to_i915(dev);
2683         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2684         struct drm_i915_gem_object *obj = NULL;
2685         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2686         struct drm_framebuffer *fb = &plane_config->fb->base;
2687         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2688         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2689                                     PAGE_SIZE);
2690
2691         size_aligned -= base_aligned;
2692
2693         if (plane_config->size == 0)
2694                 return false;
2695
2696         /* If the FB is too big, just don't use it since fbdev is not very
2697          * important and we should probably use that space with FBC or other
2698          * features. */
2699         if (size_aligned * 2 > ggtt->stolen_usable_size)
2700                 return false;
2701
2702         mutex_lock(&dev->struct_mutex);
2703
2704         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2705                                                              base_aligned,
2706                                                              base_aligned,
2707                                                              size_aligned);
2708         if (!obj) {
2709                 mutex_unlock(&dev->struct_mutex);
2710                 return false;
2711         }
2712
2713         if (plane_config->tiling == I915_TILING_X)
2714                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2715
2716         mode_cmd.pixel_format = fb->pixel_format;
2717         mode_cmd.width = fb->width;
2718         mode_cmd.height = fb->height;
2719         mode_cmd.pitches[0] = fb->pitches[0];
2720         mode_cmd.modifier[0] = fb->modifier[0];
2721         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2722
2723         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2724                                    &mode_cmd, obj)) {
2725                 DRM_DEBUG_KMS("intel fb init failed\n");
2726                 goto out_unref_obj;
2727         }
2728
2729         mutex_unlock(&dev->struct_mutex);
2730
2731         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2732         return true;
2733
2734 out_unref_obj:
2735         i915_gem_object_put(obj);
2736         mutex_unlock(&dev->struct_mutex);
2737         return false;
2738 }
2739
2740 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2741 static void
2742 update_state_fb(struct drm_plane *plane)
2743 {
2744         if (plane->fb == plane->state->fb)
2745                 return;
2746
2747         if (plane->state->fb)
2748                 drm_framebuffer_unreference(plane->state->fb);
2749         plane->state->fb = plane->fb;
2750         if (plane->state->fb)
2751                 drm_framebuffer_reference(plane->state->fb);
2752 }
2753
2754 static void
2755 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2756                              struct intel_initial_plane_config *plane_config)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = to_i915(dev);
2760         struct drm_crtc *c;
2761         struct intel_crtc *i;
2762         struct drm_i915_gem_object *obj;
2763         struct drm_plane *primary = intel_crtc->base.primary;
2764         struct drm_plane_state *plane_state = primary->state;
2765         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2766         struct intel_plane *intel_plane = to_intel_plane(primary);
2767         struct intel_plane_state *intel_state =
2768                 to_intel_plane_state(plane_state);
2769         struct drm_framebuffer *fb;
2770
2771         if (!plane_config->fb)
2772                 return;
2773
2774         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2775                 fb = &plane_config->fb->base;
2776                 goto valid_fb;
2777         }
2778
2779         kfree(plane_config->fb);
2780
2781         /*
2782          * Failed to alloc the obj, check to see if we should share
2783          * an fb with another CRTC instead
2784          */
2785         for_each_crtc(dev, c) {
2786                 i = to_intel_crtc(c);
2787
2788                 if (c == &intel_crtc->base)
2789                         continue;
2790
2791                 if (!i->active)
2792                         continue;
2793
2794                 fb = c->primary->fb;
2795                 if (!fb)
2796                         continue;
2797
2798                 obj = intel_fb_obj(fb);
2799                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2800                         drm_framebuffer_reference(fb);
2801                         goto valid_fb;
2802                 }
2803         }
2804
2805         /*
2806          * We've failed to reconstruct the BIOS FB.  Current display state
2807          * indicates that the primary plane is visible, but has a NULL FB,
2808          * which will lead to problems later if we don't fix it up.  The
2809          * simplest solution is to just disable the primary plane now and
2810          * pretend the BIOS never had it enabled.
2811          */
2812         to_intel_plane_state(plane_state)->base.visible = false;
2813         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2814         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2815         intel_plane->disable_plane(primary, &intel_crtc->base);
2816
2817         return;
2818
2819 valid_fb:
2820         plane_state->src_x = 0;
2821         plane_state->src_y = 0;
2822         plane_state->src_w = fb->width << 16;
2823         plane_state->src_h = fb->height << 16;
2824
2825         plane_state->crtc_x = 0;
2826         plane_state->crtc_y = 0;
2827         plane_state->crtc_w = fb->width;
2828         plane_state->crtc_h = fb->height;
2829
2830         intel_state->base.src.x1 = plane_state->src_x;
2831         intel_state->base.src.y1 = plane_state->src_y;
2832         intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2833         intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2834         intel_state->base.dst.x1 = plane_state->crtc_x;
2835         intel_state->base.dst.y1 = plane_state->crtc_y;
2836         intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2837         intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2838
2839         obj = intel_fb_obj(fb);
2840         if (i915_gem_object_is_tiled(obj))
2841                 dev_priv->preserve_bios_swizzle = true;
2842
2843         drm_framebuffer_reference(fb);
2844         primary->fb = primary->state->fb = fb;
2845         primary->crtc = primary->state->crtc = &intel_crtc->base;
2846         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2847         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2848                   &obj->frontbuffer_bits);
2849 }
2850
2851 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2852                                unsigned int rotation)
2853 {
2854         int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2855
2856         switch (fb->modifier[plane]) {
2857         case DRM_FORMAT_MOD_NONE:
2858         case I915_FORMAT_MOD_X_TILED:
2859                 switch (cpp) {
2860                 case 8:
2861                         return 4096;
2862                 case 4:
2863                 case 2:
2864                 case 1:
2865                         return 8192;
2866                 default:
2867                         MISSING_CASE(cpp);
2868                         break;
2869                 }
2870                 break;
2871         case I915_FORMAT_MOD_Y_TILED:
2872         case I915_FORMAT_MOD_Yf_TILED:
2873                 switch (cpp) {
2874                 case 8:
2875                         return 2048;
2876                 case 4:
2877                         return 4096;
2878                 case 2:
2879                 case 1:
2880                         return 8192;
2881                 default:
2882                         MISSING_CASE(cpp);
2883                         break;
2884                 }
2885                 break;
2886         default:
2887                 MISSING_CASE(fb->modifier[plane]);
2888         }
2889
2890         return 2048;
2891 }
2892
2893 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2894 {
2895         const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2896         const struct drm_framebuffer *fb = plane_state->base.fb;
2897         unsigned int rotation = plane_state->base.rotation;
2898         int x = plane_state->base.src.x1 >> 16;
2899         int y = plane_state->base.src.y1 >> 16;
2900         int w = drm_rect_width(&plane_state->base.src) >> 16;
2901         int h = drm_rect_height(&plane_state->base.src) >> 16;
2902         int max_width = skl_max_plane_width(fb, 0, rotation);
2903         int max_height = 4096;
2904         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2905
2906         if (w > max_width || h > max_height) {
2907                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2908                               w, h, max_width, max_height);
2909                 return -EINVAL;
2910         }
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 0);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2914
2915         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2916
2917         /*
2918          * AUX surface offset is specified as the distance from the
2919          * main surface offset, and it must be non-negative. Make
2920          * sure that is what we will get.
2921          */
2922         if (offset > aux_offset)
2923                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2924                                                   offset, aux_offset & ~(alignment - 1));
2925
2926         /*
2927          * When using an X-tiled surface, the plane blows up
2928          * if the x offset + width exceed the stride.
2929          *
2930          * TODO: linear and Y-tiled seem fine, Yf untested,
2931          */
2932         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2933                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2934
2935                 while ((x + w) * cpp > fb->pitches[0]) {
2936                         if (offset == 0) {
2937                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2938                                 return -EINVAL;
2939                         }
2940
2941                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2942                                                           offset, offset - alignment);
2943                 }
2944         }
2945
2946         plane_state->main.offset = offset;
2947         plane_state->main.x = x;
2948         plane_state->main.y = y;
2949
2950         return 0;
2951 }
2952
2953 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2954 {
2955         const struct drm_framebuffer *fb = plane_state->base.fb;
2956         unsigned int rotation = plane_state->base.rotation;
2957         int max_width = skl_max_plane_width(fb, 1, rotation);
2958         int max_height = 4096;
2959         int x = plane_state->base.src.x1 >> 17;
2960         int y = plane_state->base.src.y1 >> 17;
2961         int w = drm_rect_width(&plane_state->base.src) >> 17;
2962         int h = drm_rect_height(&plane_state->base.src) >> 17;
2963         u32 offset;
2964
2965         intel_add_fb_offsets(&x, &y, plane_state, 1);
2966         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2967
2968         /* FIXME not quite sure how/if these apply to the chroma plane */
2969         if (w > max_width || h > max_height) {
2970                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2971                               w, h, max_width, max_height);
2972                 return -EINVAL;
2973         }
2974
2975         plane_state->aux.offset = offset;
2976         plane_state->aux.x = x;
2977         plane_state->aux.y = y;
2978
2979         return 0;
2980 }
2981
2982 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2983 {
2984         const struct drm_framebuffer *fb = plane_state->base.fb;
2985         unsigned int rotation = plane_state->base.rotation;
2986         int ret;
2987
2988         /* Rotate src coordinates to match rotated GTT view */
2989         if (intel_rotation_90_or_270(rotation))
2990                 drm_rect_rotate(&plane_state->base.src,
2991                                 fb->width, fb->height, DRM_ROTATE_270);
2992
2993         /*
2994          * Handle the AUX surface first since
2995          * the main surface setup depends on it.
2996          */
2997         if (fb->pixel_format == DRM_FORMAT_NV12) {
2998                 ret = skl_check_nv12_aux_surface(plane_state);
2999                 if (ret)
3000                         return ret;
3001         } else {
3002                 plane_state->aux.offset = ~0xfff;
3003                 plane_state->aux.x = 0;
3004                 plane_state->aux.y = 0;
3005         }
3006
3007         ret = skl_check_main_surface(plane_state);
3008         if (ret)
3009                 return ret;
3010
3011         return 0;
3012 }
3013
3014 static void i9xx_update_primary_plane(struct drm_plane *primary,
3015                                       const struct intel_crtc_state *crtc_state,
3016                                       const struct intel_plane_state *plane_state)
3017 {
3018         struct drm_device *dev = primary->dev;
3019         struct drm_i915_private *dev_priv = to_i915(dev);
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3021         struct drm_framebuffer *fb = plane_state->base.fb;
3022         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3023         int plane = intel_crtc->plane;
3024         u32 linear_offset;
3025         u32 dspcntr;
3026         i915_reg_t reg = DSPCNTR(plane);
3027         unsigned int rotation = plane_state->base.rotation;
3028         int x = plane_state->base.src.x1 >> 16;
3029         int y = plane_state->base.src.y1 >> 16;
3030
3031         dspcntr = DISPPLANE_GAMMA_ENABLE;
3032
3033         dspcntr |= DISPLAY_PLANE_ENABLE;
3034
3035         if (INTEL_INFO(dev)->gen < 4) {
3036                 if (intel_crtc->pipe == PIPE_B)
3037                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3038
3039                 /* pipesrc and dspsize control the size that is scaled from,
3040                  * which should always be the user's requested size.
3041                  */
3042                 I915_WRITE(DSPSIZE(plane),
3043                            ((crtc_state->pipe_src_h - 1) << 16) |
3044                            (crtc_state->pipe_src_w - 1));
3045                 I915_WRITE(DSPPOS(plane), 0);
3046         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3047                 I915_WRITE(PRIMSIZE(plane),
3048                            ((crtc_state->pipe_src_h - 1) << 16) |
3049                            (crtc_state->pipe_src_w - 1));
3050                 I915_WRITE(PRIMPOS(plane), 0);
3051                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3052         }
3053
3054         switch (fb->pixel_format) {
3055         case DRM_FORMAT_C8:
3056                 dspcntr |= DISPPLANE_8BPP;
3057                 break;
3058         case DRM_FORMAT_XRGB1555:
3059                 dspcntr |= DISPPLANE_BGRX555;
3060                 break;
3061         case DRM_FORMAT_RGB565:
3062                 dspcntr |= DISPPLANE_BGRX565;
3063                 break;
3064         case DRM_FORMAT_XRGB8888:
3065                 dspcntr |= DISPPLANE_BGRX888;
3066                 break;
3067         case DRM_FORMAT_XBGR8888:
3068                 dspcntr |= DISPPLANE_RGBX888;
3069                 break;
3070         case DRM_FORMAT_XRGB2101010:
3071                 dspcntr |= DISPPLANE_BGRX101010;
3072                 break;
3073         case DRM_FORMAT_XBGR2101010:
3074                 dspcntr |= DISPPLANE_RGBX101010;
3075                 break;
3076         default:
3077                 BUG();
3078         }
3079
3080         if (INTEL_GEN(dev_priv) >= 4 &&
3081             fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3082                 dspcntr |= DISPPLANE_TILED;
3083
3084         if (IS_G4X(dev))
3085                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3086
3087         intel_add_fb_offsets(&x, &y, plane_state, 0);
3088
3089         if (INTEL_INFO(dev)->gen >= 4)
3090                 intel_crtc->dspaddr_offset =
3091                         intel_compute_tile_offset(&x, &y, plane_state, 0);
3092
3093         if (rotation == DRM_ROTATE_180) {
3094                 dspcntr |= DISPPLANE_ROTATE_180;
3095
3096                 x += (crtc_state->pipe_src_w - 1);
3097                 y += (crtc_state->pipe_src_h - 1);
3098         }
3099
3100         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3101
3102         if (INTEL_INFO(dev)->gen < 4)
3103                 intel_crtc->dspaddr_offset = linear_offset;
3104
3105         intel_crtc->adjusted_x = x;
3106         intel_crtc->adjusted_y = y;
3107
3108         I915_WRITE(reg, dspcntr);
3109
3110         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3111         if (INTEL_INFO(dev)->gen >= 4) {
3112                 I915_WRITE(DSPSURF(plane),
3113                            intel_fb_gtt_offset(fb, rotation) +
3114                            intel_crtc->dspaddr_offset);
3115                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3116                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3117         } else
3118                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
3119         POSTING_READ(reg);
3120 }
3121
3122 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3123                                        struct drm_crtc *crtc)
3124 {
3125         struct drm_device *dev = crtc->dev;
3126         struct drm_i915_private *dev_priv = to_i915(dev);
3127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128         int plane = intel_crtc->plane;
3129
3130         I915_WRITE(DSPCNTR(plane), 0);
3131         if (INTEL_INFO(dev_priv)->gen >= 4)
3132                 I915_WRITE(DSPSURF(plane), 0);
3133         else
3134                 I915_WRITE(DSPADDR(plane), 0);
3135         POSTING_READ(DSPCNTR(plane));
3136 }
3137
3138 static void ironlake_update_primary_plane(struct drm_plane *primary,
3139                                           const struct intel_crtc_state *crtc_state,
3140                                           const struct intel_plane_state *plane_state)
3141 {
3142         struct drm_device *dev = primary->dev;
3143         struct drm_i915_private *dev_priv = to_i915(dev);
3144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3145         struct drm_framebuffer *fb = plane_state->base.fb;
3146         int plane = intel_crtc->plane;
3147         u32 linear_offset;
3148         u32 dspcntr;
3149         i915_reg_t reg = DSPCNTR(plane);
3150         unsigned int rotation = plane_state->base.rotation;
3151         int x = plane_state->base.src.x1 >> 16;
3152         int y = plane_state->base.src.y1 >> 16;
3153
3154         dspcntr = DISPPLANE_GAMMA_ENABLE;
3155         dspcntr |= DISPLAY_PLANE_ENABLE;
3156
3157         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3158                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3159
3160         switch (fb->pixel_format) {
3161         case DRM_FORMAT_C8:
3162                 dspcntr |= DISPPLANE_8BPP;
3163                 break;
3164         case DRM_FORMAT_RGB565:
3165                 dspcntr |= DISPPLANE_BGRX565;
3166                 break;
3167         case DRM_FORMAT_XRGB8888:
3168                 dspcntr |= DISPPLANE_BGRX888;
3169                 break;
3170         case DRM_FORMAT_XBGR8888:
3171                 dspcntr |= DISPPLANE_RGBX888;
3172                 break;
3173         case DRM_FORMAT_XRGB2101010:
3174                 dspcntr |= DISPPLANE_BGRX101010;
3175                 break;
3176         case DRM_FORMAT_XBGR2101010:
3177                 dspcntr |= DISPPLANE_RGBX101010;
3178                 break;
3179         default:
3180                 BUG();
3181         }
3182
3183         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3184                 dspcntr |= DISPPLANE_TILED;
3185
3186         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3187                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3188
3189         intel_add_fb_offsets(&x, &y, plane_state, 0);
3190
3191         intel_crtc->dspaddr_offset =
3192                 intel_compute_tile_offset(&x, &y, plane_state, 0);
3193
3194         if (rotation == DRM_ROTATE_180) {
3195                 dspcntr |= DISPPLANE_ROTATE_180;
3196
3197                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3198                         x += (crtc_state->pipe_src_w - 1);
3199                         y += (crtc_state->pipe_src_h - 1);
3200                 }
3201         }
3202
3203         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3204
3205         intel_crtc->adjusted_x = x;
3206         intel_crtc->adjusted_y = y;
3207
3208         I915_WRITE(reg, dspcntr);
3209
3210         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3211         I915_WRITE(DSPSURF(plane),
3212                    intel_fb_gtt_offset(fb, rotation) +
3213                    intel_crtc->dspaddr_offset);
3214         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3215                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3216         } else {
3217                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3218                 I915_WRITE(DSPLINOFF(plane), linear_offset);
3219         }
3220         POSTING_READ(reg);
3221 }
3222
3223 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3224                               uint64_t fb_modifier, uint32_t pixel_format)
3225 {
3226         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3227                 return 64;
3228         } else {
3229                 int cpp = drm_format_plane_cpp(pixel_format, 0);
3230
3231                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3232         }
3233 }
3234
3235 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3236                         unsigned int rotation)
3237 {
3238         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3239         struct i915_ggtt_view view;
3240         u64 offset;
3241
3242         intel_fill_fb_ggtt_view(&view, fb, rotation);
3243
3244         offset = i915_gem_obj_ggtt_offset_view(obj, &view);
3245
3246         WARN_ON(upper_32_bits(offset));
3247
3248         return lower_32_bits(offset);
3249 }
3250
3251 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3252 {
3253         struct drm_device *dev = intel_crtc->base.dev;
3254         struct drm_i915_private *dev_priv = to_i915(dev);
3255
3256         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3257         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3258         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3259 }
3260
3261 /*
3262  * This function detaches (aka. unbinds) unused scalers in hardware
3263  */
3264 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3265 {
3266         struct intel_crtc_scaler_state *scaler_state;
3267         int i;
3268
3269         scaler_state = &intel_crtc->config->scaler_state;
3270
3271         /* loop through and disable scalers that aren't in use */
3272         for (i = 0; i < intel_crtc->num_scalers; i++) {
3273                 if (!scaler_state->scalers[i].in_use)
3274                         skl_detach_scaler(intel_crtc, i);
3275         }
3276 }
3277
3278 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3279                      unsigned int rotation)
3280 {
3281         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3282         u32 stride = intel_fb_pitch(fb, plane, rotation);
3283
3284         /*
3285          * The stride is either expressed as a multiple of 64 bytes chunks for
3286          * linear buffers or in number of tiles for tiled buffers.
3287          */
3288         if (intel_rotation_90_or_270(rotation)) {
3289                 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3290
3291                 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3292         } else {
3293                 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3294                                                     fb->pixel_format);
3295         }
3296
3297         return stride;
3298 }
3299
3300 u32 skl_plane_ctl_format(uint32_t pixel_format)
3301 {
3302         switch (pixel_format) {
3303         case DRM_FORMAT_C8:
3304                 return PLANE_CTL_FORMAT_INDEXED;
3305         case DRM_FORMAT_RGB565:
3306                 return PLANE_CTL_FORMAT_RGB_565;
3307         case DRM_FORMAT_XBGR8888:
3308                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3309         case DRM_FORMAT_XRGB8888:
3310                 return PLANE_CTL_FORMAT_XRGB_8888;
3311         /*
3312          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3313          * to be already pre-multiplied. We need to add a knob (or a different
3314          * DRM_FORMAT) for user-space to configure that.
3315          */
3316         case DRM_FORMAT_ABGR8888:
3317                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3318                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3319         case DRM_FORMAT_ARGB8888:
3320                 return PLANE_CTL_FORMAT_XRGB_8888 |
3321                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3322         case DRM_FORMAT_XRGB2101010:
3323                 return PLANE_CTL_FORMAT_XRGB_2101010;
3324         case DRM_FORMAT_XBGR2101010:
3325                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3326         case DRM_FORMAT_YUYV:
3327                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3328         case DRM_FORMAT_YVYU:
3329                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3330         case DRM_FORMAT_UYVY:
3331                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3332         case DRM_FORMAT_VYUY:
3333                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3334         default:
3335                 MISSING_CASE(pixel_format);
3336         }
3337
3338         return 0;
3339 }
3340
3341 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3342 {
3343         switch (fb_modifier) {
3344         case DRM_FORMAT_MOD_NONE:
3345                 break;
3346         case I915_FORMAT_MOD_X_TILED:
3347                 return PLANE_CTL_TILED_X;
3348         case I915_FORMAT_MOD_Y_TILED:
3349                 return PLANE_CTL_TILED_Y;
3350         case I915_FORMAT_MOD_Yf_TILED:
3351                 return PLANE_CTL_TILED_YF;
3352         default:
3353                 MISSING_CASE(fb_modifier);
3354         }
3355
3356         return 0;
3357 }
3358
3359 u32 skl_plane_ctl_rotation(unsigned int rotation)
3360 {
3361         switch (rotation) {
3362         case DRM_ROTATE_0:
3363                 break;
3364         /*
3365          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3366          * while i915 HW rotation is clockwise, thats why this swapping.
3367          */
3368         case DRM_ROTATE_90:
3369                 return PLANE_CTL_ROTATE_270;
3370         case DRM_ROTATE_180:
3371                 return PLANE_CTL_ROTATE_180;
3372         case DRM_ROTATE_270:
3373                 return PLANE_CTL_ROTATE_90;
3374         default:
3375                 MISSING_CASE(rotation);
3376         }
3377
3378         return 0;
3379 }
3380
3381 static void skylake_update_primary_plane(struct drm_plane *plane,
3382                                          const struct intel_crtc_state *crtc_state,
3383                                          const struct intel_plane_state *plane_state)
3384 {
3385         struct drm_device *dev = plane->dev;
3386         struct drm_i915_private *dev_priv = to_i915(dev);
3387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3388         struct drm_framebuffer *fb = plane_state->base.fb;
3389         int pipe = intel_crtc->pipe;
3390         u32 plane_ctl;
3391         unsigned int rotation = plane_state->base.rotation;
3392         u32 stride = skl_plane_stride(fb, 0, rotation);
3393         u32 surf_addr = plane_state->main.offset;
3394         int scaler_id = plane_state->scaler_id;
3395         int src_x = plane_state->main.x;
3396         int src_y = plane_state->main.y;
3397         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3398         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3399         int dst_x = plane_state->base.dst.x1;
3400         int dst_y = plane_state->base.dst.y1;
3401         int dst_w = drm_rect_width(&plane_state->base.dst);
3402         int dst_h = drm_rect_height(&plane_state->base.dst);
3403
3404         plane_ctl = PLANE_CTL_ENABLE |
3405                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3406                     PLANE_CTL_PIPE_CSC_ENABLE;
3407
3408         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3409         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3410         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3411         plane_ctl |= skl_plane_ctl_rotation(rotation);
3412
3413         /* Sizes are 0 based */
3414         src_w--;
3415         src_h--;
3416         dst_w--;
3417         dst_h--;
3418
3419         intel_crtc->adjusted_x = src_x;
3420         intel_crtc->adjusted_y = src_y;
3421
3422         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3423         I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3424         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3425         I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3426
3427         if (scaler_id >= 0) {
3428                 uint32_t ps_ctrl = 0;
3429
3430                 WARN_ON(!dst_w || !dst_h);
3431                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3432                         crtc_state->scaler_state.scalers[scaler_id].mode;
3433                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3434                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3435                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3436                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3437                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3438         } else {
3439                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3440         }
3441
3442         I915_WRITE(PLANE_SURF(pipe, 0),
3443                    intel_fb_gtt_offset(fb, rotation) + surf_addr);
3444
3445         POSTING_READ(PLANE_SURF(pipe, 0));
3446 }
3447
3448 static void skylake_disable_primary_plane(struct drm_plane *primary,
3449                                           struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = to_i915(dev);
3453         int pipe = to_intel_crtc(crtc)->pipe;
3454
3455         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3456         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3457         POSTING_READ(PLANE_SURF(pipe, 0));
3458 }
3459
3460 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3461 static int
3462 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3463                            int x, int y, enum mode_set_atomic state)
3464 {
3465         /* Support for kgdboc is disabled, this needs a major rework. */
3466         DRM_ERROR("legacy panic handler not supported any more.\n");
3467
3468         return -ENODEV;
3469 }
3470
3471 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3472 {
3473         struct intel_crtc *crtc;
3474
3475         for_each_intel_crtc(&dev_priv->drm, crtc)
3476                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3477 }
3478
3479 static void intel_update_primary_planes(struct drm_device *dev)
3480 {
3481         struct drm_crtc *crtc;
3482
3483         for_each_crtc(dev, crtc) {
3484                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3485                 struct intel_plane_state *plane_state =
3486                         to_intel_plane_state(plane->base.state);
3487
3488                 if (plane_state->base.visible)
3489                         plane->update_plane(&plane->base,
3490                                             to_intel_crtc_state(crtc->state),
3491                                             plane_state);
3492         }
3493 }
3494
3495 static int
3496 __intel_display_resume(struct drm_device *dev,
3497                        struct drm_atomic_state *state)
3498 {
3499         struct drm_crtc_state *crtc_state;
3500         struct drm_crtc *crtc;
3501         int i, ret;
3502
3503         intel_modeset_setup_hw_state(dev);
3504         i915_redisable_vga(dev);
3505
3506         if (!state)
3507                 return 0;
3508
3509         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3510                 /*
3511                  * Force recalculation even if we restore
3512                  * current state. With fast modeset this may not result
3513                  * in a modeset when the state is compatible.
3514                  */
3515                 crtc_state->mode_changed = true;
3516         }
3517
3518         /* ignore any reset values/BIOS leftovers in the WM registers */
3519         to_intel_atomic_state(state)->skip_intermediate_wm = true;
3520
3521         ret = drm_atomic_commit(state);
3522
3523         WARN_ON(ret == -EDEADLK);
3524         return ret;
3525 }
3526
3527 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3528 {
3529         return intel_has_gpu_reset(dev_priv) &&
3530                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3531 }
3532
3533 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3534 {
3535         struct drm_device *dev = &dev_priv->drm;
3536         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3537         struct drm_atomic_state *state;
3538         int ret;
3539
3540         /*
3541          * Need mode_config.mutex so that we don't
3542          * trample ongoing ->detect() and whatnot.
3543          */
3544         mutex_lock(&dev->mode_config.mutex);
3545         drm_modeset_acquire_init(ctx, 0);
3546         while (1) {
3547                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3548                 if (ret != -EDEADLK)
3549                         break;
3550
3551                 drm_modeset_backoff(ctx);
3552         }
3553
3554         /* reset doesn't touch the display, but flips might get nuked anyway, */
3555         if (!i915.force_reset_modeset_test &&
3556             !gpu_reset_clobbers_display(dev_priv))
3557                 return;
3558
3559         /*
3560          * Disabling the crtcs gracefully seems nicer. Also the
3561          * g33 docs say we should at least disable all the planes.
3562          */
3563         state = drm_atomic_helper_duplicate_state(dev, ctx);
3564         if (IS_ERR(state)) {
3565                 ret = PTR_ERR(state);
3566                 state = NULL;
3567                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3568                 goto err;
3569         }
3570
3571         ret = drm_atomic_helper_disable_all(dev, ctx);
3572         if (ret) {
3573                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3574                 goto err;
3575         }
3576
3577         dev_priv->modeset_restore_state = state;
3578         state->acquire_ctx = ctx;
3579         return;
3580
3581 err:
3582         drm_atomic_state_free(state);
3583 }
3584
3585 void intel_finish_reset(struct drm_i915_private *dev_priv)
3586 {
3587         struct drm_device *dev = &dev_priv->drm;
3588         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3589         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3590         int ret;
3591
3592         /*
3593          * Flips in the rings will be nuked by the reset,
3594          * so complete all pending flips so that user space
3595          * will get its events and not get stuck.
3596          */
3597         intel_complete_page_flips(dev_priv);
3598
3599         dev_priv->modeset_restore_state = NULL;
3600
3601         /* reset doesn't touch the display */
3602         if (!gpu_reset_clobbers_display(dev_priv)) {
3603                 if (!state) {
3604                         /*
3605                          * Flips in the rings have been nuked by the reset,
3606                          * so update the base address of all primary
3607                          * planes to the the last fb to make sure we're
3608                          * showing the correct fb after a reset.
3609                          *
3610                          * FIXME: Atomic will make this obsolete since we won't schedule
3611                          * CS-based flips (which might get lost in gpu resets) any more.
3612                          */
3613                         intel_update_primary_planes(dev);
3614                 } else {
3615                         ret = __intel_display_resume(dev, state);
3616                         if (ret)
3617                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3618                 }
3619         } else {
3620                 /*
3621                  * The display has been reset as well,
3622                  * so need a full re-initialization.
3623                  */
3624                 intel_runtime_pm_disable_interrupts(dev_priv);
3625                 intel_runtime_pm_enable_interrupts(dev_priv);
3626
3627                 intel_modeset_init_hw(dev);
3628
3629                 spin_lock_irq(&dev_priv->irq_lock);
3630                 if (dev_priv->display.hpd_irq_setup)
3631                         dev_priv->display.hpd_irq_setup(dev_priv);
3632                 spin_unlock_irq(&dev_priv->irq_lock);
3633
3634                 ret = __intel_display_resume(dev, state);
3635                 if (ret)
3636                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3637
3638                 intel_hpd_init(dev_priv);
3639         }
3640
3641         drm_modeset_drop_locks(ctx);
3642         drm_modeset_acquire_fini(ctx);
3643         mutex_unlock(&dev->mode_config.mutex);
3644 }
3645
3646 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650         unsigned reset_counter;
3651         bool pending;
3652
3653         reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3654         if (intel_crtc->reset_counter != reset_counter)
3655                 return false;
3656
3657         spin_lock_irq(&dev->event_lock);
3658         pending = to_intel_crtc(crtc)->flip_work != NULL;
3659         spin_unlock_irq(&dev->event_lock);
3660
3661         return pending;
3662 }
3663
3664 static void intel_update_pipe_config(struct intel_crtc *crtc,
3665                                      struct intel_crtc_state *old_crtc_state)
3666 {
3667         struct drm_device *dev = crtc->base.dev;
3668         struct drm_i915_private *dev_priv = to_i915(dev);
3669         struct intel_crtc_state *pipe_config =
3670                 to_intel_crtc_state(crtc->base.state);
3671
3672         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3673         crtc->base.mode = crtc->base.state->mode;
3674
3675         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3676                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3677                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3678
3679         /*
3680          * Update pipe size and adjust fitter if needed: the reason for this is
3681          * that in compute_mode_changes we check the native mode (not the pfit
3682          * mode) to see if we can flip rather than do a full mode set. In the
3683          * fastboot case, we'll flip, but if we don't update the pipesrc and
3684          * pfit state, we'll end up with a big fb scanned out into the wrong
3685          * sized surface.
3686          */
3687
3688         I915_WRITE(PIPESRC(crtc->pipe),
3689                    ((pipe_config->pipe_src_w - 1) << 16) |
3690                    (pipe_config->pipe_src_h - 1));
3691
3692         /* on skylake this is done by detaching scalers */
3693         if (INTEL_INFO(dev)->gen >= 9) {
3694                 skl_detach_scalers(crtc);
3695
3696                 if (pipe_config->pch_pfit.enabled)
3697                         skylake_pfit_enable(crtc);
3698         } else if (HAS_PCH_SPLIT(dev)) {
3699                 if (pipe_config->pch_pfit.enabled)
3700                         ironlake_pfit_enable(crtc);
3701                 else if (old_crtc_state->pch_pfit.enabled)
3702                         ironlake_pfit_disable(crtc, true);
3703         }
3704 }
3705
3706 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         struct drm_i915_private *dev_priv = to_i915(dev);
3710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3711         int pipe = intel_crtc->pipe;
3712         i915_reg_t reg;
3713         u32 temp;
3714
3715         /* enable normal train */
3716         reg = FDI_TX_CTL(pipe);
3717         temp = I915_READ(reg);
3718         if (IS_IVYBRIDGE(dev)) {
3719                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3720                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3721         } else {
3722                 temp &= ~FDI_LINK_TRAIN_NONE;
3723                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3724         }
3725         I915_WRITE(reg, temp);
3726
3727         reg = FDI_RX_CTL(pipe);
3728         temp = I915_READ(reg);
3729         if (HAS_PCH_CPT(dev)) {
3730                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3732         } else {
3733                 temp &= ~FDI_LINK_TRAIN_NONE;
3734                 temp |= FDI_LINK_TRAIN_NONE;
3735         }
3736         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3737
3738         /* wait one idle pattern time */
3739         POSTING_READ(reg);
3740         udelay(1000);
3741
3742         /* IVB wants error correction enabled */
3743         if (IS_IVYBRIDGE(dev))
3744                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3745                            FDI_FE_ERRC_ENABLE);
3746 }
3747
3748 /* The FDI link training functions for ILK/Ibexpeak. */
3749 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3750 {
3751         struct drm_device *dev = crtc->dev;
3752         struct drm_i915_private *dev_priv = to_i915(dev);
3753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3754         int pipe = intel_crtc->pipe;
3755         i915_reg_t reg;
3756         u32 temp, tries;
3757
3758         /* FDI needs bits from pipe first */
3759         assert_pipe_enabled(dev_priv, pipe);
3760
3761         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3762            for train result */
3763         reg = FDI_RX_IMR(pipe);
3764         temp = I915_READ(reg);
3765         temp &= ~FDI_RX_SYMBOL_LOCK;
3766         temp &= ~FDI_RX_BIT_LOCK;
3767         I915_WRITE(reg, temp);
3768         I915_READ(reg);
3769         udelay(150);
3770
3771         /* enable CPU FDI TX and PCH FDI RX */
3772         reg = FDI_TX_CTL(pipe);
3773         temp = I915_READ(reg);
3774         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3775         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3776         temp &= ~FDI_LINK_TRAIN_NONE;
3777         temp |= FDI_LINK_TRAIN_PATTERN_1;
3778         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3779
3780         reg = FDI_RX_CTL(pipe);
3781         temp = I915_READ(reg);
3782         temp &= ~FDI_LINK_TRAIN_NONE;
3783         temp |= FDI_LINK_TRAIN_PATTERN_1;
3784         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3785
3786         POSTING_READ(reg);
3787         udelay(150);
3788
3789         /* Ironlake workaround, enable clock pointer after FDI enable*/
3790         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3791         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3792                    FDI_RX_PHASE_SYNC_POINTER_EN);
3793
3794         reg = FDI_RX_IIR(pipe);
3795         for (tries = 0; tries < 5; tries++) {
3796                 temp = I915_READ(reg);
3797                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3798
3799                 if ((temp & FDI_RX_BIT_LOCK)) {
3800                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3801                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3802                         break;
3803                 }
3804         }
3805         if (tries == 5)
3806                 DRM_ERROR("FDI train 1 fail!\n");
3807
3808         /* Train 2 */
3809         reg = FDI_TX_CTL(pipe);
3810         temp = I915_READ(reg);
3811         temp &= ~FDI_LINK_TRAIN_NONE;
3812         temp |= FDI_LINK_TRAIN_PATTERN_2;
3813         I915_WRITE(reg, temp);
3814
3815         reg = FDI_RX_CTL(pipe);
3816         temp = I915_READ(reg);
3817         temp &= ~FDI_LINK_TRAIN_NONE;
3818         temp |= FDI_LINK_TRAIN_PATTERN_2;
3819         I915_WRITE(reg, temp);
3820
3821         POSTING_READ(reg);
3822         udelay(150);
3823
3824         reg = FDI_RX_IIR(pipe);
3825         for (tries = 0; tries < 5; tries++) {
3826                 temp = I915_READ(reg);
3827                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3828
3829                 if (temp & FDI_RX_SYMBOL_LOCK) {
3830                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3831                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3832                         break;
3833                 }
3834         }
3835         if (tries == 5)
3836                 DRM_ERROR("FDI train 2 fail!\n");
3837
3838         DRM_DEBUG_KMS("FDI train done\n");
3839
3840 }
3841
3842 static const int snb_b_fdi_train_param[] = {
3843         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3844         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3845         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3846         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3847 };
3848
3849 /* The FDI link training functions for SNB/Cougarpoint. */
3850 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3851 {
3852         struct drm_device *dev = crtc->dev;
3853         struct drm_i915_private *dev_priv = to_i915(dev);
3854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855         int pipe = intel_crtc->pipe;
3856         i915_reg_t reg;
3857         u32 temp, i, retry;
3858
3859         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3860            for train result */
3861         reg = FDI_RX_IMR(pipe);
3862         temp = I915_READ(reg);
3863         temp &= ~FDI_RX_SYMBOL_LOCK;
3864         temp &= ~FDI_RX_BIT_LOCK;
3865         I915_WRITE(reg, temp);
3866
3867         POSTING_READ(reg);
3868         udelay(150);
3869
3870         /* enable CPU FDI TX and PCH FDI RX */
3871         reg = FDI_TX_CTL(pipe);
3872         temp = I915_READ(reg);
3873         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3874         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3875         temp &= ~FDI_LINK_TRAIN_NONE;
3876         temp |= FDI_LINK_TRAIN_PATTERN_1;
3877         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3878         /* SNB-B */
3879         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3880         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3881
3882         I915_WRITE(FDI_RX_MISC(pipe),
3883                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3884
3885         reg = FDI_RX_CTL(pipe);
3886         temp = I915_READ(reg);
3887         if (HAS_PCH_CPT(dev)) {
3888                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3889                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3890         } else {
3891                 temp &= ~FDI_LINK_TRAIN_NONE;
3892                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3893         }
3894         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3895
3896         POSTING_READ(reg);
3897         udelay(150);
3898
3899         for (i = 0; i < 4; i++) {
3900                 reg = FDI_TX_CTL(pipe);
3901                 temp = I915_READ(reg);
3902                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3903                 temp |= snb_b_fdi_train_param[i];
3904                 I915_WRITE(reg, temp);
3905
3906                 POSTING_READ(reg);
3907                 udelay(500);
3908
3909                 for (retry = 0; retry < 5; retry++) {
3910                         reg = FDI_RX_IIR(pipe);
3911                         temp = I915_READ(reg);
3912                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3913                         if (temp & FDI_RX_BIT_LOCK) {
3914                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3915                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3916                                 break;
3917                         }
3918                         udelay(50);
3919                 }
3920                 if (retry < 5)
3921                         break;
3922         }
3923         if (i == 4)
3924                 DRM_ERROR("FDI train 1 fail!\n");
3925
3926         /* Train 2 */
3927         reg = FDI_TX_CTL(pipe);
3928         temp = I915_READ(reg);
3929         temp &= ~FDI_LINK_TRAIN_NONE;
3930         temp |= FDI_LINK_TRAIN_PATTERN_2;
3931         if (IS_GEN6(dev)) {
3932                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3933                 /* SNB-B */
3934                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3935         }
3936         I915_WRITE(reg, temp);
3937
3938         reg = FDI_RX_CTL(pipe);
3939         temp = I915_READ(reg);
3940         if (HAS_PCH_CPT(dev)) {
3941                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3942                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3943         } else {
3944                 temp &= ~FDI_LINK_TRAIN_NONE;
3945                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3946         }
3947         I915_WRITE(reg, temp);
3948
3949         POSTING_READ(reg);
3950         udelay(150);
3951
3952         for (i = 0; i < 4; i++) {
3953                 reg = FDI_TX_CTL(pipe);
3954                 temp = I915_READ(reg);
3955                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3956                 temp |= snb_b_fdi_train_param[i];
3957                 I915_WRITE(reg, temp);
3958
3959                 POSTING_READ(reg);
3960                 udelay(500);
3961
3962                 for (retry = 0; retry < 5; retry++) {
3963                         reg = FDI_RX_IIR(pipe);
3964                         temp = I915_READ(reg);
3965                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3966                         if (temp & FDI_RX_SYMBOL_LOCK) {
3967                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3968                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3969                                 break;
3970                         }
3971                         udelay(50);
3972                 }
3973                 if (retry < 5)
3974                         break;
3975         }
3976         if (i == 4)
3977                 DRM_ERROR("FDI train 2 fail!\n");
3978
3979         DRM_DEBUG_KMS("FDI train done.\n");
3980 }
3981
3982 /* Manual link training for Ivy Bridge A0 parts */
3983 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3984 {
3985         struct drm_device *dev = crtc->dev;
3986         struct drm_i915_private *dev_priv = to_i915(dev);
3987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988         int pipe = intel_crtc->pipe;
3989         i915_reg_t reg;
3990         u32 temp, i, j;
3991
3992         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3993            for train result */
3994         reg = FDI_RX_IMR(pipe);
3995         temp = I915_READ(reg);
3996         temp &= ~FDI_RX_SYMBOL_LOCK;
3997         temp &= ~FDI_RX_BIT_LOCK;
3998         I915_WRITE(reg, temp);
3999
4000         POSTING_READ(reg);
4001         udelay(150);
4002
4003         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4004                       I915_READ(FDI_RX_IIR(pipe)));
4005
4006         /* Try each vswing and preemphasis setting twice before moving on */
4007         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4008                 /* disable first in case we need to retry */
4009                 reg = FDI_TX_CTL(pipe);
4010                 temp = I915_READ(reg);
4011                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4012                 temp &= ~FDI_TX_ENABLE;
4013                 I915_WRITE(reg, temp);
4014
4015                 reg = FDI_RX_CTL(pipe);
4016                 temp = I915_READ(reg);
4017                 temp &= ~FDI_LINK_TRAIN_AUTO;
4018                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4019                 temp &= ~FDI_RX_ENABLE;
4020                 I915_WRITE(reg, temp);
4021
4022                 /* enable CPU FDI TX and PCH FDI RX */
4023                 reg = FDI_TX_CTL(pipe);
4024                 temp = I915_READ(reg);
4025                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4026                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4027                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4028                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4029                 temp |= snb_b_fdi_train_param[j/2];
4030                 temp |= FDI_COMPOSITE_SYNC;
4031                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4032
4033                 I915_WRITE(FDI_RX_MISC(pipe),
4034                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4035
4036                 reg = FDI_RX_CTL(pipe);
4037                 temp = I915_READ(reg);
4038                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4039                 temp |= FDI_COMPOSITE_SYNC;
4040                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4041
4042                 POSTING_READ(reg);
4043                 udelay(1); /* should be 0.5us */
4044
4045                 for (i = 0; i < 4; i++) {
4046                         reg = FDI_RX_IIR(pipe);
4047                         temp = I915_READ(reg);
4048                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4049
4050                         if (temp & FDI_RX_BIT_LOCK ||
4051                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4052                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4053                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4054                                               i);
4055                                 break;
4056                         }
4057                         udelay(1); /* should be 0.5us */
4058                 }
4059                 if (i == 4) {
4060                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4061                         continue;
4062                 }
4063
4064                 /* Train 2 */
4065                 reg = FDI_TX_CTL(pipe);
4066                 temp = I915_READ(reg);
4067                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4068                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4069                 I915_WRITE(reg, temp);
4070
4071                 reg = FDI_RX_CTL(pipe);
4072                 temp = I915_READ(reg);
4073                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4074                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4075                 I915_WRITE(reg, temp);
4076
4077                 POSTING_READ(reg);
4078                 udelay(2); /* should be 1.5us */
4079
4080                 for (i = 0; i < 4; i++) {
4081                         reg = FDI_RX_IIR(pipe);
4082                         temp = I915_READ(reg);
4083                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4084
4085                         if (temp & FDI_RX_SYMBOL_LOCK ||
4086                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4087                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4088                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4089                                               i);
4090                                 goto train_done;
4091                         }
4092                         udelay(2); /* should be 1.5us */
4093                 }
4094                 if (i == 4)
4095                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4096         }
4097
4098 train_done:
4099         DRM_DEBUG_KMS("FDI train done.\n");
4100 }
4101
4102 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4103 {
4104         struct drm_device *dev = intel_crtc->base.dev;
4105         struct drm_i915_private *dev_priv = to_i915(dev);
4106         int pipe = intel_crtc->pipe;
4107         i915_reg_t reg;
4108         u32 temp;
4109
4110         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4111         reg = FDI_RX_CTL(pipe);
4112         temp = I915_READ(reg);
4113         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4114         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4115         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4116         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4117
4118         POSTING_READ(reg);
4119         udelay(200);
4120
4121         /* Switch from Rawclk to PCDclk */
4122         temp = I915_READ(reg);
4123         I915_WRITE(reg, temp | FDI_PCDCLK);
4124
4125         POSTING_READ(reg);
4126         udelay(200);
4127
4128         /* Enable CPU FDI TX PLL, always on for Ironlake */
4129         reg = FDI_TX_CTL(pipe);
4130         temp = I915_READ(reg);
4131         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4132                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4133
4134                 POSTING_READ(reg);
4135                 udelay(100);
4136         }
4137 }
4138
4139 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4140 {
4141         struct drm_device *dev = intel_crtc->base.dev;
4142         struct drm_i915_private *dev_priv = to_i915(dev);
4143         int pipe = intel_crtc->pipe;
4144         i915_reg_t reg;
4145         u32 temp;
4146
4147         /* Switch from PCDclk to Rawclk */
4148         reg = FDI_RX_CTL(pipe);
4149         temp = I915_READ(reg);
4150         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4151
4152         /* Disable CPU FDI TX PLL */
4153         reg = FDI_TX_CTL(pipe);
4154         temp = I915_READ(reg);
4155         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4156
4157         POSTING_READ(reg);
4158         udelay(100);
4159
4160         reg = FDI_RX_CTL(pipe);
4161         temp = I915_READ(reg);
4162         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4163
4164         /* Wait for the clocks to turn off. */
4165         POSTING_READ(reg);
4166         udelay(100);
4167 }
4168
4169 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4170 {
4171         struct drm_device *dev = crtc->dev;
4172         struct drm_i915_private *dev_priv = to_i915(dev);
4173         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4174         int pipe = intel_crtc->pipe;
4175         i915_reg_t reg;
4176         u32 temp;
4177
4178         /* disable CPU FDI tx and PCH FDI rx */
4179         reg = FDI_TX_CTL(pipe);
4180         temp = I915_READ(reg);
4181         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4182         POSTING_READ(reg);
4183
4184         reg = FDI_RX_CTL(pipe);
4185         temp = I915_READ(reg);
4186         temp &= ~(0x7 << 16);
4187         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4188         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4189
4190         POSTING_READ(reg);
4191         udelay(100);
4192
4193         /* Ironlake workaround, disable clock pointer after downing FDI */
4194         if (HAS_PCH_IBX(dev))
4195                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4196
4197         /* still set train pattern 1 */
4198         reg = FDI_TX_CTL(pipe);
4199         temp = I915_READ(reg);
4200         temp &= ~FDI_LINK_TRAIN_NONE;
4201         temp |= FDI_LINK_TRAIN_PATTERN_1;
4202         I915_WRITE(reg, temp);
4203
4204         reg = FDI_RX_CTL(pipe);
4205         temp = I915_READ(reg);
4206         if (HAS_PCH_CPT(dev)) {
4207                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4208                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4209         } else {
4210                 temp &= ~FDI_LINK_TRAIN_NONE;
4211                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4212         }
4213         /* BPC in FDI rx is consistent with that in PIPECONF */
4214         temp &= ~(0x07 << 16);
4215         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4216         I915_WRITE(reg, temp);
4217
4218         POSTING_READ(reg);
4219         udelay(100);
4220 }
4221
4222 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4223 {
4224         struct intel_crtc *crtc;
4225
4226         /* Note that we don't need to be called with mode_config.lock here
4227          * as our list of CRTC objects is static for the lifetime of the
4228          * device and so cannot disappear as we iterate. Similarly, we can
4229          * happily treat the predicates as racy, atomic checks as userspace
4230          * cannot claim and pin a new fb without at least acquring the
4231          * struct_mutex and so serialising with us.
4232          */
4233         for_each_intel_crtc(dev, crtc) {
4234                 if (atomic_read(&crtc->unpin_work_count) == 0)
4235                         continue;
4236
4237                 if (crtc->flip_work)
4238                         intel_wait_for_vblank(dev, crtc->pipe);
4239
4240                 return true;
4241         }
4242
4243         return false;
4244 }
4245
4246 static void page_flip_completed(struct intel_crtc *intel_crtc)
4247 {
4248         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4249         struct intel_flip_work *work = intel_crtc->flip_work;
4250
4251         intel_crtc->flip_work = NULL;
4252
4253         if (work->event)
4254                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4255
4256         drm_crtc_vblank_put(&intel_crtc->base);
4257
4258         wake_up_all(&dev_priv->pending_flip_queue);
4259         queue_work(dev_priv->wq, &work->unpin_work);
4260
4261         trace_i915_flip_complete(intel_crtc->plane,
4262                                  work->pending_flip_obj);
4263 }
4264
4265 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4266 {
4267         struct drm_device *dev = crtc->dev;
4268         struct drm_i915_private *dev_priv = to_i915(dev);
4269         long ret;
4270
4271         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4272
4273         ret = wait_event_interruptible_timeout(
4274                                         dev_priv->pending_flip_queue,
4275                                         !intel_crtc_has_pending_flip(crtc),
4276                                         60*HZ);
4277
4278         if (ret < 0)
4279                 return ret;
4280
4281         if (ret == 0) {
4282                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4283                 struct intel_flip_work *work;
4284
4285                 spin_lock_irq(&dev->event_lock);
4286                 work = intel_crtc->flip_work;
4287                 if (work && !is_mmio_work(work)) {
4288                         WARN_ONCE(1, "Removing stuck page flip\n");
4289                         page_flip_completed(intel_crtc);
4290                 }
4291                 spin_unlock_irq(&dev->event_lock);
4292         }
4293
4294         return 0;
4295 }
4296
4297 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4298 {
4299         u32 temp;
4300
4301         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4302
4303         mutex_lock(&dev_priv->sb_lock);
4304
4305         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4306         temp |= SBI_SSCCTL_DISABLE;
4307         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4308
4309         mutex_unlock(&dev_priv->sb_lock);
4310 }
4311
4312 /* Program iCLKIP clock to the desired frequency */
4313 static void lpt_program_iclkip(struct drm_crtc *crtc)
4314 {
4315         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4316         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4317         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4318         u32 temp;
4319
4320         lpt_disable_iclkip(dev_priv);
4321
4322         /* The iCLK virtual clock root frequency is in MHz,
4323          * but the adjusted_mode->crtc_clock in in KHz. To get the
4324          * divisors, it is necessary to divide one by another, so we
4325          * convert the virtual clock precision to KHz here for higher
4326          * precision.
4327          */
4328         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4329                 u32 iclk_virtual_root_freq = 172800 * 1000;
4330                 u32 iclk_pi_range = 64;
4331                 u32 desired_divisor;
4332
4333                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4334                                                     clock << auxdiv);
4335                 divsel = (desired_divisor / iclk_pi_range) - 2;
4336                 phaseinc = desired_divisor % iclk_pi_range;
4337
4338                 /*
4339                  * Near 20MHz is a corner case which is
4340                  * out of range for the 7-bit divisor
4341                  */
4342                 if (divsel <= 0x7f)
4343                         break;
4344         }
4345
4346         /* This should not happen with any sane values */
4347         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4348                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4349         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4350                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4351
4352         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4353                         clock,
4354                         auxdiv,
4355                         divsel,
4356                         phasedir,
4357                         phaseinc);
4358
4359         mutex_lock(&dev_priv->sb_lock);
4360
4361         /* Program SSCDIVINTPHASE6 */
4362         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4363         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4364         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4365         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4366         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4367         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4368         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4369         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4370
4371         /* Program SSCAUXDIV */
4372         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4373         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4374         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4375         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4376
4377         /* Enable modulator and associated divider */
4378         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4379         temp &= ~SBI_SSCCTL_DISABLE;
4380         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4381
4382         mutex_unlock(&dev_priv->sb_lock);
4383
4384         /* Wait for initialization time */
4385         udelay(24);
4386
4387         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4388 }
4389
4390 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4391 {
4392         u32 divsel, phaseinc, auxdiv;
4393         u32 iclk_virtual_root_freq = 172800 * 1000;
4394         u32 iclk_pi_range = 64;
4395         u32 desired_divisor;
4396         u32 temp;
4397
4398         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4399                 return 0;
4400
4401         mutex_lock(&dev_priv->sb_lock);
4402
4403         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4404         if (temp & SBI_SSCCTL_DISABLE) {
4405                 mutex_unlock(&dev_priv->sb_lock);
4406                 return 0;
4407         }
4408
4409         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4410         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4411                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4412         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4413                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4414
4415         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4416         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4417                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4418
4419         mutex_unlock(&dev_priv->sb_lock);
4420
4421         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4422
4423         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4424                                  desired_divisor << auxdiv);
4425 }
4426
4427 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4428                                                 enum pipe pch_transcoder)
4429 {
4430         struct drm_device *dev = crtc->base.dev;
4431         struct drm_i915_private *dev_priv = to_i915(dev);
4432         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4433
4434         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4435                    I915_READ(HTOTAL(cpu_transcoder)));
4436         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4437                    I915_READ(HBLANK(cpu_transcoder)));
4438         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4439                    I915_READ(HSYNC(cpu_transcoder)));
4440
4441         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4442                    I915_READ(VTOTAL(cpu_transcoder)));
4443         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4444                    I915_READ(VBLANK(cpu_transcoder)));
4445         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4446                    I915_READ(VSYNC(cpu_transcoder)));
4447         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4448                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4449 }
4450
4451 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4452 {
4453         struct drm_i915_private *dev_priv = to_i915(dev);
4454         uint32_t temp;
4455
4456         temp = I915_READ(SOUTH_CHICKEN1);
4457         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4458                 return;
4459
4460         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4461         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4462
4463         temp &= ~FDI_BC_BIFURCATION_SELECT;
4464         if (enable)
4465                 temp |= FDI_BC_BIFURCATION_SELECT;
4466
4467         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4468         I915_WRITE(SOUTH_CHICKEN1, temp);
4469         POSTING_READ(SOUTH_CHICKEN1);
4470 }
4471
4472 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4473 {
4474         struct drm_device *dev = intel_crtc->base.dev;
4475
4476         switch (intel_crtc->pipe) {
4477         case PIPE_A:
4478                 break;
4479         case PIPE_B:
4480                 if (intel_crtc->config->fdi_lanes > 2)
4481                         cpt_set_fdi_bc_bifurcation(dev, false);
4482                 else
4483                         cpt_set_fdi_bc_bifurcation(dev, true);
4484
4485                 break;
4486         case PIPE_C:
4487                 cpt_set_fdi_bc_bifurcation(dev, true);
4488
4489                 break;
4490         default:
4491                 BUG();
4492         }
4493 }
4494
4495 /* Return which DP Port should be selected for Transcoder DP control */
4496 static enum port
4497 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4498 {
4499         struct drm_device *dev = crtc->dev;
4500         struct intel_encoder *encoder;
4501
4502         for_each_encoder_on_crtc(dev, crtc, encoder) {
4503                 if (encoder->type == INTEL_OUTPUT_DP ||
4504                     encoder->type == INTEL_OUTPUT_EDP)
4505                         return enc_to_dig_port(&encoder->base)->port;
4506         }
4507
4508         return -1;
4509 }
4510
4511 /*
4512  * Enable PCH resources required for PCH ports:
4513  *   - PCH PLLs
4514  *   - FDI training & RX/TX
4515  *   - update transcoder timings
4516  *   - DP transcoding bits
4517  *   - transcoder
4518  */
4519 static void ironlake_pch_enable(struct drm_crtc *crtc)
4520 {
4521         struct drm_device *dev = crtc->dev;
4522         struct drm_i915_private *dev_priv = to_i915(dev);
4523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4524         int pipe = intel_crtc->pipe;
4525         u32 temp;
4526
4527         assert_pch_transcoder_disabled(dev_priv, pipe);
4528
4529         if (IS_IVYBRIDGE(dev))
4530                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4531
4532         /* Write the TU size bits before fdi link training, so that error
4533          * detection works. */
4534         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4535                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4536
4537         /* For PCH output, training FDI link */
4538         dev_priv->display.fdi_link_train(crtc);
4539
4540         /* We need to program the right clock selection before writing the pixel
4541          * mutliplier into the DPLL. */
4542         if (HAS_PCH_CPT(dev)) {
4543                 u32 sel;
4544
4545                 temp = I915_READ(PCH_DPLL_SEL);
4546                 temp |= TRANS_DPLL_ENABLE(pipe);
4547                 sel = TRANS_DPLLB_SEL(pipe);
4548                 if (intel_crtc->config->shared_dpll ==
4549                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4550                         temp |= sel;
4551                 else
4552                         temp &= ~sel;
4553                 I915_WRITE(PCH_DPLL_SEL, temp);
4554         }
4555
4556         /* XXX: pch pll's can be enabled any time before we enable the PCH
4557          * transcoder, and we actually should do this to not upset any PCH
4558          * transcoder that already use the clock when we share it.
4559          *
4560          * Note that enable_shared_dpll tries to do the right thing, but
4561          * get_shared_dpll unconditionally resets the pll - we need that to have
4562          * the right LVDS enable sequence. */
4563         intel_enable_shared_dpll(intel_crtc);
4564
4565         /* set transcoder timing, panel must allow it */
4566         assert_panel_unlocked(dev_priv, pipe);
4567         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4568
4569         intel_fdi_normal_train(crtc);
4570
4571         /* For PCH DP, enable TRANS_DP_CTL */
4572         if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4573                 const struct drm_display_mode *adjusted_mode =
4574                         &intel_crtc->config->base.adjusted_mode;
4575                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4576                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4577                 temp = I915_READ(reg);
4578                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4579                           TRANS_DP_SYNC_MASK |
4580                           TRANS_DP_BPC_MASK);
4581                 temp |= TRANS_DP_OUTPUT_ENABLE;
4582                 temp |= bpc << 9; /* same format but at 11:9 */
4583
4584                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4585                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4586                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4587                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4588
4589                 switch (intel_trans_dp_port_sel(crtc)) {
4590                 case PORT_B:
4591                         temp |= TRANS_DP_PORT_SEL_B;
4592                         break;
4593                 case PORT_C:
4594                         temp |= TRANS_DP_PORT_SEL_C;
4595                         break;
4596                 case PORT_D:
4597                         temp |= TRANS_DP_PORT_SEL_D;
4598                         break;
4599                 default:
4600                         BUG();
4601                 }
4602
4603                 I915_WRITE(reg, temp);
4604         }
4605
4606         ironlake_enable_pch_transcoder(dev_priv, pipe);
4607 }
4608
4609 static void lpt_pch_enable(struct drm_crtc *crtc)
4610 {
4611         struct drm_device *dev = crtc->dev;
4612         struct drm_i915_private *dev_priv = to_i915(dev);
4613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4615
4616         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4617
4618         lpt_program_iclkip(crtc);
4619
4620         /* Set transcoder timing. */
4621         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4622
4623         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4624 }
4625
4626 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4627 {
4628         struct drm_i915_private *dev_priv = to_i915(dev);
4629         i915_reg_t dslreg = PIPEDSL(pipe);
4630         u32 temp;
4631
4632         temp = I915_READ(dslreg);
4633         udelay(500);
4634         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4635                 if (wait_for(I915_READ(dslreg) != temp, 5))
4636                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4637         }
4638 }
4639
4640 static int
4641 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4642                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4643                   int src_w, int src_h, int dst_w, int dst_h)
4644 {
4645         struct intel_crtc_scaler_state *scaler_state =
4646                 &crtc_state->scaler_state;
4647         struct intel_crtc *intel_crtc =
4648                 to_intel_crtc(crtc_state->base.crtc);
4649         int need_scaling;
4650
4651         need_scaling = intel_rotation_90_or_270(rotation) ?
4652                 (src_h != dst_w || src_w != dst_h):
4653                 (src_w != dst_w || src_h != dst_h);
4654
4655         /*
4656          * if plane is being disabled or scaler is no more required or force detach
4657          *  - free scaler binded to this plane/crtc
4658          *  - in order to do this, update crtc->scaler_usage
4659          *
4660          * Here scaler state in crtc_state is set free so that
4661          * scaler can be assigned to other user. Actual register
4662          * update to free the scaler is done in plane/panel-fit programming.
4663          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4664          */
4665         if (force_detach || !need_scaling) {
4666                 if (*scaler_id >= 0) {
4667                         scaler_state->scaler_users &= ~(1 << scaler_user);
4668                         scaler_state->scalers[*scaler_id].in_use = 0;
4669
4670                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4671                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4672                                 intel_crtc->pipe, scaler_user, *scaler_id,
4673                                 scaler_state->scaler_users);
4674                         *scaler_id = -1;
4675                 }
4676                 return 0;
4677         }
4678
4679         /* range checks */
4680         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4681                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4682
4683                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4684                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4685                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4686                         "size is out of scaler range\n",
4687                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4688                 return -EINVAL;
4689         }
4690
4691         /* mark this plane as a scaler user in crtc_state */
4692         scaler_state->scaler_users |= (1 << scaler_user);
4693         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4694                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4695                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4696                 scaler_state->scaler_users);
4697
4698         return 0;
4699 }
4700
4701 /**
4702  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4703  *
4704  * @state: crtc's scaler state
4705  *
4706  * Return
4707  *     0 - scaler_usage updated successfully
4708  *    error - requested scaling cannot be supported or other error condition
4709  */
4710 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4711 {
4712         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4713         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4714
4715         DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4716                       intel_crtc->base.base.id, intel_crtc->base.name,
4717                       intel_crtc->pipe, SKL_CRTC_INDEX);
4718
4719         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4720                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4721                 state->pipe_src_w, state->pipe_src_h,
4722                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4723 }
4724
4725 /**
4726  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4727  *
4728  * @state: crtc's scaler state
4729  * @plane_state: atomic plane state to update
4730  *
4731  * Return
4732  *     0 - scaler_usage updated successfully
4733  *    error - requested scaling cannot be supported or other error condition
4734  */
4735 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4736                                    struct intel_plane_state *plane_state)
4737 {
4738
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4740         struct intel_plane *intel_plane =
4741                 to_intel_plane(plane_state->base.plane);
4742         struct drm_framebuffer *fb = plane_state->base.fb;
4743         int ret;
4744
4745         bool force_detach = !fb || !plane_state->base.visible;
4746
4747         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4748                       intel_plane->base.base.id, intel_plane->base.name,
4749                       intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4750
4751         ret = skl_update_scaler(crtc_state, force_detach,
4752                                 drm_plane_index(&intel_plane->base),
4753                                 &plane_state->scaler_id,
4754                                 plane_state->base.rotation,
4755                                 drm_rect_width(&plane_state->base.src) >> 16,
4756                                 drm_rect_height(&plane_state->base.src) >> 16,
4757                                 drm_rect_width(&plane_state->base.dst),
4758                                 drm_rect_height(&plane_state->base.dst));
4759
4760         if (ret || plane_state->scaler_id < 0)
4761                 return ret;
4762
4763         /* check colorkey */
4764         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4765                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4766                               intel_plane->base.base.id,
4767                               intel_plane->base.name);
4768                 return -EINVAL;
4769         }
4770
4771         /* Check src format */
4772         switch (fb->pixel_format) {
4773         case DRM_FORMAT_RGB565:
4774         case DRM_FORMAT_XBGR8888:
4775         case DRM_FORMAT_XRGB8888:
4776         case DRM_FORMAT_ABGR8888:
4777         case DRM_FORMAT_ARGB8888:
4778         case DRM_FORMAT_XRGB2101010:
4779         case DRM_FORMAT_XBGR2101010:
4780         case DRM_FORMAT_YUYV:
4781         case DRM_FORMAT_YVYU:
4782         case DRM_FORMAT_UYVY:
4783         case DRM_FORMAT_VYUY:
4784                 break;
4785         default:
4786                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4787                               intel_plane->base.base.id, intel_plane->base.name,
4788                               fb->base.id, fb->pixel_format);
4789                 return -EINVAL;
4790         }
4791
4792         return 0;
4793 }
4794
4795 static void skylake_scaler_disable(struct intel_crtc *crtc)
4796 {
4797         int i;
4798
4799         for (i = 0; i < crtc->num_scalers; i++)
4800                 skl_detach_scaler(crtc, i);
4801 }
4802
4803 static void skylake_pfit_enable(struct intel_crtc *crtc)
4804 {
4805         struct drm_device *dev = crtc->base.dev;
4806         struct drm_i915_private *dev_priv = to_i915(dev);
4807         int pipe = crtc->pipe;
4808         struct intel_crtc_scaler_state *scaler_state =
4809                 &crtc->config->scaler_state;
4810
4811         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4812
4813         if (crtc->config->pch_pfit.enabled) {
4814                 int id;
4815
4816                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4817                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4818                         return;
4819                 }
4820
4821                 id = scaler_state->scaler_id;
4822                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4823                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4824                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4825                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4826
4827                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4828         }
4829 }
4830
4831 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4832 {
4833         struct drm_device *dev = crtc->base.dev;
4834         struct drm_i915_private *dev_priv = to_i915(dev);
4835         int pipe = crtc->pipe;
4836
4837         if (crtc->config->pch_pfit.enabled) {
4838                 /* Force use of hard-coded filter coefficients
4839                  * as some pre-programmed values are broken,
4840                  * e.g. x201.
4841                  */
4842                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4843                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4844                                                  PF_PIPE_SEL_IVB(pipe));
4845                 else
4846                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4847                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4848                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4849         }
4850 }
4851
4852 void hsw_enable_ips(struct intel_crtc *crtc)
4853 {
4854         struct drm_device *dev = crtc->base.dev;
4855         struct drm_i915_private *dev_priv = to_i915(dev);
4856
4857         if (!crtc->config->ips_enabled)
4858                 return;
4859
4860         /*
4861          * We can only enable IPS after we enable a plane and wait for a vblank
4862          * This function is called from post_plane_update, which is run after
4863          * a vblank wait.
4864          */
4865
4866         assert_plane_enabled(dev_priv, crtc->plane);
4867         if (IS_BROADWELL(dev)) {
4868                 mutex_lock(&dev_priv->rps.hw_lock);
4869                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4870                 mutex_unlock(&dev_priv->rps.hw_lock);
4871                 /* Quoting Art Runyan: "its not safe to expect any particular
4872                  * value in IPS_CTL bit 31 after enabling IPS through the
4873                  * mailbox." Moreover, the mailbox may return a bogus state,
4874                  * so we need to just enable it and continue on.
4875                  */
4876         } else {
4877                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4878                 /* The bit only becomes 1 in the next vblank, so this wait here
4879                  * is essentially intel_wait_for_vblank. If we don't have this
4880                  * and don't wait for vblanks until the end of crtc_enable, then
4881                  * the HW state readout code will complain that the expected
4882                  * IPS_CTL value is not the one we read. */
4883                 if (intel_wait_for_register(dev_priv,
4884                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4885                                             50))
4886                         DRM_ERROR("Timed out waiting for IPS enable\n");
4887         }
4888 }
4889
4890 void hsw_disable_ips(struct intel_crtc *crtc)
4891 {
4892         struct drm_device *dev = crtc->base.dev;
4893         struct drm_i915_private *dev_priv = to_i915(dev);
4894
4895         if (!crtc->config->ips_enabled)
4896                 return;
4897
4898         assert_plane_enabled(dev_priv, crtc->plane);
4899         if (IS_BROADWELL(dev)) {
4900                 mutex_lock(&dev_priv->rps.hw_lock);
4901                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4902                 mutex_unlock(&dev_priv->rps.hw_lock);
4903                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4904                 if (intel_wait_for_register(dev_priv,
4905                                             IPS_CTL, IPS_ENABLE, 0,
4906                                             42))
4907                         DRM_ERROR("Timed out waiting for IPS disable\n");
4908         } else {
4909                 I915_WRITE(IPS_CTL, 0);
4910                 POSTING_READ(IPS_CTL);
4911         }
4912
4913         /* We need to wait for a vblank before we can disable the plane. */
4914         intel_wait_for_vblank(dev, crtc->pipe);
4915 }
4916
4917 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4918 {
4919         if (intel_crtc->overlay) {
4920                 struct drm_device *dev = intel_crtc->base.dev;
4921                 struct drm_i915_private *dev_priv = to_i915(dev);
4922
4923                 mutex_lock(&dev->struct_mutex);
4924                 dev_priv->mm.interruptible = false;
4925                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4926                 dev_priv->mm.interruptible = true;
4927                 mutex_unlock(&dev->struct_mutex);
4928         }
4929
4930         /* Let userspace switch the overlay on again. In most cases userspace
4931          * has to recompute where to put it anyway.
4932          */
4933 }
4934
4935 /**
4936  * intel_post_enable_primary - Perform operations after enabling primary plane
4937  * @crtc: the CRTC whose primary plane was just enabled
4938  *
4939  * Performs potentially sleeping operations that must be done after the primary
4940  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4941  * called due to an explicit primary plane update, or due to an implicit
4942  * re-enable that is caused when a sprite plane is updated to no longer
4943  * completely hide the primary plane.
4944  */
4945 static void
4946 intel_post_enable_primary(struct drm_crtc *crtc)
4947 {
4948         struct drm_device *dev = crtc->dev;
4949         struct drm_i915_private *dev_priv = to_i915(dev);
4950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951         int pipe = intel_crtc->pipe;
4952
4953         /*
4954          * FIXME IPS should be fine as long as one plane is
4955          * enabled, but in practice it seems to have problems
4956          * when going from primary only to sprite only and vice
4957          * versa.
4958          */
4959         hsw_enable_ips(intel_crtc);
4960
4961         /*
4962          * Gen2 reports pipe underruns whenever all planes are disabled.
4963          * So don't enable underrun reporting before at least some planes
4964          * are enabled.
4965          * FIXME: Need to fix the logic to work when we turn off all planes
4966          * but leave the pipe running.
4967          */
4968         if (IS_GEN2(dev))
4969                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4970
4971         /* Underruns don't always raise interrupts, so check manually. */
4972         intel_check_cpu_fifo_underruns(dev_priv);
4973         intel_check_pch_fifo_underruns(dev_priv);
4974 }
4975
4976 /* FIXME move all this to pre_plane_update() with proper state tracking */
4977 static void
4978 intel_pre_disable_primary(struct drm_crtc *crtc)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = to_i915(dev);
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         int pipe = intel_crtc->pipe;
4984
4985         /*
4986          * Gen2 reports pipe underruns whenever all planes are disabled.
4987          * So diasble underrun reporting before all the planes get disabled.
4988          * FIXME: Need to fix the logic to work when we turn off all planes
4989          * but leave the pipe running.
4990          */
4991         if (IS_GEN2(dev))
4992                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4993
4994         /*
4995          * FIXME IPS should be fine as long as one plane is
4996          * enabled, but in practice it seems to have problems
4997          * when going from primary only to sprite only and vice
4998          * versa.
4999          */
5000         hsw_disable_ips(intel_crtc);
5001 }
5002
5003 /* FIXME get rid of this and use pre_plane_update */
5004 static void
5005 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5006 {
5007         struct drm_device *dev = crtc->dev;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010         int pipe = intel_crtc->pipe;
5011
5012         intel_pre_disable_primary(crtc);
5013
5014         /*
5015          * Vblank time updates from the shadow to live plane control register
5016          * are blocked if the memory self-refresh mode is active at that
5017          * moment. So to make sure the plane gets truly disabled, disable
5018          * first the self-refresh mode. The self-refresh enable bit in turn
5019          * will be checked/applied by the HW only at the next frame start
5020          * event which is after the vblank start event, so we need to have a
5021          * wait-for-vblank between disabling the plane and the pipe.
5022          */
5023         if (HAS_GMCH_DISPLAY(dev)) {
5024                 intel_set_memory_cxsr(dev_priv, false);
5025                 dev_priv->wm.vlv.cxsr = false;
5026                 intel_wait_for_vblank(dev, pipe);
5027         }
5028 }
5029
5030 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5031 {
5032         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5033         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5034         struct intel_crtc_state *pipe_config =
5035                 to_intel_crtc_state(crtc->base.state);
5036         struct drm_plane *primary = crtc->base.primary;
5037         struct drm_plane_state *old_pri_state =
5038                 drm_atomic_get_existing_plane_state(old_state, primary);
5039
5040         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5041
5042         crtc->wm.cxsr_allowed = true;
5043
5044         if (pipe_config->update_wm_post && pipe_config->base.active)
5045                 intel_update_watermarks(&crtc->base);
5046
5047         if (old_pri_state) {
5048                 struct intel_plane_state *primary_state =
5049                         to_intel_plane_state(primary->state);
5050                 struct intel_plane_state *old_primary_state =
5051                         to_intel_plane_state(old_pri_state);
5052
5053                 intel_fbc_post_update(crtc);
5054
5055                 if (primary_state->base.visible &&
5056                     (needs_modeset(&pipe_config->base) ||
5057                      !old_primary_state->base.visible))
5058                         intel_post_enable_primary(&crtc->base);
5059         }
5060 }
5061
5062 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5063 {
5064         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5065         struct drm_device *dev = crtc->base.dev;
5066         struct drm_i915_private *dev_priv = to_i915(dev);
5067         struct intel_crtc_state *pipe_config =
5068                 to_intel_crtc_state(crtc->base.state);
5069         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5070         struct drm_plane *primary = crtc->base.primary;
5071         struct drm_plane_state *old_pri_state =
5072                 drm_atomic_get_existing_plane_state(old_state, primary);
5073         bool modeset = needs_modeset(&pipe_config->base);
5074
5075         if (old_pri_state) {
5076                 struct intel_plane_state *primary_state =
5077                         to_intel_plane_state(primary->state);
5078                 struct intel_plane_state *old_primary_state =
5079                         to_intel_plane_state(old_pri_state);
5080
5081                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5082
5083                 if (old_primary_state->base.visible &&
5084                     (modeset || !primary_state->base.visible))
5085                         intel_pre_disable_primary(&crtc->base);
5086         }
5087
5088         if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5089                 crtc->wm.cxsr_allowed = false;
5090
5091                 /*
5092                  * Vblank time updates from the shadow to live plane control register
5093                  * are blocked if the memory self-refresh mode is active at that
5094                  * moment. So to make sure the plane gets truly disabled, disable
5095                  * first the self-refresh mode. The self-refresh enable bit in turn
5096                  * will be checked/applied by the HW only at the next frame start
5097                  * event which is after the vblank start event, so we need to have a
5098                  * wait-for-vblank between disabling the plane and the pipe.
5099                  */
5100                 if (old_crtc_state->base.active) {
5101                         intel_set_memory_cxsr(dev_priv, false);
5102                         dev_priv->wm.vlv.cxsr = false;
5103                         intel_wait_for_vblank(dev, crtc->pipe);
5104                 }
5105         }
5106
5107         /*
5108          * IVB workaround: must disable low power watermarks for at least
5109          * one frame before enabling scaling.  LP watermarks can be re-enabled
5110          * when scaling is disabled.
5111          *
5112          * WaCxSRDisabledForSpriteScaling:ivb
5113          */
5114         if (pipe_config->disable_lp_wm) {
5115                 ilk_disable_lp_wm(dev);
5116                 intel_wait_for_vblank(dev, crtc->pipe);
5117         }
5118
5119         /*
5120          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5121          * watermark programming here.
5122          */
5123         if (needs_modeset(&pipe_config->base))
5124                 return;
5125
5126         /*
5127          * For platforms that support atomic watermarks, program the
5128          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5129          * will be the intermediate values that are safe for both pre- and
5130          * post- vblank; when vblank happens, the 'active' values will be set
5131          * to the final 'target' values and we'll do this again to get the
5132          * optimal watermarks.  For gen9+ platforms, the values we program here
5133          * will be the final target values which will get automatically latched
5134          * at vblank time; no further programming will be necessary.
5135          *
5136          * If a platform hasn't been transitioned to atomic watermarks yet,
5137          * we'll continue to update watermarks the old way, if flags tell
5138          * us to.
5139          */
5140         if (dev_priv->display.initial_watermarks != NULL)
5141                 dev_priv->display.initial_watermarks(pipe_config);
5142         else if (pipe_config->update_wm_pre)
5143                 intel_update_watermarks(&crtc->base);
5144 }
5145
5146 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5147 {
5148         struct drm_device *dev = crtc->dev;
5149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5150         struct drm_plane *p;
5151         int pipe = intel_crtc->pipe;
5152
5153         intel_crtc_dpms_overlay_disable(intel_crtc);
5154
5155         drm_for_each_plane_mask(p, dev, plane_mask)
5156                 to_intel_plane(p)->disable_plane(p, crtc);
5157
5158         /*
5159          * FIXME: Once we grow proper nuclear flip support out of this we need
5160          * to compute the mask of flip planes precisely. For the time being
5161          * consider this a flip to a NULL plane.
5162          */
5163         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5164 }
5165
5166 static void ironlake_crtc_enable(struct drm_crtc *crtc)
5167 {
5168         struct drm_device *dev = crtc->dev;
5169         struct drm_i915_private *dev_priv = to_i915(dev);
5170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5171         struct intel_encoder *encoder;
5172         int pipe = intel_crtc->pipe;
5173         struct intel_crtc_state *pipe_config =
5174                 to_intel_crtc_state(crtc->state);
5175
5176         if (WARN_ON(intel_crtc->active))
5177                 return;
5178
5179         /*
5180          * Sometimes spurious CPU pipe underruns happen during FDI
5181          * training, at least with VGA+HDMI cloning. Suppress them.
5182          *
5183          * On ILK we get an occasional spurious CPU pipe underruns
5184          * between eDP port A enable and vdd enable. Also PCH port
5185          * enable seems to result in the occasional CPU pipe underrun.
5186          *
5187          * Spurious PCH underruns also occur during PCH enabling.
5188          */
5189         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5190                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5191         if (intel_crtc->config->has_pch_encoder)
5192                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5193
5194         if (intel_crtc->config->has_pch_encoder)
5195                 intel_prepare_shared_dpll(intel_crtc);
5196
5197         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5198                 intel_dp_set_m_n(intel_crtc, M1_N1);
5199
5200         intel_set_pipe_timings(intel_crtc);
5201         intel_set_pipe_src_size(intel_crtc);
5202
5203         if (intel_crtc->config->has_pch_encoder) {
5204                 intel_cpu_transcoder_set_m_n(intel_crtc,
5205                                      &intel_crtc->config->fdi_m_n, NULL);
5206         }
5207
5208         ironlake_set_pipeconf(crtc);
5209
5210         intel_crtc->active = true;
5211
5212         for_each_encoder_on_crtc(dev, crtc, encoder)
5213                 if (encoder->pre_enable)
5214                         encoder->pre_enable(encoder);
5215
5216         if (intel_crtc->config->has_pch_encoder) {
5217                 /* Note: FDI PLL enabling _must_ be done before we enable the
5218                  * cpu pipes, hence this is separate from all the other fdi/pch
5219                  * enabling. */
5220                 ironlake_fdi_pll_enable(intel_crtc);
5221         } else {
5222                 assert_fdi_tx_disabled(dev_priv, pipe);
5223                 assert_fdi_rx_disabled(dev_priv, pipe);
5224         }
5225
5226         ironlake_pfit_enable(intel_crtc);
5227
5228         /*
5229          * On ILK+ LUT must be loaded before the pipe is running but with
5230          * clocks enabled
5231          */
5232         intel_color_load_luts(&pipe_config->base);
5233
5234         if (dev_priv->display.initial_watermarks != NULL)
5235                 dev_priv->display.initial_watermarks(intel_crtc->config);
5236         intel_enable_pipe(intel_crtc);
5237
5238         if (intel_crtc->config->has_pch_encoder)
5239                 ironlake_pch_enable(crtc);
5240
5241         assert_vblank_disabled(crtc);
5242         drm_crtc_vblank_on(crtc);
5243
5244         for_each_encoder_on_crtc(dev, crtc, encoder)
5245                 encoder->enable(encoder);
5246
5247         if (HAS_PCH_CPT(dev))
5248                 cpt_verify_modeset(dev, intel_crtc->pipe);
5249
5250         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5251         if (intel_crtc->config->has_pch_encoder)
5252                 intel_wait_for_vblank(dev, pipe);
5253         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5254         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5255 }
5256
5257 /* IPS only exists on ULT machines and is tied to pipe A. */
5258 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5259 {
5260         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5261 }
5262
5263 static void haswell_crtc_enable(struct drm_crtc *crtc)
5264 {
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = to_i915(dev);
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         struct intel_encoder *encoder;
5269         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5270         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5271         struct intel_crtc_state *pipe_config =
5272                 to_intel_crtc_state(crtc->state);
5273
5274         if (WARN_ON(intel_crtc->active))
5275                 return;
5276
5277         if (intel_crtc->config->has_pch_encoder)
5278                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5279                                                       false);
5280
5281         for_each_encoder_on_crtc(dev, crtc, encoder)
5282                 if (encoder->pre_pll_enable)
5283                         encoder->pre_pll_enable(encoder);
5284
5285         if (intel_crtc->config->shared_dpll)
5286                 intel_enable_shared_dpll(intel_crtc);
5287
5288         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5289                 intel_dp_set_m_n(intel_crtc, M1_N1);
5290
5291         if (!transcoder_is_dsi(cpu_transcoder))
5292                 intel_set_pipe_timings(intel_crtc);
5293
5294         intel_set_pipe_src_size(intel_crtc);
5295
5296         if (cpu_transcoder != TRANSCODER_EDP &&
5297             !transcoder_is_dsi(cpu_transcoder)) {
5298                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5299                            intel_crtc->config->pixel_multiplier - 1);
5300         }
5301
5302         if (intel_crtc->config->has_pch_encoder) {
5303                 intel_cpu_transcoder_set_m_n(intel_crtc,
5304                                      &intel_crtc->config->fdi_m_n, NULL);
5305         }
5306
5307         if (!transcoder_is_dsi(cpu_transcoder))
5308                 haswell_set_pipeconf(crtc);
5309
5310         haswell_set_pipemisc(crtc);
5311
5312         intel_color_set_csc(&pipe_config->base);
5313
5314         intel_crtc->active = true;
5315
5316         if (intel_crtc->config->has_pch_encoder)
5317                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5318         else
5319                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5320
5321         for_each_encoder_on_crtc(dev, crtc, encoder) {
5322                 if (encoder->pre_enable)
5323                         encoder->pre_enable(encoder);
5324         }
5325
5326         if (intel_crtc->config->has_pch_encoder)
5327                 dev_priv->display.fdi_link_train(crtc);
5328
5329         if (!transcoder_is_dsi(cpu_transcoder))
5330                 intel_ddi_enable_pipe_clock(intel_crtc);
5331
5332         if (INTEL_INFO(dev)->gen >= 9)
5333                 skylake_pfit_enable(intel_crtc);
5334         else
5335                 ironlake_pfit_enable(intel_crtc);
5336
5337         /*
5338          * On ILK+ LUT must be loaded before the pipe is running but with
5339          * clocks enabled
5340          */
5341         intel_color_load_luts(&pipe_config->base);
5342
5343         intel_ddi_set_pipe_settings(crtc);
5344         if (!transcoder_is_dsi(cpu_transcoder))
5345                 intel_ddi_enable_transcoder_func(crtc);
5346
5347         if (dev_priv->display.initial_watermarks != NULL)
5348                 dev_priv->display.initial_watermarks(pipe_config);
5349         else
5350                 intel_update_watermarks(crtc);
5351
5352         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5353         if (!transcoder_is_dsi(cpu_transcoder))
5354                 intel_enable_pipe(intel_crtc);
5355
5356         if (intel_crtc->config->has_pch_encoder)
5357                 lpt_pch_enable(crtc);
5358
5359         if (intel_crtc->config->dp_encoder_is_mst)
5360                 intel_ddi_set_vc_payload_alloc(crtc, true);
5361
5362         assert_vblank_disabled(crtc);
5363         drm_crtc_vblank_on(crtc);
5364
5365         for_each_encoder_on_crtc(dev, crtc, encoder) {
5366                 encoder->enable(encoder);
5367                 intel_opregion_notify_encoder(encoder, true);
5368         }
5369
5370         if (intel_crtc->config->has_pch_encoder) {
5371                 intel_wait_for_vblank(dev, pipe);
5372                 intel_wait_for_vblank(dev, pipe);
5373                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5374                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5375                                                       true);
5376         }
5377
5378         /* If we change the relative order between pipe/planes enabling, we need
5379          * to change the workaround. */
5380         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5381         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5382                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5383                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5384         }
5385 }
5386
5387 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5388 {
5389         struct drm_device *dev = crtc->base.dev;
5390         struct drm_i915_private *dev_priv = to_i915(dev);
5391         int pipe = crtc->pipe;
5392
5393         /* To avoid upsetting the power well on haswell only disable the pfit if
5394          * it's in use. The hw state code will make sure we get this right. */
5395         if (force || crtc->config->pch_pfit.enabled) {
5396                 I915_WRITE(PF_CTL(pipe), 0);
5397                 I915_WRITE(PF_WIN_POS(pipe), 0);
5398                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5399         }
5400 }
5401
5402 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5403 {
5404         struct drm_device *dev = crtc->dev;
5405         struct drm_i915_private *dev_priv = to_i915(dev);
5406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5407         struct intel_encoder *encoder;
5408         int pipe = intel_crtc->pipe;
5409
5410         /*
5411          * Sometimes spurious CPU pipe underruns happen when the
5412          * pipe is already disabled, but FDI RX/TX is still enabled.
5413          * Happens at least with VGA+HDMI cloning. Suppress them.
5414          */
5415         if (intel_crtc->config->has_pch_encoder) {
5416                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5417                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5418         }
5419
5420         for_each_encoder_on_crtc(dev, crtc, encoder)
5421                 encoder->disable(encoder);
5422
5423         drm_crtc_vblank_off(crtc);
5424         assert_vblank_disabled(crtc);
5425
5426         intel_disable_pipe(intel_crtc);
5427
5428         ironlake_pfit_disable(intel_crtc, false);
5429
5430         if (intel_crtc->config->has_pch_encoder)
5431                 ironlake_fdi_disable(crtc);
5432
5433         for_each_encoder_on_crtc(dev, crtc, encoder)
5434                 if (encoder->post_disable)
5435                         encoder->post_disable(encoder);
5436
5437         if (intel_crtc->config->has_pch_encoder) {
5438                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5439
5440                 if (HAS_PCH_CPT(dev)) {
5441                         i915_reg_t reg;
5442                         u32 temp;
5443
5444                         /* disable TRANS_DP_CTL */
5445                         reg = TRANS_DP_CTL(pipe);
5446                         temp = I915_READ(reg);
5447                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5448                                   TRANS_DP_PORT_SEL_MASK);
5449                         temp |= TRANS_DP_PORT_SEL_NONE;
5450                         I915_WRITE(reg, temp);
5451
5452                         /* disable DPLL_SEL */
5453                         temp = I915_READ(PCH_DPLL_SEL);
5454                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5455                         I915_WRITE(PCH_DPLL_SEL, temp);
5456                 }
5457
5458                 ironlake_fdi_pll_disable(intel_crtc);
5459         }
5460
5461         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5462         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5463 }
5464
5465 static void haswell_crtc_disable(struct drm_crtc *crtc)
5466 {
5467         struct drm_device *dev = crtc->dev;
5468         struct drm_i915_private *dev_priv = to_i915(dev);
5469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5470         struct intel_encoder *encoder;
5471         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5472
5473         if (intel_crtc->config->has_pch_encoder)
5474                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5475                                                       false);
5476
5477         for_each_encoder_on_crtc(dev, crtc, encoder) {
5478                 intel_opregion_notify_encoder(encoder, false);
5479                 encoder->disable(encoder);
5480         }
5481
5482         drm_crtc_vblank_off(crtc);
5483         assert_vblank_disabled(crtc);
5484
5485         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5486         if (!transcoder_is_dsi(cpu_transcoder))
5487                 intel_disable_pipe(intel_crtc);
5488
5489         if (intel_crtc->config->dp_encoder_is_mst)
5490                 intel_ddi_set_vc_payload_alloc(crtc, false);
5491
5492         if (!transcoder_is_dsi(cpu_transcoder))
5493                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5494
5495         if (INTEL_INFO(dev)->gen >= 9)
5496                 skylake_scaler_disable(intel_crtc);
5497         else
5498                 ironlake_pfit_disable(intel_crtc, false);
5499
5500         if (!transcoder_is_dsi(cpu_transcoder))
5501                 intel_ddi_disable_pipe_clock(intel_crtc);
5502
5503         for_each_encoder_on_crtc(dev, crtc, encoder)
5504                 if (encoder->post_disable)
5505                         encoder->post_disable(encoder);
5506
5507         if (intel_crtc->config->has_pch_encoder) {
5508                 lpt_disable_pch_transcoder(dev_priv);
5509                 lpt_disable_iclkip(dev_priv);
5510                 intel_ddi_fdi_disable(crtc);
5511
5512                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5513                                                       true);
5514         }
5515 }
5516
5517 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5518 {
5519         struct drm_device *dev = crtc->base.dev;
5520         struct drm_i915_private *dev_priv = to_i915(dev);
5521         struct intel_crtc_state *pipe_config = crtc->config;
5522
5523         if (!pipe_config->gmch_pfit.control)
5524                 return;
5525
5526         /*
5527          * The panel fitter should only be adjusted whilst the pipe is disabled,
5528          * according to register description and PRM.
5529          */
5530         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5531         assert_pipe_disabled(dev_priv, crtc->pipe);
5532
5533         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5534         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5535
5536         /* Border color in case we don't scale up to the full screen. Black by
5537          * default, change to something else for debugging. */
5538         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5539 }
5540
5541 static enum intel_display_power_domain port_to_power_domain(enum port port)
5542 {
5543         switch (port) {
5544         case PORT_A:
5545                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5546         case PORT_B:
5547                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5548         case PORT_C:
5549                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5550         case PORT_D:
5551                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5552         case PORT_E:
5553                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5554         default:
5555                 MISSING_CASE(port);
5556                 return POWER_DOMAIN_PORT_OTHER;
5557         }
5558 }
5559
5560 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5561 {
5562         switch (port) {
5563         case PORT_A:
5564                 return POWER_DOMAIN_AUX_A;
5565         case PORT_B:
5566                 return POWER_DOMAIN_AUX_B;
5567         case PORT_C:
5568                 return POWER_DOMAIN_AUX_C;
5569         case PORT_D:
5570                 return POWER_DOMAIN_AUX_D;
5571         case PORT_E:
5572                 /* FIXME: Check VBT for actual wiring of PORT E */
5573                 return POWER_DOMAIN_AUX_D;
5574         default:
5575                 MISSING_CASE(port);
5576                 return POWER_DOMAIN_AUX_A;
5577         }
5578 }
5579
5580 enum intel_display_power_domain
5581 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5582 {
5583         struct drm_device *dev = intel_encoder->base.dev;
5584         struct intel_digital_port *intel_dig_port;
5585
5586         switch (intel_encoder->type) {
5587         case INTEL_OUTPUT_UNKNOWN:
5588                 /* Only DDI platforms should ever use this output type */
5589                 WARN_ON_ONCE(!HAS_DDI(dev));
5590         case INTEL_OUTPUT_DP:
5591         case INTEL_OUTPUT_HDMI:
5592         case INTEL_OUTPUT_EDP:
5593                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5594                 return port_to_power_domain(intel_dig_port->port);
5595         case INTEL_OUTPUT_DP_MST:
5596                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5597                 return port_to_power_domain(intel_dig_port->port);
5598         case INTEL_OUTPUT_ANALOG:
5599                 return POWER_DOMAIN_PORT_CRT;
5600         case INTEL_OUTPUT_DSI:
5601                 return POWER_DOMAIN_PORT_DSI;
5602         default:
5603                 return POWER_DOMAIN_PORT_OTHER;
5604         }
5605 }
5606
5607 enum intel_display_power_domain
5608 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5609 {
5610         struct drm_device *dev = intel_encoder->base.dev;
5611         struct intel_digital_port *intel_dig_port;
5612
5613         switch (intel_encoder->type) {
5614         case INTEL_OUTPUT_UNKNOWN:
5615         case INTEL_OUTPUT_HDMI:
5616                 /*
5617                  * Only DDI platforms should ever use these output types.
5618                  * We can get here after the HDMI detect code has already set
5619                  * the type of the shared encoder. Since we can't be sure
5620                  * what's the status of the given connectors, play safe and
5621                  * run the DP detection too.
5622                  */
5623                 WARN_ON_ONCE(!HAS_DDI(dev));
5624         case INTEL_OUTPUT_DP:
5625         case INTEL_OUTPUT_EDP:
5626                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5627                 return port_to_aux_power_domain(intel_dig_port->port);
5628         case INTEL_OUTPUT_DP_MST:
5629                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5630                 return port_to_aux_power_domain(intel_dig_port->port);
5631         default:
5632                 MISSING_CASE(intel_encoder->type);
5633                 return POWER_DOMAIN_AUX_A;
5634         }
5635 }
5636
5637 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5638                                             struct intel_crtc_state *crtc_state)
5639 {
5640         struct drm_device *dev = crtc->dev;
5641         struct drm_encoder *encoder;
5642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5643         enum pipe pipe = intel_crtc->pipe;
5644         unsigned long mask;
5645         enum transcoder transcoder = crtc_state->cpu_transcoder;
5646
5647         if (!crtc_state->base.active)
5648                 return 0;
5649
5650         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5651         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5652         if (crtc_state->pch_pfit.enabled ||
5653             crtc_state->pch_pfit.force_thru)
5654                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5655
5656         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5657                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5658
5659                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5660         }
5661
5662         if (crtc_state->shared_dpll)
5663                 mask |= BIT(POWER_DOMAIN_PLLS);
5664
5665         return mask;
5666 }
5667
5668 static unsigned long
5669 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5670                                struct intel_crtc_state *crtc_state)
5671 {
5672         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5674         enum intel_display_power_domain domain;
5675         unsigned long domains, new_domains, old_domains;
5676
5677         old_domains = intel_crtc->enabled_power_domains;
5678         intel_crtc->enabled_power_domains = new_domains =
5679                 get_crtc_power_domains(crtc, crtc_state);
5680
5681         domains = new_domains & ~old_domains;
5682
5683         for_each_power_domain(domain, domains)
5684                 intel_display_power_get(dev_priv, domain);
5685
5686         return old_domains & ~new_domains;
5687 }
5688
5689 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5690                                       unsigned long domains)
5691 {
5692         enum intel_display_power_domain domain;
5693
5694         for_each_power_domain(domain, domains)
5695                 intel_display_power_put(dev_priv, domain);
5696 }
5697
5698 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5699 {
5700         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5701
5702         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5703             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5704                 return max_cdclk_freq;
5705         else if (IS_CHERRYVIEW(dev_priv))
5706                 return max_cdclk_freq*95/100;
5707         else if (INTEL_INFO(dev_priv)->gen < 4)
5708                 return 2*max_cdclk_freq*90/100;
5709         else
5710                 return max_cdclk_freq*90/100;
5711 }
5712
5713 static int skl_calc_cdclk(int max_pixclk, int vco);
5714
5715 static void intel_update_max_cdclk(struct drm_device *dev)
5716 {
5717         struct drm_i915_private *dev_priv = to_i915(dev);
5718
5719         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5720                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5721                 int max_cdclk, vco;
5722
5723                 vco = dev_priv->skl_preferred_vco_freq;
5724                 WARN_ON(vco != 8100000 && vco != 8640000);
5725
5726                 /*
5727                  * Use the lower (vco 8640) cdclk values as a
5728                  * first guess. skl_calc_cdclk() will correct it
5729                  * if the preferred vco is 8100 instead.
5730                  */
5731                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5732                         max_cdclk = 617143;
5733                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5734                         max_cdclk = 540000;
5735                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5736                         max_cdclk = 432000;
5737                 else
5738                         max_cdclk = 308571;
5739
5740                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5741         } else if (IS_BROXTON(dev)) {
5742                 dev_priv->max_cdclk_freq = 624000;
5743         } else if (IS_BROADWELL(dev))  {
5744                 /*
5745                  * FIXME with extra cooling we can allow
5746                  * 540 MHz for ULX and 675 Mhz for ULT.
5747                  * How can we know if extra cooling is
5748                  * available? PCI ID, VTB, something else?
5749                  */
5750                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5751                         dev_priv->max_cdclk_freq = 450000;
5752                 else if (IS_BDW_ULX(dev))
5753                         dev_priv->max_cdclk_freq = 450000;
5754                 else if (IS_BDW_ULT(dev))
5755                         dev_priv->max_cdclk_freq = 540000;
5756                 else
5757                         dev_priv->max_cdclk_freq = 675000;
5758         } else if (IS_CHERRYVIEW(dev)) {
5759                 dev_priv->max_cdclk_freq = 320000;
5760         } else if (IS_VALLEYVIEW(dev)) {
5761                 dev_priv->max_cdclk_freq = 400000;
5762         } else {
5763                 /* otherwise assume cdclk is fixed */
5764                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5765         }
5766
5767         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5768
5769         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5770                          dev_priv->max_cdclk_freq);
5771
5772         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5773                          dev_priv->max_dotclk_freq);
5774 }
5775
5776 static void intel_update_cdclk(struct drm_device *dev)
5777 {
5778         struct drm_i915_private *dev_priv = to_i915(dev);
5779
5780         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5781
5782         if (INTEL_GEN(dev_priv) >= 9)
5783                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5784                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5785                                  dev_priv->cdclk_pll.ref);
5786         else
5787                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5788                                  dev_priv->cdclk_freq);
5789
5790         /*
5791          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5792          * Programmng [sic] note: bit[9:2] should be programmed to the number
5793          * of cdclk that generates 4MHz reference clock freq which is used to
5794          * generate GMBus clock. This will vary with the cdclk freq.
5795          */
5796         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5797                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5798 }
5799
5800 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5801 static int skl_cdclk_decimal(int cdclk)
5802 {
5803         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5804 }
5805
5806 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5807 {
5808         int ratio;
5809
5810         if (cdclk == dev_priv->cdclk_pll.ref)
5811                 return 0;
5812
5813         switch (cdclk) {
5814         default:
5815                 MISSING_CASE(cdclk);
5816         case 144000:
5817         case 288000:
5818         case 384000:
5819         case 576000:
5820                 ratio = 60;
5821                 break;
5822         case 624000:
5823                 ratio = 65;
5824                 break;
5825         }
5826
5827         return dev_priv->cdclk_pll.ref * ratio;
5828 }
5829
5830 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5831 {
5832         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5833
5834         /* Timeout 200us */
5835         if (intel_wait_for_register(dev_priv,
5836                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5837                                     1))
5838                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5839
5840         dev_priv->cdclk_pll.vco = 0;
5841 }
5842
5843 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5844 {
5845         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5846         u32 val;
5847
5848         val = I915_READ(BXT_DE_PLL_CTL);
5849         val &= ~BXT_DE_PLL_RATIO_MASK;
5850         val |= BXT_DE_PLL_RATIO(ratio);
5851         I915_WRITE(BXT_DE_PLL_CTL, val);
5852
5853         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5854
5855         /* Timeout 200us */
5856         if (intel_wait_for_register(dev_priv,
5857                                     BXT_DE_PLL_ENABLE,
5858                                     BXT_DE_PLL_LOCK,
5859                                     BXT_DE_PLL_LOCK,
5860                                     1))
5861                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5862
5863         dev_priv->cdclk_pll.vco = vco;
5864 }
5865
5866 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5867 {
5868         u32 val, divider;
5869         int vco, ret;
5870
5871         vco = bxt_de_pll_vco(dev_priv, cdclk);
5872
5873         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5874
5875         /* cdclk = vco / 2 / div{1,1.5,2,4} */
5876         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5877         case 8:
5878                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5879                 break;
5880         case 4:
5881                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5882                 break;
5883         case 3:
5884                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5885                 break;
5886         case 2:
5887                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5888                 break;
5889         default:
5890                 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5891                 WARN_ON(vco != 0);
5892
5893                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5894                 break;
5895         }
5896
5897         /* Inform power controller of upcoming frequency change */
5898         mutex_lock(&dev_priv->rps.hw_lock);
5899         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5900                                       0x80000000);
5901         mutex_unlock(&dev_priv->rps.hw_lock);
5902
5903         if (ret) {
5904                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5905                           ret, cdclk);
5906                 return;
5907         }
5908
5909         if (dev_priv->cdclk_pll.vco != 0 &&
5910             dev_priv->cdclk_pll.vco != vco)
5911                 bxt_de_pll_disable(dev_priv);
5912
5913         if (dev_priv->cdclk_pll.vco != vco)
5914                 bxt_de_pll_enable(dev_priv, vco);
5915
5916         val = divider | skl_cdclk_decimal(cdclk);
5917         /*
5918          * FIXME if only the cd2x divider needs changing, it could be done
5919          * without shutting off the pipe (if only one pipe is active).
5920          */
5921         val |= BXT_CDCLK_CD2X_PIPE_NONE;
5922         /*
5923          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5924          * enable otherwise.
5925          */
5926         if (cdclk >= 500000)
5927                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5928         I915_WRITE(CDCLK_CTL, val);
5929
5930         mutex_lock(&dev_priv->rps.hw_lock);
5931         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5932                                       DIV_ROUND_UP(cdclk, 25000));
5933         mutex_unlock(&dev_priv->rps.hw_lock);
5934
5935         if (ret) {
5936                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5937                           ret, cdclk);
5938                 return;
5939         }
5940
5941         intel_update_cdclk(&dev_priv->drm);
5942 }
5943
5944 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5945 {
5946         u32 cdctl, expected;
5947
5948         intel_update_cdclk(&dev_priv->drm);
5949
5950         if (dev_priv->cdclk_pll.vco == 0 ||
5951             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5952                 goto sanitize;
5953
5954         /* DPLL okay; verify the cdclock
5955          *
5956          * Some BIOS versions leave an incorrect decimal frequency value and
5957          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5958          * so sanitize this register.
5959          */
5960         cdctl = I915_READ(CDCLK_CTL);
5961         /*
5962          * Let's ignore the pipe field, since BIOS could have configured the
5963          * dividers both synching to an active pipe, or asynchronously
5964          * (PIPE_NONE).
5965          */
5966         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5967
5968         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5969                    skl_cdclk_decimal(dev_priv->cdclk_freq);
5970         /*
5971          * Disable SSA Precharge when CD clock frequency < 500 MHz,
5972          * enable otherwise.
5973          */
5974         if (dev_priv->cdclk_freq >= 500000)
5975                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5976
5977         if (cdctl == expected)
5978                 /* All well; nothing to sanitize */
5979                 return;
5980
5981 sanitize:
5982         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5983
5984         /* force cdclk programming */
5985         dev_priv->cdclk_freq = 0;
5986
5987         /* force full PLL disable + enable */
5988         dev_priv->cdclk_pll.vco = -1;
5989 }
5990
5991 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5992 {
5993         bxt_sanitize_cdclk(dev_priv);
5994
5995         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5996                 return;
5997
5998         /*
5999          * FIXME:
6000          * - The initial CDCLK needs to be read from VBT.
6001          *   Need to make this change after VBT has changes for BXT.
6002          */
6003         bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6004 }
6005
6006 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6007 {
6008         bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6009 }
6010
6011 static int skl_calc_cdclk(int max_pixclk, int vco)
6012 {
6013         if (vco == 8640000) {
6014                 if (max_pixclk > 540000)
6015                         return 617143;
6016                 else if (max_pixclk > 432000)
6017                         return 540000;
6018                 else if (max_pixclk > 308571)
6019                         return 432000;
6020                 else
6021                         return 308571;
6022         } else {
6023                 if (max_pixclk > 540000)
6024                         return 675000;
6025                 else if (max_pixclk > 450000)
6026                         return 540000;
6027                 else if (max_pixclk > 337500)
6028                         return 450000;
6029                 else
6030                         return 337500;
6031         }
6032 }
6033
6034 static void
6035 skl_dpll0_update(struct drm_i915_private *dev_priv)
6036 {
6037         u32 val;
6038
6039         dev_priv->cdclk_pll.ref = 24000;
6040         dev_priv->cdclk_pll.vco = 0;
6041
6042         val = I915_READ(LCPLL1_CTL);
6043         if ((val & LCPLL_PLL_ENABLE) == 0)
6044                 return;
6045
6046         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6047                 return;
6048
6049         val = I915_READ(DPLL_CTRL1);
6050
6051         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6052                             DPLL_CTRL1_SSC(SKL_DPLL0) |
6053                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6054                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6055                 return;
6056
6057         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6058         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6059         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6060         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6061         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6062                 dev_priv->cdclk_pll.vco = 8100000;
6063                 break;
6064         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6065         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6066                 dev_priv->cdclk_pll.vco = 8640000;
6067                 break;
6068         default:
6069                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6070                 break;
6071         }
6072 }
6073
6074 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6075 {
6076         bool changed = dev_priv->skl_preferred_vco_freq != vco;
6077
6078         dev_priv->skl_preferred_vco_freq = vco;
6079
6080         if (changed)
6081                 intel_update_max_cdclk(&dev_priv->drm);
6082 }
6083
6084 static void
6085 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6086 {
6087         int min_cdclk = skl_calc_cdclk(0, vco);
6088         u32 val;
6089
6090         WARN_ON(vco != 8100000 && vco != 8640000);
6091
6092         /* select the minimum CDCLK before enabling DPLL 0 */
6093         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6094         I915_WRITE(CDCLK_CTL, val);
6095         POSTING_READ(CDCLK_CTL);
6096
6097         /*
6098          * We always enable DPLL0 with the lowest link rate possible, but still
6099          * taking into account the VCO required to operate the eDP panel at the
6100          * desired frequency. The usual DP link rates operate with a VCO of
6101          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6102          * The modeset code is responsible for the selection of the exact link
6103          * rate later on, with the constraint of choosing a frequency that
6104          * works with vco.
6105          */
6106         val = I915_READ(DPLL_CTRL1);
6107
6108         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6109                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6110         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6111         if (vco == 8640000)
6112                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6113                                             SKL_DPLL0);
6114         else
6115                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6116                                             SKL_DPLL0);
6117
6118         I915_WRITE(DPLL_CTRL1, val);
6119         POSTING_READ(DPLL_CTRL1);
6120
6121         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6122
6123         if (intel_wait_for_register(dev_priv,
6124                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6125                                     5))
6126                 DRM_ERROR("DPLL0 not locked\n");
6127
6128         dev_priv->cdclk_pll.vco = vco;
6129
6130         /* We'll want to keep using the current vco from now on. */
6131         skl_set_preferred_cdclk_vco(dev_priv, vco);
6132 }
6133
6134 static void
6135 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6136 {
6137         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6138         if (intel_wait_for_register(dev_priv,
6139                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6140                                    1))
6141                 DRM_ERROR("Couldn't disable DPLL0\n");
6142
6143         dev_priv->cdclk_pll.vco = 0;
6144 }
6145
6146 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
6147 {
6148         int ret;
6149         u32 val;
6150
6151         /* inform PCU we want to change CDCLK */
6152         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
6153         mutex_lock(&dev_priv->rps.hw_lock);
6154         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
6155         mutex_unlock(&dev_priv->rps.hw_lock);
6156
6157         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
6158 }
6159
6160 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
6161 {
6162         return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
6163 }
6164
6165 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6166 {
6167         struct drm_device *dev = &dev_priv->drm;
6168         u32 freq_select, pcu_ack;
6169
6170         WARN_ON((cdclk == 24000) != (vco == 0));
6171
6172         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6173
6174         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
6175                 DRM_ERROR("failed to inform PCU about cdclk change\n");
6176                 return;
6177         }
6178
6179         /* set CDCLK_CTL */
6180         switch (cdclk) {
6181         case 450000:
6182         case 432000:
6183                 freq_select = CDCLK_FREQ_450_432;
6184                 pcu_ack = 1;
6185                 break;
6186         case 540000:
6187                 freq_select = CDCLK_FREQ_540;
6188                 pcu_ack = 2;
6189                 break;
6190         case 308571:
6191         case 337500:
6192         default:
6193                 freq_select = CDCLK_FREQ_337_308;
6194                 pcu_ack = 0;
6195                 break;
6196         case 617143:
6197         case 675000:
6198                 freq_select = CDCLK_FREQ_675_617;
6199                 pcu_ack = 3;
6200                 break;
6201         }
6202
6203         if (dev_priv->cdclk_pll.vco != 0 &&
6204             dev_priv->cdclk_pll.vco != vco)
6205                 skl_dpll0_disable(dev_priv);
6206
6207         if (dev_priv->cdclk_pll.vco != vco)
6208                 skl_dpll0_enable(dev_priv, vco);
6209
6210         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6211         POSTING_READ(CDCLK_CTL);
6212
6213         /* inform PCU of the change */
6214         mutex_lock(&dev_priv->rps.hw_lock);
6215         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6216         mutex_unlock(&dev_priv->rps.hw_lock);
6217
6218         intel_update_cdclk(dev);
6219 }
6220
6221 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6222
6223 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6224 {
6225         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6226 }
6227
6228 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6229 {
6230         int cdclk, vco;
6231
6232         skl_sanitize_cdclk(dev_priv);
6233
6234         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6235                 /*
6236                  * Use the current vco as our initial
6237                  * guess as to what the preferred vco is.
6238                  */
6239                 if (dev_priv->skl_preferred_vco_freq == 0)
6240                         skl_set_preferred_cdclk_vco(dev_priv,
6241                                                     dev_priv->cdclk_pll.vco);
6242                 return;
6243         }
6244
6245         vco = dev_priv->skl_preferred_vco_freq;
6246         if (vco == 0)
6247                 vco = 8100000;
6248         cdclk = skl_calc_cdclk(0, vco);
6249
6250         skl_set_cdclk(dev_priv, cdclk, vco);
6251 }
6252
6253 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6254 {
6255         uint32_t cdctl, expected;
6256
6257         /*
6258          * check if the pre-os intialized the display
6259          * There is SWF18 scratchpad register defined which is set by the
6260          * pre-os which can be used by the OS drivers to check the status
6261          */
6262         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6263                 goto sanitize;
6264
6265         intel_update_cdclk(&dev_priv->drm);
6266         /* Is PLL enabled and locked ? */
6267         if (dev_priv->cdclk_pll.vco == 0 ||
6268             dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6269                 goto sanitize;
6270
6271         /* DPLL okay; verify the cdclock
6272          *
6273          * Noticed in some instances that the freq selection is correct but
6274          * decimal part is programmed wrong from BIOS where pre-os does not
6275          * enable display. Verify the same as well.
6276          */
6277         cdctl = I915_READ(CDCLK_CTL);
6278         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6279                 skl_cdclk_decimal(dev_priv->cdclk_freq);
6280         if (cdctl == expected)
6281                 /* All well; nothing to sanitize */
6282                 return;
6283
6284 sanitize:
6285         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6286
6287         /* force cdclk programming */
6288         dev_priv->cdclk_freq = 0;
6289         /* force full PLL disable + enable */
6290         dev_priv->cdclk_pll.vco = -1;
6291 }
6292
6293 /* Adjust CDclk dividers to allow high res or save power if possible */
6294 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6295 {
6296         struct drm_i915_private *dev_priv = to_i915(dev);
6297         u32 val, cmd;
6298
6299         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6300                                         != dev_priv->cdclk_freq);
6301
6302         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6303                 cmd = 2;
6304         else if (cdclk == 266667)
6305                 cmd = 1;
6306         else
6307                 cmd = 0;
6308
6309         mutex_lock(&dev_priv->rps.hw_lock);
6310         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6311         val &= ~DSPFREQGUAR_MASK;
6312         val |= (cmd << DSPFREQGUAR_SHIFT);
6313         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6314         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6315                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6316                      50)) {
6317                 DRM_ERROR("timed out waiting for CDclk change\n");
6318         }
6319         mutex_unlock(&dev_priv->rps.hw_lock);
6320
6321         mutex_lock(&dev_priv->sb_lock);
6322
6323         if (cdclk == 400000) {
6324                 u32 divider;
6325
6326                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6327
6328                 /* adjust cdclk divider */
6329                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6330                 val &= ~CCK_FREQUENCY_VALUES;
6331                 val |= divider;
6332                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6333
6334                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6335                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6336                              50))
6337                         DRM_ERROR("timed out waiting for CDclk change\n");
6338         }
6339
6340         /* adjust self-refresh exit latency value */
6341         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6342         val &= ~0x7f;
6343
6344         /*
6345          * For high bandwidth configs, we set a higher latency in the bunit
6346          * so that the core display fetch happens in time to avoid underruns.
6347          */
6348         if (cdclk == 400000)
6349                 val |= 4500 / 250; /* 4.5 usec */
6350         else
6351                 val |= 3000 / 250; /* 3.0 usec */
6352         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6353
6354         mutex_unlock(&dev_priv->sb_lock);
6355
6356         intel_update_cdclk(dev);
6357 }
6358
6359 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6360 {
6361         struct drm_i915_private *dev_priv = to_i915(dev);
6362         u32 val, cmd;
6363
6364         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6365                                                 != dev_priv->cdclk_freq);
6366
6367         switch (cdclk) {
6368         case 333333:
6369         case 320000:
6370         case 266667:
6371         case 200000:
6372                 break;
6373         default:
6374                 MISSING_CASE(cdclk);
6375                 return;
6376         }
6377
6378         /*
6379          * Specs are full of misinformation, but testing on actual
6380          * hardware has shown that we just need to write the desired
6381          * CCK divider into the Punit register.
6382          */
6383         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6384
6385         mutex_lock(&dev_priv->rps.hw_lock);
6386         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6387         val &= ~DSPFREQGUAR_MASK_CHV;
6388         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6389         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6390         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6391                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6392                      50)) {
6393                 DRM_ERROR("timed out waiting for CDclk change\n");
6394         }
6395         mutex_unlock(&dev_priv->rps.hw_lock);
6396
6397         intel_update_cdclk(dev);
6398 }
6399
6400 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6401                                  int max_pixclk)
6402 {
6403         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
6404         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6405
6406         /*
6407          * Really only a few cases to deal with, as only 4 CDclks are supported:
6408          *   200MHz
6409          *   267MHz
6410          *   320/333MHz (depends on HPLL freq)
6411          *   400MHz (VLV only)
6412          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6413          * of the lower bin and adjust if needed.
6414          *
6415          * We seem to get an unstable or solid color picture at 200MHz.
6416          * Not sure what's wrong. For now use 200MHz only when all pipes
6417          * are off.
6418          */
6419         if (!IS_CHERRYVIEW(dev_priv) &&
6420             max_pixclk > freq_320*limit/100)
6421                 return 400000;
6422         else if (max_pixclk > 266667*limit/100)
6423                 return freq_320;
6424         else if (max_pixclk > 0)
6425                 return 266667;
6426         else
6427                 return 200000;
6428 }
6429
6430 static int bxt_calc_cdclk(int max_pixclk)
6431 {
6432         if (max_pixclk > 576000)
6433                 return 624000;
6434         else if (max_pixclk > 384000)
6435                 return 576000;
6436         else if (max_pixclk > 288000)
6437                 return 384000;
6438         else if (max_pixclk > 144000)
6439                 return 288000;
6440         else
6441                 return 144000;
6442 }
6443
6444 /* Compute the max pixel clock for new configuration. */
6445 static int intel_mode_max_pixclk(struct drm_device *dev,
6446                                  struct drm_atomic_state *state)
6447 {
6448         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6449         struct drm_i915_private *dev_priv = to_i915(dev);
6450         struct drm_crtc *crtc;
6451         struct drm_crtc_state *crtc_state;
6452         unsigned max_pixclk = 0, i;
6453         enum pipe pipe;
6454
6455         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6456                sizeof(intel_state->min_pixclk));
6457
6458         for_each_crtc_in_state(state, crtc, crtc_state, i) {
6459                 int pixclk = 0;
6460
6461                 if (crtc_state->enable)
6462                         pixclk = crtc_state->adjusted_mode.crtc_clock;
6463
6464                 intel_state->min_pixclk[i] = pixclk;
6465         }
6466
6467         for_each_pipe(dev_priv, pipe)
6468                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6469
6470         return max_pixclk;
6471 }
6472
6473 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6474 {
6475         struct drm_device *dev = state->dev;
6476         struct drm_i915_private *dev_priv = to_i915(dev);
6477         int max_pixclk = intel_mode_max_pixclk(dev, state);
6478         struct intel_atomic_state *intel_state =
6479                 to_intel_atomic_state(state);
6480
6481         intel_state->cdclk = intel_state->dev_cdclk =
6482                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6483
6484         if (!intel_state->active_crtcs)
6485                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6486
6487         return 0;
6488 }
6489
6490 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6491 {
6492         int max_pixclk = ilk_max_pixel_rate(state);
6493         struct intel_atomic_state *intel_state =
6494                 to_intel_atomic_state(state);
6495
6496         intel_state->cdclk = intel_state->dev_cdclk =
6497                 bxt_calc_cdclk(max_pixclk);
6498
6499         if (!intel_state->active_crtcs)
6500                 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6501
6502         return 0;
6503 }
6504
6505 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6506 {
6507         unsigned int credits, default_credits;
6508
6509         if (IS_CHERRYVIEW(dev_priv))
6510                 default_credits = PFI_CREDIT(12);
6511         else
6512                 default_credits = PFI_CREDIT(8);
6513
6514         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6515                 /* CHV suggested value is 31 or 63 */
6516                 if (IS_CHERRYVIEW(dev_priv))
6517                         credits = PFI_CREDIT_63;
6518                 else
6519                         credits = PFI_CREDIT(15);
6520         } else {
6521                 credits = default_credits;
6522         }
6523
6524         /*
6525          * WA - write default credits before re-programming
6526          * FIXME: should we also set the resend bit here?
6527          */
6528         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6529                    default_credits);
6530
6531         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6532                    credits | PFI_CREDIT_RESEND);
6533
6534         /*
6535          * FIXME is this guaranteed to clear
6536          * immediately or should we poll for it?
6537          */
6538         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6539 }
6540
6541 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6542 {
6543         struct drm_device *dev = old_state->dev;
6544         struct drm_i915_private *dev_priv = to_i915(dev);
6545         struct intel_atomic_state *old_intel_state =
6546                 to_intel_atomic_state(old_state);
6547         unsigned req_cdclk = old_intel_state->dev_cdclk;
6548
6549         /*
6550          * FIXME: We can end up here with all power domains off, yet
6551          * with a CDCLK frequency other than the minimum. To account
6552          * for this take the PIPE-A power domain, which covers the HW
6553          * blocks needed for the following programming. This can be
6554          * removed once it's guaranteed that we get here either with
6555          * the minimum CDCLK set, or the required power domains
6556          * enabled.
6557          */
6558         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6559
6560         if (IS_CHERRYVIEW(dev))
6561                 cherryview_set_cdclk(dev, req_cdclk);
6562         else
6563                 valleyview_set_cdclk(dev, req_cdclk);
6564
6565         vlv_program_pfi_credits(dev_priv);
6566
6567         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6568 }
6569
6570 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6571 {
6572         struct drm_device *dev = crtc->dev;
6573         struct drm_i915_private *dev_priv = to_i915(dev);
6574         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575         struct intel_encoder *encoder;
6576         struct intel_crtc_state *pipe_config =
6577                 to_intel_crtc_state(crtc->state);
6578         int pipe = intel_crtc->pipe;
6579
6580         if (WARN_ON(intel_crtc->active))
6581                 return;
6582
6583         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6584                 intel_dp_set_m_n(intel_crtc, M1_N1);
6585
6586         intel_set_pipe_timings(intel_crtc);
6587         intel_set_pipe_src_size(intel_crtc);
6588
6589         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6590                 struct drm_i915_private *dev_priv = to_i915(dev);
6591
6592                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6593                 I915_WRITE(CHV_CANVAS(pipe), 0);
6594         }
6595
6596         i9xx_set_pipeconf(intel_crtc);
6597
6598         intel_crtc->active = true;
6599
6600         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6601
6602         for_each_encoder_on_crtc(dev, crtc, encoder)
6603                 if (encoder->pre_pll_enable)
6604                         encoder->pre_pll_enable(encoder);
6605
6606         if (IS_CHERRYVIEW(dev)) {
6607                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6608                 chv_enable_pll(intel_crtc, intel_crtc->config);
6609         } else {
6610                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6611                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6612         }
6613
6614         for_each_encoder_on_crtc(dev, crtc, encoder)
6615                 if (encoder->pre_enable)
6616                         encoder->pre_enable(encoder);
6617
6618         i9xx_pfit_enable(intel_crtc);
6619
6620         intel_color_load_luts(&pipe_config->base);
6621
6622         intel_update_watermarks(crtc);
6623         intel_enable_pipe(intel_crtc);
6624
6625         assert_vblank_disabled(crtc);
6626         drm_crtc_vblank_on(crtc);
6627
6628         for_each_encoder_on_crtc(dev, crtc, encoder)
6629                 encoder->enable(encoder);
6630 }
6631
6632 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6633 {
6634         struct drm_device *dev = crtc->base.dev;
6635         struct drm_i915_private *dev_priv = to_i915(dev);
6636
6637         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6638         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6639 }
6640
6641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6642 {
6643         struct drm_device *dev = crtc->dev;
6644         struct drm_i915_private *dev_priv = to_i915(dev);
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         struct intel_encoder *encoder;
6647         struct intel_crtc_state *pipe_config =
6648                 to_intel_crtc_state(crtc->state);
6649         enum pipe pipe = intel_crtc->pipe;
6650
6651         if (WARN_ON(intel_crtc->active))
6652                 return;
6653
6654         i9xx_set_pll_dividers(intel_crtc);
6655
6656         if (intel_crtc_has_dp_encoder(intel_crtc->config))
6657                 intel_dp_set_m_n(intel_crtc, M1_N1);
6658
6659         intel_set_pipe_timings(intel_crtc);
6660         intel_set_pipe_src_size(intel_crtc);
6661
6662         i9xx_set_pipeconf(intel_crtc);
6663
6664         intel_crtc->active = true;
6665
6666         if (!IS_GEN2(dev))
6667                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6668
6669         for_each_encoder_on_crtc(dev, crtc, encoder)
6670                 if (encoder->pre_enable)
6671                         encoder->pre_enable(encoder);
6672
6673         i9xx_enable_pll(intel_crtc);
6674
6675         i9xx_pfit_enable(intel_crtc);
6676
6677         intel_color_load_luts(&pipe_config->base);
6678
6679         intel_update_watermarks(crtc);
6680         intel_enable_pipe(intel_crtc);
6681
6682         assert_vblank_disabled(crtc);
6683         drm_crtc_vblank_on(crtc);
6684
6685         for_each_encoder_on_crtc(dev, crtc, encoder)
6686                 encoder->enable(encoder);
6687 }
6688
6689 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6690 {
6691         struct drm_device *dev = crtc->base.dev;
6692         struct drm_i915_private *dev_priv = to_i915(dev);
6693
6694         if (!crtc->config->gmch_pfit.control)
6695                 return;
6696
6697         assert_pipe_disabled(dev_priv, crtc->pipe);
6698
6699         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6700                          I915_READ(PFIT_CONTROL));
6701         I915_WRITE(PFIT_CONTROL, 0);
6702 }
6703
6704 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6705 {
6706         struct drm_device *dev = crtc->dev;
6707         struct drm_i915_private *dev_priv = to_i915(dev);
6708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6709         struct intel_encoder *encoder;
6710         int pipe = intel_crtc->pipe;
6711
6712         /*
6713          * On gen2 planes are double buffered but the pipe isn't, so we must
6714          * wait for planes to fully turn off before disabling the pipe.
6715          */
6716         if (IS_GEN2(dev))
6717                 intel_wait_for_vblank(dev, pipe);
6718
6719         for_each_encoder_on_crtc(dev, crtc, encoder)
6720                 encoder->disable(encoder);
6721
6722         drm_crtc_vblank_off(crtc);
6723         assert_vblank_disabled(crtc);
6724
6725         intel_disable_pipe(intel_crtc);
6726
6727         i9xx_pfit_disable(intel_crtc);
6728
6729         for_each_encoder_on_crtc(dev, crtc, encoder)
6730                 if (encoder->post_disable)
6731                         encoder->post_disable(encoder);
6732
6733         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6734                 if (IS_CHERRYVIEW(dev))
6735                         chv_disable_pll(dev_priv, pipe);
6736                 else if (IS_VALLEYVIEW(dev))
6737                         vlv_disable_pll(dev_priv, pipe);
6738                 else
6739                         i9xx_disable_pll(intel_crtc);
6740         }
6741
6742         for_each_encoder_on_crtc(dev, crtc, encoder)
6743                 if (encoder->post_pll_disable)
6744                         encoder->post_pll_disable(encoder);
6745
6746         if (!IS_GEN2(dev))
6747                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6748 }
6749
6750 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6751 {
6752         struct intel_encoder *encoder;
6753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6755         enum intel_display_power_domain domain;
6756         unsigned long domains;
6757
6758         if (!intel_crtc->active)
6759                 return;
6760
6761         if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6762                 WARN_ON(intel_crtc->flip_work);
6763
6764                 intel_pre_disable_primary_noatomic(crtc);
6765
6766                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6767                 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6768         }
6769
6770         dev_priv->display.crtc_disable(crtc);
6771
6772         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6773                       crtc->base.id, crtc->name);
6774
6775         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6776         crtc->state->active = false;
6777         intel_crtc->active = false;
6778         crtc->enabled = false;
6779         crtc->state->connector_mask = 0;
6780         crtc->state->encoder_mask = 0;
6781
6782         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6783                 encoder->base.crtc = NULL;
6784
6785         intel_fbc_disable(intel_crtc);
6786         intel_update_watermarks(crtc);
6787         intel_disable_shared_dpll(intel_crtc);
6788
6789         domains = intel_crtc->enabled_power_domains;
6790         for_each_power_domain(domain, domains)
6791                 intel_display_power_put(dev_priv, domain);
6792         intel_crtc->enabled_power_domains = 0;
6793
6794         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6795         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6796 }
6797
6798 /*
6799  * turn all crtc's off, but do not adjust state
6800  * This has to be paired with a call to intel_modeset_setup_hw_state.
6801  */
6802 int intel_display_suspend(struct drm_device *dev)
6803 {
6804         struct drm_i915_private *dev_priv = to_i915(dev);
6805         struct drm_atomic_state *state;
6806         int ret;
6807
6808         state = drm_atomic_helper_suspend(dev);
6809         ret = PTR_ERR_OR_ZERO(state);
6810         if (ret)
6811                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6812         else
6813                 dev_priv->modeset_restore_state = state;
6814         return ret;
6815 }
6816
6817 void intel_encoder_destroy(struct drm_encoder *encoder)
6818 {
6819         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6820
6821         drm_encoder_cleanup(encoder);
6822         kfree(intel_encoder);
6823 }
6824
6825 /* Cross check the actual hw state with our own modeset state tracking (and it's
6826  * internal consistency). */
6827 static void intel_connector_verify_state(struct intel_connector *connector)
6828 {
6829         struct drm_crtc *crtc = connector->base.state->crtc;
6830
6831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6832                       connector->base.base.id,
6833                       connector->base.name);
6834
6835         if (connector->get_hw_state(connector)) {
6836                 struct intel_encoder *encoder = connector->encoder;
6837                 struct drm_connector_state *conn_state = connector->base.state;
6838
6839                 I915_STATE_WARN(!crtc,
6840                          "connector enabled without attached crtc\n");
6841
6842                 if (!crtc)
6843                         return;
6844
6845                 I915_STATE_WARN(!crtc->state->active,
6846                       "connector is active, but attached crtc isn't\n");
6847
6848                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6849                         return;
6850
6851                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6852                         "atomic encoder doesn't match attached encoder\n");
6853
6854                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6855                         "attached encoder crtc differs from connector crtc\n");
6856         } else {
6857                 I915_STATE_WARN(crtc && crtc->state->active,
6858                         "attached crtc is active, but connector isn't\n");
6859                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6860                         "best encoder set without crtc!\n");
6861         }
6862 }
6863
6864 int intel_connector_init(struct intel_connector *connector)
6865 {
6866         drm_atomic_helper_connector_reset(&connector->base);
6867
6868         if (!connector->base.state)
6869                 return -ENOMEM;
6870
6871         return 0;
6872 }
6873
6874 struct intel_connector *intel_connector_alloc(void)
6875 {
6876         struct intel_connector *connector;
6877
6878         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6879         if (!connector)
6880                 return NULL;
6881
6882         if (intel_connector_init(connector) < 0) {
6883                 kfree(connector);
6884                 return NULL;
6885         }
6886
6887         return connector;
6888 }
6889
6890 /* Simple connector->get_hw_state implementation for encoders that support only
6891  * one connector and no cloning and hence the encoder state determines the state
6892  * of the connector. */
6893 bool intel_connector_get_hw_state(struct intel_connector *connector)
6894 {
6895         enum pipe pipe = 0;
6896         struct intel_encoder *encoder = connector->encoder;
6897
6898         return encoder->get_hw_state(encoder, &pipe);
6899 }
6900
6901 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6902 {
6903         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6904                 return crtc_state->fdi_lanes;
6905
6906         return 0;
6907 }
6908
6909 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6910                                      struct intel_crtc_state *pipe_config)
6911 {
6912         struct drm_atomic_state *state = pipe_config->base.state;
6913         struct intel_crtc *other_crtc;
6914         struct intel_crtc_state *other_crtc_state;
6915
6916         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6917                       pipe_name(pipe), pipe_config->fdi_lanes);
6918         if (pipe_config->fdi_lanes > 4) {
6919                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6920                               pipe_name(pipe), pipe_config->fdi_lanes);
6921                 return -EINVAL;
6922         }
6923
6924         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6925                 if (pipe_config->fdi_lanes > 2) {
6926                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6927                                       pipe_config->fdi_lanes);
6928                         return -EINVAL;
6929                 } else {
6930                         return 0;
6931                 }
6932         }
6933
6934         if (INTEL_INFO(dev)->num_pipes == 2)
6935                 return 0;
6936
6937         /* Ivybridge 3 pipe is really complicated */
6938         switch (pipe) {
6939         case PIPE_A:
6940                 return 0;
6941         case PIPE_B:
6942                 if (pipe_config->fdi_lanes <= 2)
6943                         return 0;
6944
6945                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6946                 other_crtc_state =
6947                         intel_atomic_get_crtc_state(state, other_crtc);
6948                 if (IS_ERR(other_crtc_state))
6949                         return PTR_ERR(other_crtc_state);
6950
6951                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6952                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6953                                       pipe_name(pipe), pipe_config->fdi_lanes);
6954                         return -EINVAL;
6955                 }
6956                 return 0;
6957         case PIPE_C:
6958                 if (pipe_config->fdi_lanes > 2) {
6959                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6960                                       pipe_name(pipe), pipe_config->fdi_lanes);
6961                         return -EINVAL;
6962                 }
6963
6964                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6965                 other_crtc_state =
6966                         intel_atomic_get_crtc_state(state, other_crtc);
6967                 if (IS_ERR(other_crtc_state))
6968                         return PTR_ERR(other_crtc_state);
6969
6970                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6971                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6972                         return -EINVAL;
6973                 }
6974                 return 0;
6975         default:
6976                 BUG();
6977         }
6978 }
6979
6980 #define RETRY 1
6981 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6982                                        struct intel_crtc_state *pipe_config)
6983 {
6984         struct drm_device *dev = intel_crtc->base.dev;
6985         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6986         int lane, link_bw, fdi_dotclock, ret;
6987         bool needs_recompute = false;
6988
6989 retry:
6990         /* FDI is a binary signal running at ~2.7GHz, encoding
6991          * each output octet as 10 bits. The actual frequency
6992          * is stored as a divider into a 100MHz clock, and the
6993          * mode pixel clock is stored in units of 1KHz.
6994          * Hence the bw of each lane in terms of the mode signal
6995          * is:
6996          */
6997         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6998
6999         fdi_dotclock = adjusted_mode->crtc_clock;
7000
7001         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7002                                            pipe_config->pipe_bpp);
7003
7004         pipe_config->fdi_lanes = lane;
7005
7006         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7007                                link_bw, &pipe_config->fdi_m_n);
7008
7009         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7010         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7011                 pipe_config->pipe_bpp -= 2*3;
7012                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7013                               pipe_config->pipe_bpp);
7014                 needs_recompute = true;
7015                 pipe_config->bw_constrained = true;
7016
7017                 goto retry;
7018         }
7019
7020         if (needs_recompute)
7021                 return RETRY;
7022
7023         return ret;
7024 }
7025
7026 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7027                                      struct intel_crtc_state *pipe_config)
7028 {
7029         if (pipe_config->pipe_bpp > 24)
7030                 return false;
7031
7032         /* HSW can handle pixel rate up to cdclk? */
7033         if (IS_HASWELL(dev_priv))
7034                 return true;
7035
7036         /*
7037          * We compare against max which means we must take
7038          * the increased cdclk requirement into account when
7039          * calculating the new cdclk.
7040          *
7041          * Should measure whether using a lower cdclk w/o IPS
7042          */
7043         return ilk_pipe_pixel_rate(pipe_config) <=
7044                 dev_priv->max_cdclk_freq * 95 / 100;
7045 }
7046
7047 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7048                                    struct intel_crtc_state *pipe_config)
7049 {
7050         struct drm_device *dev = crtc->base.dev;
7051         struct drm_i915_private *dev_priv = to_i915(dev);
7052
7053         pipe_config->ips_enabled = i915.enable_ips &&
7054                 hsw_crtc_supports_ips(crtc) &&
7055                 pipe_config_supports_ips(dev_priv, pipe_config);
7056 }
7057
7058 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7059 {
7060         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7061
7062         /* GDG double wide on either pipe, otherwise pipe A only */
7063         return INTEL_INFO(dev_priv)->gen < 4 &&
7064                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7065 }
7066
7067 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7068                                      struct intel_crtc_state *pipe_config)
7069 {
7070         struct drm_device *dev = crtc->base.dev;
7071         struct drm_i915_private *dev_priv = to_i915(dev);
7072         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7073         int clock_limit = dev_priv->max_dotclk_freq;
7074
7075         if (INTEL_INFO(dev)->gen < 4) {
7076                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7077
7078                 /*
7079                  * Enable double wide mode when the dot clock
7080                  * is > 90% of the (display) core speed.
7081                  */
7082                 if (intel_crtc_supports_double_wide(crtc) &&
7083                     adjusted_mode->crtc_clock > clock_limit) {
7084                         clock_limit = dev_priv->max_dotclk_freq;
7085                         pipe_config->double_wide = true;
7086                 }
7087         }
7088
7089         if (adjusted_mode->crtc_clock > clock_limit) {
7090                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7091                               adjusted_mode->crtc_clock, clock_limit,
7092                               yesno(pipe_config->double_wide));
7093                 return -EINVAL;
7094         }
7095
7096         /*
7097          * Pipe horizontal size must be even in:
7098          * - DVO ganged mode
7099          * - LVDS dual channel mode
7100          * - Double wide pipe
7101          */
7102         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7103              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7104                 pipe_config->pipe_src_w &= ~1;
7105
7106         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7107          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7108          */
7109         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7110                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7111                 return -EINVAL;
7112
7113         if (HAS_IPS(dev))
7114                 hsw_compute_ips_config(crtc, pipe_config);
7115
7116         if (pipe_config->has_pch_encoder)
7117                 return ironlake_fdi_compute_config(crtc, pipe_config);
7118
7119         return 0;
7120 }
7121
7122 static int skylake_get_display_clock_speed(struct drm_device *dev)
7123 {
7124         struct drm_i915_private *dev_priv = to_i915(dev);
7125         uint32_t cdctl;
7126
7127         skl_dpll0_update(dev_priv);
7128
7129         if (dev_priv->cdclk_pll.vco == 0)
7130                 return dev_priv->cdclk_pll.ref;
7131
7132         cdctl = I915_READ(CDCLK_CTL);
7133
7134         if (dev_priv->cdclk_pll.vco == 8640000) {
7135                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7136                 case CDCLK_FREQ_450_432:
7137                         return 432000;
7138                 case CDCLK_FREQ_337_308:
7139                         return 308571;
7140                 case CDCLK_FREQ_540:
7141                         return 540000;
7142                 case CDCLK_FREQ_675_617:
7143                         return 617143;
7144                 default:
7145                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7146                 }
7147         } else {
7148                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7149                 case CDCLK_FREQ_450_432:
7150                         return 450000;
7151                 case CDCLK_FREQ_337_308:
7152                         return 337500;
7153                 case CDCLK_FREQ_540:
7154                         return 540000;
7155                 case CDCLK_FREQ_675_617:
7156                         return 675000;
7157                 default:
7158                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7159                 }
7160         }
7161
7162         return dev_priv->cdclk_pll.ref;
7163 }
7164
7165 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7166 {
7167         u32 val;
7168
7169         dev_priv->cdclk_pll.ref = 19200;
7170         dev_priv->cdclk_pll.vco = 0;
7171
7172         val = I915_READ(BXT_DE_PLL_ENABLE);
7173         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7174                 return;
7175
7176         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7177                 return;
7178
7179         val = I915_READ(BXT_DE_PLL_CTL);
7180         dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7181                 dev_priv->cdclk_pll.ref;
7182 }
7183
7184 static int broxton_get_display_clock_speed(struct drm_device *dev)
7185 {
7186         struct drm_i915_private *dev_priv = to_i915(dev);
7187         u32 divider;
7188         int div, vco;
7189
7190         bxt_de_pll_update(dev_priv);
7191
7192         vco = dev_priv->cdclk_pll.vco;
7193         if (vco == 0)
7194                 return dev_priv->cdclk_pll.ref;
7195
7196         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7197
7198         switch (divider) {
7199         case BXT_CDCLK_CD2X_DIV_SEL_1:
7200                 div = 2;
7201                 break;
7202         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7203                 div = 3;
7204                 break;
7205         case BXT_CDCLK_CD2X_DIV_SEL_2:
7206                 div = 4;
7207                 break;
7208         case BXT_CDCLK_CD2X_DIV_SEL_4:
7209                 div = 8;
7210                 break;
7211         default:
7212                 MISSING_CASE(divider);
7213                 return dev_priv->cdclk_pll.ref;
7214         }
7215
7216         return DIV_ROUND_CLOSEST(vco, div);
7217 }
7218
7219 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7220 {
7221         struct drm_i915_private *dev_priv = to_i915(dev);
7222         uint32_t lcpll = I915_READ(LCPLL_CTL);
7223         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7224
7225         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7226                 return 800000;
7227         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7228                 return 450000;
7229         else if (freq == LCPLL_CLK_FREQ_450)
7230                 return 450000;
7231         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7232                 return 540000;
7233         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7234                 return 337500;
7235         else
7236                 return 675000;
7237 }
7238
7239 static int haswell_get_display_clock_speed(struct drm_device *dev)
7240 {
7241         struct drm_i915_private *dev_priv = to_i915(dev);
7242         uint32_t lcpll = I915_READ(LCPLL_CTL);
7243         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7244
7245         if (lcpll & LCPLL_CD_SOURCE_FCLK)
7246                 return 800000;
7247         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7248                 return 450000;
7249         else if (freq == LCPLL_CLK_FREQ_450)
7250                 return 450000;
7251         else if (IS_HSW_ULT(dev))
7252                 return 337500;
7253         else
7254                 return 540000;
7255 }
7256
7257 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7258 {
7259         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7260                                       CCK_DISPLAY_CLOCK_CONTROL);
7261 }
7262
7263 static int ilk_get_display_clock_speed(struct drm_device *dev)
7264 {
7265         return 450000;
7266 }
7267
7268 static int i945_get_display_clock_speed(struct drm_device *dev)
7269 {
7270         return 400000;
7271 }
7272
7273 static int i915_get_display_clock_speed(struct drm_device *dev)
7274 {
7275         return 333333;
7276 }
7277
7278 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7279 {
7280         return 200000;
7281 }
7282
7283 static int pnv_get_display_clock_speed(struct drm_device *dev)
7284 {
7285         u16 gcfgc = 0;
7286
7287         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7288
7289         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7290         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7291                 return 266667;
7292         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7293                 return 333333;
7294         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7295                 return 444444;
7296         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7297                 return 200000;
7298         default:
7299                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7300         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7301                 return 133333;
7302         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7303                 return 166667;
7304         }
7305 }
7306
7307 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7308 {
7309         u16 gcfgc = 0;
7310
7311         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
7312
7313         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7314                 return 133333;
7315         else {
7316                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7317                 case GC_DISPLAY_CLOCK_333_MHZ:
7318                         return 333333;
7319                 default:
7320                 case GC_DISPLAY_CLOCK_190_200_MHZ:
7321                         return 190000;
7322                 }
7323         }
7324 }
7325
7326 static int i865_get_display_clock_speed(struct drm_device *dev)
7327 {
7328         return 266667;
7329 }
7330
7331 static int i85x_get_display_clock_speed(struct drm_device *dev)
7332 {
7333         u16 hpllcc = 0;
7334
7335         /*
7336          * 852GM/852GMV only supports 133 MHz and the HPLLCC
7337          * encoding is different :(
7338          * FIXME is this the right way to detect 852GM/852GMV?
7339          */
7340         if (dev->pdev->revision == 0x1)
7341                 return 133333;
7342
7343         pci_bus_read_config_word(dev->pdev->bus,
7344                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7345
7346         /* Assume that the hardware is in the high speed state.  This
7347          * should be the default.
7348          */
7349         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7350         case GC_CLOCK_133_200:
7351         case GC_CLOCK_133_200_2:
7352         case GC_CLOCK_100_200:
7353                 return 200000;
7354         case GC_CLOCK_166_250:
7355                 return 250000;
7356         case GC_CLOCK_100_133:
7357                 return 133333;
7358         case GC_CLOCK_133_266:
7359         case GC_CLOCK_133_266_2:
7360         case GC_CLOCK_166_266:
7361                 return 266667;
7362         }
7363
7364         /* Shouldn't happen */
7365         return 0;
7366 }
7367
7368 static int i830_get_display_clock_speed(struct drm_device *dev)
7369 {
7370         return 133333;
7371 }
7372
7373 static unsigned int intel_hpll_vco(struct drm_device *dev)
7374 {
7375         struct drm_i915_private *dev_priv = to_i915(dev);
7376         static const unsigned int blb_vco[8] = {
7377                 [0] = 3200000,
7378                 [1] = 4000000,
7379                 [2] = 5333333,
7380                 [3] = 4800000,
7381                 [4] = 6400000,
7382         };
7383         static const unsigned int pnv_vco[8] = {
7384                 [0] = 3200000,
7385                 [1] = 4000000,
7386                 [2] = 5333333,
7387                 [3] = 4800000,
7388                 [4] = 2666667,
7389         };
7390         static const unsigned int cl_vco[8] = {
7391                 [0] = 3200000,
7392                 [1] = 4000000,
7393                 [2] = 5333333,
7394                 [3] = 6400000,
7395                 [4] = 3333333,
7396                 [5] = 3566667,
7397                 [6] = 4266667,
7398         };
7399         static const unsigned int elk_vco[8] = {
7400                 [0] = 3200000,
7401                 [1] = 4000000,
7402                 [2] = 5333333,
7403                 [3] = 4800000,
7404         };
7405         static const unsigned int ctg_vco[8] = {
7406                 [0] = 3200000,
7407                 [1] = 4000000,
7408                 [2] = 5333333,
7409                 [3] = 6400000,
7410                 [4] = 2666667,
7411                 [5] = 4266667,
7412         };
7413         const unsigned int *vco_table;
7414         unsigned int vco;
7415         uint8_t tmp = 0;
7416
7417         /* FIXME other chipsets? */
7418         if (IS_GM45(dev))
7419                 vco_table = ctg_vco;
7420         else if (IS_G4X(dev))
7421                 vco_table = elk_vco;
7422         else if (IS_CRESTLINE(dev))
7423                 vco_table = cl_vco;
7424         else if (IS_PINEVIEW(dev))
7425                 vco_table = pnv_vco;
7426         else if (IS_G33(dev))
7427                 vco_table = blb_vco;
7428         else
7429                 return 0;
7430
7431         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7432
7433         vco = vco_table[tmp & 0x7];
7434         if (vco == 0)
7435                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7436         else
7437                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7438
7439         return vco;
7440 }
7441
7442 static int gm45_get_display_clock_speed(struct drm_device *dev)
7443 {
7444         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7445         uint16_t tmp = 0;
7446
7447         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7448
7449         cdclk_sel = (tmp >> 12) & 0x1;
7450
7451         switch (vco) {
7452         case 2666667:
7453         case 4000000:
7454         case 5333333:
7455                 return cdclk_sel ? 333333 : 222222;
7456         case 3200000:
7457                 return cdclk_sel ? 320000 : 228571;
7458         default:
7459                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7460                 return 222222;
7461         }
7462 }
7463
7464 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7465 {
7466         static const uint8_t div_3200[] = { 16, 10,  8 };
7467         static const uint8_t div_4000[] = { 20, 12, 10 };
7468         static const uint8_t div_5333[] = { 24, 16, 14 };
7469         const uint8_t *div_table;
7470         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7471         uint16_t tmp = 0;
7472
7473         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7474
7475         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7476
7477         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7478                 goto fail;
7479
7480         switch (vco) {
7481         case 3200000:
7482                 div_table = div_3200;
7483                 break;
7484         case 4000000:
7485                 div_table = div_4000;
7486                 break;
7487         case 5333333:
7488                 div_table = div_5333;
7489                 break;
7490         default:
7491                 goto fail;
7492         }
7493
7494         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7495
7496 fail:
7497         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7498         return 200000;
7499 }
7500
7501 static int g33_get_display_clock_speed(struct drm_device *dev)
7502 {
7503         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7504         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7505         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7506         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7507         const uint8_t *div_table;
7508         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7509         uint16_t tmp = 0;
7510
7511         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7512
7513         cdclk_sel = (tmp >> 4) & 0x7;
7514
7515         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7516                 goto fail;
7517
7518         switch (vco) {
7519         case 3200000:
7520                 div_table = div_3200;
7521                 break;
7522         case 4000000:
7523                 div_table = div_4000;
7524                 break;
7525         case 4800000:
7526                 div_table = div_4800;
7527                 break;
7528         case 5333333:
7529                 div_table = div_5333;
7530                 break;
7531         default:
7532                 goto fail;
7533         }
7534
7535         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7536
7537 fail:
7538         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7539         return 190476;
7540 }
7541
7542 static void
7543 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7544 {
7545         while (*num > DATA_LINK_M_N_MASK ||
7546                *den > DATA_LINK_M_N_MASK) {
7547                 *num >>= 1;
7548                 *den >>= 1;
7549         }
7550 }
7551
7552 static void compute_m_n(unsigned int m, unsigned int n,
7553                         uint32_t *ret_m, uint32_t *ret_n)
7554 {
7555         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7556         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7557         intel_reduce_m_n_ratio(ret_m, ret_n);
7558 }
7559
7560 void
7561 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7562                        int pixel_clock, int link_clock,
7563                        struct intel_link_m_n *m_n)
7564 {
7565         m_n->tu = 64;
7566
7567         compute_m_n(bits_per_pixel * pixel_clock,
7568                     link_clock * nlanes * 8,
7569                     &m_n->gmch_m, &m_n->gmch_n);
7570
7571         compute_m_n(pixel_clock, link_clock,
7572                     &m_n->link_m, &m_n->link_n);
7573 }
7574
7575 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7576 {
7577         if (i915.panel_use_ssc >= 0)
7578                 return i915.panel_use_ssc != 0;
7579         return dev_priv->vbt.lvds_use_ssc
7580                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7581 }
7582
7583 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7584 {
7585         return (1 << dpll->n) << 16 | dpll->m2;
7586 }
7587
7588 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7589 {
7590         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7591 }
7592
7593 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7594                                      struct intel_crtc_state *crtc_state,
7595                                      struct dpll *reduced_clock)
7596 {
7597         struct drm_device *dev = crtc->base.dev;
7598         u32 fp, fp2 = 0;
7599
7600         if (IS_PINEVIEW(dev)) {
7601                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7602                 if (reduced_clock)
7603                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7604         } else {
7605                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7606                 if (reduced_clock)
7607                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7608         }
7609
7610         crtc_state->dpll_hw_state.fp0 = fp;
7611
7612         crtc->lowfreq_avail = false;
7613         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7614             reduced_clock) {
7615                 crtc_state->dpll_hw_state.fp1 = fp2;
7616                 crtc->lowfreq_avail = true;
7617         } else {
7618                 crtc_state->dpll_hw_state.fp1 = fp;
7619         }
7620 }
7621
7622 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7623                 pipe)
7624 {
7625         u32 reg_val;
7626
7627         /*
7628          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7629          * and set it to a reasonable value instead.
7630          */
7631         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7632         reg_val &= 0xffffff00;
7633         reg_val |= 0x00000030;
7634         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7635
7636         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7637         reg_val &= 0x8cffffff;
7638         reg_val = 0x8c000000;
7639         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7640
7641         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7642         reg_val &= 0xffffff00;
7643         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7644
7645         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7646         reg_val &= 0x00ffffff;
7647         reg_val |= 0xb0000000;
7648         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7649 }
7650
7651 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7652                                          struct intel_link_m_n *m_n)
7653 {
7654         struct drm_device *dev = crtc->base.dev;
7655         struct drm_i915_private *dev_priv = to_i915(dev);
7656         int pipe = crtc->pipe;
7657
7658         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7659         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7660         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7661         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7662 }
7663
7664 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7665                                          struct intel_link_m_n *m_n,
7666                                          struct intel_link_m_n *m2_n2)
7667 {
7668         struct drm_device *dev = crtc->base.dev;
7669         struct drm_i915_private *dev_priv = to_i915(dev);
7670         int pipe = crtc->pipe;
7671         enum transcoder transcoder = crtc->config->cpu_transcoder;
7672
7673         if (INTEL_INFO(dev)->gen >= 5) {
7674                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7675                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7676                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7677                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7678                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7679                  * for gen < 8) and if DRRS is supported (to make sure the
7680                  * registers are not unnecessarily accessed).
7681                  */
7682                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7683                         crtc->config->has_drrs) {
7684                         I915_WRITE(PIPE_DATA_M2(transcoder),
7685                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7686                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7687                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7688                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7689                 }
7690         } else {
7691                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7692                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7693                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7694                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7695         }
7696 }
7697
7698 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7699 {
7700         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7701
7702         if (m_n == M1_N1) {
7703                 dp_m_n = &crtc->config->dp_m_n;
7704                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7705         } else if (m_n == M2_N2) {
7706
7707                 /*
7708                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7709                  * needs to be programmed into M1_N1.
7710                  */
7711                 dp_m_n = &crtc->config->dp_m2_n2;
7712         } else {
7713                 DRM_ERROR("Unsupported divider value\n");
7714                 return;
7715         }
7716
7717         if (crtc->config->has_pch_encoder)
7718                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7719         else
7720                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7721 }
7722
7723 static void vlv_compute_dpll(struct intel_crtc *crtc,
7724                              struct intel_crtc_state *pipe_config)
7725 {
7726         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7727                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7728         if (crtc->pipe != PIPE_A)
7729                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7730
7731         /* DPLL not used with DSI, but still need the rest set up */
7732         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7733                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7734                         DPLL_EXT_BUFFER_ENABLE_VLV;
7735
7736         pipe_config->dpll_hw_state.dpll_md =
7737                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7738 }
7739
7740 static void chv_compute_dpll(struct intel_crtc *crtc,
7741                              struct intel_crtc_state *pipe_config)
7742 {
7743         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7744                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7745         if (crtc->pipe != PIPE_A)
7746                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7747
7748         /* DPLL not used with DSI, but still need the rest set up */
7749         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7750                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7751
7752         pipe_config->dpll_hw_state.dpll_md =
7753                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7754 }
7755
7756 static void vlv_prepare_pll(struct intel_crtc *crtc,
7757                             const struct intel_crtc_state *pipe_config)
7758 {
7759         struct drm_device *dev = crtc->base.dev;
7760         struct drm_i915_private *dev_priv = to_i915(dev);
7761         enum pipe pipe = crtc->pipe;
7762         u32 mdiv;
7763         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7764         u32 coreclk, reg_val;
7765
7766         /* Enable Refclk */
7767         I915_WRITE(DPLL(pipe),
7768                    pipe_config->dpll_hw_state.dpll &
7769                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7770
7771         /* No need to actually set up the DPLL with DSI */
7772         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7773                 return;
7774
7775         mutex_lock(&dev_priv->sb_lock);
7776
7777         bestn = pipe_config->dpll.n;
7778         bestm1 = pipe_config->dpll.m1;
7779         bestm2 = pipe_config->dpll.m2;
7780         bestp1 = pipe_config->dpll.p1;
7781         bestp2 = pipe_config->dpll.p2;
7782
7783         /* See eDP HDMI DPIO driver vbios notes doc */
7784
7785         /* PLL B needs special handling */
7786         if (pipe == PIPE_B)
7787                 vlv_pllb_recal_opamp(dev_priv, pipe);
7788
7789         /* Set up Tx target for periodic Rcomp update */
7790         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7791
7792         /* Disable target IRef on PLL */
7793         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7794         reg_val &= 0x00ffffff;
7795         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7796
7797         /* Disable fast lock */
7798         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7799
7800         /* Set idtafcrecal before PLL is enabled */
7801         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7802         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7803         mdiv |= ((bestn << DPIO_N_SHIFT));
7804         mdiv |= (1 << DPIO_K_SHIFT);
7805
7806         /*
7807          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7808          * but we don't support that).
7809          * Note: don't use the DAC post divider as it seems unstable.
7810          */
7811         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7812         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7813
7814         mdiv |= DPIO_ENABLE_CALIBRATION;
7815         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7816
7817         /* Set HBR and RBR LPF coefficients */
7818         if (pipe_config->port_clock == 162000 ||
7819             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7820             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7821                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7822                                  0x009f0003);
7823         else
7824                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7825                                  0x00d0000f);
7826
7827         if (intel_crtc_has_dp_encoder(pipe_config)) {
7828                 /* Use SSC source */
7829                 if (pipe == PIPE_A)
7830                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7831                                          0x0df40000);
7832                 else
7833                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7834                                          0x0df70000);
7835         } else { /* HDMI or VGA */
7836                 /* Use bend source */
7837                 if (pipe == PIPE_A)
7838                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7839                                          0x0df70000);
7840                 else
7841                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7842                                          0x0df40000);
7843         }
7844
7845         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7846         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7847         if (intel_crtc_has_dp_encoder(crtc->config))
7848                 coreclk |= 0x01000000;
7849         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7850
7851         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7852         mutex_unlock(&dev_priv->sb_lock);
7853 }
7854
7855 static void chv_prepare_pll(struct intel_crtc *crtc,
7856                             const struct intel_crtc_state *pipe_config)
7857 {
7858         struct drm_device *dev = crtc->base.dev;
7859         struct drm_i915_private *dev_priv = to_i915(dev);
7860         enum pipe pipe = crtc->pipe;
7861         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7862         u32 loopfilter, tribuf_calcntr;
7863         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7864         u32 dpio_val;
7865         int vco;
7866
7867         /* Enable Refclk and SSC */
7868         I915_WRITE(DPLL(pipe),
7869                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7870
7871         /* No need to actually set up the DPLL with DSI */
7872         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7873                 return;
7874
7875         bestn = pipe_config->dpll.n;
7876         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7877         bestm1 = pipe_config->dpll.m1;
7878         bestm2 = pipe_config->dpll.m2 >> 22;
7879         bestp1 = pipe_config->dpll.p1;
7880         bestp2 = pipe_config->dpll.p2;
7881         vco = pipe_config->dpll.vco;
7882         dpio_val = 0;
7883         loopfilter = 0;
7884
7885         mutex_lock(&dev_priv->sb_lock);
7886
7887         /* p1 and p2 divider */
7888         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7889                         5 << DPIO_CHV_S1_DIV_SHIFT |
7890                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7891                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7892                         1 << DPIO_CHV_K_DIV_SHIFT);
7893
7894         /* Feedback post-divider - m2 */
7895         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7896
7897         /* Feedback refclk divider - n and m1 */
7898         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7899                         DPIO_CHV_M1_DIV_BY_2 |
7900                         1 << DPIO_CHV_N_DIV_SHIFT);
7901
7902         /* M2 fraction division */
7903         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7904
7905         /* M2 fraction division enable */
7906         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7907         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7908         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7909         if (bestm2_frac)
7910                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7911         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7912
7913         /* Program digital lock detect threshold */
7914         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7915         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7916                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7917         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7918         if (!bestm2_frac)
7919                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7920         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7921
7922         /* Loop filter */
7923         if (vco == 5400000) {
7924                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7925                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7926                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7927                 tribuf_calcntr = 0x9;
7928         } else if (vco <= 6200000) {
7929                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7930                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7931                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7932                 tribuf_calcntr = 0x9;
7933         } else if (vco <= 6480000) {
7934                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7935                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7936                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7937                 tribuf_calcntr = 0x8;
7938         } else {
7939                 /* Not supported. Apply the same limits as in the max case */
7940                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7941                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7942                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7943                 tribuf_calcntr = 0;
7944         }
7945         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7946
7947         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7948         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7949         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7950         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7951
7952         /* AFC Recal */
7953         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7954                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7955                         DPIO_AFC_RECAL);
7956
7957         mutex_unlock(&dev_priv->sb_lock);
7958 }
7959
7960 /**
7961  * vlv_force_pll_on - forcibly enable just the PLL
7962  * @dev_priv: i915 private structure
7963  * @pipe: pipe PLL to enable
7964  * @dpll: PLL configuration
7965  *
7966  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7967  * in cases where we need the PLL enabled even when @pipe is not going to
7968  * be enabled.
7969  */
7970 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7971                      const struct dpll *dpll)
7972 {
7973         struct intel_crtc *crtc =
7974                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7975         struct intel_crtc_state *pipe_config;
7976
7977         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7978         if (!pipe_config)
7979                 return -ENOMEM;
7980
7981         pipe_config->base.crtc = &crtc->base;
7982         pipe_config->pixel_multiplier = 1;
7983         pipe_config->dpll = *dpll;
7984
7985         if (IS_CHERRYVIEW(dev)) {
7986                 chv_compute_dpll(crtc, pipe_config);
7987                 chv_prepare_pll(crtc, pipe_config);
7988                 chv_enable_pll(crtc, pipe_config);
7989         } else {
7990                 vlv_compute_dpll(crtc, pipe_config);
7991                 vlv_prepare_pll(crtc, pipe_config);
7992                 vlv_enable_pll(crtc, pipe_config);
7993         }
7994
7995         kfree(pipe_config);
7996
7997         return 0;
7998 }
7999
8000 /**
8001  * vlv_force_pll_off - forcibly disable just the PLL
8002  * @dev_priv: i915 private structure
8003  * @pipe: pipe PLL to disable
8004  *
8005  * Disable the PLL for @pipe. To be used in cases where we need
8006  * the PLL enabled even when @pipe is not going to be enabled.
8007  */
8008 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8009 {
8010         if (IS_CHERRYVIEW(dev))
8011                 chv_disable_pll(to_i915(dev), pipe);
8012         else
8013                 vlv_disable_pll(to_i915(dev), pipe);
8014 }
8015
8016 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8017                               struct intel_crtc_state *crtc_state,
8018                               struct dpll *reduced_clock)
8019 {
8020         struct drm_device *dev = crtc->base.dev;
8021         struct drm_i915_private *dev_priv = to_i915(dev);
8022         u32 dpll;
8023         struct dpll *clock = &crtc_state->dpll;
8024
8025         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8026
8027         dpll = DPLL_VGA_MODE_DIS;
8028
8029         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8030                 dpll |= DPLLB_MODE_LVDS;
8031         else
8032                 dpll |= DPLLB_MODE_DAC_SERIAL;
8033
8034         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8035                 dpll |= (crtc_state->pixel_multiplier - 1)
8036                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8037         }
8038
8039         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8040             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8041                 dpll |= DPLL_SDVO_HIGH_SPEED;
8042
8043         if (intel_crtc_has_dp_encoder(crtc_state))
8044                 dpll |= DPLL_SDVO_HIGH_SPEED;
8045
8046         /* compute bitmask from p1 value */
8047         if (IS_PINEVIEW(dev))
8048                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8049         else {
8050                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8051                 if (IS_G4X(dev) && reduced_clock)
8052                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8053         }
8054         switch (clock->p2) {
8055         case 5:
8056                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8057                 break;
8058         case 7:
8059                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8060                 break;
8061         case 10:
8062                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8063                 break;
8064         case 14:
8065                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8066                 break;
8067         }
8068         if (INTEL_INFO(dev)->gen >= 4)
8069                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8070
8071         if (crtc_state->sdvo_tv_clock)
8072                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8073         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8074                  intel_panel_use_ssc(dev_priv))
8075                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8076         else
8077                 dpll |= PLL_REF_INPUT_DREFCLK;
8078
8079         dpll |= DPLL_VCO_ENABLE;
8080         crtc_state->dpll_hw_state.dpll = dpll;
8081
8082         if (INTEL_INFO(dev)->gen >= 4) {
8083                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8084                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8085                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8086         }
8087 }
8088
8089 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8090                               struct intel_crtc_state *crtc_state,
8091                               struct dpll *reduced_clock)
8092 {
8093         struct drm_device *dev = crtc->base.dev;
8094         struct drm_i915_private *dev_priv = to_i915(dev);
8095         u32 dpll;
8096         struct dpll *clock = &crtc_state->dpll;
8097
8098         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8099
8100         dpll = DPLL_VGA_MODE_DIS;
8101
8102         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8103                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8104         } else {
8105                 if (clock->p1 == 2)
8106                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8107                 else
8108                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8109                 if (clock->p2 == 4)
8110                         dpll |= PLL_P2_DIVIDE_BY_4;
8111         }
8112
8113         if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8114                 dpll |= DPLL_DVO_2X_MODE;
8115
8116         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8117             intel_panel_use_ssc(dev_priv))
8118                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8119         else
8120                 dpll |= PLL_REF_INPUT_DREFCLK;
8121
8122         dpll |= DPLL_VCO_ENABLE;
8123         crtc_state->dpll_hw_state.dpll = dpll;
8124 }
8125
8126 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8127 {
8128         struct drm_device *dev = intel_crtc->base.dev;
8129         struct drm_i915_private *dev_priv = to_i915(dev);
8130         enum pipe pipe = intel_crtc->pipe;
8131         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8132         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8133         uint32_t crtc_vtotal, crtc_vblank_end;
8134         int vsyncshift = 0;
8135
8136         /* We need to be careful not to changed the adjusted mode, for otherwise
8137          * the hw state checker will get angry at the mismatch. */
8138         crtc_vtotal = adjusted_mode->crtc_vtotal;
8139         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8140
8141         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8142                 /* the chip adds 2 halflines automatically */
8143                 crtc_vtotal -= 1;
8144                 crtc_vblank_end -= 1;
8145
8146                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8147                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8148                 else
8149                         vsyncshift = adjusted_mode->crtc_hsync_start -
8150                                 adjusted_mode->crtc_htotal / 2;
8151                 if (vsyncshift < 0)
8152                         vsyncshift += adjusted_mode->crtc_htotal;
8153         }
8154
8155         if (INTEL_INFO(dev)->gen > 3)
8156                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8157
8158         I915_WRITE(HTOTAL(cpu_transcoder),
8159                    (adjusted_mode->crtc_hdisplay - 1) |
8160                    ((adjusted_mode->crtc_htotal - 1) << 16));
8161         I915_WRITE(HBLANK(cpu_transcoder),
8162                    (adjusted_mode->crtc_hblank_start - 1) |
8163                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
8164         I915_WRITE(HSYNC(cpu_transcoder),
8165                    (adjusted_mode->crtc_hsync_start - 1) |
8166                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
8167
8168         I915_WRITE(VTOTAL(cpu_transcoder),
8169                    (adjusted_mode->crtc_vdisplay - 1) |
8170                    ((crtc_vtotal - 1) << 16));
8171         I915_WRITE(VBLANK(cpu_transcoder),
8172                    (adjusted_mode->crtc_vblank_start - 1) |
8173                    ((crtc_vblank_end - 1) << 16));
8174         I915_WRITE(VSYNC(cpu_transcoder),
8175                    (adjusted_mode->crtc_vsync_start - 1) |
8176                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
8177
8178         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8179          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8180          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8181          * bits. */
8182         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8183             (pipe == PIPE_B || pipe == PIPE_C))
8184                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8185
8186 }
8187
8188 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8189 {
8190         struct drm_device *dev = intel_crtc->base.dev;
8191         struct drm_i915_private *dev_priv = to_i915(dev);
8192         enum pipe pipe = intel_crtc->pipe;
8193
8194         /* pipesrc controls the size that is scaled from, which should
8195          * always be the user's requested size.
8196          */
8197         I915_WRITE(PIPESRC(pipe),
8198                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
8199                    (intel_crtc->config->pipe_src_h - 1));
8200 }
8201
8202 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8203                                    struct intel_crtc_state *pipe_config)
8204 {
8205         struct drm_device *dev = crtc->base.dev;
8206         struct drm_i915_private *dev_priv = to_i915(dev);
8207         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8208         uint32_t tmp;
8209
8210         tmp = I915_READ(HTOTAL(cpu_transcoder));
8211         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8212         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8213         tmp = I915_READ(HBLANK(cpu_transcoder));
8214         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8215         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8216         tmp = I915_READ(HSYNC(cpu_transcoder));
8217         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8218         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8219
8220         tmp = I915_READ(VTOTAL(cpu_transcoder));
8221         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8222         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8223         tmp = I915_READ(VBLANK(cpu_transcoder));
8224         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8225         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8226         tmp = I915_READ(VSYNC(cpu_transcoder));
8227         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8228         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8229
8230         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8231                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8232                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8233                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8234         }
8235 }
8236
8237 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8238                                     struct intel_crtc_state *pipe_config)
8239 {
8240         struct drm_device *dev = crtc->base.dev;
8241         struct drm_i915_private *dev_priv = to_i915(dev);
8242         u32 tmp;
8243
8244         tmp = I915_READ(PIPESRC(crtc->pipe));
8245         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8246         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8247
8248         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8249         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8250 }
8251
8252 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8253                                  struct intel_crtc_state *pipe_config)
8254 {
8255         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8256         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8257         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8258         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8259
8260         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8261         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8262         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8263         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8264
8265         mode->flags = pipe_config->base.adjusted_mode.flags;
8266         mode->type = DRM_MODE_TYPE_DRIVER;
8267
8268         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8269         mode->flags |= pipe_config->base.adjusted_mode.flags;
8270
8271         mode->hsync = drm_mode_hsync(mode);
8272         mode->vrefresh = drm_mode_vrefresh(mode);
8273         drm_mode_set_name(mode);
8274 }
8275
8276 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8277 {
8278         struct drm_device *dev = intel_crtc->base.dev;
8279         struct drm_i915_private *dev_priv = to_i915(dev);
8280         uint32_t pipeconf;
8281
8282         pipeconf = 0;
8283
8284         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8285             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8286                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8287
8288         if (intel_crtc->config->double_wide)
8289                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8290
8291         /* only g4x and later have fancy bpc/dither controls */
8292         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8293                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8294                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8295                         pipeconf |= PIPECONF_DITHER_EN |
8296                                     PIPECONF_DITHER_TYPE_SP;
8297
8298                 switch (intel_crtc->config->pipe_bpp) {
8299                 case 18:
8300                         pipeconf |= PIPECONF_6BPC;
8301                         break;
8302                 case 24:
8303                         pipeconf |= PIPECONF_8BPC;
8304                         break;
8305                 case 30:
8306                         pipeconf |= PIPECONF_10BPC;
8307                         break;
8308                 default:
8309                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8310                         BUG();
8311                 }
8312         }
8313
8314         if (HAS_PIPE_CXSR(dev)) {
8315                 if (intel_crtc->lowfreq_avail) {
8316                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8317                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8318                 } else {
8319                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8320                 }
8321         }
8322
8323         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8324                 if (INTEL_INFO(dev)->gen < 4 ||
8325                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8326                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8327                 else
8328                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8329         } else
8330                 pipeconf |= PIPECONF_PROGRESSIVE;
8331
8332         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8333              intel_crtc->config->limited_color_range)
8334                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8335
8336         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8337         POSTING_READ(PIPECONF(intel_crtc->pipe));
8338 }
8339
8340 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8341                                    struct intel_crtc_state *crtc_state)
8342 {
8343         struct drm_device *dev = crtc->base.dev;
8344         struct drm_i915_private *dev_priv = to_i915(dev);
8345         const struct intel_limit *limit;
8346         int refclk = 48000;
8347
8348         memset(&crtc_state->dpll_hw_state, 0,
8349                sizeof(crtc_state->dpll_hw_state));
8350
8351         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8352                 if (intel_panel_use_ssc(dev_priv)) {
8353                         refclk = dev_priv->vbt.lvds_ssc_freq;
8354                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8355                 }
8356
8357                 limit = &intel_limits_i8xx_lvds;
8358         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8359                 limit = &intel_limits_i8xx_dvo;
8360         } else {
8361                 limit = &intel_limits_i8xx_dac;
8362         }
8363
8364         if (!crtc_state->clock_set &&
8365             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8366                                  refclk, NULL, &crtc_state->dpll)) {
8367                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8368                 return -EINVAL;
8369         }
8370
8371         i8xx_compute_dpll(crtc, crtc_state, NULL);
8372
8373         return 0;
8374 }
8375
8376 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8377                                   struct intel_crtc_state *crtc_state)
8378 {
8379         struct drm_device *dev = crtc->base.dev;
8380         struct drm_i915_private *dev_priv = to_i915(dev);
8381         const struct intel_limit *limit;
8382         int refclk = 96000;
8383
8384         memset(&crtc_state->dpll_hw_state, 0,
8385                sizeof(crtc_state->dpll_hw_state));
8386
8387         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8388                 if (intel_panel_use_ssc(dev_priv)) {
8389                         refclk = dev_priv->vbt.lvds_ssc_freq;
8390                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8391                 }
8392
8393                 if (intel_is_dual_link_lvds(dev))
8394                         limit = &intel_limits_g4x_dual_channel_lvds;
8395                 else
8396                         limit = &intel_limits_g4x_single_channel_lvds;
8397         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8398                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8399                 limit = &intel_limits_g4x_hdmi;
8400         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8401                 limit = &intel_limits_g4x_sdvo;
8402         } else {
8403                 /* The option is for other outputs */
8404                 limit = &intel_limits_i9xx_sdvo;
8405         }
8406
8407         if (!crtc_state->clock_set &&
8408             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8409                                 refclk, NULL, &crtc_state->dpll)) {
8410                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8411                 return -EINVAL;
8412         }
8413
8414         i9xx_compute_dpll(crtc, crtc_state, NULL);
8415
8416         return 0;
8417 }
8418
8419 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8420                                   struct intel_crtc_state *crtc_state)
8421 {
8422         struct drm_device *dev = crtc->base.dev;
8423         struct drm_i915_private *dev_priv = to_i915(dev);
8424         const struct intel_limit *limit;
8425         int refclk = 96000;
8426
8427         memset(&crtc_state->dpll_hw_state, 0,
8428                sizeof(crtc_state->dpll_hw_state));
8429
8430         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8431                 if (intel_panel_use_ssc(dev_priv)) {
8432                         refclk = dev_priv->vbt.lvds_ssc_freq;
8433                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8434                 }
8435
8436                 limit = &intel_limits_pineview_lvds;
8437         } else {
8438                 limit = &intel_limits_pineview_sdvo;
8439         }
8440
8441         if (!crtc_state->clock_set &&
8442             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8443                                 refclk, NULL, &crtc_state->dpll)) {
8444                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8445                 return -EINVAL;
8446         }
8447
8448         i9xx_compute_dpll(crtc, crtc_state, NULL);
8449
8450         return 0;
8451 }
8452
8453 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8454                                    struct intel_crtc_state *crtc_state)
8455 {
8456         struct drm_device *dev = crtc->base.dev;
8457         struct drm_i915_private *dev_priv = to_i915(dev);
8458         const struct intel_limit *limit;
8459         int refclk = 96000;
8460
8461         memset(&crtc_state->dpll_hw_state, 0,
8462                sizeof(crtc_state->dpll_hw_state));
8463
8464         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8465                 if (intel_panel_use_ssc(dev_priv)) {
8466                         refclk = dev_priv->vbt.lvds_ssc_freq;
8467                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8468                 }
8469
8470                 limit = &intel_limits_i9xx_lvds;
8471         } else {
8472                 limit = &intel_limits_i9xx_sdvo;
8473         }
8474
8475         if (!crtc_state->clock_set &&
8476             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8477                                  refclk, NULL, &crtc_state->dpll)) {
8478                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8479                 return -EINVAL;
8480         }
8481
8482         i9xx_compute_dpll(crtc, crtc_state, NULL);
8483
8484         return 0;
8485 }
8486
8487 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8488                                   struct intel_crtc_state *crtc_state)
8489 {
8490         int refclk = 100000;
8491         const struct intel_limit *limit = &intel_limits_chv;
8492
8493         memset(&crtc_state->dpll_hw_state, 0,
8494                sizeof(crtc_state->dpll_hw_state));
8495
8496         if (!crtc_state->clock_set &&
8497             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8498                                 refclk, NULL, &crtc_state->dpll)) {
8499                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8500                 return -EINVAL;
8501         }
8502
8503         chv_compute_dpll(crtc, crtc_state);
8504
8505         return 0;
8506 }
8507
8508 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8509                                   struct intel_crtc_state *crtc_state)
8510 {
8511         int refclk = 100000;
8512         const struct intel_limit *limit = &intel_limits_vlv;
8513
8514         memset(&crtc_state->dpll_hw_state, 0,
8515                sizeof(crtc_state->dpll_hw_state));
8516
8517         if (!crtc_state->clock_set &&
8518             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8519                                 refclk, NULL, &crtc_state->dpll)) {
8520                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8521                 return -EINVAL;
8522         }
8523
8524         vlv_compute_dpll(crtc, crtc_state);
8525
8526         return 0;
8527 }
8528
8529 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8530                                  struct intel_crtc_state *pipe_config)
8531 {
8532         struct drm_device *dev = crtc->base.dev;
8533         struct drm_i915_private *dev_priv = to_i915(dev);
8534         uint32_t tmp;
8535
8536         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8537                 return;
8538
8539         tmp = I915_READ(PFIT_CONTROL);
8540         if (!(tmp & PFIT_ENABLE))
8541                 return;
8542
8543         /* Check whether the pfit is attached to our pipe. */
8544         if (INTEL_INFO(dev)->gen < 4) {
8545                 if (crtc->pipe != PIPE_B)
8546                         return;
8547         } else {
8548                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8549                         return;
8550         }
8551
8552         pipe_config->gmch_pfit.control = tmp;
8553         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8554 }
8555
8556 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8557                                struct intel_crtc_state *pipe_config)
8558 {
8559         struct drm_device *dev = crtc->base.dev;
8560         struct drm_i915_private *dev_priv = to_i915(dev);
8561         int pipe = pipe_config->cpu_transcoder;
8562         struct dpll clock;
8563         u32 mdiv;
8564         int refclk = 100000;
8565
8566         /* In case of DSI, DPLL will not be used */
8567         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8568                 return;
8569
8570         mutex_lock(&dev_priv->sb_lock);
8571         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8572         mutex_unlock(&dev_priv->sb_lock);
8573
8574         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8575         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8576         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8577         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8578         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8579
8580         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8581 }
8582
8583 static void
8584 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8585                               struct intel_initial_plane_config *plane_config)
8586 {
8587         struct drm_device *dev = crtc->base.dev;
8588         struct drm_i915_private *dev_priv = to_i915(dev);
8589         u32 val, base, offset;
8590         int pipe = crtc->pipe, plane = crtc->plane;
8591         int fourcc, pixel_format;
8592         unsigned int aligned_height;
8593         struct drm_framebuffer *fb;
8594         struct intel_framebuffer *intel_fb;
8595
8596         val = I915_READ(DSPCNTR(plane));
8597         if (!(val & DISPLAY_PLANE_ENABLE))
8598                 return;
8599
8600         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8601         if (!intel_fb) {
8602                 DRM_DEBUG_KMS("failed to alloc fb\n");
8603                 return;
8604         }
8605
8606         fb = &intel_fb->base;
8607
8608         if (INTEL_INFO(dev)->gen >= 4) {
8609                 if (val & DISPPLANE_TILED) {
8610                         plane_config->tiling = I915_TILING_X;
8611                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8612                 }
8613         }
8614
8615         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8616         fourcc = i9xx_format_to_fourcc(pixel_format);
8617         fb->pixel_format = fourcc;
8618         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8619
8620         if (INTEL_INFO(dev)->gen >= 4) {
8621                 if (plane_config->tiling)
8622                         offset = I915_READ(DSPTILEOFF(plane));
8623                 else
8624                         offset = I915_READ(DSPLINOFF(plane));
8625                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8626         } else {
8627                 base = I915_READ(DSPADDR(plane));
8628         }
8629         plane_config->base = base;
8630
8631         val = I915_READ(PIPESRC(pipe));
8632         fb->width = ((val >> 16) & 0xfff) + 1;
8633         fb->height = ((val >> 0) & 0xfff) + 1;
8634
8635         val = I915_READ(DSPSTRIDE(pipe));
8636         fb->pitches[0] = val & 0xffffffc0;
8637
8638         aligned_height = intel_fb_align_height(dev, fb->height,
8639                                                fb->pixel_format,
8640                                                fb->modifier[0]);
8641
8642         plane_config->size = fb->pitches[0] * aligned_height;
8643
8644         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8645                       pipe_name(pipe), plane, fb->width, fb->height,
8646                       fb->bits_per_pixel, base, fb->pitches[0],
8647                       plane_config->size);
8648
8649         plane_config->fb = intel_fb;
8650 }
8651
8652 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8653                                struct intel_crtc_state *pipe_config)
8654 {
8655         struct drm_device *dev = crtc->base.dev;
8656         struct drm_i915_private *dev_priv = to_i915(dev);
8657         int pipe = pipe_config->cpu_transcoder;
8658         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8659         struct dpll clock;
8660         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8661         int refclk = 100000;
8662
8663         /* In case of DSI, DPLL will not be used */
8664         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8665                 return;
8666
8667         mutex_lock(&dev_priv->sb_lock);
8668         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8669         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8670         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8671         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8672         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8673         mutex_unlock(&dev_priv->sb_lock);
8674
8675         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8676         clock.m2 = (pll_dw0 & 0xff) << 22;
8677         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8678                 clock.m2 |= pll_dw2 & 0x3fffff;
8679         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8680         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8681         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8682
8683         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8684 }
8685
8686 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8687                                  struct intel_crtc_state *pipe_config)
8688 {
8689         struct drm_device *dev = crtc->base.dev;
8690         struct drm_i915_private *dev_priv = to_i915(dev);
8691         enum intel_display_power_domain power_domain;
8692         uint32_t tmp;
8693         bool ret;
8694
8695         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8696         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8697                 return false;
8698
8699         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8700         pipe_config->shared_dpll = NULL;
8701
8702         ret = false;
8703
8704         tmp = I915_READ(PIPECONF(crtc->pipe));
8705         if (!(tmp & PIPECONF_ENABLE))
8706                 goto out;
8707
8708         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8709                 switch (tmp & PIPECONF_BPC_MASK) {
8710                 case PIPECONF_6BPC:
8711                         pipe_config->pipe_bpp = 18;
8712                         break;
8713                 case PIPECONF_8BPC:
8714                         pipe_config->pipe_bpp = 24;
8715                         break;
8716                 case PIPECONF_10BPC:
8717                         pipe_config->pipe_bpp = 30;
8718                         break;
8719                 default:
8720                         break;
8721                 }
8722         }
8723
8724         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8725             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8726                 pipe_config->limited_color_range = true;
8727
8728         if (INTEL_INFO(dev)->gen < 4)
8729                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8730
8731         intel_get_pipe_timings(crtc, pipe_config);
8732         intel_get_pipe_src_size(crtc, pipe_config);
8733
8734         i9xx_get_pfit_config(crtc, pipe_config);
8735
8736         if (INTEL_INFO(dev)->gen >= 4) {
8737                 /* No way to read it out on pipes B and C */
8738                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8739                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8740                 else
8741                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8742                 pipe_config->pixel_multiplier =
8743                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8744                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8745                 pipe_config->dpll_hw_state.dpll_md = tmp;
8746         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8747                 tmp = I915_READ(DPLL(crtc->pipe));
8748                 pipe_config->pixel_multiplier =
8749                         ((tmp & SDVO_MULTIPLIER_MASK)
8750                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8751         } else {
8752                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8753                  * port and will be fixed up in the encoder->get_config
8754                  * function. */
8755                 pipe_config->pixel_multiplier = 1;
8756         }
8757         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8758         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8759                 /*
8760                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8761                  * on 830. Filter it out here so that we don't
8762                  * report errors due to that.
8763                  */
8764                 if (IS_I830(dev))
8765                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8766
8767                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8768                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8769         } else {
8770                 /* Mask out read-only status bits. */
8771                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8772                                                      DPLL_PORTC_READY_MASK |
8773                                                      DPLL_PORTB_READY_MASK);
8774         }
8775
8776         if (IS_CHERRYVIEW(dev))
8777                 chv_crtc_clock_get(crtc, pipe_config);
8778         else if (IS_VALLEYVIEW(dev))
8779                 vlv_crtc_clock_get(crtc, pipe_config);
8780         else
8781                 i9xx_crtc_clock_get(crtc, pipe_config);
8782
8783         /*
8784          * Normally the dotclock is filled in by the encoder .get_config()
8785          * but in case the pipe is enabled w/o any ports we need a sane
8786          * default.
8787          */
8788         pipe_config->base.adjusted_mode.crtc_clock =
8789                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8790
8791         ret = true;
8792
8793 out:
8794         intel_display_power_put(dev_priv, power_domain);
8795
8796         return ret;
8797 }
8798
8799 static void ironlake_init_pch_refclk(struct drm_device *dev)
8800 {
8801         struct drm_i915_private *dev_priv = to_i915(dev);
8802         struct intel_encoder *encoder;
8803         int i;
8804         u32 val, final;
8805         bool has_lvds = false;
8806         bool has_cpu_edp = false;
8807         bool has_panel = false;
8808         bool has_ck505 = false;
8809         bool can_ssc = false;
8810         bool using_ssc_source = false;
8811
8812         /* We need to take the global config into account */
8813         for_each_intel_encoder(dev, encoder) {
8814                 switch (encoder->type) {
8815                 case INTEL_OUTPUT_LVDS:
8816                         has_panel = true;
8817                         has_lvds = true;
8818                         break;
8819                 case INTEL_OUTPUT_EDP:
8820                         has_panel = true;
8821                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8822                                 has_cpu_edp = true;
8823                         break;
8824                 default:
8825                         break;
8826                 }
8827         }
8828
8829         if (HAS_PCH_IBX(dev)) {
8830                 has_ck505 = dev_priv->vbt.display_clock_mode;
8831                 can_ssc = has_ck505;
8832         } else {
8833                 has_ck505 = false;
8834                 can_ssc = true;
8835         }
8836
8837         /* Check if any DPLLs are using the SSC source */
8838         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8839                 u32 temp = I915_READ(PCH_DPLL(i));
8840
8841                 if (!(temp & DPLL_VCO_ENABLE))
8842                         continue;
8843
8844                 if ((temp & PLL_REF_INPUT_MASK) ==
8845                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8846                         using_ssc_source = true;
8847                         break;
8848                 }
8849         }
8850
8851         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8852                       has_panel, has_lvds, has_ck505, using_ssc_source);
8853
8854         /* Ironlake: try to setup display ref clock before DPLL
8855          * enabling. This is only under driver's control after
8856          * PCH B stepping, previous chipset stepping should be
8857          * ignoring this setting.
8858          */
8859         val = I915_READ(PCH_DREF_CONTROL);
8860
8861         /* As we must carefully and slowly disable/enable each source in turn,
8862          * compute the final state we want first and check if we need to
8863          * make any changes at all.
8864          */
8865         final = val;
8866         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8867         if (has_ck505)
8868                 final |= DREF_NONSPREAD_CK505_ENABLE;
8869         else
8870                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8871
8872         final &= ~DREF_SSC_SOURCE_MASK;
8873         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8874         final &= ~DREF_SSC1_ENABLE;
8875
8876         if (has_panel) {
8877                 final |= DREF_SSC_SOURCE_ENABLE;
8878
8879                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8880                         final |= DREF_SSC1_ENABLE;
8881
8882                 if (has_cpu_edp) {
8883                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8884                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8885                         else
8886                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8887                 } else
8888                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8889         } else if (using_ssc_source) {
8890                 final |= DREF_SSC_SOURCE_ENABLE;
8891                 final |= DREF_SSC1_ENABLE;
8892         }
8893
8894         if (final == val)
8895                 return;
8896
8897         /* Always enable nonspread source */
8898         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8899
8900         if (has_ck505)
8901                 val |= DREF_NONSPREAD_CK505_ENABLE;
8902         else
8903                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8904
8905         if (has_panel) {
8906                 val &= ~DREF_SSC_SOURCE_MASK;
8907                 val |= DREF_SSC_SOURCE_ENABLE;
8908
8909                 /* SSC must be turned on before enabling the CPU output  */
8910                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8911                         DRM_DEBUG_KMS("Using SSC on panel\n");
8912                         val |= DREF_SSC1_ENABLE;
8913                 } else
8914                         val &= ~DREF_SSC1_ENABLE;
8915
8916                 /* Get SSC going before enabling the outputs */
8917                 I915_WRITE(PCH_DREF_CONTROL, val);
8918                 POSTING_READ(PCH_DREF_CONTROL);
8919                 udelay(200);
8920
8921                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8922
8923                 /* Enable CPU source on CPU attached eDP */
8924                 if (has_cpu_edp) {
8925                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8926                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8927                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8928                         } else
8929                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8930                 } else
8931                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8932
8933                 I915_WRITE(PCH_DREF_CONTROL, val);
8934                 POSTING_READ(PCH_DREF_CONTROL);
8935                 udelay(200);
8936         } else {
8937                 DRM_DEBUG_KMS("Disabling CPU source output\n");
8938
8939                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8940
8941                 /* Turn off CPU output */
8942                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8943
8944                 I915_WRITE(PCH_DREF_CONTROL, val);
8945                 POSTING_READ(PCH_DREF_CONTROL);
8946                 udelay(200);
8947
8948                 if (!using_ssc_source) {
8949                         DRM_DEBUG_KMS("Disabling SSC source\n");
8950
8951                         /* Turn off the SSC source */
8952                         val &= ~DREF_SSC_SOURCE_MASK;
8953                         val |= DREF_SSC_SOURCE_DISABLE;
8954
8955                         /* Turn off SSC1 */
8956                         val &= ~DREF_SSC1_ENABLE;
8957
8958                         I915_WRITE(PCH_DREF_CONTROL, val);
8959                         POSTING_READ(PCH_DREF_CONTROL);
8960                         udelay(200);
8961                 }
8962         }
8963
8964         BUG_ON(val != final);
8965 }
8966
8967 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8968 {
8969         uint32_t tmp;
8970
8971         tmp = I915_READ(SOUTH_CHICKEN2);
8972         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8973         I915_WRITE(SOUTH_CHICKEN2, tmp);
8974
8975         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8976                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8977                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8978
8979         tmp = I915_READ(SOUTH_CHICKEN2);
8980         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8981         I915_WRITE(SOUTH_CHICKEN2, tmp);
8982
8983         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8984                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8985                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8986 }
8987
8988 /* WaMPhyProgramming:hsw */
8989 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8990 {
8991         uint32_t tmp;
8992
8993         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8994         tmp &= ~(0xFF << 24);
8995         tmp |= (0x12 << 24);
8996         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8997
8998         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8999         tmp |= (1 << 11);
9000         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9001
9002         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9003         tmp |= (1 << 11);
9004         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9005
9006         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9007         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9008         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9009
9010         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9011         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9012         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9013
9014         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9015         tmp &= ~(7 << 13);
9016         tmp |= (5 << 13);
9017         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9018
9019         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9020         tmp &= ~(7 << 13);
9021         tmp |= (5 << 13);
9022         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9023
9024         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9025         tmp &= ~0xFF;
9026         tmp |= 0x1C;
9027         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9028
9029         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9030         tmp &= ~0xFF;
9031         tmp |= 0x1C;
9032         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9033
9034         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9035         tmp &= ~(0xFF << 16);
9036         tmp |= (0x1C << 16);
9037         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9038
9039         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9040         tmp &= ~(0xFF << 16);
9041         tmp |= (0x1C << 16);
9042         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9043
9044         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9045         tmp |= (1 << 27);
9046         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9047
9048         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9049         tmp |= (1 << 27);
9050         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9051
9052         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9053         tmp &= ~(0xF << 28);
9054         tmp |= (4 << 28);
9055         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9056
9057         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9058         tmp &= ~(0xF << 28);
9059         tmp |= (4 << 28);
9060         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9061 }
9062
9063 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9064  * Programming" based on the parameters passed:
9065  * - Sequence to enable CLKOUT_DP
9066  * - Sequence to enable CLKOUT_DP without spread
9067  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9068  */
9069 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9070                                  bool with_fdi)
9071 {
9072         struct drm_i915_private *dev_priv = to_i915(dev);
9073         uint32_t reg, tmp;
9074
9075         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9076                 with_spread = true;
9077         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9078                 with_fdi = false;
9079
9080         mutex_lock(&dev_priv->sb_lock);
9081
9082         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9083         tmp &= ~SBI_SSCCTL_DISABLE;
9084         tmp |= SBI_SSCCTL_PATHALT;
9085         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9086
9087         udelay(24);
9088
9089         if (with_spread) {
9090                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9091                 tmp &= ~SBI_SSCCTL_PATHALT;
9092                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9093
9094                 if (with_fdi) {
9095                         lpt_reset_fdi_mphy(dev_priv);
9096                         lpt_program_fdi_mphy(dev_priv);
9097                 }
9098         }
9099
9100         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9101         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9102         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9103         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9104
9105         mutex_unlock(&dev_priv->sb_lock);
9106 }
9107
9108 /* Sequence to disable CLKOUT_DP */
9109 static void lpt_disable_clkout_dp(struct drm_device *dev)
9110 {
9111         struct drm_i915_private *dev_priv = to_i915(dev);
9112         uint32_t reg, tmp;
9113
9114         mutex_lock(&dev_priv->sb_lock);
9115
9116         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9117         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9118         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9119         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9120
9121         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9122         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9123                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9124                         tmp |= SBI_SSCCTL_PATHALT;
9125                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9126                         udelay(32);
9127                 }
9128                 tmp |= SBI_SSCCTL_DISABLE;
9129                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9130         }
9131
9132         mutex_unlock(&dev_priv->sb_lock);
9133 }
9134
9135 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9136
9137 static const uint16_t sscdivintphase[] = {
9138         [BEND_IDX( 50)] = 0x3B23,
9139         [BEND_IDX( 45)] = 0x3B23,
9140         [BEND_IDX( 40)] = 0x3C23,
9141         [BEND_IDX( 35)] = 0x3C23,
9142         [BEND_IDX( 30)] = 0x3D23,
9143         [BEND_IDX( 25)] = 0x3D23,
9144         [BEND_IDX( 20)] = 0x3E23,
9145         [BEND_IDX( 15)] = 0x3E23,
9146         [BEND_IDX( 10)] = 0x3F23,
9147         [BEND_IDX(  5)] = 0x3F23,
9148         [BEND_IDX(  0)] = 0x0025,
9149         [BEND_IDX( -5)] = 0x0025,
9150         [BEND_IDX(-10)] = 0x0125,
9151         [BEND_IDX(-15)] = 0x0125,
9152         [BEND_IDX(-20)] = 0x0225,
9153         [BEND_IDX(-25)] = 0x0225,
9154         [BEND_IDX(-30)] = 0x0325,
9155         [BEND_IDX(-35)] = 0x0325,
9156         [BEND_IDX(-40)] = 0x0425,
9157         [BEND_IDX(-45)] = 0x0425,
9158         [BEND_IDX(-50)] = 0x0525,
9159 };
9160
9161 /*
9162  * Bend CLKOUT_DP
9163  * steps -50 to 50 inclusive, in steps of 5
9164  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9165  * change in clock period = -(steps / 10) * 5.787 ps
9166  */
9167 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9168 {
9169         uint32_t tmp;
9170         int idx = BEND_IDX(steps);
9171
9172         if (WARN_ON(steps % 5 != 0))
9173                 return;
9174
9175         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9176                 return;
9177
9178         mutex_lock(&dev_priv->sb_lock);
9179
9180         if (steps % 10 != 0)
9181                 tmp = 0xAAAAAAAB;
9182         else
9183                 tmp = 0x00000000;
9184         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9185
9186         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9187         tmp &= 0xffff0000;
9188         tmp |= sscdivintphase[idx];
9189         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9190
9191         mutex_unlock(&dev_priv->sb_lock);
9192 }
9193
9194 #undef BEND_IDX
9195
9196 static void lpt_init_pch_refclk(struct drm_device *dev)
9197 {
9198         struct intel_encoder *encoder;
9199         bool has_vga = false;
9200
9201         for_each_intel_encoder(dev, encoder) {
9202                 switch (encoder->type) {
9203                 case INTEL_OUTPUT_ANALOG:
9204                         has_vga = true;
9205                         break;
9206                 default:
9207                         break;
9208                 }
9209         }
9210
9211         if (has_vga) {
9212                 lpt_bend_clkout_dp(to_i915(dev), 0);
9213                 lpt_enable_clkout_dp(dev, true, true);
9214         } else {
9215                 lpt_disable_clkout_dp(dev);
9216         }
9217 }
9218
9219 /*
9220  * Initialize reference clocks when the driver loads
9221  */
9222 void intel_init_pch_refclk(struct drm_device *dev)
9223 {
9224         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9225                 ironlake_init_pch_refclk(dev);
9226         else if (HAS_PCH_LPT(dev))
9227                 lpt_init_pch_refclk(dev);
9228 }
9229
9230 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9231 {
9232         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9234         int pipe = intel_crtc->pipe;
9235         uint32_t val;
9236
9237         val = 0;
9238
9239         switch (intel_crtc->config->pipe_bpp) {
9240         case 18:
9241                 val |= PIPECONF_6BPC;
9242                 break;
9243         case 24:
9244                 val |= PIPECONF_8BPC;
9245                 break;
9246         case 30:
9247                 val |= PIPECONF_10BPC;
9248                 break;
9249         case 36:
9250                 val |= PIPECONF_12BPC;
9251                 break;
9252         default:
9253                 /* Case prevented by intel_choose_pipe_bpp_dither. */
9254                 BUG();
9255         }
9256
9257         if (intel_crtc->config->dither)
9258                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9259
9260         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9261                 val |= PIPECONF_INTERLACED_ILK;
9262         else
9263                 val |= PIPECONF_PROGRESSIVE;
9264
9265         if (intel_crtc->config->limited_color_range)
9266                 val |= PIPECONF_COLOR_RANGE_SELECT;
9267
9268         I915_WRITE(PIPECONF(pipe), val);
9269         POSTING_READ(PIPECONF(pipe));
9270 }
9271
9272 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9273 {
9274         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9276         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9277         u32 val = 0;
9278
9279         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9280                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9281
9282         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9283                 val |= PIPECONF_INTERLACED_ILK;
9284         else
9285                 val |= PIPECONF_PROGRESSIVE;
9286
9287         I915_WRITE(PIPECONF(cpu_transcoder), val);
9288         POSTING_READ(PIPECONF(cpu_transcoder));
9289 }
9290
9291 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9292 {
9293         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9295
9296         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9297                 u32 val = 0;
9298
9299                 switch (intel_crtc->config->pipe_bpp) {
9300                 case 18:
9301                         val |= PIPEMISC_DITHER_6_BPC;
9302                         break;
9303                 case 24:
9304                         val |= PIPEMISC_DITHER_8_BPC;
9305                         break;
9306                 case 30:
9307                         val |= PIPEMISC_DITHER_10_BPC;
9308                         break;
9309                 case 36:
9310                         val |= PIPEMISC_DITHER_12_BPC;
9311                         break;
9312                 default:
9313                         /* Case prevented by pipe_config_set_bpp. */
9314                         BUG();
9315                 }
9316
9317                 if (intel_crtc->config->dither)
9318                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9319
9320                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9321         }
9322 }
9323
9324 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9325 {
9326         /*
9327          * Account for spread spectrum to avoid
9328          * oversubscribing the link. Max center spread
9329          * is 2.5%; use 5% for safety's sake.
9330          */
9331         u32 bps = target_clock * bpp * 21 / 20;
9332         return DIV_ROUND_UP(bps, link_bw * 8);
9333 }
9334
9335 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9336 {
9337         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9338 }
9339
9340 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9341                                   struct intel_crtc_state *crtc_state,
9342                                   struct dpll *reduced_clock)
9343 {
9344         struct drm_crtc *crtc = &intel_crtc->base;
9345         struct drm_device *dev = crtc->dev;
9346         struct drm_i915_private *dev_priv = to_i915(dev);
9347         u32 dpll, fp, fp2;
9348         int factor;
9349
9350         /* Enable autotuning of the PLL clock (if permissible) */
9351         factor = 21;
9352         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9353                 if ((intel_panel_use_ssc(dev_priv) &&
9354                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
9355                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9356                         factor = 25;
9357         } else if (crtc_state->sdvo_tv_clock)
9358                 factor = 20;
9359
9360         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9361
9362         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9363                 fp |= FP_CB_TUNE;
9364
9365         if (reduced_clock) {
9366                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9367
9368                 if (reduced_clock->m < factor * reduced_clock->n)
9369                         fp2 |= FP_CB_TUNE;
9370         } else {
9371                 fp2 = fp;
9372         }
9373
9374         dpll = 0;
9375
9376         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9377                 dpll |= DPLLB_MODE_LVDS;
9378         else
9379                 dpll |= DPLLB_MODE_DAC_SERIAL;
9380
9381         dpll |= (crtc_state->pixel_multiplier - 1)
9382                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9383
9384         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9385             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9386                 dpll |= DPLL_SDVO_HIGH_SPEED;
9387
9388         if (intel_crtc_has_dp_encoder(crtc_state))
9389                 dpll |= DPLL_SDVO_HIGH_SPEED;
9390
9391         /* compute bitmask from p1 value */
9392         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9393         /* also FPA1 */
9394         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9395
9396         switch (crtc_state->dpll.p2) {
9397         case 5:
9398                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9399                 break;
9400         case 7:
9401                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9402                 break;
9403         case 10:
9404                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9405                 break;
9406         case 14:
9407                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9408                 break;
9409         }
9410
9411         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9412             intel_panel_use_ssc(dev_priv))
9413                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9414         else
9415                 dpll |= PLL_REF_INPUT_DREFCLK;
9416
9417         dpll |= DPLL_VCO_ENABLE;
9418
9419         crtc_state->dpll_hw_state.dpll = dpll;
9420         crtc_state->dpll_hw_state.fp0 = fp;
9421         crtc_state->dpll_hw_state.fp1 = fp2;
9422 }
9423
9424 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9425                                        struct intel_crtc_state *crtc_state)
9426 {
9427         struct drm_device *dev = crtc->base.dev;
9428         struct drm_i915_private *dev_priv = to_i915(dev);
9429         struct dpll reduced_clock;
9430         bool has_reduced_clock = false;
9431         struct intel_shared_dpll *pll;
9432         const struct intel_limit *limit;
9433         int refclk = 120000;
9434
9435         memset(&crtc_state->dpll_hw_state, 0,
9436                sizeof(crtc_state->dpll_hw_state));
9437
9438         crtc->lowfreq_avail = false;
9439
9440         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9441         if (!crtc_state->has_pch_encoder)
9442                 return 0;
9443
9444         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9445                 if (intel_panel_use_ssc(dev_priv)) {
9446                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9447                                       dev_priv->vbt.lvds_ssc_freq);
9448                         refclk = dev_priv->vbt.lvds_ssc_freq;
9449                 }
9450
9451                 if (intel_is_dual_link_lvds(dev)) {
9452                         if (refclk == 100000)
9453                                 limit = &intel_limits_ironlake_dual_lvds_100m;
9454                         else
9455                                 limit = &intel_limits_ironlake_dual_lvds;
9456                 } else {
9457                         if (refclk == 100000)
9458                                 limit = &intel_limits_ironlake_single_lvds_100m;
9459                         else
9460                                 limit = &intel_limits_ironlake_single_lvds;
9461                 }
9462         } else {
9463                 limit = &intel_limits_ironlake_dac;
9464         }
9465
9466         if (!crtc_state->clock_set &&
9467             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9468                                 refclk, NULL, &crtc_state->dpll)) {
9469                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9470                 return -EINVAL;
9471         }
9472
9473         ironlake_compute_dpll(crtc, crtc_state,
9474                               has_reduced_clock ? &reduced_clock : NULL);
9475
9476         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9477         if (pll == NULL) {
9478                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9479                                  pipe_name(crtc->pipe));
9480                 return -EINVAL;
9481         }
9482
9483         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9484             has_reduced_clock)
9485                 crtc->lowfreq_avail = true;
9486
9487         return 0;
9488 }
9489
9490 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9491                                          struct intel_link_m_n *m_n)
9492 {
9493         struct drm_device *dev = crtc->base.dev;
9494         struct drm_i915_private *dev_priv = to_i915(dev);
9495         enum pipe pipe = crtc->pipe;
9496
9497         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9498         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9499         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9500                 & ~TU_SIZE_MASK;
9501         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9502         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9503                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9504 }
9505
9506 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9507                                          enum transcoder transcoder,
9508                                          struct intel_link_m_n *m_n,
9509                                          struct intel_link_m_n *m2_n2)
9510 {
9511         struct drm_device *dev = crtc->base.dev;
9512         struct drm_i915_private *dev_priv = to_i915(dev);
9513         enum pipe pipe = crtc->pipe;
9514
9515         if (INTEL_INFO(dev)->gen >= 5) {
9516                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9517                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9518                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9519                         & ~TU_SIZE_MASK;
9520                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9521                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9522                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9523                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9524                  * gen < 8) and if DRRS is supported (to make sure the
9525                  * registers are not unnecessarily read).
9526                  */
9527                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9528                         crtc->config->has_drrs) {
9529                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9530                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9531                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9532                                         & ~TU_SIZE_MASK;
9533                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9534                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9535                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9536                 }
9537         } else {
9538                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9539                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9540                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9541                         & ~TU_SIZE_MASK;
9542                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9543                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9544                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9545         }
9546 }
9547
9548 void intel_dp_get_m_n(struct intel_crtc *crtc,
9549                       struct intel_crtc_state *pipe_config)
9550 {
9551         if (pipe_config->has_pch_encoder)
9552                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9553         else
9554                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9555                                              &pipe_config->dp_m_n,
9556                                              &pipe_config->dp_m2_n2);
9557 }
9558
9559 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9560                                         struct intel_crtc_state *pipe_config)
9561 {
9562         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9563                                      &pipe_config->fdi_m_n, NULL);
9564 }
9565
9566 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9567                                     struct intel_crtc_state *pipe_config)
9568 {
9569         struct drm_device *dev = crtc->base.dev;
9570         struct drm_i915_private *dev_priv = to_i915(dev);
9571         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9572         uint32_t ps_ctrl = 0;
9573         int id = -1;
9574         int i;
9575
9576         /* find scaler attached to this pipe */
9577         for (i = 0; i < crtc->num_scalers; i++) {
9578                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9579                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9580                         id = i;
9581                         pipe_config->pch_pfit.enabled = true;
9582                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9583                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9584                         break;
9585                 }
9586         }
9587
9588         scaler_state->scaler_id = id;
9589         if (id >= 0) {
9590                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9591         } else {
9592                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9593         }
9594 }
9595
9596 static void
9597 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9598                                  struct intel_initial_plane_config *plane_config)
9599 {
9600         struct drm_device *dev = crtc->base.dev;
9601         struct drm_i915_private *dev_priv = to_i915(dev);
9602         u32 val, base, offset, stride_mult, tiling;
9603         int pipe = crtc->pipe;
9604         int fourcc, pixel_format;
9605         unsigned int aligned_height;
9606         struct drm_framebuffer *fb;
9607         struct intel_framebuffer *intel_fb;
9608
9609         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9610         if (!intel_fb) {
9611                 DRM_DEBUG_KMS("failed to alloc fb\n");
9612                 return;
9613         }
9614
9615         fb = &intel_fb->base;
9616
9617         val = I915_READ(PLANE_CTL(pipe, 0));
9618         if (!(val & PLANE_CTL_ENABLE))
9619                 goto error;
9620
9621         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9622         fourcc = skl_format_to_fourcc(pixel_format,
9623                                       val & PLANE_CTL_ORDER_RGBX,
9624                                       val & PLANE_CTL_ALPHA_MASK);
9625         fb->pixel_format = fourcc;
9626         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9627
9628         tiling = val & PLANE_CTL_TILED_MASK;
9629         switch (tiling) {
9630         case PLANE_CTL_TILED_LINEAR:
9631                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9632                 break;
9633         case PLANE_CTL_TILED_X:
9634                 plane_config->tiling = I915_TILING_X;
9635                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9636                 break;
9637         case PLANE_CTL_TILED_Y:
9638                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9639                 break;
9640         case PLANE_CTL_TILED_YF:
9641                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9642                 break;
9643         default:
9644                 MISSING_CASE(tiling);
9645                 goto error;
9646         }
9647
9648         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9649         plane_config->base = base;
9650
9651         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9652
9653         val = I915_READ(PLANE_SIZE(pipe, 0));
9654         fb->height = ((val >> 16) & 0xfff) + 1;
9655         fb->width = ((val >> 0) & 0x1fff) + 1;
9656
9657         val = I915_READ(PLANE_STRIDE(pipe, 0));
9658         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9659                                                 fb->pixel_format);
9660         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9661
9662         aligned_height = intel_fb_align_height(dev, fb->height,
9663                                                fb->pixel_format,
9664                                                fb->modifier[0]);
9665
9666         plane_config->size = fb->pitches[0] * aligned_height;
9667
9668         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9669                       pipe_name(pipe), fb->width, fb->height,
9670                       fb->bits_per_pixel, base, fb->pitches[0],
9671                       plane_config->size);
9672
9673         plane_config->fb = intel_fb;
9674         return;
9675
9676 error:
9677         kfree(fb);
9678 }
9679
9680 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9681                                      struct intel_crtc_state *pipe_config)
9682 {
9683         struct drm_device *dev = crtc->base.dev;
9684         struct drm_i915_private *dev_priv = to_i915(dev);
9685         uint32_t tmp;
9686
9687         tmp = I915_READ(PF_CTL(crtc->pipe));
9688
9689         if (tmp & PF_ENABLE) {
9690                 pipe_config->pch_pfit.enabled = true;
9691                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9692                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9693
9694                 /* We currently do not free assignements of panel fitters on
9695                  * ivb/hsw (since we don't use the higher upscaling modes which
9696                  * differentiates them) so just WARN about this case for now. */
9697                 if (IS_GEN7(dev)) {
9698                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9699                                 PF_PIPE_SEL_IVB(crtc->pipe));
9700                 }
9701         }
9702 }
9703
9704 static void
9705 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9706                                   struct intel_initial_plane_config *plane_config)
9707 {
9708         struct drm_device *dev = crtc->base.dev;
9709         struct drm_i915_private *dev_priv = to_i915(dev);
9710         u32 val, base, offset;
9711         int pipe = crtc->pipe;
9712         int fourcc, pixel_format;
9713         unsigned int aligned_height;
9714         struct drm_framebuffer *fb;
9715         struct intel_framebuffer *intel_fb;
9716
9717         val = I915_READ(DSPCNTR(pipe));
9718         if (!(val & DISPLAY_PLANE_ENABLE))
9719                 return;
9720
9721         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9722         if (!intel_fb) {
9723                 DRM_DEBUG_KMS("failed to alloc fb\n");
9724                 return;
9725         }
9726
9727         fb = &intel_fb->base;
9728
9729         if (INTEL_INFO(dev)->gen >= 4) {
9730                 if (val & DISPPLANE_TILED) {
9731                         plane_config->tiling = I915_TILING_X;
9732                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9733                 }
9734         }
9735
9736         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9737         fourcc = i9xx_format_to_fourcc(pixel_format);
9738         fb->pixel_format = fourcc;
9739         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9740
9741         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9742         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9743                 offset = I915_READ(DSPOFFSET(pipe));
9744         } else {
9745                 if (plane_config->tiling)
9746                         offset = I915_READ(DSPTILEOFF(pipe));
9747                 else
9748                         offset = I915_READ(DSPLINOFF(pipe));
9749         }
9750         plane_config->base = base;
9751
9752         val = I915_READ(PIPESRC(pipe));
9753         fb->width = ((val >> 16) & 0xfff) + 1;
9754         fb->height = ((val >> 0) & 0xfff) + 1;
9755
9756         val = I915_READ(DSPSTRIDE(pipe));
9757         fb->pitches[0] = val & 0xffffffc0;
9758
9759         aligned_height = intel_fb_align_height(dev, fb->height,
9760                                                fb->pixel_format,
9761                                                fb->modifier[0]);
9762
9763         plane_config->size = fb->pitches[0] * aligned_height;
9764
9765         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9766                       pipe_name(pipe), fb->width, fb->height,
9767                       fb->bits_per_pixel, base, fb->pitches[0],
9768                       plane_config->size);
9769
9770         plane_config->fb = intel_fb;
9771 }
9772
9773 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9774                                      struct intel_crtc_state *pipe_config)
9775 {
9776         struct drm_device *dev = crtc->base.dev;
9777         struct drm_i915_private *dev_priv = to_i915(dev);
9778         enum intel_display_power_domain power_domain;
9779         uint32_t tmp;
9780         bool ret;
9781
9782         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9783         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9784                 return false;
9785
9786         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9787         pipe_config->shared_dpll = NULL;
9788
9789         ret = false;
9790         tmp = I915_READ(PIPECONF(crtc->pipe));
9791         if (!(tmp & PIPECONF_ENABLE))
9792                 goto out;
9793
9794         switch (tmp & PIPECONF_BPC_MASK) {
9795         case PIPECONF_6BPC:
9796                 pipe_config->pipe_bpp = 18;
9797                 break;
9798         case PIPECONF_8BPC:
9799                 pipe_config->pipe_bpp = 24;
9800                 break;
9801         case PIPECONF_10BPC:
9802                 pipe_config->pipe_bpp = 30;
9803                 break;
9804         case PIPECONF_12BPC:
9805                 pipe_config->pipe_bpp = 36;
9806                 break;
9807         default:
9808                 break;
9809         }
9810
9811         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9812                 pipe_config->limited_color_range = true;
9813
9814         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9815                 struct intel_shared_dpll *pll;
9816                 enum intel_dpll_id pll_id;
9817
9818                 pipe_config->has_pch_encoder = true;
9819
9820                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9821                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9822                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9823
9824                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9825
9826                 if (HAS_PCH_IBX(dev_priv)) {
9827                         /*
9828                          * The pipe->pch transcoder and pch transcoder->pll
9829                          * mapping is fixed.
9830                          */
9831                         pll_id = (enum intel_dpll_id) crtc->pipe;
9832                 } else {
9833                         tmp = I915_READ(PCH_DPLL_SEL);
9834                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9835                                 pll_id = DPLL_ID_PCH_PLL_B;
9836                         else
9837                                 pll_id= DPLL_ID_PCH_PLL_A;
9838                 }
9839
9840                 pipe_config->shared_dpll =
9841                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9842                 pll = pipe_config->shared_dpll;
9843
9844                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9845                                                  &pipe_config->dpll_hw_state));
9846
9847                 tmp = pipe_config->dpll_hw_state.dpll;
9848                 pipe_config->pixel_multiplier =
9849                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9850                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9851
9852                 ironlake_pch_clock_get(crtc, pipe_config);
9853         } else {
9854                 pipe_config->pixel_multiplier = 1;
9855         }
9856
9857         intel_get_pipe_timings(crtc, pipe_config);
9858         intel_get_pipe_src_size(crtc, pipe_config);
9859
9860         ironlake_get_pfit_config(crtc, pipe_config);
9861
9862         ret = true;
9863
9864 out:
9865         intel_display_power_put(dev_priv, power_domain);
9866
9867         return ret;
9868 }
9869
9870 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9871 {
9872         struct drm_device *dev = &dev_priv->drm;
9873         struct intel_crtc *crtc;
9874
9875         for_each_intel_crtc(dev, crtc)
9876                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9877                      pipe_name(crtc->pipe));
9878
9879         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9880         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9881         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9882         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9883         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
9884         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9885              "CPU PWM1 enabled\n");
9886         if (IS_HASWELL(dev))
9887                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9888                      "CPU PWM2 enabled\n");
9889         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9890              "PCH PWM1 enabled\n");
9891         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9892              "Utility pin enabled\n");
9893         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9894
9895         /*
9896          * In theory we can still leave IRQs enabled, as long as only the HPD
9897          * interrupts remain enabled. We used to check for that, but since it's
9898          * gen-specific and since we only disable LCPLL after we fully disable
9899          * the interrupts, the check below should be enough.
9900          */
9901         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9902 }
9903
9904 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9905 {
9906         struct drm_device *dev = &dev_priv->drm;
9907
9908         if (IS_HASWELL(dev))
9909                 return I915_READ(D_COMP_HSW);
9910         else
9911                 return I915_READ(D_COMP_BDW);
9912 }
9913
9914 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9915 {
9916         struct drm_device *dev = &dev_priv->drm;
9917
9918         if (IS_HASWELL(dev)) {
9919                 mutex_lock(&dev_priv->rps.hw_lock);
9920                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9921                                             val))
9922                         DRM_ERROR("Failed to write to D_COMP\n");
9923                 mutex_unlock(&dev_priv->rps.hw_lock);
9924         } else {
9925                 I915_WRITE(D_COMP_BDW, val);
9926                 POSTING_READ(D_COMP_BDW);
9927         }
9928 }
9929
9930 /*
9931  * This function implements pieces of two sequences from BSpec:
9932  * - Sequence for display software to disable LCPLL
9933  * - Sequence for display software to allow package C8+
9934  * The steps implemented here are just the steps that actually touch the LCPLL
9935  * register. Callers should take care of disabling all the display engine
9936  * functions, doing the mode unset, fixing interrupts, etc.
9937  */
9938 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9939                               bool switch_to_fclk, bool allow_power_down)
9940 {
9941         uint32_t val;
9942
9943         assert_can_disable_lcpll(dev_priv);
9944
9945         val = I915_READ(LCPLL_CTL);
9946
9947         if (switch_to_fclk) {
9948                 val |= LCPLL_CD_SOURCE_FCLK;
9949                 I915_WRITE(LCPLL_CTL, val);
9950
9951                 if (wait_for_us(I915_READ(LCPLL_CTL) &
9952                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9953                         DRM_ERROR("Switching to FCLK failed\n");
9954
9955                 val = I915_READ(LCPLL_CTL);
9956         }
9957
9958         val |= LCPLL_PLL_DISABLE;
9959         I915_WRITE(LCPLL_CTL, val);
9960         POSTING_READ(LCPLL_CTL);
9961
9962         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
9963                 DRM_ERROR("LCPLL still locked\n");
9964
9965         val = hsw_read_dcomp(dev_priv);
9966         val |= D_COMP_COMP_DISABLE;
9967         hsw_write_dcomp(dev_priv, val);
9968         ndelay(100);
9969
9970         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9971                      1))
9972                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9973
9974         if (allow_power_down) {
9975                 val = I915_READ(LCPLL_CTL);
9976                 val |= LCPLL_POWER_DOWN_ALLOW;
9977                 I915_WRITE(LCPLL_CTL, val);
9978                 POSTING_READ(LCPLL_CTL);
9979         }
9980 }
9981
9982 /*
9983  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9984  * source.
9985  */
9986 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9987 {
9988         uint32_t val;
9989
9990         val = I915_READ(LCPLL_CTL);
9991
9992         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9993                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9994                 return;
9995
9996         /*
9997          * Make sure we're not on PC8 state before disabling PC8, otherwise
9998          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9999          */
10000         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10001
10002         if (val & LCPLL_POWER_DOWN_ALLOW) {
10003                 val &= ~LCPLL_POWER_DOWN_ALLOW;
10004                 I915_WRITE(LCPLL_CTL, val);
10005                 POSTING_READ(LCPLL_CTL);
10006         }
10007
10008         val = hsw_read_dcomp(dev_priv);
10009         val |= D_COMP_COMP_FORCE;
10010         val &= ~D_COMP_COMP_DISABLE;
10011         hsw_write_dcomp(dev_priv, val);
10012
10013         val = I915_READ(LCPLL_CTL);
10014         val &= ~LCPLL_PLL_DISABLE;
10015         I915_WRITE(LCPLL_CTL, val);
10016
10017         if (intel_wait_for_register(dev_priv,
10018                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10019                                     5))
10020                 DRM_ERROR("LCPLL not locked yet\n");
10021
10022         if (val & LCPLL_CD_SOURCE_FCLK) {
10023                 val = I915_READ(LCPLL_CTL);
10024                 val &= ~LCPLL_CD_SOURCE_FCLK;
10025                 I915_WRITE(LCPLL_CTL, val);
10026
10027                 if (wait_for_us((I915_READ(LCPLL_CTL) &
10028                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10029                         DRM_ERROR("Switching back to LCPLL failed\n");
10030         }
10031
10032         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10033         intel_update_cdclk(&dev_priv->drm);
10034 }
10035
10036 /*
10037  * Package states C8 and deeper are really deep PC states that can only be
10038  * reached when all the devices on the system allow it, so even if the graphics
10039  * device allows PC8+, it doesn't mean the system will actually get to these
10040  * states. Our driver only allows PC8+ when going into runtime PM.
10041  *
10042  * The requirements for PC8+ are that all the outputs are disabled, the power
10043  * well is disabled and most interrupts are disabled, and these are also
10044  * requirements for runtime PM. When these conditions are met, we manually do
10045  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10046  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10047  * hang the machine.
10048  *
10049  * When we really reach PC8 or deeper states (not just when we allow it) we lose
10050  * the state of some registers, so when we come back from PC8+ we need to
10051  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10052  * need to take care of the registers kept by RC6. Notice that this happens even
10053  * if we don't put the device in PCI D3 state (which is what currently happens
10054  * because of the runtime PM support).
10055  *
10056  * For more, read "Display Sequences for Package C8" on the hardware
10057  * documentation.
10058  */
10059 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10060 {
10061         struct drm_device *dev = &dev_priv->drm;
10062         uint32_t val;
10063
10064         DRM_DEBUG_KMS("Enabling package C8+\n");
10065
10066         if (HAS_PCH_LPT_LP(dev)) {
10067                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10068                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10069                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10070         }
10071
10072         lpt_disable_clkout_dp(dev);
10073         hsw_disable_lcpll(dev_priv, true, true);
10074 }
10075
10076 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10077 {
10078         struct drm_device *dev = &dev_priv->drm;
10079         uint32_t val;
10080
10081         DRM_DEBUG_KMS("Disabling package C8+\n");
10082
10083         hsw_restore_lcpll(dev_priv);
10084         lpt_init_pch_refclk(dev);
10085
10086         if (HAS_PCH_LPT_LP(dev)) {
10087                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10088                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10089                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10090         }
10091 }
10092
10093 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10094 {
10095         struct drm_device *dev = old_state->dev;
10096         struct intel_atomic_state *old_intel_state =
10097                 to_intel_atomic_state(old_state);
10098         unsigned int req_cdclk = old_intel_state->dev_cdclk;
10099
10100         bxt_set_cdclk(to_i915(dev), req_cdclk);
10101 }
10102
10103 /* compute the max rate for new configuration */
10104 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10105 {
10106         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10107         struct drm_i915_private *dev_priv = to_i915(state->dev);
10108         struct drm_crtc *crtc;
10109         struct drm_crtc_state *cstate;
10110         struct intel_crtc_state *crtc_state;
10111         unsigned max_pixel_rate = 0, i;
10112         enum pipe pipe;
10113
10114         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10115                sizeof(intel_state->min_pixclk));
10116
10117         for_each_crtc_in_state(state, crtc, cstate, i) {
10118                 int pixel_rate;
10119
10120                 crtc_state = to_intel_crtc_state(cstate);
10121                 if (!crtc_state->base.enable) {
10122                         intel_state->min_pixclk[i] = 0;
10123                         continue;
10124                 }
10125
10126                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10127
10128                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10129                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10130                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10131
10132                 intel_state->min_pixclk[i] = pixel_rate;
10133         }
10134
10135         for_each_pipe(dev_priv, pipe)
10136                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10137
10138         return max_pixel_rate;
10139 }
10140
10141 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10142 {
10143         struct drm_i915_private *dev_priv = to_i915(dev);
10144         uint32_t val, data;
10145         int ret;
10146
10147         if (WARN((I915_READ(LCPLL_CTL) &
10148                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10149                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10150                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10151                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10152                  "trying to change cdclk frequency with cdclk not enabled\n"))
10153                 return;
10154
10155         mutex_lock(&dev_priv->rps.hw_lock);
10156         ret = sandybridge_pcode_write(dev_priv,
10157                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10158         mutex_unlock(&dev_priv->rps.hw_lock);
10159         if (ret) {
10160                 DRM_ERROR("failed to inform pcode about cdclk change\n");
10161                 return;
10162         }
10163
10164         val = I915_READ(LCPLL_CTL);
10165         val |= LCPLL_CD_SOURCE_FCLK;
10166         I915_WRITE(LCPLL_CTL, val);
10167
10168         if (wait_for_us(I915_READ(LCPLL_CTL) &
10169                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
10170                 DRM_ERROR("Switching to FCLK failed\n");
10171
10172         val = I915_READ(LCPLL_CTL);
10173         val &= ~LCPLL_CLK_FREQ_MASK;
10174
10175         switch (cdclk) {
10176         case 450000:
10177                 val |= LCPLL_CLK_FREQ_450;
10178                 data = 0;
10179                 break;
10180         case 540000:
10181                 val |= LCPLL_CLK_FREQ_54O_BDW;
10182                 data = 1;
10183                 break;
10184         case 337500:
10185                 val |= LCPLL_CLK_FREQ_337_5_BDW;
10186                 data = 2;
10187                 break;
10188         case 675000:
10189                 val |= LCPLL_CLK_FREQ_675_BDW;
10190                 data = 3;
10191                 break;
10192         default:
10193                 WARN(1, "invalid cdclk frequency\n");
10194                 return;
10195         }
10196
10197         I915_WRITE(LCPLL_CTL, val);
10198
10199         val = I915_READ(LCPLL_CTL);
10200         val &= ~LCPLL_CD_SOURCE_FCLK;
10201         I915_WRITE(LCPLL_CTL, val);
10202
10203         if (wait_for_us((I915_READ(LCPLL_CTL) &
10204                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10205                 DRM_ERROR("Switching back to LCPLL failed\n");
10206
10207         mutex_lock(&dev_priv->rps.hw_lock);
10208         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10209         mutex_unlock(&dev_priv->rps.hw_lock);
10210
10211         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10212
10213         intel_update_cdclk(dev);
10214
10215         WARN(cdclk != dev_priv->cdclk_freq,
10216              "cdclk requested %d kHz but got %d kHz\n",
10217              cdclk, dev_priv->cdclk_freq);
10218 }
10219
10220 static int broadwell_calc_cdclk(int max_pixclk)
10221 {
10222         if (max_pixclk > 540000)
10223                 return 675000;
10224         else if (max_pixclk > 450000)
10225                 return 540000;
10226         else if (max_pixclk > 337500)
10227                 return 450000;
10228         else
10229                 return 337500;
10230 }
10231
10232 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10233 {
10234         struct drm_i915_private *dev_priv = to_i915(state->dev);
10235         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10236         int max_pixclk = ilk_max_pixel_rate(state);
10237         int cdclk;
10238
10239         /*
10240          * FIXME should also account for plane ratio
10241          * once 64bpp pixel formats are supported.
10242          */
10243         cdclk = broadwell_calc_cdclk(max_pixclk);
10244
10245         if (cdclk > dev_priv->max_cdclk_freq) {
10246                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10247                               cdclk, dev_priv->max_cdclk_freq);
10248                 return -EINVAL;
10249         }
10250
10251         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10252         if (!intel_state->active_crtcs)
10253                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10254
10255         return 0;
10256 }
10257
10258 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10259 {
10260         struct drm_device *dev = old_state->dev;
10261         struct intel_atomic_state *old_intel_state =
10262                 to_intel_atomic_state(old_state);
10263         unsigned req_cdclk = old_intel_state->dev_cdclk;
10264
10265         broadwell_set_cdclk(dev, req_cdclk);
10266 }
10267
10268 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10269 {
10270         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10271         struct drm_i915_private *dev_priv = to_i915(state->dev);
10272         const int max_pixclk = ilk_max_pixel_rate(state);
10273         int vco = intel_state->cdclk_pll_vco;
10274         int cdclk;
10275
10276         /*
10277          * FIXME should also account for plane ratio
10278          * once 64bpp pixel formats are supported.
10279          */
10280         cdclk = skl_calc_cdclk(max_pixclk, vco);
10281
10282         /*
10283          * FIXME move the cdclk caclulation to
10284          * compute_config() so we can fail gracegully.
10285          */
10286         if (cdclk > dev_priv->max_cdclk_freq) {
10287                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10288                           cdclk, dev_priv->max_cdclk_freq);
10289                 cdclk = dev_priv->max_cdclk_freq;
10290         }
10291
10292         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10293         if (!intel_state->active_crtcs)
10294                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10295
10296         return 0;
10297 }
10298
10299 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10300 {
10301         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10302         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10303         unsigned int req_cdclk = intel_state->dev_cdclk;
10304         unsigned int req_vco = intel_state->cdclk_pll_vco;
10305
10306         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10307 }
10308
10309 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10310                                       struct intel_crtc_state *crtc_state)
10311 {
10312         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10313                 if (!intel_ddi_pll_select(crtc, crtc_state))
10314                         return -EINVAL;
10315         }
10316
10317         crtc->lowfreq_avail = false;
10318
10319         return 0;
10320 }
10321
10322 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10323                                 enum port port,
10324                                 struct intel_crtc_state *pipe_config)
10325 {
10326         enum intel_dpll_id id;
10327
10328         switch (port) {
10329         case PORT_A:
10330                 pipe_config->ddi_pll_sel = SKL_DPLL0;
10331                 id = DPLL_ID_SKL_DPLL0;
10332                 break;
10333         case PORT_B:
10334                 pipe_config->ddi_pll_sel = SKL_DPLL1;
10335                 id = DPLL_ID_SKL_DPLL1;
10336                 break;
10337         case PORT_C:
10338                 pipe_config->ddi_pll_sel = SKL_DPLL2;
10339                 id = DPLL_ID_SKL_DPLL2;
10340                 break;
10341         default:
10342                 DRM_ERROR("Incorrect port type\n");
10343                 return;
10344         }
10345
10346         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10347 }
10348
10349 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10350                                 enum port port,
10351                                 struct intel_crtc_state *pipe_config)
10352 {
10353         enum intel_dpll_id id;
10354         u32 temp;
10355
10356         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10357         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
10358
10359         switch (pipe_config->ddi_pll_sel) {
10360         case SKL_DPLL0:
10361                 id = DPLL_ID_SKL_DPLL0;
10362                 break;
10363         case SKL_DPLL1:
10364                 id = DPLL_ID_SKL_DPLL1;
10365                 break;
10366         case SKL_DPLL2:
10367                 id = DPLL_ID_SKL_DPLL2;
10368                 break;
10369         case SKL_DPLL3:
10370                 id = DPLL_ID_SKL_DPLL3;
10371                 break;
10372         default:
10373                 MISSING_CASE(pipe_config->ddi_pll_sel);
10374                 return;
10375         }
10376
10377         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10378 }
10379
10380 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10381                                 enum port port,
10382                                 struct intel_crtc_state *pipe_config)
10383 {
10384         enum intel_dpll_id id;
10385
10386         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10387
10388         switch (pipe_config->ddi_pll_sel) {
10389         case PORT_CLK_SEL_WRPLL1:
10390                 id = DPLL_ID_WRPLL1;
10391                 break;
10392         case PORT_CLK_SEL_WRPLL2:
10393                 id = DPLL_ID_WRPLL2;
10394                 break;
10395         case PORT_CLK_SEL_SPLL:
10396                 id = DPLL_ID_SPLL;
10397                 break;
10398         case PORT_CLK_SEL_LCPLL_810:
10399                 id = DPLL_ID_LCPLL_810;
10400                 break;
10401         case PORT_CLK_SEL_LCPLL_1350:
10402                 id = DPLL_ID_LCPLL_1350;
10403                 break;
10404         case PORT_CLK_SEL_LCPLL_2700:
10405                 id = DPLL_ID_LCPLL_2700;
10406                 break;
10407         default:
10408                 MISSING_CASE(pipe_config->ddi_pll_sel);
10409                 /* fall through */
10410         case PORT_CLK_SEL_NONE:
10411                 return;
10412         }
10413
10414         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10415 }
10416
10417 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10418                                      struct intel_crtc_state *pipe_config,
10419                                      unsigned long *power_domain_mask)
10420 {
10421         struct drm_device *dev = crtc->base.dev;
10422         struct drm_i915_private *dev_priv = to_i915(dev);
10423         enum intel_display_power_domain power_domain;
10424         u32 tmp;
10425
10426         /*
10427          * The pipe->transcoder mapping is fixed with the exception of the eDP
10428          * transcoder handled below.
10429          */
10430         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10431
10432         /*
10433          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10434          * consistency and less surprising code; it's in always on power).
10435          */
10436         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10437         if (tmp & TRANS_DDI_FUNC_ENABLE) {
10438                 enum pipe trans_edp_pipe;
10439                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10440                 default:
10441                         WARN(1, "unknown pipe linked to edp transcoder\n");
10442                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10443                 case TRANS_DDI_EDP_INPUT_A_ON:
10444                         trans_edp_pipe = PIPE_A;
10445                         break;
10446                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10447                         trans_edp_pipe = PIPE_B;
10448                         break;
10449                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10450                         trans_edp_pipe = PIPE_C;
10451                         break;
10452                 }
10453
10454                 if (trans_edp_pipe == crtc->pipe)
10455                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
10456         }
10457
10458         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10459         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10460                 return false;
10461         *power_domain_mask |= BIT(power_domain);
10462
10463         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10464
10465         return tmp & PIPECONF_ENABLE;
10466 }
10467
10468 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10469                                          struct intel_crtc_state *pipe_config,
10470                                          unsigned long *power_domain_mask)
10471 {
10472         struct drm_device *dev = crtc->base.dev;
10473         struct drm_i915_private *dev_priv = to_i915(dev);
10474         enum intel_display_power_domain power_domain;
10475         enum port port;
10476         enum transcoder cpu_transcoder;
10477         u32 tmp;
10478
10479         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10480                 if (port == PORT_A)
10481                         cpu_transcoder = TRANSCODER_DSI_A;
10482                 else
10483                         cpu_transcoder = TRANSCODER_DSI_C;
10484
10485                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10486                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10487                         continue;
10488                 *power_domain_mask |= BIT(power_domain);
10489
10490                 /*
10491                  * The PLL needs to be enabled with a valid divider
10492                  * configuration, otherwise accessing DSI registers will hang
10493                  * the machine. See BSpec North Display Engine
10494                  * registers/MIPI[BXT]. We can break out here early, since we
10495                  * need the same DSI PLL to be enabled for both DSI ports.
10496                  */
10497                 if (!intel_dsi_pll_is_enabled(dev_priv))
10498                         break;
10499
10500                 /* XXX: this works for video mode only */
10501                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10502                 if (!(tmp & DPI_ENABLE))
10503                         continue;
10504
10505                 tmp = I915_READ(MIPI_CTRL(port));
10506                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10507                         continue;
10508
10509                 pipe_config->cpu_transcoder = cpu_transcoder;
10510                 break;
10511         }
10512
10513         return transcoder_is_dsi(pipe_config->cpu_transcoder);
10514 }
10515
10516 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10517                                        struct intel_crtc_state *pipe_config)
10518 {
10519         struct drm_device *dev = crtc->base.dev;
10520         struct drm_i915_private *dev_priv = to_i915(dev);
10521         struct intel_shared_dpll *pll;
10522         enum port port;
10523         uint32_t tmp;
10524
10525         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10526
10527         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10528
10529         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10530                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10531         else if (IS_BROXTON(dev))
10532                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10533         else
10534                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10535
10536         pll = pipe_config->shared_dpll;
10537         if (pll) {
10538                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10539                                                  &pipe_config->dpll_hw_state));
10540         }
10541
10542         /*
10543          * Haswell has only FDI/PCH transcoder A. It is which is connected to
10544          * DDI E. So just check whether this pipe is wired to DDI E and whether
10545          * the PCH transcoder is on.
10546          */
10547         if (INTEL_INFO(dev)->gen < 9 &&
10548             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10549                 pipe_config->has_pch_encoder = true;
10550
10551                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10552                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10553                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10554
10555                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10556         }
10557 }
10558
10559 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10560                                     struct intel_crtc_state *pipe_config)
10561 {
10562         struct drm_device *dev = crtc->base.dev;
10563         struct drm_i915_private *dev_priv = to_i915(dev);
10564         enum intel_display_power_domain power_domain;
10565         unsigned long power_domain_mask;
10566         bool active;
10567
10568         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10569         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10570                 return false;
10571         power_domain_mask = BIT(power_domain);
10572
10573         pipe_config->shared_dpll = NULL;
10574
10575         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10576
10577         if (IS_BROXTON(dev_priv) &&
10578             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10579                 WARN_ON(active);
10580                 active = true;
10581         }
10582
10583         if (!active)
10584                 goto out;
10585
10586         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10587                 haswell_get_ddi_port_state(crtc, pipe_config);
10588                 intel_get_pipe_timings(crtc, pipe_config);
10589         }
10590
10591         intel_get_pipe_src_size(crtc, pipe_config);
10592
10593         pipe_config->gamma_mode =
10594                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10595
10596         if (INTEL_INFO(dev)->gen >= 9) {
10597                 skl_init_scalers(dev, crtc, pipe_config);
10598         }
10599
10600         if (INTEL_INFO(dev)->gen >= 9) {
10601                 pipe_config->scaler_state.scaler_id = -1;
10602                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10603         }
10604
10605         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10606         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10607                 power_domain_mask |= BIT(power_domain);
10608                 if (INTEL_INFO(dev)->gen >= 9)
10609                         skylake_get_pfit_config(crtc, pipe_config);
10610                 else
10611                         ironlake_get_pfit_config(crtc, pipe_config);
10612         }
10613
10614         if (IS_HASWELL(dev))
10615                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10616                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10617
10618         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10619             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10620                 pipe_config->pixel_multiplier =
10621                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10622         } else {
10623                 pipe_config->pixel_multiplier = 1;
10624         }
10625
10626 out:
10627         for_each_power_domain(power_domain, power_domain_mask)
10628                 intel_display_power_put(dev_priv, power_domain);
10629
10630         return active;
10631 }
10632
10633 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10634                                const struct intel_plane_state *plane_state)
10635 {
10636         struct drm_device *dev = crtc->dev;
10637         struct drm_i915_private *dev_priv = to_i915(dev);
10638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10639         uint32_t cntl = 0, size = 0;
10640
10641         if (plane_state && plane_state->base.visible) {
10642                 unsigned int width = plane_state->base.crtc_w;
10643                 unsigned int height = plane_state->base.crtc_h;
10644                 unsigned int stride = roundup_pow_of_two(width) * 4;
10645
10646                 switch (stride) {
10647                 default:
10648                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10649                                   width, stride);
10650                         stride = 256;
10651                         /* fallthrough */
10652                 case 256:
10653                 case 512:
10654                 case 1024:
10655                 case 2048:
10656                         break;
10657                 }
10658
10659                 cntl |= CURSOR_ENABLE |
10660                         CURSOR_GAMMA_ENABLE |
10661                         CURSOR_FORMAT_ARGB |
10662                         CURSOR_STRIDE(stride);
10663
10664                 size = (height << 12) | width;
10665         }
10666
10667         if (intel_crtc->cursor_cntl != 0 &&
10668             (intel_crtc->cursor_base != base ||
10669              intel_crtc->cursor_size != size ||
10670              intel_crtc->cursor_cntl != cntl)) {
10671                 /* On these chipsets we can only modify the base/size/stride
10672                  * whilst the cursor is disabled.
10673                  */
10674                 I915_WRITE(CURCNTR(PIPE_A), 0);
10675                 POSTING_READ(CURCNTR(PIPE_A));
10676                 intel_crtc->cursor_cntl = 0;
10677         }
10678
10679         if (intel_crtc->cursor_base != base) {
10680                 I915_WRITE(CURBASE(PIPE_A), base);
10681                 intel_crtc->cursor_base = base;
10682         }
10683
10684         if (intel_crtc->cursor_size != size) {
10685                 I915_WRITE(CURSIZE, size);
10686                 intel_crtc->cursor_size = size;
10687         }
10688
10689         if (intel_crtc->cursor_cntl != cntl) {
10690                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10691                 POSTING_READ(CURCNTR(PIPE_A));
10692                 intel_crtc->cursor_cntl = cntl;
10693         }
10694 }
10695
10696 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10697                                const struct intel_plane_state *plane_state)
10698 {
10699         struct drm_device *dev = crtc->dev;
10700         struct drm_i915_private *dev_priv = to_i915(dev);
10701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702         int pipe = intel_crtc->pipe;
10703         uint32_t cntl = 0;
10704
10705         if (plane_state && plane_state->base.visible) {
10706                 cntl = MCURSOR_GAMMA_ENABLE;
10707                 switch (plane_state->base.crtc_w) {
10708                         case 64:
10709                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10710                                 break;
10711                         case 128:
10712                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10713                                 break;
10714                         case 256:
10715                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10716                                 break;
10717                         default:
10718                                 MISSING_CASE(plane_state->base.crtc_w);
10719                                 return;
10720                 }
10721                 cntl |= pipe << 28; /* Connect to correct pipe */
10722
10723                 if (HAS_DDI(dev))
10724                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10725
10726                 if (plane_state->base.rotation == DRM_ROTATE_180)
10727                         cntl |= CURSOR_ROTATE_180;
10728         }
10729
10730         if (intel_crtc->cursor_cntl != cntl) {
10731                 I915_WRITE(CURCNTR(pipe), cntl);
10732                 POSTING_READ(CURCNTR(pipe));
10733                 intel_crtc->cursor_cntl = cntl;
10734         }
10735
10736         /* and commit changes on next vblank */
10737         I915_WRITE(CURBASE(pipe), base);
10738         POSTING_READ(CURBASE(pipe));
10739
10740         intel_crtc->cursor_base = base;
10741 }
10742
10743 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10744 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10745                                      const struct intel_plane_state *plane_state)
10746 {
10747         struct drm_device *dev = crtc->dev;
10748         struct drm_i915_private *dev_priv = to_i915(dev);
10749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10750         int pipe = intel_crtc->pipe;
10751         u32 base = intel_crtc->cursor_addr;
10752         u32 pos = 0;
10753
10754         if (plane_state) {
10755                 int x = plane_state->base.crtc_x;
10756                 int y = plane_state->base.crtc_y;
10757
10758                 if (x < 0) {
10759                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10760                         x = -x;
10761                 }
10762                 pos |= x << CURSOR_X_SHIFT;
10763
10764                 if (y < 0) {
10765                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10766                         y = -y;
10767                 }
10768                 pos |= y << CURSOR_Y_SHIFT;
10769
10770                 /* ILK+ do this automagically */
10771                 if (HAS_GMCH_DISPLAY(dev) &&
10772                     plane_state->base.rotation == DRM_ROTATE_180) {
10773                         base += (plane_state->base.crtc_h *
10774                                  plane_state->base.crtc_w - 1) * 4;
10775                 }
10776         }
10777
10778         I915_WRITE(CURPOS(pipe), pos);
10779
10780         if (IS_845G(dev) || IS_I865G(dev))
10781                 i845_update_cursor(crtc, base, plane_state);
10782         else
10783                 i9xx_update_cursor(crtc, base, plane_state);
10784 }
10785
10786 static bool cursor_size_ok(struct drm_device *dev,
10787                            uint32_t width, uint32_t height)
10788 {
10789         if (width == 0 || height == 0)
10790                 return false;
10791
10792         /*
10793          * 845g/865g are special in that they are only limited by
10794          * the width of their cursors, the height is arbitrary up to
10795          * the precision of the register. Everything else requires
10796          * square cursors, limited to a few power-of-two sizes.
10797          */
10798         if (IS_845G(dev) || IS_I865G(dev)) {
10799                 if ((width & 63) != 0)
10800                         return false;
10801
10802                 if (width > (IS_845G(dev) ? 64 : 512))
10803                         return false;
10804
10805                 if (height > 1023)
10806                         return false;
10807         } else {
10808                 switch (width | height) {
10809                 case 256:
10810                 case 128:
10811                         if (IS_GEN2(dev))
10812                                 return false;
10813                 case 64:
10814                         break;
10815                 default:
10816                         return false;
10817                 }
10818         }
10819
10820         return true;
10821 }
10822
10823 /* VESA 640x480x72Hz mode to set on the pipe */
10824 static struct drm_display_mode load_detect_mode = {
10825         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10826                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10827 };
10828
10829 struct drm_framebuffer *
10830 __intel_framebuffer_create(struct drm_device *dev,
10831                            struct drm_mode_fb_cmd2 *mode_cmd,
10832                            struct drm_i915_gem_object *obj)
10833 {
10834         struct intel_framebuffer *intel_fb;
10835         int ret;
10836
10837         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10838         if (!intel_fb)
10839                 return ERR_PTR(-ENOMEM);
10840
10841         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10842         if (ret)
10843                 goto err;
10844
10845         return &intel_fb->base;
10846
10847 err:
10848         kfree(intel_fb);
10849         return ERR_PTR(ret);
10850 }
10851
10852 static struct drm_framebuffer *
10853 intel_framebuffer_create(struct drm_device *dev,
10854                          struct drm_mode_fb_cmd2 *mode_cmd,
10855                          struct drm_i915_gem_object *obj)
10856 {
10857         struct drm_framebuffer *fb;
10858         int ret;
10859
10860         ret = i915_mutex_lock_interruptible(dev);
10861         if (ret)
10862                 return ERR_PTR(ret);
10863         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10864         mutex_unlock(&dev->struct_mutex);
10865
10866         return fb;
10867 }
10868
10869 static u32
10870 intel_framebuffer_pitch_for_width(int width, int bpp)
10871 {
10872         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10873         return ALIGN(pitch, 64);
10874 }
10875
10876 static u32
10877 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10878 {
10879         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10880         return PAGE_ALIGN(pitch * mode->vdisplay);
10881 }
10882
10883 static struct drm_framebuffer *
10884 intel_framebuffer_create_for_mode(struct drm_device *dev,
10885                                   struct drm_display_mode *mode,
10886                                   int depth, int bpp)
10887 {
10888         struct drm_framebuffer *fb;
10889         struct drm_i915_gem_object *obj;
10890         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10891
10892         obj = i915_gem_object_create(dev,
10893                                     intel_framebuffer_size_for_mode(mode, bpp));
10894         if (IS_ERR(obj))
10895                 return ERR_CAST(obj);
10896
10897         mode_cmd.width = mode->hdisplay;
10898         mode_cmd.height = mode->vdisplay;
10899         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10900                                                                 bpp);
10901         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10902
10903         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10904         if (IS_ERR(fb))
10905                 i915_gem_object_put_unlocked(obj);
10906
10907         return fb;
10908 }
10909
10910 static struct drm_framebuffer *
10911 mode_fits_in_fbdev(struct drm_device *dev,
10912                    struct drm_display_mode *mode)
10913 {
10914 #ifdef CONFIG_DRM_FBDEV_EMULATION
10915         struct drm_i915_private *dev_priv = to_i915(dev);
10916         struct drm_i915_gem_object *obj;
10917         struct drm_framebuffer *fb;
10918
10919         if (!dev_priv->fbdev)
10920                 return NULL;
10921
10922         if (!dev_priv->fbdev->fb)
10923                 return NULL;
10924
10925         obj = dev_priv->fbdev->fb->obj;
10926         BUG_ON(!obj);
10927
10928         fb = &dev_priv->fbdev->fb->base;
10929         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10930                                                                fb->bits_per_pixel))
10931                 return NULL;
10932
10933         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10934                 return NULL;
10935
10936         drm_framebuffer_reference(fb);
10937         return fb;
10938 #else
10939         return NULL;
10940 #endif
10941 }
10942
10943 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10944                                            struct drm_crtc *crtc,
10945                                            struct drm_display_mode *mode,
10946                                            struct drm_framebuffer *fb,
10947                                            int x, int y)
10948 {
10949         struct drm_plane_state *plane_state;
10950         int hdisplay, vdisplay;
10951         int ret;
10952
10953         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10954         if (IS_ERR(plane_state))
10955                 return PTR_ERR(plane_state);
10956
10957         if (mode)
10958                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10959         else
10960                 hdisplay = vdisplay = 0;
10961
10962         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10963         if (ret)
10964                 return ret;
10965         drm_atomic_set_fb_for_plane(plane_state, fb);
10966         plane_state->crtc_x = 0;
10967         plane_state->crtc_y = 0;
10968         plane_state->crtc_w = hdisplay;
10969         plane_state->crtc_h = vdisplay;
10970         plane_state->src_x = x << 16;
10971         plane_state->src_y = y << 16;
10972         plane_state->src_w = hdisplay << 16;
10973         plane_state->src_h = vdisplay << 16;
10974
10975         return 0;
10976 }
10977
10978 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10979                                 struct drm_display_mode *mode,
10980                                 struct intel_load_detect_pipe *old,
10981                                 struct drm_modeset_acquire_ctx *ctx)
10982 {
10983         struct intel_crtc *intel_crtc;
10984         struct intel_encoder *intel_encoder =
10985                 intel_attached_encoder(connector);
10986         struct drm_crtc *possible_crtc;
10987         struct drm_encoder *encoder = &intel_encoder->base;
10988         struct drm_crtc *crtc = NULL;
10989         struct drm_device *dev = encoder->dev;
10990         struct drm_framebuffer *fb;
10991         struct drm_mode_config *config = &dev->mode_config;
10992         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10993         struct drm_connector_state *connector_state;
10994         struct intel_crtc_state *crtc_state;
10995         int ret, i = -1;
10996
10997         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10998                       connector->base.id, connector->name,
10999                       encoder->base.id, encoder->name);
11000
11001         old->restore_state = NULL;
11002
11003 retry:
11004         ret = drm_modeset_lock(&config->connection_mutex, ctx);
11005         if (ret)
11006                 goto fail;
11007
11008         /*
11009          * Algorithm gets a little messy:
11010          *
11011          *   - if the connector already has an assigned crtc, use it (but make
11012          *     sure it's on first)
11013          *
11014          *   - try to find the first unused crtc that can drive this connector,
11015          *     and use that if we find one
11016          */
11017
11018         /* See if we already have a CRTC for this connector */
11019         if (connector->state->crtc) {
11020                 crtc = connector->state->crtc;
11021
11022                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11023                 if (ret)
11024                         goto fail;
11025
11026                 /* Make sure the crtc and connector are running */
11027                 goto found;
11028         }
11029
11030         /* Find an unused one (if possible) */
11031         for_each_crtc(dev, possible_crtc) {
11032                 i++;
11033                 if (!(encoder->possible_crtcs & (1 << i)))
11034                         continue;
11035
11036                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11037                 if (ret)
11038                         goto fail;
11039
11040                 if (possible_crtc->state->enable) {
11041                         drm_modeset_unlock(&possible_crtc->mutex);
11042                         continue;
11043                 }
11044
11045                 crtc = possible_crtc;
11046                 break;
11047         }
11048
11049         /*
11050          * If we didn't find an unused CRTC, don't use any.
11051          */
11052         if (!crtc) {
11053                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11054                 goto fail;
11055         }
11056
11057 found:
11058         intel_crtc = to_intel_crtc(crtc);
11059
11060         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11061         if (ret)
11062                 goto fail;
11063
11064         state = drm_atomic_state_alloc(dev);
11065         restore_state = drm_atomic_state_alloc(dev);
11066         if (!state || !restore_state) {
11067                 ret = -ENOMEM;
11068                 goto fail;
11069         }
11070
11071         state->acquire_ctx = ctx;
11072         restore_state->acquire_ctx = ctx;
11073
11074         connector_state = drm_atomic_get_connector_state(state, connector);
11075         if (IS_ERR(connector_state)) {
11076                 ret = PTR_ERR(connector_state);
11077                 goto fail;
11078         }
11079
11080         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11081         if (ret)
11082                 goto fail;
11083
11084         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11085         if (IS_ERR(crtc_state)) {
11086                 ret = PTR_ERR(crtc_state);
11087                 goto fail;
11088         }
11089
11090         crtc_state->base.active = crtc_state->base.enable = true;
11091
11092         if (!mode)
11093                 mode = &load_detect_mode;
11094
11095         /* We need a framebuffer large enough to accommodate all accesses
11096          * that the plane may generate whilst we perform load detection.
11097          * We can not rely on the fbcon either being present (we get called
11098          * during its initialisation to detect all boot displays, or it may
11099          * not even exist) or that it is large enough to satisfy the
11100          * requested mode.
11101          */
11102         fb = mode_fits_in_fbdev(dev, mode);
11103         if (fb == NULL) {
11104                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11105                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11106         } else
11107                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11108         if (IS_ERR(fb)) {
11109                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11110                 goto fail;
11111         }
11112
11113         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11114         if (ret)
11115                 goto fail;
11116
11117         drm_framebuffer_unreference(fb);
11118
11119         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11120         if (ret)
11121                 goto fail;
11122
11123         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11124         if (!ret)
11125                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11126         if (!ret)
11127                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11128         if (ret) {
11129                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11130                 goto fail;
11131         }
11132
11133         ret = drm_atomic_commit(state);
11134         if (ret) {
11135                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11136                 goto fail;
11137         }
11138
11139         old->restore_state = restore_state;
11140
11141         /* let the connector get through one full cycle before testing */
11142         intel_wait_for_vblank(dev, intel_crtc->pipe);
11143         return true;
11144
11145 fail:
11146         drm_atomic_state_free(state);
11147         drm_atomic_state_free(restore_state);
11148         restore_state = state = NULL;
11149
11150         if (ret == -EDEADLK) {
11151                 drm_modeset_backoff(ctx);
11152                 goto retry;
11153         }
11154
11155         return false;
11156 }
11157
11158 void intel_release_load_detect_pipe(struct drm_connector *connector,
11159                                     struct intel_load_detect_pipe *old,
11160                                     struct drm_modeset_acquire_ctx *ctx)
11161 {
11162         struct intel_encoder *intel_encoder =
11163                 intel_attached_encoder(connector);
11164         struct drm_encoder *encoder = &intel_encoder->base;
11165         struct drm_atomic_state *state = old->restore_state;
11166         int ret;
11167
11168         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11169                       connector->base.id, connector->name,
11170                       encoder->base.id, encoder->name);
11171
11172         if (!state)
11173                 return;
11174
11175         ret = drm_atomic_commit(state);
11176         if (ret) {
11177                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11178                 drm_atomic_state_free(state);
11179         }
11180 }
11181
11182 static int i9xx_pll_refclk(struct drm_device *dev,
11183                            const struct intel_crtc_state *pipe_config)
11184 {
11185         struct drm_i915_private *dev_priv = to_i915(dev);
11186         u32 dpll = pipe_config->dpll_hw_state.dpll;
11187
11188         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11189                 return dev_priv->vbt.lvds_ssc_freq;
11190         else if (HAS_PCH_SPLIT(dev))
11191                 return 120000;
11192         else if (!IS_GEN2(dev))
11193                 return 96000;
11194         else
11195                 return 48000;
11196 }
11197
11198 /* Returns the clock of the currently programmed mode of the given pipe. */
11199 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11200                                 struct intel_crtc_state *pipe_config)
11201 {
11202         struct drm_device *dev = crtc->base.dev;
11203         struct drm_i915_private *dev_priv = to_i915(dev);
11204         int pipe = pipe_config->cpu_transcoder;
11205         u32 dpll = pipe_config->dpll_hw_state.dpll;
11206         u32 fp;
11207         struct dpll clock;
11208         int port_clock;
11209         int refclk = i9xx_pll_refclk(dev, pipe_config);
11210
11211         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11212                 fp = pipe_config->dpll_hw_state.fp0;
11213         else
11214                 fp = pipe_config->dpll_hw_state.fp1;
11215
11216         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11217         if (IS_PINEVIEW(dev)) {
11218                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11219                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11220         } else {
11221                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11222                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11223         }
11224
11225         if (!IS_GEN2(dev)) {
11226                 if (IS_PINEVIEW(dev))
11227                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11228                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11229                 else
11230                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11231                                DPLL_FPA01_P1_POST_DIV_SHIFT);
11232
11233                 switch (dpll & DPLL_MODE_MASK) {
11234                 case DPLLB_MODE_DAC_SERIAL:
11235                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11236                                 5 : 10;
11237                         break;
11238                 case DPLLB_MODE_LVDS:
11239                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11240                                 7 : 14;
11241                         break;
11242                 default:
11243                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11244                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
11245                         return;
11246                 }
11247
11248                 if (IS_PINEVIEW(dev))
11249                         port_clock = pnv_calc_dpll_params(refclk, &clock);
11250                 else
11251                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
11252         } else {
11253                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11254                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11255
11256                 if (is_lvds) {
11257                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11258                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
11259
11260                         if (lvds & LVDS_CLKB_POWER_UP)
11261                                 clock.p2 = 7;
11262                         else
11263                                 clock.p2 = 14;
11264                 } else {
11265                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
11266                                 clock.p1 = 2;
11267                         else {
11268                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11269                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11270                         }
11271                         if (dpll & PLL_P2_DIVIDE_BY_4)
11272                                 clock.p2 = 4;
11273                         else
11274                                 clock.p2 = 2;
11275                 }
11276
11277                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11278         }
11279
11280         /*
11281          * This value includes pixel_multiplier. We will use
11282          * port_clock to compute adjusted_mode.crtc_clock in the
11283          * encoder's get_config() function.
11284          */
11285         pipe_config->port_clock = port_clock;
11286 }
11287
11288 int intel_dotclock_calculate(int link_freq,
11289                              const struct intel_link_m_n *m_n)
11290 {
11291         /*
11292          * The calculation for the data clock is:
11293          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11294          * But we want to avoid losing precison if possible, so:
11295          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11296          *
11297          * and the link clock is simpler:
11298          * link_clock = (m * link_clock) / n
11299          */
11300
11301         if (!m_n->link_n)
11302                 return 0;
11303
11304         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11305 }
11306
11307 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11308                                    struct intel_crtc_state *pipe_config)
11309 {
11310         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11311
11312         /* read out port_clock from the DPLL */
11313         i9xx_crtc_clock_get(crtc, pipe_config);
11314
11315         /*
11316          * In case there is an active pipe without active ports,
11317          * we may need some idea for the dotclock anyway.
11318          * Calculate one based on the FDI configuration.
11319          */
11320         pipe_config->base.adjusted_mode.crtc_clock =
11321                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11322                                          &pipe_config->fdi_m_n);
11323 }
11324
11325 /** Returns the currently programmed mode of the given pipe. */
11326 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11327                                              struct drm_crtc *crtc)
11328 {
11329         struct drm_i915_private *dev_priv = to_i915(dev);
11330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
11332         struct drm_display_mode *mode;
11333         struct intel_crtc_state *pipe_config;
11334         int htot = I915_READ(HTOTAL(cpu_transcoder));
11335         int hsync = I915_READ(HSYNC(cpu_transcoder));
11336         int vtot = I915_READ(VTOTAL(cpu_transcoder));
11337         int vsync = I915_READ(VSYNC(cpu_transcoder));
11338         enum pipe pipe = intel_crtc->pipe;
11339
11340         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11341         if (!mode)
11342                 return NULL;
11343
11344         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11345         if (!pipe_config) {
11346                 kfree(mode);
11347                 return NULL;
11348         }
11349
11350         /*
11351          * Construct a pipe_config sufficient for getting the clock info
11352          * back out of crtc_clock_get.
11353          *
11354          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11355          * to use a real value here instead.
11356          */
11357         pipe_config->cpu_transcoder = (enum transcoder) pipe;
11358         pipe_config->pixel_multiplier = 1;
11359         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11360         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11361         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11362         i9xx_crtc_clock_get(intel_crtc, pipe_config);
11363
11364         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11365         mode->hdisplay = (htot & 0xffff) + 1;
11366         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11367         mode->hsync_start = (hsync & 0xffff) + 1;
11368         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11369         mode->vdisplay = (vtot & 0xffff) + 1;
11370         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11371         mode->vsync_start = (vsync & 0xffff) + 1;
11372         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11373
11374         drm_mode_set_name(mode);
11375
11376         kfree(pipe_config);
11377
11378         return mode;
11379 }
11380
11381 static void intel_crtc_destroy(struct drm_crtc *crtc)
11382 {
11383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11384         struct drm_device *dev = crtc->dev;
11385         struct intel_flip_work *work;
11386
11387         spin_lock_irq(&dev->event_lock);
11388         work = intel_crtc->flip_work;
11389         intel_crtc->flip_work = NULL;
11390         spin_unlock_irq(&dev->event_lock);
11391
11392         if (work) {
11393                 cancel_work_sync(&work->mmio_work);
11394                 cancel_work_sync(&work->unpin_work);
11395                 kfree(work);
11396         }
11397
11398         drm_crtc_cleanup(crtc);
11399
11400         kfree(intel_crtc);
11401 }
11402
11403 static void intel_unpin_work_fn(struct work_struct *__work)
11404 {
11405         struct intel_flip_work *work =
11406                 container_of(__work, struct intel_flip_work, unpin_work);
11407         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11408         struct drm_device *dev = crtc->base.dev;
11409         struct drm_plane *primary = crtc->base.primary;
11410
11411         if (is_mmio_work(work))
11412                 flush_work(&work->mmio_work);
11413
11414         mutex_lock(&dev->struct_mutex);
11415         intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11416         i915_gem_object_put(work->pending_flip_obj);
11417         mutex_unlock(&dev->struct_mutex);
11418
11419         i915_gem_request_put(work->flip_queued_req);
11420
11421         intel_frontbuffer_flip_complete(to_i915(dev),
11422                                         to_intel_plane(primary)->frontbuffer_bit);
11423         intel_fbc_post_update(crtc);
11424         drm_framebuffer_unreference(work->old_fb);
11425
11426         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11427         atomic_dec(&crtc->unpin_work_count);
11428
11429         kfree(work);
11430 }
11431
11432 /* Is 'a' after or equal to 'b'? */
11433 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11434 {
11435         return !((a - b) & 0x80000000);
11436 }
11437
11438 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11439                                    struct intel_flip_work *work)
11440 {
11441         struct drm_device *dev = crtc->base.dev;
11442         struct drm_i915_private *dev_priv = to_i915(dev);
11443         unsigned reset_counter;
11444
11445         reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11446         if (crtc->reset_counter != reset_counter)
11447                 return true;
11448
11449         /*
11450          * The relevant registers doen't exist on pre-ctg.
11451          * As the flip done interrupt doesn't trigger for mmio
11452          * flips on gmch platforms, a flip count check isn't
11453          * really needed there. But since ctg has the registers,
11454          * include it in the check anyway.
11455          */
11456         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11457                 return true;
11458
11459         /*
11460          * BDW signals flip done immediately if the plane
11461          * is disabled, even if the plane enable is already
11462          * armed to occur at the next vblank :(
11463          */
11464
11465         /*
11466          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11467          * used the same base address. In that case the mmio flip might
11468          * have completed, but the CS hasn't even executed the flip yet.
11469          *
11470          * A flip count check isn't enough as the CS might have updated
11471          * the base address just after start of vblank, but before we
11472          * managed to process the interrupt. This means we'd complete the
11473          * CS flip too soon.
11474          *
11475          * Combining both checks should get us a good enough result. It may
11476          * still happen that the CS flip has been executed, but has not
11477          * yet actually completed. But in case the base address is the same
11478          * anyway, we don't really care.
11479          */
11480         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11481                 crtc->flip_work->gtt_offset &&
11482                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11483                                     crtc->flip_work->flip_count);
11484 }
11485
11486 static bool
11487 __pageflip_finished_mmio(struct intel_crtc *crtc,
11488                                struct intel_flip_work *work)
11489 {
11490         /*
11491          * MMIO work completes when vblank is different from
11492          * flip_queued_vblank.
11493          *
11494          * Reset counter value doesn't matter, this is handled by
11495          * i915_wait_request finishing early, so no need to handle
11496          * reset here.
11497          */
11498         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11499 }
11500
11501
11502 static bool pageflip_finished(struct intel_crtc *crtc,
11503                               struct intel_flip_work *work)
11504 {
11505         if (!atomic_read(&work->pending))
11506                 return false;
11507
11508         smp_rmb();
11509
11510         if (is_mmio_work(work))
11511                 return __pageflip_finished_mmio(crtc, work);
11512         else
11513                 return __pageflip_finished_cs(crtc, work);
11514 }
11515
11516 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11517 {
11518         struct drm_device *dev = &dev_priv->drm;
11519         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11521         struct intel_flip_work *work;
11522         unsigned long flags;
11523
11524         /* Ignore early vblank irqs */
11525         if (!crtc)
11526                 return;
11527
11528         /*
11529          * This is called both by irq handlers and the reset code (to complete
11530          * lost pageflips) so needs the full irqsave spinlocks.
11531          */
11532         spin_lock_irqsave(&dev->event_lock, flags);
11533         work = intel_crtc->flip_work;
11534
11535         if (work != NULL &&
11536             !is_mmio_work(work) &&
11537             pageflip_finished(intel_crtc, work))
11538                 page_flip_completed(intel_crtc);
11539
11540         spin_unlock_irqrestore(&dev->event_lock, flags);
11541 }
11542
11543 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11544 {
11545         struct drm_device *dev = &dev_priv->drm;
11546         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11548         struct intel_flip_work *work;
11549         unsigned long flags;
11550
11551         /* Ignore early vblank irqs */
11552         if (!crtc)
11553                 return;
11554
11555         /*
11556          * This is called both by irq handlers and the reset code (to complete
11557          * lost pageflips) so needs the full irqsave spinlocks.
11558          */
11559         spin_lock_irqsave(&dev->event_lock, flags);
11560         work = intel_crtc->flip_work;
11561
11562         if (work != NULL &&
11563             is_mmio_work(work) &&
11564             pageflip_finished(intel_crtc, work))
11565                 page_flip_completed(intel_crtc);
11566
11567         spin_unlock_irqrestore(&dev->event_lock, flags);
11568 }
11569
11570 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11571                                                struct intel_flip_work *work)
11572 {
11573         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11574
11575         /* Ensure that the work item is consistent when activating it ... */
11576         smp_mb__before_atomic();
11577         atomic_set(&work->pending, 1);
11578 }
11579
11580 static int intel_gen2_queue_flip(struct drm_device *dev,
11581                                  struct drm_crtc *crtc,
11582                                  struct drm_framebuffer *fb,
11583                                  struct drm_i915_gem_object *obj,
11584                                  struct drm_i915_gem_request *req,
11585                                  uint32_t flags)
11586 {
11587         struct intel_ring *ring = req->ring;
11588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11589         u32 flip_mask;
11590         int ret;
11591
11592         ret = intel_ring_begin(req, 6);
11593         if (ret)
11594                 return ret;
11595
11596         /* Can't queue multiple flips, so wait for the previous
11597          * one to finish before executing the next.
11598          */
11599         if (intel_crtc->plane)
11600                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11601         else
11602                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11603         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11604         intel_ring_emit(ring, MI_NOOP);
11605         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11606                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11607         intel_ring_emit(ring, fb->pitches[0]);
11608         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11609         intel_ring_emit(ring, 0); /* aux display base address, unused */
11610
11611         return 0;
11612 }
11613
11614 static int intel_gen3_queue_flip(struct drm_device *dev,
11615                                  struct drm_crtc *crtc,
11616                                  struct drm_framebuffer *fb,
11617                                  struct drm_i915_gem_object *obj,
11618                                  struct drm_i915_gem_request *req,
11619                                  uint32_t flags)
11620 {
11621         struct intel_ring *ring = req->ring;
11622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11623         u32 flip_mask;
11624         int ret;
11625
11626         ret = intel_ring_begin(req, 6);
11627         if (ret)
11628                 return ret;
11629
11630         if (intel_crtc->plane)
11631                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11632         else
11633                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11634         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11635         intel_ring_emit(ring, MI_NOOP);
11636         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11637                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11638         intel_ring_emit(ring, fb->pitches[0]);
11639         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11640         intel_ring_emit(ring, MI_NOOP);
11641
11642         return 0;
11643 }
11644
11645 static int intel_gen4_queue_flip(struct drm_device *dev,
11646                                  struct drm_crtc *crtc,
11647                                  struct drm_framebuffer *fb,
11648                                  struct drm_i915_gem_object *obj,
11649                                  struct drm_i915_gem_request *req,
11650                                  uint32_t flags)
11651 {
11652         struct intel_ring *ring = req->ring;
11653         struct drm_i915_private *dev_priv = to_i915(dev);
11654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11655         uint32_t pf, pipesrc;
11656         int ret;
11657
11658         ret = intel_ring_begin(req, 4);
11659         if (ret)
11660                 return ret;
11661
11662         /* i965+ uses the linear or tiled offsets from the
11663          * Display Registers (which do not change across a page-flip)
11664          * so we need only reprogram the base address.
11665          */
11666         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11667                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11668         intel_ring_emit(ring, fb->pitches[0]);
11669         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11670                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11671
11672         /* XXX Enabling the panel-fitter across page-flip is so far
11673          * untested on non-native modes, so ignore it for now.
11674          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11675          */
11676         pf = 0;
11677         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11678         intel_ring_emit(ring, pf | pipesrc);
11679
11680         return 0;
11681 }
11682
11683 static int intel_gen6_queue_flip(struct drm_device *dev,
11684                                  struct drm_crtc *crtc,
11685                                  struct drm_framebuffer *fb,
11686                                  struct drm_i915_gem_object *obj,
11687                                  struct drm_i915_gem_request *req,
11688                                  uint32_t flags)
11689 {
11690         struct intel_ring *ring = req->ring;
11691         struct drm_i915_private *dev_priv = to_i915(dev);
11692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11693         uint32_t pf, pipesrc;
11694         int ret;
11695
11696         ret = intel_ring_begin(req, 4);
11697         if (ret)
11698                 return ret;
11699
11700         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11701                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11702         intel_ring_emit(ring, fb->pitches[0] |
11703                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11704         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11705
11706         /* Contrary to the suggestions in the documentation,
11707          * "Enable Panel Fitter" does not seem to be required when page
11708          * flipping with a non-native mode, and worse causes a normal
11709          * modeset to fail.
11710          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11711          */
11712         pf = 0;
11713         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11714         intel_ring_emit(ring, pf | pipesrc);
11715
11716         return 0;
11717 }
11718
11719 static int intel_gen7_queue_flip(struct drm_device *dev,
11720                                  struct drm_crtc *crtc,
11721                                  struct drm_framebuffer *fb,
11722                                  struct drm_i915_gem_object *obj,
11723                                  struct drm_i915_gem_request *req,
11724                                  uint32_t flags)
11725 {
11726         struct intel_ring *ring = req->ring;
11727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11728         uint32_t plane_bit = 0;
11729         int len, ret;
11730
11731         switch (intel_crtc->plane) {
11732         case PLANE_A:
11733                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11734                 break;
11735         case PLANE_B:
11736                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11737                 break;
11738         case PLANE_C:
11739                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11740                 break;
11741         default:
11742                 WARN_ONCE(1, "unknown plane in flip command\n");
11743                 return -ENODEV;
11744         }
11745
11746         len = 4;
11747         if (req->engine->id == RCS) {
11748                 len += 6;
11749                 /*
11750                  * On Gen 8, SRM is now taking an extra dword to accommodate
11751                  * 48bits addresses, and we need a NOOP for the batch size to
11752                  * stay even.
11753                  */
11754                 if (IS_GEN8(dev))
11755                         len += 2;
11756         }
11757
11758         /*
11759          * BSpec MI_DISPLAY_FLIP for IVB:
11760          * "The full packet must be contained within the same cache line."
11761          *
11762          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11763          * cacheline, if we ever start emitting more commands before
11764          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11765          * then do the cacheline alignment, and finally emit the
11766          * MI_DISPLAY_FLIP.
11767          */
11768         ret = intel_ring_cacheline_align(req);
11769         if (ret)
11770                 return ret;
11771
11772         ret = intel_ring_begin(req, len);
11773         if (ret)
11774                 return ret;
11775
11776         /* Unmask the flip-done completion message. Note that the bspec says that
11777          * we should do this for both the BCS and RCS, and that we must not unmask
11778          * more than one flip event at any time (or ensure that one flip message
11779          * can be sent by waiting for flip-done prior to queueing new flips).
11780          * Experimentation says that BCS works despite DERRMR masking all
11781          * flip-done completion events and that unmasking all planes at once
11782          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11783          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11784          */
11785         if (req->engine->id == RCS) {
11786                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11787                 intel_ring_emit_reg(ring, DERRMR);
11788                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11789                                           DERRMR_PIPEB_PRI_FLIP_DONE |
11790                                           DERRMR_PIPEC_PRI_FLIP_DONE));
11791                 if (IS_GEN8(dev))
11792                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11793                                               MI_SRM_LRM_GLOBAL_GTT);
11794                 else
11795                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11796                                               MI_SRM_LRM_GLOBAL_GTT);
11797                 intel_ring_emit_reg(ring, DERRMR);
11798                 intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
11799                 if (IS_GEN8(dev)) {
11800                         intel_ring_emit(ring, 0);
11801                         intel_ring_emit(ring, MI_NOOP);
11802                 }
11803         }
11804
11805         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11806         intel_ring_emit(ring, fb->pitches[0] |
11807                         intel_fb_modifier_to_tiling(fb->modifier[0]));
11808         intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11809         intel_ring_emit(ring, (MI_NOOP));
11810
11811         return 0;
11812 }
11813
11814 static bool use_mmio_flip(struct intel_engine_cs *engine,
11815                           struct drm_i915_gem_object *obj)
11816 {
11817         struct reservation_object *resv;
11818
11819         /*
11820          * This is not being used for older platforms, because
11821          * non-availability of flip done interrupt forces us to use
11822          * CS flips. Older platforms derive flip done using some clever
11823          * tricks involving the flip_pending status bits and vblank irqs.
11824          * So using MMIO flips there would disrupt this mechanism.
11825          */
11826
11827         if (engine == NULL)
11828                 return true;
11829
11830         if (INTEL_GEN(engine->i915) < 5)
11831                 return false;
11832
11833         if (i915.use_mmio_flip < 0)
11834                 return false;
11835         else if (i915.use_mmio_flip > 0)
11836                 return true;
11837         else if (i915.enable_execlists)
11838                 return true;
11839
11840         resv = i915_gem_object_get_dmabuf_resv(obj);
11841         if (resv && !reservation_object_test_signaled_rcu(resv, false))
11842                 return true;
11843
11844         return engine != i915_gem_active_get_engine(&obj->last_write,
11845                                                     &obj->base.dev->struct_mutex);
11846 }
11847
11848 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11849                              unsigned int rotation,
11850                              struct intel_flip_work *work)
11851 {
11852         struct drm_device *dev = intel_crtc->base.dev;
11853         struct drm_i915_private *dev_priv = to_i915(dev);
11854         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11855         const enum pipe pipe = intel_crtc->pipe;
11856         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
11857
11858         ctl = I915_READ(PLANE_CTL(pipe, 0));
11859         ctl &= ~PLANE_CTL_TILED_MASK;
11860         switch (fb->modifier[0]) {
11861         case DRM_FORMAT_MOD_NONE:
11862                 break;
11863         case I915_FORMAT_MOD_X_TILED:
11864                 ctl |= PLANE_CTL_TILED_X;
11865                 break;
11866         case I915_FORMAT_MOD_Y_TILED:
11867                 ctl |= PLANE_CTL_TILED_Y;
11868                 break;
11869         case I915_FORMAT_MOD_Yf_TILED:
11870                 ctl |= PLANE_CTL_TILED_YF;
11871                 break;
11872         default:
11873                 MISSING_CASE(fb->modifier[0]);
11874         }
11875
11876         /*
11877          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11878          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11879          */
11880         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11881         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11882
11883         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11884         POSTING_READ(PLANE_SURF(pipe, 0));
11885 }
11886
11887 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11888                              struct intel_flip_work *work)
11889 {
11890         struct drm_device *dev = intel_crtc->base.dev;
11891         struct drm_i915_private *dev_priv = to_i915(dev);
11892         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11893         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11894         u32 dspcntr;
11895
11896         dspcntr = I915_READ(reg);
11897
11898         if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
11899                 dspcntr |= DISPPLANE_TILED;
11900         else
11901                 dspcntr &= ~DISPPLANE_TILED;
11902
11903         I915_WRITE(reg, dspcntr);
11904
11905         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11906         POSTING_READ(DSPSURF(intel_crtc->plane));
11907 }
11908
11909 static void intel_mmio_flip_work_func(struct work_struct *w)
11910 {
11911         struct intel_flip_work *work =
11912                 container_of(w, struct intel_flip_work, mmio_work);
11913         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11914         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11915         struct intel_framebuffer *intel_fb =
11916                 to_intel_framebuffer(crtc->base.primary->fb);
11917         struct drm_i915_gem_object *obj = intel_fb->obj;
11918         struct reservation_object *resv;
11919
11920         if (work->flip_queued_req)
11921                 WARN_ON(i915_wait_request(work->flip_queued_req,
11922                                           false, NULL,
11923                                           NO_WAITBOOST));
11924
11925         /* For framebuffer backed by dmabuf, wait for fence */
11926         resv = i915_gem_object_get_dmabuf_resv(obj);
11927         if (resv)
11928                 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11929                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11930
11931         intel_pipe_update_start(crtc);
11932
11933         if (INTEL_GEN(dev_priv) >= 9)
11934                 skl_do_mmio_flip(crtc, work->rotation, work);
11935         else
11936                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11937                 ilk_do_mmio_flip(crtc, work);
11938
11939         intel_pipe_update_end(crtc, work);
11940 }
11941
11942 static int intel_default_queue_flip(struct drm_device *dev,
11943                                     struct drm_crtc *crtc,
11944                                     struct drm_framebuffer *fb,
11945                                     struct drm_i915_gem_object *obj,
11946                                     struct drm_i915_gem_request *req,
11947                                     uint32_t flags)
11948 {
11949         return -ENODEV;
11950 }
11951
11952 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11953                                       struct intel_crtc *intel_crtc,
11954                                       struct intel_flip_work *work)
11955 {
11956         u32 addr, vblank;
11957
11958         if (!atomic_read(&work->pending))
11959                 return false;
11960
11961         smp_rmb();
11962
11963         vblank = intel_crtc_get_vblank_counter(intel_crtc);
11964         if (work->flip_ready_vblank == 0) {
11965                 if (work->flip_queued_req &&
11966                     !i915_gem_request_completed(work->flip_queued_req))
11967                         return false;
11968
11969                 work->flip_ready_vblank = vblank;
11970         }
11971
11972         if (vblank - work->flip_ready_vblank < 3)
11973                 return false;
11974
11975         /* Potential stall - if we see that the flip has happened,
11976          * assume a missed interrupt. */
11977         if (INTEL_GEN(dev_priv) >= 4)
11978                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11979         else
11980                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11981
11982         /* There is a potential issue here with a false positive after a flip
11983          * to the same address. We could address this by checking for a
11984          * non-incrementing frame counter.
11985          */
11986         return addr == work->gtt_offset;
11987 }
11988
11989 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11990 {
11991         struct drm_device *dev = &dev_priv->drm;
11992         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11994         struct intel_flip_work *work;
11995
11996         WARN_ON(!in_interrupt());
11997
11998         if (crtc == NULL)
11999                 return;
12000
12001         spin_lock(&dev->event_lock);
12002         work = intel_crtc->flip_work;
12003
12004         if (work != NULL && !is_mmio_work(work) &&
12005             __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12006                 WARN_ONCE(1,
12007                           "Kicking stuck page flip: queued at %d, now %d\n",
12008                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12009                 page_flip_completed(intel_crtc);
12010                 work = NULL;
12011         }
12012
12013         if (work != NULL && !is_mmio_work(work) &&
12014             intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12015                 intel_queue_rps_boost_for_request(work->flip_queued_req);
12016         spin_unlock(&dev->event_lock);
12017 }
12018
12019 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12020                                 struct drm_framebuffer *fb,
12021                                 struct drm_pending_vblank_event *event,
12022                                 uint32_t page_flip_flags)
12023 {
12024         struct drm_device *dev = crtc->dev;
12025         struct drm_i915_private *dev_priv = to_i915(dev);
12026         struct drm_framebuffer *old_fb = crtc->primary->fb;
12027         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12029         struct drm_plane *primary = crtc->primary;
12030         enum pipe pipe = intel_crtc->pipe;
12031         struct intel_flip_work *work;
12032         struct intel_engine_cs *engine;
12033         bool mmio_flip;
12034         struct drm_i915_gem_request *request;
12035         int ret;
12036
12037         /*
12038          * drm_mode_page_flip_ioctl() should already catch this, but double
12039          * check to be safe.  In the future we may enable pageflipping from
12040          * a disabled primary plane.
12041          */
12042         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12043                 return -EBUSY;
12044
12045         /* Can't change pixel format via MI display flips. */
12046         if (fb->pixel_format != crtc->primary->fb->pixel_format)
12047                 return -EINVAL;
12048
12049         /*
12050          * TILEOFF/LINOFF registers can't be changed via MI display flips.
12051          * Note that pitch changes could also affect these register.
12052          */
12053         if (INTEL_INFO(dev)->gen > 3 &&
12054             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12055              fb->pitches[0] != crtc->primary->fb->pitches[0]))
12056                 return -EINVAL;
12057
12058         if (i915_terminally_wedged(&dev_priv->gpu_error))
12059                 goto out_hang;
12060
12061         work = kzalloc(sizeof(*work), GFP_KERNEL);
12062         if (work == NULL)
12063                 return -ENOMEM;
12064
12065         work->event = event;
12066         work->crtc = crtc;
12067         work->old_fb = old_fb;
12068         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12069
12070         ret = drm_crtc_vblank_get(crtc);
12071         if (ret)
12072                 goto free_work;
12073
12074         /* We borrow the event spin lock for protecting flip_work */
12075         spin_lock_irq(&dev->event_lock);
12076         if (intel_crtc->flip_work) {
12077                 /* Before declaring the flip queue wedged, check if
12078                  * the hardware completed the operation behind our backs.
12079                  */
12080                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12081                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12082                         page_flip_completed(intel_crtc);
12083                 } else {
12084                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12085                         spin_unlock_irq(&dev->event_lock);
12086
12087                         drm_crtc_vblank_put(crtc);
12088                         kfree(work);
12089                         return -EBUSY;
12090                 }
12091         }
12092         intel_crtc->flip_work = work;
12093         spin_unlock_irq(&dev->event_lock);
12094
12095         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12096                 flush_workqueue(dev_priv->wq);
12097
12098         /* Reference the objects for the scheduled work. */
12099         drm_framebuffer_reference(work->old_fb);
12100
12101         crtc->primary->fb = fb;
12102         update_state_fb(crtc->primary);
12103
12104         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12105                              to_intel_plane_state(primary->state));
12106
12107         work->pending_flip_obj = i915_gem_object_get(obj);
12108
12109         ret = i915_mutex_lock_interruptible(dev);
12110         if (ret)
12111                 goto cleanup;
12112
12113         intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
12114         if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
12115                 ret = -EIO;
12116                 goto cleanup;
12117         }
12118
12119         atomic_inc(&intel_crtc->unpin_work_count);
12120
12121         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12122                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12123
12124         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12125                 engine = &dev_priv->engine[BCS];
12126                 if (fb->modifier[0] != old_fb->modifier[0])
12127                         /* vlv: DISPLAY_FLIP fails to change tiling */
12128                         engine = NULL;
12129         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12130                 engine = &dev_priv->engine[BCS];
12131         } else if (INTEL_INFO(dev)->gen >= 7) {
12132                 engine = i915_gem_active_get_engine(&obj->last_write,
12133                                                     &obj->base.dev->struct_mutex);
12134                 if (engine == NULL || engine->id != RCS)
12135                         engine = &dev_priv->engine[BCS];
12136         } else {
12137                 engine = &dev_priv->engine[RCS];
12138         }
12139
12140         mmio_flip = use_mmio_flip(engine, obj);
12141
12142         ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12143         if (ret)
12144                 goto cleanup_pending;
12145
12146         work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12147         work->gtt_offset += intel_crtc->dspaddr_offset;
12148         work->rotation = crtc->primary->state->rotation;
12149
12150         if (mmio_flip) {
12151                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12152
12153                 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12154                                                             &obj->base.dev->struct_mutex);
12155                 schedule_work(&work->mmio_work);
12156         } else {
12157                 request = i915_gem_request_alloc(engine, engine->last_context);
12158                 if (IS_ERR(request)) {
12159                         ret = PTR_ERR(request);
12160                         goto cleanup_unpin;
12161                 }
12162
12163                 ret = i915_gem_object_sync(obj, request);
12164                 if (ret)
12165                         goto cleanup_request;
12166
12167                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12168                                                    page_flip_flags);
12169                 if (ret)
12170                         goto cleanup_request;
12171
12172                 intel_mark_page_flip_active(intel_crtc, work);
12173
12174                 work->flip_queued_req = i915_gem_request_get(request);
12175                 i915_add_request_no_flush(request);
12176         }
12177
12178         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12179                           to_intel_plane(primary)->frontbuffer_bit);
12180         mutex_unlock(&dev->struct_mutex);
12181
12182         intel_frontbuffer_flip_prepare(to_i915(dev),
12183                                        to_intel_plane(primary)->frontbuffer_bit);
12184
12185         trace_i915_flip_request(intel_crtc->plane, obj);
12186
12187         return 0;
12188
12189 cleanup_request:
12190         i915_add_request_no_flush(request);
12191 cleanup_unpin:
12192         intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12193 cleanup_pending:
12194         atomic_dec(&intel_crtc->unpin_work_count);
12195         mutex_unlock(&dev->struct_mutex);
12196 cleanup:
12197         crtc->primary->fb = old_fb;
12198         update_state_fb(crtc->primary);
12199
12200         i915_gem_object_put_unlocked(obj);
12201         drm_framebuffer_unreference(work->old_fb);
12202
12203         spin_lock_irq(&dev->event_lock);
12204         intel_crtc->flip_work = NULL;
12205         spin_unlock_irq(&dev->event_lock);
12206
12207         drm_crtc_vblank_put(crtc);
12208 free_work:
12209         kfree(work);
12210
12211         if (ret == -EIO) {
12212                 struct drm_atomic_state *state;
12213                 struct drm_plane_state *plane_state;
12214
12215 out_hang:
12216                 state = drm_atomic_state_alloc(dev);
12217                 if (!state)
12218                         return -ENOMEM;
12219                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12220
12221 retry:
12222                 plane_state = drm_atomic_get_plane_state(state, primary);
12223                 ret = PTR_ERR_OR_ZERO(plane_state);
12224                 if (!ret) {
12225                         drm_atomic_set_fb_for_plane(plane_state, fb);
12226
12227                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12228                         if (!ret)
12229                                 ret = drm_atomic_commit(state);
12230                 }
12231
12232                 if (ret == -EDEADLK) {
12233                         drm_modeset_backoff(state->acquire_ctx);
12234                         drm_atomic_state_clear(state);
12235                         goto retry;
12236                 }
12237
12238                 if (ret)
12239                         drm_atomic_state_free(state);
12240
12241                 if (ret == 0 && event) {
12242                         spin_lock_irq(&dev->event_lock);
12243                         drm_crtc_send_vblank_event(crtc, event);
12244                         spin_unlock_irq(&dev->event_lock);
12245                 }
12246         }
12247         return ret;
12248 }
12249
12250
12251 /**
12252  * intel_wm_need_update - Check whether watermarks need updating
12253  * @plane: drm plane
12254  * @state: new plane state
12255  *
12256  * Check current plane state versus the new one to determine whether
12257  * watermarks need to be recalculated.
12258  *
12259  * Returns true or false.
12260  */
12261 static bool intel_wm_need_update(struct drm_plane *plane,
12262                                  struct drm_plane_state *state)
12263 {
12264         struct intel_plane_state *new = to_intel_plane_state(state);
12265         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12266
12267         /* Update watermarks on tiling or size changes. */
12268         if (new->base.visible != cur->base.visible)
12269                 return true;
12270
12271         if (!cur->base.fb || !new->base.fb)
12272                 return false;
12273
12274         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12275             cur->base.rotation != new->base.rotation ||
12276             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12277             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12278             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12279             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12280                 return true;
12281
12282         return false;
12283 }
12284
12285 static bool needs_scaling(struct intel_plane_state *state)
12286 {
12287         int src_w = drm_rect_width(&state->base.src) >> 16;
12288         int src_h = drm_rect_height(&state->base.src) >> 16;
12289         int dst_w = drm_rect_width(&state->base.dst);
12290         int dst_h = drm_rect_height(&state->base.dst);
12291
12292         return (src_w != dst_w || src_h != dst_h);
12293 }
12294
12295 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12296                                     struct drm_plane_state *plane_state)
12297 {
12298         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12299         struct drm_crtc *crtc = crtc_state->crtc;
12300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12301         struct drm_plane *plane = plane_state->plane;
12302         struct drm_device *dev = crtc->dev;
12303         struct drm_i915_private *dev_priv = to_i915(dev);
12304         struct intel_plane_state *old_plane_state =
12305                 to_intel_plane_state(plane->state);
12306         bool mode_changed = needs_modeset(crtc_state);
12307         bool was_crtc_enabled = crtc->state->active;
12308         bool is_crtc_enabled = crtc_state->active;
12309         bool turn_off, turn_on, visible, was_visible;
12310         struct drm_framebuffer *fb = plane_state->fb;
12311         int ret;
12312
12313         if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12314                 ret = skl_update_scaler_plane(
12315                         to_intel_crtc_state(crtc_state),
12316                         to_intel_plane_state(plane_state));
12317                 if (ret)
12318                         return ret;
12319         }
12320
12321         was_visible = old_plane_state->base.visible;
12322         visible = to_intel_plane_state(plane_state)->base.visible;
12323
12324         if (!was_crtc_enabled && WARN_ON(was_visible))
12325                 was_visible = false;
12326
12327         /*
12328          * Visibility is calculated as if the crtc was on, but
12329          * after scaler setup everything depends on it being off
12330          * when the crtc isn't active.
12331          *
12332          * FIXME this is wrong for watermarks. Watermarks should also
12333          * be computed as if the pipe would be active. Perhaps move
12334          * per-plane wm computation to the .check_plane() hook, and
12335          * only combine the results from all planes in the current place?
12336          */
12337         if (!is_crtc_enabled)
12338                 to_intel_plane_state(plane_state)->base.visible = visible = false;
12339
12340         if (!was_visible && !visible)
12341                 return 0;
12342
12343         if (fb != old_plane_state->base.fb)
12344                 pipe_config->fb_changed = true;
12345
12346         turn_off = was_visible && (!visible || mode_changed);
12347         turn_on = visible && (!was_visible || mode_changed);
12348
12349         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12350                          intel_crtc->base.base.id,
12351                          intel_crtc->base.name,
12352                          plane->base.id, plane->name,
12353                          fb ? fb->base.id : -1);
12354
12355         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12356                          plane->base.id, plane->name,
12357                          was_visible, visible,
12358                          turn_off, turn_on, mode_changed);
12359
12360         if (turn_on) {
12361                 pipe_config->update_wm_pre = true;
12362
12363                 /* must disable cxsr around plane enable/disable */
12364                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12365                         pipe_config->disable_cxsr = true;
12366         } else if (turn_off) {
12367                 pipe_config->update_wm_post = true;
12368
12369                 /* must disable cxsr around plane enable/disable */
12370                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12371                         pipe_config->disable_cxsr = true;
12372         } else if (intel_wm_need_update(plane, plane_state)) {
12373                 /* FIXME bollocks */
12374                 pipe_config->update_wm_pre = true;
12375                 pipe_config->update_wm_post = true;
12376         }
12377
12378         /* Pre-gen9 platforms need two-step watermark updates */
12379         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12380             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12381                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12382
12383         if (visible || was_visible)
12384                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12385
12386         /*
12387          * WaCxSRDisabledForSpriteScaling:ivb
12388          *
12389          * cstate->update_wm was already set above, so this flag will
12390          * take effect when we commit and program watermarks.
12391          */
12392         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12393             needs_scaling(to_intel_plane_state(plane_state)) &&
12394             !needs_scaling(old_plane_state))
12395                 pipe_config->disable_lp_wm = true;
12396
12397         return 0;
12398 }
12399
12400 static bool encoders_cloneable(const struct intel_encoder *a,
12401                                const struct intel_encoder *b)
12402 {
12403         /* masks could be asymmetric, so check both ways */
12404         return a == b || (a->cloneable & (1 << b->type) &&
12405                           b->cloneable & (1 << a->type));
12406 }
12407
12408 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12409                                          struct intel_crtc *crtc,
12410                                          struct intel_encoder *encoder)
12411 {
12412         struct intel_encoder *source_encoder;
12413         struct drm_connector *connector;
12414         struct drm_connector_state *connector_state;
12415         int i;
12416
12417         for_each_connector_in_state(state, connector, connector_state, i) {
12418                 if (connector_state->crtc != &crtc->base)
12419                         continue;
12420
12421                 source_encoder =
12422                         to_intel_encoder(connector_state->best_encoder);
12423                 if (!encoders_cloneable(encoder, source_encoder))
12424                         return false;
12425         }
12426
12427         return true;
12428 }
12429
12430 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12431                                    struct drm_crtc_state *crtc_state)
12432 {
12433         struct drm_device *dev = crtc->dev;
12434         struct drm_i915_private *dev_priv = to_i915(dev);
12435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12436         struct intel_crtc_state *pipe_config =
12437                 to_intel_crtc_state(crtc_state);
12438         struct drm_atomic_state *state = crtc_state->state;
12439         int ret;
12440         bool mode_changed = needs_modeset(crtc_state);
12441
12442         if (mode_changed && !crtc_state->active)
12443                 pipe_config->update_wm_post = true;
12444
12445         if (mode_changed && crtc_state->enable &&
12446             dev_priv->display.crtc_compute_clock &&
12447             !WARN_ON(pipe_config->shared_dpll)) {
12448                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12449                                                            pipe_config);
12450                 if (ret)
12451                         return ret;
12452         }
12453
12454         if (crtc_state->color_mgmt_changed) {
12455                 ret = intel_color_check(crtc, crtc_state);
12456                 if (ret)
12457                         return ret;
12458
12459                 /*
12460                  * Changing color management on Intel hardware is
12461                  * handled as part of planes update.
12462                  */
12463                 crtc_state->planes_changed = true;
12464         }
12465
12466         ret = 0;
12467         if (dev_priv->display.compute_pipe_wm) {
12468                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12469                 if (ret) {
12470                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12471                         return ret;
12472                 }
12473         }
12474
12475         if (dev_priv->display.compute_intermediate_wm &&
12476             !to_intel_atomic_state(state)->skip_intermediate_wm) {
12477                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12478                         return 0;
12479
12480                 /*
12481                  * Calculate 'intermediate' watermarks that satisfy both the
12482                  * old state and the new state.  We can program these
12483                  * immediately.
12484                  */
12485                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12486                                                                 intel_crtc,
12487                                                                 pipe_config);
12488                 if (ret) {
12489                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12490                         return ret;
12491                 }
12492         } else if (dev_priv->display.compute_intermediate_wm) {
12493                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12494                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12495         }
12496
12497         if (INTEL_INFO(dev)->gen >= 9) {
12498                 if (mode_changed)
12499                         ret = skl_update_scaler_crtc(pipe_config);
12500
12501                 if (!ret)
12502                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12503                                                          pipe_config);
12504         }
12505
12506         return ret;
12507 }
12508
12509 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12510         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12511         .atomic_begin = intel_begin_crtc_commit,
12512         .atomic_flush = intel_finish_crtc_commit,
12513         .atomic_check = intel_crtc_atomic_check,
12514 };
12515
12516 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12517 {
12518         struct intel_connector *connector;
12519
12520         for_each_intel_connector(dev, connector) {
12521                 if (connector->base.state->crtc)
12522                         drm_connector_unreference(&connector->base);
12523
12524                 if (connector->base.encoder) {
12525                         connector->base.state->best_encoder =
12526                                 connector->base.encoder;
12527                         connector->base.state->crtc =
12528                                 connector->base.encoder->crtc;
12529
12530                         drm_connector_reference(&connector->base);
12531                 } else {
12532                         connector->base.state->best_encoder = NULL;
12533                         connector->base.state->crtc = NULL;
12534                 }
12535         }
12536 }
12537
12538 static void
12539 connected_sink_compute_bpp(struct intel_connector *connector,
12540                            struct intel_crtc_state *pipe_config)
12541 {
12542         int bpp = pipe_config->pipe_bpp;
12543
12544         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12545                 connector->base.base.id,
12546                 connector->base.name);
12547
12548         /* Don't use an invalid EDID bpc value */
12549         if (connector->base.display_info.bpc &&
12550             connector->base.display_info.bpc * 3 < bpp) {
12551                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12552                               bpp, connector->base.display_info.bpc*3);
12553                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12554         }
12555
12556         /* Clamp bpp to 8 on screens without EDID 1.4 */
12557         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12558                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12559                               bpp);
12560                 pipe_config->pipe_bpp = 24;
12561         }
12562 }
12563
12564 static int
12565 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12566                           struct intel_crtc_state *pipe_config)
12567 {
12568         struct drm_device *dev = crtc->base.dev;
12569         struct drm_atomic_state *state;
12570         struct drm_connector *connector;
12571         struct drm_connector_state *connector_state;
12572         int bpp, i;
12573
12574         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12575                 bpp = 10*3;
12576         else if (INTEL_INFO(dev)->gen >= 5)
12577                 bpp = 12*3;
12578         else
12579                 bpp = 8*3;
12580
12581
12582         pipe_config->pipe_bpp = bpp;
12583
12584         state = pipe_config->base.state;
12585
12586         /* Clamp display bpp to EDID value */
12587         for_each_connector_in_state(state, connector, connector_state, i) {
12588                 if (connector_state->crtc != &crtc->base)
12589                         continue;
12590
12591                 connected_sink_compute_bpp(to_intel_connector(connector),
12592                                            pipe_config);
12593         }
12594
12595         return bpp;
12596 }
12597
12598 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12599 {
12600         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12601                         "type: 0x%x flags: 0x%x\n",
12602                 mode->crtc_clock,
12603                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12604                 mode->crtc_hsync_end, mode->crtc_htotal,
12605                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12606                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12607 }
12608
12609 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12610                                    struct intel_crtc_state *pipe_config,
12611                                    const char *context)
12612 {
12613         struct drm_device *dev = crtc->base.dev;
12614         struct drm_plane *plane;
12615         struct intel_plane *intel_plane;
12616         struct intel_plane_state *state;
12617         struct drm_framebuffer *fb;
12618
12619         DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12620                       crtc->base.base.id, crtc->base.name,
12621                       context, pipe_config, pipe_name(crtc->pipe));
12622
12623         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12624         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12625                       pipe_config->pipe_bpp, pipe_config->dither);
12626         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12627                       pipe_config->has_pch_encoder,
12628                       pipe_config->fdi_lanes,
12629                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12630                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12631                       pipe_config->fdi_m_n.tu);
12632         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12633                       intel_crtc_has_dp_encoder(pipe_config),
12634                       pipe_config->lane_count,
12635                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12636                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12637                       pipe_config->dp_m_n.tu);
12638
12639         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12640                       intel_crtc_has_dp_encoder(pipe_config),
12641                       pipe_config->lane_count,
12642                       pipe_config->dp_m2_n2.gmch_m,
12643                       pipe_config->dp_m2_n2.gmch_n,
12644                       pipe_config->dp_m2_n2.link_m,
12645                       pipe_config->dp_m2_n2.link_n,
12646                       pipe_config->dp_m2_n2.tu);
12647
12648         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12649                       pipe_config->has_audio,
12650                       pipe_config->has_infoframe);
12651
12652         DRM_DEBUG_KMS("requested mode:\n");
12653         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12654         DRM_DEBUG_KMS("adjusted mode:\n");
12655         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12656         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12657         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12658         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12659                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12660         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12661                       crtc->num_scalers,
12662                       pipe_config->scaler_state.scaler_users,
12663                       pipe_config->scaler_state.scaler_id);
12664         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12665                       pipe_config->gmch_pfit.control,
12666                       pipe_config->gmch_pfit.pgm_ratios,
12667                       pipe_config->gmch_pfit.lvds_border_bits);
12668         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12669                       pipe_config->pch_pfit.pos,
12670                       pipe_config->pch_pfit.size,
12671                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12672         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12673         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12674
12675         if (IS_BROXTON(dev)) {
12676                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12677                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12678                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12679                               pipe_config->ddi_pll_sel,
12680                               pipe_config->dpll_hw_state.ebb0,
12681                               pipe_config->dpll_hw_state.ebb4,
12682                               pipe_config->dpll_hw_state.pll0,
12683                               pipe_config->dpll_hw_state.pll1,
12684                               pipe_config->dpll_hw_state.pll2,
12685                               pipe_config->dpll_hw_state.pll3,
12686                               pipe_config->dpll_hw_state.pll6,
12687                               pipe_config->dpll_hw_state.pll8,
12688                               pipe_config->dpll_hw_state.pll9,
12689                               pipe_config->dpll_hw_state.pll10,
12690                               pipe_config->dpll_hw_state.pcsdw12);
12691         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12692                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12693                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12694                               pipe_config->ddi_pll_sel,
12695                               pipe_config->dpll_hw_state.ctrl1,
12696                               pipe_config->dpll_hw_state.cfgcr1,
12697                               pipe_config->dpll_hw_state.cfgcr2);
12698         } else if (HAS_DDI(dev)) {
12699                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12700                               pipe_config->ddi_pll_sel,
12701                               pipe_config->dpll_hw_state.wrpll,
12702                               pipe_config->dpll_hw_state.spll);
12703         } else {
12704                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12705                               "fp0: 0x%x, fp1: 0x%x\n",
12706                               pipe_config->dpll_hw_state.dpll,
12707                               pipe_config->dpll_hw_state.dpll_md,
12708                               pipe_config->dpll_hw_state.fp0,
12709                               pipe_config->dpll_hw_state.fp1);
12710         }
12711
12712         DRM_DEBUG_KMS("planes on this crtc\n");
12713         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12714                 intel_plane = to_intel_plane(plane);
12715                 if (intel_plane->pipe != crtc->pipe)
12716                         continue;
12717
12718                 state = to_intel_plane_state(plane->state);
12719                 fb = state->base.fb;
12720                 if (!fb) {
12721                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12722                                       plane->base.id, plane->name, state->scaler_id);
12723                         continue;
12724                 }
12725
12726                 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12727                               plane->base.id, plane->name);
12728                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12729                               fb->base.id, fb->width, fb->height,
12730                               drm_get_format_name(fb->pixel_format));
12731                 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12732                               state->scaler_id,
12733                               state->base.src.x1 >> 16,
12734                               state->base.src.y1 >> 16,
12735                               drm_rect_width(&state->base.src) >> 16,
12736                               drm_rect_height(&state->base.src) >> 16,
12737                               state->base.dst.x1, state->base.dst.y1,
12738                               drm_rect_width(&state->base.dst),
12739                               drm_rect_height(&state->base.dst));
12740         }
12741 }
12742
12743 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12744 {
12745         struct drm_device *dev = state->dev;
12746         struct drm_connector *connector;
12747         unsigned int used_ports = 0;
12748         unsigned int used_mst_ports = 0;
12749
12750         /*
12751          * Walk the connector list instead of the encoder
12752          * list to detect the problem on ddi platforms
12753          * where there's just one encoder per digital port.
12754          */
12755         drm_for_each_connector(connector, dev) {
12756                 struct drm_connector_state *connector_state;
12757                 struct intel_encoder *encoder;
12758
12759                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12760                 if (!connector_state)
12761                         connector_state = connector->state;
12762
12763                 if (!connector_state->best_encoder)
12764                         continue;
12765
12766                 encoder = to_intel_encoder(connector_state->best_encoder);
12767
12768                 WARN_ON(!connector_state->crtc);
12769
12770                 switch (encoder->type) {
12771                         unsigned int port_mask;
12772                 case INTEL_OUTPUT_UNKNOWN:
12773                         if (WARN_ON(!HAS_DDI(dev)))
12774                                 break;
12775                 case INTEL_OUTPUT_DP:
12776                 case INTEL_OUTPUT_HDMI:
12777                 case INTEL_OUTPUT_EDP:
12778                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12779
12780                         /* the same port mustn't appear more than once */
12781                         if (used_ports & port_mask)
12782                                 return false;
12783
12784                         used_ports |= port_mask;
12785                         break;
12786                 case INTEL_OUTPUT_DP_MST:
12787                         used_mst_ports |=
12788                                 1 << enc_to_mst(&encoder->base)->primary->port;
12789                         break;
12790                 default:
12791                         break;
12792                 }
12793         }
12794
12795         /* can't mix MST and SST/HDMI on the same port */
12796         if (used_ports & used_mst_ports)
12797                 return false;
12798
12799         return true;
12800 }
12801
12802 static void
12803 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12804 {
12805         struct drm_crtc_state tmp_state;
12806         struct intel_crtc_scaler_state scaler_state;
12807         struct intel_dpll_hw_state dpll_hw_state;
12808         struct intel_shared_dpll *shared_dpll;
12809         uint32_t ddi_pll_sel;
12810         bool force_thru;
12811
12812         /* FIXME: before the switch to atomic started, a new pipe_config was
12813          * kzalloc'd. Code that depends on any field being zero should be
12814          * fixed, so that the crtc_state can be safely duplicated. For now,
12815          * only fields that are know to not cause problems are preserved. */
12816
12817         tmp_state = crtc_state->base;
12818         scaler_state = crtc_state->scaler_state;
12819         shared_dpll = crtc_state->shared_dpll;
12820         dpll_hw_state = crtc_state->dpll_hw_state;
12821         ddi_pll_sel = crtc_state->ddi_pll_sel;
12822         force_thru = crtc_state->pch_pfit.force_thru;
12823
12824         memset(crtc_state, 0, sizeof *crtc_state);
12825
12826         crtc_state->base = tmp_state;
12827         crtc_state->scaler_state = scaler_state;
12828         crtc_state->shared_dpll = shared_dpll;
12829         crtc_state->dpll_hw_state = dpll_hw_state;
12830         crtc_state->ddi_pll_sel = ddi_pll_sel;
12831         crtc_state->pch_pfit.force_thru = force_thru;
12832 }
12833
12834 static int
12835 intel_modeset_pipe_config(struct drm_crtc *crtc,
12836                           struct intel_crtc_state *pipe_config)
12837 {
12838         struct drm_atomic_state *state = pipe_config->base.state;
12839         struct intel_encoder *encoder;
12840         struct drm_connector *connector;
12841         struct drm_connector_state *connector_state;
12842         int base_bpp, ret = -EINVAL;
12843         int i;
12844         bool retry = true;
12845
12846         clear_intel_crtc_state(pipe_config);
12847
12848         pipe_config->cpu_transcoder =
12849                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12850
12851         /*
12852          * Sanitize sync polarity flags based on requested ones. If neither
12853          * positive or negative polarity is requested, treat this as meaning
12854          * negative polarity.
12855          */
12856         if (!(pipe_config->base.adjusted_mode.flags &
12857               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12858                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12859
12860         if (!(pipe_config->base.adjusted_mode.flags &
12861               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12862                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12863
12864         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12865                                              pipe_config);
12866         if (base_bpp < 0)
12867                 goto fail;
12868
12869         /*
12870          * Determine the real pipe dimensions. Note that stereo modes can
12871          * increase the actual pipe size due to the frame doubling and
12872          * insertion of additional space for blanks between the frame. This
12873          * is stored in the crtc timings. We use the requested mode to do this
12874          * computation to clearly distinguish it from the adjusted mode, which
12875          * can be changed by the connectors in the below retry loop.
12876          */
12877         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12878                                &pipe_config->pipe_src_w,
12879                                &pipe_config->pipe_src_h);
12880
12881         for_each_connector_in_state(state, connector, connector_state, i) {
12882                 if (connector_state->crtc != crtc)
12883                         continue;
12884
12885                 encoder = to_intel_encoder(connector_state->best_encoder);
12886
12887                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12888                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12889                         goto fail;
12890                 }
12891
12892                 /*
12893                  * Determine output_types before calling the .compute_config()
12894                  * hooks so that the hooks can use this information safely.
12895                  */
12896                 pipe_config->output_types |= 1 << encoder->type;
12897         }
12898
12899 encoder_retry:
12900         /* Ensure the port clock defaults are reset when retrying. */
12901         pipe_config->port_clock = 0;
12902         pipe_config->pixel_multiplier = 1;
12903
12904         /* Fill in default crtc timings, allow encoders to overwrite them. */
12905         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12906                               CRTC_STEREO_DOUBLE);
12907
12908         /* Pass our mode to the connectors and the CRTC to give them a chance to
12909          * adjust it according to limitations or connector properties, and also
12910          * a chance to reject the mode entirely.
12911          */
12912         for_each_connector_in_state(state, connector, connector_state, i) {
12913                 if (connector_state->crtc != crtc)
12914                         continue;
12915
12916                 encoder = to_intel_encoder(connector_state->best_encoder);
12917
12918                 if (!(encoder->compute_config(encoder, pipe_config))) {
12919                         DRM_DEBUG_KMS("Encoder config failure\n");
12920                         goto fail;
12921                 }
12922         }
12923
12924         /* Set default port clock if not overwritten by the encoder. Needs to be
12925          * done afterwards in case the encoder adjusts the mode. */
12926         if (!pipe_config->port_clock)
12927                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12928                         * pipe_config->pixel_multiplier;
12929
12930         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12931         if (ret < 0) {
12932                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12933                 goto fail;
12934         }
12935
12936         if (ret == RETRY) {
12937                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12938                         ret = -EINVAL;
12939                         goto fail;
12940                 }
12941
12942                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12943                 retry = false;
12944                 goto encoder_retry;
12945         }
12946
12947         /* Dithering seems to not pass-through bits correctly when it should, so
12948          * only enable it on 6bpc panels. */
12949         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12950         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12951                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12952
12953 fail:
12954         return ret;
12955 }
12956
12957 static void
12958 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12959 {
12960         struct drm_crtc *crtc;
12961         struct drm_crtc_state *crtc_state;
12962         int i;
12963
12964         /* Double check state. */
12965         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12966                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12967
12968                 /* Update hwmode for vblank functions */
12969                 if (crtc->state->active)
12970                         crtc->hwmode = crtc->state->adjusted_mode;
12971                 else
12972                         crtc->hwmode.crtc_clock = 0;
12973
12974                 /*
12975                  * Update legacy state to satisfy fbc code. This can
12976                  * be removed when fbc uses the atomic state.
12977                  */
12978                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12979                         struct drm_plane_state *plane_state = crtc->primary->state;
12980
12981                         crtc->primary->fb = plane_state->fb;
12982                         crtc->x = plane_state->src_x >> 16;
12983                         crtc->y = plane_state->src_y >> 16;
12984                 }
12985         }
12986 }
12987
12988 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12989 {
12990         int diff;
12991
12992         if (clock1 == clock2)
12993                 return true;
12994
12995         if (!clock1 || !clock2)
12996                 return false;
12997
12998         diff = abs(clock1 - clock2);
12999
13000         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13001                 return true;
13002
13003         return false;
13004 }
13005
13006 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
13007         list_for_each_entry((intel_crtc), \
13008                             &(dev)->mode_config.crtc_list, \
13009                             base.head) \
13010                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
13011
13012 static bool
13013 intel_compare_m_n(unsigned int m, unsigned int n,
13014                   unsigned int m2, unsigned int n2,
13015                   bool exact)
13016 {
13017         if (m == m2 && n == n2)
13018                 return true;
13019
13020         if (exact || !m || !n || !m2 || !n2)
13021                 return false;
13022
13023         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13024
13025         if (n > n2) {
13026                 while (n > n2) {
13027                         m2 <<= 1;
13028                         n2 <<= 1;
13029                 }
13030         } else if (n < n2) {
13031                 while (n < n2) {
13032                         m <<= 1;
13033                         n <<= 1;
13034                 }
13035         }
13036
13037         if (n != n2)
13038                 return false;
13039
13040         return intel_fuzzy_clock_check(m, m2);
13041 }
13042
13043 static bool
13044 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13045                        struct intel_link_m_n *m2_n2,
13046                        bool adjust)
13047 {
13048         if (m_n->tu == m2_n2->tu &&
13049             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13050                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13051             intel_compare_m_n(m_n->link_m, m_n->link_n,
13052                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
13053                 if (adjust)
13054                         *m2_n2 = *m_n;
13055
13056                 return true;
13057         }
13058
13059         return false;
13060 }
13061
13062 static bool
13063 intel_pipe_config_compare(struct drm_device *dev,
13064                           struct intel_crtc_state *current_config,
13065                           struct intel_crtc_state *pipe_config,
13066                           bool adjust)
13067 {
13068         bool ret = true;
13069
13070 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13071         do { \
13072                 if (!adjust) \
13073                         DRM_ERROR(fmt, ##__VA_ARGS__); \
13074                 else \
13075                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13076         } while (0)
13077
13078 #define PIPE_CONF_CHECK_X(name) \
13079         if (current_config->name != pipe_config->name) { \
13080                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13081                           "(expected 0x%08x, found 0x%08x)\n", \
13082                           current_config->name, \
13083                           pipe_config->name); \
13084                 ret = false; \
13085         }
13086
13087 #define PIPE_CONF_CHECK_I(name) \
13088         if (current_config->name != pipe_config->name) { \
13089                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13090                           "(expected %i, found %i)\n", \
13091                           current_config->name, \
13092                           pipe_config->name); \
13093                 ret = false; \
13094         }
13095
13096 #define PIPE_CONF_CHECK_P(name) \
13097         if (current_config->name != pipe_config->name) { \
13098                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13099                           "(expected %p, found %p)\n", \
13100                           current_config->name, \
13101                           pipe_config->name); \
13102                 ret = false; \
13103         }
13104
13105 #define PIPE_CONF_CHECK_M_N(name) \
13106         if (!intel_compare_link_m_n(&current_config->name, \
13107                                     &pipe_config->name,\
13108                                     adjust)) { \
13109                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13110                           "(expected tu %i gmch %i/%i link %i/%i, " \
13111                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13112                           current_config->name.tu, \
13113                           current_config->name.gmch_m, \
13114                           current_config->name.gmch_n, \
13115                           current_config->name.link_m, \
13116                           current_config->name.link_n, \
13117                           pipe_config->name.tu, \
13118                           pipe_config->name.gmch_m, \
13119                           pipe_config->name.gmch_n, \
13120                           pipe_config->name.link_m, \
13121                           pipe_config->name.link_n); \
13122                 ret = false; \
13123         }
13124
13125 /* This is required for BDW+ where there is only one set of registers for
13126  * switching between high and low RR.
13127  * This macro can be used whenever a comparison has to be made between one
13128  * hw state and multiple sw state variables.
13129  */
13130 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13131         if (!intel_compare_link_m_n(&current_config->name, \
13132                                     &pipe_config->name, adjust) && \
13133             !intel_compare_link_m_n(&current_config->alt_name, \
13134                                     &pipe_config->name, adjust)) { \
13135                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13136                           "(expected tu %i gmch %i/%i link %i/%i, " \
13137                           "or tu %i gmch %i/%i link %i/%i, " \
13138                           "found tu %i, gmch %i/%i link %i/%i)\n", \
13139                           current_config->name.tu, \
13140                           current_config->name.gmch_m, \
13141                           current_config->name.gmch_n, \
13142                           current_config->name.link_m, \
13143                           current_config->name.link_n, \
13144                           current_config->alt_name.tu, \
13145                           current_config->alt_name.gmch_m, \
13146                           current_config->alt_name.gmch_n, \
13147                           current_config->alt_name.link_m, \
13148                           current_config->alt_name.link_n, \
13149                           pipe_config->name.tu, \
13150                           pipe_config->name.gmch_m, \
13151                           pipe_config->name.gmch_n, \
13152                           pipe_config->name.link_m, \
13153                           pipe_config->name.link_n); \
13154                 ret = false; \
13155         }
13156
13157 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
13158         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13159                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13160                           "(expected %i, found %i)\n", \
13161                           current_config->name & (mask), \
13162                           pipe_config->name & (mask)); \
13163                 ret = false; \
13164         }
13165
13166 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13167         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13168                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13169                           "(expected %i, found %i)\n", \
13170                           current_config->name, \
13171                           pipe_config->name); \
13172                 ret = false; \
13173         }
13174
13175 #define PIPE_CONF_QUIRK(quirk)  \
13176         ((current_config->quirks | pipe_config->quirks) & (quirk))
13177
13178         PIPE_CONF_CHECK_I(cpu_transcoder);
13179
13180         PIPE_CONF_CHECK_I(has_pch_encoder);
13181         PIPE_CONF_CHECK_I(fdi_lanes);
13182         PIPE_CONF_CHECK_M_N(fdi_m_n);
13183
13184         PIPE_CONF_CHECK_I(lane_count);
13185         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13186
13187         if (INTEL_INFO(dev)->gen < 8) {
13188                 PIPE_CONF_CHECK_M_N(dp_m_n);
13189
13190                 if (current_config->has_drrs)
13191                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13192         } else
13193                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13194
13195         PIPE_CONF_CHECK_X(output_types);
13196
13197         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13198         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13199         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13200         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13201         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13202         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13203
13204         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13205         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13206         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13207         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13208         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13209         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13210
13211         PIPE_CONF_CHECK_I(pixel_multiplier);
13212         PIPE_CONF_CHECK_I(has_hdmi_sink);
13213         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13214             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13215                 PIPE_CONF_CHECK_I(limited_color_range);
13216         PIPE_CONF_CHECK_I(has_infoframe);
13217
13218         PIPE_CONF_CHECK_I(has_audio);
13219
13220         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13221                               DRM_MODE_FLAG_INTERLACE);
13222
13223         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13224                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13225                                       DRM_MODE_FLAG_PHSYNC);
13226                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13227                                       DRM_MODE_FLAG_NHSYNC);
13228                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13229                                       DRM_MODE_FLAG_PVSYNC);
13230                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13231                                       DRM_MODE_FLAG_NVSYNC);
13232         }
13233
13234         PIPE_CONF_CHECK_X(gmch_pfit.control);
13235         /* pfit ratios are autocomputed by the hw on gen4+ */
13236         if (INTEL_INFO(dev)->gen < 4)
13237                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13238         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13239
13240         if (!adjust) {
13241                 PIPE_CONF_CHECK_I(pipe_src_w);
13242                 PIPE_CONF_CHECK_I(pipe_src_h);
13243
13244                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13245                 if (current_config->pch_pfit.enabled) {
13246                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13247                         PIPE_CONF_CHECK_X(pch_pfit.size);
13248                 }
13249
13250                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13251         }
13252
13253         /* BDW+ don't expose a synchronous way to read the state */
13254         if (IS_HASWELL(dev))
13255                 PIPE_CONF_CHECK_I(ips_enabled);
13256
13257         PIPE_CONF_CHECK_I(double_wide);
13258
13259         PIPE_CONF_CHECK_X(ddi_pll_sel);
13260
13261         PIPE_CONF_CHECK_P(shared_dpll);
13262         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13263         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13264         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13265         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13266         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13267         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13268         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13269         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13270         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13271
13272         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13273         PIPE_CONF_CHECK_X(dsi_pll.div);
13274
13275         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13276                 PIPE_CONF_CHECK_I(pipe_bpp);
13277
13278         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13279         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13280
13281 #undef PIPE_CONF_CHECK_X
13282 #undef PIPE_CONF_CHECK_I
13283 #undef PIPE_CONF_CHECK_P
13284 #undef PIPE_CONF_CHECK_FLAGS
13285 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13286 #undef PIPE_CONF_QUIRK
13287 #undef INTEL_ERR_OR_DBG_KMS
13288
13289         return ret;
13290 }
13291
13292 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13293                                            const struct intel_crtc_state *pipe_config)
13294 {
13295         if (pipe_config->has_pch_encoder) {
13296                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13297                                                             &pipe_config->fdi_m_n);
13298                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13299
13300                 /*
13301                  * FDI already provided one idea for the dotclock.
13302                  * Yell if the encoder disagrees.
13303                  */
13304                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13305                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13306                      fdi_dotclock, dotclock);
13307         }
13308 }
13309
13310 static void verify_wm_state(struct drm_crtc *crtc,
13311                             struct drm_crtc_state *new_state)
13312 {
13313         struct drm_device *dev = crtc->dev;
13314         struct drm_i915_private *dev_priv = to_i915(dev);
13315         struct skl_ddb_allocation hw_ddb, *sw_ddb;
13316         struct skl_ddb_entry *hw_entry, *sw_entry;
13317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13318         const enum pipe pipe = intel_crtc->pipe;
13319         int plane;
13320
13321         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13322                 return;
13323
13324         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13325         sw_ddb = &dev_priv->wm.skl_hw.ddb;
13326
13327         /* planes */
13328         for_each_plane(dev_priv, pipe, plane) {
13329                 hw_entry = &hw_ddb.plane[pipe][plane];
13330                 sw_entry = &sw_ddb->plane[pipe][plane];
13331
13332                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13333                         continue;
13334
13335                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13336                           "(expected (%u,%u), found (%u,%u))\n",
13337                           pipe_name(pipe), plane + 1,
13338                           sw_entry->start, sw_entry->end,
13339                           hw_entry->start, hw_entry->end);
13340         }
13341
13342         /* cursor */
13343         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13344         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13345
13346         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13347                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13348                           "(expected (%u,%u), found (%u,%u))\n",
13349                           pipe_name(pipe),
13350                           sw_entry->start, sw_entry->end,
13351                           hw_entry->start, hw_entry->end);
13352         }
13353 }
13354
13355 static void
13356 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13357 {
13358         struct drm_connector *connector;
13359
13360         drm_for_each_connector(connector, dev) {
13361                 struct drm_encoder *encoder = connector->encoder;
13362                 struct drm_connector_state *state = connector->state;
13363
13364                 if (state->crtc != crtc)
13365                         continue;
13366
13367                 intel_connector_verify_state(to_intel_connector(connector));
13368
13369                 I915_STATE_WARN(state->best_encoder != encoder,
13370                      "connector's atomic encoder doesn't match legacy encoder\n");
13371         }
13372 }
13373
13374 static void
13375 verify_encoder_state(struct drm_device *dev)
13376 {
13377         struct intel_encoder *encoder;
13378         struct intel_connector *connector;
13379
13380         for_each_intel_encoder(dev, encoder) {
13381                 bool enabled = false;
13382                 enum pipe pipe;
13383
13384                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13385                               encoder->base.base.id,
13386                               encoder->base.name);
13387
13388                 for_each_intel_connector(dev, connector) {
13389                         if (connector->base.state->best_encoder != &encoder->base)
13390                                 continue;
13391                         enabled = true;
13392
13393                         I915_STATE_WARN(connector->base.state->crtc !=
13394                                         encoder->base.crtc,
13395                              "connector's crtc doesn't match encoder crtc\n");
13396                 }
13397
13398                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13399                      "encoder's enabled state mismatch "
13400                      "(expected %i, found %i)\n",
13401                      !!encoder->base.crtc, enabled);
13402
13403                 if (!encoder->base.crtc) {
13404                         bool active;
13405
13406                         active = encoder->get_hw_state(encoder, &pipe);
13407                         I915_STATE_WARN(active,
13408                              "encoder detached but still enabled on pipe %c.\n",
13409                              pipe_name(pipe));
13410                 }
13411         }
13412 }
13413
13414 static void
13415 verify_crtc_state(struct drm_crtc *crtc,
13416                   struct drm_crtc_state *old_crtc_state,
13417                   struct drm_crtc_state *new_crtc_state)
13418 {
13419         struct drm_device *dev = crtc->dev;
13420         struct drm_i915_private *dev_priv = to_i915(dev);
13421         struct intel_encoder *encoder;
13422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13423         struct intel_crtc_state *pipe_config, *sw_config;
13424         struct drm_atomic_state *old_state;
13425         bool active;
13426
13427         old_state = old_crtc_state->state;
13428         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13429         pipe_config = to_intel_crtc_state(old_crtc_state);
13430         memset(pipe_config, 0, sizeof(*pipe_config));
13431         pipe_config->base.crtc = crtc;
13432         pipe_config->base.state = old_state;
13433
13434         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13435
13436         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13437
13438         /* hw state is inconsistent with the pipe quirk */
13439         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13440             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13441                 active = new_crtc_state->active;
13442
13443         I915_STATE_WARN(new_crtc_state->active != active,
13444              "crtc active state doesn't match with hw state "
13445              "(expected %i, found %i)\n", new_crtc_state->active, active);
13446
13447         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13448              "transitional active state does not match atomic hw state "
13449              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13450
13451         for_each_encoder_on_crtc(dev, crtc, encoder) {
13452                 enum pipe pipe;
13453
13454                 active = encoder->get_hw_state(encoder, &pipe);
13455                 I915_STATE_WARN(active != new_crtc_state->active,
13456                         "[ENCODER:%i] active %i with crtc active %i\n",
13457                         encoder->base.base.id, active, new_crtc_state->active);
13458
13459                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13460                                 "Encoder connected to wrong pipe %c\n",
13461                                 pipe_name(pipe));
13462
13463                 if (active) {
13464                         pipe_config->output_types |= 1 << encoder->type;
13465                         encoder->get_config(encoder, pipe_config);
13466                 }
13467         }
13468
13469         if (!new_crtc_state->active)
13470                 return;
13471
13472         intel_pipe_config_sanity_check(dev_priv, pipe_config);
13473
13474         sw_config = to_intel_crtc_state(crtc->state);
13475         if (!intel_pipe_config_compare(dev, sw_config,
13476                                        pipe_config, false)) {
13477                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13478                 intel_dump_pipe_config(intel_crtc, pipe_config,
13479                                        "[hw state]");
13480                 intel_dump_pipe_config(intel_crtc, sw_config,
13481                                        "[sw state]");
13482         }
13483 }
13484
13485 static void
13486 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13487                          struct intel_shared_dpll *pll,
13488                          struct drm_crtc *crtc,
13489                          struct drm_crtc_state *new_state)
13490 {
13491         struct intel_dpll_hw_state dpll_hw_state;
13492         unsigned crtc_mask;
13493         bool active;
13494
13495         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13496
13497         DRM_DEBUG_KMS("%s\n", pll->name);
13498
13499         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13500
13501         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13502                 I915_STATE_WARN(!pll->on && pll->active_mask,
13503                      "pll in active use but not on in sw tracking\n");
13504                 I915_STATE_WARN(pll->on && !pll->active_mask,
13505                      "pll is on but not used by any active crtc\n");
13506                 I915_STATE_WARN(pll->on != active,
13507                      "pll on state mismatch (expected %i, found %i)\n",
13508                      pll->on, active);
13509         }
13510
13511         if (!crtc) {
13512                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13513                                 "more active pll users than references: %x vs %x\n",
13514                                 pll->active_mask, pll->config.crtc_mask);
13515
13516                 return;
13517         }
13518
13519         crtc_mask = 1 << drm_crtc_index(crtc);
13520
13521         if (new_state->active)
13522                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13523                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13524                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13525         else
13526                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13527                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13528                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13529
13530         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13531                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13532                         crtc_mask, pll->config.crtc_mask);
13533
13534         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13535                                           &dpll_hw_state,
13536                                           sizeof(dpll_hw_state)),
13537                         "pll hw state mismatch\n");
13538 }
13539
13540 static void
13541 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13542                          struct drm_crtc_state *old_crtc_state,
13543                          struct drm_crtc_state *new_crtc_state)
13544 {
13545         struct drm_i915_private *dev_priv = to_i915(dev);
13546         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13547         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13548
13549         if (new_state->shared_dpll)
13550                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13551
13552         if (old_state->shared_dpll &&
13553             old_state->shared_dpll != new_state->shared_dpll) {
13554                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13555                 struct intel_shared_dpll *pll = old_state->shared_dpll;
13556
13557                 I915_STATE_WARN(pll->active_mask & crtc_mask,
13558                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13559                                 pipe_name(drm_crtc_index(crtc)));
13560                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13561                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13562                                 pipe_name(drm_crtc_index(crtc)));
13563         }
13564 }
13565
13566 static void
13567 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13568                          struct drm_crtc_state *old_state,
13569                          struct drm_crtc_state *new_state)
13570 {
13571         if (!needs_modeset(new_state) &&
13572             !to_intel_crtc_state(new_state)->update_pipe)
13573                 return;
13574
13575         verify_wm_state(crtc, new_state);
13576         verify_connector_state(crtc->dev, crtc);
13577         verify_crtc_state(crtc, old_state, new_state);
13578         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13579 }
13580
13581 static void
13582 verify_disabled_dpll_state(struct drm_device *dev)
13583 {
13584         struct drm_i915_private *dev_priv = to_i915(dev);
13585         int i;
13586
13587         for (i = 0; i < dev_priv->num_shared_dpll; i++)
13588                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13589 }
13590
13591 static void
13592 intel_modeset_verify_disabled(struct drm_device *dev)
13593 {
13594         verify_encoder_state(dev);
13595         verify_connector_state(dev, NULL);
13596         verify_disabled_dpll_state(dev);
13597 }
13598
13599 static void update_scanline_offset(struct intel_crtc *crtc)
13600 {
13601         struct drm_device *dev = crtc->base.dev;
13602
13603         /*
13604          * The scanline counter increments at the leading edge of hsync.
13605          *
13606          * On most platforms it starts counting from vtotal-1 on the
13607          * first active line. That means the scanline counter value is
13608          * always one less than what we would expect. Ie. just after
13609          * start of vblank, which also occurs at start of hsync (on the
13610          * last active line), the scanline counter will read vblank_start-1.
13611          *
13612          * On gen2 the scanline counter starts counting from 1 instead
13613          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13614          * to keep the value positive), instead of adding one.
13615          *
13616          * On HSW+ the behaviour of the scanline counter depends on the output
13617          * type. For DP ports it behaves like most other platforms, but on HDMI
13618          * there's an extra 1 line difference. So we need to add two instead of
13619          * one to the value.
13620          */
13621         if (IS_GEN2(dev)) {
13622                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13623                 int vtotal;
13624
13625                 vtotal = adjusted_mode->crtc_vtotal;
13626                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13627                         vtotal /= 2;
13628
13629                 crtc->scanline_offset = vtotal - 1;
13630         } else if (HAS_DDI(dev) &&
13631                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13632                 crtc->scanline_offset = 2;
13633         } else
13634                 crtc->scanline_offset = 1;
13635 }
13636
13637 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13638 {
13639         struct drm_device *dev = state->dev;
13640         struct drm_i915_private *dev_priv = to_i915(dev);
13641         struct intel_shared_dpll_config *shared_dpll = NULL;
13642         struct drm_crtc *crtc;
13643         struct drm_crtc_state *crtc_state;
13644         int i;
13645
13646         if (!dev_priv->display.crtc_compute_clock)
13647                 return;
13648
13649         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13650                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13651                 struct intel_shared_dpll *old_dpll =
13652                         to_intel_crtc_state(crtc->state)->shared_dpll;
13653
13654                 if (!needs_modeset(crtc_state))
13655                         continue;
13656
13657                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13658
13659                 if (!old_dpll)
13660                         continue;
13661
13662                 if (!shared_dpll)
13663                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13664
13665                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13666         }
13667 }
13668
13669 /*
13670  * This implements the workaround described in the "notes" section of the mode
13671  * set sequence documentation. When going from no pipes or single pipe to
13672  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13673  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13674  */
13675 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13676 {
13677         struct drm_crtc_state *crtc_state;
13678         struct intel_crtc *intel_crtc;
13679         struct drm_crtc *crtc;
13680         struct intel_crtc_state *first_crtc_state = NULL;
13681         struct intel_crtc_state *other_crtc_state = NULL;
13682         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13683         int i;
13684
13685         /* look at all crtc's that are going to be enabled in during modeset */
13686         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13687                 intel_crtc = to_intel_crtc(crtc);
13688
13689                 if (!crtc_state->active || !needs_modeset(crtc_state))
13690                         continue;
13691
13692                 if (first_crtc_state) {
13693                         other_crtc_state = to_intel_crtc_state(crtc_state);
13694                         break;
13695                 } else {
13696                         first_crtc_state = to_intel_crtc_state(crtc_state);
13697                         first_pipe = intel_crtc->pipe;
13698                 }
13699         }
13700
13701         /* No workaround needed? */
13702         if (!first_crtc_state)
13703                 return 0;
13704
13705         /* w/a possibly needed, check how many crtc's are already enabled. */
13706         for_each_intel_crtc(state->dev, intel_crtc) {
13707                 struct intel_crtc_state *pipe_config;
13708
13709                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13710                 if (IS_ERR(pipe_config))
13711                         return PTR_ERR(pipe_config);
13712
13713                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13714
13715                 if (!pipe_config->base.active ||
13716                     needs_modeset(&pipe_config->base))
13717                         continue;
13718
13719                 /* 2 or more enabled crtcs means no need for w/a */
13720                 if (enabled_pipe != INVALID_PIPE)
13721                         return 0;
13722
13723                 enabled_pipe = intel_crtc->pipe;
13724         }
13725
13726         if (enabled_pipe != INVALID_PIPE)
13727                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13728         else if (other_crtc_state)
13729                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13730
13731         return 0;
13732 }
13733
13734 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13735 {
13736         struct drm_crtc *crtc;
13737         struct drm_crtc_state *crtc_state;
13738         int ret = 0;
13739
13740         /* add all active pipes to the state */
13741         for_each_crtc(state->dev, crtc) {
13742                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13743                 if (IS_ERR(crtc_state))
13744                         return PTR_ERR(crtc_state);
13745
13746                 if (!crtc_state->active || needs_modeset(crtc_state))
13747                         continue;
13748
13749                 crtc_state->mode_changed = true;
13750
13751                 ret = drm_atomic_add_affected_connectors(state, crtc);
13752                 if (ret)
13753                         break;
13754
13755                 ret = drm_atomic_add_affected_planes(state, crtc);
13756                 if (ret)
13757                         break;
13758         }
13759
13760         return ret;
13761 }
13762
13763 static int intel_modeset_checks(struct drm_atomic_state *state)
13764 {
13765         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13766         struct drm_i915_private *dev_priv = to_i915(state->dev);
13767         struct drm_crtc *crtc;
13768         struct drm_crtc_state *crtc_state;
13769         int ret = 0, i;
13770
13771         if (!check_digital_port_conflicts(state)) {
13772                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13773                 return -EINVAL;
13774         }
13775
13776         intel_state->modeset = true;
13777         intel_state->active_crtcs = dev_priv->active_crtcs;
13778
13779         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13780                 if (crtc_state->active)
13781                         intel_state->active_crtcs |= 1 << i;
13782                 else
13783                         intel_state->active_crtcs &= ~(1 << i);
13784
13785                 if (crtc_state->active != crtc->state->active)
13786                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13787         }
13788
13789         /*
13790          * See if the config requires any additional preparation, e.g.
13791          * to adjust global state with pipes off.  We need to do this
13792          * here so we can get the modeset_pipe updated config for the new
13793          * mode set on this crtc.  For other crtcs we need to use the
13794          * adjusted_mode bits in the crtc directly.
13795          */
13796         if (dev_priv->display.modeset_calc_cdclk) {
13797                 if (!intel_state->cdclk_pll_vco)
13798                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13799                 if (!intel_state->cdclk_pll_vco)
13800                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13801
13802                 ret = dev_priv->display.modeset_calc_cdclk(state);
13803                 if (ret < 0)
13804                         return ret;
13805
13806                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13807                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13808                         ret = intel_modeset_all_pipes(state);
13809
13810                 if (ret < 0)
13811                         return ret;
13812
13813                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13814                               intel_state->cdclk, intel_state->dev_cdclk);
13815         } else
13816                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13817
13818         intel_modeset_clear_plls(state);
13819
13820         if (IS_HASWELL(dev_priv))
13821                 return haswell_mode_set_planes_workaround(state);
13822
13823         return 0;
13824 }
13825
13826 /*
13827  * Handle calculation of various watermark data at the end of the atomic check
13828  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13829  * handlers to ensure that all derived state has been updated.
13830  */
13831 static int calc_watermark_data(struct drm_atomic_state *state)
13832 {
13833         struct drm_device *dev = state->dev;
13834         struct drm_i915_private *dev_priv = to_i915(dev);
13835
13836         /* Is there platform-specific watermark information to calculate? */
13837         if (dev_priv->display.compute_global_watermarks)
13838                 return dev_priv->display.compute_global_watermarks(state);
13839
13840         return 0;
13841 }
13842
13843 /**
13844  * intel_atomic_check - validate state object
13845  * @dev: drm device
13846  * @state: state to validate
13847  */
13848 static int intel_atomic_check(struct drm_device *dev,
13849                               struct drm_atomic_state *state)
13850 {
13851         struct drm_i915_private *dev_priv = to_i915(dev);
13852         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13853         struct drm_crtc *crtc;
13854         struct drm_crtc_state *crtc_state;
13855         int ret, i;
13856         bool any_ms = false;
13857
13858         ret = drm_atomic_helper_check_modeset(dev, state);
13859         if (ret)
13860                 return ret;
13861
13862         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13863                 struct intel_crtc_state *pipe_config =
13864                         to_intel_crtc_state(crtc_state);
13865
13866                 /* Catch I915_MODE_FLAG_INHERITED */
13867                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13868                         crtc_state->mode_changed = true;
13869
13870                 if (!needs_modeset(crtc_state))
13871                         continue;
13872
13873                 if (!crtc_state->enable) {
13874                         any_ms = true;
13875                         continue;
13876                 }
13877
13878                 /* FIXME: For only active_changed we shouldn't need to do any
13879                  * state recomputation at all. */
13880
13881                 ret = drm_atomic_add_affected_connectors(state, crtc);
13882                 if (ret)
13883                         return ret;
13884
13885                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13886                 if (ret) {
13887                         intel_dump_pipe_config(to_intel_crtc(crtc),
13888                                                pipe_config, "[failed]");
13889                         return ret;
13890                 }
13891
13892                 if (i915.fastboot &&
13893                     intel_pipe_config_compare(dev,
13894                                         to_intel_crtc_state(crtc->state),
13895                                         pipe_config, true)) {
13896                         crtc_state->mode_changed = false;
13897                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13898                 }
13899
13900                 if (needs_modeset(crtc_state))
13901                         any_ms = true;
13902
13903                 ret = drm_atomic_add_affected_planes(state, crtc);
13904                 if (ret)
13905                         return ret;
13906
13907                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13908                                        needs_modeset(crtc_state) ?
13909                                        "[modeset]" : "[fastset]");
13910         }
13911
13912         if (any_ms) {
13913                 ret = intel_modeset_checks(state);
13914
13915                 if (ret)
13916                         return ret;
13917         } else
13918                 intel_state->cdclk = dev_priv->cdclk_freq;
13919
13920         ret = drm_atomic_helper_check_planes(dev, state);
13921         if (ret)
13922                 return ret;
13923
13924         intel_fbc_choose_crtc(dev_priv, state);
13925         return calc_watermark_data(state);
13926 }
13927
13928 static int intel_atomic_prepare_commit(struct drm_device *dev,
13929                                        struct drm_atomic_state *state,
13930                                        bool nonblock)
13931 {
13932         struct drm_i915_private *dev_priv = to_i915(dev);
13933         struct drm_plane_state *plane_state;
13934         struct drm_crtc_state *crtc_state;
13935         struct drm_plane *plane;
13936         struct drm_crtc *crtc;
13937         int i, ret;
13938
13939         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13940                 if (state->legacy_cursor_update)
13941                         continue;
13942
13943                 ret = intel_crtc_wait_for_pending_flips(crtc);
13944                 if (ret)
13945                         return ret;
13946
13947                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13948                         flush_workqueue(dev_priv->wq);
13949         }
13950
13951         ret = mutex_lock_interruptible(&dev->struct_mutex);
13952         if (ret)
13953                 return ret;
13954
13955         ret = drm_atomic_helper_prepare_planes(dev, state);
13956         mutex_unlock(&dev->struct_mutex);
13957
13958         if (!ret && !nonblock) {
13959                 for_each_plane_in_state(state, plane, plane_state, i) {
13960                         struct intel_plane_state *intel_plane_state =
13961                                 to_intel_plane_state(plane_state);
13962
13963                         if (!intel_plane_state->wait_req)
13964                                 continue;
13965
13966                         ret = i915_wait_request(intel_plane_state->wait_req,
13967                                                 true, NULL, NULL);
13968                         if (ret) {
13969                                 /* Any hang should be swallowed by the wait */
13970                                 WARN_ON(ret == -EIO);
13971                                 mutex_lock(&dev->struct_mutex);
13972                                 drm_atomic_helper_cleanup_planes(dev, state);
13973                                 mutex_unlock(&dev->struct_mutex);
13974                                 break;
13975                         }
13976                 }
13977         }
13978
13979         return ret;
13980 }
13981
13982 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13983 {
13984         struct drm_device *dev = crtc->base.dev;
13985
13986         if (!dev->max_vblank_count)
13987                 return drm_accurate_vblank_count(&crtc->base);
13988
13989         return dev->driver->get_vblank_counter(dev, crtc->pipe);
13990 }
13991
13992 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13993                                           struct drm_i915_private *dev_priv,
13994                                           unsigned crtc_mask)
13995 {
13996         unsigned last_vblank_count[I915_MAX_PIPES];
13997         enum pipe pipe;
13998         int ret;
13999
14000         if (!crtc_mask)
14001                 return;
14002
14003         for_each_pipe(dev_priv, pipe) {
14004                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14005
14006                 if (!((1 << pipe) & crtc_mask))
14007                         continue;
14008
14009                 ret = drm_crtc_vblank_get(crtc);
14010                 if (WARN_ON(ret != 0)) {
14011                         crtc_mask &= ~(1 << pipe);
14012                         continue;
14013                 }
14014
14015                 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14016         }
14017
14018         for_each_pipe(dev_priv, pipe) {
14019                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14020                 long lret;
14021
14022                 if (!((1 << pipe) & crtc_mask))
14023                         continue;
14024
14025                 lret = wait_event_timeout(dev->vblank[pipe].queue,
14026                                 last_vblank_count[pipe] !=
14027                                         drm_crtc_vblank_count(crtc),
14028                                 msecs_to_jiffies(50));
14029
14030                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14031
14032                 drm_crtc_vblank_put(crtc);
14033         }
14034 }
14035
14036 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14037 {
14038         /* fb updated, need to unpin old fb */
14039         if (crtc_state->fb_changed)
14040                 return true;
14041
14042         /* wm changes, need vblank before final wm's */
14043         if (crtc_state->update_wm_post)
14044                 return true;
14045
14046         /*
14047          * cxsr is re-enabled after vblank.
14048          * This is already handled by crtc_state->update_wm_post,
14049          * but added for clarity.
14050          */
14051         if (crtc_state->disable_cxsr)
14052                 return true;
14053
14054         return false;
14055 }
14056
14057 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14058 {
14059         struct drm_device *dev = state->dev;
14060         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14061         struct drm_i915_private *dev_priv = to_i915(dev);
14062         struct drm_crtc_state *old_crtc_state;
14063         struct drm_crtc *crtc;
14064         struct intel_crtc_state *intel_cstate;
14065         struct drm_plane *plane;
14066         struct drm_plane_state *plane_state;
14067         bool hw_check = intel_state->modeset;
14068         unsigned long put_domains[I915_MAX_PIPES] = {};
14069         unsigned crtc_vblank_mask = 0;
14070         int i, ret;
14071
14072         for_each_plane_in_state(state, plane, plane_state, i) {
14073                 struct intel_plane_state *intel_plane_state =
14074                         to_intel_plane_state(plane_state);
14075
14076                 if (!intel_plane_state->wait_req)
14077                         continue;
14078
14079                 ret = i915_wait_request(intel_plane_state->wait_req,
14080                                         true, NULL, NULL);
14081                 /* EIO should be eaten, and we can't get interrupted in the
14082                  * worker, and blocking commits have waited already. */
14083                 WARN_ON(ret);
14084         }
14085
14086         drm_atomic_helper_wait_for_dependencies(state);
14087
14088         if (intel_state->modeset) {
14089                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14090                        sizeof(intel_state->min_pixclk));
14091                 dev_priv->active_crtcs = intel_state->active_crtcs;
14092                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14093
14094                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14095         }
14096
14097         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14098                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14099
14100                 if (needs_modeset(crtc->state) ||
14101                     to_intel_crtc_state(crtc->state)->update_pipe) {
14102                         hw_check = true;
14103
14104                         put_domains[to_intel_crtc(crtc)->pipe] =
14105                                 modeset_get_crtc_power_domains(crtc,
14106                                         to_intel_crtc_state(crtc->state));
14107                 }
14108
14109                 if (!needs_modeset(crtc->state))
14110                         continue;
14111
14112                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14113
14114                 if (old_crtc_state->active) {
14115                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14116                         dev_priv->display.crtc_disable(crtc);
14117                         intel_crtc->active = false;
14118                         intel_fbc_disable(intel_crtc);
14119                         intel_disable_shared_dpll(intel_crtc);
14120
14121                         /*
14122                          * Underruns don't always raise
14123                          * interrupts, so check manually.
14124                          */
14125                         intel_check_cpu_fifo_underruns(dev_priv);
14126                         intel_check_pch_fifo_underruns(dev_priv);
14127
14128                         if (!crtc->state->active)
14129                                 intel_update_watermarks(crtc);
14130                 }
14131         }
14132
14133         /* Only after disabling all output pipelines that will be changed can we
14134          * update the the output configuration. */
14135         intel_modeset_update_crtc_state(state);
14136
14137         if (intel_state->modeset) {
14138                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14139
14140                 if (dev_priv->display.modeset_commit_cdclk &&
14141                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14142                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14143                         dev_priv->display.modeset_commit_cdclk(state);
14144
14145                 intel_modeset_verify_disabled(dev);
14146         }
14147
14148         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14149         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14151                 bool modeset = needs_modeset(crtc->state);
14152                 struct intel_crtc_state *pipe_config =
14153                         to_intel_crtc_state(crtc->state);
14154
14155                 if (modeset && crtc->state->active) {
14156                         update_scanline_offset(to_intel_crtc(crtc));
14157                         dev_priv->display.crtc_enable(crtc);
14158                 }
14159
14160                 /* Complete events for now disable pipes here. */
14161                 if (modeset && !crtc->state->active && crtc->state->event) {
14162                         spin_lock_irq(&dev->event_lock);
14163                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
14164                         spin_unlock_irq(&dev->event_lock);
14165
14166                         crtc->state->event = NULL;
14167                 }
14168
14169                 if (!modeset)
14170                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14171
14172                 if (crtc->state->active &&
14173                     drm_atomic_get_existing_plane_state(state, crtc->primary))
14174                         intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
14175
14176                 if (crtc->state->active)
14177                         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14178
14179                 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
14180                         crtc_vblank_mask |= 1 << i;
14181         }
14182
14183         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14184          * already, but still need the state for the delayed optimization. To
14185          * fix this:
14186          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14187          * - schedule that vblank worker _before_ calling hw_done
14188          * - at the start of commit_tail, cancel it _synchrously
14189          * - switch over to the vblank wait helper in the core after that since
14190          *   we don't need out special handling any more.
14191          */
14192         if (!state->legacy_cursor_update)
14193                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14194
14195         /*
14196          * Now that the vblank has passed, we can go ahead and program the
14197          * optimal watermarks on platforms that need two-step watermark
14198          * programming.
14199          *
14200          * TODO: Move this (and other cleanup) to an async worker eventually.
14201          */
14202         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14203                 intel_cstate = to_intel_crtc_state(crtc->state);
14204
14205                 if (dev_priv->display.optimize_watermarks)
14206                         dev_priv->display.optimize_watermarks(intel_cstate);
14207         }
14208
14209         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14210                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14211
14212                 if (put_domains[i])
14213                         modeset_put_power_domains(dev_priv, put_domains[i]);
14214
14215                 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14216         }
14217
14218         drm_atomic_helper_commit_hw_done(state);
14219
14220         if (intel_state->modeset)
14221                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14222
14223         mutex_lock(&dev->struct_mutex);
14224         drm_atomic_helper_cleanup_planes(dev, state);
14225         mutex_unlock(&dev->struct_mutex);
14226
14227         drm_atomic_helper_commit_cleanup_done(state);
14228
14229         drm_atomic_state_free(state);
14230
14231         /* As one of the primary mmio accessors, KMS has a high likelihood
14232          * of triggering bugs in unclaimed access. After we finish
14233          * modesetting, see if an error has been flagged, and if so
14234          * enable debugging for the next modeset - and hope we catch
14235          * the culprit.
14236          *
14237          * XXX note that we assume display power is on at this point.
14238          * This might hold true now but we need to add pm helper to check
14239          * unclaimed only when the hardware is on, as atomic commits
14240          * can happen also when the device is completely off.
14241          */
14242         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14243 }
14244
14245 static void intel_atomic_commit_work(struct work_struct *work)
14246 {
14247         struct drm_atomic_state *state = container_of(work,
14248                                                       struct drm_atomic_state,
14249                                                       commit_work);
14250         intel_atomic_commit_tail(state);
14251 }
14252
14253 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14254 {
14255         struct drm_plane_state *old_plane_state;
14256         struct drm_plane *plane;
14257         int i;
14258
14259         for_each_plane_in_state(state, plane, old_plane_state, i)
14260                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14261                                   intel_fb_obj(plane->state->fb),
14262                                   to_intel_plane(plane)->frontbuffer_bit);
14263 }
14264
14265 /**
14266  * intel_atomic_commit - commit validated state object
14267  * @dev: DRM device
14268  * @state: the top-level driver state object
14269  * @nonblock: nonblocking commit
14270  *
14271  * This function commits a top-level state object that has been validated
14272  * with drm_atomic_helper_check().
14273  *
14274  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
14275  * nonblocking commits are only safe for pure plane updates. Everything else
14276  * should work though.
14277  *
14278  * RETURNS
14279  * Zero for success or -errno.
14280  */
14281 static int intel_atomic_commit(struct drm_device *dev,
14282                                struct drm_atomic_state *state,
14283                                bool nonblock)
14284 {
14285         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14286         struct drm_i915_private *dev_priv = to_i915(dev);
14287         int ret = 0;
14288
14289         if (intel_state->modeset && nonblock) {
14290                 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14291                 return -EINVAL;
14292         }
14293
14294         ret = drm_atomic_helper_setup_commit(state, nonblock);
14295         if (ret)
14296                 return ret;
14297
14298         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14299
14300         ret = intel_atomic_prepare_commit(dev, state, nonblock);
14301         if (ret) {
14302                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14303                 return ret;
14304         }
14305
14306         drm_atomic_helper_swap_state(state, true);
14307         dev_priv->wm.distrust_bios_wm = false;
14308         dev_priv->wm.skl_results = intel_state->wm_results;
14309         intel_shared_dpll_commit(state);
14310         intel_atomic_track_fbs(state);
14311
14312         if (nonblock)
14313                 queue_work(system_unbound_wq, &state->commit_work);
14314         else
14315                 intel_atomic_commit_tail(state);
14316
14317         return 0;
14318 }
14319
14320 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14321 {
14322         struct drm_device *dev = crtc->dev;
14323         struct drm_atomic_state *state;
14324         struct drm_crtc_state *crtc_state;
14325         int ret;
14326
14327         state = drm_atomic_state_alloc(dev);
14328         if (!state) {
14329                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14330                               crtc->base.id, crtc->name);
14331                 return;
14332         }
14333
14334         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14335
14336 retry:
14337         crtc_state = drm_atomic_get_crtc_state(state, crtc);
14338         ret = PTR_ERR_OR_ZERO(crtc_state);
14339         if (!ret) {
14340                 if (!crtc_state->active)
14341                         goto out;
14342
14343                 crtc_state->mode_changed = true;
14344                 ret = drm_atomic_commit(state);
14345         }
14346
14347         if (ret == -EDEADLK) {
14348                 drm_atomic_state_clear(state);
14349                 drm_modeset_backoff(state->acquire_ctx);
14350                 goto retry;
14351         }
14352
14353         if (ret)
14354 out:
14355                 drm_atomic_state_free(state);
14356 }
14357
14358 #undef for_each_intel_crtc_masked
14359
14360 /*
14361  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14362  *        drm_atomic_helper_legacy_gamma_set() directly.
14363  */
14364 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14365                                          u16 *red, u16 *green, u16 *blue,
14366                                          uint32_t size)
14367 {
14368         struct drm_device *dev = crtc->dev;
14369         struct drm_mode_config *config = &dev->mode_config;
14370         struct drm_crtc_state *state;
14371         int ret;
14372
14373         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14374         if (ret)
14375                 return ret;
14376
14377         /*
14378          * Make sure we update the legacy properties so this works when
14379          * atomic is not enabled.
14380          */
14381
14382         state = crtc->state;
14383
14384         drm_object_property_set_value(&crtc->base,
14385                                       config->degamma_lut_property,
14386                                       (state->degamma_lut) ?
14387                                       state->degamma_lut->base.id : 0);
14388
14389         drm_object_property_set_value(&crtc->base,
14390                                       config->ctm_property,
14391                                       (state->ctm) ?
14392                                       state->ctm->base.id : 0);
14393
14394         drm_object_property_set_value(&crtc->base,
14395                                       config->gamma_lut_property,
14396                                       (state->gamma_lut) ?
14397                                       state->gamma_lut->base.id : 0);
14398
14399         return 0;
14400 }
14401
14402 static const struct drm_crtc_funcs intel_crtc_funcs = {
14403         .gamma_set = intel_atomic_legacy_gamma_set,
14404         .set_config = drm_atomic_helper_set_config,
14405         .set_property = drm_atomic_helper_crtc_set_property,
14406         .destroy = intel_crtc_destroy,
14407         .page_flip = intel_crtc_page_flip,
14408         .atomic_duplicate_state = intel_crtc_duplicate_state,
14409         .atomic_destroy_state = intel_crtc_destroy_state,
14410 };
14411
14412 /**
14413  * intel_prepare_plane_fb - Prepare fb for usage on plane
14414  * @plane: drm plane to prepare for
14415  * @fb: framebuffer to prepare for presentation
14416  *
14417  * Prepares a framebuffer for usage on a display plane.  Generally this
14418  * involves pinning the underlying object and updating the frontbuffer tracking
14419  * bits.  Some older platforms need special physical address handling for
14420  * cursor planes.
14421  *
14422  * Must be called with struct_mutex held.
14423  *
14424  * Returns 0 on success, negative error code on failure.
14425  */
14426 int
14427 intel_prepare_plane_fb(struct drm_plane *plane,
14428                        const struct drm_plane_state *new_state)
14429 {
14430         struct drm_device *dev = plane->dev;
14431         struct drm_framebuffer *fb = new_state->fb;
14432         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14433         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14434         struct reservation_object *resv;
14435         int ret = 0;
14436
14437         if (!obj && !old_obj)
14438                 return 0;
14439
14440         if (old_obj) {
14441                 struct drm_crtc_state *crtc_state =
14442                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14443
14444                 /* Big Hammer, we also need to ensure that any pending
14445                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14446                  * current scanout is retired before unpinning the old
14447                  * framebuffer. Note that we rely on userspace rendering
14448                  * into the buffer attached to the pipe they are waiting
14449                  * on. If not, userspace generates a GPU hang with IPEHR
14450                  * point to the MI_WAIT_FOR_EVENT.
14451                  *
14452                  * This should only fail upon a hung GPU, in which case we
14453                  * can safely continue.
14454                  */
14455                 if (needs_modeset(crtc_state))
14456                         ret = i915_gem_object_wait_rendering(old_obj, true);
14457                 if (ret) {
14458                         /* GPU hangs should have been swallowed by the wait */
14459                         WARN_ON(ret == -EIO);
14460                         return ret;
14461                 }
14462         }
14463
14464         if (!obj)
14465                 return 0;
14466
14467         /* For framebuffer backed by dmabuf, wait for fence */
14468         resv = i915_gem_object_get_dmabuf_resv(obj);
14469         if (resv) {
14470                 long lret;
14471
14472                 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14473                                                            MAX_SCHEDULE_TIMEOUT);
14474                 if (lret == -ERESTARTSYS)
14475                         return lret;
14476
14477                 WARN(lret < 0, "waiting returns %li\n", lret);
14478         }
14479
14480         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14481             INTEL_INFO(dev)->cursor_needs_physical) {
14482                 int align = IS_I830(dev) ? 16 * 1024 : 256;
14483                 ret = i915_gem_object_attach_phys(obj, align);
14484                 if (ret)
14485                         DRM_DEBUG_KMS("failed to attach phys object\n");
14486         } else {
14487                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14488         }
14489
14490         if (ret == 0) {
14491                 to_intel_plane_state(new_state)->wait_req =
14492                         i915_gem_active_get(&obj->last_write,
14493                                             &obj->base.dev->struct_mutex);
14494         }
14495
14496         return ret;
14497 }
14498
14499 /**
14500  * intel_cleanup_plane_fb - Cleans up an fb after plane use
14501  * @plane: drm plane to clean up for
14502  * @fb: old framebuffer that was on plane
14503  *
14504  * Cleans up a framebuffer that has just been removed from a plane.
14505  *
14506  * Must be called with struct_mutex held.
14507  */
14508 void
14509 intel_cleanup_plane_fb(struct drm_plane *plane,
14510                        const struct drm_plane_state *old_state)
14511 {
14512         struct drm_device *dev = plane->dev;
14513         struct intel_plane_state *old_intel_state;
14514         struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14515         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14516         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14517
14518         old_intel_state = to_intel_plane_state(old_state);
14519
14520         if (!obj && !old_obj)
14521                 return;
14522
14523         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14524             !INTEL_INFO(dev)->cursor_needs_physical))
14525                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14526
14527         i915_gem_request_assign(&intel_state->wait_req, NULL);
14528         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14529 }
14530
14531 int
14532 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14533 {
14534         int max_scale;
14535         int crtc_clock, cdclk;
14536
14537         if (!intel_crtc || !crtc_state->base.enable)
14538                 return DRM_PLANE_HELPER_NO_SCALING;
14539
14540         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14541         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14542
14543         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14544                 return DRM_PLANE_HELPER_NO_SCALING;
14545
14546         /*
14547          * skl max scale is lower of:
14548          *    close to 3 but not 3, -1 is for that purpose
14549          *            or
14550          *    cdclk/crtc_clock
14551          */
14552         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14553
14554         return max_scale;
14555 }
14556
14557 static int
14558 intel_check_primary_plane(struct drm_plane *plane,
14559                           struct intel_crtc_state *crtc_state,
14560                           struct intel_plane_state *state)
14561 {
14562         struct drm_i915_private *dev_priv = to_i915(plane->dev);
14563         struct drm_crtc *crtc = state->base.crtc;
14564         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14565         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14566         bool can_position = false;
14567         int ret;
14568
14569         if (INTEL_GEN(dev_priv) >= 9) {
14570                 /* use scaler when colorkey is not required */
14571                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14572                         min_scale = 1;
14573                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14574                 }
14575                 can_position = true;
14576         }
14577
14578         ret = drm_plane_helper_check_state(&state->base,
14579                                            &state->clip,
14580                                            min_scale, max_scale,
14581                                            can_position, true);
14582         if (ret)
14583                 return ret;
14584
14585         if (!state->base.fb)
14586                 return 0;
14587
14588         if (INTEL_GEN(dev_priv) >= 9) {
14589                 ret = skl_check_plane_surface(state);
14590                 if (ret)
14591                         return ret;
14592         }
14593
14594         return 0;
14595 }
14596
14597 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14598                                     struct drm_crtc_state *old_crtc_state)
14599 {
14600         struct drm_device *dev = crtc->dev;
14601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14602         struct intel_crtc_state *old_intel_state =
14603                 to_intel_crtc_state(old_crtc_state);
14604         bool modeset = needs_modeset(crtc->state);
14605
14606         /* Perform vblank evasion around commit operation */
14607         intel_pipe_update_start(intel_crtc);
14608
14609         if (modeset)
14610                 return;
14611
14612         if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14613                 intel_color_set_csc(crtc->state);
14614                 intel_color_load_luts(crtc->state);
14615         }
14616
14617         if (to_intel_crtc_state(crtc->state)->update_pipe)
14618                 intel_update_pipe_config(intel_crtc, old_intel_state);
14619         else if (INTEL_INFO(dev)->gen >= 9)
14620                 skl_detach_scalers(intel_crtc);
14621 }
14622
14623 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14624                                      struct drm_crtc_state *old_crtc_state)
14625 {
14626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14627
14628         intel_pipe_update_end(intel_crtc, NULL);
14629 }
14630
14631 /**
14632  * intel_plane_destroy - destroy a plane
14633  * @plane: plane to destroy
14634  *
14635  * Common destruction function for all types of planes (primary, cursor,
14636  * sprite).
14637  */
14638 void intel_plane_destroy(struct drm_plane *plane)
14639 {
14640         if (!plane)
14641                 return;
14642
14643         drm_plane_cleanup(plane);
14644         kfree(to_intel_plane(plane));
14645 }
14646
14647 const struct drm_plane_funcs intel_plane_funcs = {
14648         .update_plane = drm_atomic_helper_update_plane,
14649         .disable_plane = drm_atomic_helper_disable_plane,
14650         .destroy = intel_plane_destroy,
14651         .set_property = drm_atomic_helper_plane_set_property,
14652         .atomic_get_property = intel_plane_atomic_get_property,
14653         .atomic_set_property = intel_plane_atomic_set_property,
14654         .atomic_duplicate_state = intel_plane_duplicate_state,
14655         .atomic_destroy_state = intel_plane_destroy_state,
14656
14657 };
14658
14659 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14660                                                     int pipe)
14661 {
14662         struct intel_plane *primary = NULL;
14663         struct intel_plane_state *state = NULL;
14664         const uint32_t *intel_primary_formats;
14665         unsigned int num_formats;
14666         int ret;
14667
14668         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14669         if (!primary)
14670                 goto fail;
14671
14672         state = intel_create_plane_state(&primary->base);
14673         if (!state)
14674                 goto fail;
14675         primary->base.state = &state->base;
14676
14677         primary->can_scale = false;
14678         primary->max_downscale = 1;
14679         if (INTEL_INFO(dev)->gen >= 9) {
14680                 primary->can_scale = true;
14681                 state->scaler_id = -1;
14682         }
14683         primary->pipe = pipe;
14684         primary->plane = pipe;
14685         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14686         primary->check_plane = intel_check_primary_plane;
14687         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14688                 primary->plane = !pipe;
14689
14690         if (INTEL_INFO(dev)->gen >= 9) {
14691                 intel_primary_formats = skl_primary_formats;
14692                 num_formats = ARRAY_SIZE(skl_primary_formats);
14693
14694                 primary->update_plane = skylake_update_primary_plane;
14695                 primary->disable_plane = skylake_disable_primary_plane;
14696         } else if (HAS_PCH_SPLIT(dev)) {
14697                 intel_primary_formats = i965_primary_formats;
14698                 num_formats = ARRAY_SIZE(i965_primary_formats);
14699
14700                 primary->update_plane = ironlake_update_primary_plane;
14701                 primary->disable_plane = i9xx_disable_primary_plane;
14702         } else if (INTEL_INFO(dev)->gen >= 4) {
14703                 intel_primary_formats = i965_primary_formats;
14704                 num_formats = ARRAY_SIZE(i965_primary_formats);
14705
14706                 primary->update_plane = i9xx_update_primary_plane;
14707                 primary->disable_plane = i9xx_disable_primary_plane;
14708         } else {
14709                 intel_primary_formats = i8xx_primary_formats;
14710                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14711
14712                 primary->update_plane = i9xx_update_primary_plane;
14713                 primary->disable_plane = i9xx_disable_primary_plane;
14714         }
14715
14716         if (INTEL_INFO(dev)->gen >= 9)
14717                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14718                                                &intel_plane_funcs,
14719                                                intel_primary_formats, num_formats,
14720                                                DRM_PLANE_TYPE_PRIMARY,
14721                                                "plane 1%c", pipe_name(pipe));
14722         else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14723                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14724                                                &intel_plane_funcs,
14725                                                intel_primary_formats, num_formats,
14726                                                DRM_PLANE_TYPE_PRIMARY,
14727                                                "primary %c", pipe_name(pipe));
14728         else
14729                 ret = drm_universal_plane_init(dev, &primary->base, 0,
14730                                                &intel_plane_funcs,
14731                                                intel_primary_formats, num_formats,
14732                                                DRM_PLANE_TYPE_PRIMARY,
14733                                                "plane %c", plane_name(primary->plane));
14734         if (ret)
14735                 goto fail;
14736
14737         if (INTEL_INFO(dev)->gen >= 4)
14738                 intel_create_rotation_property(dev, primary);
14739
14740         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14741
14742         return &primary->base;
14743
14744 fail:
14745         kfree(state);
14746         kfree(primary);
14747
14748         return NULL;
14749 }
14750
14751 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14752 {
14753         if (!dev->mode_config.rotation_property) {
14754                 unsigned long flags = DRM_ROTATE_0 |
14755                         DRM_ROTATE_180;
14756
14757                 if (INTEL_INFO(dev)->gen >= 9)
14758                         flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
14759
14760                 dev->mode_config.rotation_property =
14761                         drm_mode_create_rotation_property(dev, flags);
14762         }
14763         if (dev->mode_config.rotation_property)
14764                 drm_object_attach_property(&plane->base.base,
14765                                 dev->mode_config.rotation_property,
14766                                 plane->base.state->rotation);
14767 }
14768
14769 static int
14770 intel_check_cursor_plane(struct drm_plane *plane,
14771                          struct intel_crtc_state *crtc_state,
14772                          struct intel_plane_state *state)
14773 {
14774         struct drm_framebuffer *fb = state->base.fb;
14775         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14776         enum pipe pipe = to_intel_plane(plane)->pipe;
14777         unsigned stride;
14778         int ret;
14779
14780         ret = drm_plane_helper_check_state(&state->base,
14781                                            &state->clip,
14782                                            DRM_PLANE_HELPER_NO_SCALING,
14783                                            DRM_PLANE_HELPER_NO_SCALING,
14784                                            true, true);
14785         if (ret)
14786                 return ret;
14787
14788         /* if we want to turn off the cursor ignore width and height */
14789         if (!obj)
14790                 return 0;
14791
14792         /* Check for which cursor types we support */
14793         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14794                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14795                           state->base.crtc_w, state->base.crtc_h);
14796                 return -EINVAL;
14797         }
14798
14799         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14800         if (obj->base.size < stride * state->base.crtc_h) {
14801                 DRM_DEBUG_KMS("buffer is too small\n");
14802                 return -ENOMEM;
14803         }
14804
14805         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14806                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14807                 return -EINVAL;
14808         }
14809
14810         /*
14811          * There's something wrong with the cursor on CHV pipe C.
14812          * If it straddles the left edge of the screen then
14813          * moving it away from the edge or disabling it often
14814          * results in a pipe underrun, and often that can lead to
14815          * dead pipe (constant underrun reported, and it scans
14816          * out just a solid color). To recover from that, the
14817          * display power well must be turned off and on again.
14818          * Refuse the put the cursor into that compromised position.
14819          */
14820         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14821             state->base.visible && state->base.crtc_x < 0) {
14822                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14823                 return -EINVAL;
14824         }
14825
14826         return 0;
14827 }
14828
14829 static void
14830 intel_disable_cursor_plane(struct drm_plane *plane,
14831                            struct drm_crtc *crtc)
14832 {
14833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14834
14835         intel_crtc->cursor_addr = 0;
14836         intel_crtc_update_cursor(crtc, NULL);
14837 }
14838
14839 static void
14840 intel_update_cursor_plane(struct drm_plane *plane,
14841                           const struct intel_crtc_state *crtc_state,
14842                           const struct intel_plane_state *state)
14843 {
14844         struct drm_crtc *crtc = crtc_state->base.crtc;
14845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14846         struct drm_device *dev = plane->dev;
14847         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14848         uint32_t addr;
14849
14850         if (!obj)
14851                 addr = 0;
14852         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14853                 addr = i915_gem_obj_ggtt_offset(obj);
14854         else
14855                 addr = obj->phys_handle->busaddr;
14856
14857         intel_crtc->cursor_addr = addr;
14858         intel_crtc_update_cursor(crtc, state);
14859 }
14860
14861 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14862                                                    int pipe)
14863 {
14864         struct intel_plane *cursor = NULL;
14865         struct intel_plane_state *state = NULL;
14866         int ret;
14867
14868         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14869         if (!cursor)
14870                 goto fail;
14871
14872         state = intel_create_plane_state(&cursor->base);
14873         if (!state)
14874                 goto fail;
14875         cursor->base.state = &state->base;
14876
14877         cursor->can_scale = false;
14878         cursor->max_downscale = 1;
14879         cursor->pipe = pipe;
14880         cursor->plane = pipe;
14881         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14882         cursor->check_plane = intel_check_cursor_plane;
14883         cursor->update_plane = intel_update_cursor_plane;
14884         cursor->disable_plane = intel_disable_cursor_plane;
14885
14886         ret = drm_universal_plane_init(dev, &cursor->base, 0,
14887                                        &intel_plane_funcs,
14888                                        intel_cursor_formats,
14889                                        ARRAY_SIZE(intel_cursor_formats),
14890                                        DRM_PLANE_TYPE_CURSOR,
14891                                        "cursor %c", pipe_name(pipe));
14892         if (ret)
14893                 goto fail;
14894
14895         if (INTEL_INFO(dev)->gen >= 4) {
14896                 if (!dev->mode_config.rotation_property)
14897                         dev->mode_config.rotation_property =
14898                                 drm_mode_create_rotation_property(dev,
14899                                                         DRM_ROTATE_0 |
14900                                                         DRM_ROTATE_180);
14901                 if (dev->mode_config.rotation_property)
14902                         drm_object_attach_property(&cursor->base.base,
14903                                 dev->mode_config.rotation_property,
14904                                 state->base.rotation);
14905         }
14906
14907         if (INTEL_INFO(dev)->gen >=9)
14908                 state->scaler_id = -1;
14909
14910         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14911
14912         return &cursor->base;
14913
14914 fail:
14915         kfree(state);
14916         kfree(cursor);
14917
14918         return NULL;
14919 }
14920
14921 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14922         struct intel_crtc_state *crtc_state)
14923 {
14924         int i;
14925         struct intel_scaler *intel_scaler;
14926         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14927
14928         for (i = 0; i < intel_crtc->num_scalers; i++) {
14929                 intel_scaler = &scaler_state->scalers[i];
14930                 intel_scaler->in_use = 0;
14931                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14932         }
14933
14934         scaler_state->scaler_id = -1;
14935 }
14936
14937 static void intel_crtc_init(struct drm_device *dev, int pipe)
14938 {
14939         struct drm_i915_private *dev_priv = to_i915(dev);
14940         struct intel_crtc *intel_crtc;
14941         struct intel_crtc_state *crtc_state = NULL;
14942         struct drm_plane *primary = NULL;
14943         struct drm_plane *cursor = NULL;
14944         int ret;
14945
14946         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14947         if (intel_crtc == NULL)
14948                 return;
14949
14950         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14951         if (!crtc_state)
14952                 goto fail;
14953         intel_crtc->config = crtc_state;
14954         intel_crtc->base.state = &crtc_state->base;
14955         crtc_state->base.crtc = &intel_crtc->base;
14956
14957         /* initialize shared scalers */
14958         if (INTEL_INFO(dev)->gen >= 9) {
14959                 if (pipe == PIPE_C)
14960                         intel_crtc->num_scalers = 1;
14961                 else
14962                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14963
14964                 skl_init_scalers(dev, intel_crtc, crtc_state);
14965         }
14966
14967         primary = intel_primary_plane_create(dev, pipe);
14968         if (!primary)
14969                 goto fail;
14970
14971         cursor = intel_cursor_plane_create(dev, pipe);
14972         if (!cursor)
14973                 goto fail;
14974
14975         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14976                                         cursor, &intel_crtc_funcs,
14977                                         "pipe %c", pipe_name(pipe));
14978         if (ret)
14979                 goto fail;
14980
14981         /*
14982          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14983          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14984          */
14985         intel_crtc->pipe = pipe;
14986         intel_crtc->plane = pipe;
14987         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14988                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14989                 intel_crtc->plane = !pipe;
14990         }
14991
14992         intel_crtc->cursor_base = ~0;
14993         intel_crtc->cursor_cntl = ~0;
14994         intel_crtc->cursor_size = ~0;
14995
14996         intel_crtc->wm.cxsr_allowed = true;
14997
14998         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14999                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15000         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15001         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15002
15003         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15004
15005         intel_color_init(&intel_crtc->base);
15006
15007         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15008         return;
15009
15010 fail:
15011         intel_plane_destroy(primary);
15012         intel_plane_destroy(cursor);
15013         kfree(crtc_state);
15014         kfree(intel_crtc);
15015 }
15016
15017 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15018 {
15019         struct drm_encoder *encoder = connector->base.encoder;
15020         struct drm_device *dev = connector->base.dev;
15021
15022         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15023
15024         if (!encoder || WARN_ON(!encoder->crtc))
15025                 return INVALID_PIPE;
15026
15027         return to_intel_crtc(encoder->crtc)->pipe;
15028 }
15029
15030 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15031                                 struct drm_file *file)
15032 {
15033         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15034         struct drm_crtc *drmmode_crtc;
15035         struct intel_crtc *crtc;
15036
15037         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15038         if (!drmmode_crtc)
15039                 return -ENOENT;
15040
15041         crtc = to_intel_crtc(drmmode_crtc);
15042         pipe_from_crtc_id->pipe = crtc->pipe;
15043
15044         return 0;
15045 }
15046
15047 static int intel_encoder_clones(struct intel_encoder *encoder)
15048 {
15049         struct drm_device *dev = encoder->base.dev;
15050         struct intel_encoder *source_encoder;
15051         int index_mask = 0;
15052         int entry = 0;
15053
15054         for_each_intel_encoder(dev, source_encoder) {
15055                 if (encoders_cloneable(encoder, source_encoder))
15056                         index_mask |= (1 << entry);
15057
15058                 entry++;
15059         }
15060
15061         return index_mask;
15062 }
15063
15064 static bool has_edp_a(struct drm_device *dev)
15065 {
15066         struct drm_i915_private *dev_priv = to_i915(dev);
15067
15068         if (!IS_MOBILE(dev))
15069                 return false;
15070
15071         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15072                 return false;
15073
15074         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15075                 return false;
15076
15077         return true;
15078 }
15079
15080 static bool intel_crt_present(struct drm_device *dev)
15081 {
15082         struct drm_i915_private *dev_priv = to_i915(dev);
15083
15084         if (INTEL_INFO(dev)->gen >= 9)
15085                 return false;
15086
15087         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15088                 return false;
15089
15090         if (IS_CHERRYVIEW(dev))
15091                 return false;
15092
15093         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15094                 return false;
15095
15096         /* DDI E can't be used if DDI A requires 4 lanes */
15097         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15098                 return false;
15099
15100         if (!dev_priv->vbt.int_crt_support)
15101                 return false;
15102
15103         return true;
15104 }
15105
15106 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15107 {
15108         int pps_num;
15109         int pps_idx;
15110
15111         if (HAS_DDI(dev_priv))
15112                 return;
15113         /*
15114          * This w/a is needed at least on CPT/PPT, but to be sure apply it
15115          * everywhere where registers can be write protected.
15116          */
15117         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15118                 pps_num = 2;
15119         else
15120                 pps_num = 1;
15121
15122         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15123                 u32 val = I915_READ(PP_CONTROL(pps_idx));
15124
15125                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15126                 I915_WRITE(PP_CONTROL(pps_idx), val);
15127         }
15128 }
15129
15130 static void intel_pps_init(struct drm_i915_private *dev_priv)
15131 {
15132         if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15133                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15134         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15135                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15136         else
15137                 dev_priv->pps_mmio_base = PPS_BASE;
15138
15139         intel_pps_unlock_regs_wa(dev_priv);
15140 }
15141
15142 static void intel_setup_outputs(struct drm_device *dev)
15143 {
15144         struct drm_i915_private *dev_priv = to_i915(dev);
15145         struct intel_encoder *encoder;
15146         bool dpd_is_edp = false;
15147
15148         intel_pps_init(dev_priv);
15149
15150         /*
15151          * intel_edp_init_connector() depends on this completing first, to
15152          * prevent the registeration of both eDP and LVDS and the incorrect
15153          * sharing of the PPS.
15154          */
15155         intel_lvds_init(dev);
15156
15157         if (intel_crt_present(dev))
15158                 intel_crt_init(dev);
15159
15160         if (IS_BROXTON(dev)) {
15161                 /*
15162                  * FIXME: Broxton doesn't support port detection via the
15163                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15164                  * detect the ports.
15165                  */
15166                 intel_ddi_init(dev, PORT_A);
15167                 intel_ddi_init(dev, PORT_B);
15168                 intel_ddi_init(dev, PORT_C);
15169
15170                 intel_dsi_init(dev);
15171         } else if (HAS_DDI(dev)) {
15172                 int found;
15173
15174                 /*
15175                  * Haswell uses DDI functions to detect digital outputs.
15176                  * On SKL pre-D0 the strap isn't connected, so we assume
15177                  * it's there.
15178                  */
15179                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15180                 /* WaIgnoreDDIAStrap: skl */
15181                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15182                         intel_ddi_init(dev, PORT_A);
15183
15184                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15185                  * register */
15186                 found = I915_READ(SFUSE_STRAP);
15187
15188                 if (found & SFUSE_STRAP_DDIB_DETECTED)
15189                         intel_ddi_init(dev, PORT_B);
15190                 if (found & SFUSE_STRAP_DDIC_DETECTED)
15191                         intel_ddi_init(dev, PORT_C);
15192                 if (found & SFUSE_STRAP_DDID_DETECTED)
15193                         intel_ddi_init(dev, PORT_D);
15194                 /*
15195                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15196                  */
15197                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15198                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15199                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15200                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15201                         intel_ddi_init(dev, PORT_E);
15202
15203         } else if (HAS_PCH_SPLIT(dev)) {
15204                 int found;
15205                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15206
15207                 if (has_edp_a(dev))
15208                         intel_dp_init(dev, DP_A, PORT_A);
15209
15210                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15211                         /* PCH SDVOB multiplex with HDMIB */
15212                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15213                         if (!found)
15214                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15215                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15216                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
15217                 }
15218
15219                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15220                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15221
15222                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15223                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15224
15225                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15226                         intel_dp_init(dev, PCH_DP_C, PORT_C);
15227
15228                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15229                         intel_dp_init(dev, PCH_DP_D, PORT_D);
15230         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15231                 bool has_edp, has_port;
15232
15233                 /*
15234                  * The DP_DETECTED bit is the latched state of the DDC
15235                  * SDA pin at boot. However since eDP doesn't require DDC
15236                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
15237                  * eDP ports may have been muxed to an alternate function.
15238                  * Thus we can't rely on the DP_DETECTED bit alone to detect
15239                  * eDP ports. Consult the VBT as well as DP_DETECTED to
15240                  * detect eDP ports.
15241                  *
15242                  * Sadly the straps seem to be missing sometimes even for HDMI
15243                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15244                  * and VBT for the presence of the port. Additionally we can't
15245                  * trust the port type the VBT declares as we've seen at least
15246                  * HDMI ports that the VBT claim are DP or eDP.
15247                  */
15248                 has_edp = intel_dp_is_edp(dev, PORT_B);
15249                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15250                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15251                         has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15252                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15253                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15254
15255                 has_edp = intel_dp_is_edp(dev, PORT_C);
15256                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15257                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15258                         has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15259                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15260                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15261
15262                 if (IS_CHERRYVIEW(dev)) {
15263                         /*
15264                          * eDP not supported on port D,
15265                          * so no need to worry about it
15266                          */
15267                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15268                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15269                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
15270                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15271                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15272                 }
15273
15274                 intel_dsi_init(dev);
15275         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15276                 bool found = false;
15277
15278                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15279                         DRM_DEBUG_KMS("probing SDVOB\n");
15280                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15281                         if (!found && IS_G4X(dev)) {
15282                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15283                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15284                         }
15285
15286                         if (!found && IS_G4X(dev))
15287                                 intel_dp_init(dev, DP_B, PORT_B);
15288                 }
15289
15290                 /* Before G4X SDVOC doesn't have its own detect register */
15291
15292                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15293                         DRM_DEBUG_KMS("probing SDVOC\n");
15294                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15295                 }
15296
15297                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15298
15299                         if (IS_G4X(dev)) {
15300                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15301                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15302                         }
15303                         if (IS_G4X(dev))
15304                                 intel_dp_init(dev, DP_C, PORT_C);
15305                 }
15306
15307                 if (IS_G4X(dev) &&
15308                     (I915_READ(DP_D) & DP_DETECTED))
15309                         intel_dp_init(dev, DP_D, PORT_D);
15310         } else if (IS_GEN2(dev))
15311                 intel_dvo_init(dev);
15312
15313         if (SUPPORTS_TV(dev))
15314                 intel_tv_init(dev);
15315
15316         intel_psr_init(dev);
15317
15318         for_each_intel_encoder(dev, encoder) {
15319                 encoder->base.possible_crtcs = encoder->crtc_mask;
15320                 encoder->base.possible_clones =
15321                         intel_encoder_clones(encoder);
15322         }
15323
15324         intel_init_pch_refclk(dev);
15325
15326         drm_helper_move_panel_connectors_to_head(dev);
15327 }
15328
15329 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15330 {
15331         struct drm_device *dev = fb->dev;
15332         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15333
15334         drm_framebuffer_cleanup(fb);
15335         mutex_lock(&dev->struct_mutex);
15336         WARN_ON(!intel_fb->obj->framebuffer_references--);
15337         i915_gem_object_put(intel_fb->obj);
15338         mutex_unlock(&dev->struct_mutex);
15339         kfree(intel_fb);
15340 }
15341
15342 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15343                                                 struct drm_file *file,
15344                                                 unsigned int *handle)
15345 {
15346         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15347         struct drm_i915_gem_object *obj = intel_fb->obj;
15348
15349         if (obj->userptr.mm) {
15350                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15351                 return -EINVAL;
15352         }
15353
15354         return drm_gem_handle_create(file, &obj->base, handle);
15355 }
15356
15357 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15358                                         struct drm_file *file,
15359                                         unsigned flags, unsigned color,
15360                                         struct drm_clip_rect *clips,
15361                                         unsigned num_clips)
15362 {
15363         struct drm_device *dev = fb->dev;
15364         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15365         struct drm_i915_gem_object *obj = intel_fb->obj;
15366
15367         mutex_lock(&dev->struct_mutex);
15368         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15369         mutex_unlock(&dev->struct_mutex);
15370
15371         return 0;
15372 }
15373
15374 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15375         .destroy = intel_user_framebuffer_destroy,
15376         .create_handle = intel_user_framebuffer_create_handle,
15377         .dirty = intel_user_framebuffer_dirty,
15378 };
15379
15380 static
15381 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15382                          uint32_t pixel_format)
15383 {
15384         u32 gen = INTEL_INFO(dev)->gen;
15385
15386         if (gen >= 9) {
15387                 int cpp = drm_format_plane_cpp(pixel_format, 0);
15388
15389                 /* "The stride in bytes must not exceed the of the size of 8K
15390                  *  pixels and 32K bytes."
15391                  */
15392                 return min(8192 * cpp, 32768);
15393         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15394                 return 32*1024;
15395         } else if (gen >= 4) {
15396                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15397                         return 16*1024;
15398                 else
15399                         return 32*1024;
15400         } else if (gen >= 3) {
15401                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15402                         return 8*1024;
15403                 else
15404                         return 16*1024;
15405         } else {
15406                 /* XXX DSPC is limited to 4k tiled */
15407                 return 8*1024;
15408         }
15409 }
15410
15411 static int intel_framebuffer_init(struct drm_device *dev,
15412                                   struct intel_framebuffer *intel_fb,
15413                                   struct drm_mode_fb_cmd2 *mode_cmd,
15414                                   struct drm_i915_gem_object *obj)
15415 {
15416         struct drm_i915_private *dev_priv = to_i915(dev);
15417         unsigned int tiling = i915_gem_object_get_tiling(obj);
15418         int ret;
15419         u32 pitch_limit, stride_alignment;
15420
15421         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15422
15423         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15424                 /*
15425                  * If there's a fence, enforce that
15426                  * the fb modifier and tiling mode match.
15427                  */
15428                 if (tiling != I915_TILING_NONE &&
15429                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15430                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15431                         return -EINVAL;
15432                 }
15433         } else {
15434                 if (tiling == I915_TILING_X) {
15435                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15436                 } else if (tiling == I915_TILING_Y) {
15437                         DRM_DEBUG("No Y tiling for legacy addfb\n");
15438                         return -EINVAL;
15439                 }
15440         }
15441
15442         /* Passed in modifier sanity checking. */
15443         switch (mode_cmd->modifier[0]) {
15444         case I915_FORMAT_MOD_Y_TILED:
15445         case I915_FORMAT_MOD_Yf_TILED:
15446                 if (INTEL_INFO(dev)->gen < 9) {
15447                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15448                                   mode_cmd->modifier[0]);
15449                         return -EINVAL;
15450                 }
15451         case DRM_FORMAT_MOD_NONE:
15452         case I915_FORMAT_MOD_X_TILED:
15453                 break;
15454         default:
15455                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15456                           mode_cmd->modifier[0]);
15457                 return -EINVAL;
15458         }
15459
15460         /*
15461          * gen2/3 display engine uses the fence if present,
15462          * so the tiling mode must match the fb modifier exactly.
15463          */
15464         if (INTEL_INFO(dev_priv)->gen < 4 &&
15465             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15466                 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15467                 return -EINVAL;
15468         }
15469
15470         stride_alignment = intel_fb_stride_alignment(dev_priv,
15471                                                      mode_cmd->modifier[0],
15472                                                      mode_cmd->pixel_format);
15473         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15474                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15475                           mode_cmd->pitches[0], stride_alignment);
15476                 return -EINVAL;
15477         }
15478
15479         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15480                                            mode_cmd->pixel_format);
15481         if (mode_cmd->pitches[0] > pitch_limit) {
15482                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15483                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15484                           "tiled" : "linear",
15485                           mode_cmd->pitches[0], pitch_limit);
15486                 return -EINVAL;
15487         }
15488
15489         /*
15490          * If there's a fence, enforce that
15491          * the fb pitch and fence stride match.
15492          */
15493         if (tiling != I915_TILING_NONE &&
15494             mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15495                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15496                           mode_cmd->pitches[0],
15497                           i915_gem_object_get_stride(obj));
15498                 return -EINVAL;
15499         }
15500
15501         /* Reject formats not supported by any plane early. */
15502         switch (mode_cmd->pixel_format) {
15503         case DRM_FORMAT_C8:
15504         case DRM_FORMAT_RGB565:
15505         case DRM_FORMAT_XRGB8888:
15506         case DRM_FORMAT_ARGB8888:
15507                 break;
15508         case DRM_FORMAT_XRGB1555:
15509                 if (INTEL_INFO(dev)->gen > 3) {
15510                         DRM_DEBUG("unsupported pixel format: %s\n",
15511                                   drm_get_format_name(mode_cmd->pixel_format));
15512                         return -EINVAL;
15513                 }
15514                 break;
15515         case DRM_FORMAT_ABGR8888:
15516                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15517                     INTEL_INFO(dev)->gen < 9) {
15518                         DRM_DEBUG("unsupported pixel format: %s\n",
15519                                   drm_get_format_name(mode_cmd->pixel_format));
15520                         return -EINVAL;
15521                 }
15522                 break;
15523         case DRM_FORMAT_XBGR8888:
15524         case DRM_FORMAT_XRGB2101010:
15525         case DRM_FORMAT_XBGR2101010:
15526                 if (INTEL_INFO(dev)->gen < 4) {
15527                         DRM_DEBUG("unsupported pixel format: %s\n",
15528                                   drm_get_format_name(mode_cmd->pixel_format));
15529                         return -EINVAL;
15530                 }
15531                 break;
15532         case DRM_FORMAT_ABGR2101010:
15533                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15534                         DRM_DEBUG("unsupported pixel format: %s\n",
15535                                   drm_get_format_name(mode_cmd->pixel_format));
15536                         return -EINVAL;
15537                 }
15538                 break;
15539         case DRM_FORMAT_YUYV:
15540         case DRM_FORMAT_UYVY:
15541         case DRM_FORMAT_YVYU:
15542         case DRM_FORMAT_VYUY:
15543                 if (INTEL_INFO(dev)->gen < 5) {
15544                         DRM_DEBUG("unsupported pixel format: %s\n",
15545                                   drm_get_format_name(mode_cmd->pixel_format));
15546                         return -EINVAL;
15547                 }
15548                 break;
15549         default:
15550                 DRM_DEBUG("unsupported pixel format: %s\n",
15551                           drm_get_format_name(mode_cmd->pixel_format));
15552                 return -EINVAL;
15553         }
15554
15555         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15556         if (mode_cmd->offsets[0] != 0)
15557                 return -EINVAL;
15558
15559         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15560         intel_fb->obj = obj;
15561
15562         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15563         if (ret)
15564                 return ret;
15565
15566         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15567         if (ret) {
15568                 DRM_ERROR("framebuffer init failed %d\n", ret);
15569                 return ret;
15570         }
15571
15572         intel_fb->obj->framebuffer_references++;
15573
15574         return 0;
15575 }
15576
15577 static struct drm_framebuffer *
15578 intel_user_framebuffer_create(struct drm_device *dev,
15579                               struct drm_file *filp,
15580                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
15581 {
15582         struct drm_framebuffer *fb;
15583         struct drm_i915_gem_object *obj;
15584         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15585
15586         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15587         if (!obj)
15588                 return ERR_PTR(-ENOENT);
15589
15590         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15591         if (IS_ERR(fb))
15592                 i915_gem_object_put_unlocked(obj);
15593
15594         return fb;
15595 }
15596
15597 #ifndef CONFIG_DRM_FBDEV_EMULATION
15598 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15599 {
15600 }
15601 #endif
15602
15603 static const struct drm_mode_config_funcs intel_mode_funcs = {
15604         .fb_create = intel_user_framebuffer_create,
15605         .output_poll_changed = intel_fbdev_output_poll_changed,
15606         .atomic_check = intel_atomic_check,
15607         .atomic_commit = intel_atomic_commit,
15608         .atomic_state_alloc = intel_atomic_state_alloc,
15609         .atomic_state_clear = intel_atomic_state_clear,
15610 };
15611
15612 /**
15613  * intel_init_display_hooks - initialize the display modesetting hooks
15614  * @dev_priv: device private
15615  */
15616 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15617 {
15618         if (INTEL_INFO(dev_priv)->gen >= 9) {
15619                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15620                 dev_priv->display.get_initial_plane_config =
15621                         skylake_get_initial_plane_config;
15622                 dev_priv->display.crtc_compute_clock =
15623                         haswell_crtc_compute_clock;
15624                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15625                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15626         } else if (HAS_DDI(dev_priv)) {
15627                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15628                 dev_priv->display.get_initial_plane_config =
15629                         ironlake_get_initial_plane_config;
15630                 dev_priv->display.crtc_compute_clock =
15631                         haswell_crtc_compute_clock;
15632                 dev_priv->display.crtc_enable = haswell_crtc_enable;
15633                 dev_priv->display.crtc_disable = haswell_crtc_disable;
15634         } else if (HAS_PCH_SPLIT(dev_priv)) {
15635                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15636                 dev_priv->display.get_initial_plane_config =
15637                         ironlake_get_initial_plane_config;
15638                 dev_priv->display.crtc_compute_clock =
15639                         ironlake_crtc_compute_clock;
15640                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15641                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15642         } else if (IS_CHERRYVIEW(dev_priv)) {
15643                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15644                 dev_priv->display.get_initial_plane_config =
15645                         i9xx_get_initial_plane_config;
15646                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15647                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15648                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15649         } else if (IS_VALLEYVIEW(dev_priv)) {
15650                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15651                 dev_priv->display.get_initial_plane_config =
15652                         i9xx_get_initial_plane_config;
15653                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15654                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15655                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15656         } else if (IS_G4X(dev_priv)) {
15657                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15658                 dev_priv->display.get_initial_plane_config =
15659                         i9xx_get_initial_plane_config;
15660                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15661                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15662                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15663         } else if (IS_PINEVIEW(dev_priv)) {
15664                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15665                 dev_priv->display.get_initial_plane_config =
15666                         i9xx_get_initial_plane_config;
15667                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15668                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15669                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15670         } else if (!IS_GEN2(dev_priv)) {
15671                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15672                 dev_priv->display.get_initial_plane_config =
15673                         i9xx_get_initial_plane_config;
15674                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15675                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15676                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15677         } else {
15678                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15679                 dev_priv->display.get_initial_plane_config =
15680                         i9xx_get_initial_plane_config;
15681                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15682                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15683                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15684         }
15685
15686         /* Returns the core display clock speed */
15687         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15688                 dev_priv->display.get_display_clock_speed =
15689                         skylake_get_display_clock_speed;
15690         else if (IS_BROXTON(dev_priv))
15691                 dev_priv->display.get_display_clock_speed =
15692                         broxton_get_display_clock_speed;
15693         else if (IS_BROADWELL(dev_priv))
15694                 dev_priv->display.get_display_clock_speed =
15695                         broadwell_get_display_clock_speed;
15696         else if (IS_HASWELL(dev_priv))
15697                 dev_priv->display.get_display_clock_speed =
15698                         haswell_get_display_clock_speed;
15699         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15700                 dev_priv->display.get_display_clock_speed =
15701                         valleyview_get_display_clock_speed;
15702         else if (IS_GEN5(dev_priv))
15703                 dev_priv->display.get_display_clock_speed =
15704                         ilk_get_display_clock_speed;
15705         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15706                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15707                 dev_priv->display.get_display_clock_speed =
15708                         i945_get_display_clock_speed;
15709         else if (IS_GM45(dev_priv))
15710                 dev_priv->display.get_display_clock_speed =
15711                         gm45_get_display_clock_speed;
15712         else if (IS_CRESTLINE(dev_priv))
15713                 dev_priv->display.get_display_clock_speed =
15714                         i965gm_get_display_clock_speed;
15715         else if (IS_PINEVIEW(dev_priv))
15716                 dev_priv->display.get_display_clock_speed =
15717                         pnv_get_display_clock_speed;
15718         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15719                 dev_priv->display.get_display_clock_speed =
15720                         g33_get_display_clock_speed;
15721         else if (IS_I915G(dev_priv))
15722                 dev_priv->display.get_display_clock_speed =
15723                         i915_get_display_clock_speed;
15724         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15725                 dev_priv->display.get_display_clock_speed =
15726                         i9xx_misc_get_display_clock_speed;
15727         else if (IS_I915GM(dev_priv))
15728                 dev_priv->display.get_display_clock_speed =
15729                         i915gm_get_display_clock_speed;
15730         else if (IS_I865G(dev_priv))
15731                 dev_priv->display.get_display_clock_speed =
15732                         i865_get_display_clock_speed;
15733         else if (IS_I85X(dev_priv))
15734                 dev_priv->display.get_display_clock_speed =
15735                         i85x_get_display_clock_speed;
15736         else { /* 830 */
15737                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15738                 dev_priv->display.get_display_clock_speed =
15739                         i830_get_display_clock_speed;
15740         }
15741
15742         if (IS_GEN5(dev_priv)) {
15743                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15744         } else if (IS_GEN6(dev_priv)) {
15745                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15746         } else if (IS_IVYBRIDGE(dev_priv)) {
15747                 /* FIXME: detect B0+ stepping and use auto training */
15748                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15749         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15750                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15751         }
15752
15753         if (IS_BROADWELL(dev_priv)) {
15754                 dev_priv->display.modeset_commit_cdclk =
15755                         broadwell_modeset_commit_cdclk;
15756                 dev_priv->display.modeset_calc_cdclk =
15757                         broadwell_modeset_calc_cdclk;
15758         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15759                 dev_priv->display.modeset_commit_cdclk =
15760                         valleyview_modeset_commit_cdclk;
15761                 dev_priv->display.modeset_calc_cdclk =
15762                         valleyview_modeset_calc_cdclk;
15763         } else if (IS_BROXTON(dev_priv)) {
15764                 dev_priv->display.modeset_commit_cdclk =
15765                         bxt_modeset_commit_cdclk;
15766                 dev_priv->display.modeset_calc_cdclk =
15767                         bxt_modeset_calc_cdclk;
15768         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15769                 dev_priv->display.modeset_commit_cdclk =
15770                         skl_modeset_commit_cdclk;
15771                 dev_priv->display.modeset_calc_cdclk =
15772                         skl_modeset_calc_cdclk;
15773         }
15774
15775         switch (INTEL_INFO(dev_priv)->gen) {
15776         case 2:
15777                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15778                 break;
15779
15780         case 3:
15781                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15782                 break;
15783
15784         case 4:
15785         case 5:
15786                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15787                 break;
15788
15789         case 6:
15790                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15791                 break;
15792         case 7:
15793         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15794                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15795                 break;
15796         case 9:
15797                 /* Drop through - unsupported since execlist only. */
15798         default:
15799                 /* Default just returns -ENODEV to indicate unsupported */
15800                 dev_priv->display.queue_flip = intel_default_queue_flip;
15801         }
15802 }
15803
15804 /*
15805  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15806  * resume, or other times.  This quirk makes sure that's the case for
15807  * affected systems.
15808  */
15809 static void quirk_pipea_force(struct drm_device *dev)
15810 {
15811         struct drm_i915_private *dev_priv = to_i915(dev);
15812
15813         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15814         DRM_INFO("applying pipe a force quirk\n");
15815 }
15816
15817 static void quirk_pipeb_force(struct drm_device *dev)
15818 {
15819         struct drm_i915_private *dev_priv = to_i915(dev);
15820
15821         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15822         DRM_INFO("applying pipe b force quirk\n");
15823 }
15824
15825 /*
15826  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15827  */
15828 static void quirk_ssc_force_disable(struct drm_device *dev)
15829 {
15830         struct drm_i915_private *dev_priv = to_i915(dev);
15831         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15832         DRM_INFO("applying lvds SSC disable quirk\n");
15833 }
15834
15835 /*
15836  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15837  * brightness value
15838  */
15839 static void quirk_invert_brightness(struct drm_device *dev)
15840 {
15841         struct drm_i915_private *dev_priv = to_i915(dev);
15842         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15843         DRM_INFO("applying inverted panel brightness quirk\n");
15844 }
15845
15846 /* Some VBT's incorrectly indicate no backlight is present */
15847 static void quirk_backlight_present(struct drm_device *dev)
15848 {
15849         struct drm_i915_private *dev_priv = to_i915(dev);
15850         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15851         DRM_INFO("applying backlight present quirk\n");
15852 }
15853
15854 struct intel_quirk {
15855         int device;
15856         int subsystem_vendor;
15857         int subsystem_device;
15858         void (*hook)(struct drm_device *dev);
15859 };
15860
15861 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15862 struct intel_dmi_quirk {
15863         void (*hook)(struct drm_device *dev);
15864         const struct dmi_system_id (*dmi_id_list)[];
15865 };
15866
15867 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15868 {
15869         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15870         return 1;
15871 }
15872
15873 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15874         {
15875                 .dmi_id_list = &(const struct dmi_system_id[]) {
15876                         {
15877                                 .callback = intel_dmi_reverse_brightness,
15878                                 .ident = "NCR Corporation",
15879                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15880                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15881                                 },
15882                         },
15883                         { }  /* terminating entry */
15884                 },
15885                 .hook = quirk_invert_brightness,
15886         },
15887 };
15888
15889 static struct intel_quirk intel_quirks[] = {
15890         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15891         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15892
15893         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15894         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15895
15896         /* 830 needs to leave pipe A & dpll A up */
15897         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15898
15899         /* 830 needs to leave pipe B & dpll B up */
15900         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15901
15902         /* Lenovo U160 cannot use SSC on LVDS */
15903         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15904
15905         /* Sony Vaio Y cannot use SSC on LVDS */
15906         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15907
15908         /* Acer Aspire 5734Z must invert backlight brightness */
15909         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15910
15911         /* Acer/eMachines G725 */
15912         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15913
15914         /* Acer/eMachines e725 */
15915         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15916
15917         /* Acer/Packard Bell NCL20 */
15918         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15919
15920         /* Acer Aspire 4736Z */
15921         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15922
15923         /* Acer Aspire 5336 */
15924         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15925
15926         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15927         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15928
15929         /* Acer C720 Chromebook (Core i3 4005U) */
15930         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15931
15932         /* Apple Macbook 2,1 (Core 2 T7400) */
15933         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15934
15935         /* Apple Macbook 4,1 */
15936         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15937
15938         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15939         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15940
15941         /* HP Chromebook 14 (Celeron 2955U) */
15942         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15943
15944         /* Dell Chromebook 11 */
15945         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15946
15947         /* Dell Chromebook 11 (2015 version) */
15948         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15949 };
15950
15951 static void intel_init_quirks(struct drm_device *dev)
15952 {
15953         struct pci_dev *d = dev->pdev;
15954         int i;
15955
15956         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15957                 struct intel_quirk *q = &intel_quirks[i];
15958
15959                 if (d->device == q->device &&
15960                     (d->subsystem_vendor == q->subsystem_vendor ||
15961                      q->subsystem_vendor == PCI_ANY_ID) &&
15962                     (d->subsystem_device == q->subsystem_device ||
15963                      q->subsystem_device == PCI_ANY_ID))
15964                         q->hook(dev);
15965         }
15966         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15967                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15968                         intel_dmi_quirks[i].hook(dev);
15969         }
15970 }
15971
15972 /* Disable the VGA plane that we never use */
15973 static void i915_disable_vga(struct drm_device *dev)
15974 {
15975         struct drm_i915_private *dev_priv = to_i915(dev);
15976         u8 sr1;
15977         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15978
15979         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15980         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15981         outb(SR01, VGA_SR_INDEX);
15982         sr1 = inb(VGA_SR_DATA);
15983         outb(sr1 | 1<<5, VGA_SR_DATA);
15984         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15985         udelay(300);
15986
15987         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15988         POSTING_READ(vga_reg);
15989 }
15990
15991 void intel_modeset_init_hw(struct drm_device *dev)
15992 {
15993         struct drm_i915_private *dev_priv = to_i915(dev);
15994
15995         intel_update_cdclk(dev);
15996
15997         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15998
15999         intel_init_clock_gating(dev);
16000 }
16001
16002 /*
16003  * Calculate what we think the watermarks should be for the state we've read
16004  * out of the hardware and then immediately program those watermarks so that
16005  * we ensure the hardware settings match our internal state.
16006  *
16007  * We can calculate what we think WM's should be by creating a duplicate of the
16008  * current state (which was constructed during hardware readout) and running it
16009  * through the atomic check code to calculate new watermark values in the
16010  * state object.
16011  */
16012 static void sanitize_watermarks(struct drm_device *dev)
16013 {
16014         struct drm_i915_private *dev_priv = to_i915(dev);
16015         struct drm_atomic_state *state;
16016         struct drm_crtc *crtc;
16017         struct drm_crtc_state *cstate;
16018         struct drm_modeset_acquire_ctx ctx;
16019         int ret;
16020         int i;
16021
16022         /* Only supported on platforms that use atomic watermark design */
16023         if (!dev_priv->display.optimize_watermarks)
16024                 return;
16025
16026         /*
16027          * We need to hold connection_mutex before calling duplicate_state so
16028          * that the connector loop is protected.
16029          */
16030         drm_modeset_acquire_init(&ctx, 0);
16031 retry:
16032         ret = drm_modeset_lock_all_ctx(dev, &ctx);
16033         if (ret == -EDEADLK) {
16034                 drm_modeset_backoff(&ctx);
16035                 goto retry;
16036         } else if (WARN_ON(ret)) {
16037                 goto fail;
16038         }
16039
16040         state = drm_atomic_helper_duplicate_state(dev, &ctx);
16041         if (WARN_ON(IS_ERR(state)))
16042                 goto fail;
16043
16044         /*
16045          * Hardware readout is the only time we don't want to calculate
16046          * intermediate watermarks (since we don't trust the current
16047          * watermarks).
16048          */
16049         to_intel_atomic_state(state)->skip_intermediate_wm = true;
16050
16051         ret = intel_atomic_check(dev, state);
16052         if (ret) {
16053                 /*
16054                  * If we fail here, it means that the hardware appears to be
16055                  * programmed in a way that shouldn't be possible, given our
16056                  * understanding of watermark requirements.  This might mean a
16057                  * mistake in the hardware readout code or a mistake in the
16058                  * watermark calculations for a given platform.  Raise a WARN
16059                  * so that this is noticeable.
16060                  *
16061                  * If this actually happens, we'll have to just leave the
16062                  * BIOS-programmed watermarks untouched and hope for the best.
16063                  */
16064                 WARN(true, "Could not determine valid watermarks for inherited state\n");
16065                 goto fail;
16066         }
16067
16068         /* Write calculated watermark values back */
16069         for_each_crtc_in_state(state, crtc, cstate, i) {
16070                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16071
16072                 cs->wm.need_postvbl_update = true;
16073                 dev_priv->display.optimize_watermarks(cs);
16074         }
16075
16076         drm_atomic_state_free(state);
16077 fail:
16078         drm_modeset_drop_locks(&ctx);
16079         drm_modeset_acquire_fini(&ctx);
16080 }
16081
16082 void intel_modeset_init(struct drm_device *dev)
16083 {
16084         struct drm_i915_private *dev_priv = to_i915(dev);
16085         struct i915_ggtt *ggtt = &dev_priv->ggtt;
16086         int sprite, ret;
16087         enum pipe pipe;
16088         struct intel_crtc *crtc;
16089
16090         drm_mode_config_init(dev);
16091
16092         dev->mode_config.min_width = 0;
16093         dev->mode_config.min_height = 0;
16094
16095         dev->mode_config.preferred_depth = 24;
16096         dev->mode_config.prefer_shadow = 1;
16097
16098         dev->mode_config.allow_fb_modifiers = true;
16099
16100         dev->mode_config.funcs = &intel_mode_funcs;
16101
16102         intel_init_quirks(dev);
16103
16104         intel_init_pm(dev);
16105
16106         if (INTEL_INFO(dev)->num_pipes == 0)
16107                 return;
16108
16109         /*
16110          * There may be no VBT; and if the BIOS enabled SSC we can
16111          * just keep using it to avoid unnecessary flicker.  Whereas if the
16112          * BIOS isn't using it, don't assume it will work even if the VBT
16113          * indicates as much.
16114          */
16115         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16116                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16117                                             DREF_SSC1_ENABLE);
16118
16119                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16120                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16121                                      bios_lvds_use_ssc ? "en" : "dis",
16122                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16123                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16124                 }
16125         }
16126
16127         if (IS_GEN2(dev)) {
16128                 dev->mode_config.max_width = 2048;
16129                 dev->mode_config.max_height = 2048;
16130         } else if (IS_GEN3(dev)) {
16131                 dev->mode_config.max_width = 4096;
16132                 dev->mode_config.max_height = 4096;
16133         } else {
16134                 dev->mode_config.max_width = 8192;
16135                 dev->mode_config.max_height = 8192;
16136         }
16137
16138         if (IS_845G(dev) || IS_I865G(dev)) {
16139                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16140                 dev->mode_config.cursor_height = 1023;
16141         } else if (IS_GEN2(dev)) {
16142                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16143                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16144         } else {
16145                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16146                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16147         }
16148
16149         dev->mode_config.fb_base = ggtt->mappable_base;
16150
16151         DRM_DEBUG_KMS("%d display pipe%s available.\n",
16152                       INTEL_INFO(dev)->num_pipes,
16153                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16154
16155         for_each_pipe(dev_priv, pipe) {
16156                 intel_crtc_init(dev, pipe);
16157                 for_each_sprite(dev_priv, pipe, sprite) {
16158                         ret = intel_plane_init(dev, pipe, sprite);
16159                         if (ret)
16160                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16161                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
16162                 }
16163         }
16164
16165         intel_update_czclk(dev_priv);
16166         intel_update_cdclk(dev);
16167
16168         intel_shared_dpll_init(dev);
16169
16170         if (dev_priv->max_cdclk_freq == 0)
16171                 intel_update_max_cdclk(dev);
16172
16173         /* Just disable it once at startup */
16174         i915_disable_vga(dev);
16175         intel_setup_outputs(dev);
16176
16177         drm_modeset_lock_all(dev);
16178         intel_modeset_setup_hw_state(dev);
16179         drm_modeset_unlock_all(dev);
16180
16181         for_each_intel_crtc(dev, crtc) {
16182                 struct intel_initial_plane_config plane_config = {};
16183
16184                 if (!crtc->active)
16185                         continue;
16186
16187                 /*
16188                  * Note that reserving the BIOS fb up front prevents us
16189                  * from stuffing other stolen allocations like the ring
16190                  * on top.  This prevents some ugliness at boot time, and
16191                  * can even allow for smooth boot transitions if the BIOS
16192                  * fb is large enough for the active pipe configuration.
16193                  */
16194                 dev_priv->display.get_initial_plane_config(crtc,
16195                                                            &plane_config);
16196
16197                 /*
16198                  * If the fb is shared between multiple heads, we'll
16199                  * just get the first one.
16200                  */
16201                 intel_find_initial_plane_obj(crtc, &plane_config);
16202         }
16203
16204         /*
16205          * Make sure hardware watermarks really match the state we read out.
16206          * Note that we need to do this after reconstructing the BIOS fb's
16207          * since the watermark calculation done here will use pstate->fb.
16208          */
16209         sanitize_watermarks(dev);
16210 }
16211
16212 static void intel_enable_pipe_a(struct drm_device *dev)
16213 {
16214         struct intel_connector *connector;
16215         struct drm_connector *crt = NULL;
16216         struct intel_load_detect_pipe load_detect_temp;
16217         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16218
16219         /* We can't just switch on the pipe A, we need to set things up with a
16220          * proper mode and output configuration. As a gross hack, enable pipe A
16221          * by enabling the load detect pipe once. */
16222         for_each_intel_connector(dev, connector) {
16223                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16224                         crt = &connector->base;
16225                         break;
16226                 }
16227         }
16228
16229         if (!crt)
16230                 return;
16231
16232         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16233                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16234 }
16235
16236 static bool
16237 intel_check_plane_mapping(struct intel_crtc *crtc)
16238 {
16239         struct drm_device *dev = crtc->base.dev;
16240         struct drm_i915_private *dev_priv = to_i915(dev);
16241         u32 val;
16242
16243         if (INTEL_INFO(dev)->num_pipes == 1)
16244                 return true;
16245
16246         val = I915_READ(DSPCNTR(!crtc->plane));
16247
16248         if ((val & DISPLAY_PLANE_ENABLE) &&
16249             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16250                 return false;
16251
16252         return true;
16253 }
16254
16255 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16256 {
16257         struct drm_device *dev = crtc->base.dev;
16258         struct intel_encoder *encoder;
16259
16260         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16261                 return true;
16262
16263         return false;
16264 }
16265
16266 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
16267 {
16268         struct drm_device *dev = encoder->base.dev;
16269         struct intel_connector *connector;
16270
16271         for_each_connector_on_encoder(dev, &encoder->base, connector)
16272                 return true;
16273
16274         return false;
16275 }
16276
16277 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16278                               enum transcoder pch_transcoder)
16279 {
16280         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16281                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16282 }
16283
16284 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16285 {
16286         struct drm_device *dev = crtc->base.dev;
16287         struct drm_i915_private *dev_priv = to_i915(dev);
16288         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16289
16290         /* Clear any frame start delays used for debugging left by the BIOS */
16291         if (!transcoder_is_dsi(cpu_transcoder)) {
16292                 i915_reg_t reg = PIPECONF(cpu_transcoder);
16293
16294                 I915_WRITE(reg,
16295                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16296         }
16297
16298         /* restore vblank interrupts to correct state */
16299         drm_crtc_vblank_reset(&crtc->base);
16300         if (crtc->active) {
16301                 struct intel_plane *plane;
16302
16303                 drm_crtc_vblank_on(&crtc->base);
16304
16305                 /* Disable everything but the primary plane */
16306                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16307                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16308                                 continue;
16309
16310                         plane->disable_plane(&plane->base, &crtc->base);
16311                 }
16312         }
16313
16314         /* We need to sanitize the plane -> pipe mapping first because this will
16315          * disable the crtc (and hence change the state) if it is wrong. Note
16316          * that gen4+ has a fixed plane -> pipe mapping.  */
16317         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16318                 bool plane;
16319
16320                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16321                               crtc->base.base.id, crtc->base.name);
16322
16323                 /* Pipe has the wrong plane attached and the plane is active.
16324                  * Temporarily change the plane mapping and disable everything
16325                  * ...  */
16326                 plane = crtc->plane;
16327                 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16328                 crtc->plane = !plane;
16329                 intel_crtc_disable_noatomic(&crtc->base);
16330                 crtc->plane = plane;
16331         }
16332
16333         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16334             crtc->pipe == PIPE_A && !crtc->active) {
16335                 /* BIOS forgot to enable pipe A, this mostly happens after
16336                  * resume. Force-enable the pipe to fix this, the update_dpms
16337                  * call below we restore the pipe to the right state, but leave
16338                  * the required bits on. */
16339                 intel_enable_pipe_a(dev);
16340         }
16341
16342         /* Adjust the state of the output pipe according to whether we
16343          * have active connectors/encoders. */
16344         if (crtc->active && !intel_crtc_has_encoders(crtc))
16345                 intel_crtc_disable_noatomic(&crtc->base);
16346
16347         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16348                 /*
16349                  * We start out with underrun reporting disabled to avoid races.
16350                  * For correct bookkeeping mark this on active crtcs.
16351                  *
16352                  * Also on gmch platforms we dont have any hardware bits to
16353                  * disable the underrun reporting. Which means we need to start
16354                  * out with underrun reporting disabled also on inactive pipes,
16355                  * since otherwise we'll complain about the garbage we read when
16356                  * e.g. coming up after runtime pm.
16357                  *
16358                  * No protection against concurrent access is required - at
16359                  * worst a fifo underrun happens which also sets this to false.
16360                  */
16361                 crtc->cpu_fifo_underrun_disabled = true;
16362                 /*
16363                  * We track the PCH trancoder underrun reporting state
16364                  * within the crtc. With crtc for pipe A housing the underrun
16365                  * reporting state for PCH transcoder A, crtc for pipe B housing
16366                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16367                  * and marking underrun reporting as disabled for the non-existing
16368                  * PCH transcoders B and C would prevent enabling the south
16369                  * error interrupt (see cpt_can_enable_serr_int()).
16370                  */
16371                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16372                         crtc->pch_fifo_underrun_disabled = true;
16373         }
16374 }
16375
16376 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16377 {
16378         struct intel_connector *connector;
16379         struct drm_device *dev = encoder->base.dev;
16380
16381         /* We need to check both for a crtc link (meaning that the
16382          * encoder is active and trying to read from a pipe) and the
16383          * pipe itself being active. */
16384         bool has_active_crtc = encoder->base.crtc &&
16385                 to_intel_crtc(encoder->base.crtc)->active;
16386
16387         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
16388                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16389                               encoder->base.base.id,
16390                               encoder->base.name);
16391
16392                 /* Connector is active, but has no active pipe. This is
16393                  * fallout from our resume register restoring. Disable
16394                  * the encoder manually again. */
16395                 if (encoder->base.crtc) {
16396                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16397                                       encoder->base.base.id,
16398                                       encoder->base.name);
16399                         encoder->disable(encoder);
16400                         if (encoder->post_disable)
16401                                 encoder->post_disable(encoder);
16402                 }
16403                 encoder->base.crtc = NULL;
16404
16405                 /* Inconsistent output/port/pipe state happens presumably due to
16406                  * a bug in one of the get_hw_state functions. Or someplace else
16407                  * in our code, like the register restore mess on resume. Clamp
16408                  * things to off as a safer default. */
16409                 for_each_intel_connector(dev, connector) {
16410                         if (connector->encoder != encoder)
16411                                 continue;
16412                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16413                         connector->base.encoder = NULL;
16414                 }
16415         }
16416         /* Enabled encoders without active connectors will be fixed in
16417          * the crtc fixup. */
16418 }
16419
16420 void i915_redisable_vga_power_on(struct drm_device *dev)
16421 {
16422         struct drm_i915_private *dev_priv = to_i915(dev);
16423         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16424
16425         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16426                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16427                 i915_disable_vga(dev);
16428         }
16429 }
16430
16431 void i915_redisable_vga(struct drm_device *dev)
16432 {
16433         struct drm_i915_private *dev_priv = to_i915(dev);
16434
16435         /* This function can be called both from intel_modeset_setup_hw_state or
16436          * at a very early point in our resume sequence, where the power well
16437          * structures are not yet restored. Since this function is at a very
16438          * paranoid "someone might have enabled VGA while we were not looking"
16439          * level, just check if the power well is enabled instead of trying to
16440          * follow the "don't touch the power well if we don't need it" policy
16441          * the rest of the driver uses. */
16442         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16443                 return;
16444
16445         i915_redisable_vga_power_on(dev);
16446
16447         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16448 }
16449
16450 static bool primary_get_hw_state(struct intel_plane *plane)
16451 {
16452         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16453
16454         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16455 }
16456
16457 /* FIXME read out full plane state for all planes */
16458 static void readout_plane_state(struct intel_crtc *crtc)
16459 {
16460         struct drm_plane *primary = crtc->base.primary;
16461         struct intel_plane_state *plane_state =
16462                 to_intel_plane_state(primary->state);
16463
16464         plane_state->base.visible = crtc->active &&
16465                 primary_get_hw_state(to_intel_plane(primary));
16466
16467         if (plane_state->base.visible)
16468                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16469 }
16470
16471 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16472 {
16473         struct drm_i915_private *dev_priv = to_i915(dev);
16474         enum pipe pipe;
16475         struct intel_crtc *crtc;
16476         struct intel_encoder *encoder;
16477         struct intel_connector *connector;
16478         int i;
16479
16480         dev_priv->active_crtcs = 0;
16481
16482         for_each_intel_crtc(dev, crtc) {
16483                 struct intel_crtc_state *crtc_state = crtc->config;
16484                 int pixclk = 0;
16485
16486                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16487                 memset(crtc_state, 0, sizeof(*crtc_state));
16488                 crtc_state->base.crtc = &crtc->base;
16489
16490                 crtc_state->base.active = crtc_state->base.enable =
16491                         dev_priv->display.get_pipe_config(crtc, crtc_state);
16492
16493                 crtc->base.enabled = crtc_state->base.enable;
16494                 crtc->active = crtc_state->base.active;
16495
16496                 if (crtc_state->base.active) {
16497                         dev_priv->active_crtcs |= 1 << crtc->pipe;
16498
16499                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16500                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
16501                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16502                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16503                         else
16504                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16505
16506                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16507                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16508                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16509                 }
16510
16511                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16512
16513                 readout_plane_state(crtc);
16514
16515                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16516                               crtc->base.base.id, crtc->base.name,
16517                               crtc->active ? "enabled" : "disabled");
16518         }
16519
16520         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16521                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16522
16523                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16524                                                   &pll->config.hw_state);
16525                 pll->config.crtc_mask = 0;
16526                 for_each_intel_crtc(dev, crtc) {
16527                         if (crtc->active && crtc->config->shared_dpll == pll)
16528                                 pll->config.crtc_mask |= 1 << crtc->pipe;
16529                 }
16530                 pll->active_mask = pll->config.crtc_mask;
16531
16532                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16533                               pll->name, pll->config.crtc_mask, pll->on);
16534         }
16535
16536         for_each_intel_encoder(dev, encoder) {
16537                 pipe = 0;
16538
16539                 if (encoder->get_hw_state(encoder, &pipe)) {
16540                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16541                         encoder->base.crtc = &crtc->base;
16542                         crtc->config->output_types |= 1 << encoder->type;
16543                         encoder->get_config(encoder, crtc->config);
16544                 } else {
16545                         encoder->base.crtc = NULL;
16546                 }
16547
16548                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16549                               encoder->base.base.id,
16550                               encoder->base.name,
16551                               encoder->base.crtc ? "enabled" : "disabled",
16552                               pipe_name(pipe));
16553         }
16554
16555         for_each_intel_connector(dev, connector) {
16556                 if (connector->get_hw_state(connector)) {
16557                         connector->base.dpms = DRM_MODE_DPMS_ON;
16558
16559                         encoder = connector->encoder;
16560                         connector->base.encoder = &encoder->base;
16561
16562                         if (encoder->base.crtc &&
16563                             encoder->base.crtc->state->active) {
16564                                 /*
16565                                  * This has to be done during hardware readout
16566                                  * because anything calling .crtc_disable may
16567                                  * rely on the connector_mask being accurate.
16568                                  */
16569                                 encoder->base.crtc->state->connector_mask |=
16570                                         1 << drm_connector_index(&connector->base);
16571                                 encoder->base.crtc->state->encoder_mask |=
16572                                         1 << drm_encoder_index(&encoder->base);
16573                         }
16574
16575                 } else {
16576                         connector->base.dpms = DRM_MODE_DPMS_OFF;
16577                         connector->base.encoder = NULL;
16578                 }
16579                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16580                               connector->base.base.id,
16581                               connector->base.name,
16582                               connector->base.encoder ? "enabled" : "disabled");
16583         }
16584
16585         for_each_intel_crtc(dev, crtc) {
16586                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16587
16588                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16589                 if (crtc->base.state->active) {
16590                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16591                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16592                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16593
16594                         /*
16595                          * The initial mode needs to be set in order to keep
16596                          * the atomic core happy. It wants a valid mode if the
16597                          * crtc's enabled, so we do the above call.
16598                          *
16599                          * At this point some state updated by the connectors
16600                          * in their ->detect() callback has not run yet, so
16601                          * no recalculation can be done yet.
16602                          *
16603                          * Even if we could do a recalculation and modeset
16604                          * right now it would cause a double modeset if
16605                          * fbdev or userspace chooses a different initial mode.
16606                          *
16607                          * If that happens, someone indicated they wanted a
16608                          * mode change, which means it's safe to do a full
16609                          * recalculation.
16610                          */
16611                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16612
16613                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16614                         update_scanline_offset(crtc);
16615                 }
16616
16617                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16618         }
16619 }
16620
16621 /* Scan out the current hw modeset state,
16622  * and sanitizes it to the current state
16623  */
16624 static void
16625 intel_modeset_setup_hw_state(struct drm_device *dev)
16626 {
16627         struct drm_i915_private *dev_priv = to_i915(dev);
16628         enum pipe pipe;
16629         struct intel_crtc *crtc;
16630         struct intel_encoder *encoder;
16631         int i;
16632
16633         intel_modeset_readout_hw_state(dev);
16634
16635         /* HW state is read out, now we need to sanitize this mess. */
16636         for_each_intel_encoder(dev, encoder) {
16637                 intel_sanitize_encoder(encoder);
16638         }
16639
16640         for_each_pipe(dev_priv, pipe) {
16641                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16642                 intel_sanitize_crtc(crtc);
16643                 intel_dump_pipe_config(crtc, crtc->config,
16644                                        "[setup_hw_state]");
16645         }
16646
16647         intel_modeset_update_connector_atomic_state(dev);
16648
16649         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16650                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16651
16652                 if (!pll->on || pll->active_mask)
16653                         continue;
16654
16655                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16656
16657                 pll->funcs.disable(dev_priv, pll);
16658                 pll->on = false;
16659         }
16660
16661         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16662                 vlv_wm_get_hw_state(dev);
16663         else if (IS_GEN9(dev))
16664                 skl_wm_get_hw_state(dev);
16665         else if (HAS_PCH_SPLIT(dev))
16666                 ilk_wm_get_hw_state(dev);
16667
16668         for_each_intel_crtc(dev, crtc) {
16669                 unsigned long put_domains;
16670
16671                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16672                 if (WARN_ON(put_domains))
16673                         modeset_put_power_domains(dev_priv, put_domains);
16674         }
16675         intel_display_set_init_power(dev_priv, false);
16676
16677         intel_fbc_init_pipe_state(dev_priv);
16678 }
16679
16680 void intel_display_resume(struct drm_device *dev)
16681 {
16682         struct drm_i915_private *dev_priv = to_i915(dev);
16683         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16684         struct drm_modeset_acquire_ctx ctx;
16685         int ret;
16686
16687         dev_priv->modeset_restore_state = NULL;
16688         if (state)
16689                 state->acquire_ctx = &ctx;
16690
16691         /*
16692          * This is a cludge because with real atomic modeset mode_config.mutex
16693          * won't be taken. Unfortunately some probed state like
16694          * audio_codec_enable is still protected by mode_config.mutex, so lock
16695          * it here for now.
16696          */
16697         mutex_lock(&dev->mode_config.mutex);
16698         drm_modeset_acquire_init(&ctx, 0);
16699
16700         while (1) {
16701                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16702                 if (ret != -EDEADLK)
16703                         break;
16704
16705                 drm_modeset_backoff(&ctx);
16706         }
16707
16708         if (!ret)
16709                 ret = __intel_display_resume(dev, state);
16710
16711         drm_modeset_drop_locks(&ctx);
16712         drm_modeset_acquire_fini(&ctx);
16713         mutex_unlock(&dev->mode_config.mutex);
16714
16715         if (ret) {
16716                 DRM_ERROR("Restoring old state failed with %i\n", ret);
16717                 drm_atomic_state_free(state);
16718         }
16719 }
16720
16721 void intel_modeset_gem_init(struct drm_device *dev)
16722 {
16723         struct drm_i915_private *dev_priv = to_i915(dev);
16724         struct drm_crtc *c;
16725         struct drm_i915_gem_object *obj;
16726         int ret;
16727
16728         intel_init_gt_powersave(dev_priv);
16729
16730         intel_modeset_init_hw(dev);
16731
16732         intel_setup_overlay(dev_priv);
16733
16734         /*
16735          * Make sure any fbs we allocated at startup are properly
16736          * pinned & fenced.  When we do the allocation it's too early
16737          * for this.
16738          */
16739         for_each_crtc(dev, c) {
16740                 obj = intel_fb_obj(c->primary->fb);
16741                 if (obj == NULL)
16742                         continue;
16743
16744                 mutex_lock(&dev->struct_mutex);
16745                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16746                                                  c->primary->state->rotation);
16747                 mutex_unlock(&dev->struct_mutex);
16748                 if (ret) {
16749                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
16750                                   to_intel_crtc(c)->pipe);
16751                         drm_framebuffer_unreference(c->primary->fb);
16752                         c->primary->fb = NULL;
16753                         c->primary->crtc = c->primary->state->crtc = NULL;
16754                         update_state_fb(c->primary);
16755                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16756                 }
16757         }
16758 }
16759
16760 int intel_connector_register(struct drm_connector *connector)
16761 {
16762         struct intel_connector *intel_connector = to_intel_connector(connector);
16763         int ret;
16764
16765         ret = intel_backlight_device_register(intel_connector);
16766         if (ret)
16767                 goto err;
16768
16769         return 0;
16770
16771 err:
16772         return ret;
16773 }
16774
16775 void intel_connector_unregister(struct drm_connector *connector)
16776 {
16777         struct intel_connector *intel_connector = to_intel_connector(connector);
16778
16779         intel_backlight_device_unregister(intel_connector);
16780         intel_panel_destroy_backlight(connector);
16781 }
16782
16783 void intel_modeset_cleanup(struct drm_device *dev)
16784 {
16785         struct drm_i915_private *dev_priv = to_i915(dev);
16786
16787         intel_disable_gt_powersave(dev_priv);
16788
16789         /*
16790          * Interrupts and polling as the first thing to avoid creating havoc.
16791          * Too much stuff here (turning of connectors, ...) would
16792          * experience fancy races otherwise.
16793          */
16794         intel_irq_uninstall(dev_priv);
16795
16796         /*
16797          * Due to the hpd irq storm handling the hotplug work can re-arm the
16798          * poll handlers. Hence disable polling after hpd handling is shut down.
16799          */
16800         drm_kms_helper_poll_fini(dev);
16801
16802         intel_unregister_dsm_handler();
16803
16804         intel_fbc_global_disable(dev_priv);
16805
16806         /* flush any delayed tasks or pending work */
16807         flush_scheduled_work();
16808
16809         drm_mode_config_cleanup(dev);
16810
16811         intel_cleanup_overlay(dev_priv);
16812
16813         intel_cleanup_gt_powersave(dev_priv);
16814
16815         intel_teardown_gmbus(dev);
16816 }
16817
16818 void intel_connector_attach_encoder(struct intel_connector *connector,
16819                                     struct intel_encoder *encoder)
16820 {
16821         connector->encoder = encoder;
16822         drm_mode_connector_attach_encoder(&connector->base,
16823                                           &encoder->base);
16824 }
16825
16826 /*
16827  * set vga decode state - true == enable VGA decode
16828  */
16829 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16830 {
16831         struct drm_i915_private *dev_priv = to_i915(dev);
16832         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16833         u16 gmch_ctrl;
16834
16835         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16836                 DRM_ERROR("failed to read control word\n");
16837                 return -EIO;
16838         }
16839
16840         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16841                 return 0;
16842
16843         if (state)
16844                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16845         else
16846                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16847
16848         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16849                 DRM_ERROR("failed to write control word\n");
16850                 return -EIO;
16851         }
16852
16853         return 0;
16854 }
16855
16856 struct intel_display_error_state {
16857
16858         u32 power_well_driver;
16859
16860         int num_transcoders;
16861
16862         struct intel_cursor_error_state {
16863                 u32 control;
16864                 u32 position;
16865                 u32 base;
16866                 u32 size;
16867         } cursor[I915_MAX_PIPES];
16868
16869         struct intel_pipe_error_state {
16870                 bool power_domain_on;
16871                 u32 source;
16872                 u32 stat;
16873         } pipe[I915_MAX_PIPES];
16874
16875         struct intel_plane_error_state {
16876                 u32 control;
16877                 u32 stride;
16878                 u32 size;
16879                 u32 pos;
16880                 u32 addr;
16881                 u32 surface;
16882                 u32 tile_offset;
16883         } plane[I915_MAX_PIPES];
16884
16885         struct intel_transcoder_error_state {
16886                 bool power_domain_on;
16887                 enum transcoder cpu_transcoder;
16888
16889                 u32 conf;
16890
16891                 u32 htotal;
16892                 u32 hblank;
16893                 u32 hsync;
16894                 u32 vtotal;
16895                 u32 vblank;
16896                 u32 vsync;
16897         } transcoder[4];
16898 };
16899
16900 struct intel_display_error_state *
16901 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16902 {
16903         struct intel_display_error_state *error;
16904         int transcoders[] = {
16905                 TRANSCODER_A,
16906                 TRANSCODER_B,
16907                 TRANSCODER_C,
16908                 TRANSCODER_EDP,
16909         };
16910         int i;
16911
16912         if (INTEL_INFO(dev_priv)->num_pipes == 0)
16913                 return NULL;
16914
16915         error = kzalloc(sizeof(*error), GFP_ATOMIC);
16916         if (error == NULL)
16917                 return NULL;
16918
16919         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16920                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16921
16922         for_each_pipe(dev_priv, i) {
16923                 error->pipe[i].power_domain_on =
16924                         __intel_display_power_is_enabled(dev_priv,
16925                                                          POWER_DOMAIN_PIPE(i));
16926                 if (!error->pipe[i].power_domain_on)
16927                         continue;
16928
16929                 error->cursor[i].control = I915_READ(CURCNTR(i));
16930                 error->cursor[i].position = I915_READ(CURPOS(i));
16931                 error->cursor[i].base = I915_READ(CURBASE(i));
16932
16933                 error->plane[i].control = I915_READ(DSPCNTR(i));
16934                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16935                 if (INTEL_GEN(dev_priv) <= 3) {
16936                         error->plane[i].size = I915_READ(DSPSIZE(i));
16937                         error->plane[i].pos = I915_READ(DSPPOS(i));
16938                 }
16939                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16940                         error->plane[i].addr = I915_READ(DSPADDR(i));
16941                 if (INTEL_GEN(dev_priv) >= 4) {
16942                         error->plane[i].surface = I915_READ(DSPSURF(i));
16943                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16944                 }
16945
16946                 error->pipe[i].source = I915_READ(PIPESRC(i));
16947
16948                 if (HAS_GMCH_DISPLAY(dev_priv))
16949                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16950         }
16951
16952         /* Note: this does not include DSI transcoders. */
16953         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16954         if (HAS_DDI(dev_priv))
16955                 error->num_transcoders++; /* Account for eDP. */
16956
16957         for (i = 0; i < error->num_transcoders; i++) {
16958                 enum transcoder cpu_transcoder = transcoders[i];
16959
16960                 error->transcoder[i].power_domain_on =
16961                         __intel_display_power_is_enabled(dev_priv,
16962                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16963                 if (!error->transcoder[i].power_domain_on)
16964                         continue;
16965
16966                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16967
16968                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16969                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16970                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16971                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16972                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16973                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16974                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16975         }
16976
16977         return error;
16978 }
16979
16980 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16981
16982 void
16983 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16984                                 struct drm_device *dev,
16985                                 struct intel_display_error_state *error)
16986 {
16987         struct drm_i915_private *dev_priv = to_i915(dev);
16988         int i;
16989
16990         if (!error)
16991                 return;
16992
16993         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16994         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16995                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16996                            error->power_well_driver);
16997         for_each_pipe(dev_priv, i) {
16998                 err_printf(m, "Pipe [%d]:\n", i);
16999                 err_printf(m, "  Power: %s\n",
17000                            onoff(error->pipe[i].power_domain_on));
17001                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
17002                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
17003
17004                 err_printf(m, "Plane [%d]:\n", i);
17005                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
17006                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
17007                 if (INTEL_INFO(dev)->gen <= 3) {
17008                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
17009                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
17010                 }
17011                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17012                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
17013                 if (INTEL_INFO(dev)->gen >= 4) {
17014                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
17015                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
17016                 }
17017
17018                 err_printf(m, "Cursor [%d]:\n", i);
17019                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
17020                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
17021                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
17022         }
17023
17024         for (i = 0; i < error->num_transcoders; i++) {
17025                 err_printf(m, "CPU transcoder: %s\n",
17026                            transcoder_name(error->transcoder[i].cpu_transcoder));
17027                 err_printf(m, "  Power: %s\n",
17028                            onoff(error->transcoder[i].power_domain_on));
17029                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
17030                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
17031                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
17032                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
17033                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
17034                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
17035                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
17036         }
17037 }