drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  *
1433  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434  */
1435 void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* No really, not for ILK+ */
1441         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445                 assert_panel_unlocked(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val |= DPLL_VCO_ENABLE;
1450
1451         /* We do this three times for luck */
1452         I915_WRITE(reg, val);
1453         POSTING_READ(reg);
1454         udelay(150); /* wait for warmup */
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         udelay(150); /* wait for warmup */
1458         I915_WRITE(reg, val);
1459         POSTING_READ(reg);
1460         udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464  * intel_disable_pll - disable a PLL
1465  * @dev_priv: i915 private structure
1466  * @pipe: pipe PLL to disable
1467  *
1468  * Disable the PLL for @pipe, making sure the pipe is off first.
1469  *
1470  * Note!  This is for pre-ILK only.
1471  */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* Don't disable pipe A or pipe A PLLs if needed */
1478         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479                 return;
1480
1481         /* Make sure the pipe isn't still relying on us */
1482         assert_pipe_disabled(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val &= ~DPLL_VCO_ENABLE;
1487         I915_WRITE(reg, val);
1488         POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495         unsigned long flags;
1496
1497         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499                                 100)) {
1500                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501                 goto out_unlock;
1502         }
1503
1504         I915_WRITE(SBI_ADDR,
1505                         (reg << 16));
1506         I915_WRITE(SBI_DATA,
1507                         value);
1508         I915_WRITE(SBI_CTL_STAT,
1509                         SBI_BUSY |
1510                         SBI_CTL_OP_CRWR);
1511
1512         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513                                 100)) {
1514                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515                 goto out_unlock;
1516         }
1517
1518 out_unlock:
1519         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525         unsigned long flags;
1526         u32 value = 0;
1527
1528         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530                                 100)) {
1531                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532                 goto out_unlock;
1533         }
1534
1535         I915_WRITE(SBI_ADDR,
1536                         (reg << 16));
1537         I915_WRITE(SBI_CTL_STAT,
1538                         SBI_BUSY |
1539                         SBI_CTL_OP_CRRD);
1540
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544                 goto out_unlock;
1545         }
1546
1547         value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551         return value;
1552 }
1553
1554 /**
1555  * intel_enable_pch_pll - enable PCH PLL
1556  * @dev_priv: i915 private structure
1557  * @pipe: pipe PLL to enable
1558  *
1559  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560  * drives the transcoder clock.
1561  */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565         struct intel_pch_pll *pll;
1566         int reg;
1567         u32 val;
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(dev_priv->info->gen < 5);
1571         pll = intel_crtc->pch_pll;
1572         if (pll == NULL)
1573                 return;
1574
1575         if (WARN_ON(pll->refcount == 0))
1576                 return;
1577
1578         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579                       pll->pll_reg, pll->active, pll->on,
1580                       intel_crtc->base.base.id);
1581
1582         /* PCH refclock must be enabled first */
1583         assert_pch_refclk_enabled(dev_priv);
1584
1585         if (pll->active++ && pll->on) {
1586                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587                 return;
1588         }
1589
1590         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592         reg = pll->pll_reg;
1593         val = I915_READ(reg);
1594         val |= DPLL_VCO_ENABLE;
1595         I915_WRITE(reg, val);
1596         POSTING_READ(reg);
1597         udelay(200);
1598
1599         pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606         int reg;
1607         u32 val;
1608
1609         /* PCH only available on ILK+ */
1610         BUG_ON(dev_priv->info->gen < 5);
1611         if (pll == NULL)
1612                return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         if (WARN_ON(pll->active == 0)) {
1622                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623                 return;
1624         }
1625
1626         if (--pll->active) {
1627                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628                 return;
1629         }
1630
1631         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633         /* Make sure transcoder isn't still depending on us */
1634         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636         reg = pll->pll_reg;
1637         val = I915_READ(reg);
1638         val &= ~DPLL_VCO_ENABLE;
1639         I915_WRITE(reg, val);
1640         POSTING_READ(reg);
1641         udelay(200);
1642
1643         pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647                                     enum pipe pipe)
1648 {
1649         int reg;
1650         u32 val, pipeconf_val;
1651         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653         /* PCH only available on ILK+ */
1654         BUG_ON(dev_priv->info->gen < 5);
1655
1656         /* Make sure PCH DPLL is enabled */
1657         assert_pch_pll_enabled(dev_priv,
1658                                to_intel_crtc(crtc)->pch_pll,
1659                                to_intel_crtc(crtc));
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667                 return;
1668         }
1669         reg = TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv->dev)) {
1674                 /*
1675                  * make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg.
1677                  */
1678                 val &= ~PIPE_BPC_MASK;
1679                 val |= pipeconf_val & PIPE_BPC_MASK;
1680         }
1681
1682         val &= ~TRANS_INTERLACE_MASK;
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684                 if (HAS_PCH_IBX(dev_priv->dev) &&
1685                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686                         val |= TRANS_LEGACY_INTERLACED_ILK;
1687                 else
1688                         val |= TRANS_INTERLACED;
1689         else
1690                 val |= TRANS_PROGRESSIVE;
1691
1692         I915_WRITE(reg, val | TRANS_ENABLE);
1693         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698                                      enum pipe pipe)
1699 {
1700         int reg;
1701         u32 val;
1702
1703         /* FDI relies on the transcoder */
1704         assert_fdi_tx_disabled(dev_priv, pipe);
1705         assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707         /* Ports must be off as well */
1708         assert_pch_ports_disabled(dev_priv, pipe);
1709
1710         reg = TRANSCONF(pipe);
1711         val = I915_READ(reg);
1712         val &= ~TRANS_ENABLE;
1713         I915_WRITE(reg, val);
1714         /* wait for PCH transcoder off, transcoder state */
1715         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720  * intel_enable_pipe - enable a pipe, asserting requirements
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe to enable
1723  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724  *
1725  * Enable @pipe, making sure that various hardware specific requirements
1726  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727  *
1728  * @pipe should be %PIPE_A or %PIPE_B.
1729  *
1730  * Will wait until the pipe is actually running (i.e. first vblank) before
1731  * returning.
1732  */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734                               bool pch_port)
1735 {
1736         int reg;
1737         u32 val;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751                 }
1752                 /* FIXME: assert CPU port conditions for SNB+ */
1753         }
1754
1755         reg = PIPECONF(pipe);
1756         val = I915_READ(reg);
1757         if (val & PIPECONF_ENABLE)
1758                 return;
1759
1760         I915_WRITE(reg, val | PIPECONF_ENABLE);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_pipe - disable a pipe, asserting requirements
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe to disable
1768  *
1769  * Disable @pipe, making sure that various hardware specific requirements
1770  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771  *
1772  * @pipe should be %PIPE_A or %PIPE_B.
1773  *
1774  * Will wait until the pipe has shut down before returning.
1775  */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777                                enum pipe pipe)
1778 {
1779         int reg;
1780         u32 val;
1781
1782         /*
1783          * Make sure planes won't keep trying to pump pixels to us,
1784          * or we might hang the display.
1785          */
1786         assert_planes_disabled(dev_priv, pipe);
1787
1788         /* Don't disable pipe A or pipe A PLLs if needed */
1789         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790                 return;
1791
1792         reg = PIPECONF(pipe);
1793         val = I915_READ(reg);
1794         if ((val & PIPECONF_ENABLE) == 0)
1795                 return;
1796
1797         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802  * Plane regs are double buffered, going from enabled->disabled needs a
1803  * trigger in order to latch.  The display address reg provides this.
1804  */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806                                       enum plane plane)
1807 {
1808         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813  * intel_enable_plane - enable a display plane on a given pipe
1814  * @dev_priv: i915 private structure
1815  * @plane: plane to enable
1816  * @pipe: pipe being fed
1817  *
1818  * Enable @plane on @pipe, making sure that @pipe is running first.
1819  */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane, enum pipe pipe)
1822 {
1823         int reg;
1824         u32 val;
1825
1826         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827         assert_pipe_enabled(dev_priv, pipe);
1828
1829         reg = DSPCNTR(plane);
1830         val = I915_READ(reg);
1831         if (val & DISPLAY_PLANE_ENABLE)
1832                 return;
1833
1834         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835         intel_flush_display_plane(dev_priv, plane);
1836         intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840  * intel_disable_plane - disable a display plane
1841  * @dev_priv: i915 private structure
1842  * @plane: plane to disable
1843  * @pipe: pipe consuming the data
1844  *
1845  * Disable @plane; should be an independent operation.
1846  */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848                                 enum plane plane, enum pipe pipe)
1849 {
1850         int reg;
1851         u32 val;
1852
1853         reg = DSPCNTR(plane);
1854         val = I915_READ(reg);
1855         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856                 return;
1857
1858         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859         intel_flush_display_plane(dev_priv, plane);
1860         intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864                            enum pipe pipe, int reg, u32 port_sel)
1865 {
1866         u32 val = I915_READ(reg);
1867         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869                 I915_WRITE(reg, val & ~DP_PORT_EN);
1870         }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874                              enum pipe pipe, int reg)
1875 {
1876         u32 val = I915_READ(reg);
1877         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1878                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879                               reg, pipe);
1880                 I915_WRITE(reg, val & ~PORT_ENABLE);
1881         }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886                                     enum pipe pipe)
1887 {
1888         u32 reg, val;
1889
1890         val = I915_READ(PCH_PP_CONTROL);
1891         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897         reg = PCH_ADPA;
1898         val = I915_READ(reg);
1899         if (adpa_pipe_enabled(dev_priv, val, pipe))
1900                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902         reg = PCH_LVDS;
1903         val = I915_READ(reg);
1904         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1905                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907                 POSTING_READ(reg);
1908                 udelay(100);
1909         }
1910
1911         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913         disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918                            struct drm_i915_gem_object *obj,
1919                            struct intel_ring_buffer *pipelined)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         u32 alignment;
1923         int ret;
1924
1925         switch (obj->tiling_mode) {
1926         case I915_TILING_NONE:
1927                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928                         alignment = 128 * 1024;
1929                 else if (INTEL_INFO(dev)->gen >= 4)
1930                         alignment = 4 * 1024;
1931                 else
1932                         alignment = 64 * 1024;
1933                 break;
1934         case I915_TILING_X:
1935                 /* pin() will align the object as required by fence */
1936                 alignment = 0;
1937                 break;
1938         case I915_TILING_Y:
1939                 /* FIXME: Is this true? */
1940                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941                 return -EINVAL;
1942         default:
1943                 BUG();
1944         }
1945
1946         dev_priv->mm.interruptible = false;
1947         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948         if (ret)
1949                 goto err_interruptible;
1950
1951         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952          * fence, whereas 965+ only requires a fence if using
1953          * framebuffer compression.  For simplicity, we always install
1954          * a fence as the cost is not that onerous.
1955          */
1956         ret = i915_gem_object_get_fence(obj);
1957         if (ret)
1958                 goto err_unpin;
1959
1960         i915_gem_object_pin_fence(obj);
1961
1962         dev_priv->mm.interruptible = true;
1963         return 0;
1964
1965 err_unpin:
1966         i915_gem_object_unpin(obj);
1967 err_interruptible:
1968         dev_priv->mm.interruptible = true;
1969         return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974         i915_gem_object_unpin_fence(obj);
1975         i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979  * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981                                                         unsigned int bpp,
1982                                                         unsigned int pitch)
1983 {
1984         int tile_rows, tiles;
1985
1986         tile_rows = *y / 8;
1987         *y %= 8;
1988         tiles = *x / (512/bpp);
1989         *x %= 512/bpp;
1990
1991         return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->bits_per_pixel) {
2024         case 8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case 16:
2028                 if (fb->depth == 15)
2029                         dspcntr |= DISPPLANE_15_16BPP;
2030                 else
2031                         dspcntr |= DISPPLANE_16BPP;
2032                 break;
2033         case 24:
2034         case 32:
2035                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036                 break;
2037         default:
2038                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039                 return -EINVAL;
2040         }
2041         if (INTEL_INFO(dev)->gen >= 4) {
2042                 if (obj->tiling_mode != I915_TILING_NONE)
2043                         dspcntr |= DISPPLANE_TILED;
2044                 else
2045                         dspcntr &= ~DISPPLANE_TILED;
2046         }
2047
2048         I915_WRITE(reg, dspcntr);
2049
2050         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052         if (INTEL_INFO(dev)->gen >= 4) {
2053                 intel_crtc->dspaddr_offset =
2054                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055                                                            fb->bits_per_pixel / 8,
2056                                                            fb->pitches[0]);
2057                 linear_offset -= intel_crtc->dspaddr_offset;
2058         } else {
2059                 intel_crtc->dspaddr_offset = linear_offset;
2060         }
2061
2062         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065         if (INTEL_INFO(dev)->gen >= 4) {
2066                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072         POSTING_READ(reg);
2073
2074         return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078                                  struct drm_framebuffer *fb, int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long linear_offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093         case 2:
2094                 break;
2095         default:
2096                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097                 return -EINVAL;
2098         }
2099
2100         intel_fb = to_intel_framebuffer(fb);
2101         obj = intel_fb->obj;
2102
2103         reg = DSPCNTR(plane);
2104         dspcntr = I915_READ(reg);
2105         /* Mask out pixel format bits in case we change it */
2106         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107         switch (fb->bits_per_pixel) {
2108         case 8:
2109                 dspcntr |= DISPPLANE_8BPP;
2110                 break;
2111         case 16:
2112                 if (fb->depth != 16)
2113                         return -EINVAL;
2114
2115                 dspcntr |= DISPPLANE_16BPP;
2116                 break;
2117         case 24:
2118         case 32:
2119                 if (fb->depth == 24)
2120                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121                 else if (fb->depth == 30)
2122                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123                 else
2124                         return -EINVAL;
2125                 break;
2126         default:
2127                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128                 return -EINVAL;
2129         }
2130
2131         if (obj->tiling_mode != I915_TILING_NONE)
2132                 dspcntr |= DISPPLANE_TILED;
2133         else
2134                 dspcntr &= ~DISPPLANE_TILED;
2135
2136         /* must disable */
2137         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139         I915_WRITE(reg, dspcntr);
2140
2141         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142         intel_crtc->dspaddr_offset =
2143                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144                                                    fb->bits_per_pixel / 8,
2145                                                    fb->pitches[0]);
2146         linear_offset -= intel_crtc->dspaddr_offset;
2147
2148         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151         I915_MODIFY_DISPBASE(DSPSURF(plane),
2152                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2153         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154         I915_WRITE(DSPLINOFF(plane), linear_offset);
2155         POSTING_READ(reg);
2156
2157         return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163                            int x, int y, enum mode_set_atomic state)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         if (dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170         intel_increase_pllclock(crtc);
2171
2172         return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180         bool was_interruptible = dev_priv->mm.interruptible;
2181         int ret;
2182
2183         wait_event(dev_priv->pending_flip_queue,
2184                    atomic_read(&dev_priv->mm.wedged) ||
2185                    atomic_read(&obj->pending_flip) == 0);
2186
2187         /* Big Hammer, we also need to ensure that any pending
2188          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189          * current scanout is retired before unpinning the old
2190          * framebuffer.
2191          *
2192          * This should only fail upon a hung GPU, in which case we
2193          * can safely continue.
2194          */
2195         dev_priv->mm.interruptible = false;
2196         ret = i915_gem_object_finish_gpu(obj);
2197         dev_priv->mm.interruptible = was_interruptible;
2198
2199         return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *old_fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_master_private *master_priv;
2209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210         int ret;
2211
2212         /* no fb bound */
2213         if (!crtc->fb) {
2214                 DRM_ERROR("No FB bound\n");
2215                 return 0;
2216         }
2217
2218         if(intel_crtc->plane > dev_priv->num_pipe) {
2219                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220                                 intel_crtc->plane,
2221                                 dev_priv->num_pipe);
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 DRM_ERROR("pin & fence failed\n");
2232                 return ret;
2233         }
2234
2235         if (old_fb)
2236                 intel_finish_fb(old_fb);
2237
2238         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239         if (ret) {
2240                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241                 mutex_unlock(&dev->struct_mutex);
2242                 DRM_ERROR("failed to update base address\n");
2243                 return ret;
2244         }
2245
2246         if (old_fb) {
2247                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249         }
2250
2251         intel_update_fbc(dev);
2252         mutex_unlock(&dev->struct_mutex);
2253
2254         if (!dev->primary->master)
2255                 return 0;
2256
2257         master_priv = dev->primary->master->driver_priv;
2258         if (!master_priv->sarea_priv)
2259                 return 0;
2260
2261         if (intel_crtc->pipe) {
2262                 master_priv->sarea_priv->pipeB_x = x;
2263                 master_priv->sarea_priv->pipeB_y = y;
2264         } else {
2265                 master_priv->sarea_priv->pipeA_x = x;
2266                 master_priv->sarea_priv->pipeA_y = y;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274         struct drm_device *dev = crtc->dev;
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         u32 dpa_ctl;
2277
2278         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279         dpa_ctl = I915_READ(DP_A);
2280         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282         if (clock < 200000) {
2283                 u32 temp;
2284                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285                 /* workaround for 160Mhz:
2286                    1) program 0x4600c bits 15:0 = 0x8124
2287                    2) program 0x46010 bit 0 = 1
2288                    3) program 0x46034 bit 24 = 1
2289                    4) program 0x64000 bit 14 = 1
2290                    */
2291                 temp = I915_READ(0x4600c);
2292                 temp &= 0xffff0000;
2293                 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295                 temp = I915_READ(0x46010);
2296                 I915_WRITE(0x46010, temp | 1);
2297
2298                 temp = I915_READ(0x46034);
2299                 I915_WRITE(0x46034, temp | (1 << 24));
2300         } else {
2301                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302         }
2303         I915_WRITE(DP_A, dpa_ctl);
2304
2305         POSTING_READ(DP_A);
2306         udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311         struct drm_device *dev = crtc->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314         int pipe = intel_crtc->pipe;
2315         u32 reg, temp;
2316
2317         /* enable normal train */
2318         reg = FDI_TX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         if (IS_IVYBRIDGE(dev)) {
2321                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323         } else {
2324                 temp &= ~FDI_LINK_TRAIN_NONE;
2325                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326         }
2327         I915_WRITE(reg, temp);
2328
2329         reg = FDI_RX_CTL(pipe);
2330         temp = I915_READ(reg);
2331         if (HAS_PCH_CPT(dev)) {
2332                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334         } else {
2335                 temp &= ~FDI_LINK_TRAIN_NONE;
2336                 temp |= FDI_LINK_TRAIN_NONE;
2337         }
2338         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340         /* wait one idle pattern time */
2341         POSTING_READ(reg);
2342         udelay(1000);
2343
2344         /* IVB wants error correction enabled */
2345         if (IS_IVYBRIDGE(dev))
2346                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347                            FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355         flags |= FDI_PHASE_SYNC_OVR(pipe);
2356         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357         flags |= FDI_PHASE_SYNC_EN(pipe);
2358         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359         POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365         struct drm_device *dev = crtc->dev;
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368         int pipe = intel_crtc->pipe;
2369         int plane = intel_crtc->plane;
2370         u32 reg, temp, tries;
2371
2372         /* FDI needs bits from pipe & plane first */
2373         assert_pipe_enabled(dev_priv, pipe);
2374         assert_plane_enabled(dev_priv, plane);
2375
2376         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377            for train result */
2378         reg = FDI_RX_IMR(pipe);
2379         temp = I915_READ(reg);
2380         temp &= ~FDI_RX_SYMBOL_LOCK;
2381         temp &= ~FDI_RX_BIT_LOCK;
2382         I915_WRITE(reg, temp);
2383         I915_READ(reg);
2384         udelay(150);
2385
2386         /* enable CPU FDI TX and PCH FDI RX */
2387         reg = FDI_TX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~(7 << 19);
2390         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395         reg = FDI_RX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_LINK_TRAIN_NONE;
2398         temp |= FDI_LINK_TRAIN_PATTERN_1;
2399         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401         POSTING_READ(reg);
2402         udelay(150);
2403
2404         /* Ironlake workaround, enable clock pointer after FDI enable*/
2405         if (HAS_PCH_IBX(dev)) {
2406                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408                            FDI_RX_PHASE_SYNC_POINTER_EN);
2409         }
2410
2411         reg = FDI_RX_IIR(pipe);
2412         for (tries = 0; tries < 5; tries++) {
2413                 temp = I915_READ(reg);
2414                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416                 if ((temp & FDI_RX_BIT_LOCK)) {
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419                         break;
2420                 }
2421         }
2422         if (tries == 5)
2423                 DRM_ERROR("FDI train 1 fail!\n");
2424
2425         /* Train 2 */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_LINK_TRAIN_NONE;
2429         temp |= FDI_LINK_TRAIN_PATTERN_2;
2430         I915_WRITE(reg, temp);
2431
2432         reg = FDI_RX_CTL(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_LINK_TRAIN_NONE;
2435         temp |= FDI_LINK_TRAIN_PATTERN_2;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         reg = FDI_RX_IIR(pipe);
2442         for (tries = 0; tries < 5; tries++) {
2443                 temp = I915_READ(reg);
2444                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446                 if (temp & FDI_RX_SYMBOL_LOCK) {
2447                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2449                         break;
2450                 }
2451         }
2452         if (tries == 5)
2453                 DRM_ERROR("FDI train 2 fail!\n");
2454
2455         DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469         struct drm_device *dev = crtc->dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472         int pipe = intel_crtc->pipe;
2473         u32 reg, temp, i, retry;
2474
2475         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476            for train result */
2477         reg = FDI_RX_IMR(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_RX_SYMBOL_LOCK;
2480         temp &= ~FDI_RX_BIT_LOCK;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494         /* SNB-B */
2495         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         if (HAS_PCH_CPT(dev))
2513                 cpt_phase_pointer_enable(dev, pipe);
2514
2515         for (i = 0; i < 4; i++) {
2516                 reg = FDI_TX_CTL(pipe);
2517                 temp = I915_READ(reg);
2518                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519                 temp |= snb_b_fdi_train_param[i];
2520                 I915_WRITE(reg, temp);
2521
2522                 POSTING_READ(reg);
2523                 udelay(500);
2524
2525                 for (retry = 0; retry < 5; retry++) {
2526                         reg = FDI_RX_IIR(pipe);
2527                         temp = I915_READ(reg);
2528                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529                         if (temp & FDI_RX_BIT_LOCK) {
2530                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532                                 break;
2533                         }
2534                         udelay(50);
2535                 }
2536                 if (retry < 5)
2537                         break;
2538         }
2539         if (i == 4)
2540                 DRM_ERROR("FDI train 1 fail!\n");
2541
2542         /* Train 2 */
2543         reg = FDI_TX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_LINK_TRAIN_NONE;
2546         temp |= FDI_LINK_TRAIN_PATTERN_2;
2547         if (IS_GEN6(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549                 /* SNB-B */
2550                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         }
2552         I915_WRITE(reg, temp);
2553
2554         reg = FDI_RX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         if (HAS_PCH_CPT(dev)) {
2557                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559         } else {
2560                 temp &= ~FDI_LINK_TRAIN_NONE;
2561                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         }
2563         I915_WRITE(reg, temp);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         for (i = 0; i < 4; i++) {
2569                 reg = FDI_TX_CTL(pipe);
2570                 temp = I915_READ(reg);
2571                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572                 temp |= snb_b_fdi_train_param[i];
2573                 I915_WRITE(reg, temp);
2574
2575                 POSTING_READ(reg);
2576                 udelay(500);
2577
2578                 for (retry = 0; retry < 5; retry++) {
2579                         reg = FDI_RX_IIR(pipe);
2580                         temp = I915_READ(reg);
2581                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582                         if (temp & FDI_RX_SYMBOL_LOCK) {
2583                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585                                 break;
2586                         }
2587                         udelay(50);
2588                 }
2589                 if (retry < 5)
2590                         break;
2591         }
2592         if (i == 4)
2593                 DRM_ERROR("FDI train 2 fail!\n");
2594
2595         DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601         struct drm_device *dev = crtc->dev;
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604         int pipe = intel_crtc->pipe;
2605         u32 reg, temp, i;
2606
2607         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608            for train result */
2609         reg = FDI_RX_IMR(pipe);
2610         temp = I915_READ(reg);
2611         temp &= ~FDI_RX_SYMBOL_LOCK;
2612         temp &= ~FDI_RX_BIT_LOCK;
2613         I915_WRITE(reg, temp);
2614
2615         POSTING_READ(reg);
2616         udelay(150);
2617
2618         /* enable CPU FDI TX and PCH FDI RX */
2619         reg = FDI_TX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~(7 << 19);
2622         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627         temp |= FDI_COMPOSITE_SYNC;
2628         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630         reg = FDI_RX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~FDI_LINK_TRAIN_AUTO;
2633         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635         temp |= FDI_COMPOSITE_SYNC;
2636         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         if (HAS_PCH_CPT(dev))
2642                 cpt_phase_pointer_enable(dev, pipe);
2643
2644         for (i = 0; i < 4; i++) {
2645                 reg = FDI_TX_CTL(pipe);
2646                 temp = I915_READ(reg);
2647                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648                 temp |= snb_b_fdi_train_param[i];
2649                 I915_WRITE(reg, temp);
2650
2651                 POSTING_READ(reg);
2652                 udelay(500);
2653
2654                 reg = FDI_RX_IIR(pipe);
2655                 temp = I915_READ(reg);
2656                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658                 if (temp & FDI_RX_BIT_LOCK ||
2659                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                         break;
2663                 }
2664         }
2665         if (i == 4)
2666                 DRM_ERROR("FDI train 1 fail!\n");
2667
2668         /* Train 2 */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675         I915_WRITE(reg, temp);
2676
2677         reg = FDI_RX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681         I915_WRITE(reg, temp);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_SYMBOL_LOCK) {
2701                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2703                         break;
2704                 }
2705         }
2706         if (i == 4)
2707                 DRM_ERROR("FDI train 2 fail!\n");
2708
2709         DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2713 {
2714         struct drm_device *dev = crtc->dev;
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717         int pipe = intel_crtc->pipe;
2718         u32 reg, temp;
2719
2720         /* Write the TU size bits so error detection works */
2721         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2722                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2723
2724         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2725         reg = FDI_RX_CTL(pipe);
2726         temp = I915_READ(reg);
2727         temp &= ~((0x7 << 19) | (0x7 << 16));
2728         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2730         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2731
2732         POSTING_READ(reg);
2733         udelay(200);
2734
2735         /* Switch from Rawclk to PCDclk */
2736         temp = I915_READ(reg);
2737         I915_WRITE(reg, temp | FDI_PCDCLK);
2738
2739         POSTING_READ(reg);
2740         udelay(200);
2741
2742         /* On Haswell, the PLL configuration for ports and pipes is handled
2743          * separately, as part of DDI setup */
2744         if (!IS_HASWELL(dev)) {
2745                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2746                 reg = FDI_TX_CTL(pipe);
2747                 temp = I915_READ(reg);
2748                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2749                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2750
2751                         POSTING_READ(reg);
2752                         udelay(100);
2753                 }
2754         }
2755 }
2756
2757 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2758 {
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         u32 flags = I915_READ(SOUTH_CHICKEN1);
2761
2762         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2763         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2764         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2765         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2766         POSTING_READ(SOUTH_CHICKEN1);
2767 }
2768 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2769 {
2770         struct drm_device *dev = crtc->dev;
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773         int pipe = intel_crtc->pipe;
2774         u32 reg, temp;
2775
2776         /* disable CPU FDI tx and PCH FDI rx */
2777         reg = FDI_TX_CTL(pipe);
2778         temp = I915_READ(reg);
2779         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2780         POSTING_READ(reg);
2781
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         temp &= ~(0x7 << 16);
2785         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2786         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2787
2788         POSTING_READ(reg);
2789         udelay(100);
2790
2791         /* Ironlake workaround, disable clock pointer after downing FDI */
2792         if (HAS_PCH_IBX(dev)) {
2793                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2794                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2795                            I915_READ(FDI_RX_CHICKEN(pipe) &
2796                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2797         } else if (HAS_PCH_CPT(dev)) {
2798                 cpt_phase_pointer_disable(dev, pipe);
2799         }
2800
2801         /* still set train pattern 1 */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         if (HAS_PCH_CPT(dev)) {
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813         } else {
2814                 temp &= ~FDI_LINK_TRAIN_NONE;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816         }
2817         /* BPC in FDI rx is consistent with that in PIPECONF */
2818         temp &= ~(0x07 << 16);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824 }
2825
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829
2830         if (crtc->fb == NULL)
2831                 return;
2832
2833         mutex_lock(&dev->struct_mutex);
2834         intel_finish_fb(crtc->fb);
2835         mutex_unlock(&dev->struct_mutex);
2836 }
2837
2838 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2839 {
2840         struct drm_device *dev = crtc->dev;
2841         struct intel_encoder *intel_encoder;
2842
2843         /*
2844          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2845          * must be driven by its own crtc; no sharing is possible.
2846          */
2847         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2848
2849                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2850                  * CPU handles all others */
2851                 if (IS_HASWELL(dev)) {
2852                         /* It is still unclear how this will work on PPT, so throw up a warning */
2853                         WARN_ON(!HAS_PCH_LPT(dev));
2854
2855                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2856                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2857                                 return true;
2858                         } else {
2859                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2860                                               intel_encoder->type);
2861                                 return false;
2862                         }
2863                 }
2864
2865                 switch (intel_encoder->type) {
2866                 case INTEL_OUTPUT_EDP:
2867                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2868                                 return false;
2869                         continue;
2870                 }
2871         }
2872
2873         return true;
2874 }
2875
2876 /* Program iCLKIP clock to the desired frequency */
2877 static void lpt_program_iclkip(struct drm_crtc *crtc)
2878 {
2879         struct drm_device *dev = crtc->dev;
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2882         u32 temp;
2883
2884         /* It is necessary to ungate the pixclk gate prior to programming
2885          * the divisors, and gate it back when it is done.
2886          */
2887         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2888
2889         /* Disable SSCCTL */
2890         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2891                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2892                                         SBI_SSCCTL_DISABLE);
2893
2894         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895         if (crtc->mode.clock == 20000) {
2896                 auxdiv = 1;
2897                 divsel = 0x41;
2898                 phaseinc = 0x20;
2899         } else {
2900                 /* The iCLK virtual clock root frequency is in MHz,
2901                  * but the crtc->mode.clock in in KHz. To get the divisors,
2902                  * it is necessary to divide one by another, so we
2903                  * convert the virtual clock precision to KHz here for higher
2904                  * precision.
2905                  */
2906                 u32 iclk_virtual_root_freq = 172800 * 1000;
2907                 u32 iclk_pi_range = 64;
2908                 u32 desired_divisor, msb_divisor_value, pi_value;
2909
2910                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2911                 msb_divisor_value = desired_divisor / iclk_pi_range;
2912                 pi_value = desired_divisor % iclk_pi_range;
2913
2914                 auxdiv = 0;
2915                 divsel = msb_divisor_value - 2;
2916                 phaseinc = pi_value;
2917         }
2918
2919         /* This should not happen with any sane values */
2920         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2921                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2922         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2923                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2924
2925         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2926                         crtc->mode.clock,
2927                         auxdiv,
2928                         divsel,
2929                         phasedir,
2930                         phaseinc);
2931
2932         /* Program SSCDIVINTPHASE6 */
2933         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2934         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2935         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2936         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2937         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2938         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2939         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2940
2941         intel_sbi_write(dev_priv,
2942                         SBI_SSCDIVINTPHASE6,
2943                         temp);
2944
2945         /* Program SSCAUXDIV */
2946         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2947         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2948         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2949         intel_sbi_write(dev_priv,
2950                         SBI_SSCAUXDIV6,
2951                         temp);
2952
2953
2954         /* Enable modulator and associated divider */
2955         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2956         temp &= ~SBI_SSCCTL_DISABLE;
2957         intel_sbi_write(dev_priv,
2958                         SBI_SSCCTL6,
2959                         temp);
2960
2961         /* Wait for initialization time */
2962         udelay(24);
2963
2964         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2965 }
2966
2967 /*
2968  * Enable PCH resources required for PCH ports:
2969  *   - PCH PLLs
2970  *   - FDI training & RX/TX
2971  *   - update transcoder timings
2972  *   - DP transcoding bits
2973  *   - transcoder
2974  */
2975 static void ironlake_pch_enable(struct drm_crtc *crtc)
2976 {
2977         struct drm_device *dev = crtc->dev;
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2980         int pipe = intel_crtc->pipe;
2981         u32 reg, temp;
2982
2983         assert_transcoder_disabled(dev_priv, pipe);
2984
2985         /* For PCH output, training FDI link */
2986         dev_priv->display.fdi_link_train(crtc);
2987
2988         intel_enable_pch_pll(intel_crtc);
2989
2990         if (HAS_PCH_LPT(dev)) {
2991                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2992                 lpt_program_iclkip(crtc);
2993         } else if (HAS_PCH_CPT(dev)) {
2994                 u32 sel;
2995
2996                 temp = I915_READ(PCH_DPLL_SEL);
2997                 switch (pipe) {
2998                 default:
2999                 case 0:
3000                         temp |= TRANSA_DPLL_ENABLE;
3001                         sel = TRANSA_DPLLB_SEL;
3002                         break;
3003                 case 1:
3004                         temp |= TRANSB_DPLL_ENABLE;
3005                         sel = TRANSB_DPLLB_SEL;
3006                         break;
3007                 case 2:
3008                         temp |= TRANSC_DPLL_ENABLE;
3009                         sel = TRANSC_DPLLB_SEL;
3010                         break;
3011                 }
3012                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3013                         temp |= sel;
3014                 else
3015                         temp &= ~sel;
3016                 I915_WRITE(PCH_DPLL_SEL, temp);
3017         }
3018
3019         /* set transcoder timing, panel must allow it */
3020         assert_panel_unlocked(dev_priv, pipe);
3021         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3022         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3023         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3024
3025         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3026         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3027         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3028         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3029
3030         if (!IS_HASWELL(dev))
3031                 intel_fdi_normal_train(crtc);
3032
3033         /* For PCH DP, enable TRANS_DP_CTL */
3034         if (HAS_PCH_CPT(dev) &&
3035             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3036              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3037                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3038                 reg = TRANS_DP_CTL(pipe);
3039                 temp = I915_READ(reg);
3040                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3041                           TRANS_DP_SYNC_MASK |
3042                           TRANS_DP_BPC_MASK);
3043                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3044                          TRANS_DP_ENH_FRAMING);
3045                 temp |= bpc << 9; /* same format but at 11:9 */
3046
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3048                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3049                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3050                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3051
3052                 switch (intel_trans_dp_port_sel(crtc)) {
3053                 case PCH_DP_B:
3054                         temp |= TRANS_DP_PORT_SEL_B;
3055                         break;
3056                 case PCH_DP_C:
3057                         temp |= TRANS_DP_PORT_SEL_C;
3058                         break;
3059                 case PCH_DP_D:
3060                         temp |= TRANS_DP_PORT_SEL_D;
3061                         break;
3062                 default:
3063                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3064                         temp |= TRANS_DP_PORT_SEL_B;
3065                         break;
3066                 }
3067
3068                 I915_WRITE(reg, temp);
3069         }
3070
3071         intel_enable_transcoder(dev_priv, pipe);
3072 }
3073
3074 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3075 {
3076         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3077
3078         if (pll == NULL)
3079                 return;
3080
3081         if (pll->refcount == 0) {
3082                 WARN(1, "bad PCH PLL refcount\n");
3083                 return;
3084         }
3085
3086         --pll->refcount;
3087         intel_crtc->pch_pll = NULL;
3088 }
3089
3090 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3091 {
3092         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3093         struct intel_pch_pll *pll;
3094         int i;
3095
3096         pll = intel_crtc->pch_pll;
3097         if (pll) {
3098                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3099                               intel_crtc->base.base.id, pll->pll_reg);
3100                 goto prepare;
3101         }
3102
3103         if (HAS_PCH_IBX(dev_priv->dev)) {
3104                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3105                 i = intel_crtc->pipe;
3106                 pll = &dev_priv->pch_plls[i];
3107
3108                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3109                               intel_crtc->base.base.id, pll->pll_reg);
3110
3111                 goto found;
3112         }
3113
3114         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3115                 pll = &dev_priv->pch_plls[i];
3116
3117                 /* Only want to check enabled timings first */
3118                 if (pll->refcount == 0)
3119                         continue;
3120
3121                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3122                     fp == I915_READ(pll->fp0_reg)) {
3123                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3124                                       intel_crtc->base.base.id,
3125                                       pll->pll_reg, pll->refcount, pll->active);
3126
3127                         goto found;
3128                 }
3129         }
3130
3131         /* Ok no matching timings, maybe there's a free one? */
3132         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3133                 pll = &dev_priv->pch_plls[i];
3134                 if (pll->refcount == 0) {
3135                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3136                                       intel_crtc->base.base.id, pll->pll_reg);
3137                         goto found;
3138                 }
3139         }
3140
3141         return NULL;
3142
3143 found:
3144         intel_crtc->pch_pll = pll;
3145         pll->refcount++;
3146         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3147 prepare: /* separate function? */
3148         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3149
3150         /* Wait for the clocks to stabilize before rewriting the regs */
3151         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3152         POSTING_READ(pll->pll_reg);
3153         udelay(150);
3154
3155         I915_WRITE(pll->fp0_reg, fp);
3156         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3157         pll->on = false;
3158         return pll;
3159 }
3160
3161 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3162 {
3163         struct drm_i915_private *dev_priv = dev->dev_private;
3164         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3165         u32 temp;
3166
3167         temp = I915_READ(dslreg);
3168         udelay(500);
3169         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3170                 /* Without this, mode sets may fail silently on FDI */
3171                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3172                 udelay(250);
3173                 I915_WRITE(tc2reg, 0);
3174                 if (wait_for(I915_READ(dslreg) != temp, 5))
3175                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3176         }
3177 }
3178
3179 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3180 {
3181         struct drm_device *dev = crtc->dev;
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184         int pipe = intel_crtc->pipe;
3185         int plane = intel_crtc->plane;
3186         u32 temp;
3187         bool is_pch_port;
3188
3189         if (intel_crtc->active)
3190                 return;
3191
3192         intel_crtc->active = true;
3193         intel_update_watermarks(dev);
3194
3195         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3196                 temp = I915_READ(PCH_LVDS);
3197                 if ((temp & LVDS_PORT_EN) == 0)
3198                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3199         }
3200
3201         is_pch_port = intel_crtc_driving_pch(crtc);
3202
3203         if (is_pch_port)
3204                 ironlake_fdi_pll_enable(crtc);
3205         else
3206                 ironlake_fdi_disable(crtc);
3207
3208         /* Enable panel fitting for LVDS */
3209         if (dev_priv->pch_pf_size &&
3210             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3211                 /* Force use of hard-coded filter coefficients
3212                  * as some pre-programmed values are broken,
3213                  * e.g. x201.
3214                  */
3215                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3216                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3217                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3218         }
3219
3220         /*
3221          * On ILK+ LUT must be loaded before the pipe is running but with
3222          * clocks enabled
3223          */
3224         intel_crtc_load_lut(crtc);
3225
3226         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3227         intel_enable_plane(dev_priv, plane, pipe);
3228
3229         if (is_pch_port)
3230                 ironlake_pch_enable(crtc);
3231
3232         mutex_lock(&dev->struct_mutex);
3233         intel_update_fbc(dev);
3234         mutex_unlock(&dev->struct_mutex);
3235
3236         intel_crtc_update_cursor(crtc, true);
3237 }
3238
3239 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3240 {
3241         struct drm_device *dev = crtc->dev;
3242         struct drm_i915_private *dev_priv = dev->dev_private;
3243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244         int pipe = intel_crtc->pipe;
3245         int plane = intel_crtc->plane;
3246         u32 reg, temp;
3247
3248         if (!intel_crtc->active)
3249                 return;
3250
3251         intel_crtc_wait_for_pending_flips(crtc);
3252         drm_vblank_off(dev, pipe);
3253         intel_crtc_update_cursor(crtc, false);
3254
3255         intel_disable_plane(dev_priv, plane, pipe);
3256
3257         if (dev_priv->cfb_plane == plane)
3258                 intel_disable_fbc(dev);
3259
3260         intel_disable_pipe(dev_priv, pipe);
3261
3262         /* Disable PF */
3263         I915_WRITE(PF_CTL(pipe), 0);
3264         I915_WRITE(PF_WIN_SZ(pipe), 0);
3265
3266         ironlake_fdi_disable(crtc);
3267
3268         /* This is a horrible layering violation; we should be doing this in
3269          * the connector/encoder ->prepare instead, but we don't always have
3270          * enough information there about the config to know whether it will
3271          * actually be necessary or just cause undesired flicker.
3272          */
3273         intel_disable_pch_ports(dev_priv, pipe);
3274
3275         intel_disable_transcoder(dev_priv, pipe);
3276
3277         if (HAS_PCH_CPT(dev)) {
3278                 /* disable TRANS_DP_CTL */
3279                 reg = TRANS_DP_CTL(pipe);
3280                 temp = I915_READ(reg);
3281                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3282                 temp |= TRANS_DP_PORT_SEL_NONE;
3283                 I915_WRITE(reg, temp);
3284
3285                 /* disable DPLL_SEL */
3286                 temp = I915_READ(PCH_DPLL_SEL);
3287                 switch (pipe) {
3288                 case 0:
3289                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3290                         break;
3291                 case 1:
3292                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3293                         break;
3294                 case 2:
3295                         /* C shares PLL A or B */
3296                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3297                         break;
3298                 default:
3299                         BUG(); /* wtf */
3300                 }
3301                 I915_WRITE(PCH_DPLL_SEL, temp);
3302         }
3303
3304         /* disable PCH DPLL */
3305         intel_disable_pch_pll(intel_crtc);
3306
3307         /* Switch from PCDclk to Rawclk */
3308         reg = FDI_RX_CTL(pipe);
3309         temp = I915_READ(reg);
3310         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3311
3312         /* Disable CPU FDI TX PLL */
3313         reg = FDI_TX_CTL(pipe);
3314         temp = I915_READ(reg);
3315         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3316
3317         POSTING_READ(reg);
3318         udelay(100);
3319
3320         reg = FDI_RX_CTL(pipe);
3321         temp = I915_READ(reg);
3322         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3323
3324         /* Wait for the clocks to turn off. */
3325         POSTING_READ(reg);
3326         udelay(100);
3327
3328         intel_crtc->active = false;
3329         intel_update_watermarks(dev);
3330
3331         mutex_lock(&dev->struct_mutex);
3332         intel_update_fbc(dev);
3333         mutex_unlock(&dev->struct_mutex);
3334 }
3335
3336 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3337 {
3338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3339         int pipe = intel_crtc->pipe;
3340         int plane = intel_crtc->plane;
3341
3342         /* XXX: When our outputs are all unaware of DPMS modes other than off
3343          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3344          */
3345         switch (mode) {
3346         case DRM_MODE_DPMS_ON:
3347         case DRM_MODE_DPMS_STANDBY:
3348         case DRM_MODE_DPMS_SUSPEND:
3349                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3350                 ironlake_crtc_enable(crtc);
3351                 break;
3352
3353         case DRM_MODE_DPMS_OFF:
3354                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3355                 ironlake_crtc_disable(crtc);
3356                 break;
3357         }
3358 }
3359
3360 static void ironlake_crtc_off(struct drm_crtc *crtc)
3361 {
3362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363         intel_put_pch_pll(intel_crtc);
3364 }
3365
3366 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3367 {
3368         if (!enable && intel_crtc->overlay) {
3369                 struct drm_device *dev = intel_crtc->base.dev;
3370                 struct drm_i915_private *dev_priv = dev->dev_private;
3371
3372                 mutex_lock(&dev->struct_mutex);
3373                 dev_priv->mm.interruptible = false;
3374                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3375                 dev_priv->mm.interruptible = true;
3376                 mutex_unlock(&dev->struct_mutex);
3377         }
3378
3379         /* Let userspace switch the overlay on again. In most cases userspace
3380          * has to recompute where to put it anyway.
3381          */
3382 }
3383
3384 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3385 {
3386         struct drm_device *dev = crtc->dev;
3387         struct drm_i915_private *dev_priv = dev->dev_private;
3388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3389         int pipe = intel_crtc->pipe;
3390         int plane = intel_crtc->plane;
3391
3392         if (intel_crtc->active)
3393                 return;
3394
3395         intel_crtc->active = true;
3396         intel_update_watermarks(dev);
3397
3398         intel_enable_pll(dev_priv, pipe);
3399         intel_enable_pipe(dev_priv, pipe, false);
3400         intel_enable_plane(dev_priv, plane, pipe);
3401
3402         intel_crtc_load_lut(crtc);
3403         intel_update_fbc(dev);
3404
3405         /* Give the overlay scaler a chance to enable if it's on this pipe */
3406         intel_crtc_dpms_overlay(intel_crtc, true);
3407         intel_crtc_update_cursor(crtc, true);
3408 }
3409
3410 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415         int pipe = intel_crtc->pipe;
3416         int plane = intel_crtc->plane;
3417
3418         if (!intel_crtc->active)
3419                 return;
3420
3421         /* Give the overlay scaler a chance to disable if it's on this pipe */
3422         intel_crtc_wait_for_pending_flips(crtc);
3423         drm_vblank_off(dev, pipe);
3424         intel_crtc_dpms_overlay(intel_crtc, false);
3425         intel_crtc_update_cursor(crtc, false);
3426
3427         if (dev_priv->cfb_plane == plane)
3428                 intel_disable_fbc(dev);
3429
3430         intel_disable_plane(dev_priv, plane, pipe);
3431         intel_disable_pipe(dev_priv, pipe);
3432         intel_disable_pll(dev_priv, pipe);
3433
3434         intel_crtc->active = false;
3435         intel_update_fbc(dev);
3436         intel_update_watermarks(dev);
3437 }
3438
3439 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3440 {
3441         /* XXX: When our outputs are all unaware of DPMS modes other than off
3442          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3443          */
3444         switch (mode) {
3445         case DRM_MODE_DPMS_ON:
3446         case DRM_MODE_DPMS_STANDBY:
3447         case DRM_MODE_DPMS_SUSPEND:
3448                 i9xx_crtc_enable(crtc);
3449                 break;
3450         case DRM_MODE_DPMS_OFF:
3451                 i9xx_crtc_disable(crtc);
3452                 break;
3453         }
3454 }
3455
3456 static void i9xx_crtc_off(struct drm_crtc *crtc)
3457 {
3458 }
3459
3460 /**
3461  * Sets the power management mode of the pipe and plane.
3462  */
3463 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3464 {
3465         struct drm_device *dev = crtc->dev;
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467         struct drm_i915_master_private *master_priv;
3468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3469         int pipe = intel_crtc->pipe;
3470         bool enabled;
3471
3472         if (intel_crtc->dpms_mode == mode)
3473                 return;
3474
3475         intel_crtc->dpms_mode = mode;
3476
3477         dev_priv->display.dpms(crtc, mode);
3478
3479         if (!dev->primary->master)
3480                 return;
3481
3482         master_priv = dev->primary->master->driver_priv;
3483         if (!master_priv->sarea_priv)
3484                 return;
3485
3486         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3487
3488         switch (pipe) {
3489         case 0:
3490                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3491                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3492                 break;
3493         case 1:
3494                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3495                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3496                 break;
3497         default:
3498                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3499                 break;
3500         }
3501 }
3502
3503 static void intel_crtc_disable(struct drm_crtc *crtc)
3504 {
3505         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508
3509         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3510         dev_priv->display.off(crtc);
3511
3512         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3513         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3514
3515         if (crtc->fb) {
3516                 mutex_lock(&dev->struct_mutex);
3517                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3518                 mutex_unlock(&dev->struct_mutex);
3519         }
3520 }
3521
3522 /* Prepare for a mode set.
3523  *
3524  * Note we could be a lot smarter here.  We need to figure out which outputs
3525  * will be enabled, which disabled (in short, how the config will changes)
3526  * and perform the minimum necessary steps to accomplish that, e.g. updating
3527  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3528  * panel fitting is in the proper state, etc.
3529  */
3530 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3531 {
3532         i9xx_crtc_disable(crtc);
3533 }
3534
3535 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3536 {
3537         i9xx_crtc_enable(crtc);
3538 }
3539
3540 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3541 {
3542         ironlake_crtc_disable(crtc);
3543 }
3544
3545 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3546 {
3547         ironlake_crtc_enable(crtc);
3548 }
3549
3550 void intel_encoder_prepare(struct drm_encoder *encoder)
3551 {
3552         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3553         /* lvds has its own version of prepare see intel_lvds_prepare */
3554         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3555 }
3556
3557 void intel_encoder_commit(struct drm_encoder *encoder)
3558 {
3559         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3560         struct drm_device *dev = encoder->dev;
3561         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3562
3563         /* lvds has its own version of commit see intel_lvds_commit */
3564         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3565
3566         if (HAS_PCH_CPT(dev))
3567                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3568 }
3569
3570 void intel_encoder_destroy(struct drm_encoder *encoder)
3571 {
3572         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3573
3574         drm_encoder_cleanup(encoder);
3575         kfree(intel_encoder);
3576 }
3577
3578 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3579                                   const struct drm_display_mode *mode,
3580                                   struct drm_display_mode *adjusted_mode)
3581 {
3582         struct drm_device *dev = crtc->dev;
3583
3584         if (HAS_PCH_SPLIT(dev)) {
3585                 /* FDI link clock is fixed at 2.7G */
3586                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3587                         return false;
3588         }
3589
3590         /* All interlaced capable intel hw wants timings in frames. Note though
3591          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3592          * timings, so we need to be careful not to clobber these.*/
3593         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3594                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3595
3596         return true;
3597 }
3598
3599 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3600 {
3601         return 400000; /* FIXME */
3602 }
3603
3604 static int i945_get_display_clock_speed(struct drm_device *dev)
3605 {
3606         return 400000;
3607 }
3608
3609 static int i915_get_display_clock_speed(struct drm_device *dev)
3610 {
3611         return 333000;
3612 }
3613
3614 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3615 {
3616         return 200000;
3617 }
3618
3619 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3620 {
3621         u16 gcfgc = 0;
3622
3623         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3624
3625         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3626                 return 133000;
3627         else {
3628                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3629                 case GC_DISPLAY_CLOCK_333_MHZ:
3630                         return 333000;
3631                 default:
3632                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3633                         return 190000;
3634                 }
3635         }
3636 }
3637
3638 static int i865_get_display_clock_speed(struct drm_device *dev)
3639 {
3640         return 266000;
3641 }
3642
3643 static int i855_get_display_clock_speed(struct drm_device *dev)
3644 {
3645         u16 hpllcc = 0;
3646         /* Assume that the hardware is in the high speed state.  This
3647          * should be the default.
3648          */
3649         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3650         case GC_CLOCK_133_200:
3651         case GC_CLOCK_100_200:
3652                 return 200000;
3653         case GC_CLOCK_166_250:
3654                 return 250000;
3655         case GC_CLOCK_100_133:
3656                 return 133000;
3657         }
3658
3659         /* Shouldn't happen */
3660         return 0;
3661 }
3662
3663 static int i830_get_display_clock_speed(struct drm_device *dev)
3664 {
3665         return 133000;
3666 }
3667
3668 struct fdi_m_n {
3669         u32        tu;
3670         u32        gmch_m;
3671         u32        gmch_n;
3672         u32        link_m;
3673         u32        link_n;
3674 };
3675
3676 static void
3677 fdi_reduce_ratio(u32 *num, u32 *den)
3678 {
3679         while (*num > 0xffffff || *den > 0xffffff) {
3680                 *num >>= 1;
3681                 *den >>= 1;
3682         }
3683 }
3684
3685 static void
3686 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3687                      int link_clock, struct fdi_m_n *m_n)
3688 {
3689         m_n->tu = 64; /* default size */
3690
3691         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3692         m_n->gmch_m = bits_per_pixel * pixel_clock;
3693         m_n->gmch_n = link_clock * nlanes * 8;
3694         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3695
3696         m_n->link_m = pixel_clock;
3697         m_n->link_n = link_clock;
3698         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3699 }
3700
3701 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3702 {
3703         if (i915_panel_use_ssc >= 0)
3704                 return i915_panel_use_ssc != 0;
3705         return dev_priv->lvds_use_ssc
3706                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3707 }
3708
3709 /**
3710  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3711  * @crtc: CRTC structure
3712  * @mode: requested mode
3713  *
3714  * A pipe may be connected to one or more outputs.  Based on the depth of the
3715  * attached framebuffer, choose a good color depth to use on the pipe.
3716  *
3717  * If possible, match the pipe depth to the fb depth.  In some cases, this
3718  * isn't ideal, because the connected output supports a lesser or restricted
3719  * set of depths.  Resolve that here:
3720  *    LVDS typically supports only 6bpc, so clamp down in that case
3721  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3722  *    Displays may support a restricted set as well, check EDID and clamp as
3723  *      appropriate.
3724  *    DP may want to dither down to 6bpc to fit larger modes
3725  *
3726  * RETURNS:
3727  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3728  * true if they don't match).
3729  */
3730 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3731                                          unsigned int *pipe_bpp,
3732                                          struct drm_display_mode *mode)
3733 {
3734         struct drm_device *dev = crtc->dev;
3735         struct drm_i915_private *dev_priv = dev->dev_private;
3736         struct drm_connector *connector;
3737         struct intel_encoder *intel_encoder;
3738         unsigned int display_bpc = UINT_MAX, bpc;
3739
3740         /* Walk the encoders & connectors on this crtc, get min bpc */
3741         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3742
3743                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3744                         unsigned int lvds_bpc;
3745
3746                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3747                             LVDS_A3_POWER_UP)
3748                                 lvds_bpc = 8;
3749                         else
3750                                 lvds_bpc = 6;
3751
3752                         if (lvds_bpc < display_bpc) {
3753                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3754                                 display_bpc = lvds_bpc;
3755                         }
3756                         continue;
3757                 }
3758
3759                 /* Not one of the known troublemakers, check the EDID */
3760                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3761                                     head) {
3762                         if (connector->encoder != &intel_encoder->base)
3763                                 continue;
3764
3765                         /* Don't use an invalid EDID bpc value */
3766                         if (connector->display_info.bpc &&
3767                             connector->display_info.bpc < display_bpc) {
3768                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3769                                 display_bpc = connector->display_info.bpc;
3770                         }
3771                 }
3772
3773                 /*
3774                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3775                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3776                  */
3777                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3778                         if (display_bpc > 8 && display_bpc < 12) {
3779                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3780                                 display_bpc = 12;
3781                         } else {
3782                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3783                                 display_bpc = 8;
3784                         }
3785                 }
3786         }
3787
3788         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3789                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3790                 display_bpc = 6;
3791         }
3792
3793         /*
3794          * We could just drive the pipe at the highest bpc all the time and
3795          * enable dithering as needed, but that costs bandwidth.  So choose
3796          * the minimum value that expresses the full color range of the fb but
3797          * also stays within the max display bpc discovered above.
3798          */
3799
3800         switch (crtc->fb->depth) {
3801         case 8:
3802                 bpc = 8; /* since we go through a colormap */
3803                 break;
3804         case 15:
3805         case 16:
3806                 bpc = 6; /* min is 18bpp */
3807                 break;
3808         case 24:
3809                 bpc = 8;
3810                 break;
3811         case 30:
3812                 bpc = 10;
3813                 break;
3814         case 48:
3815                 bpc = 12;
3816                 break;
3817         default:
3818                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3819                 bpc = min((unsigned int)8, display_bpc);
3820                 break;
3821         }
3822
3823         display_bpc = min(display_bpc, bpc);
3824
3825         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3826                       bpc, display_bpc);
3827
3828         *pipe_bpp = display_bpc * 3;
3829
3830         return display_bpc != bpc;
3831 }
3832
3833 static int vlv_get_refclk(struct drm_crtc *crtc)
3834 {
3835         struct drm_device *dev = crtc->dev;
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837         int refclk = 27000; /* for DP & HDMI */
3838
3839         return 100000; /* only one validated so far */
3840
3841         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3842                 refclk = 96000;
3843         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3844                 if (intel_panel_use_ssc(dev_priv))
3845                         refclk = 100000;
3846                 else
3847                         refclk = 96000;
3848         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3849                 refclk = 100000;
3850         }
3851
3852         return refclk;
3853 }
3854
3855 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3856 {
3857         struct drm_device *dev = crtc->dev;
3858         struct drm_i915_private *dev_priv = dev->dev_private;
3859         int refclk;
3860
3861         if (IS_VALLEYVIEW(dev)) {
3862                 refclk = vlv_get_refclk(crtc);
3863         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3864             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3865                 refclk = dev_priv->lvds_ssc_freq * 1000;
3866                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3867                               refclk / 1000);
3868         } else if (!IS_GEN2(dev)) {
3869                 refclk = 96000;
3870         } else {
3871                 refclk = 48000;
3872         }
3873
3874         return refclk;
3875 }
3876
3877 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3878                                       intel_clock_t *clock)
3879 {
3880         /* SDVO TV has fixed PLL values depend on its clock range,
3881            this mirrors vbios setting. */
3882         if (adjusted_mode->clock >= 100000
3883             && adjusted_mode->clock < 140500) {
3884                 clock->p1 = 2;
3885                 clock->p2 = 10;
3886                 clock->n = 3;
3887                 clock->m1 = 16;
3888                 clock->m2 = 8;
3889         } else if (adjusted_mode->clock >= 140500
3890                    && adjusted_mode->clock <= 200000) {
3891                 clock->p1 = 1;
3892                 clock->p2 = 10;
3893                 clock->n = 6;
3894                 clock->m1 = 12;
3895                 clock->m2 = 8;
3896         }
3897 }
3898
3899 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3900                                      intel_clock_t *clock,
3901                                      intel_clock_t *reduced_clock)
3902 {
3903         struct drm_device *dev = crtc->dev;
3904         struct drm_i915_private *dev_priv = dev->dev_private;
3905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3906         int pipe = intel_crtc->pipe;
3907         u32 fp, fp2 = 0;
3908
3909         if (IS_PINEVIEW(dev)) {
3910                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3911                 if (reduced_clock)
3912                         fp2 = (1 << reduced_clock->n) << 16 |
3913                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3914         } else {
3915                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3916                 if (reduced_clock)
3917                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3918                                 reduced_clock->m2;
3919         }
3920
3921         I915_WRITE(FP0(pipe), fp);
3922
3923         intel_crtc->lowfreq_avail = false;
3924         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3925             reduced_clock && i915_powersave) {
3926                 I915_WRITE(FP1(pipe), fp2);
3927                 intel_crtc->lowfreq_avail = true;
3928         } else {
3929                 I915_WRITE(FP1(pipe), fp);
3930         }
3931 }
3932
3933 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3934                               struct drm_display_mode *adjusted_mode)
3935 {
3936         struct drm_device *dev = crtc->dev;
3937         struct drm_i915_private *dev_priv = dev->dev_private;
3938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939         int pipe = intel_crtc->pipe;
3940         u32 temp;
3941
3942         temp = I915_READ(LVDS);
3943         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3944         if (pipe == 1) {
3945                 temp |= LVDS_PIPEB_SELECT;
3946         } else {
3947                 temp &= ~LVDS_PIPEB_SELECT;
3948         }
3949         /* set the corresponsding LVDS_BORDER bit */
3950         temp |= dev_priv->lvds_border_bits;
3951         /* Set the B0-B3 data pairs corresponding to whether we're going to
3952          * set the DPLLs for dual-channel mode or not.
3953          */
3954         if (clock->p2 == 7)
3955                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3956         else
3957                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3958
3959         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3960          * appropriately here, but we need to look more thoroughly into how
3961          * panels behave in the two modes.
3962          */
3963         /* set the dithering flag on LVDS as needed */
3964         if (INTEL_INFO(dev)->gen >= 4) {
3965                 if (dev_priv->lvds_dither)
3966                         temp |= LVDS_ENABLE_DITHER;
3967                 else
3968                         temp &= ~LVDS_ENABLE_DITHER;
3969         }
3970         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3971         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3972                 temp |= LVDS_HSYNC_POLARITY;
3973         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3974                 temp |= LVDS_VSYNC_POLARITY;
3975         I915_WRITE(LVDS, temp);
3976 }
3977
3978 static void vlv_update_pll(struct drm_crtc *crtc,
3979                            struct drm_display_mode *mode,
3980                            struct drm_display_mode *adjusted_mode,
3981                            intel_clock_t *clock, intel_clock_t *reduced_clock,
3982                            int refclk, int num_connectors)
3983 {
3984         struct drm_device *dev = crtc->dev;
3985         struct drm_i915_private *dev_priv = dev->dev_private;
3986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3987         int pipe = intel_crtc->pipe;
3988         u32 dpll, mdiv, pdiv;
3989         u32 bestn, bestm1, bestm2, bestp1, bestp2;
3990         bool is_hdmi;
3991
3992         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3993
3994         bestn = clock->n;
3995         bestm1 = clock->m1;
3996         bestm2 = clock->m2;
3997         bestp1 = clock->p1;
3998         bestp2 = clock->p2;
3999
4000         /* Enable DPIO clock input */
4001         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4002                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4003         I915_WRITE(DPLL(pipe), dpll);
4004         POSTING_READ(DPLL(pipe));
4005
4006         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4007         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4008         mdiv |= ((bestn << DPIO_N_SHIFT));
4009         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4010         mdiv |= (1 << DPIO_K_SHIFT);
4011         mdiv |= DPIO_ENABLE_CALIBRATION;
4012         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4013
4014         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4015
4016         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4017                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4018                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4019         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4020
4021         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4022
4023         dpll |= DPLL_VCO_ENABLE;
4024         I915_WRITE(DPLL(pipe), dpll);
4025         POSTING_READ(DPLL(pipe));
4026         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4027                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4028
4029         if (is_hdmi) {
4030                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4031
4032                 if (temp > 1)
4033                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4034                 else
4035                         temp = 0;
4036
4037                 I915_WRITE(DPLL_MD(pipe), temp);
4038                 POSTING_READ(DPLL_MD(pipe));
4039         }
4040
4041         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4042 }
4043
4044 static void i9xx_update_pll(struct drm_crtc *crtc,
4045                             struct drm_display_mode *mode,
4046                             struct drm_display_mode *adjusted_mode,
4047                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4048                             int num_connectors)
4049 {
4050         struct drm_device *dev = crtc->dev;
4051         struct drm_i915_private *dev_priv = dev->dev_private;
4052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053         int pipe = intel_crtc->pipe;
4054         u32 dpll;
4055         bool is_sdvo;
4056
4057         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4058                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4059
4060         dpll = DPLL_VGA_MODE_DIS;
4061
4062         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4063                 dpll |= DPLLB_MODE_LVDS;
4064         else
4065                 dpll |= DPLLB_MODE_DAC_SERIAL;
4066         if (is_sdvo) {
4067                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4068                 if (pixel_multiplier > 1) {
4069                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4070                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4071                 }
4072                 dpll |= DPLL_DVO_HIGH_SPEED;
4073         }
4074         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4075                 dpll |= DPLL_DVO_HIGH_SPEED;
4076
4077         /* compute bitmask from p1 value */
4078         if (IS_PINEVIEW(dev))
4079                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4080         else {
4081                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4082                 if (IS_G4X(dev) && reduced_clock)
4083                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4084         }
4085         switch (clock->p2) {
4086         case 5:
4087                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4088                 break;
4089         case 7:
4090                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4091                 break;
4092         case 10:
4093                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4094                 break;
4095         case 14:
4096                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4097                 break;
4098         }
4099         if (INTEL_INFO(dev)->gen >= 4)
4100                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4101
4102         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4103                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4104         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4105                 /* XXX: just matching BIOS for now */
4106                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4107                 dpll |= 3;
4108         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4109                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4110                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4111         else
4112                 dpll |= PLL_REF_INPUT_DREFCLK;
4113
4114         dpll |= DPLL_VCO_ENABLE;
4115         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4116         POSTING_READ(DPLL(pipe));
4117         udelay(150);
4118
4119         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4120          * This is an exception to the general rule that mode_set doesn't turn
4121          * things on.
4122          */
4123         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4124                 intel_update_lvds(crtc, clock, adjusted_mode);
4125
4126         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4127                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4128
4129         I915_WRITE(DPLL(pipe), dpll);
4130
4131         /* Wait for the clocks to stabilize. */
4132         POSTING_READ(DPLL(pipe));
4133         udelay(150);
4134
4135         if (INTEL_INFO(dev)->gen >= 4) {
4136                 u32 temp = 0;
4137                 if (is_sdvo) {
4138                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4139                         if (temp > 1)
4140                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4141                         else
4142                                 temp = 0;
4143                 }
4144                 I915_WRITE(DPLL_MD(pipe), temp);
4145         } else {
4146                 /* The pixel multiplier can only be updated once the
4147                  * DPLL is enabled and the clocks are stable.
4148                  *
4149                  * So write it again.
4150                  */
4151                 I915_WRITE(DPLL(pipe), dpll);
4152         }
4153 }
4154
4155 static void i8xx_update_pll(struct drm_crtc *crtc,
4156                             struct drm_display_mode *adjusted_mode,
4157                             intel_clock_t *clock,
4158                             int num_connectors)
4159 {
4160         struct drm_device *dev = crtc->dev;
4161         struct drm_i915_private *dev_priv = dev->dev_private;
4162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4163         int pipe = intel_crtc->pipe;
4164         u32 dpll;
4165
4166         dpll = DPLL_VGA_MODE_DIS;
4167
4168         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4169                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170         } else {
4171                 if (clock->p1 == 2)
4172                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4173                 else
4174                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175                 if (clock->p2 == 4)
4176                         dpll |= PLL_P2_DIVIDE_BY_4;
4177         }
4178
4179         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4180                 /* XXX: just matching BIOS for now */
4181                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4182                 dpll |= 3;
4183         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4184                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4185                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4186         else
4187                 dpll |= PLL_REF_INPUT_DREFCLK;
4188
4189         dpll |= DPLL_VCO_ENABLE;
4190         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4191         POSTING_READ(DPLL(pipe));
4192         udelay(150);
4193
4194         I915_WRITE(DPLL(pipe), dpll);
4195
4196         /* Wait for the clocks to stabilize. */
4197         POSTING_READ(DPLL(pipe));
4198         udelay(150);
4199
4200         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4201          * This is an exception to the general rule that mode_set doesn't turn
4202          * things on.
4203          */
4204         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4205                 intel_update_lvds(crtc, clock, adjusted_mode);
4206
4207         /* The pixel multiplier can only be updated once the
4208          * DPLL is enabled and the clocks are stable.
4209          *
4210          * So write it again.
4211          */
4212         I915_WRITE(DPLL(pipe), dpll);
4213 }
4214
4215 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4216                               struct drm_display_mode *mode,
4217                               struct drm_display_mode *adjusted_mode,
4218                               int x, int y,
4219                               struct drm_framebuffer *old_fb)
4220 {
4221         struct drm_device *dev = crtc->dev;
4222         struct drm_i915_private *dev_priv = dev->dev_private;
4223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224         int pipe = intel_crtc->pipe;
4225         int plane = intel_crtc->plane;
4226         int refclk, num_connectors = 0;
4227         intel_clock_t clock, reduced_clock;
4228         u32 dspcntr, pipeconf, vsyncshift;
4229         bool ok, has_reduced_clock = false, is_sdvo = false;
4230         bool is_lvds = false, is_tv = false, is_dp = false;
4231         struct intel_encoder *encoder;
4232         const intel_limit_t *limit;
4233         int ret;
4234
4235         for_each_encoder_on_crtc(dev, crtc, encoder) {
4236                 switch (encoder->type) {
4237                 case INTEL_OUTPUT_LVDS:
4238                         is_lvds = true;
4239                         break;
4240                 case INTEL_OUTPUT_SDVO:
4241                 case INTEL_OUTPUT_HDMI:
4242                         is_sdvo = true;
4243                         if (encoder->needs_tv_clock)
4244                                 is_tv = true;
4245                         break;
4246                 case INTEL_OUTPUT_TVOUT:
4247                         is_tv = true;
4248                         break;
4249                 case INTEL_OUTPUT_DISPLAYPORT:
4250                         is_dp = true;
4251                         break;
4252                 }
4253
4254                 num_connectors++;
4255         }
4256
4257         refclk = i9xx_get_refclk(crtc, num_connectors);
4258
4259         /*
4260          * Returns a set of divisors for the desired target clock with the given
4261          * refclk, or FALSE.  The returned values represent the clock equation:
4262          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4263          */
4264         limit = intel_limit(crtc, refclk);
4265         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4266                              &clock);
4267         if (!ok) {
4268                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4269                 return -EINVAL;
4270         }
4271
4272         /* Ensure that the cursor is valid for the new mode before changing... */
4273         intel_crtc_update_cursor(crtc, true);
4274
4275         if (is_lvds && dev_priv->lvds_downclock_avail) {
4276                 /*
4277                  * Ensure we match the reduced clock's P to the target clock.
4278                  * If the clocks don't match, we can't switch the display clock
4279                  * by using the FP0/FP1. In such case we will disable the LVDS
4280                  * downclock feature.
4281                 */
4282                 has_reduced_clock = limit->find_pll(limit, crtc,
4283                                                     dev_priv->lvds_downclock,
4284                                                     refclk,
4285                                                     &clock,
4286                                                     &reduced_clock);
4287         }
4288
4289         if (is_sdvo && is_tv)
4290                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4291
4292         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4293                                  &reduced_clock : NULL);
4294
4295         if (IS_GEN2(dev))
4296                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4297         else if (IS_VALLEYVIEW(dev))
4298                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4299                                refclk, num_connectors);
4300         else
4301                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4302                                 has_reduced_clock ? &reduced_clock : NULL,
4303                                 num_connectors);
4304
4305         /* setup pipeconf */
4306         pipeconf = I915_READ(PIPECONF(pipe));
4307
4308         /* Set up the display plane register */
4309         dspcntr = DISPPLANE_GAMMA_ENABLE;
4310
4311         if (pipe == 0)
4312                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4313         else
4314                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4315
4316         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4317                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4318                  * core speed.
4319                  *
4320                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4321                  * pipe == 0 check?
4322                  */
4323                 if (mode->clock >
4324                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4325                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4326                 else
4327                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4328         }
4329
4330         /* default to 8bpc */
4331         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4332         if (is_dp) {
4333                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4334                         pipeconf |= PIPECONF_BPP_6 |
4335                                     PIPECONF_DITHER_EN |
4336                                     PIPECONF_DITHER_TYPE_SP;
4337                 }
4338         }
4339
4340         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4341         drm_mode_debug_printmodeline(mode);
4342
4343         if (HAS_PIPE_CXSR(dev)) {
4344                 if (intel_crtc->lowfreq_avail) {
4345                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4346                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4347                 } else {
4348                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4349                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4350                 }
4351         }
4352
4353         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4354         if (!IS_GEN2(dev) &&
4355             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4356                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4357                 /* the chip adds 2 halflines automatically */
4358                 adjusted_mode->crtc_vtotal -= 1;
4359                 adjusted_mode->crtc_vblank_end -= 1;
4360                 vsyncshift = adjusted_mode->crtc_hsync_start
4361                              - adjusted_mode->crtc_htotal/2;
4362         } else {
4363                 pipeconf |= PIPECONF_PROGRESSIVE;
4364                 vsyncshift = 0;
4365         }
4366
4367         if (!IS_GEN3(dev))
4368                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4369
4370         I915_WRITE(HTOTAL(pipe),
4371                    (adjusted_mode->crtc_hdisplay - 1) |
4372                    ((adjusted_mode->crtc_htotal - 1) << 16));
4373         I915_WRITE(HBLANK(pipe),
4374                    (adjusted_mode->crtc_hblank_start - 1) |
4375                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4376         I915_WRITE(HSYNC(pipe),
4377                    (adjusted_mode->crtc_hsync_start - 1) |
4378                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4379
4380         I915_WRITE(VTOTAL(pipe),
4381                    (adjusted_mode->crtc_vdisplay - 1) |
4382                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4383         I915_WRITE(VBLANK(pipe),
4384                    (adjusted_mode->crtc_vblank_start - 1) |
4385                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4386         I915_WRITE(VSYNC(pipe),
4387                    (adjusted_mode->crtc_vsync_start - 1) |
4388                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4389
4390         /* pipesrc and dspsize control the size that is scaled from,
4391          * which should always be the user's requested size.
4392          */
4393         I915_WRITE(DSPSIZE(plane),
4394                    ((mode->vdisplay - 1) << 16) |
4395                    (mode->hdisplay - 1));
4396         I915_WRITE(DSPPOS(plane), 0);
4397         I915_WRITE(PIPESRC(pipe),
4398                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4399
4400         I915_WRITE(PIPECONF(pipe), pipeconf);
4401         POSTING_READ(PIPECONF(pipe));
4402         intel_enable_pipe(dev_priv, pipe, false);
4403
4404         intel_wait_for_vblank(dev, pipe);
4405
4406         I915_WRITE(DSPCNTR(plane), dspcntr);
4407         POSTING_READ(DSPCNTR(plane));
4408
4409         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4410
4411         intel_update_watermarks(dev);
4412
4413         return ret;
4414 }
4415
4416 /*
4417  * Initialize reference clocks when the driver loads
4418  */
4419 void ironlake_init_pch_refclk(struct drm_device *dev)
4420 {
4421         struct drm_i915_private *dev_priv = dev->dev_private;
4422         struct drm_mode_config *mode_config = &dev->mode_config;
4423         struct intel_encoder *encoder;
4424         u32 temp;
4425         bool has_lvds = false;
4426         bool has_cpu_edp = false;
4427         bool has_pch_edp = false;
4428         bool has_panel = false;
4429         bool has_ck505 = false;
4430         bool can_ssc = false;
4431
4432         /* We need to take the global config into account */
4433         list_for_each_entry(encoder, &mode_config->encoder_list,
4434                             base.head) {
4435                 switch (encoder->type) {
4436                 case INTEL_OUTPUT_LVDS:
4437                         has_panel = true;
4438                         has_lvds = true;
4439                         break;
4440                 case INTEL_OUTPUT_EDP:
4441                         has_panel = true;
4442                         if (intel_encoder_is_pch_edp(&encoder->base))
4443                                 has_pch_edp = true;
4444                         else
4445                                 has_cpu_edp = true;
4446                         break;
4447                 }
4448         }
4449
4450         if (HAS_PCH_IBX(dev)) {
4451                 has_ck505 = dev_priv->display_clock_mode;
4452                 can_ssc = has_ck505;
4453         } else {
4454                 has_ck505 = false;
4455                 can_ssc = true;
4456         }
4457
4458         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4459                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4460                       has_ck505);
4461
4462         /* Ironlake: try to setup display ref clock before DPLL
4463          * enabling. This is only under driver's control after
4464          * PCH B stepping, previous chipset stepping should be
4465          * ignoring this setting.
4466          */
4467         temp = I915_READ(PCH_DREF_CONTROL);
4468         /* Always enable nonspread source */
4469         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4470
4471         if (has_ck505)
4472                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4473         else
4474                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4475
4476         if (has_panel) {
4477                 temp &= ~DREF_SSC_SOURCE_MASK;
4478                 temp |= DREF_SSC_SOURCE_ENABLE;
4479
4480                 /* SSC must be turned on before enabling the CPU output  */
4481                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4482                         DRM_DEBUG_KMS("Using SSC on panel\n");
4483                         temp |= DREF_SSC1_ENABLE;
4484                 } else
4485                         temp &= ~DREF_SSC1_ENABLE;
4486
4487                 /* Get SSC going before enabling the outputs */
4488                 I915_WRITE(PCH_DREF_CONTROL, temp);
4489                 POSTING_READ(PCH_DREF_CONTROL);
4490                 udelay(200);
4491
4492                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4493
4494                 /* Enable CPU source on CPU attached eDP */
4495                 if (has_cpu_edp) {
4496                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4497                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4498                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4499                         }
4500                         else
4501                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4502                 } else
4503                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4504
4505                 I915_WRITE(PCH_DREF_CONTROL, temp);
4506                 POSTING_READ(PCH_DREF_CONTROL);
4507                 udelay(200);
4508         } else {
4509                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4510
4511                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4512
4513                 /* Turn off CPU output */
4514                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4515
4516                 I915_WRITE(PCH_DREF_CONTROL, temp);
4517                 POSTING_READ(PCH_DREF_CONTROL);
4518                 udelay(200);
4519
4520                 /* Turn off the SSC source */
4521                 temp &= ~DREF_SSC_SOURCE_MASK;
4522                 temp |= DREF_SSC_SOURCE_DISABLE;
4523
4524                 /* Turn off SSC1 */
4525                 temp &= ~ DREF_SSC1_ENABLE;
4526
4527                 I915_WRITE(PCH_DREF_CONTROL, temp);
4528                 POSTING_READ(PCH_DREF_CONTROL);
4529                 udelay(200);
4530         }
4531 }
4532
4533 static int ironlake_get_refclk(struct drm_crtc *crtc)
4534 {
4535         struct drm_device *dev = crtc->dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_encoder *encoder;
4538         struct intel_encoder *edp_encoder = NULL;
4539         int num_connectors = 0;
4540         bool is_lvds = false;
4541
4542         for_each_encoder_on_crtc(dev, crtc, encoder) {
4543                 switch (encoder->type) {
4544                 case INTEL_OUTPUT_LVDS:
4545                         is_lvds = true;
4546                         break;
4547                 case INTEL_OUTPUT_EDP:
4548                         edp_encoder = encoder;
4549                         break;
4550                 }
4551                 num_connectors++;
4552         }
4553
4554         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4555                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4556                               dev_priv->lvds_ssc_freq);
4557                 return dev_priv->lvds_ssc_freq * 1000;
4558         }
4559
4560         return 120000;
4561 }
4562
4563 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4564                                   struct drm_display_mode *mode,
4565                                   struct drm_display_mode *adjusted_mode,
4566                                   int x, int y,
4567                                   struct drm_framebuffer *old_fb)
4568 {
4569         struct drm_device *dev = crtc->dev;
4570         struct drm_i915_private *dev_priv = dev->dev_private;
4571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572         int pipe = intel_crtc->pipe;
4573         int plane = intel_crtc->plane;
4574         int refclk, num_connectors = 0;
4575         intel_clock_t clock, reduced_clock;
4576         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4577         bool ok, has_reduced_clock = false, is_sdvo = false;
4578         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4579         struct intel_encoder *encoder, *edp_encoder = NULL;
4580         const intel_limit_t *limit;
4581         int ret;
4582         struct fdi_m_n m_n = {0};
4583         u32 temp;
4584         int target_clock, pixel_multiplier, lane, link_bw, factor;
4585         unsigned int pipe_bpp;
4586         bool dither;
4587         bool is_cpu_edp = false, is_pch_edp = false;
4588
4589         for_each_encoder_on_crtc(dev, crtc, encoder) {
4590                 switch (encoder->type) {
4591                 case INTEL_OUTPUT_LVDS:
4592                         is_lvds = true;
4593                         break;
4594                 case INTEL_OUTPUT_SDVO:
4595                 case INTEL_OUTPUT_HDMI:
4596                         is_sdvo = true;
4597                         if (encoder->needs_tv_clock)
4598                                 is_tv = true;
4599                         break;
4600                 case INTEL_OUTPUT_TVOUT:
4601                         is_tv = true;
4602                         break;
4603                 case INTEL_OUTPUT_ANALOG:
4604                         is_crt = true;
4605                         break;
4606                 case INTEL_OUTPUT_DISPLAYPORT:
4607                         is_dp = true;
4608                         break;
4609                 case INTEL_OUTPUT_EDP:
4610                         is_dp = true;
4611                         if (intel_encoder_is_pch_edp(&encoder->base))
4612                                 is_pch_edp = true;
4613                         else
4614                                 is_cpu_edp = true;
4615                         edp_encoder = encoder;
4616                         break;
4617                 }
4618
4619                 num_connectors++;
4620         }
4621
4622         refclk = ironlake_get_refclk(crtc);
4623
4624         /*
4625          * Returns a set of divisors for the desired target clock with the given
4626          * refclk, or FALSE.  The returned values represent the clock equation:
4627          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4628          */
4629         limit = intel_limit(crtc, refclk);
4630         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4631                              &clock);
4632         if (!ok) {
4633                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4634                 return -EINVAL;
4635         }
4636
4637         /* Ensure that the cursor is valid for the new mode before changing... */
4638         intel_crtc_update_cursor(crtc, true);
4639
4640         if (is_lvds && dev_priv->lvds_downclock_avail) {
4641                 /*
4642                  * Ensure we match the reduced clock's P to the target clock.
4643                  * If the clocks don't match, we can't switch the display clock
4644                  * by using the FP0/FP1. In such case we will disable the LVDS
4645                  * downclock feature.
4646                 */
4647                 has_reduced_clock = limit->find_pll(limit, crtc,
4648                                                     dev_priv->lvds_downclock,
4649                                                     refclk,
4650                                                     &clock,
4651                                                     &reduced_clock);
4652         }
4653
4654         if (is_sdvo && is_tv)
4655                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4656
4657
4658         /* FDI link */
4659         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4660         lane = 0;
4661         /* CPU eDP doesn't require FDI link, so just set DP M/N
4662            according to current link config */
4663         if (is_cpu_edp) {
4664                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4665         } else {
4666                 /* FDI is a binary signal running at ~2.7GHz, encoding
4667                  * each output octet as 10 bits. The actual frequency
4668                  * is stored as a divider into a 100MHz clock, and the
4669                  * mode pixel clock is stored in units of 1KHz.
4670                  * Hence the bw of each lane in terms of the mode signal
4671                  * is:
4672                  */
4673                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4674         }
4675
4676         /* [e]DP over FDI requires target mode clock instead of link clock. */
4677         if (edp_encoder)
4678                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4679         else if (is_dp)
4680                 target_clock = mode->clock;
4681         else
4682                 target_clock = adjusted_mode->clock;
4683
4684         /* determine panel color depth */
4685         temp = I915_READ(PIPECONF(pipe));
4686         temp &= ~PIPE_BPC_MASK;
4687         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4688         switch (pipe_bpp) {
4689         case 18:
4690                 temp |= PIPE_6BPC;
4691                 break;
4692         case 24:
4693                 temp |= PIPE_8BPC;
4694                 break;
4695         case 30:
4696                 temp |= PIPE_10BPC;
4697                 break;
4698         case 36:
4699                 temp |= PIPE_12BPC;
4700                 break;
4701         default:
4702                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4703                         pipe_bpp);
4704                 temp |= PIPE_8BPC;
4705                 pipe_bpp = 24;
4706                 break;
4707         }
4708
4709         intel_crtc->bpp = pipe_bpp;
4710         I915_WRITE(PIPECONF(pipe), temp);
4711
4712         if (!lane) {
4713                 /*
4714                  * Account for spread spectrum to avoid
4715                  * oversubscribing the link. Max center spread
4716                  * is 2.5%; use 5% for safety's sake.
4717                  */
4718                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4719                 lane = bps / (link_bw * 8) + 1;
4720         }
4721
4722         intel_crtc->fdi_lanes = lane;
4723
4724         if (pixel_multiplier > 1)
4725                 link_bw *= pixel_multiplier;
4726         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4727                              &m_n);
4728
4729         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4730         if (has_reduced_clock)
4731                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4732                         reduced_clock.m2;
4733
4734         /* Enable autotuning of the PLL clock (if permissible) */
4735         factor = 21;
4736         if (is_lvds) {
4737                 if ((intel_panel_use_ssc(dev_priv) &&
4738                      dev_priv->lvds_ssc_freq == 100) ||
4739                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4740                         factor = 25;
4741         } else if (is_sdvo && is_tv)
4742                 factor = 20;
4743
4744         if (clock.m < factor * clock.n)
4745                 fp |= FP_CB_TUNE;
4746
4747         dpll = 0;
4748
4749         if (is_lvds)
4750                 dpll |= DPLLB_MODE_LVDS;
4751         else
4752                 dpll |= DPLLB_MODE_DAC_SERIAL;
4753         if (is_sdvo) {
4754                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4755                 if (pixel_multiplier > 1) {
4756                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4757                 }
4758                 dpll |= DPLL_DVO_HIGH_SPEED;
4759         }
4760         if (is_dp && !is_cpu_edp)
4761                 dpll |= DPLL_DVO_HIGH_SPEED;
4762
4763         /* compute bitmask from p1 value */
4764         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4765         /* also FPA1 */
4766         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4767
4768         switch (clock.p2) {
4769         case 5:
4770                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4771                 break;
4772         case 7:
4773                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4774                 break;
4775         case 10:
4776                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4777                 break;
4778         case 14:
4779                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4780                 break;
4781         }
4782
4783         if (is_sdvo && is_tv)
4784                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4785         else if (is_tv)
4786                 /* XXX: just matching BIOS for now */
4787                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4788                 dpll |= 3;
4789         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4790                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4791         else
4792                 dpll |= PLL_REF_INPUT_DREFCLK;
4793
4794         /* setup pipeconf */
4795         pipeconf = I915_READ(PIPECONF(pipe));
4796
4797         /* Set up the display plane register */
4798         dspcntr = DISPPLANE_GAMMA_ENABLE;
4799
4800         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4801         drm_mode_debug_printmodeline(mode);
4802
4803         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4804          * pre-Haswell/LPT generation */
4805         if (HAS_PCH_LPT(dev)) {
4806                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4807                                 pipe);
4808         } else if (!is_cpu_edp) {
4809                 struct intel_pch_pll *pll;
4810
4811                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4812                 if (pll == NULL) {
4813                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4814                                          pipe);
4815                         return -EINVAL;
4816                 }
4817         } else
4818                 intel_put_pch_pll(intel_crtc);
4819
4820         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4821          * This is an exception to the general rule that mode_set doesn't turn
4822          * things on.
4823          */
4824         if (is_lvds) {
4825                 temp = I915_READ(PCH_LVDS);
4826                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4827                 if (HAS_PCH_CPT(dev)) {
4828                         temp &= ~PORT_TRANS_SEL_MASK;
4829                         temp |= PORT_TRANS_SEL_CPT(pipe);
4830                 } else {
4831                         if (pipe == 1)
4832                                 temp |= LVDS_PIPEB_SELECT;
4833                         else
4834                                 temp &= ~LVDS_PIPEB_SELECT;
4835                 }
4836
4837                 /* set the corresponsding LVDS_BORDER bit */
4838                 temp |= dev_priv->lvds_border_bits;
4839                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4840                  * set the DPLLs for dual-channel mode or not.
4841                  */
4842                 if (clock.p2 == 7)
4843                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4844                 else
4845                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4846
4847                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4848                  * appropriately here, but we need to look more thoroughly into how
4849                  * panels behave in the two modes.
4850                  */
4851                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4852                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4853                         temp |= LVDS_HSYNC_POLARITY;
4854                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4855                         temp |= LVDS_VSYNC_POLARITY;
4856                 I915_WRITE(PCH_LVDS, temp);
4857         }
4858
4859         pipeconf &= ~PIPECONF_DITHER_EN;
4860         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4861         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4862                 pipeconf |= PIPECONF_DITHER_EN;
4863                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4864         }
4865         if (is_dp && !is_cpu_edp) {
4866                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4867         } else {
4868                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4869                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4870                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4871                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4872                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4873         }
4874
4875         if (intel_crtc->pch_pll) {
4876                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4877
4878                 /* Wait for the clocks to stabilize. */
4879                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4880                 udelay(150);
4881
4882                 /* The pixel multiplier can only be updated once the
4883                  * DPLL is enabled and the clocks are stable.
4884                  *
4885                  * So write it again.
4886                  */
4887                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4888         }
4889
4890         intel_crtc->lowfreq_avail = false;
4891         if (intel_crtc->pch_pll) {
4892                 if (is_lvds && has_reduced_clock && i915_powersave) {
4893                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4894                         intel_crtc->lowfreq_avail = true;
4895                 } else {
4896                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4897                 }
4898         }
4899
4900         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4901         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4902                 pipeconf |= PIPECONF_INTERLACED_ILK;
4903                 /* the chip adds 2 halflines automatically */
4904                 adjusted_mode->crtc_vtotal -= 1;
4905                 adjusted_mode->crtc_vblank_end -= 1;
4906                 I915_WRITE(VSYNCSHIFT(pipe),
4907                            adjusted_mode->crtc_hsync_start
4908                            - adjusted_mode->crtc_htotal/2);
4909         } else {
4910                 pipeconf |= PIPECONF_PROGRESSIVE;
4911                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4912         }
4913
4914         I915_WRITE(HTOTAL(pipe),
4915                    (adjusted_mode->crtc_hdisplay - 1) |
4916                    ((adjusted_mode->crtc_htotal - 1) << 16));
4917         I915_WRITE(HBLANK(pipe),
4918                    (adjusted_mode->crtc_hblank_start - 1) |
4919                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4920         I915_WRITE(HSYNC(pipe),
4921                    (adjusted_mode->crtc_hsync_start - 1) |
4922                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4923
4924         I915_WRITE(VTOTAL(pipe),
4925                    (adjusted_mode->crtc_vdisplay - 1) |
4926                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4927         I915_WRITE(VBLANK(pipe),
4928                    (adjusted_mode->crtc_vblank_start - 1) |
4929                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4930         I915_WRITE(VSYNC(pipe),
4931                    (adjusted_mode->crtc_vsync_start - 1) |
4932                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4933
4934         /* pipesrc controls the size that is scaled from, which should
4935          * always be the user's requested size.
4936          */
4937         I915_WRITE(PIPESRC(pipe),
4938                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4939
4940         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4941         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4942         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4943         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4944
4945         if (is_cpu_edp)
4946                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4947
4948         I915_WRITE(PIPECONF(pipe), pipeconf);
4949         POSTING_READ(PIPECONF(pipe));
4950
4951         intel_wait_for_vblank(dev, pipe);
4952
4953         I915_WRITE(DSPCNTR(plane), dspcntr);
4954         POSTING_READ(DSPCNTR(plane));
4955
4956         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4957
4958         intel_update_watermarks(dev);
4959
4960         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4961
4962         return ret;
4963 }
4964
4965 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4966                                struct drm_display_mode *mode,
4967                                struct drm_display_mode *adjusted_mode,
4968                                int x, int y,
4969                                struct drm_framebuffer *old_fb)
4970 {
4971         struct drm_device *dev = crtc->dev;
4972         struct drm_i915_private *dev_priv = dev->dev_private;
4973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974         int pipe = intel_crtc->pipe;
4975         int ret;
4976
4977         drm_vblank_pre_modeset(dev, pipe);
4978
4979         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4980                                               x, y, old_fb);
4981         drm_vblank_post_modeset(dev, pipe);
4982
4983         if (ret)
4984                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4985         else
4986                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4987
4988         return ret;
4989 }
4990
4991 static bool intel_eld_uptodate(struct drm_connector *connector,
4992                                int reg_eldv, uint32_t bits_eldv,
4993                                int reg_elda, uint32_t bits_elda,
4994                                int reg_edid)
4995 {
4996         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4997         uint8_t *eld = connector->eld;
4998         uint32_t i;
4999
5000         i = I915_READ(reg_eldv);
5001         i &= bits_eldv;
5002
5003         if (!eld[0])
5004                 return !i;
5005
5006         if (!i)
5007                 return false;
5008
5009         i = I915_READ(reg_elda);
5010         i &= ~bits_elda;
5011         I915_WRITE(reg_elda, i);
5012
5013         for (i = 0; i < eld[2]; i++)
5014                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5015                         return false;
5016
5017         return true;
5018 }
5019
5020 static void g4x_write_eld(struct drm_connector *connector,
5021                           struct drm_crtc *crtc)
5022 {
5023         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5024         uint8_t *eld = connector->eld;
5025         uint32_t eldv;
5026         uint32_t len;
5027         uint32_t i;
5028
5029         i = I915_READ(G4X_AUD_VID_DID);
5030
5031         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5032                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5033         else
5034                 eldv = G4X_ELDV_DEVCTG;
5035
5036         if (intel_eld_uptodate(connector,
5037                                G4X_AUD_CNTL_ST, eldv,
5038                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5039                                G4X_HDMIW_HDMIEDID))
5040                 return;
5041
5042         i = I915_READ(G4X_AUD_CNTL_ST);
5043         i &= ~(eldv | G4X_ELD_ADDR);
5044         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5045         I915_WRITE(G4X_AUD_CNTL_ST, i);
5046
5047         if (!eld[0])
5048                 return;
5049
5050         len = min_t(uint8_t, eld[2], len);
5051         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5052         for (i = 0; i < len; i++)
5053                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5054
5055         i = I915_READ(G4X_AUD_CNTL_ST);
5056         i |= eldv;
5057         I915_WRITE(G4X_AUD_CNTL_ST, i);
5058 }
5059
5060 static void ironlake_write_eld(struct drm_connector *connector,
5061                                      struct drm_crtc *crtc)
5062 {
5063         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5064         uint8_t *eld = connector->eld;
5065         uint32_t eldv;
5066         uint32_t i;
5067         int len;
5068         int hdmiw_hdmiedid;
5069         int aud_config;
5070         int aud_cntl_st;
5071         int aud_cntrl_st2;
5072
5073         if (HAS_PCH_IBX(connector->dev)) {
5074                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
5075                 aud_config = IBX_AUD_CONFIG_A;
5076                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5077                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5078         } else {
5079                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
5080                 aud_config = CPT_AUD_CONFIG_A;
5081                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5082                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5083         }
5084
5085         i = to_intel_crtc(crtc)->pipe;
5086         hdmiw_hdmiedid += i * 0x100;
5087         aud_cntl_st += i * 0x100;
5088         aud_config += i * 0x100;
5089
5090         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5091
5092         i = I915_READ(aud_cntl_st);
5093         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5094         if (!i) {
5095                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5096                 /* operate blindly on all ports */
5097                 eldv = IBX_ELD_VALIDB;
5098                 eldv |= IBX_ELD_VALIDB << 4;
5099                 eldv |= IBX_ELD_VALIDB << 8;
5100         } else {
5101                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5102                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5103         }
5104
5105         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5106                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5107                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5108                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5109         } else
5110                 I915_WRITE(aud_config, 0);
5111
5112         if (intel_eld_uptodate(connector,
5113                                aud_cntrl_st2, eldv,
5114                                aud_cntl_st, IBX_ELD_ADDRESS,
5115                                hdmiw_hdmiedid))
5116                 return;
5117
5118         i = I915_READ(aud_cntrl_st2);
5119         i &= ~eldv;
5120         I915_WRITE(aud_cntrl_st2, i);
5121
5122         if (!eld[0])
5123                 return;
5124
5125         i = I915_READ(aud_cntl_st);
5126         i &= ~IBX_ELD_ADDRESS;
5127         I915_WRITE(aud_cntl_st, i);
5128
5129         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5130         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5131         for (i = 0; i < len; i++)
5132                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5133
5134         i = I915_READ(aud_cntrl_st2);
5135         i |= eldv;
5136         I915_WRITE(aud_cntrl_st2, i);
5137 }
5138
5139 void intel_write_eld(struct drm_encoder *encoder,
5140                      struct drm_display_mode *mode)
5141 {
5142         struct drm_crtc *crtc = encoder->crtc;
5143         struct drm_connector *connector;
5144         struct drm_device *dev = encoder->dev;
5145         struct drm_i915_private *dev_priv = dev->dev_private;
5146
5147         connector = drm_select_eld(encoder, mode);
5148         if (!connector)
5149                 return;
5150
5151         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5152                          connector->base.id,
5153                          drm_get_connector_name(connector),
5154                          connector->encoder->base.id,
5155                          drm_get_encoder_name(connector->encoder));
5156
5157         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5158
5159         if (dev_priv->display.write_eld)
5160                 dev_priv->display.write_eld(connector, crtc);
5161 }
5162
5163 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5164 void intel_crtc_load_lut(struct drm_crtc *crtc)
5165 {
5166         struct drm_device *dev = crtc->dev;
5167         struct drm_i915_private *dev_priv = dev->dev_private;
5168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5169         int palreg = PALETTE(intel_crtc->pipe);
5170         int i;
5171
5172         /* The clocks have to be on to load the palette. */
5173         if (!crtc->enabled || !intel_crtc->active)
5174                 return;
5175
5176         /* use legacy palette for Ironlake */
5177         if (HAS_PCH_SPLIT(dev))
5178                 palreg = LGC_PALETTE(intel_crtc->pipe);
5179
5180         for (i = 0; i < 256; i++) {
5181                 I915_WRITE(palreg + 4 * i,
5182                            (intel_crtc->lut_r[i] << 16) |
5183                            (intel_crtc->lut_g[i] << 8) |
5184                            intel_crtc->lut_b[i]);
5185         }
5186 }
5187
5188 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5189 {
5190         struct drm_device *dev = crtc->dev;
5191         struct drm_i915_private *dev_priv = dev->dev_private;
5192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5193         bool visible = base != 0;
5194         u32 cntl;
5195
5196         if (intel_crtc->cursor_visible == visible)
5197                 return;
5198
5199         cntl = I915_READ(_CURACNTR);
5200         if (visible) {
5201                 /* On these chipsets we can only modify the base whilst
5202                  * the cursor is disabled.
5203                  */
5204                 I915_WRITE(_CURABASE, base);
5205
5206                 cntl &= ~(CURSOR_FORMAT_MASK);
5207                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5208                 cntl |= CURSOR_ENABLE |
5209                         CURSOR_GAMMA_ENABLE |
5210                         CURSOR_FORMAT_ARGB;
5211         } else
5212                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5213         I915_WRITE(_CURACNTR, cntl);
5214
5215         intel_crtc->cursor_visible = visible;
5216 }
5217
5218 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5219 {
5220         struct drm_device *dev = crtc->dev;
5221         struct drm_i915_private *dev_priv = dev->dev_private;
5222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223         int pipe = intel_crtc->pipe;
5224         bool visible = base != 0;
5225
5226         if (intel_crtc->cursor_visible != visible) {
5227                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5228                 if (base) {
5229                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5230                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5231                         cntl |= pipe << 28; /* Connect to correct pipe */
5232                 } else {
5233                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5234                         cntl |= CURSOR_MODE_DISABLE;
5235                 }
5236                 I915_WRITE(CURCNTR(pipe), cntl);
5237
5238                 intel_crtc->cursor_visible = visible;
5239         }
5240         /* and commit changes on next vblank */
5241         I915_WRITE(CURBASE(pipe), base);
5242 }
5243
5244 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5245 {
5246         struct drm_device *dev = crtc->dev;
5247         struct drm_i915_private *dev_priv = dev->dev_private;
5248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249         int pipe = intel_crtc->pipe;
5250         bool visible = base != 0;
5251
5252         if (intel_crtc->cursor_visible != visible) {
5253                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5254                 if (base) {
5255                         cntl &= ~CURSOR_MODE;
5256                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5257                 } else {
5258                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5259                         cntl |= CURSOR_MODE_DISABLE;
5260                 }
5261                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5262
5263                 intel_crtc->cursor_visible = visible;
5264         }
5265         /* and commit changes on next vblank */
5266         I915_WRITE(CURBASE_IVB(pipe), base);
5267 }
5268
5269 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5270 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5271                                      bool on)
5272 {
5273         struct drm_device *dev = crtc->dev;
5274         struct drm_i915_private *dev_priv = dev->dev_private;
5275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5276         int pipe = intel_crtc->pipe;
5277         int x = intel_crtc->cursor_x;
5278         int y = intel_crtc->cursor_y;
5279         u32 base, pos;
5280         bool visible;
5281
5282         pos = 0;
5283
5284         if (on && crtc->enabled && crtc->fb) {
5285                 base = intel_crtc->cursor_addr;
5286                 if (x > (int) crtc->fb->width)
5287                         base = 0;
5288
5289                 if (y > (int) crtc->fb->height)
5290                         base = 0;
5291         } else
5292                 base = 0;
5293
5294         if (x < 0) {
5295                 if (x + intel_crtc->cursor_width < 0)
5296                         base = 0;
5297
5298                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5299                 x = -x;
5300         }
5301         pos |= x << CURSOR_X_SHIFT;
5302
5303         if (y < 0) {
5304                 if (y + intel_crtc->cursor_height < 0)
5305                         base = 0;
5306
5307                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5308                 y = -y;
5309         }
5310         pos |= y << CURSOR_Y_SHIFT;
5311
5312         visible = base != 0;
5313         if (!visible && !intel_crtc->cursor_visible)
5314                 return;
5315
5316         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5317                 I915_WRITE(CURPOS_IVB(pipe), pos);
5318                 ivb_update_cursor(crtc, base);
5319         } else {
5320                 I915_WRITE(CURPOS(pipe), pos);
5321                 if (IS_845G(dev) || IS_I865G(dev))
5322                         i845_update_cursor(crtc, base);
5323                 else
5324                         i9xx_update_cursor(crtc, base);
5325         }
5326 }
5327
5328 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5329                                  struct drm_file *file,
5330                                  uint32_t handle,
5331                                  uint32_t width, uint32_t height)
5332 {
5333         struct drm_device *dev = crtc->dev;
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5336         struct drm_i915_gem_object *obj;
5337         uint32_t addr;
5338         int ret;
5339
5340         DRM_DEBUG_KMS("\n");
5341
5342         /* if we want to turn off the cursor ignore width and height */
5343         if (!handle) {
5344                 DRM_DEBUG_KMS("cursor off\n");
5345                 addr = 0;
5346                 obj = NULL;
5347                 mutex_lock(&dev->struct_mutex);
5348                 goto finish;
5349         }
5350
5351         /* Currently we only support 64x64 cursors */
5352         if (width != 64 || height != 64) {
5353                 DRM_ERROR("we currently only support 64x64 cursors\n");
5354                 return -EINVAL;
5355         }
5356
5357         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5358         if (&obj->base == NULL)
5359                 return -ENOENT;
5360
5361         if (obj->base.size < width * height * 4) {
5362                 DRM_ERROR("buffer is to small\n");
5363                 ret = -ENOMEM;
5364                 goto fail;
5365         }
5366
5367         /* we only need to pin inside GTT if cursor is non-phy */
5368         mutex_lock(&dev->struct_mutex);
5369         if (!dev_priv->info->cursor_needs_physical) {
5370                 if (obj->tiling_mode) {
5371                         DRM_ERROR("cursor cannot be tiled\n");
5372                         ret = -EINVAL;
5373                         goto fail_locked;
5374                 }
5375
5376                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5377                 if (ret) {
5378                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5379                         goto fail_locked;
5380                 }
5381
5382                 ret = i915_gem_object_put_fence(obj);
5383                 if (ret) {
5384                         DRM_ERROR("failed to release fence for cursor");
5385                         goto fail_unpin;
5386                 }
5387
5388                 addr = obj->gtt_offset;
5389         } else {
5390                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5391                 ret = i915_gem_attach_phys_object(dev, obj,
5392                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5393                                                   align);
5394                 if (ret) {
5395                         DRM_ERROR("failed to attach phys object\n");
5396                         goto fail_locked;
5397                 }
5398                 addr = obj->phys_obj->handle->busaddr;
5399         }
5400
5401         if (IS_GEN2(dev))
5402                 I915_WRITE(CURSIZE, (height << 12) | width);
5403
5404  finish:
5405         if (intel_crtc->cursor_bo) {
5406                 if (dev_priv->info->cursor_needs_physical) {
5407                         if (intel_crtc->cursor_bo != obj)
5408                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5409                 } else
5410                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5411                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5412         }
5413
5414         mutex_unlock(&dev->struct_mutex);
5415
5416         intel_crtc->cursor_addr = addr;
5417         intel_crtc->cursor_bo = obj;
5418         intel_crtc->cursor_width = width;
5419         intel_crtc->cursor_height = height;
5420
5421         intel_crtc_update_cursor(crtc, true);
5422
5423         return 0;
5424 fail_unpin:
5425         i915_gem_object_unpin(obj);
5426 fail_locked:
5427         mutex_unlock(&dev->struct_mutex);
5428 fail:
5429         drm_gem_object_unreference_unlocked(&obj->base);
5430         return ret;
5431 }
5432
5433 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5434 {
5435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5436
5437         intel_crtc->cursor_x = x;
5438         intel_crtc->cursor_y = y;
5439
5440         intel_crtc_update_cursor(crtc, true);
5441
5442         return 0;
5443 }
5444
5445 /** Sets the color ramps on behalf of RandR */
5446 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5447                                  u16 blue, int regno)
5448 {
5449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450
5451         intel_crtc->lut_r[regno] = red >> 8;
5452         intel_crtc->lut_g[regno] = green >> 8;
5453         intel_crtc->lut_b[regno] = blue >> 8;
5454 }
5455
5456 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5457                              u16 *blue, int regno)
5458 {
5459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460
5461         *red = intel_crtc->lut_r[regno] << 8;
5462         *green = intel_crtc->lut_g[regno] << 8;
5463         *blue = intel_crtc->lut_b[regno] << 8;
5464 }
5465
5466 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5467                                  u16 *blue, uint32_t start, uint32_t size)
5468 {
5469         int end = (start + size > 256) ? 256 : start + size, i;
5470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5471
5472         for (i = start; i < end; i++) {
5473                 intel_crtc->lut_r[i] = red[i] >> 8;
5474                 intel_crtc->lut_g[i] = green[i] >> 8;
5475                 intel_crtc->lut_b[i] = blue[i] >> 8;
5476         }
5477
5478         intel_crtc_load_lut(crtc);
5479 }
5480
5481 /**
5482  * Get a pipe with a simple mode set on it for doing load-based monitor
5483  * detection.
5484  *
5485  * It will be up to the load-detect code to adjust the pipe as appropriate for
5486  * its requirements.  The pipe will be connected to no other encoders.
5487  *
5488  * Currently this code will only succeed if there is a pipe with no encoders
5489  * configured for it.  In the future, it could choose to temporarily disable
5490  * some outputs to free up a pipe for its use.
5491  *
5492  * \return crtc, or NULL if no pipes are available.
5493  */
5494
5495 /* VESA 640x480x72Hz mode to set on the pipe */
5496 static struct drm_display_mode load_detect_mode = {
5497         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5498                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5499 };
5500
5501 static struct drm_framebuffer *
5502 intel_framebuffer_create(struct drm_device *dev,
5503                          struct drm_mode_fb_cmd2 *mode_cmd,
5504                          struct drm_i915_gem_object *obj)
5505 {
5506         struct intel_framebuffer *intel_fb;
5507         int ret;
5508
5509         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5510         if (!intel_fb) {
5511                 drm_gem_object_unreference_unlocked(&obj->base);
5512                 return ERR_PTR(-ENOMEM);
5513         }
5514
5515         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5516         if (ret) {
5517                 drm_gem_object_unreference_unlocked(&obj->base);
5518                 kfree(intel_fb);
5519                 return ERR_PTR(ret);
5520         }
5521
5522         return &intel_fb->base;
5523 }
5524
5525 static u32
5526 intel_framebuffer_pitch_for_width(int width, int bpp)
5527 {
5528         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5529         return ALIGN(pitch, 64);
5530 }
5531
5532 static u32
5533 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5534 {
5535         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5536         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5537 }
5538
5539 static struct drm_framebuffer *
5540 intel_framebuffer_create_for_mode(struct drm_device *dev,
5541                                   struct drm_display_mode *mode,
5542                                   int depth, int bpp)
5543 {
5544         struct drm_i915_gem_object *obj;
5545         struct drm_mode_fb_cmd2 mode_cmd;
5546
5547         obj = i915_gem_alloc_object(dev,
5548                                     intel_framebuffer_size_for_mode(mode, bpp));
5549         if (obj == NULL)
5550                 return ERR_PTR(-ENOMEM);
5551
5552         mode_cmd.width = mode->hdisplay;
5553         mode_cmd.height = mode->vdisplay;
5554         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5555                                                                 bpp);
5556         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5557
5558         return intel_framebuffer_create(dev, &mode_cmd, obj);
5559 }
5560
5561 static struct drm_framebuffer *
5562 mode_fits_in_fbdev(struct drm_device *dev,
5563                    struct drm_display_mode *mode)
5564 {
5565         struct drm_i915_private *dev_priv = dev->dev_private;
5566         struct drm_i915_gem_object *obj;
5567         struct drm_framebuffer *fb;
5568
5569         if (dev_priv->fbdev == NULL)
5570                 return NULL;
5571
5572         obj = dev_priv->fbdev->ifb.obj;
5573         if (obj == NULL)
5574                 return NULL;
5575
5576         fb = &dev_priv->fbdev->ifb.base;
5577         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5578                                                                fb->bits_per_pixel))
5579                 return NULL;
5580
5581         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5582                 return NULL;
5583
5584         return fb;
5585 }
5586
5587 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5588                                 struct drm_connector *connector,
5589                                 struct drm_display_mode *mode,
5590                                 struct intel_load_detect_pipe *old)
5591 {
5592         struct intel_crtc *intel_crtc;
5593         struct drm_crtc *possible_crtc;
5594         struct drm_encoder *encoder = &intel_encoder->base;
5595         struct drm_crtc *crtc = NULL;
5596         struct drm_device *dev = encoder->dev;
5597         struct drm_framebuffer *old_fb;
5598         int i = -1;
5599
5600         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5601                       connector->base.id, drm_get_connector_name(connector),
5602                       encoder->base.id, drm_get_encoder_name(encoder));
5603
5604         /*
5605          * Algorithm gets a little messy:
5606          *
5607          *   - if the connector already has an assigned crtc, use it (but make
5608          *     sure it's on first)
5609          *
5610          *   - try to find the first unused crtc that can drive this connector,
5611          *     and use that if we find one
5612          */
5613
5614         /* See if we already have a CRTC for this connector */
5615         if (encoder->crtc) {
5616                 crtc = encoder->crtc;
5617
5618                 intel_crtc = to_intel_crtc(crtc);
5619                 old->dpms_mode = intel_crtc->dpms_mode;
5620                 old->load_detect_temp = false;
5621
5622                 /* Make sure the crtc and connector are running */
5623                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5624                         struct drm_encoder_helper_funcs *encoder_funcs;
5625                         struct drm_crtc_helper_funcs *crtc_funcs;
5626
5627                         crtc_funcs = crtc->helper_private;
5628                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5629
5630                         encoder_funcs = encoder->helper_private;
5631                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5632                 }
5633
5634                 return true;
5635         }
5636
5637         /* Find an unused one (if possible) */
5638         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5639                 i++;
5640                 if (!(encoder->possible_crtcs & (1 << i)))
5641                         continue;
5642                 if (!possible_crtc->enabled) {
5643                         crtc = possible_crtc;
5644                         break;
5645                 }
5646         }
5647
5648         /*
5649          * If we didn't find an unused CRTC, don't use any.
5650          */
5651         if (!crtc) {
5652                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5653                 return false;
5654         }
5655
5656         encoder->crtc = crtc;
5657         connector->encoder = encoder;
5658
5659         intel_crtc = to_intel_crtc(crtc);
5660         old->dpms_mode = intel_crtc->dpms_mode;
5661         old->load_detect_temp = true;
5662         old->release_fb = NULL;
5663
5664         if (!mode)
5665                 mode = &load_detect_mode;
5666
5667         old_fb = crtc->fb;
5668
5669         /* We need a framebuffer large enough to accommodate all accesses
5670          * that the plane may generate whilst we perform load detection.
5671          * We can not rely on the fbcon either being present (we get called
5672          * during its initialisation to detect all boot displays, or it may
5673          * not even exist) or that it is large enough to satisfy the
5674          * requested mode.
5675          */
5676         crtc->fb = mode_fits_in_fbdev(dev, mode);
5677         if (crtc->fb == NULL) {
5678                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5679                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5680                 old->release_fb = crtc->fb;
5681         } else
5682                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5683         if (IS_ERR(crtc->fb)) {
5684                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5685                 crtc->fb = old_fb;
5686                 return false;
5687         }
5688
5689         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5690                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5691                 if (old->release_fb)
5692                         old->release_fb->funcs->destroy(old->release_fb);
5693                 crtc->fb = old_fb;
5694                 return false;
5695         }
5696
5697         /* let the connector get through one full cycle before testing */
5698         intel_wait_for_vblank(dev, intel_crtc->pipe);
5699
5700         return true;
5701 }
5702
5703 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5704                                     struct drm_connector *connector,
5705                                     struct intel_load_detect_pipe *old)
5706 {
5707         struct drm_encoder *encoder = &intel_encoder->base;
5708         struct drm_device *dev = encoder->dev;
5709         struct drm_crtc *crtc = encoder->crtc;
5710         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5711         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5712
5713         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5714                       connector->base.id, drm_get_connector_name(connector),
5715                       encoder->base.id, drm_get_encoder_name(encoder));
5716
5717         if (old->load_detect_temp) {
5718                 connector->encoder = NULL;
5719                 drm_helper_disable_unused_functions(dev);
5720
5721                 if (old->release_fb)
5722                         old->release_fb->funcs->destroy(old->release_fb);
5723
5724                 return;
5725         }
5726
5727         /* Switch crtc and encoder back off if necessary */
5728         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5729                 encoder_funcs->dpms(encoder, old->dpms_mode);
5730                 crtc_funcs->dpms(crtc, old->dpms_mode);
5731         }
5732 }
5733
5734 /* Returns the clock of the currently programmed mode of the given pipe. */
5735 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5736 {
5737         struct drm_i915_private *dev_priv = dev->dev_private;
5738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5739         int pipe = intel_crtc->pipe;
5740         u32 dpll = I915_READ(DPLL(pipe));
5741         u32 fp;
5742         intel_clock_t clock;
5743
5744         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5745                 fp = I915_READ(FP0(pipe));
5746         else
5747                 fp = I915_READ(FP1(pipe));
5748
5749         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5750         if (IS_PINEVIEW(dev)) {
5751                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5752                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5753         } else {
5754                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5755                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5756         }
5757
5758         if (!IS_GEN2(dev)) {
5759                 if (IS_PINEVIEW(dev))
5760                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5761                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5762                 else
5763                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5764                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5765
5766                 switch (dpll & DPLL_MODE_MASK) {
5767                 case DPLLB_MODE_DAC_SERIAL:
5768                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5769                                 5 : 10;
5770                         break;
5771                 case DPLLB_MODE_LVDS:
5772                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5773                                 7 : 14;
5774                         break;
5775                 default:
5776                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5777                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5778                         return 0;
5779                 }
5780
5781                 /* XXX: Handle the 100Mhz refclk */
5782                 intel_clock(dev, 96000, &clock);
5783         } else {
5784                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5785
5786                 if (is_lvds) {
5787                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5788                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5789                         clock.p2 = 14;
5790
5791                         if ((dpll & PLL_REF_INPUT_MASK) ==
5792                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5793                                 /* XXX: might not be 66MHz */
5794                                 intel_clock(dev, 66000, &clock);
5795                         } else
5796                                 intel_clock(dev, 48000, &clock);
5797                 } else {
5798                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5799                                 clock.p1 = 2;
5800                         else {
5801                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5802                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5803                         }
5804                         if (dpll & PLL_P2_DIVIDE_BY_4)
5805                                 clock.p2 = 4;
5806                         else
5807                                 clock.p2 = 2;
5808
5809                         intel_clock(dev, 48000, &clock);
5810                 }
5811         }
5812
5813         /* XXX: It would be nice to validate the clocks, but we can't reuse
5814          * i830PllIsValid() because it relies on the xf86_config connector
5815          * configuration being accurate, which it isn't necessarily.
5816          */
5817
5818         return clock.dot;
5819 }
5820
5821 /** Returns the currently programmed mode of the given pipe. */
5822 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5823                                              struct drm_crtc *crtc)
5824 {
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5827         int pipe = intel_crtc->pipe;
5828         struct drm_display_mode *mode;
5829         int htot = I915_READ(HTOTAL(pipe));
5830         int hsync = I915_READ(HSYNC(pipe));
5831         int vtot = I915_READ(VTOTAL(pipe));
5832         int vsync = I915_READ(VSYNC(pipe));
5833
5834         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5835         if (!mode)
5836                 return NULL;
5837
5838         mode->clock = intel_crtc_clock_get(dev, crtc);
5839         mode->hdisplay = (htot & 0xffff) + 1;
5840         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5841         mode->hsync_start = (hsync & 0xffff) + 1;
5842         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5843         mode->vdisplay = (vtot & 0xffff) + 1;
5844         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5845         mode->vsync_start = (vsync & 0xffff) + 1;
5846         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5847
5848         drm_mode_set_name(mode);
5849
5850         return mode;
5851 }
5852
5853 static void intel_increase_pllclock(struct drm_crtc *crtc)
5854 {
5855         struct drm_device *dev = crtc->dev;
5856         drm_i915_private_t *dev_priv = dev->dev_private;
5857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5858         int pipe = intel_crtc->pipe;
5859         int dpll_reg = DPLL(pipe);
5860         int dpll;
5861
5862         if (HAS_PCH_SPLIT(dev))
5863                 return;
5864
5865         if (!dev_priv->lvds_downclock_avail)
5866                 return;
5867
5868         dpll = I915_READ(dpll_reg);
5869         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5870                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5871
5872                 assert_panel_unlocked(dev_priv, pipe);
5873
5874                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5875                 I915_WRITE(dpll_reg, dpll);
5876                 intel_wait_for_vblank(dev, pipe);
5877
5878                 dpll = I915_READ(dpll_reg);
5879                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5880                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5881         }
5882 }
5883
5884 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5885 {
5886         struct drm_device *dev = crtc->dev;
5887         drm_i915_private_t *dev_priv = dev->dev_private;
5888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889
5890         if (HAS_PCH_SPLIT(dev))
5891                 return;
5892
5893         if (!dev_priv->lvds_downclock_avail)
5894                 return;
5895
5896         /*
5897          * Since this is called by a timer, we should never get here in
5898          * the manual case.
5899          */
5900         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5901                 int pipe = intel_crtc->pipe;
5902                 int dpll_reg = DPLL(pipe);
5903                 int dpll;
5904
5905                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5906
5907                 assert_panel_unlocked(dev_priv, pipe);
5908
5909                 dpll = I915_READ(dpll_reg);
5910                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5911                 I915_WRITE(dpll_reg, dpll);
5912                 intel_wait_for_vblank(dev, pipe);
5913                 dpll = I915_READ(dpll_reg);
5914                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5915                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5916         }
5917
5918 }
5919
5920 void intel_mark_busy(struct drm_device *dev)
5921 {
5922         i915_update_gfx_val(dev->dev_private);
5923 }
5924
5925 void intel_mark_idle(struct drm_device *dev)
5926 {
5927 }
5928
5929 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
5930 {
5931         struct drm_device *dev = obj->base.dev;
5932         struct drm_crtc *crtc;
5933
5934         if (!i915_powersave)
5935                 return;
5936
5937         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5938                 if (!crtc->fb)
5939                         continue;
5940
5941                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5942                         intel_increase_pllclock(crtc);
5943         }
5944 }
5945
5946 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
5947 {
5948         struct drm_device *dev = obj->base.dev;
5949         struct drm_crtc *crtc;
5950
5951         if (!i915_powersave)
5952                 return;
5953
5954         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5955                 if (!crtc->fb)
5956                         continue;
5957
5958                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5959                         intel_decrease_pllclock(crtc);
5960         }
5961 }
5962
5963 static void intel_crtc_destroy(struct drm_crtc *crtc)
5964 {
5965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5966         struct drm_device *dev = crtc->dev;
5967         struct intel_unpin_work *work;
5968         unsigned long flags;
5969
5970         spin_lock_irqsave(&dev->event_lock, flags);
5971         work = intel_crtc->unpin_work;
5972         intel_crtc->unpin_work = NULL;
5973         spin_unlock_irqrestore(&dev->event_lock, flags);
5974
5975         if (work) {
5976                 cancel_work_sync(&work->work);
5977                 kfree(work);
5978         }
5979
5980         drm_crtc_cleanup(crtc);
5981
5982         kfree(intel_crtc);
5983 }
5984
5985 static void intel_unpin_work_fn(struct work_struct *__work)
5986 {
5987         struct intel_unpin_work *work =
5988                 container_of(__work, struct intel_unpin_work, work);
5989
5990         mutex_lock(&work->dev->struct_mutex);
5991         intel_unpin_fb_obj(work->old_fb_obj);
5992         drm_gem_object_unreference(&work->pending_flip_obj->base);
5993         drm_gem_object_unreference(&work->old_fb_obj->base);
5994
5995         intel_update_fbc(work->dev);
5996         mutex_unlock(&work->dev->struct_mutex);
5997         kfree(work);
5998 }
5999
6000 static void do_intel_finish_page_flip(struct drm_device *dev,
6001                                       struct drm_crtc *crtc)
6002 {
6003         drm_i915_private_t *dev_priv = dev->dev_private;
6004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6005         struct intel_unpin_work *work;
6006         struct drm_i915_gem_object *obj;
6007         struct drm_pending_vblank_event *e;
6008         struct timeval tnow, tvbl;
6009         unsigned long flags;
6010
6011         /* Ignore early vblank irqs */
6012         if (intel_crtc == NULL)
6013                 return;
6014
6015         do_gettimeofday(&tnow);
6016
6017         spin_lock_irqsave(&dev->event_lock, flags);
6018         work = intel_crtc->unpin_work;
6019         if (work == NULL || !work->pending) {
6020                 spin_unlock_irqrestore(&dev->event_lock, flags);
6021                 return;
6022         }
6023
6024         intel_crtc->unpin_work = NULL;
6025
6026         if (work->event) {
6027                 e = work->event;
6028                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6029
6030                 /* Called before vblank count and timestamps have
6031                  * been updated for the vblank interval of flip
6032                  * completion? Need to increment vblank count and
6033                  * add one videorefresh duration to returned timestamp
6034                  * to account for this. We assume this happened if we
6035                  * get called over 0.9 frame durations after the last
6036                  * timestamped vblank.
6037                  *
6038                  * This calculation can not be used with vrefresh rates
6039                  * below 5Hz (10Hz to be on the safe side) without
6040                  * promoting to 64 integers.
6041                  */
6042                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6043                     9 * crtc->framedur_ns) {
6044                         e->event.sequence++;
6045                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6046                                              crtc->framedur_ns);
6047                 }
6048
6049                 e->event.tv_sec = tvbl.tv_sec;
6050                 e->event.tv_usec = tvbl.tv_usec;
6051
6052                 list_add_tail(&e->base.link,
6053                               &e->base.file_priv->event_list);
6054                 wake_up_interruptible(&e->base.file_priv->event_wait);
6055         }
6056
6057         drm_vblank_put(dev, intel_crtc->pipe);
6058
6059         spin_unlock_irqrestore(&dev->event_lock, flags);
6060
6061         obj = work->old_fb_obj;
6062
6063         atomic_clear_mask(1 << intel_crtc->plane,
6064                           &obj->pending_flip.counter);
6065         if (atomic_read(&obj->pending_flip) == 0)
6066                 wake_up(&dev_priv->pending_flip_queue);
6067
6068         schedule_work(&work->work);
6069
6070         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6071 }
6072
6073 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6074 {
6075         drm_i915_private_t *dev_priv = dev->dev_private;
6076         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6077
6078         do_intel_finish_page_flip(dev, crtc);
6079 }
6080
6081 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6082 {
6083         drm_i915_private_t *dev_priv = dev->dev_private;
6084         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6085
6086         do_intel_finish_page_flip(dev, crtc);
6087 }
6088
6089 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6090 {
6091         drm_i915_private_t *dev_priv = dev->dev_private;
6092         struct intel_crtc *intel_crtc =
6093                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6094         unsigned long flags;
6095
6096         spin_lock_irqsave(&dev->event_lock, flags);
6097         if (intel_crtc->unpin_work) {
6098                 if ((++intel_crtc->unpin_work->pending) > 1)
6099                         DRM_ERROR("Prepared flip multiple times\n");
6100         } else {
6101                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6102         }
6103         spin_unlock_irqrestore(&dev->event_lock, flags);
6104 }
6105
6106 static int intel_gen2_queue_flip(struct drm_device *dev,
6107                                  struct drm_crtc *crtc,
6108                                  struct drm_framebuffer *fb,
6109                                  struct drm_i915_gem_object *obj)
6110 {
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6113         u32 flip_mask;
6114         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6115         int ret;
6116
6117         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6118         if (ret)
6119                 goto err;
6120
6121         ret = intel_ring_begin(ring, 6);
6122         if (ret)
6123                 goto err_unpin;
6124
6125         /* Can't queue multiple flips, so wait for the previous
6126          * one to finish before executing the next.
6127          */
6128         if (intel_crtc->plane)
6129                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6130         else
6131                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6132         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6133         intel_ring_emit(ring, MI_NOOP);
6134         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6135                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6136         intel_ring_emit(ring, fb->pitches[0]);
6137         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6138         intel_ring_emit(ring, 0); /* aux display base address, unused */
6139         intel_ring_advance(ring);
6140         return 0;
6141
6142 err_unpin:
6143         intel_unpin_fb_obj(obj);
6144 err:
6145         return ret;
6146 }
6147
6148 static int intel_gen3_queue_flip(struct drm_device *dev,
6149                                  struct drm_crtc *crtc,
6150                                  struct drm_framebuffer *fb,
6151                                  struct drm_i915_gem_object *obj)
6152 {
6153         struct drm_i915_private *dev_priv = dev->dev_private;
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         u32 flip_mask;
6156         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6157         int ret;
6158
6159         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6160         if (ret)
6161                 goto err;
6162
6163         ret = intel_ring_begin(ring, 6);
6164         if (ret)
6165                 goto err_unpin;
6166
6167         if (intel_crtc->plane)
6168                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6169         else
6170                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6171         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6172         intel_ring_emit(ring, MI_NOOP);
6173         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6174                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6175         intel_ring_emit(ring, fb->pitches[0]);
6176         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6177         intel_ring_emit(ring, MI_NOOP);
6178
6179         intel_ring_advance(ring);
6180         return 0;
6181
6182 err_unpin:
6183         intel_unpin_fb_obj(obj);
6184 err:
6185         return ret;
6186 }
6187
6188 static int intel_gen4_queue_flip(struct drm_device *dev,
6189                                  struct drm_crtc *crtc,
6190                                  struct drm_framebuffer *fb,
6191                                  struct drm_i915_gem_object *obj)
6192 {
6193         struct drm_i915_private *dev_priv = dev->dev_private;
6194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195         uint32_t pf, pipesrc;
6196         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6197         int ret;
6198
6199         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6200         if (ret)
6201                 goto err;
6202
6203         ret = intel_ring_begin(ring, 4);
6204         if (ret)
6205                 goto err_unpin;
6206
6207         /* i965+ uses the linear or tiled offsets from the
6208          * Display Registers (which do not change across a page-flip)
6209          * so we need only reprogram the base address.
6210          */
6211         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6212                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6213         intel_ring_emit(ring, fb->pitches[0]);
6214         intel_ring_emit(ring,
6215                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6216                         obj->tiling_mode);
6217
6218         /* XXX Enabling the panel-fitter across page-flip is so far
6219          * untested on non-native modes, so ignore it for now.
6220          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6221          */
6222         pf = 0;
6223         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6224         intel_ring_emit(ring, pf | pipesrc);
6225         intel_ring_advance(ring);
6226         return 0;
6227
6228 err_unpin:
6229         intel_unpin_fb_obj(obj);
6230 err:
6231         return ret;
6232 }
6233
6234 static int intel_gen6_queue_flip(struct drm_device *dev,
6235                                  struct drm_crtc *crtc,
6236                                  struct drm_framebuffer *fb,
6237                                  struct drm_i915_gem_object *obj)
6238 {
6239         struct drm_i915_private *dev_priv = dev->dev_private;
6240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6241         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6242         uint32_t pf, pipesrc;
6243         int ret;
6244
6245         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6246         if (ret)
6247                 goto err;
6248
6249         ret = intel_ring_begin(ring, 4);
6250         if (ret)
6251                 goto err_unpin;
6252
6253         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6254                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6255         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6256         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6257
6258         /* Contrary to the suggestions in the documentation,
6259          * "Enable Panel Fitter" does not seem to be required when page
6260          * flipping with a non-native mode, and worse causes a normal
6261          * modeset to fail.
6262          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6263          */
6264         pf = 0;
6265         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6266         intel_ring_emit(ring, pf | pipesrc);
6267         intel_ring_advance(ring);
6268         return 0;
6269
6270 err_unpin:
6271         intel_unpin_fb_obj(obj);
6272 err:
6273         return ret;
6274 }
6275
6276 /*
6277  * On gen7 we currently use the blit ring because (in early silicon at least)
6278  * the render ring doesn't give us interrpts for page flip completion, which
6279  * means clients will hang after the first flip is queued.  Fortunately the
6280  * blit ring generates interrupts properly, so use it instead.
6281  */
6282 static int intel_gen7_queue_flip(struct drm_device *dev,
6283                                  struct drm_crtc *crtc,
6284                                  struct drm_framebuffer *fb,
6285                                  struct drm_i915_gem_object *obj)
6286 {
6287         struct drm_i915_private *dev_priv = dev->dev_private;
6288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6290         uint32_t plane_bit = 0;
6291         int ret;
6292
6293         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6294         if (ret)
6295                 goto err;
6296
6297         switch(intel_crtc->plane) {
6298         case PLANE_A:
6299                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6300                 break;
6301         case PLANE_B:
6302                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6303                 break;
6304         case PLANE_C:
6305                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6306                 break;
6307         default:
6308                 WARN_ONCE(1, "unknown plane in flip command\n");
6309                 ret = -ENODEV;
6310                 goto err_unpin;
6311         }
6312
6313         ret = intel_ring_begin(ring, 4);
6314         if (ret)
6315                 goto err_unpin;
6316
6317         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6318         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6319         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6320         intel_ring_emit(ring, (MI_NOOP));
6321         intel_ring_advance(ring);
6322         return 0;
6323
6324 err_unpin:
6325         intel_unpin_fb_obj(obj);
6326 err:
6327         return ret;
6328 }
6329
6330 static int intel_default_queue_flip(struct drm_device *dev,
6331                                     struct drm_crtc *crtc,
6332                                     struct drm_framebuffer *fb,
6333                                     struct drm_i915_gem_object *obj)
6334 {
6335         return -ENODEV;
6336 }
6337
6338 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6339                                 struct drm_framebuffer *fb,
6340                                 struct drm_pending_vblank_event *event)
6341 {
6342         struct drm_device *dev = crtc->dev;
6343         struct drm_i915_private *dev_priv = dev->dev_private;
6344         struct intel_framebuffer *intel_fb;
6345         struct drm_i915_gem_object *obj;
6346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347         struct intel_unpin_work *work;
6348         unsigned long flags;
6349         int ret;
6350
6351         /* Can't change pixel format via MI display flips. */
6352         if (fb->pixel_format != crtc->fb->pixel_format)
6353                 return -EINVAL;
6354
6355         /*
6356          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6357          * Note that pitch changes could also affect these register.
6358          */
6359         if (INTEL_INFO(dev)->gen > 3 &&
6360             (fb->offsets[0] != crtc->fb->offsets[0] ||
6361              fb->pitches[0] != crtc->fb->pitches[0]))
6362                 return -EINVAL;
6363
6364         work = kzalloc(sizeof *work, GFP_KERNEL);
6365         if (work == NULL)
6366                 return -ENOMEM;
6367
6368         work->event = event;
6369         work->dev = crtc->dev;
6370         intel_fb = to_intel_framebuffer(crtc->fb);
6371         work->old_fb_obj = intel_fb->obj;
6372         INIT_WORK(&work->work, intel_unpin_work_fn);
6373
6374         ret = drm_vblank_get(dev, intel_crtc->pipe);
6375         if (ret)
6376                 goto free_work;
6377
6378         /* We borrow the event spin lock for protecting unpin_work */
6379         spin_lock_irqsave(&dev->event_lock, flags);
6380         if (intel_crtc->unpin_work) {
6381                 spin_unlock_irqrestore(&dev->event_lock, flags);
6382                 kfree(work);
6383                 drm_vblank_put(dev, intel_crtc->pipe);
6384
6385                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6386                 return -EBUSY;
6387         }
6388         intel_crtc->unpin_work = work;
6389         spin_unlock_irqrestore(&dev->event_lock, flags);
6390
6391         intel_fb = to_intel_framebuffer(fb);
6392         obj = intel_fb->obj;
6393
6394         ret = i915_mutex_lock_interruptible(dev);
6395         if (ret)
6396                 goto cleanup;
6397
6398         /* Reference the objects for the scheduled work. */
6399         drm_gem_object_reference(&work->old_fb_obj->base);
6400         drm_gem_object_reference(&obj->base);
6401
6402         crtc->fb = fb;
6403
6404         work->pending_flip_obj = obj;
6405
6406         work->enable_stall_check = true;
6407
6408         /* Block clients from rendering to the new back buffer until
6409          * the flip occurs and the object is no longer visible.
6410          */
6411         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6412
6413         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6414         if (ret)
6415                 goto cleanup_pending;
6416
6417         intel_disable_fbc(dev);
6418         intel_mark_fb_busy(obj);
6419         mutex_unlock(&dev->struct_mutex);
6420
6421         trace_i915_flip_request(intel_crtc->plane, obj);
6422
6423         return 0;
6424
6425 cleanup_pending:
6426         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6427         drm_gem_object_unreference(&work->old_fb_obj->base);
6428         drm_gem_object_unreference(&obj->base);
6429         mutex_unlock(&dev->struct_mutex);
6430
6431 cleanup:
6432         spin_lock_irqsave(&dev->event_lock, flags);
6433         intel_crtc->unpin_work = NULL;
6434         spin_unlock_irqrestore(&dev->event_lock, flags);
6435
6436         drm_vblank_put(dev, intel_crtc->pipe);
6437 free_work:
6438         kfree(work);
6439
6440         return ret;
6441 }
6442
6443 static void intel_sanitize_modesetting(struct drm_device *dev,
6444                                        int pipe, int plane)
6445 {
6446         struct drm_i915_private *dev_priv = dev->dev_private;
6447         u32 reg, val;
6448         int i;
6449
6450         /* Clear any frame start delays used for debugging left by the BIOS */
6451         for_each_pipe(i) {
6452                 reg = PIPECONF(i);
6453                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6454         }
6455
6456         if (HAS_PCH_SPLIT(dev))
6457                 return;
6458
6459         /* Who knows what state these registers were left in by the BIOS or
6460          * grub?
6461          *
6462          * If we leave the registers in a conflicting state (e.g. with the
6463          * display plane reading from the other pipe than the one we intend
6464          * to use) then when we attempt to teardown the active mode, we will
6465          * not disable the pipes and planes in the correct order -- leaving
6466          * a plane reading from a disabled pipe and possibly leading to
6467          * undefined behaviour.
6468          */
6469
6470         reg = DSPCNTR(plane);
6471         val = I915_READ(reg);
6472
6473         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6474                 return;
6475         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6476                 return;
6477
6478         /* This display plane is active and attached to the other CPU pipe. */
6479         pipe = !pipe;
6480
6481         /* Disable the plane and wait for it to stop reading from the pipe. */
6482         intel_disable_plane(dev_priv, plane, pipe);
6483         intel_disable_pipe(dev_priv, pipe);
6484 }
6485
6486 static void intel_crtc_reset(struct drm_crtc *crtc)
6487 {
6488         struct drm_device *dev = crtc->dev;
6489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6490
6491         /* Reset flags back to the 'unknown' status so that they
6492          * will be correctly set on the initial modeset.
6493          */
6494         intel_crtc->dpms_mode = -1;
6495
6496         /* We need to fix up any BIOS configuration that conflicts with
6497          * our expectations.
6498          */
6499         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6500 }
6501
6502 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6503         .dpms = intel_crtc_dpms,
6504         .mode_fixup = intel_crtc_mode_fixup,
6505         .mode_set = intel_crtc_mode_set,
6506         .mode_set_base = intel_pipe_set_base,
6507         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6508         .load_lut = intel_crtc_load_lut,
6509         .disable = intel_crtc_disable,
6510 };
6511
6512 static const struct drm_crtc_funcs intel_crtc_funcs = {
6513         .reset = intel_crtc_reset,
6514         .cursor_set = intel_crtc_cursor_set,
6515         .cursor_move = intel_crtc_cursor_move,
6516         .gamma_set = intel_crtc_gamma_set,
6517         .set_config = drm_crtc_helper_set_config,
6518         .destroy = intel_crtc_destroy,
6519         .page_flip = intel_crtc_page_flip,
6520 };
6521
6522 static void intel_pch_pll_init(struct drm_device *dev)
6523 {
6524         drm_i915_private_t *dev_priv = dev->dev_private;
6525         int i;
6526
6527         if (dev_priv->num_pch_pll == 0) {
6528                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6529                 return;
6530         }
6531
6532         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6533                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6534                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6535                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6536         }
6537 }
6538
6539 static void intel_crtc_init(struct drm_device *dev, int pipe)
6540 {
6541         drm_i915_private_t *dev_priv = dev->dev_private;
6542         struct intel_crtc *intel_crtc;
6543         int i;
6544
6545         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6546         if (intel_crtc == NULL)
6547                 return;
6548
6549         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6550
6551         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6552         for (i = 0; i < 256; i++) {
6553                 intel_crtc->lut_r[i] = i;
6554                 intel_crtc->lut_g[i] = i;
6555                 intel_crtc->lut_b[i] = i;
6556         }
6557
6558         /* Swap pipes & planes for FBC on pre-965 */
6559         intel_crtc->pipe = pipe;
6560         intel_crtc->plane = pipe;
6561         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6562                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6563                 intel_crtc->plane = !pipe;
6564         }
6565
6566         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6567                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6568         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6569         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6570
6571         intel_crtc_reset(&intel_crtc->base);
6572         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6573         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6574
6575         if (HAS_PCH_SPLIT(dev)) {
6576                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6577                 intel_helper_funcs.commit = ironlake_crtc_commit;
6578         } else {
6579                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6580                 intel_helper_funcs.commit = i9xx_crtc_commit;
6581         }
6582
6583         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6584 }
6585
6586 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6587                                 struct drm_file *file)
6588 {
6589         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6590         struct drm_mode_object *drmmode_obj;
6591         struct intel_crtc *crtc;
6592
6593         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6594                 return -ENODEV;
6595
6596         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6597                         DRM_MODE_OBJECT_CRTC);
6598
6599         if (!drmmode_obj) {
6600                 DRM_ERROR("no such CRTC id\n");
6601                 return -EINVAL;
6602         }
6603
6604         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6605         pipe_from_crtc_id->pipe = crtc->pipe;
6606
6607         return 0;
6608 }
6609
6610 static int intel_encoder_clones(struct intel_encoder *encoder)
6611 {
6612         struct drm_device *dev = encoder->base.dev;
6613         struct intel_encoder *source_encoder;
6614         int index_mask = 0;
6615         int entry = 0;
6616
6617         list_for_each_entry(source_encoder,
6618                             &dev->mode_config.encoder_list, base.head) {
6619
6620                 if (encoder == source_encoder)
6621                         index_mask |= (1 << entry);
6622
6623                 /* Intel hw has only one MUX where enocoders could be cloned. */
6624                 if (encoder->cloneable && source_encoder->cloneable)
6625                         index_mask |= (1 << entry);
6626
6627                 entry++;
6628         }
6629
6630         return index_mask;
6631 }
6632
6633 static bool has_edp_a(struct drm_device *dev)
6634 {
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636
6637         if (!IS_MOBILE(dev))
6638                 return false;
6639
6640         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6641                 return false;
6642
6643         if (IS_GEN5(dev) &&
6644             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6645                 return false;
6646
6647         return true;
6648 }
6649
6650 static void intel_setup_outputs(struct drm_device *dev)
6651 {
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_encoder *encoder;
6654         bool dpd_is_edp = false;
6655         bool has_lvds;
6656
6657         has_lvds = intel_lvds_init(dev);
6658         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6659                 /* disable the panel fitter on everything but LVDS */
6660                 I915_WRITE(PFIT_CONTROL, 0);
6661         }
6662
6663         if (HAS_PCH_SPLIT(dev)) {
6664                 dpd_is_edp = intel_dpd_is_edp(dev);
6665
6666                 if (has_edp_a(dev))
6667                         intel_dp_init(dev, DP_A, PORT_A);
6668
6669                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6670                         intel_dp_init(dev, PCH_DP_D, PORT_D);
6671         }
6672
6673         intel_crt_init(dev);
6674
6675         if (IS_HASWELL(dev)) {
6676                 int found;
6677
6678                 /* Haswell uses DDI functions to detect digital outputs */
6679                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6680                 /* DDI A only supports eDP */
6681                 if (found)
6682                         intel_ddi_init(dev, PORT_A);
6683
6684                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6685                  * register */
6686                 found = I915_READ(SFUSE_STRAP);
6687
6688                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6689                         intel_ddi_init(dev, PORT_B);
6690                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6691                         intel_ddi_init(dev, PORT_C);
6692                 if (found & SFUSE_STRAP_DDID_DETECTED)
6693                         intel_ddi_init(dev, PORT_D);
6694         } else if (HAS_PCH_SPLIT(dev)) {
6695                 int found;
6696
6697                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6698                         /* PCH SDVOB multiplex with HDMIB */
6699                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6700                         if (!found)
6701                                 intel_hdmi_init(dev, HDMIB, PORT_B);
6702                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6703                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
6704                 }
6705
6706                 if (I915_READ(HDMIC) & PORT_DETECTED)
6707                         intel_hdmi_init(dev, HDMIC, PORT_C);
6708
6709                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6710                         intel_hdmi_init(dev, HDMID, PORT_D);
6711
6712                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6713                         intel_dp_init(dev, PCH_DP_C, PORT_C);
6714
6715                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6716                         intel_dp_init(dev, PCH_DP_D, PORT_D);
6717         } else if (IS_VALLEYVIEW(dev)) {
6718                 int found;
6719
6720                 if (I915_READ(SDVOB) & PORT_DETECTED) {
6721                         /* SDVOB multiplex with HDMIB */
6722                         found = intel_sdvo_init(dev, SDVOB, true);
6723                         if (!found)
6724                                 intel_hdmi_init(dev, SDVOB, PORT_B);
6725                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
6726                                 intel_dp_init(dev, DP_B, PORT_B);
6727                 }
6728
6729                 if (I915_READ(SDVOC) & PORT_DETECTED)
6730                         intel_hdmi_init(dev, SDVOC, PORT_C);
6731
6732                 /* Shares lanes with HDMI on SDVOC */
6733                 if (I915_READ(DP_C) & DP_DETECTED)
6734                         intel_dp_init(dev, DP_C, PORT_C);
6735         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6736                 bool found = false;
6737
6738                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6739                         DRM_DEBUG_KMS("probing SDVOB\n");
6740                         found = intel_sdvo_init(dev, SDVOB, true);
6741                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6742                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6743                                 intel_hdmi_init(dev, SDVOB, PORT_B);
6744                         }
6745
6746                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6747                                 DRM_DEBUG_KMS("probing DP_B\n");
6748                                 intel_dp_init(dev, DP_B, PORT_B);
6749                         }
6750                 }
6751
6752                 /* Before G4X SDVOC doesn't have its own detect register */
6753
6754                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6755                         DRM_DEBUG_KMS("probing SDVOC\n");
6756                         found = intel_sdvo_init(dev, SDVOC, false);
6757                 }
6758
6759                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6760
6761                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6762                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6763                                 intel_hdmi_init(dev, SDVOC, PORT_C);
6764                         }
6765                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6766                                 DRM_DEBUG_KMS("probing DP_C\n");
6767                                 intel_dp_init(dev, DP_C, PORT_C);
6768                         }
6769                 }
6770
6771                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6772                     (I915_READ(DP_D) & DP_DETECTED)) {
6773                         DRM_DEBUG_KMS("probing DP_D\n");
6774                         intel_dp_init(dev, DP_D, PORT_D);
6775                 }
6776         } else if (IS_GEN2(dev))
6777                 intel_dvo_init(dev);
6778
6779         if (SUPPORTS_TV(dev))
6780                 intel_tv_init(dev);
6781
6782         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6783                 encoder->base.possible_crtcs = encoder->crtc_mask;
6784                 encoder->base.possible_clones =
6785                         intel_encoder_clones(encoder);
6786         }
6787
6788         /* disable all the possible outputs/crtcs before entering KMS mode */
6789         drm_helper_disable_unused_functions(dev);
6790
6791         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6792                 ironlake_init_pch_refclk(dev);
6793 }
6794
6795 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6796 {
6797         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6798
6799         drm_framebuffer_cleanup(fb);
6800         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6801
6802         kfree(intel_fb);
6803 }
6804
6805 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6806                                                 struct drm_file *file,
6807                                                 unsigned int *handle)
6808 {
6809         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6810         struct drm_i915_gem_object *obj = intel_fb->obj;
6811
6812         return drm_gem_handle_create(file, &obj->base, handle);
6813 }
6814
6815 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6816         .destroy = intel_user_framebuffer_destroy,
6817         .create_handle = intel_user_framebuffer_create_handle,
6818 };
6819
6820 int intel_framebuffer_init(struct drm_device *dev,
6821                            struct intel_framebuffer *intel_fb,
6822                            struct drm_mode_fb_cmd2 *mode_cmd,
6823                            struct drm_i915_gem_object *obj)
6824 {
6825         int ret;
6826
6827         if (obj->tiling_mode == I915_TILING_Y)
6828                 return -EINVAL;
6829
6830         if (mode_cmd->pitches[0] & 63)
6831                 return -EINVAL;
6832
6833         switch (mode_cmd->pixel_format) {
6834         case DRM_FORMAT_RGB332:
6835         case DRM_FORMAT_RGB565:
6836         case DRM_FORMAT_XRGB8888:
6837         case DRM_FORMAT_XBGR8888:
6838         case DRM_FORMAT_ARGB8888:
6839         case DRM_FORMAT_XRGB2101010:
6840         case DRM_FORMAT_ARGB2101010:
6841                 /* RGB formats are common across chipsets */
6842                 break;
6843         case DRM_FORMAT_YUYV:
6844         case DRM_FORMAT_UYVY:
6845         case DRM_FORMAT_YVYU:
6846         case DRM_FORMAT_VYUY:
6847                 break;
6848         default:
6849                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6850                                 mode_cmd->pixel_format);
6851                 return -EINVAL;
6852         }
6853
6854         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6855         if (ret) {
6856                 DRM_ERROR("framebuffer init failed %d\n", ret);
6857                 return ret;
6858         }
6859
6860         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6861         intel_fb->obj = obj;
6862         return 0;
6863 }
6864
6865 static struct drm_framebuffer *
6866 intel_user_framebuffer_create(struct drm_device *dev,
6867                               struct drm_file *filp,
6868                               struct drm_mode_fb_cmd2 *mode_cmd)
6869 {
6870         struct drm_i915_gem_object *obj;
6871
6872         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6873                                                 mode_cmd->handles[0]));
6874         if (&obj->base == NULL)
6875                 return ERR_PTR(-ENOENT);
6876
6877         return intel_framebuffer_create(dev, mode_cmd, obj);
6878 }
6879
6880 static const struct drm_mode_config_funcs intel_mode_funcs = {
6881         .fb_create = intel_user_framebuffer_create,
6882         .output_poll_changed = intel_fb_output_poll_changed,
6883 };
6884
6885 /* Set up chip specific display functions */
6886 static void intel_init_display(struct drm_device *dev)
6887 {
6888         struct drm_i915_private *dev_priv = dev->dev_private;
6889
6890         /* We always want a DPMS function */
6891         if (HAS_PCH_SPLIT(dev)) {
6892                 dev_priv->display.dpms = ironlake_crtc_dpms;
6893                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6894                 dev_priv->display.off = ironlake_crtc_off;
6895                 dev_priv->display.update_plane = ironlake_update_plane;
6896         } else {
6897                 dev_priv->display.dpms = i9xx_crtc_dpms;
6898                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6899                 dev_priv->display.off = i9xx_crtc_off;
6900                 dev_priv->display.update_plane = i9xx_update_plane;
6901         }
6902
6903         /* Returns the core display clock speed */
6904         if (IS_VALLEYVIEW(dev))
6905                 dev_priv->display.get_display_clock_speed =
6906                         valleyview_get_display_clock_speed;
6907         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6908                 dev_priv->display.get_display_clock_speed =
6909                         i945_get_display_clock_speed;
6910         else if (IS_I915G(dev))
6911                 dev_priv->display.get_display_clock_speed =
6912                         i915_get_display_clock_speed;
6913         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6914                 dev_priv->display.get_display_clock_speed =
6915                         i9xx_misc_get_display_clock_speed;
6916         else if (IS_I915GM(dev))
6917                 dev_priv->display.get_display_clock_speed =
6918                         i915gm_get_display_clock_speed;
6919         else if (IS_I865G(dev))
6920                 dev_priv->display.get_display_clock_speed =
6921                         i865_get_display_clock_speed;
6922         else if (IS_I85X(dev))
6923                 dev_priv->display.get_display_clock_speed =
6924                         i855_get_display_clock_speed;
6925         else /* 852, 830 */
6926                 dev_priv->display.get_display_clock_speed =
6927                         i830_get_display_clock_speed;
6928
6929         if (HAS_PCH_SPLIT(dev)) {
6930                 if (IS_GEN5(dev)) {
6931                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6932                         dev_priv->display.write_eld = ironlake_write_eld;
6933                 } else if (IS_GEN6(dev)) {
6934                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6935                         dev_priv->display.write_eld = ironlake_write_eld;
6936                 } else if (IS_IVYBRIDGE(dev)) {
6937                         /* FIXME: detect B0+ stepping and use auto training */
6938                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6939                         dev_priv->display.write_eld = ironlake_write_eld;
6940                 } else if (IS_HASWELL(dev)) {
6941                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
6942                         dev_priv->display.write_eld = ironlake_write_eld;
6943                 } else
6944                         dev_priv->display.update_wm = NULL;
6945         } else if (IS_G4X(dev)) {
6946                 dev_priv->display.write_eld = g4x_write_eld;
6947         }
6948
6949         /* Default just returns -ENODEV to indicate unsupported */
6950         dev_priv->display.queue_flip = intel_default_queue_flip;
6951
6952         switch (INTEL_INFO(dev)->gen) {
6953         case 2:
6954                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6955                 break;
6956
6957         case 3:
6958                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6959                 break;
6960
6961         case 4:
6962         case 5:
6963                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6964                 break;
6965
6966         case 6:
6967                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6968                 break;
6969         case 7:
6970                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6971                 break;
6972         }
6973 }
6974
6975 /*
6976  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6977  * resume, or other times.  This quirk makes sure that's the case for
6978  * affected systems.
6979  */
6980 static void quirk_pipea_force(struct drm_device *dev)
6981 {
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983
6984         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6985         DRM_INFO("applying pipe a force quirk\n");
6986 }
6987
6988 /*
6989  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6990  */
6991 static void quirk_ssc_force_disable(struct drm_device *dev)
6992 {
6993         struct drm_i915_private *dev_priv = dev->dev_private;
6994         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6995         DRM_INFO("applying lvds SSC disable quirk\n");
6996 }
6997
6998 /*
6999  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7000  * brightness value
7001  */
7002 static void quirk_invert_brightness(struct drm_device *dev)
7003 {
7004         struct drm_i915_private *dev_priv = dev->dev_private;
7005         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7006         DRM_INFO("applying inverted panel brightness quirk\n");
7007 }
7008
7009 struct intel_quirk {
7010         int device;
7011         int subsystem_vendor;
7012         int subsystem_device;
7013         void (*hook)(struct drm_device *dev);
7014 };
7015
7016 static struct intel_quirk intel_quirks[] = {
7017         /* HP Mini needs pipe A force quirk (LP: #322104) */
7018         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7019
7020         /* Thinkpad R31 needs pipe A force quirk */
7021         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7022         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7023         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7024
7025         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7026         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7027         /* ThinkPad X40 needs pipe A force quirk */
7028
7029         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7030         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7031
7032         /* 855 & before need to leave pipe A & dpll A up */
7033         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7034         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7035
7036         /* Lenovo U160 cannot use SSC on LVDS */
7037         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7038
7039         /* Sony Vaio Y cannot use SSC on LVDS */
7040         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7041
7042         /* Acer Aspire 5734Z must invert backlight brightness */
7043         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7044 };
7045
7046 static void intel_init_quirks(struct drm_device *dev)
7047 {
7048         struct pci_dev *d = dev->pdev;
7049         int i;
7050
7051         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7052                 struct intel_quirk *q = &intel_quirks[i];
7053
7054                 if (d->device == q->device &&
7055                     (d->subsystem_vendor == q->subsystem_vendor ||
7056                      q->subsystem_vendor == PCI_ANY_ID) &&
7057                     (d->subsystem_device == q->subsystem_device ||
7058                      q->subsystem_device == PCI_ANY_ID))
7059                         q->hook(dev);
7060         }
7061 }
7062
7063 /* Disable the VGA plane that we never use */
7064 static void i915_disable_vga(struct drm_device *dev)
7065 {
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         u8 sr1;
7068         u32 vga_reg;
7069
7070         if (HAS_PCH_SPLIT(dev))
7071                 vga_reg = CPU_VGACNTRL;
7072         else
7073                 vga_reg = VGACNTRL;
7074
7075         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7076         outb(SR01, VGA_SR_INDEX);
7077         sr1 = inb(VGA_SR_DATA);
7078         outb(sr1 | 1<<5, VGA_SR_DATA);
7079         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7080         udelay(300);
7081
7082         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7083         POSTING_READ(vga_reg);
7084 }
7085
7086 void intel_modeset_init_hw(struct drm_device *dev)
7087 {
7088         /* We attempt to init the necessary power wells early in the initialization
7089          * time, so the subsystems that expect power to be enabled can work.
7090          */
7091         intel_init_power_wells(dev);
7092
7093         intel_prepare_ddi(dev);
7094
7095         intel_init_clock_gating(dev);
7096
7097         mutex_lock(&dev->struct_mutex);
7098         intel_enable_gt_powersave(dev);
7099         mutex_unlock(&dev->struct_mutex);
7100 }
7101
7102 void intel_modeset_init(struct drm_device *dev)
7103 {
7104         struct drm_i915_private *dev_priv = dev->dev_private;
7105         int i, ret;
7106
7107         drm_mode_config_init(dev);
7108
7109         dev->mode_config.min_width = 0;
7110         dev->mode_config.min_height = 0;
7111
7112         dev->mode_config.preferred_depth = 24;
7113         dev->mode_config.prefer_shadow = 1;
7114
7115         dev->mode_config.funcs = &intel_mode_funcs;
7116
7117         intel_init_quirks(dev);
7118
7119         intel_init_pm(dev);
7120
7121         intel_init_display(dev);
7122
7123         if (IS_GEN2(dev)) {
7124                 dev->mode_config.max_width = 2048;
7125                 dev->mode_config.max_height = 2048;
7126         } else if (IS_GEN3(dev)) {
7127                 dev->mode_config.max_width = 4096;
7128                 dev->mode_config.max_height = 4096;
7129         } else {
7130                 dev->mode_config.max_width = 8192;
7131                 dev->mode_config.max_height = 8192;
7132         }
7133         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7134
7135         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7136                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7137
7138         for (i = 0; i < dev_priv->num_pipe; i++) {
7139                 intel_crtc_init(dev, i);
7140                 ret = intel_plane_init(dev, i);
7141                 if (ret)
7142                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7143         }
7144
7145         intel_pch_pll_init(dev);
7146
7147         /* Just disable it once at startup */
7148         i915_disable_vga(dev);
7149         intel_setup_outputs(dev);
7150 }
7151
7152 void intel_modeset_gem_init(struct drm_device *dev)
7153 {
7154         intel_modeset_init_hw(dev);
7155
7156         intel_setup_overlay(dev);
7157 }
7158
7159 void intel_modeset_cleanup(struct drm_device *dev)
7160 {
7161         struct drm_i915_private *dev_priv = dev->dev_private;
7162         struct drm_crtc *crtc;
7163         struct intel_crtc *intel_crtc;
7164
7165         drm_kms_helper_poll_fini(dev);
7166         mutex_lock(&dev->struct_mutex);
7167
7168         intel_unregister_dsm_handler();
7169
7170
7171         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7172                 /* Skip inactive CRTCs */
7173                 if (!crtc->fb)
7174                         continue;
7175
7176                 intel_crtc = to_intel_crtc(crtc);
7177                 intel_increase_pllclock(crtc);
7178         }
7179
7180         intel_disable_fbc(dev);
7181
7182         intel_disable_gt_powersave(dev);
7183
7184         ironlake_teardown_rc6(dev);
7185
7186         if (IS_VALLEYVIEW(dev))
7187                 vlv_init_dpio(dev);
7188
7189         mutex_unlock(&dev->struct_mutex);
7190
7191         /* Disable the irq before mode object teardown, for the irq might
7192          * enqueue unpin/hotplug work. */
7193         drm_irq_uninstall(dev);
7194         cancel_work_sync(&dev_priv->hotplug_work);
7195         cancel_work_sync(&dev_priv->rps.work);
7196
7197         /* flush any delayed tasks or pending work */
7198         flush_scheduled_work();
7199
7200         drm_mode_config_cleanup(dev);
7201 }
7202
7203 /*
7204  * Return which encoder is currently attached for connector.
7205  */
7206 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7207 {
7208         return &intel_attached_encoder(connector)->base;
7209 }
7210
7211 void intel_connector_attach_encoder(struct intel_connector *connector,
7212                                     struct intel_encoder *encoder)
7213 {
7214         connector->encoder = encoder;
7215         drm_mode_connector_attach_encoder(&connector->base,
7216                                           &encoder->base);
7217 }
7218
7219 /*
7220  * set vga decode state - true == enable VGA decode
7221  */
7222 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7223 {
7224         struct drm_i915_private *dev_priv = dev->dev_private;
7225         u16 gmch_ctrl;
7226
7227         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7228         if (state)
7229                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7230         else
7231                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7232         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7233         return 0;
7234 }
7235
7236 #ifdef CONFIG_DEBUG_FS
7237 #include <linux/seq_file.h>
7238
7239 struct intel_display_error_state {
7240         struct intel_cursor_error_state {
7241                 u32 control;
7242                 u32 position;
7243                 u32 base;
7244                 u32 size;
7245         } cursor[2];
7246
7247         struct intel_pipe_error_state {
7248                 u32 conf;
7249                 u32 source;
7250
7251                 u32 htotal;
7252                 u32 hblank;
7253                 u32 hsync;
7254                 u32 vtotal;
7255                 u32 vblank;
7256                 u32 vsync;
7257         } pipe[2];
7258
7259         struct intel_plane_error_state {
7260                 u32 control;
7261                 u32 stride;
7262                 u32 size;
7263                 u32 pos;
7264                 u32 addr;
7265                 u32 surface;
7266                 u32 tile_offset;
7267         } plane[2];
7268 };
7269
7270 struct intel_display_error_state *
7271 intel_display_capture_error_state(struct drm_device *dev)
7272 {
7273         drm_i915_private_t *dev_priv = dev->dev_private;
7274         struct intel_display_error_state *error;
7275         int i;
7276
7277         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7278         if (error == NULL)
7279                 return NULL;
7280
7281         for (i = 0; i < 2; i++) {
7282                 error->cursor[i].control = I915_READ(CURCNTR(i));
7283                 error->cursor[i].position = I915_READ(CURPOS(i));
7284                 error->cursor[i].base = I915_READ(CURBASE(i));
7285
7286                 error->plane[i].control = I915_READ(DSPCNTR(i));
7287                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7288                 error->plane[i].size = I915_READ(DSPSIZE(i));
7289                 error->plane[i].pos = I915_READ(DSPPOS(i));
7290                 error->plane[i].addr = I915_READ(DSPADDR(i));
7291                 if (INTEL_INFO(dev)->gen >= 4) {
7292                         error->plane[i].surface = I915_READ(DSPSURF(i));
7293                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7294                 }
7295
7296                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7297                 error->pipe[i].source = I915_READ(PIPESRC(i));
7298                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7299                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7300                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7301                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7302                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7303                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7304         }
7305
7306         return error;
7307 }
7308
7309 void
7310 intel_display_print_error_state(struct seq_file *m,
7311                                 struct drm_device *dev,
7312                                 struct intel_display_error_state *error)
7313 {
7314         int i;
7315
7316         for (i = 0; i < 2; i++) {
7317                 seq_printf(m, "Pipe [%d]:\n", i);
7318                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7319                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7320                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7321                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7322                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7323                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7324                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7325                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7326
7327                 seq_printf(m, "Plane [%d]:\n", i);
7328                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7329                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7330                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7331                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7332                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7333                 if (INTEL_INFO(dev)->gen >= 4) {
7334                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7335                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7336                 }
7337
7338                 seq_printf(m, "Cursor [%d]:\n", i);
7339                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7340                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7341                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7342         }
7343 }
7344 #endif