drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else
 223                 return dev_priv->fdi_pll_freq;
 224 }
 225
 226 static const struct intel_limit intel_limits_i8xx_dac = {
 227         .dot = { .min = 25000, .max = 350000 },
 228         .vco = { .min = 908000, .max = 1512000 },
 229         .n = { .min = 2, .max = 16 },
 230         .m = { .min = 96, .max = 140 },
 231         .m1 = { .min = 18, .max = 26 },
 232         .m2 = { .min = 6, .max = 16 },
 233         .p = { .min = 4, .max = 128 },
 234         .p1 = { .min = 2, .max = 33 },
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 4, .p2_fast = 2 },
 237 };
 238
 239 static const struct intel_limit intel_limits_i8xx_dvo = {
 240         .dot = { .min = 25000, .max = 350000 },
 241         .vco = { .min = 908000, .max = 1512000 },
 242         .n = { .min = 2, .max = 16 },
 243         .m = { .min = 96, .max = 140 },
 244         .m1 = { .min = 18, .max = 26 },
 245         .m2 = { .min = 6, .max = 16 },
 246         .p = { .min = 4, .max = 128 },
 247         .p1 = { .min = 2, .max = 33 },
 248         .p2 = { .dot_limit = 165000,
 249                 .p2_slow = 4, .p2_fast = 4 },
 250 };
 251
 252 static const struct intel_limit intel_limits_i8xx_lvds = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 1, .max = 6 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 14, .p2_fast = 7 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i9xx_sdvo = {
 266         .dot = { .min = 20000, .max = 400000 },
 267         .vco = { .min = 1400000, .max = 2800000 },
 268         .n = { .min = 1, .max = 6 },
 269         .m = { .min = 70, .max = 120 },
 270         .m1 = { .min = 8, .max = 18 },
 271         .m2 = { .min = 3, .max = 7 },
 272         .p = { .min = 5, .max = 80 },
 273         .p1 = { .min = 1, .max = 8 },
 274         .p2 = { .dot_limit = 200000,
 275                 .p2_slow = 10, .p2_fast = 5 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i9xx_lvds = {
 279         .dot = { .min = 20000, .max = 400000 },
 280         .vco = { .min = 1400000, .max = 2800000 },
 281         .n = { .min = 1, .max = 6 },
 282         .m = { .min = 70, .max = 120 },
 283         .m1 = { .min = 8, .max = 18 },
 284         .m2 = { .min = 3, .max = 7 },
 285         .p = { .min = 7, .max = 98 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 112000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291
 292 static const struct intel_limit intel_limits_g4x_sdvo = {
 293         .dot = { .min = 25000, .max = 270000 },
 294         .vco = { .min = 1750000, .max = 3500000},
 295         .n = { .min = 1, .max = 4 },
 296         .m = { .min = 104, .max = 138 },
 297         .m1 = { .min = 17, .max = 23 },
 298         .m2 = { .min = 5, .max = 11 },
 299         .p = { .min = 10, .max = 30 },
 300         .p1 = { .min = 1, .max = 3},
 301         .p2 = { .dot_limit = 270000,
 302                 .p2_slow = 10,
 303                 .p2_fast = 10
 304         },
 305 };
 306
 307 static const struct intel_limit intel_limits_g4x_hdmi = {
 308         .dot = { .min = 22000, .max = 400000 },
 309         .vco = { .min = 1750000, .max = 3500000},
 310         .n = { .min = 1, .max = 4 },
 311         .m = { .min = 104, .max = 138 },
 312         .m1 = { .min = 16, .max = 23 },
 313         .m2 = { .min = 5, .max = 11 },
 314         .p = { .min = 5, .max = 80 },
 315         .p1 = { .min = 1, .max = 8},
 316         .p2 = { .dot_limit = 165000,
 317                 .p2_slow = 10, .p2_fast = 5 },
 318 };
 319
 320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 321         .dot = { .min = 20000, .max = 115000 },
 322         .vco = { .min = 1750000, .max = 3500000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 0,
 330                 .p2_slow = 14, .p2_fast = 14
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 335         .dot = { .min = 80000, .max = 224000 },
 336         .vco = { .min = 1750000, .max = 3500000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 17, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 0,
 344                 .p2_slow = 7, .p2_fast = 7
 345         },
 346 };
 347
 348 static const struct intel_limit intel_limits_pineview_sdvo = {
 349         .dot = { .min = 20000, .max = 400000},
 350         .vco = { .min = 1700000, .max = 3500000 },
 351         /* Pineview's Ncounter is a ring counter */
 352         .n = { .min = 3, .max = 6 },
 353         .m = { .min = 2, .max = 256 },
 354         /* Pineview only has one combined m divider, which we treat as m2. */
 355         .m1 = { .min = 0, .max = 0 },
 356         .m2 = { .min = 0, .max = 254 },
 357         .p = { .min = 5, .max = 80 },
 358         .p1 = { .min = 1, .max = 8 },
 359         .p2 = { .dot_limit = 200000,
 360                 .p2_slow = 10, .p2_fast = 5 },
 361 };
 362
 363 static const struct intel_limit intel_limits_pineview_lvds = {
 364         .dot = { .min = 20000, .max = 400000 },
 365         .vco = { .min = 1700000, .max = 3500000 },
 366         .n = { .min = 3, .max = 6 },
 367         .m = { .min = 2, .max = 256 },
 368         .m1 = { .min = 0, .max = 0 },
 369         .m2 = { .min = 0, .max = 254 },
 370         .p = { .min = 7, .max = 112 },
 371         .p1 = { .min = 1, .max = 8 },
 372         .p2 = { .dot_limit = 112000,
 373                 .p2_slow = 14, .p2_fast = 14 },
 374 };
 375
 376 /* Ironlake / Sandybridge
 377  *
 378  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 379  * the range value for them is (actual_value - 2).
 380  */
 381 static const struct intel_limit intel_limits_ironlake_dac = {
 382         .dot = { .min = 25000, .max = 350000 },
 383         .vco = { .min = 1760000, .max = 3510000 },
 384         .n = { .min = 1, .max = 5 },
 385         .m = { .min = 79, .max = 127 },
 386         .m1 = { .min = 12, .max = 22 },
 387         .m2 = { .min = 5, .max = 9 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 225000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 395         .dot = { .min = 25000, .max = 350000 },
 396         .vco = { .min = 1760000, .max = 3510000 },
 397         .n = { .min = 1, .max = 3 },
 398         .m = { .min = 79, .max = 118 },
 399         .m1 = { .min = 12, .max = 22 },
 400         .m2 = { .min = 5, .max = 9 },
 401         .p = { .min = 28, .max = 112 },
 402         .p1 = { .min = 2, .max = 8 },
 403         .p2 = { .dot_limit = 225000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 3 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 14, .max = 56 },
 415         .p1 = { .min = 2, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 7, .p2_fast = 7 },
 418 };
 419
 420 /* LVDS 100mhz refclk limits. */
 421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 2 },
 425         .m = { .min = 79, .max = 126 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 126 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 42 },
 442         .p1 = { .min = 2, .max = 6 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 static const struct intel_limit intel_limits_vlv = {
 448          /*
 449           * These are the data rate limits (measured in fast clocks)
 450           * since those are the strictest limits we have. The fast
 451           * clock and actual rate limits are more relaxed, so checking
 452           * them would make no difference.
 453           */
 454         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 455         .vco = { .min = 4000000, .max = 6000000 },
 456         .n = { .min = 1, .max = 7 },
 457         .m1 = { .min = 2, .max = 3 },
 458         .m2 = { .min = 11, .max = 156 },
 459         .p1 = { .min = 2, .max = 3 },
 460         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 461 };
 462
 463 static const struct intel_limit intel_limits_chv = {
 464         /*
 465          * These are the data rate limits (measured in fast clocks)
 466          * since those are the strictest limits we have.  The fast
 467          * clock and actual rate limits are more relaxed, so checking
 468          * them would make no difference.
 469          */
 470         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 471         .vco = { .min = 4800000, .max = 6480000 },
 472         .n = { .min = 1, .max = 1 },
 473         .m1 = { .min = 2, .max = 2 },
 474         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 475         .p1 = { .min = 2, .max = 4 },
 476         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 477 };
 478
 479 static const struct intel_limit intel_limits_bxt = {
 480         /* FIXME: find real dot limits */
 481         .dot = { .min = 0, .max = INT_MAX },
 482         .vco = { .min = 4800000, .max = 6700000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         /* FIXME: find real m2 limits */
 486         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 487         .p1 = { .min = 2, .max = 4 },
 488         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 489 };
 490
 491 static bool
 492 needs_modeset(struct drm_crtc_state *state)
 493 {
 494         return drm_atomic_crtc_needs_modeset(state);
 495 }
 496
 497 /*
 498  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 499  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 500  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 501  * The helpers' return value is the rate of the clock that is fed to the
 502  * display engine's pipe which can be the above fast dot clock rate or a
 503  * divided-down version of it.
 504  */
 505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 506 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 507 {
 508         clock->m = clock->m2 + 2;
 509         clock->p = clock->p1 * clock->p2;
 510         if (WARN_ON(clock->n == 0 || clock->p == 0))
 511                 return 0;
 512         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 513         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 514
 515         return clock->dot;
 516 }
 517
 518 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 519 {
 520         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 521 }
 522
 523 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 524 {
 525         clock->m = i9xx_dpll_compute_m(clock);
 526         clock->p = clock->p1 * clock->p2;
 527         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 528                 return 0;
 529         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 530         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 531
 532         return clock->dot;
 533 }
 534
 535 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 536 {
 537         clock->m = clock->m1 * clock->m2;
 538         clock->p = clock->p1 * clock->p2;
 539         if (WARN_ON(clock->n == 0 || clock->p == 0))
 540                 return 0;
 541         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 542         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 543
 544         return clock->dot / 5;
 545 }
 546
 547 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 548 {
 549         clock->m = clock->m1 * clock->m2;
 550         clock->p = clock->p1 * clock->p2;
 551         if (WARN_ON(clock->n == 0 || clock->p == 0))
 552                 return 0;
 553         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 554                         clock->n << 22);
 555         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 556
 557         return clock->dot / 5;
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 567                                const struct intel_limit *limit,
 568                                const struct dpll *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 580             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 581                 if (clock->m1 <= clock->m2)
 582                         INTELPllInvalid("m1 <= m2\n");
 583
 584         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 585             !IS_GEN9_LP(dev_priv)) {
 586                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 587                         INTELPllInvalid("p out of range\n");
 588                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 589                         INTELPllInvalid("m out of range\n");
 590         }
 591
 592         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 593                 INTELPllInvalid("vco out of range\n");
 594         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 595          * connector, etc., rather than just a single range.
 596          */
 597         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 598                 INTELPllInvalid("dot out of range\n");
 599
 600         return true;
 601 }
 602
 603 static int
 604 i9xx_select_p2_div(const struct intel_limit *limit,
 605                    const struct intel_crtc_state *crtc_state,
 606                    int target)
 607 {
 608         struct drm_device *dev = crtc_state->base.crtc->dev;
 609
 610         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         return limit->p2.p2_fast;
 618                 else
 619                         return limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         return limit->p2.p2_slow;
 623                 else
 624                         return limit->p2.p2_fast;
 625         }
 626 }
 627
 628 /*
 629  * Returns a set of divisors for the desired target clock with the given
 630  * refclk, or FALSE.  The returned values represent the clock equation:
 631  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 632  *
 633  * Target and reference clocks are specified in kHz.
 634  *
 635  * If match_clock is provided, then best_clock P divider must match the P
 636  * divider from @match_clock used for LVDS downclocking.
 637  */
 638 static bool
 639 i9xx_find_best_dpll(const struct intel_limit *limit,
 640                     struct intel_crtc_state *crtc_state,
 641                     int target, int refclk, struct dpll *match_clock,
 642                     struct dpll *best_clock)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645         struct dpll clock;
 646         int err = target;
 647
 648         memset(best_clock, 0, sizeof(*best_clock));
 649
 650         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 651
 652         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 653              clock.m1++) {
 654                 for (clock.m2 = limit->m2.min;
 655                      clock.m2 <= limit->m2.max; clock.m2++) {
 656                         if (clock.m2 >= clock.m1)
 657                                 break;
 658                         for (clock.n = limit->n.min;
 659                              clock.n <= limit->n.max; clock.n++) {
 660                                 for (clock.p1 = limit->p1.min;
 661                                         clock.p1 <= limit->p1.max; clock.p1++) {
 662                                         int this_err;
 663
 664                                         i9xx_calc_dpll_params(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(to_i915(dev),
 666                                                                 limit,
 667                                                                 &clock))
 668                                                 continue;
 669                                         if (match_clock &&
 670                                             clock.p != match_clock->p)
 671                                                 continue;
 672
 673                                         this_err = abs(clock.dot - target);
 674                                         if (this_err < err) {
 675                                                 *best_clock = clock;
 676                                                 err = this_err;
 677                                         }
 678                                 }
 679                         }
 680                 }
 681         }
 682
 683         return (err != target);
 684 }
 685
 686 /*
 687  * Returns a set of divisors for the desired target clock with the given
 688  * refclk, or FALSE.  The returned values represent the clock equation:
 689  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 690  *
 691  * Target and reference clocks are specified in kHz.
 692  *
 693  * If match_clock is provided, then best_clock P divider must match the P
 694  * divider from @match_clock used for LVDS downclocking.
 695  */
 696 static bool
 697 pnv_find_best_dpll(const struct intel_limit *limit,
 698                    struct intel_crtc_state *crtc_state,
 699                    int target, int refclk, struct dpll *match_clock,
 700                    struct dpll *best_clock)
 701 {
 702         struct drm_device *dev = crtc_state->base.crtc->dev;
 703         struct dpll clock;
 704         int err = target;
 705
 706         memset(best_clock, 0, sizeof(*best_clock));
 707
 708         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 709
 710         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711              clock.m1++) {
 712                 for (clock.m2 = limit->m2.min;
 713                      clock.m2 <= limit->m2.max; clock.m2++) {
 714                         for (clock.n = limit->n.min;
 715                              clock.n <= limit->n.max; clock.n++) {
 716                                 for (clock.p1 = limit->p1.min;
 717                                         clock.p1 <= limit->p1.max; clock.p1++) {
 718                                         int this_err;
 719
 720                                         pnv_calc_dpll_params(refclk, &clock);
 721                                         if (!intel_PLL_is_valid(to_i915(dev),
 722                                                                 limit,
 723                                                                 &clock))
 724                                                 continue;
 725                                         if (match_clock &&
 726                                             clock.p != match_clock->p)
 727                                                 continue;
 728
 729                                         this_err = abs(clock.dot - target);
 730                                         if (this_err < err) {
 731                                                 *best_clock = clock;
 732                                                 err = this_err;
 733                                         }
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         return (err != target);
 740 }
 741
 742 /*
 743  * Returns a set of divisors for the desired target clock with the given
 744  * refclk, or FALSE.  The returned values represent the clock equation:
 745  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 746  *
 747  * Target and reference clocks are specified in kHz.
 748  *
 749  * If match_clock is provided, then best_clock P divider must match the P
 750  * divider from @match_clock used for LVDS downclocking.
 751  */
 752 static bool
 753 g4x_find_best_dpll(const struct intel_limit *limit,
 754                    struct intel_crtc_state *crtc_state,
 755                    int target, int refclk, struct dpll *match_clock,
 756                    struct dpll *best_clock)
 757 {
 758         struct drm_device *dev = crtc_state->base.crtc->dev;
 759         struct dpll clock;
 760         int max_n;
 761         bool found = false;
 762         /* approximately equals target * 0.00585 */
 763         int err_most = (target >> 8) + (target >> 9);
 764
 765         memset(best_clock, 0, sizeof(*best_clock));
 766
 767         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 768
 769         max_n = limit->n.max;
 770         /* based on hardware requirement, prefer smaller n to precision */
 771         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 772                 /* based on hardware requirement, prefere larger m1,m2 */
 773                 for (clock.m1 = limit->m1.max;
 774                      clock.m1 >= limit->m1.min; clock.m1--) {
 775                         for (clock.m2 = limit->m2.max;
 776                              clock.m2 >= limit->m2.min; clock.m2--) {
 777                                 for (clock.p1 = limit->p1.max;
 778                                      clock.p1 >= limit->p1.min; clock.p1--) {
 779                                         int this_err;
 780
 781                                         i9xx_calc_dpll_params(refclk, &clock);
 782                                         if (!intel_PLL_is_valid(to_i915(dev),
 783                                                                 limit,
 784                                                                 &clock))
 785                                                 continue;
 786
 787                                         this_err = abs(clock.dot - target);
 788                                         if (this_err < err_most) {
 789                                                 *best_clock = clock;
 790                                                 err_most = this_err;
 791                                                 max_n = clock.n;
 792                                                 found = true;
 793                                         }
 794                                 }
 795                         }
 796                 }
 797         }
 798         return found;
 799 }
 800
 801 /*
 802  * Check if the calculated PLL configuration is more optimal compared to the
 803  * best configuration and error found so far. Return the calculated error.
 804  */
 805 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 806                                const struct dpll *calculated_clock,
 807                                const struct dpll *best_clock,
 808                                unsigned int best_error_ppm,
 809                                unsigned int *error_ppm)
 810 {
 811         /*
 812          * For CHV ignore the error and consider only the P value.
 813          * Prefer a bigger P value based on HW requirements.
 814          */
 815         if (IS_CHERRYVIEW(to_i915(dev))) {
 816                 *error_ppm = 0;
 817
 818                 return calculated_clock->p > best_clock->p;
 819         }
 820
 821         if (WARN_ON_ONCE(!target_freq))
 822                 return false;
 823
 824         *error_ppm = div_u64(1000000ULL *
 825                                 abs(target_freq - calculated_clock->dot),
 826                              target_freq);
 827         /*
 828          * Prefer a better P value over a better (smaller) error if the error
 829          * is small. Ensure this preference for future configurations too by
 830          * setting the error to 0.
 831          */
 832         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 833                 *error_ppm = 0;
 834
 835                 return true;
 836         }
 837
 838         return *error_ppm + 10 < best_error_ppm;
 839 }
 840
 841 /*
 842  * Returns a set of divisors for the desired target clock with the given
 843  * refclk, or FALSE.  The returned values represent the clock equation:
 844  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 845  */
 846 static bool
 847 vlv_find_best_dpll(const struct intel_limit *limit,
 848                    struct intel_crtc_state *crtc_state,
 849                    int target, int refclk, struct dpll *match_clock,
 850                    struct dpll *best_clock)
 851 {
 852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 853         struct drm_device *dev = crtc->base.dev;
 854         struct dpll clock;
 855         unsigned int bestppm = 1000000;
 856         /* min update 19.2 MHz */
 857         int max_n = min(limit->n.max, refclk / 19200);
 858         bool found = false;
 859
 860         target *= 5; /* fast clock */
 861
 862         memset(best_clock, 0, sizeof(*best_clock));
 863
 864         /* based on hardware requirement, prefer smaller n to precision */
 865         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 866                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 867                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 868                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 869                                 clock.p = clock.p1 * clock.p2;
 870                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 871                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 872                                         unsigned int ppm;
 873
 874                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 875                                                                      refclk * clock.m1);
 876
 877                                         vlv_calc_dpll_params(refclk, &clock);
 878
 879                                         if (!intel_PLL_is_valid(to_i915(dev),
 880                                                                 limit,
 881                                                                 &clock))
 882                                                 continue;
 883
 884                                         if (!vlv_PLL_is_optimal(dev, target,
 885                                                                 &clock,
 886                                                                 best_clock,
 887                                                                 bestppm, &ppm))
 888                                                 continue;
 889
 890                                         *best_clock = clock;
 891                                         bestppm = ppm;
 892                                         found = true;
 893                                 }
 894                         }
 895                 }
 896         }
 897
 898         return found;
 899 }
 900
 901 /*
 902  * Returns a set of divisors for the desired target clock with the given
 903  * refclk, or FALSE.  The returned values represent the clock equation:
 904  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 905  */
 906 static bool
 907 chv_find_best_dpll(const struct intel_limit *limit,
 908                    struct intel_crtc_state *crtc_state,
 909                    int target, int refclk, struct dpll *match_clock,
 910                    struct dpll *best_clock)
 911 {
 912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 913         struct drm_device *dev = crtc->base.dev;
 914         unsigned int best_error_ppm;
 915         struct dpll clock;
 916         uint64_t m2;
 917         int found = false;
 918
 919         memset(best_clock, 0, sizeof(*best_clock));
 920         best_error_ppm = 1000000;
 921
 922         /*
 923          * Based on hardware doc, the n always set to 1, and m1 always
 924          * set to 2.  If requires to support 200Mhz refclk, we need to
 925          * revisit this because n may not 1 anymore.
 926          */
 927         clock.n = 1, clock.m1 = 2;
 928         target *= 5;    /* fast clock */
 929
 930         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 931                 for (clock.p2 = limit->p2.p2_fast;
 932                                 clock.p2 >= limit->p2.p2_slow;
 933                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 934                         unsigned int error_ppm;
 935
 936                         clock.p = clock.p1 * clock.p2;
 937
 938                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 939                                         clock.n) << 22, refclk * clock.m1);
 940
 941                         if (m2 > INT_MAX/clock.m1)
 942                                 continue;
 943
 944                         clock.m2 = m2;
 945
 946                         chv_calc_dpll_params(refclk, &clock);
 947
 948                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 949                                 continue;
 950
 951                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 952                                                 best_error_ppm, &error_ppm))
 953                                 continue;
 954
 955                         *best_clock = clock;
 956                         best_error_ppm = error_ppm;
 957                         found = true;
 958                 }
 959         }
 960
 961         return found;
 962 }
 963
 964 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 965                         struct dpll *best_clock)
 966 {
 967         int refclk = 100000;
 968         const struct intel_limit *limit = &intel_limits_bxt;
 969
 970         return chv_find_best_dpll(limit, crtc_state,
 971                                   target_clock, refclk, NULL, best_clock);
 972 }
 973
 974 bool intel_crtc_active(struct intel_crtc *crtc)
 975 {
 976         /* Be paranoid as we can arrive here with only partial
 977          * state retrieved from the hardware during setup.
 978          *
 979          * We can ditch the adjusted_mode.crtc_clock check as soon
 980          * as Haswell has gained clock readout/fastboot support.
 981          *
 982          * We can ditch the crtc->primary->fb check as soon as we can
 983          * properly reconstruct framebuffers.
 984          *
 985          * FIXME: The intel_crtc->active here should be switched to
 986          * crtc->state->active once we have proper CRTC states wired up
 987          * for atomic.
 988          */
 989         return crtc->active && crtc->base.primary->state->fb &&
 990                 crtc->config->base.adjusted_mode.crtc_clock;
 991 }
 992
 993 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 994                                              enum pipe pipe)
 995 {
 996         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 997
 998         return crtc->config->cpu_transcoder;
 999 }
1000
1001 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1002 {
1003         i915_reg_t reg = PIPEDSL(pipe);
1004         u32 line1, line2;
1005         u32 line_mask;
1006
1007         if (IS_GEN2(dev_priv))
1008                 line_mask = DSL_LINEMASK_GEN2;
1009         else
1010                 line_mask = DSL_LINEMASK_GEN3;
1011
1012         line1 = I915_READ(reg) & line_mask;
1013         msleep(5);
1014         line2 = I915_READ(reg) & line_mask;
1015
1016         return line1 == line2;
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @crtc: crtc whose pipe to wait for
1022  *
1023  * After disabling a pipe, we can't wait for vblank in the usual way,
1024  * spinning on the vblank interrupt status bit, since we won't actually
1025  * see an interrupt when the pipe is disabled.
1026  *
1027  * On Gen4 and above:
1028  *   wait for the pipe register state bit to turn off
1029  *
1030  * Otherwise:
1031  *   wait for the display line value to settle (it usually
1032  *   ends up stopping at the start of the next frame).
1033  *
1034  */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1038         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1039         enum pipe pipe = crtc->pipe;
1040
1041         if (INTEL_GEN(dev_priv) >= 4) {
1042                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1043
1044                 /* Wait for the Pipe State to go off */
1045                 if (intel_wait_for_register(dev_priv,
1046                                             reg, I965_PIPECONF_ACTIVE, 0,
1047                                             100))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         } else {
1050                 /* Wait for the display line to settle */
1051                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1052                         WARN(1, "pipe_off wait timed out\n");
1053         }
1054 }
1055
1056 /* Only for pre-ILK configs */
1057 void assert_pll(struct drm_i915_private *dev_priv,
1058                 enum pipe pipe, bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         val = I915_READ(DPLL(pipe));
1064         cur_state = !!(val & DPLL_VCO_ENABLE);
1065         I915_STATE_WARN(cur_state != state,
1066              "PLL state assertion failure (expected %s, current %s)\n",
1067                         onoff(state), onoff(cur_state));
1068 }
1069
1070 /* XXX: the dsi pll is shared between MIPI DSI ports */
1071 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1072 {
1073         u32 val;
1074         bool cur_state;
1075
1076         mutex_lock(&dev_priv->sb_lock);
1077         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1078         mutex_unlock(&dev_priv->sb_lock);
1079
1080         cur_state = val & DSI_PLL_VCO_EN;
1081         I915_STATE_WARN(cur_state != state,
1082              "DSI PLL state assertion failure (expected %s, current %s)\n",
1083                         onoff(state), onoff(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087                           enum pipe pipe, bool state)
1088 {
1089         bool cur_state;
1090         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091                                                                       pipe);
1092
1093         if (HAS_DDI(dev_priv)) {
1094                 /* DDI does not have a specific FDI_TX register */
1095                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1096                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097         } else {
1098                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113
1114         val = I915_READ(FDI_RX_CTL(pipe));
1115         cur_state = !!(val & FDI_RX_ENABLE);
1116         I915_STATE_WARN(cur_state != state,
1117              "FDI RX state assertion failure (expected %s, current %s)\n",
1118                         onoff(state), onoff(cur_state));
1119 }
1120 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1121 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122
1123 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1124                                       enum pipe pipe)
1125 {
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (IS_GEN5(dev_priv))
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv))
1134                 return;
1135
1136         val = I915_READ(FDI_TX_CTL(pipe));
1137         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1138 }
1139
1140 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1141                        enum pipe pipe, bool state)
1142 {
1143         u32 val;
1144         bool cur_state;
1145
1146         val = I915_READ(FDI_RX_CTL(pipe));
1147         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1148         I915_STATE_WARN(cur_state != state,
1149              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1150                         onoff(state), onoff(cur_state));
1151 }
1152
1153 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155         i915_reg_t pp_reg;
1156         u32 val;
1157         enum pipe panel_pipe = PIPE_A;
1158         bool locked = true;
1159
1160         if (WARN_ON(HAS_DDI(dev_priv)))
1161                 return;
1162
1163         if (HAS_PCH_SPLIT(dev_priv)) {
1164                 u32 port_sel;
1165
1166                 pp_reg = PP_CONTROL(0);
1167                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1168
1169                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1170                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1171                         panel_pipe = PIPE_B;
1172                 /* XXX: else fix for eDP */
1173         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1174                 /* presumably write lock depends on pipe, not port select */
1175                 pp_reg = PP_CONTROL(pipe);
1176                 panel_pipe = pipe;
1177         } else {
1178                 pp_reg = PP_CONTROL(0);
1179                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1180                         panel_pipe = PIPE_B;
1181         }
1182
1183         val = I915_READ(pp_reg);
1184         if (!(val & PANEL_POWER_ON) ||
1185             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1186                 locked = false;
1187
1188         I915_STATE_WARN(panel_pipe == pipe && locked,
1189              "panel assertion failure, pipe %c regs locked\n",
1190              pipe_name(pipe));
1191 }
1192
1193 static void assert_cursor(struct drm_i915_private *dev_priv,
1194                           enum pipe pipe, bool state)
1195 {
1196         bool cur_state;
1197
1198         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1199                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1200         else
1201                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1202
1203         I915_STATE_WARN(cur_state != state,
1204              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1205                         pipe_name(pipe), onoff(state), onoff(cur_state));
1206 }
1207 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1208 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1209
1210 void assert_pipe(struct drm_i915_private *dev_priv,
1211                  enum pipe pipe, bool state)
1212 {
1213         bool cur_state;
1214         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1215                                                                       pipe);
1216         enum intel_display_power_domain power_domain;
1217
1218         /* we keep both pipes enabled on 830 */
1219         if (IS_I830(dev_priv))
1220                 state = true;
1221
1222         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1223         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1224                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1225                 cur_state = !!(val & PIPECONF_ENABLE);
1226
1227                 intel_display_power_put(dev_priv, power_domain);
1228         } else {
1229                 cur_state = false;
1230         }
1231
1232         I915_STATE_WARN(cur_state != state,
1233              "pipe %c assertion failure (expected %s, current %s)\n",
1234                         pipe_name(pipe), onoff(state), onoff(cur_state));
1235 }
1236
1237 static void assert_plane(struct drm_i915_private *dev_priv,
1238                          enum plane plane, bool state)
1239 {
1240         u32 val;
1241         bool cur_state;
1242
1243         val = I915_READ(DSPCNTR(plane));
1244         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1245         I915_STATE_WARN(cur_state != state,
1246              "plane %c assertion failure (expected %s, current %s)\n",
1247                         plane_name(plane), onoff(state), onoff(cur_state));
1248 }
1249
1250 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1251 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1252
1253 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1254                                    enum pipe pipe)
1255 {
1256         int i;
1257
1258         /* Primary planes are fixed to pipes on gen4+ */
1259         if (INTEL_GEN(dev_priv) >= 4) {
1260                 u32 val = I915_READ(DSPCNTR(pipe));
1261                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1262                      "plane %c assertion failure, should be disabled but not\n",
1263                      plane_name(pipe));
1264                 return;
1265         }
1266
1267         /* Need to check both planes against the pipe */
1268         for_each_pipe(dev_priv, i) {
1269                 u32 val = I915_READ(DSPCNTR(i));
1270                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         int sprite;
1282
1283         if (INTEL_GEN(dev_priv) >= 9) {
1284                 for_each_sprite(dev_priv, pipe, sprite) {
1285                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1286                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1287                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1288                              sprite, pipe_name(pipe));
1289                 }
1290         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1291                 for_each_sprite(dev_priv, pipe, sprite) {
1292                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1293                         I915_STATE_WARN(val & SP_ENABLE,
1294                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1295                              sprite_name(pipe, sprite), pipe_name(pipe));
1296                 }
1297         } else if (INTEL_GEN(dev_priv) >= 7) {
1298                 u32 val = I915_READ(SPRCTL(pipe));
1299                 I915_STATE_WARN(val & SPRITE_ENABLE,
1300                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301                      plane_name(pipe), pipe_name(pipe));
1302         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1303                 u32 val = I915_READ(DVSCNTR(pipe));
1304                 I915_STATE_WARN(val & DVS_ENABLE,
1305                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306                      plane_name(pipe), pipe_name(pipe));
1307         }
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313                 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         val = I915_READ(PCH_TRANSCONF(pipe));
1323         enabled = !!(val & TRANS_ENABLE);
1324         I915_STATE_WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv)) {
1336                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1337                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1338                         return false;
1339         } else if (IS_CHERRYVIEW(dev_priv)) {
1340                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & SDVO_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv)) {
1356                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1357                         return false;
1358         } else if (IS_CHERRYVIEW(dev_priv)) {
1359                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1360                         return false;
1361         } else {
1362                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1363                         return false;
1364         }
1365         return true;
1366 }
1367
1368 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1369                               enum pipe pipe, u32 val)
1370 {
1371         if ((val & LVDS_PORT_EN) == 0)
1372                 return false;
1373
1374         if (HAS_PCH_CPT(dev_priv)) {
1375                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & ADPA_DAC_ENABLE) == 0)
1388                 return false;
1389         if (HAS_PCH_CPT(dev_priv)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1400                                    enum pipe pipe, i915_reg_t reg,
1401                                    u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              i915_mmio_reg_offset(reg), pipe_name(pipe));
1407
1408         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, i915_reg_t reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              i915_mmio_reg_offset(reg), pipe_name(pipe));
1420
1421         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         u32 val;
1430
1431         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1434
1435         val = I915_READ(PCH_ADPA);
1436         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1437              "PCH VGA enabled on transcoder %c, should be disabled\n",
1438              pipe_name(pipe));
1439
1440         val = I915_READ(PCH_LVDS);
1441         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1442              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1443              pipe_name(pipe));
1444
1445         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1448 }
1449
1450 static void _vlv_enable_pll(struct intel_crtc *crtc,
1451                             const struct intel_crtc_state *pipe_config)
1452 {
1453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1454         enum pipe pipe = crtc->pipe;
1455
1456         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457         POSTING_READ(DPLL(pipe));
1458         udelay(150);
1459
1460         if (intel_wait_for_register(dev_priv,
1461                                     DPLL(pipe),
1462                                     DPLL_LOCK_VLV,
1463                                     DPLL_LOCK_VLV,
1464                                     1))
1465                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1466 }
1467
1468 static void vlv_enable_pll(struct intel_crtc *crtc,
1469                            const struct intel_crtc_state *pipe_config)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1472         enum pipe pipe = crtc->pipe;
1473
1474         assert_pipe_disabled(dev_priv, pipe);
1475
1476         /* PLL is protected by panel, make sure we can write it */
1477         assert_panel_unlocked(dev_priv, pipe);
1478
1479         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1480                 _vlv_enable_pll(crtc, pipe_config);
1481
1482         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1483         POSTING_READ(DPLL_MD(pipe));
1484 }
1485
1486
1487 static void _chv_enable_pll(struct intel_crtc *crtc,
1488                             const struct intel_crtc_state *pipe_config)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1491         enum pipe pipe = crtc->pipe;
1492         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1493         u32 tmp;
1494
1495         mutex_lock(&dev_priv->sb_lock);
1496
1497         /* Enable back the 10bit clock to display controller */
1498         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1499         tmp |= DPIO_DCLKP_EN;
1500         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1501
1502         mutex_unlock(&dev_priv->sb_lock);
1503
1504         /*
1505          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1506          */
1507         udelay(1);
1508
1509         /* Enable PLL */
1510         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1511
1512         /* Check PLL is locked */
1513         if (intel_wait_for_register(dev_priv,
1514                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1515                                     1))
1516                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1517 }
1518
1519 static void chv_enable_pll(struct intel_crtc *crtc,
1520                            const struct intel_crtc_state *pipe_config)
1521 {
1522         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1523         enum pipe pipe = crtc->pipe;
1524
1525         assert_pipe_disabled(dev_priv, pipe);
1526
1527         /* PLL is protected by panel, make sure we can write it */
1528         assert_panel_unlocked(dev_priv, pipe);
1529
1530         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1531                 _chv_enable_pll(crtc, pipe_config);
1532
1533         if (pipe != PIPE_A) {
1534                 /*
1535                  * WaPixelRepeatModeFixForC0:chv
1536                  *
1537                  * DPLLCMD is AWOL. Use chicken bits to propagate
1538                  * the value from DPLLBMD to either pipe B or C.
1539                  */
1540                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1541                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1542                 I915_WRITE(CBR4_VLV, 0);
1543                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1544
1545                 /*
1546                  * DPLLB VGA mode also seems to cause problems.
1547                  * We should always have it disabled.
1548                  */
1549                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1550         } else {
1551                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1552                 POSTING_READ(DPLL_MD(pipe));
1553         }
1554 }
1555
1556 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1557 {
1558         struct intel_crtc *crtc;
1559         int count = 0;
1560
1561         for_each_intel_crtc(&dev_priv->drm, crtc) {
1562                 count += crtc->base.state->active &&
1563                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1564         }
1565
1566         return count;
1567 }
1568
1569 static void i9xx_enable_pll(struct intel_crtc *crtc,
1570                             const struct intel_crtc_state *crtc_state)
1571 {
1572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1573         i915_reg_t reg = DPLL(crtc->pipe);
1574         u32 dpll = crtc_state->dpll_hw_state.dpll;
1575         int i;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         /* PLL is protected by panel, make sure we can write it */
1580         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1581                 assert_panel_unlocked(dev_priv, crtc->pipe);
1582
1583         /* Enable DVO 2x clock on both PLLs if necessary */
1584         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1585                 /*
1586                  * It appears to be important that we don't enable this
1587                  * for the current pipe before otherwise configuring the
1588                  * PLL. No idea how this should be handled if multiple
1589                  * DVO outputs are enabled simultaneosly.
1590                  */
1591                 dpll |= DPLL_DVO_2X_MODE;
1592                 I915_WRITE(DPLL(!crtc->pipe),
1593                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1594         }
1595
1596         /*
1597          * Apparently we need to have VGA mode enabled prior to changing
1598          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1599          * dividers, even though the register value does change.
1600          */
1601         I915_WRITE(reg, 0);
1602
1603         I915_WRITE(reg, dpll);
1604
1605         /* Wait for the clocks to stabilize. */
1606         POSTING_READ(reg);
1607         udelay(150);
1608
1609         if (INTEL_GEN(dev_priv) >= 4) {
1610                 I915_WRITE(DPLL_MD(crtc->pipe),
1611                            crtc_state->dpll_hw_state.dpll_md);
1612         } else {
1613                 /* The pixel multiplier can only be updated once the
1614                  * DPLL is enabled and the clocks are stable.
1615                  *
1616                  * So write it again.
1617                  */
1618                 I915_WRITE(reg, dpll);
1619         }
1620
1621         /* We do this three times for luck */
1622         for (i = 0; i < 3; i++) {
1623                 I915_WRITE(reg, dpll);
1624                 POSTING_READ(reg);
1625                 udelay(150); /* wait for warmup */
1626         }
1627 }
1628
1629 static void i9xx_disable_pll(struct intel_crtc *crtc)
1630 {
1631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1632         enum pipe pipe = crtc->pipe;
1633
1634         /* Disable DVO 2x clock on both PLLs if necessary */
1635         if (IS_I830(dev_priv) &&
1636             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1637             !intel_num_dvo_pipes(dev_priv)) {
1638                 I915_WRITE(DPLL(PIPE_B),
1639                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1640                 I915_WRITE(DPLL(PIPE_A),
1641                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1642         }
1643
1644         /* Don't disable pipe or pipe PLLs if needed */
1645         if (IS_I830(dev_priv))
1646                 return;
1647
1648         /* Make sure the pipe isn't still relying on us */
1649         assert_pipe_disabled(dev_priv, pipe);
1650
1651         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1652         POSTING_READ(DPLL(pipe));
1653 }
1654
1655 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1656 {
1657         u32 val;
1658
1659         /* Make sure the pipe isn't still relying on us */
1660         assert_pipe_disabled(dev_priv, pipe);
1661
1662         val = DPLL_INTEGRATED_REF_CLK_VLV |
1663                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1664         if (pipe != PIPE_A)
1665                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1666
1667         I915_WRITE(DPLL(pipe), val);
1668         POSTING_READ(DPLL(pipe));
1669 }
1670
1671 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1672 {
1673         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1674         u32 val;
1675
1676         /* Make sure the pipe isn't still relying on us */
1677         assert_pipe_disabled(dev_priv, pipe);
1678
1679         val = DPLL_SSC_REF_CLK_CHV |
1680                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1681         if (pipe != PIPE_A)
1682                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1683
1684         I915_WRITE(DPLL(pipe), val);
1685         POSTING_READ(DPLL(pipe));
1686
1687         mutex_lock(&dev_priv->sb_lock);
1688
1689         /* Disable 10bit clock to display controller */
1690         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1691         val &= ~DPIO_DCLKP_EN;
1692         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1693
1694         mutex_unlock(&dev_priv->sb_lock);
1695 }
1696
1697 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1698                          struct intel_digital_port *dport,
1699                          unsigned int expected_mask)
1700 {
1701         u32 port_mask;
1702         i915_reg_t dpll_reg;
1703
1704         switch (dport->base.port) {
1705         case PORT_B:
1706                 port_mask = DPLL_PORTB_READY_MASK;
1707                 dpll_reg = DPLL(0);
1708                 break;
1709         case PORT_C:
1710                 port_mask = DPLL_PORTC_READY_MASK;
1711                 dpll_reg = DPLL(0);
1712                 expected_mask <<= 4;
1713                 break;
1714         case PORT_D:
1715                 port_mask = DPLL_PORTD_READY_MASK;
1716                 dpll_reg = DPIO_PHY_STATUS;
1717                 break;
1718         default:
1719                 BUG();
1720         }
1721
1722         if (intel_wait_for_register(dev_priv,
1723                                     dpll_reg, port_mask, expected_mask,
1724                                     1000))
1725                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1726                      port_name(dport->base.port),
1727                      I915_READ(dpll_reg) & port_mask, expected_mask);
1728 }
1729
1730 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1731                                            enum pipe pipe)
1732 {
1733         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1734                                                                 pipe);
1735         i915_reg_t reg;
1736         uint32_t val, pipeconf_val;
1737
1738         /* Make sure PCH DPLL is enabled */
1739         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1740
1741         /* FDI must be feeding us bits for PCH ports */
1742         assert_fdi_tx_enabled(dev_priv, pipe);
1743         assert_fdi_rx_enabled(dev_priv, pipe);
1744
1745         if (HAS_PCH_CPT(dev_priv)) {
1746                 /* Workaround: Set the timing override bit before enabling the
1747                  * pch transcoder. */
1748                 reg = TRANS_CHICKEN2(pipe);
1749                 val = I915_READ(reg);
1750                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751                 I915_WRITE(reg, val);
1752         }
1753
1754         reg = PCH_TRANSCONF(pipe);
1755         val = I915_READ(reg);
1756         pipeconf_val = I915_READ(PIPECONF(pipe));
1757
1758         if (HAS_PCH_IBX(dev_priv)) {
1759                 /*
1760                  * Make the BPC in transcoder be consistent with
1761                  * that in pipeconf reg. For HDMI we must use 8bpc
1762                  * here for both 8bpc and 12bpc.
1763                  */
1764                 val &= ~PIPECONF_BPC_MASK;
1765                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1766                         val |= PIPECONF_8BPC;
1767                 else
1768                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1769         }
1770
1771         val &= ~TRANS_INTERLACE_MASK;
1772         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1773                 if (HAS_PCH_IBX(dev_priv) &&
1774                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1775                         val |= TRANS_LEGACY_INTERLACED_ILK;
1776                 else
1777                         val |= TRANS_INTERLACED;
1778         else
1779                 val |= TRANS_PROGRESSIVE;
1780
1781         I915_WRITE(reg, val | TRANS_ENABLE);
1782         if (intel_wait_for_register(dev_priv,
1783                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1784                                     100))
1785                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1786 }
1787
1788 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789                                       enum transcoder cpu_transcoder)
1790 {
1791         u32 val, pipeconf_val;
1792
1793         /* FDI must be feeding us bits for PCH ports */
1794         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1795         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1796
1797         /* Workaround: set timing override bit. */
1798         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1799         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1801
1802         val = TRANS_ENABLE;
1803         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1804
1805         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1806             PIPECONF_INTERLACED_ILK)
1807                 val |= TRANS_INTERLACED;
1808         else
1809                 val |= TRANS_PROGRESSIVE;
1810
1811         I915_WRITE(LPT_TRANSCONF, val);
1812         if (intel_wait_for_register(dev_priv,
1813                                     LPT_TRANSCONF,
1814                                     TRANS_STATE_ENABLE,
1815                                     TRANS_STATE_ENABLE,
1816                                     100))
1817                 DRM_ERROR("Failed to enable PCH transcoder\n");
1818 }
1819
1820 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1821                                             enum pipe pipe)
1822 {
1823         i915_reg_t reg;
1824         uint32_t val;
1825
1826         /* FDI relies on the transcoder */
1827         assert_fdi_tx_disabled(dev_priv, pipe);
1828         assert_fdi_rx_disabled(dev_priv, pipe);
1829
1830         /* Ports must be off as well */
1831         assert_pch_ports_disabled(dev_priv, pipe);
1832
1833         reg = PCH_TRANSCONF(pipe);
1834         val = I915_READ(reg);
1835         val &= ~TRANS_ENABLE;
1836         I915_WRITE(reg, val);
1837         /* wait for PCH transcoder off, transcoder state */
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, 0,
1840                                     50))
1841                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1842
1843         if (HAS_PCH_CPT(dev_priv)) {
1844                 /* Workaround: Clear the timing override chicken bit again. */
1845                 reg = TRANS_CHICKEN2(pipe);
1846                 val = I915_READ(reg);
1847                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848                 I915_WRITE(reg, val);
1849         }
1850 }
1851
1852 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1853 {
1854         u32 val;
1855
1856         val = I915_READ(LPT_TRANSCONF);
1857         val &= ~TRANS_ENABLE;
1858         I915_WRITE(LPT_TRANSCONF, val);
1859         /* wait for PCH transcoder off, transcoder state */
1860         if (intel_wait_for_register(dev_priv,
1861                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1862                                     50))
1863                 DRM_ERROR("Failed to disable PCH transcoder\n");
1864
1865         /* Workaround: clear timing override bit. */
1866         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1867         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1869 }
1870
1871 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1872 {
1873         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874
1875         WARN_ON(!crtc->config->has_pch_encoder);
1876
1877         if (HAS_PCH_LPT(dev_priv))
1878                 return PIPE_A;
1879         else
1880                 return crtc->pipe;
1881 }
1882
1883 /**
1884  * intel_enable_pipe - enable a pipe, asserting requirements
1885  * @crtc: crtc responsible for the pipe
1886  *
1887  * Enable @crtc's pipe, making sure that various hardware specific requirements
1888  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1889  */
1890 static void intel_enable_pipe(struct intel_crtc *crtc)
1891 {
1892         struct drm_device *dev = crtc->base.dev;
1893         struct drm_i915_private *dev_priv = to_i915(dev);
1894         enum pipe pipe = crtc->pipe;
1895         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1896         i915_reg_t reg;
1897         u32 val;
1898
1899         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1900
1901         assert_planes_disabled(dev_priv, pipe);
1902         assert_cursor_disabled(dev_priv, pipe);
1903         assert_sprites_disabled(dev_priv, pipe);
1904
1905         /*
1906          * A pipe without a PLL won't actually be able to drive bits from
1907          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1908          * need the check.
1909          */
1910         if (HAS_GMCH_DISPLAY(dev_priv)) {
1911                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1912                         assert_dsi_pll_enabled(dev_priv);
1913                 else
1914                         assert_pll_enabled(dev_priv, pipe);
1915         } else {
1916                 if (crtc->config->has_pch_encoder) {
1917                         /* if driving the PCH, we need FDI enabled */
1918                         assert_fdi_rx_pll_enabled(dev_priv,
1919                                                   intel_crtc_pch_transcoder(crtc));
1920                         assert_fdi_tx_pll_enabled(dev_priv,
1921                                                   (enum pipe) cpu_transcoder);
1922                 }
1923                 /* FIXME: assert CPU port conditions for SNB+ */
1924         }
1925
1926         reg = PIPECONF(cpu_transcoder);
1927         val = I915_READ(reg);
1928         if (val & PIPECONF_ENABLE) {
1929                 /* we keep both pipes enabled on 830 */
1930                 WARN_ON(!IS_I830(dev_priv));
1931                 return;
1932         }
1933
1934         I915_WRITE(reg, val | PIPECONF_ENABLE);
1935         POSTING_READ(reg);
1936
1937         /*
1938          * Until the pipe starts DSL will read as 0, which would cause
1939          * an apparent vblank timestamp jump, which messes up also the
1940          * frame count when it's derived from the timestamps. So let's
1941          * wait for the pipe to start properly before we call
1942          * drm_crtc_vblank_on()
1943          */
1944         if (dev->max_vblank_count == 0 &&
1945             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1946                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1947 }
1948
1949 /**
1950  * intel_disable_pipe - disable a pipe, asserting requirements
1951  * @crtc: crtc whose pipes is to be disabled
1952  *
1953  * Disable the pipe of @crtc, making sure that various hardware
1954  * specific requirements are met, if applicable, e.g. plane
1955  * disabled, panel fitter off, etc.
1956  *
1957  * Will wait until the pipe has shut down before returning.
1958  */
1959 static void intel_disable_pipe(struct intel_crtc *crtc)
1960 {
1961         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1962         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1963         enum pipe pipe = crtc->pipe;
1964         i915_reg_t reg;
1965         u32 val;
1966
1967         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1968
1969         /*
1970          * Make sure planes won't keep trying to pump pixels to us,
1971          * or we might hang the display.
1972          */
1973         assert_planes_disabled(dev_priv, pipe);
1974         assert_cursor_disabled(dev_priv, pipe);
1975         assert_sprites_disabled(dev_priv, pipe);
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if ((val & PIPECONF_ENABLE) == 0)
1980                 return;
1981
1982         /*
1983          * Double wide has implications for planes
1984          * so best keep it disabled when not needed.
1985          */
1986         if (crtc->config->double_wide)
1987                 val &= ~PIPECONF_DOUBLE_WIDE;
1988
1989         /* Don't disable pipe or pipe PLLs if needed */
1990         if (!IS_I830(dev_priv))
1991                 val &= ~PIPECONF_ENABLE;
1992
1993         I915_WRITE(reg, val);
1994         if ((val & PIPECONF_ENABLE) == 0)
1995                 intel_wait_for_pipe_off(crtc);
1996 }
1997
1998 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1999 {
2000         return IS_GEN2(dev_priv) ? 2048 : 4096;
2001 }
2002
2003 static unsigned int
2004 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2005 {
2006         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2007         unsigned int cpp = fb->format->cpp[plane];
2008
2009         switch (fb->modifier) {
2010         case DRM_FORMAT_MOD_LINEAR:
2011                 return cpp;
2012         case I915_FORMAT_MOD_X_TILED:
2013                 if (IS_GEN2(dev_priv))
2014                         return 128;
2015                 else
2016                         return 512;
2017         case I915_FORMAT_MOD_Y_TILED_CCS:
2018                 if (plane == 1)
2019                         return 128;
2020                 /* fall through */
2021         case I915_FORMAT_MOD_Y_TILED:
2022                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2023                         return 128;
2024                 else
2025                         return 512;
2026         case I915_FORMAT_MOD_Yf_TILED_CCS:
2027                 if (plane == 1)
2028                         return 128;
2029                 /* fall through */
2030         case I915_FORMAT_MOD_Yf_TILED:
2031                 switch (cpp) {
2032                 case 1:
2033                         return 64;
2034                 case 2:
2035                 case 4:
2036                         return 128;
2037                 case 8:
2038                 case 16:
2039                         return 256;
2040                 default:
2041                         MISSING_CASE(cpp);
2042                         return cpp;
2043                 }
2044                 break;
2045         default:
2046                 MISSING_CASE(fb->modifier);
2047                 return cpp;
2048         }
2049 }
2050
2051 static unsigned int
2052 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2053 {
2054         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2055                 return 1;
2056         else
2057                 return intel_tile_size(to_i915(fb->dev)) /
2058                         intel_tile_width_bytes(fb, plane);
2059 }
2060
2061 /* Return the tile dimensions in pixel units */
2062 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2063                             unsigned int *tile_width,
2064                             unsigned int *tile_height)
2065 {
2066         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2067         unsigned int cpp = fb->format->cpp[plane];
2068
2069         *tile_width = tile_width_bytes / cpp;
2070         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2071 }
2072
2073 unsigned int
2074 intel_fb_align_height(const struct drm_framebuffer *fb,
2075                       int plane, unsigned int height)
2076 {
2077         unsigned int tile_height = intel_tile_height(fb, plane);
2078
2079         return ALIGN(height, tile_height);
2080 }
2081
2082 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2083 {
2084         unsigned int size = 0;
2085         int i;
2086
2087         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2088                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2089
2090         return size;
2091 }
2092
2093 static void
2094 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2095                         const struct drm_framebuffer *fb,
2096                         unsigned int rotation)
2097 {
2098         view->type = I915_GGTT_VIEW_NORMAL;
2099         if (drm_rotation_90_or_270(rotation)) {
2100                 view->type = I915_GGTT_VIEW_ROTATED;
2101                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2102         }
2103 }
2104
2105 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2106 {
2107         if (IS_I830(dev_priv))
2108                 return 16 * 1024;
2109         else if (IS_I85X(dev_priv))
2110                 return 256;
2111         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2112                 return 32;
2113         else
2114                 return 4 * 1024;
2115 }
2116
2117 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2118 {
2119         if (INTEL_INFO(dev_priv)->gen >= 9)
2120                 return 256 * 1024;
2121         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2122                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2123                 return 128 * 1024;
2124         else if (INTEL_INFO(dev_priv)->gen >= 4)
2125                 return 4 * 1024;
2126         else
2127                 return 0;
2128 }
2129
2130 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2131                                          int plane)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2134
2135         /* AUX_DIST needs only 4K alignment */
2136         if (plane == 1)
2137                 return 4096;
2138
2139         switch (fb->modifier) {
2140         case DRM_FORMAT_MOD_LINEAR:
2141                 return intel_linear_alignment(dev_priv);
2142         case I915_FORMAT_MOD_X_TILED:
2143                 if (INTEL_GEN(dev_priv) >= 9)
2144                         return 256 * 1024;
2145                 return 0;
2146         case I915_FORMAT_MOD_Y_TILED_CCS:
2147         case I915_FORMAT_MOD_Yf_TILED_CCS:
2148         case I915_FORMAT_MOD_Y_TILED:
2149         case I915_FORMAT_MOD_Yf_TILED:
2150                 return 1 * 1024 * 1024;
2151         default:
2152                 MISSING_CASE(fb->modifier);
2153                 return 0;
2154         }
2155 }
2156
2157 struct i915_vma *
2158 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2159 {
2160         struct drm_device *dev = fb->dev;
2161         struct drm_i915_private *dev_priv = to_i915(dev);
2162         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2163         struct i915_ggtt_view view;
2164         struct i915_vma *vma;
2165         u32 alignment;
2166
2167         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2168
2169         alignment = intel_surf_alignment(fb, 0);
2170
2171         intel_fill_fb_ggtt_view(&view, fb, rotation);
2172
2173         /* Note that the w/a also requires 64 PTE of padding following the
2174          * bo. We currently fill all unused PTE with the shadow page and so
2175          * we should always have valid PTE following the scanout preventing
2176          * the VT-d warning.
2177          */
2178         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2179                 alignment = 256 * 1024;
2180
2181         /*
2182          * Global gtt pte registers are special registers which actually forward
2183          * writes to a chunk of system memory. Which means that there is no risk
2184          * that the register values disappear as soon as we call
2185          * intel_runtime_pm_put(), so it is correct to wrap only the
2186          * pin/unpin/fence and not more.
2187          */
2188         intel_runtime_pm_get(dev_priv);
2189
2190         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2191
2192         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2193         if (IS_ERR(vma))
2194                 goto err;
2195
2196         if (i915_vma_is_map_and_fenceable(vma)) {
2197                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2198                  * fence, whereas 965+ only requires a fence if using
2199                  * framebuffer compression.  For simplicity, we always, when
2200                  * possible, install a fence as the cost is not that onerous.
2201                  *
2202                  * If we fail to fence the tiled scanout, then either the
2203                  * modeset will reject the change (which is highly unlikely as
2204                  * the affected systems, all but one, do not have unmappable
2205                  * space) or we will not be able to enable full powersaving
2206                  * techniques (also likely not to apply due to various limits
2207                  * FBC and the like impose on the size of the buffer, which
2208                  * presumably we violated anyway with this unmappable buffer).
2209                  * Anyway, it is presumably better to stumble onwards with
2210                  * something and try to run the system in a "less than optimal"
2211                  * mode that matches the user configuration.
2212                  */
2213                 i915_vma_pin_fence(vma);
2214         }
2215
2216         i915_vma_get(vma);
2217 err:
2218         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2219
2220         intel_runtime_pm_put(dev_priv);
2221         return vma;
2222 }
2223
2224 void intel_unpin_fb_vma(struct i915_vma *vma)
2225 {
2226         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2227
2228         i915_vma_unpin_fence(vma);
2229         i915_gem_object_unpin_from_display_plane(vma);
2230         i915_vma_put(vma);
2231 }
2232
2233 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2234                           unsigned int rotation)
2235 {
2236         if (drm_rotation_90_or_270(rotation))
2237                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2238         else
2239                 return fb->pitches[plane];
2240 }
2241
2242 /*
2243  * Convert the x/y offsets into a linear offset.
2244  * Only valid with 0/180 degree rotation, which is fine since linear
2245  * offset is only used with linear buffers on pre-hsw and tiled buffers
2246  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2247  */
2248 u32 intel_fb_xy_to_linear(int x, int y,
2249                           const struct intel_plane_state *state,
2250                           int plane)
2251 {
2252         const struct drm_framebuffer *fb = state->base.fb;
2253         unsigned int cpp = fb->format->cpp[plane];
2254         unsigned int pitch = fb->pitches[plane];
2255
2256         return y * pitch + x * cpp;
2257 }
2258
2259 /*
2260  * Add the x/y offsets derived from fb->offsets[] to the user
2261  * specified plane src x/y offsets. The resulting x/y offsets
2262  * specify the start of scanout from the beginning of the gtt mapping.
2263  */
2264 void intel_add_fb_offsets(int *x, int *y,
2265                           const struct intel_plane_state *state,
2266                           int plane)
2267
2268 {
2269         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2270         unsigned int rotation = state->base.rotation;
2271
2272         if (drm_rotation_90_or_270(rotation)) {
2273                 *x += intel_fb->rotated[plane].x;
2274                 *y += intel_fb->rotated[plane].y;
2275         } else {
2276                 *x += intel_fb->normal[plane].x;
2277                 *y += intel_fb->normal[plane].y;
2278         }
2279 }
2280
2281 static u32 __intel_adjust_tile_offset(int *x, int *y,
2282                                       unsigned int tile_width,
2283                                       unsigned int tile_height,
2284                                       unsigned int tile_size,
2285                                       unsigned int pitch_tiles,
2286                                       u32 old_offset,
2287                                       u32 new_offset)
2288 {
2289         unsigned int pitch_pixels = pitch_tiles * tile_width;
2290         unsigned int tiles;
2291
2292         WARN_ON(old_offset & (tile_size - 1));
2293         WARN_ON(new_offset & (tile_size - 1));
2294         WARN_ON(new_offset > old_offset);
2295
2296         tiles = (old_offset - new_offset) / tile_size;
2297
2298         *y += tiles / pitch_tiles * tile_height;
2299         *x += tiles % pitch_tiles * tile_width;
2300
2301         /* minimize x in case it got needlessly big */
2302         *y += *x / pitch_pixels * tile_height;
2303         *x %= pitch_pixels;
2304
2305         return new_offset;
2306 }
2307
2308 static u32 _intel_adjust_tile_offset(int *x, int *y,
2309                                      const struct drm_framebuffer *fb, int plane,
2310                                      unsigned int rotation,
2311                                      u32 old_offset, u32 new_offset)
2312 {
2313         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314         unsigned int cpp = fb->format->cpp[plane];
2315         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2316
2317         WARN_ON(new_offset > old_offset);
2318
2319         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2320                 unsigned int tile_size, tile_width, tile_height;
2321                 unsigned int pitch_tiles;
2322
2323                 tile_size = intel_tile_size(dev_priv);
2324                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2325
2326                 if (drm_rotation_90_or_270(rotation)) {
2327                         pitch_tiles = pitch / tile_height;
2328                         swap(tile_width, tile_height);
2329                 } else {
2330                         pitch_tiles = pitch / (tile_width * cpp);
2331                 }
2332
2333                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2334                                            tile_size, pitch_tiles,
2335                                            old_offset, new_offset);
2336         } else {
2337                 old_offset += *y * pitch + *x * cpp;
2338
2339                 *y = (old_offset - new_offset) / pitch;
2340                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2341         }
2342
2343         return new_offset;
2344 }
2345
2346 /*
2347  * Adjust the tile offset by moving the difference into
2348  * the x/y offsets.
2349  */
2350 static u32 intel_adjust_tile_offset(int *x, int *y,
2351                                     const struct intel_plane_state *state, int plane,
2352                                     u32 old_offset, u32 new_offset)
2353 {
2354         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2355                                          state->base.rotation,
2356                                          old_offset, new_offset);
2357 }
2358
2359 /*
2360  * Computes the linear offset to the base tile and adjusts
2361  * x, y. bytes per pixel is assumed to be a power-of-two.
2362  *
2363  * In the 90/270 rotated case, x and y are assumed
2364  * to be already rotated to match the rotated GTT view, and
2365  * pitch is the tile_height aligned framebuffer height.
2366  *
2367  * This function is used when computing the derived information
2368  * under intel_framebuffer, so using any of that information
2369  * here is not allowed. Anything under drm_framebuffer can be
2370  * used. This is why the user has to pass in the pitch since it
2371  * is specified in the rotated orientation.
2372  */
2373 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2374                                       int *x, int *y,
2375                                       const struct drm_framebuffer *fb, int plane,
2376                                       unsigned int pitch,
2377                                       unsigned int rotation,
2378                                       u32 alignment)
2379 {
2380         uint64_t fb_modifier = fb->modifier;
2381         unsigned int cpp = fb->format->cpp[plane];
2382         u32 offset, offset_aligned;
2383
2384         if (alignment)
2385                 alignment--;
2386
2387         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2388                 unsigned int tile_size, tile_width, tile_height;
2389                 unsigned int tile_rows, tiles, pitch_tiles;
2390
2391                 tile_size = intel_tile_size(dev_priv);
2392                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2393
2394                 if (drm_rotation_90_or_270(rotation)) {
2395                         pitch_tiles = pitch / tile_height;
2396                         swap(tile_width, tile_height);
2397                 } else {
2398                         pitch_tiles = pitch / (tile_width * cpp);
2399                 }
2400
2401                 tile_rows = *y / tile_height;
2402                 *y %= tile_height;
2403
2404                 tiles = *x / tile_width;
2405                 *x %= tile_width;
2406
2407                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2408                 offset_aligned = offset & ~alignment;
2409
2410                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2411                                            tile_size, pitch_tiles,
2412                                            offset, offset_aligned);
2413         } else {
2414                 offset = *y * pitch + *x * cpp;
2415                 offset_aligned = offset & ~alignment;
2416
2417                 *y = (offset & alignment) / pitch;
2418                 *x = ((offset & alignment) - *y * pitch) / cpp;
2419         }
2420
2421         return offset_aligned;
2422 }
2423
2424 u32 intel_compute_tile_offset(int *x, int *y,
2425                               const struct intel_plane_state *state,
2426                               int plane)
2427 {
2428         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2429         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2430         const struct drm_framebuffer *fb = state->base.fb;
2431         unsigned int rotation = state->base.rotation;
2432         int pitch = intel_fb_pitch(fb, plane, rotation);
2433         u32 alignment;
2434
2435         if (intel_plane->id == PLANE_CURSOR)
2436                 alignment = intel_cursor_alignment(dev_priv);
2437         else
2438                 alignment = intel_surf_alignment(fb, plane);
2439
2440         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2441                                           rotation, alignment);
2442 }
2443
2444 /* Convert the fb->offset[] into x/y offsets */
2445 static int intel_fb_offset_to_xy(int *x, int *y,
2446                                  const struct drm_framebuffer *fb, int plane)
2447 {
2448         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2449
2450         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2451             fb->offsets[plane] % intel_tile_size(dev_priv))
2452                 return -EINVAL;
2453
2454         *x = 0;
2455         *y = 0;
2456
2457         _intel_adjust_tile_offset(x, y,
2458                                   fb, plane, DRM_MODE_ROTATE_0,
2459                                   fb->offsets[plane], 0);
2460
2461         return 0;
2462 }
2463
2464 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2465 {
2466         switch (fb_modifier) {
2467         case I915_FORMAT_MOD_X_TILED:
2468                 return I915_TILING_X;
2469         case I915_FORMAT_MOD_Y_TILED:
2470         case I915_FORMAT_MOD_Y_TILED_CCS:
2471                 return I915_TILING_Y;
2472         default:
2473                 return I915_TILING_NONE;
2474         }
2475 }
2476
2477 static const struct drm_format_info ccs_formats[] = {
2478         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2479         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482 };
2483
2484 static const struct drm_format_info *
2485 lookup_format_info(const struct drm_format_info formats[],
2486                    int num_formats, u32 format)
2487 {
2488         int i;
2489
2490         for (i = 0; i < num_formats; i++) {
2491                 if (formats[i].format == format)
2492                         return &formats[i];
2493         }
2494
2495         return NULL;
2496 }
2497
2498 static const struct drm_format_info *
2499 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2500 {
2501         switch (cmd->modifier[0]) {
2502         case I915_FORMAT_MOD_Y_TILED_CCS:
2503         case I915_FORMAT_MOD_Yf_TILED_CCS:
2504                 return lookup_format_info(ccs_formats,
2505                                           ARRAY_SIZE(ccs_formats),
2506                                           cmd->pixel_format);
2507         default:
2508                 return NULL;
2509         }
2510 }
2511
2512 static int
2513 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2514                    struct drm_framebuffer *fb)
2515 {
2516         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2517         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2518         u32 gtt_offset_rotated = 0;
2519         unsigned int max_size = 0;
2520         int i, num_planes = fb->format->num_planes;
2521         unsigned int tile_size = intel_tile_size(dev_priv);
2522
2523         for (i = 0; i < num_planes; i++) {
2524                 unsigned int width, height;
2525                 unsigned int cpp, size;
2526                 u32 offset;
2527                 int x, y;
2528                 int ret;
2529
2530                 cpp = fb->format->cpp[i];
2531                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2532                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2533
2534                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2535                 if (ret) {
2536                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2537                                       i, fb->offsets[i]);
2538                         return ret;
2539                 }
2540
2541                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2542                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2543                         int hsub = fb->format->hsub;
2544                         int vsub = fb->format->vsub;
2545                         int tile_width, tile_height;
2546                         int main_x, main_y;
2547                         int ccs_x, ccs_y;
2548
2549                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2550                         tile_width *= hsub;
2551                         tile_height *= vsub;
2552
2553                         ccs_x = (x * hsub) % tile_width;
2554                         ccs_y = (y * vsub) % tile_height;
2555                         main_x = intel_fb->normal[0].x % tile_width;
2556                         main_y = intel_fb->normal[0].y % tile_height;
2557
2558                         /*
2559                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2560                          * x/y offsets must match between CCS and the main surface.
2561                          */
2562                         if (main_x != ccs_x || main_y != ccs_y) {
2563                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2564                                               main_x, main_y,
2565                                               ccs_x, ccs_y,
2566                                               intel_fb->normal[0].x,
2567                                               intel_fb->normal[0].y,
2568                                               x, y);
2569                                 return -EINVAL;
2570                         }
2571                 }
2572
2573                 /*
2574                  * The fence (if used) is aligned to the start of the object
2575                  * so having the framebuffer wrap around across the edge of the
2576                  * fenced region doesn't really work. We have no API to configure
2577                  * the fence start offset within the object (nor could we probably
2578                  * on gen2/3). So it's just easier if we just require that the
2579                  * fb layout agrees with the fence layout. We already check that the
2580                  * fb stride matches the fence stride elsewhere.
2581                  */
2582                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2583                     (x + width) * cpp > fb->pitches[i]) {
2584                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2585                                       i, fb->offsets[i]);
2586                         return -EINVAL;
2587                 }
2588
2589                 /*
2590                  * First pixel of the framebuffer from
2591                  * the start of the normal gtt mapping.
2592                  */
2593                 intel_fb->normal[i].x = x;
2594                 intel_fb->normal[i].y = y;
2595
2596                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2597                                                     fb, i, fb->pitches[i],
2598                                                     DRM_MODE_ROTATE_0, tile_size);
2599                 offset /= tile_size;
2600
2601                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2602                         unsigned int tile_width, tile_height;
2603                         unsigned int pitch_tiles;
2604                         struct drm_rect r;
2605
2606                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2607
2608                         rot_info->plane[i].offset = offset;
2609                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2610                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2611                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2612
2613                         intel_fb->rotated[i].pitch =
2614                                 rot_info->plane[i].height * tile_height;
2615
2616                         /* how many tiles does this plane need */
2617                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2618                         /*
2619                          * If the plane isn't horizontally tile aligned,
2620                          * we need one more tile.
2621                          */
2622                         if (x != 0)
2623                                 size++;
2624
2625                         /* rotate the x/y offsets to match the GTT view */
2626                         r.x1 = x;
2627                         r.y1 = y;
2628                         r.x2 = x + width;
2629                         r.y2 = y + height;
2630                         drm_rect_rotate(&r,
2631                                         rot_info->plane[i].width * tile_width,
2632                                         rot_info->plane[i].height * tile_height,
2633                                         DRM_MODE_ROTATE_270);
2634                         x = r.x1;
2635                         y = r.y1;
2636
2637                         /* rotate the tile dimensions to match the GTT view */
2638                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2639                         swap(tile_width, tile_height);
2640
2641                         /*
2642                          * We only keep the x/y offsets, so push all of the
2643                          * gtt offset into the x/y offsets.
2644                          */
2645                         __intel_adjust_tile_offset(&x, &y,
2646                                                    tile_width, tile_height,
2647                                                    tile_size, pitch_tiles,
2648                                                    gtt_offset_rotated * tile_size, 0);
2649
2650                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2651
2652                         /*
2653                          * First pixel of the framebuffer from
2654                          * the start of the rotated gtt mapping.
2655                          */
2656                         intel_fb->rotated[i].x = x;
2657                         intel_fb->rotated[i].y = y;
2658                 } else {
2659                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2660                                             x * cpp, tile_size);
2661                 }
2662
2663                 /* how many tiles in total needed in the bo */
2664                 max_size = max(max_size, offset + size);
2665         }
2666
2667         if (max_size * tile_size > intel_fb->obj->base.size) {
2668                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2669                               max_size * tile_size, intel_fb->obj->base.size);
2670                 return -EINVAL;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int i9xx_format_to_fourcc(int format)
2677 {
2678         switch (format) {
2679         case DISPPLANE_8BPP:
2680                 return DRM_FORMAT_C8;
2681         case DISPPLANE_BGRX555:
2682                 return DRM_FORMAT_XRGB1555;
2683         case DISPPLANE_BGRX565:
2684                 return DRM_FORMAT_RGB565;
2685         default:
2686         case DISPPLANE_BGRX888:
2687                 return DRM_FORMAT_XRGB8888;
2688         case DISPPLANE_RGBX888:
2689                 return DRM_FORMAT_XBGR8888;
2690         case DISPPLANE_BGRX101010:
2691                 return DRM_FORMAT_XRGB2101010;
2692         case DISPPLANE_RGBX101010:
2693                 return DRM_FORMAT_XBGR2101010;
2694         }
2695 }
2696
2697 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2698 {
2699         switch (format) {
2700         case PLANE_CTL_FORMAT_RGB_565:
2701                 return DRM_FORMAT_RGB565;
2702         default:
2703         case PLANE_CTL_FORMAT_XRGB_8888:
2704                 if (rgb_order) {
2705                         if (alpha)
2706                                 return DRM_FORMAT_ABGR8888;
2707                         else
2708                                 return DRM_FORMAT_XBGR8888;
2709                 } else {
2710                         if (alpha)
2711                                 return DRM_FORMAT_ARGB8888;
2712                         else
2713                                 return DRM_FORMAT_XRGB8888;
2714                 }
2715         case PLANE_CTL_FORMAT_XRGB_2101010:
2716                 if (rgb_order)
2717                         return DRM_FORMAT_XBGR2101010;
2718                 else
2719                         return DRM_FORMAT_XRGB2101010;
2720         }
2721 }
2722
2723 static bool
2724 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2725                               struct intel_initial_plane_config *plane_config)
2726 {
2727         struct drm_device *dev = crtc->base.dev;
2728         struct drm_i915_private *dev_priv = to_i915(dev);
2729         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2730         struct drm_i915_gem_object *obj = NULL;
2731         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2732         struct drm_framebuffer *fb = &plane_config->fb->base;
2733         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2734         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2735                                     PAGE_SIZE);
2736
2737         size_aligned -= base_aligned;
2738
2739         if (plane_config->size == 0)
2740                 return false;
2741
2742         /* If the FB is too big, just don't use it since fbdev is not very
2743          * important and we should probably use that space with FBC or other
2744          * features. */
2745         if (size_aligned * 2 > ggtt->stolen_usable_size)
2746                 return false;
2747
2748         mutex_lock(&dev->struct_mutex);
2749         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2750                                                              base_aligned,
2751                                                              base_aligned,
2752                                                              size_aligned);
2753         mutex_unlock(&dev->struct_mutex);
2754         if (!obj)
2755                 return false;
2756
2757         if (plane_config->tiling == I915_TILING_X)
2758                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2759
2760         mode_cmd.pixel_format = fb->format->format;
2761         mode_cmd.width = fb->width;
2762         mode_cmd.height = fb->height;
2763         mode_cmd.pitches[0] = fb->pitches[0];
2764         mode_cmd.modifier[0] = fb->modifier;
2765         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2766
2767         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2768                 DRM_DEBUG_KMS("intel fb init failed\n");
2769                 goto out_unref_obj;
2770         }
2771
2772
2773         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2774         return true;
2775
2776 out_unref_obj:
2777         i915_gem_object_put(obj);
2778         return false;
2779 }
2780
2781 static void
2782 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2783                         struct intel_plane_state *plane_state,
2784                         bool visible)
2785 {
2786         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2787
2788         plane_state->base.visible = visible;
2789
2790         /* FIXME pre-g4x don't work like this */
2791         if (visible) {
2792                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2793                 crtc_state->active_planes |= BIT(plane->id);
2794         } else {
2795                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2796                 crtc_state->active_planes &= ~BIT(plane->id);
2797         }
2798
2799         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2800                       crtc_state->base.crtc->name,
2801                       crtc_state->active_planes);
2802 }
2803
2804 static void
2805 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2806                              struct intel_initial_plane_config *plane_config)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = to_i915(dev);
2810         struct drm_crtc *c;
2811         struct drm_i915_gem_object *obj;
2812         struct drm_plane *primary = intel_crtc->base.primary;
2813         struct drm_plane_state *plane_state = primary->state;
2814         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2815         struct intel_plane *intel_plane = to_intel_plane(primary);
2816         struct intel_plane_state *intel_state =
2817                 to_intel_plane_state(plane_state);
2818         struct drm_framebuffer *fb;
2819
2820         if (!plane_config->fb)
2821                 return;
2822
2823         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2824                 fb = &plane_config->fb->base;
2825                 goto valid_fb;
2826         }
2827
2828         kfree(plane_config->fb);
2829
2830         /*
2831          * Failed to alloc the obj, check to see if we should share
2832          * an fb with another CRTC instead
2833          */
2834         for_each_crtc(dev, c) {
2835                 struct intel_plane_state *state;
2836
2837                 if (c == &intel_crtc->base)
2838                         continue;
2839
2840                 if (!to_intel_crtc(c)->active)
2841                         continue;
2842
2843                 state = to_intel_plane_state(c->primary->state);
2844                 if (!state->vma)
2845                         continue;
2846
2847                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2848                         fb = c->primary->fb;
2849                         drm_framebuffer_get(fb);
2850                         goto valid_fb;
2851                 }
2852         }
2853
2854         /*
2855          * We've failed to reconstruct the BIOS FB.  Current display state
2856          * indicates that the primary plane is visible, but has a NULL FB,
2857          * which will lead to problems later if we don't fix it up.  The
2858          * simplest solution is to just disable the primary plane now and
2859          * pretend the BIOS never had it enabled.
2860          */
2861         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2862                                 to_intel_plane_state(plane_state),
2863                                 false);
2864         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2865         trace_intel_disable_plane(primary, intel_crtc);
2866         intel_plane->disable_plane(intel_plane, intel_crtc);
2867
2868         return;
2869
2870 valid_fb:
2871         mutex_lock(&dev->struct_mutex);
2872         intel_state->vma =
2873                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2874         mutex_unlock(&dev->struct_mutex);
2875         if (IS_ERR(intel_state->vma)) {
2876                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2877                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2878
2879                 intel_state->vma = NULL;
2880                 drm_framebuffer_put(fb);
2881                 return;
2882         }
2883
2884         plane_state->src_x = 0;
2885         plane_state->src_y = 0;
2886         plane_state->src_w = fb->width << 16;
2887         plane_state->src_h = fb->height << 16;
2888
2889         plane_state->crtc_x = 0;
2890         plane_state->crtc_y = 0;
2891         plane_state->crtc_w = fb->width;
2892         plane_state->crtc_h = fb->height;
2893
2894         intel_state->base.src = drm_plane_state_src(plane_state);
2895         intel_state->base.dst = drm_plane_state_dest(plane_state);
2896
2897         obj = intel_fb_obj(fb);
2898         if (i915_gem_object_is_tiled(obj))
2899                 dev_priv->preserve_bios_swizzle = true;
2900
2901         drm_framebuffer_get(fb);
2902         primary->fb = primary->state->fb = fb;
2903         primary->crtc = primary->state->crtc = &intel_crtc->base;
2904
2905         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2906                                 to_intel_plane_state(plane_state),
2907                                 true);
2908
2909         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2910                   &obj->frontbuffer_bits);
2911 }
2912
2913 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2914                                unsigned int rotation)
2915 {
2916         int cpp = fb->format->cpp[plane];
2917
2918         switch (fb->modifier) {
2919         case DRM_FORMAT_MOD_LINEAR:
2920         case I915_FORMAT_MOD_X_TILED:
2921                 switch (cpp) {
2922                 case 8:
2923                         return 4096;
2924                 case 4:
2925                 case 2:
2926                 case 1:
2927                         return 8192;
2928                 default:
2929                         MISSING_CASE(cpp);
2930                         break;
2931                 }
2932                 break;
2933         case I915_FORMAT_MOD_Y_TILED_CCS:
2934         case I915_FORMAT_MOD_Yf_TILED_CCS:
2935                 /* FIXME AUX plane? */
2936         case I915_FORMAT_MOD_Y_TILED:
2937         case I915_FORMAT_MOD_Yf_TILED:
2938                 switch (cpp) {
2939                 case 8:
2940                         return 2048;
2941                 case 4:
2942                         return 4096;
2943                 case 2:
2944                 case 1:
2945                         return 8192;
2946                 default:
2947                         MISSING_CASE(cpp);
2948                         break;
2949                 }
2950                 break;
2951         default:
2952                 MISSING_CASE(fb->modifier);
2953         }
2954
2955         return 2048;
2956 }
2957
2958 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2959                                            int main_x, int main_y, u32 main_offset)
2960 {
2961         const struct drm_framebuffer *fb = plane_state->base.fb;
2962         int hsub = fb->format->hsub;
2963         int vsub = fb->format->vsub;
2964         int aux_x = plane_state->aux.x;
2965         int aux_y = plane_state->aux.y;
2966         u32 aux_offset = plane_state->aux.offset;
2967         u32 alignment = intel_surf_alignment(fb, 1);
2968
2969         while (aux_offset >= main_offset && aux_y <= main_y) {
2970                 int x, y;
2971
2972                 if (aux_x == main_x && aux_y == main_y)
2973                         break;
2974
2975                 if (aux_offset == 0)
2976                         break;
2977
2978                 x = aux_x / hsub;
2979                 y = aux_y / vsub;
2980                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2981                                                       aux_offset, aux_offset - alignment);
2982                 aux_x = x * hsub + aux_x % hsub;
2983                 aux_y = y * vsub + aux_y % vsub;
2984         }
2985
2986         if (aux_x != main_x || aux_y != main_y)
2987                 return false;
2988
2989         plane_state->aux.offset = aux_offset;
2990         plane_state->aux.x = aux_x;
2991         plane_state->aux.y = aux_y;
2992
2993         return true;
2994 }
2995
2996 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2997 {
2998         const struct drm_framebuffer *fb = plane_state->base.fb;
2999         unsigned int rotation = plane_state->base.rotation;
3000         int x = plane_state->base.src.x1 >> 16;
3001         int y = plane_state->base.src.y1 >> 16;
3002         int w = drm_rect_width(&plane_state->base.src) >> 16;
3003         int h = drm_rect_height(&plane_state->base.src) >> 16;
3004         int max_width = skl_max_plane_width(fb, 0, rotation);
3005         int max_height = 4096;
3006         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3007
3008         if (w > max_width || h > max_height) {
3009                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3010                               w, h, max_width, max_height);
3011                 return -EINVAL;
3012         }
3013
3014         intel_add_fb_offsets(&x, &y, plane_state, 0);
3015         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3016         alignment = intel_surf_alignment(fb, 0);
3017
3018         /*
3019          * AUX surface offset is specified as the distance from the
3020          * main surface offset, and it must be non-negative. Make
3021          * sure that is what we will get.
3022          */
3023         if (offset > aux_offset)
3024                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3025                                                   offset, aux_offset & ~(alignment - 1));
3026
3027         /*
3028          * When using an X-tiled surface, the plane blows up
3029          * if the x offset + width exceed the stride.
3030          *
3031          * TODO: linear and Y-tiled seem fine, Yf untested,
3032          */
3033         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3034                 int cpp = fb->format->cpp[0];
3035
3036                 while ((x + w) * cpp > fb->pitches[0]) {
3037                         if (offset == 0) {
3038                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3039                                 return -EINVAL;
3040                         }
3041
3042                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3043                                                           offset, offset - alignment);
3044                 }
3045         }
3046
3047         /*
3048          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3049          * they match with the main surface x/y offsets.
3050          */
3051         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3052             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3053                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3054                         if (offset == 0)
3055                                 break;
3056
3057                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3058                                                           offset, offset - alignment);
3059                 }
3060
3061                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3062                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3063                         return -EINVAL;
3064                 }
3065         }
3066
3067         plane_state->main.offset = offset;
3068         plane_state->main.x = x;
3069         plane_state->main.y = y;
3070
3071         return 0;
3072 }
3073
3074 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3075 {
3076         const struct drm_framebuffer *fb = plane_state->base.fb;
3077         unsigned int rotation = plane_state->base.rotation;
3078         int max_width = skl_max_plane_width(fb, 1, rotation);
3079         int max_height = 4096;
3080         int x = plane_state->base.src.x1 >> 17;
3081         int y = plane_state->base.src.y1 >> 17;
3082         int w = drm_rect_width(&plane_state->base.src) >> 17;
3083         int h = drm_rect_height(&plane_state->base.src) >> 17;
3084         u32 offset;
3085
3086         intel_add_fb_offsets(&x, &y, plane_state, 1);
3087         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3088
3089         /* FIXME not quite sure how/if these apply to the chroma plane */
3090         if (w > max_width || h > max_height) {
3091                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3092                               w, h, max_width, max_height);
3093                 return -EINVAL;
3094         }
3095
3096         plane_state->aux.offset = offset;
3097         plane_state->aux.x = x;
3098         plane_state->aux.y = y;
3099
3100         return 0;
3101 }
3102
3103 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3104 {
3105         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3106         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3107         const struct drm_framebuffer *fb = plane_state->base.fb;
3108         int src_x = plane_state->base.src.x1 >> 16;
3109         int src_y = plane_state->base.src.y1 >> 16;
3110         int hsub = fb->format->hsub;
3111         int vsub = fb->format->vsub;
3112         int x = src_x / hsub;
3113         int y = src_y / vsub;
3114         u32 offset;
3115
3116         switch (plane->id) {
3117         case PLANE_PRIMARY:
3118         case PLANE_SPRITE0:
3119                 break;
3120         default:
3121                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3122                 return -EINVAL;
3123         }
3124
3125         if (crtc->pipe == PIPE_C) {
3126                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3127                 return -EINVAL;
3128         }
3129
3130         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3131                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3132                               plane_state->base.rotation);
3133                 return -EINVAL;
3134         }
3135
3136         intel_add_fb_offsets(&x, &y, plane_state, 1);
3137         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3138
3139         plane_state->aux.offset = offset;
3140         plane_state->aux.x = x * hsub + src_x % hsub;
3141         plane_state->aux.y = y * vsub + src_y % vsub;
3142
3143         return 0;
3144 }
3145
3146 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3147 {
3148         const struct drm_framebuffer *fb = plane_state->base.fb;
3149         unsigned int rotation = plane_state->base.rotation;
3150         int ret;
3151
3152         if (!plane_state->base.visible)
3153                 return 0;
3154
3155         /* Rotate src coordinates to match rotated GTT view */
3156         if (drm_rotation_90_or_270(rotation))
3157                 drm_rect_rotate(&plane_state->base.src,
3158                                 fb->width << 16, fb->height << 16,
3159                                 DRM_MODE_ROTATE_270);
3160
3161         /*
3162          * Handle the AUX surface first since
3163          * the main surface setup depends on it.
3164          */
3165         if (fb->format->format == DRM_FORMAT_NV12) {
3166                 ret = skl_check_nv12_aux_surface(plane_state);
3167                 if (ret)
3168                         return ret;
3169         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3170                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3171                 ret = skl_check_ccs_aux_surface(plane_state);
3172                 if (ret)
3173                         return ret;
3174         } else {
3175                 plane_state->aux.offset = ~0xfff;
3176                 plane_state->aux.x = 0;
3177                 plane_state->aux.y = 0;
3178         }
3179
3180         ret = skl_check_main_surface(plane_state);
3181         if (ret)
3182                 return ret;
3183
3184         return 0;
3185 }
3186
3187 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3188                           const struct intel_plane_state *plane_state)
3189 {
3190         struct drm_i915_private *dev_priv =
3191                 to_i915(plane_state->base.plane->dev);
3192         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3193         const struct drm_framebuffer *fb = plane_state->base.fb;
3194         unsigned int rotation = plane_state->base.rotation;
3195         u32 dspcntr;
3196
3197         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3198
3199         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3200             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3201                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3202
3203         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3204                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3205
3206         if (INTEL_GEN(dev_priv) < 4)
3207                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3208
3209         switch (fb->format->format) {
3210         case DRM_FORMAT_C8:
3211                 dspcntr |= DISPPLANE_8BPP;
3212                 break;
3213         case DRM_FORMAT_XRGB1555:
3214                 dspcntr |= DISPPLANE_BGRX555;
3215                 break;
3216         case DRM_FORMAT_RGB565:
3217                 dspcntr |= DISPPLANE_BGRX565;
3218                 break;
3219         case DRM_FORMAT_XRGB8888:
3220                 dspcntr |= DISPPLANE_BGRX888;
3221                 break;
3222         case DRM_FORMAT_XBGR8888:
3223                 dspcntr |= DISPPLANE_RGBX888;
3224                 break;
3225         case DRM_FORMAT_XRGB2101010:
3226                 dspcntr |= DISPPLANE_BGRX101010;
3227                 break;
3228         case DRM_FORMAT_XBGR2101010:
3229                 dspcntr |= DISPPLANE_RGBX101010;
3230                 break;
3231         default:
3232                 MISSING_CASE(fb->format->format);
3233                 return 0;
3234         }
3235
3236         if (INTEL_GEN(dev_priv) >= 4 &&
3237             fb->modifier == I915_FORMAT_MOD_X_TILED)
3238                 dspcntr |= DISPPLANE_TILED;
3239
3240         if (rotation & DRM_MODE_ROTATE_180)
3241                 dspcntr |= DISPPLANE_ROTATE_180;
3242
3243         if (rotation & DRM_MODE_REFLECT_X)
3244                 dspcntr |= DISPPLANE_MIRROR;
3245
3246         return dspcntr;
3247 }
3248
3249 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3250 {
3251         struct drm_i915_private *dev_priv =
3252                 to_i915(plane_state->base.plane->dev);
3253         int src_x = plane_state->base.src.x1 >> 16;
3254         int src_y = plane_state->base.src.y1 >> 16;
3255         u32 offset;
3256
3257         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3258
3259         if (INTEL_GEN(dev_priv) >= 4)
3260                 offset = intel_compute_tile_offset(&src_x, &src_y,
3261                                                    plane_state, 0);
3262         else
3263                 offset = 0;
3264
3265         /* HSW/BDW do this automagically in hardware */
3266         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3267                 unsigned int rotation = plane_state->base.rotation;
3268                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3269                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3270
3271                 if (rotation & DRM_MODE_ROTATE_180) {
3272                         src_x += src_w - 1;
3273                         src_y += src_h - 1;
3274                 } else if (rotation & DRM_MODE_REFLECT_X) {
3275                         src_x += src_w - 1;
3276                 }
3277         }
3278
3279         plane_state->main.offset = offset;
3280         plane_state->main.x = src_x;
3281         plane_state->main.y = src_y;
3282
3283         return 0;
3284 }
3285
3286 static void i9xx_update_primary_plane(struct intel_plane *primary,
3287                                       const struct intel_crtc_state *crtc_state,
3288                                       const struct intel_plane_state *plane_state)
3289 {
3290         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3291         const struct drm_framebuffer *fb = plane_state->base.fb;
3292         enum plane plane = primary->plane;
3293         u32 linear_offset;
3294         u32 dspcntr = plane_state->ctl;
3295         i915_reg_t reg = DSPCNTR(plane);
3296         int x = plane_state->main.x;
3297         int y = plane_state->main.y;
3298         unsigned long irqflags;
3299         u32 dspaddr_offset;
3300
3301         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3302
3303         if (INTEL_GEN(dev_priv) >= 4)
3304                 dspaddr_offset = plane_state->main.offset;
3305         else
3306                 dspaddr_offset = linear_offset;
3307
3308         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3309
3310         if (INTEL_GEN(dev_priv) < 4) {
3311                 /* pipesrc and dspsize control the size that is scaled from,
3312                  * which should always be the user's requested size.
3313                  */
3314                 I915_WRITE_FW(DSPSIZE(plane),
3315                               ((crtc_state->pipe_src_h - 1) << 16) |
3316                               (crtc_state->pipe_src_w - 1));
3317                 I915_WRITE_FW(DSPPOS(plane), 0);
3318         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3319                 I915_WRITE_FW(PRIMSIZE(plane),
3320                               ((crtc_state->pipe_src_h - 1) << 16) |
3321                               (crtc_state->pipe_src_w - 1));
3322                 I915_WRITE_FW(PRIMPOS(plane), 0);
3323                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3324         }
3325
3326         I915_WRITE_FW(reg, dspcntr);
3327
3328         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3329         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3330                 I915_WRITE_FW(DSPSURF(plane),
3331                               intel_plane_ggtt_offset(plane_state) +
3332                               dspaddr_offset);
3333                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3334         } else if (INTEL_GEN(dev_priv) >= 4) {
3335                 I915_WRITE_FW(DSPSURF(plane),
3336                               intel_plane_ggtt_offset(plane_state) +
3337                               dspaddr_offset);
3338                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3339                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3340         } else {
3341                 I915_WRITE_FW(DSPADDR(plane),
3342                               intel_plane_ggtt_offset(plane_state) +
3343                               dspaddr_offset);
3344         }
3345         POSTING_READ_FW(reg);
3346
3347         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3348 }
3349
3350 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3351                                        struct intel_crtc *crtc)
3352 {
3353         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3354         enum plane plane = primary->plane;
3355         unsigned long irqflags;
3356
3357         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3358
3359         I915_WRITE_FW(DSPCNTR(plane), 0);
3360         if (INTEL_INFO(dev_priv)->gen >= 4)
3361                 I915_WRITE_FW(DSPSURF(plane), 0);
3362         else
3363                 I915_WRITE_FW(DSPADDR(plane), 0);
3364         POSTING_READ_FW(DSPCNTR(plane));
3365
3366         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3367 }
3368
3369 static u32
3370 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3371 {
3372         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3373                 return 64;
3374         else
3375                 return intel_tile_width_bytes(fb, plane);
3376 }
3377
3378 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3379 {
3380         struct drm_device *dev = intel_crtc->base.dev;
3381         struct drm_i915_private *dev_priv = to_i915(dev);
3382
3383         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3384         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3385         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3386 }
3387
3388 /*
3389  * This function detaches (aka. unbinds) unused scalers in hardware
3390  */
3391 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3392 {
3393         struct intel_crtc_scaler_state *scaler_state;
3394         int i;
3395
3396         scaler_state = &intel_crtc->config->scaler_state;
3397
3398         /* loop through and disable scalers that aren't in use */
3399         for (i = 0; i < intel_crtc->num_scalers; i++) {
3400                 if (!scaler_state->scalers[i].in_use)
3401                         skl_detach_scaler(intel_crtc, i);
3402         }
3403 }
3404
3405 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3406                      unsigned int rotation)
3407 {
3408         u32 stride;
3409
3410         if (plane >= fb->format->num_planes)
3411                 return 0;
3412
3413         stride = intel_fb_pitch(fb, plane, rotation);
3414
3415         /*
3416          * The stride is either expressed as a multiple of 64 bytes chunks for
3417          * linear buffers or in number of tiles for tiled buffers.
3418          */
3419         if (drm_rotation_90_or_270(rotation))
3420                 stride /= intel_tile_height(fb, plane);
3421         else
3422                 stride /= intel_fb_stride_alignment(fb, plane);
3423
3424         return stride;
3425 }
3426
3427 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3428 {
3429         switch (pixel_format) {
3430         case DRM_FORMAT_C8:
3431                 return PLANE_CTL_FORMAT_INDEXED;
3432         case DRM_FORMAT_RGB565:
3433                 return PLANE_CTL_FORMAT_RGB_565;
3434         case DRM_FORMAT_XBGR8888:
3435                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3436         case DRM_FORMAT_XRGB8888:
3437                 return PLANE_CTL_FORMAT_XRGB_8888;
3438         /*
3439          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3440          * to be already pre-multiplied. We need to add a knob (or a different
3441          * DRM_FORMAT) for user-space to configure that.
3442          */
3443         case DRM_FORMAT_ABGR8888:
3444                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3445                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3446         case DRM_FORMAT_ARGB8888:
3447                 return PLANE_CTL_FORMAT_XRGB_8888 |
3448                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3449         case DRM_FORMAT_XRGB2101010:
3450                 return PLANE_CTL_FORMAT_XRGB_2101010;
3451         case DRM_FORMAT_XBGR2101010:
3452                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3453         case DRM_FORMAT_YUYV:
3454                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3455         case DRM_FORMAT_YVYU:
3456                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3457         case DRM_FORMAT_UYVY:
3458                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3459         case DRM_FORMAT_VYUY:
3460                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3461         default:
3462                 MISSING_CASE(pixel_format);
3463         }
3464
3465         return 0;
3466 }
3467
3468 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3469 {
3470         switch (fb_modifier) {
3471         case DRM_FORMAT_MOD_LINEAR:
3472                 break;
3473         case I915_FORMAT_MOD_X_TILED:
3474                 return PLANE_CTL_TILED_X;
3475         case I915_FORMAT_MOD_Y_TILED:
3476                 return PLANE_CTL_TILED_Y;
3477         case I915_FORMAT_MOD_Y_TILED_CCS:
3478                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3479         case I915_FORMAT_MOD_Yf_TILED:
3480                 return PLANE_CTL_TILED_YF;
3481         case I915_FORMAT_MOD_Yf_TILED_CCS:
3482                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3483         default:
3484                 MISSING_CASE(fb_modifier);
3485         }
3486
3487         return 0;
3488 }
3489
3490 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3491 {
3492         switch (rotation) {
3493         case DRM_MODE_ROTATE_0:
3494                 break;
3495         /*
3496          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3497          * while i915 HW rotation is clockwise, thats why this swapping.
3498          */
3499         case DRM_MODE_ROTATE_90:
3500                 return PLANE_CTL_ROTATE_270;
3501         case DRM_MODE_ROTATE_180:
3502                 return PLANE_CTL_ROTATE_180;
3503         case DRM_MODE_ROTATE_270:
3504                 return PLANE_CTL_ROTATE_90;
3505         default:
3506                 MISSING_CASE(rotation);
3507         }
3508
3509         return 0;
3510 }
3511
3512 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3513                   const struct intel_plane_state *plane_state)
3514 {
3515         struct drm_i915_private *dev_priv =
3516                 to_i915(plane_state->base.plane->dev);
3517         const struct drm_framebuffer *fb = plane_state->base.fb;
3518         unsigned int rotation = plane_state->base.rotation;
3519         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3520         u32 plane_ctl;
3521
3522         plane_ctl = PLANE_CTL_ENABLE;
3523
3524         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3525                 plane_ctl |=
3526                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3527                         PLANE_CTL_PIPE_CSC_ENABLE |
3528                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3529         }
3530
3531         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3532         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3533         plane_ctl |= skl_plane_ctl_rotation(rotation);
3534
3535         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3536                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3537         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3538                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3539
3540         return plane_ctl;
3541 }
3542
3543 static int
3544 __intel_display_resume(struct drm_device *dev,
3545                        struct drm_atomic_state *state,
3546                        struct drm_modeset_acquire_ctx *ctx)
3547 {
3548         struct drm_crtc_state *crtc_state;
3549         struct drm_crtc *crtc;
3550         int i, ret;
3551
3552         intel_modeset_setup_hw_state(dev, ctx);
3553         i915_redisable_vga(to_i915(dev));
3554
3555         if (!state)
3556                 return 0;
3557
3558         /*
3559          * We've duplicated the state, pointers to the old state are invalid.
3560          *
3561          * Don't attempt to use the old state until we commit the duplicated state.
3562          */
3563         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3564                 /*
3565                  * Force recalculation even if we restore
3566                  * current state. With fast modeset this may not result
3567                  * in a modeset when the state is compatible.
3568                  */
3569                 crtc_state->mode_changed = true;
3570         }
3571
3572         /* ignore any reset values/BIOS leftovers in the WM registers */
3573         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3574                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3575
3576         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3577
3578         WARN_ON(ret == -EDEADLK);
3579         return ret;
3580 }
3581
3582 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3583 {
3584         return intel_has_gpu_reset(dev_priv) &&
3585                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3586 }
3587
3588 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3589 {
3590         struct drm_device *dev = &dev_priv->drm;
3591         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592         struct drm_atomic_state *state;
3593         int ret;
3594
3595
3596         /* reset doesn't touch the display */
3597         if (!i915_modparams.force_reset_modeset_test &&
3598             !gpu_reset_clobbers_display(dev_priv))
3599                 return;
3600
3601         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3602         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3603         wake_up_all(&dev_priv->gpu_error.wait_queue);
3604
3605         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3606                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3607                 i915_gem_set_wedged(dev_priv);
3608         }
3609
3610         /*
3611          * Need mode_config.mutex so that we don't
3612          * trample ongoing ->detect() and whatnot.
3613          */
3614         mutex_lock(&dev->mode_config.mutex);
3615         drm_modeset_acquire_init(ctx, 0);
3616         while (1) {
3617                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3618                 if (ret != -EDEADLK)
3619                         break;
3620
3621                 drm_modeset_backoff(ctx);
3622         }
3623         /*
3624          * Disabling the crtcs gracefully seems nicer. Also the
3625          * g33 docs say we should at least disable all the planes.
3626          */
3627         state = drm_atomic_helper_duplicate_state(dev, ctx);
3628         if (IS_ERR(state)) {
3629                 ret = PTR_ERR(state);
3630                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3631                 return;
3632         }
3633
3634         ret = drm_atomic_helper_disable_all(dev, ctx);
3635         if (ret) {
3636                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3637                 drm_atomic_state_put(state);
3638                 return;
3639         }
3640
3641         dev_priv->modeset_restore_state = state;
3642         state->acquire_ctx = ctx;
3643 }
3644
3645 void intel_finish_reset(struct drm_i915_private *dev_priv)
3646 {
3647         struct drm_device *dev = &dev_priv->drm;
3648         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3649         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3650         int ret;
3651
3652         /* reset doesn't touch the display */
3653         if (!i915_modparams.force_reset_modeset_test &&
3654             !gpu_reset_clobbers_display(dev_priv))
3655                 return;
3656
3657         if (!state)
3658                 goto unlock;
3659
3660         dev_priv->modeset_restore_state = NULL;
3661
3662         /* reset doesn't touch the display */
3663         if (!gpu_reset_clobbers_display(dev_priv)) {
3664                 /* for testing only restore the display */
3665                 ret = __intel_display_resume(dev, state, ctx);
3666                 if (ret)
3667                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3668         } else {
3669                 /*
3670                  * The display has been reset as well,
3671                  * so need a full re-initialization.
3672                  */
3673                 intel_runtime_pm_disable_interrupts(dev_priv);
3674                 intel_runtime_pm_enable_interrupts(dev_priv);
3675
3676                 intel_pps_unlock_regs_wa(dev_priv);
3677                 intel_modeset_init_hw(dev);
3678                 intel_init_clock_gating(dev_priv);
3679
3680                 spin_lock_irq(&dev_priv->irq_lock);
3681                 if (dev_priv->display.hpd_irq_setup)
3682                         dev_priv->display.hpd_irq_setup(dev_priv);
3683                 spin_unlock_irq(&dev_priv->irq_lock);
3684
3685                 ret = __intel_display_resume(dev, state, ctx);
3686                 if (ret)
3687                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3688
3689                 intel_hpd_init(dev_priv);
3690         }
3691
3692         drm_atomic_state_put(state);
3693 unlock:
3694         drm_modeset_drop_locks(ctx);
3695         drm_modeset_acquire_fini(ctx);
3696         mutex_unlock(&dev->mode_config.mutex);
3697
3698         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3699 }
3700
3701 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3702                                      const struct intel_crtc_state *new_crtc_state)
3703 {
3704         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3705         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3706
3707         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3708         crtc->base.mode = new_crtc_state->base.mode;
3709
3710         /*
3711          * Update pipe size and adjust fitter if needed: the reason for this is
3712          * that in compute_mode_changes we check the native mode (not the pfit
3713          * mode) to see if we can flip rather than do a full mode set. In the
3714          * fastboot case, we'll flip, but if we don't update the pipesrc and
3715          * pfit state, we'll end up with a big fb scanned out into the wrong
3716          * sized surface.
3717          */
3718
3719         I915_WRITE(PIPESRC(crtc->pipe),
3720                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3721                    (new_crtc_state->pipe_src_h - 1));
3722
3723         /* on skylake this is done by detaching scalers */
3724         if (INTEL_GEN(dev_priv) >= 9) {
3725                 skl_detach_scalers(crtc);
3726
3727                 if (new_crtc_state->pch_pfit.enabled)
3728                         skylake_pfit_enable(crtc);
3729         } else if (HAS_PCH_SPLIT(dev_priv)) {
3730                 if (new_crtc_state->pch_pfit.enabled)
3731                         ironlake_pfit_enable(crtc);
3732                 else if (old_crtc_state->pch_pfit.enabled)
3733                         ironlake_pfit_disable(crtc, true);
3734         }
3735 }
3736
3737 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->base.dev;
3740         struct drm_i915_private *dev_priv = to_i915(dev);
3741         int pipe = crtc->pipe;
3742         i915_reg_t reg;
3743         u32 temp;
3744
3745         /* enable normal train */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         if (IS_IVYBRIDGE(dev_priv)) {
3749                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3750                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3751         } else {
3752                 temp &= ~FDI_LINK_TRAIN_NONE;
3753                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3754         }
3755         I915_WRITE(reg, temp);
3756
3757         reg = FDI_RX_CTL(pipe);
3758         temp = I915_READ(reg);
3759         if (HAS_PCH_CPT(dev_priv)) {
3760                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3761                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3762         } else {
3763                 temp &= ~FDI_LINK_TRAIN_NONE;
3764                 temp |= FDI_LINK_TRAIN_NONE;
3765         }
3766         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3767
3768         /* wait one idle pattern time */
3769         POSTING_READ(reg);
3770         udelay(1000);
3771
3772         /* IVB wants error correction enabled */
3773         if (IS_IVYBRIDGE(dev_priv))
3774                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3775                            FDI_FE_ERRC_ENABLE);
3776 }
3777
3778 /* The FDI link training functions for ILK/Ibexpeak. */
3779 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3780                                     const struct intel_crtc_state *crtc_state)
3781 {
3782         struct drm_device *dev = crtc->base.dev;
3783         struct drm_i915_private *dev_priv = to_i915(dev);
3784         int pipe = crtc->pipe;
3785         i915_reg_t reg;
3786         u32 temp, tries;
3787
3788         /* FDI needs bits from pipe first */
3789         assert_pipe_enabled(dev_priv, pipe);
3790
3791         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3792            for train result */
3793         reg = FDI_RX_IMR(pipe);
3794         temp = I915_READ(reg);
3795         temp &= ~FDI_RX_SYMBOL_LOCK;
3796         temp &= ~FDI_RX_BIT_LOCK;
3797         I915_WRITE(reg, temp);
3798         I915_READ(reg);
3799         udelay(150);
3800
3801         /* enable CPU FDI TX and PCH FDI RX */
3802         reg = FDI_TX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3805         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3806         temp &= ~FDI_LINK_TRAIN_NONE;
3807         temp |= FDI_LINK_TRAIN_PATTERN_1;
3808         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3809
3810         reg = FDI_RX_CTL(pipe);
3811         temp = I915_READ(reg);
3812         temp &= ~FDI_LINK_TRAIN_NONE;
3813         temp |= FDI_LINK_TRAIN_PATTERN_1;
3814         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3815
3816         POSTING_READ(reg);
3817         udelay(150);
3818
3819         /* Ironlake workaround, enable clock pointer after FDI enable*/
3820         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3821         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3822                    FDI_RX_PHASE_SYNC_POINTER_EN);
3823
3824         reg = FDI_RX_IIR(pipe);
3825         for (tries = 0; tries < 5; tries++) {
3826                 temp = I915_READ(reg);
3827                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3828
3829                 if ((temp & FDI_RX_BIT_LOCK)) {
3830                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3831                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3832                         break;
3833                 }
3834         }
3835         if (tries == 5)
3836                 DRM_ERROR("FDI train 1 fail!\n");
3837
3838         /* Train 2 */
3839         reg = FDI_TX_CTL(pipe);
3840         temp = I915_READ(reg);
3841         temp &= ~FDI_LINK_TRAIN_NONE;
3842         temp |= FDI_LINK_TRAIN_PATTERN_2;
3843         I915_WRITE(reg, temp);
3844
3845         reg = FDI_RX_CTL(pipe);
3846         temp = I915_READ(reg);
3847         temp &= ~FDI_LINK_TRAIN_NONE;
3848         temp |= FDI_LINK_TRAIN_PATTERN_2;
3849         I915_WRITE(reg, temp);
3850
3851         POSTING_READ(reg);
3852         udelay(150);
3853
3854         reg = FDI_RX_IIR(pipe);
3855         for (tries = 0; tries < 5; tries++) {
3856                 temp = I915_READ(reg);
3857                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3858
3859                 if (temp & FDI_RX_SYMBOL_LOCK) {
3860                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3861                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3862                         break;
3863                 }
3864         }
3865         if (tries == 5)
3866                 DRM_ERROR("FDI train 2 fail!\n");
3867
3868         DRM_DEBUG_KMS("FDI train done\n");
3869
3870 }
3871
3872 static const int snb_b_fdi_train_param[] = {
3873         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3874         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3875         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3876         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3877 };
3878
3879 /* The FDI link training functions for SNB/Cougarpoint. */
3880 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3881                                 const struct intel_crtc_state *crtc_state)
3882 {
3883         struct drm_device *dev = crtc->base.dev;
3884         struct drm_i915_private *dev_priv = to_i915(dev);
3885         int pipe = crtc->pipe;
3886         i915_reg_t reg;
3887         u32 temp, i, retry;
3888
3889         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3890            for train result */
3891         reg = FDI_RX_IMR(pipe);
3892         temp = I915_READ(reg);
3893         temp &= ~FDI_RX_SYMBOL_LOCK;
3894         temp &= ~FDI_RX_BIT_LOCK;
3895         I915_WRITE(reg, temp);
3896
3897         POSTING_READ(reg);
3898         udelay(150);
3899
3900         /* enable CPU FDI TX and PCH FDI RX */
3901         reg = FDI_TX_CTL(pipe);
3902         temp = I915_READ(reg);
3903         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3904         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3905         temp &= ~FDI_LINK_TRAIN_NONE;
3906         temp |= FDI_LINK_TRAIN_PATTERN_1;
3907         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908         /* SNB-B */
3909         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3910         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3911
3912         I915_WRITE(FDI_RX_MISC(pipe),
3913                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3914
3915         reg = FDI_RX_CTL(pipe);
3916         temp = I915_READ(reg);
3917         if (HAS_PCH_CPT(dev_priv)) {
3918                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3919                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3920         } else {
3921                 temp &= ~FDI_LINK_TRAIN_NONE;
3922                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3923         }
3924         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3925
3926         POSTING_READ(reg);
3927         udelay(150);
3928
3929         for (i = 0; i < 4; i++) {
3930                 reg = FDI_TX_CTL(pipe);
3931                 temp = I915_READ(reg);
3932                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3933                 temp |= snb_b_fdi_train_param[i];
3934                 I915_WRITE(reg, temp);
3935
3936                 POSTING_READ(reg);
3937                 udelay(500);
3938
3939                 for (retry = 0; retry < 5; retry++) {
3940                         reg = FDI_RX_IIR(pipe);
3941                         temp = I915_READ(reg);
3942                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3943                         if (temp & FDI_RX_BIT_LOCK) {
3944                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3945                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3946                                 break;
3947                         }
3948                         udelay(50);
3949                 }
3950                 if (retry < 5)
3951                         break;
3952         }
3953         if (i == 4)
3954                 DRM_ERROR("FDI train 1 fail!\n");
3955
3956         /* Train 2 */
3957         reg = FDI_TX_CTL(pipe);
3958         temp = I915_READ(reg);
3959         temp &= ~FDI_LINK_TRAIN_NONE;
3960         temp |= FDI_LINK_TRAIN_PATTERN_2;
3961         if (IS_GEN6(dev_priv)) {
3962                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3963                 /* SNB-B */
3964                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3965         }
3966         I915_WRITE(reg, temp);
3967
3968         reg = FDI_RX_CTL(pipe);
3969         temp = I915_READ(reg);
3970         if (HAS_PCH_CPT(dev_priv)) {
3971                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3972                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3973         } else {
3974                 temp &= ~FDI_LINK_TRAIN_NONE;
3975                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3976         }
3977         I915_WRITE(reg, temp);
3978
3979         POSTING_READ(reg);
3980         udelay(150);
3981
3982         for (i = 0; i < 4; i++) {
3983                 reg = FDI_TX_CTL(pipe);
3984                 temp = I915_READ(reg);
3985                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3986                 temp |= snb_b_fdi_train_param[i];
3987                 I915_WRITE(reg, temp);
3988
3989                 POSTING_READ(reg);
3990                 udelay(500);
3991
3992                 for (retry = 0; retry < 5; retry++) {
3993                         reg = FDI_RX_IIR(pipe);
3994                         temp = I915_READ(reg);
3995                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3996                         if (temp & FDI_RX_SYMBOL_LOCK) {
3997                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3998                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3999                                 break;
4000                         }
4001                         udelay(50);
4002                 }
4003                 if (retry < 5)
4004                         break;
4005         }
4006         if (i == 4)
4007                 DRM_ERROR("FDI train 2 fail!\n");
4008
4009         DRM_DEBUG_KMS("FDI train done.\n");
4010 }
4011
4012 /* Manual link training for Ivy Bridge A0 parts */
4013 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4014                                       const struct intel_crtc_state *crtc_state)
4015 {
4016         struct drm_device *dev = crtc->base.dev;
4017         struct drm_i915_private *dev_priv = to_i915(dev);
4018         int pipe = crtc->pipe;
4019         i915_reg_t reg;
4020         u32 temp, i, j;
4021
4022         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4023            for train result */
4024         reg = FDI_RX_IMR(pipe);
4025         temp = I915_READ(reg);
4026         temp &= ~FDI_RX_SYMBOL_LOCK;
4027         temp &= ~FDI_RX_BIT_LOCK;
4028         I915_WRITE(reg, temp);
4029
4030         POSTING_READ(reg);
4031         udelay(150);
4032
4033         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4034                       I915_READ(FDI_RX_IIR(pipe)));
4035
4036         /* Try each vswing and preemphasis setting twice before moving on */
4037         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4038                 /* disable first in case we need to retry */
4039                 reg = FDI_TX_CTL(pipe);
4040                 temp = I915_READ(reg);
4041                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4042                 temp &= ~FDI_TX_ENABLE;
4043                 I915_WRITE(reg, temp);
4044
4045                 reg = FDI_RX_CTL(pipe);
4046                 temp = I915_READ(reg);
4047                 temp &= ~FDI_LINK_TRAIN_AUTO;
4048                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4049                 temp &= ~FDI_RX_ENABLE;
4050                 I915_WRITE(reg, temp);
4051
4052                 /* enable CPU FDI TX and PCH FDI RX */
4053                 reg = FDI_TX_CTL(pipe);
4054                 temp = I915_READ(reg);
4055                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4056                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4057                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4058                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4059                 temp |= snb_b_fdi_train_param[j/2];
4060                 temp |= FDI_COMPOSITE_SYNC;
4061                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4062
4063                 I915_WRITE(FDI_RX_MISC(pipe),
4064                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4065
4066                 reg = FDI_RX_CTL(pipe);
4067                 temp = I915_READ(reg);
4068                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4069                 temp |= FDI_COMPOSITE_SYNC;
4070                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4071
4072                 POSTING_READ(reg);
4073                 udelay(1); /* should be 0.5us */
4074
4075                 for (i = 0; i < 4; i++) {
4076                         reg = FDI_RX_IIR(pipe);
4077                         temp = I915_READ(reg);
4078                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4079
4080                         if (temp & FDI_RX_BIT_LOCK ||
4081                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4082                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4083                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4084                                               i);
4085                                 break;
4086                         }
4087                         udelay(1); /* should be 0.5us */
4088                 }
4089                 if (i == 4) {
4090                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4091                         continue;
4092                 }
4093
4094                 /* Train 2 */
4095                 reg = FDI_TX_CTL(pipe);
4096                 temp = I915_READ(reg);
4097                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4098                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4099                 I915_WRITE(reg, temp);
4100
4101                 reg = FDI_RX_CTL(pipe);
4102                 temp = I915_READ(reg);
4103                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4104                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4105                 I915_WRITE(reg, temp);
4106
4107                 POSTING_READ(reg);
4108                 udelay(2); /* should be 1.5us */
4109
4110                 for (i = 0; i < 4; i++) {
4111                         reg = FDI_RX_IIR(pipe);
4112                         temp = I915_READ(reg);
4113                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4114
4115                         if (temp & FDI_RX_SYMBOL_LOCK ||
4116                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4117                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4118                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4119                                               i);
4120                                 goto train_done;
4121                         }
4122                         udelay(2); /* should be 1.5us */
4123                 }
4124                 if (i == 4)
4125                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4126         }
4127
4128 train_done:
4129         DRM_DEBUG_KMS("FDI train done.\n");
4130 }
4131
4132 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4133 {
4134         struct drm_device *dev = intel_crtc->base.dev;
4135         struct drm_i915_private *dev_priv = to_i915(dev);
4136         int pipe = intel_crtc->pipe;
4137         i915_reg_t reg;
4138         u32 temp;
4139
4140         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4141         reg = FDI_RX_CTL(pipe);
4142         temp = I915_READ(reg);
4143         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4144         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4145         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4146         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4147
4148         POSTING_READ(reg);
4149         udelay(200);
4150
4151         /* Switch from Rawclk to PCDclk */
4152         temp = I915_READ(reg);
4153         I915_WRITE(reg, temp | FDI_PCDCLK);
4154
4155         POSTING_READ(reg);
4156         udelay(200);
4157
4158         /* Enable CPU FDI TX PLL, always on for Ironlake */
4159         reg = FDI_TX_CTL(pipe);
4160         temp = I915_READ(reg);
4161         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4162                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4163
4164                 POSTING_READ(reg);
4165                 udelay(100);
4166         }
4167 }
4168
4169 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4170 {
4171         struct drm_device *dev = intel_crtc->base.dev;
4172         struct drm_i915_private *dev_priv = to_i915(dev);
4173         int pipe = intel_crtc->pipe;
4174         i915_reg_t reg;
4175         u32 temp;
4176
4177         /* Switch from PCDclk to Rawclk */
4178         reg = FDI_RX_CTL(pipe);
4179         temp = I915_READ(reg);
4180         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4181
4182         /* Disable CPU FDI TX PLL */
4183         reg = FDI_TX_CTL(pipe);
4184         temp = I915_READ(reg);
4185         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4186
4187         POSTING_READ(reg);
4188         udelay(100);
4189
4190         reg = FDI_RX_CTL(pipe);
4191         temp = I915_READ(reg);
4192         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4193
4194         /* Wait for the clocks to turn off. */
4195         POSTING_READ(reg);
4196         udelay(100);
4197 }
4198
4199 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = to_i915(dev);
4203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204         int pipe = intel_crtc->pipe;
4205         i915_reg_t reg;
4206         u32 temp;
4207
4208         /* disable CPU FDI tx and PCH FDI rx */
4209         reg = FDI_TX_CTL(pipe);
4210         temp = I915_READ(reg);
4211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4212         POSTING_READ(reg);
4213
4214         reg = FDI_RX_CTL(pipe);
4215         temp = I915_READ(reg);
4216         temp &= ~(0x7 << 16);
4217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4219
4220         POSTING_READ(reg);
4221         udelay(100);
4222
4223         /* Ironlake workaround, disable clock pointer after downing FDI */
4224         if (HAS_PCH_IBX(dev_priv))
4225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4226
4227         /* still set train pattern 1 */
4228         reg = FDI_TX_CTL(pipe);
4229         temp = I915_READ(reg);
4230         temp &= ~FDI_LINK_TRAIN_NONE;
4231         temp |= FDI_LINK_TRAIN_PATTERN_1;
4232         I915_WRITE(reg, temp);
4233
4234         reg = FDI_RX_CTL(pipe);
4235         temp = I915_READ(reg);
4236         if (HAS_PCH_CPT(dev_priv)) {
4237                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4238                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4239         } else {
4240                 temp &= ~FDI_LINK_TRAIN_NONE;
4241                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4242         }
4243         /* BPC in FDI rx is consistent with that in PIPECONF */
4244         temp &= ~(0x07 << 16);
4245         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4246         I915_WRITE(reg, temp);
4247
4248         POSTING_READ(reg);
4249         udelay(100);
4250 }
4251
4252 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4253 {
4254         struct drm_crtc *crtc;
4255         bool cleanup_done;
4256
4257         drm_for_each_crtc(crtc, &dev_priv->drm) {
4258                 struct drm_crtc_commit *commit;
4259                 spin_lock(&crtc->commit_lock);
4260                 commit = list_first_entry_or_null(&crtc->commit_list,
4261                                                   struct drm_crtc_commit, commit_entry);
4262                 cleanup_done = commit ?
4263                         try_wait_for_completion(&commit->cleanup_done) : true;
4264                 spin_unlock(&crtc->commit_lock);
4265
4266                 if (cleanup_done)
4267                         continue;
4268
4269                 drm_crtc_wait_one_vblank(crtc);
4270
4271                 return true;
4272         }
4273
4274         return false;
4275 }
4276
4277 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4278 {
4279         u32 temp;
4280
4281         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4282
4283         mutex_lock(&dev_priv->sb_lock);
4284
4285         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4286         temp |= SBI_SSCCTL_DISABLE;
4287         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4288
4289         mutex_unlock(&dev_priv->sb_lock);
4290 }
4291
4292 /* Program iCLKIP clock to the desired frequency */
4293 static void lpt_program_iclkip(struct intel_crtc *crtc)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4296         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4297         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4298         u32 temp;
4299
4300         lpt_disable_iclkip(dev_priv);
4301
4302         /* The iCLK virtual clock root frequency is in MHz,
4303          * but the adjusted_mode->crtc_clock in in KHz. To get the
4304          * divisors, it is necessary to divide one by another, so we
4305          * convert the virtual clock precision to KHz here for higher
4306          * precision.
4307          */
4308         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4309                 u32 iclk_virtual_root_freq = 172800 * 1000;
4310                 u32 iclk_pi_range = 64;
4311                 u32 desired_divisor;
4312
4313                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4314                                                     clock << auxdiv);
4315                 divsel = (desired_divisor / iclk_pi_range) - 2;
4316                 phaseinc = desired_divisor % iclk_pi_range;
4317
4318                 /*
4319                  * Near 20MHz is a corner case which is
4320                  * out of range for the 7-bit divisor
4321                  */
4322                 if (divsel <= 0x7f)
4323                         break;
4324         }
4325
4326         /* This should not happen with any sane values */
4327         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4328                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4329         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4330                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4331
4332         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4333                         clock,
4334                         auxdiv,
4335                         divsel,
4336                         phasedir,
4337                         phaseinc);
4338
4339         mutex_lock(&dev_priv->sb_lock);
4340
4341         /* Program SSCDIVINTPHASE6 */
4342         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4343         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4344         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4345         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4346         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4347         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4348         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4349         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4350
4351         /* Program SSCAUXDIV */
4352         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4353         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4354         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4355         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4356
4357         /* Enable modulator and associated divider */
4358         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4359         temp &= ~SBI_SSCCTL_DISABLE;
4360         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4361
4362         mutex_unlock(&dev_priv->sb_lock);
4363
4364         /* Wait for initialization time */
4365         udelay(24);
4366
4367         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4368 }
4369
4370 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4371 {
4372         u32 divsel, phaseinc, auxdiv;
4373         u32 iclk_virtual_root_freq = 172800 * 1000;
4374         u32 iclk_pi_range = 64;
4375         u32 desired_divisor;
4376         u32 temp;
4377
4378         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4379                 return 0;
4380
4381         mutex_lock(&dev_priv->sb_lock);
4382
4383         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4384         if (temp & SBI_SSCCTL_DISABLE) {
4385                 mutex_unlock(&dev_priv->sb_lock);
4386                 return 0;
4387         }
4388
4389         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4390         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4391                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4392         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4393                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4394
4395         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4396         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4397                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4398
4399         mutex_unlock(&dev_priv->sb_lock);
4400
4401         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4402
4403         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4404                                  desired_divisor << auxdiv);
4405 }
4406
4407 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4408                                                 enum pipe pch_transcoder)
4409 {
4410         struct drm_device *dev = crtc->base.dev;
4411         struct drm_i915_private *dev_priv = to_i915(dev);
4412         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4413
4414         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4415                    I915_READ(HTOTAL(cpu_transcoder)));
4416         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4417                    I915_READ(HBLANK(cpu_transcoder)));
4418         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4419                    I915_READ(HSYNC(cpu_transcoder)));
4420
4421         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4422                    I915_READ(VTOTAL(cpu_transcoder)));
4423         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4424                    I915_READ(VBLANK(cpu_transcoder)));
4425         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4426                    I915_READ(VSYNC(cpu_transcoder)));
4427         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4428                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4429 }
4430
4431 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4432 {
4433         struct drm_i915_private *dev_priv = to_i915(dev);
4434         uint32_t temp;
4435
4436         temp = I915_READ(SOUTH_CHICKEN1);
4437         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4438                 return;
4439
4440         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4441         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4442
4443         temp &= ~FDI_BC_BIFURCATION_SELECT;
4444         if (enable)
4445                 temp |= FDI_BC_BIFURCATION_SELECT;
4446
4447         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4448         I915_WRITE(SOUTH_CHICKEN1, temp);
4449         POSTING_READ(SOUTH_CHICKEN1);
4450 }
4451
4452 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4453 {
4454         struct drm_device *dev = intel_crtc->base.dev;
4455
4456         switch (intel_crtc->pipe) {
4457         case PIPE_A:
4458                 break;
4459         case PIPE_B:
4460                 if (intel_crtc->config->fdi_lanes > 2)
4461                         cpt_set_fdi_bc_bifurcation(dev, false);
4462                 else
4463                         cpt_set_fdi_bc_bifurcation(dev, true);
4464
4465                 break;
4466         case PIPE_C:
4467                 cpt_set_fdi_bc_bifurcation(dev, true);
4468
4469                 break;
4470         default:
4471                 BUG();
4472         }
4473 }
4474
4475 /* Return which DP Port should be selected for Transcoder DP control */
4476 static enum port
4477 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4478 {
4479         struct drm_device *dev = crtc->base.dev;
4480         struct intel_encoder *encoder;
4481
4482         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4483                 if (encoder->type == INTEL_OUTPUT_DP ||
4484                     encoder->type == INTEL_OUTPUT_EDP)
4485                         return encoder->port;
4486         }
4487
4488         return -1;
4489 }
4490
4491 /*
4492  * Enable PCH resources required for PCH ports:
4493  *   - PCH PLLs
4494  *   - FDI training & RX/TX
4495  *   - update transcoder timings
4496  *   - DP transcoding bits
4497  *   - transcoder
4498  */
4499 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4500 {
4501         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4502         struct drm_device *dev = crtc->base.dev;
4503         struct drm_i915_private *dev_priv = to_i915(dev);
4504         int pipe = crtc->pipe;
4505         u32 temp;
4506
4507         assert_pch_transcoder_disabled(dev_priv, pipe);
4508
4509         if (IS_IVYBRIDGE(dev_priv))
4510                 ivybridge_update_fdi_bc_bifurcation(crtc);
4511
4512         /* Write the TU size bits before fdi link training, so that error
4513          * detection works. */
4514         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4515                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4516
4517         /* For PCH output, training FDI link */
4518         dev_priv->display.fdi_link_train(crtc, crtc_state);
4519
4520         /* We need to program the right clock selection before writing the pixel
4521          * mutliplier into the DPLL. */
4522         if (HAS_PCH_CPT(dev_priv)) {
4523                 u32 sel;
4524
4525                 temp = I915_READ(PCH_DPLL_SEL);
4526                 temp |= TRANS_DPLL_ENABLE(pipe);
4527                 sel = TRANS_DPLLB_SEL(pipe);
4528                 if (crtc_state->shared_dpll ==
4529                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4530                         temp |= sel;
4531                 else
4532                         temp &= ~sel;
4533                 I915_WRITE(PCH_DPLL_SEL, temp);
4534         }
4535
4536         /* XXX: pch pll's can be enabled any time before we enable the PCH
4537          * transcoder, and we actually should do this to not upset any PCH
4538          * transcoder that already use the clock when we share it.
4539          *
4540          * Note that enable_shared_dpll tries to do the right thing, but
4541          * get_shared_dpll unconditionally resets the pll - we need that to have
4542          * the right LVDS enable sequence. */
4543         intel_enable_shared_dpll(crtc);
4544
4545         /* set transcoder timing, panel must allow it */
4546         assert_panel_unlocked(dev_priv, pipe);
4547         ironlake_pch_transcoder_set_timings(crtc, pipe);
4548
4549         intel_fdi_normal_train(crtc);
4550
4551         /* For PCH DP, enable TRANS_DP_CTL */
4552         if (HAS_PCH_CPT(dev_priv) &&
4553             intel_crtc_has_dp_encoder(crtc_state)) {
4554                 const struct drm_display_mode *adjusted_mode =
4555                         &crtc_state->base.adjusted_mode;
4556                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4557                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4558                 temp = I915_READ(reg);
4559                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4560                           TRANS_DP_SYNC_MASK |
4561                           TRANS_DP_BPC_MASK);
4562                 temp |= TRANS_DP_OUTPUT_ENABLE;
4563                 temp |= bpc << 9; /* same format but at 11:9 */
4564
4565                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4566                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4567                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4568                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4569
4570                 switch (intel_trans_dp_port_sel(crtc)) {
4571                 case PORT_B:
4572                         temp |= TRANS_DP_PORT_SEL_B;
4573                         break;
4574                 case PORT_C:
4575                         temp |= TRANS_DP_PORT_SEL_C;
4576                         break;
4577                 case PORT_D:
4578                         temp |= TRANS_DP_PORT_SEL_D;
4579                         break;
4580                 default:
4581                         BUG();
4582                 }
4583
4584                 I915_WRITE(reg, temp);
4585         }
4586
4587         ironlake_enable_pch_transcoder(dev_priv, pipe);
4588 }
4589
4590 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4591 {
4592         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4594         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4595
4596         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4597
4598         lpt_program_iclkip(crtc);
4599
4600         /* Set transcoder timing. */
4601         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4602
4603         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4604 }
4605
4606 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4607 {
4608         struct drm_i915_private *dev_priv = to_i915(dev);
4609         i915_reg_t dslreg = PIPEDSL(pipe);
4610         u32 temp;
4611
4612         temp = I915_READ(dslreg);
4613         udelay(500);
4614         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4615                 if (wait_for(I915_READ(dslreg) != temp, 5))
4616                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4617         }
4618 }
4619
4620 static int
4621 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4622                   unsigned int scaler_user, int *scaler_id,
4623                   int src_w, int src_h, int dst_w, int dst_h)
4624 {
4625         struct intel_crtc_scaler_state *scaler_state =
4626                 &crtc_state->scaler_state;
4627         struct intel_crtc *intel_crtc =
4628                 to_intel_crtc(crtc_state->base.crtc);
4629         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4630         const struct drm_display_mode *adjusted_mode =
4631                 &crtc_state->base.adjusted_mode;
4632         int need_scaling;
4633
4634         /*
4635          * Src coordinates are already rotated by 270 degrees for
4636          * the 90/270 degree plane rotation cases (to match the
4637          * GTT mapping), hence no need to account for rotation here.
4638          */
4639         need_scaling = src_w != dst_w || src_h != dst_h;
4640
4641         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4642                 need_scaling = true;
4643
4644         /*
4645          * Scaling/fitting not supported in IF-ID mode in GEN9+
4646          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4647          * Once NV12 is enabled, handle it here while allocating scaler
4648          * for NV12.
4649          */
4650         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4651             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4653                 return -EINVAL;
4654         }
4655
4656         /*
4657          * if plane is being disabled or scaler is no more required or force detach
4658          *  - free scaler binded to this plane/crtc
4659          *  - in order to do this, update crtc->scaler_usage
4660          *
4661          * Here scaler state in crtc_state is set free so that
4662          * scaler can be assigned to other user. Actual register
4663          * update to free the scaler is done in plane/panel-fit programming.
4664          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4665          */
4666         if (force_detach || !need_scaling) {
4667                 if (*scaler_id >= 0) {
4668                         scaler_state->scaler_users &= ~(1 << scaler_user);
4669                         scaler_state->scalers[*scaler_id].in_use = 0;
4670
4671                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4672                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4673                                 intel_crtc->pipe, scaler_user, *scaler_id,
4674                                 scaler_state->scaler_users);
4675                         *scaler_id = -1;
4676                 }
4677                 return 0;
4678         }
4679
4680         /* range checks */
4681         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4682                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4683
4684                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4685                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4686                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4687                         "size is out of scaler range\n",
4688                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4689                 return -EINVAL;
4690         }
4691
4692         /* mark this plane as a scaler user in crtc_state */
4693         scaler_state->scaler_users |= (1 << scaler_user);
4694         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4695                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4696                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4697                 scaler_state->scaler_users);
4698
4699         return 0;
4700 }
4701
4702 /**
4703  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4704  *
4705  * @state: crtc's scaler state
4706  *
4707  * Return
4708  *     0 - scaler_usage updated successfully
4709  *    error - requested scaling cannot be supported or other error condition
4710  */
4711 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4712 {
4713         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4714
4715         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4716                 &state->scaler_state.scaler_id,
4717                 state->pipe_src_w, state->pipe_src_h,
4718                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4719 }
4720
4721 /**
4722  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4723  *
4724  * @state: crtc's scaler state
4725  * @plane_state: atomic plane state to update
4726  *
4727  * Return
4728  *     0 - scaler_usage updated successfully
4729  *    error - requested scaling cannot be supported or other error condition
4730  */
4731 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4732                                    struct intel_plane_state *plane_state)
4733 {
4734
4735         struct intel_plane *intel_plane =
4736                 to_intel_plane(plane_state->base.plane);
4737         struct drm_framebuffer *fb = plane_state->base.fb;
4738         int ret;
4739
4740         bool force_detach = !fb || !plane_state->base.visible;
4741
4742         ret = skl_update_scaler(crtc_state, force_detach,
4743                                 drm_plane_index(&intel_plane->base),
4744                                 &plane_state->scaler_id,
4745                                 drm_rect_width(&plane_state->base.src) >> 16,
4746                                 drm_rect_height(&plane_state->base.src) >> 16,
4747                                 drm_rect_width(&plane_state->base.dst),
4748                                 drm_rect_height(&plane_state->base.dst));
4749
4750         if (ret || plane_state->scaler_id < 0)
4751                 return ret;
4752
4753         /* check colorkey */
4754         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4755                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4756                               intel_plane->base.base.id,
4757                               intel_plane->base.name);
4758                 return -EINVAL;
4759         }
4760
4761         /* Check src format */
4762         switch (fb->format->format) {
4763         case DRM_FORMAT_RGB565:
4764         case DRM_FORMAT_XBGR8888:
4765         case DRM_FORMAT_XRGB8888:
4766         case DRM_FORMAT_ABGR8888:
4767         case DRM_FORMAT_ARGB8888:
4768         case DRM_FORMAT_XRGB2101010:
4769         case DRM_FORMAT_XBGR2101010:
4770         case DRM_FORMAT_YUYV:
4771         case DRM_FORMAT_YVYU:
4772         case DRM_FORMAT_UYVY:
4773         case DRM_FORMAT_VYUY:
4774                 break;
4775         default:
4776                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4777                               intel_plane->base.base.id, intel_plane->base.name,
4778                               fb->base.id, fb->format->format);
4779                 return -EINVAL;
4780         }
4781
4782         return 0;
4783 }
4784
4785 static void skylake_scaler_disable(struct intel_crtc *crtc)
4786 {
4787         int i;
4788
4789         for (i = 0; i < crtc->num_scalers; i++)
4790                 skl_detach_scaler(crtc, i);
4791 }
4792
4793 static void skylake_pfit_enable(struct intel_crtc *crtc)
4794 {
4795         struct drm_device *dev = crtc->base.dev;
4796         struct drm_i915_private *dev_priv = to_i915(dev);
4797         int pipe = crtc->pipe;
4798         struct intel_crtc_scaler_state *scaler_state =
4799                 &crtc->config->scaler_state;
4800
4801         if (crtc->config->pch_pfit.enabled) {
4802                 int id;
4803
4804                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4805                         return;
4806
4807                 id = scaler_state->scaler_id;
4808                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4809                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4810                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4811                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4812         }
4813 }
4814
4815 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4816 {
4817         struct drm_device *dev = crtc->base.dev;
4818         struct drm_i915_private *dev_priv = to_i915(dev);
4819         int pipe = crtc->pipe;
4820
4821         if (crtc->config->pch_pfit.enabled) {
4822                 /* Force use of hard-coded filter coefficients
4823                  * as some pre-programmed values are broken,
4824                  * e.g. x201.
4825                  */
4826                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4827                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4828                                                  PF_PIPE_SEL_IVB(pipe));
4829                 else
4830                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4831                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4832                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4833         }
4834 }
4835
4836 void hsw_enable_ips(struct intel_crtc *crtc)
4837 {
4838         struct drm_device *dev = crtc->base.dev;
4839         struct drm_i915_private *dev_priv = to_i915(dev);
4840
4841         if (!crtc->config->ips_enabled)
4842                 return;
4843
4844         /*
4845          * We can only enable IPS after we enable a plane and wait for a vblank
4846          * This function is called from post_plane_update, which is run after
4847          * a vblank wait.
4848          */
4849
4850         assert_plane_enabled(dev_priv, crtc->plane);
4851         if (IS_BROADWELL(dev_priv)) {
4852                 mutex_lock(&dev_priv->pcu_lock);
4853                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4854                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4855                 mutex_unlock(&dev_priv->pcu_lock);
4856                 /* Quoting Art Runyan: "its not safe to expect any particular
4857                  * value in IPS_CTL bit 31 after enabling IPS through the
4858                  * mailbox." Moreover, the mailbox may return a bogus state,
4859                  * so we need to just enable it and continue on.
4860                  */
4861         } else {
4862                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4863                 /* The bit only becomes 1 in the next vblank, so this wait here
4864                  * is essentially intel_wait_for_vblank. If we don't have this
4865                  * and don't wait for vblanks until the end of crtc_enable, then
4866                  * the HW state readout code will complain that the expected
4867                  * IPS_CTL value is not the one we read. */
4868                 if (intel_wait_for_register(dev_priv,
4869                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4870                                             50))
4871                         DRM_ERROR("Timed out waiting for IPS enable\n");
4872         }
4873 }
4874
4875 void hsw_disable_ips(struct intel_crtc *crtc)
4876 {
4877         struct drm_device *dev = crtc->base.dev;
4878         struct drm_i915_private *dev_priv = to_i915(dev);
4879
4880         if (!crtc->config->ips_enabled)
4881                 return;
4882
4883         assert_plane_enabled(dev_priv, crtc->plane);
4884         if (IS_BROADWELL(dev_priv)) {
4885                 mutex_lock(&dev_priv->pcu_lock);
4886                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4887                 mutex_unlock(&dev_priv->pcu_lock);
4888                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4889                 if (intel_wait_for_register(dev_priv,
4890                                             IPS_CTL, IPS_ENABLE, 0,
4891                                             42))
4892                         DRM_ERROR("Timed out waiting for IPS disable\n");
4893         } else {
4894                 I915_WRITE(IPS_CTL, 0);
4895                 POSTING_READ(IPS_CTL);
4896         }
4897
4898         /* We need to wait for a vblank before we can disable the plane. */
4899         intel_wait_for_vblank(dev_priv, crtc->pipe);
4900 }
4901
4902 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4903 {
4904         if (intel_crtc->overlay) {
4905                 struct drm_device *dev = intel_crtc->base.dev;
4906
4907                 mutex_lock(&dev->struct_mutex);
4908                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4909                 mutex_unlock(&dev->struct_mutex);
4910         }
4911
4912         /* Let userspace switch the overlay on again. In most cases userspace
4913          * has to recompute where to put it anyway.
4914          */
4915 }
4916
4917 /**
4918  * intel_post_enable_primary - Perform operations after enabling primary plane
4919  * @crtc: the CRTC whose primary plane was just enabled
4920  *
4921  * Performs potentially sleeping operations that must be done after the primary
4922  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4923  * called due to an explicit primary plane update, or due to an implicit
4924  * re-enable that is caused when a sprite plane is updated to no longer
4925  * completely hide the primary plane.
4926  */
4927 static void
4928 intel_post_enable_primary(struct drm_crtc *crtc)
4929 {
4930         struct drm_device *dev = crtc->dev;
4931         struct drm_i915_private *dev_priv = to_i915(dev);
4932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933         int pipe = intel_crtc->pipe;
4934
4935         /*
4936          * FIXME IPS should be fine as long as one plane is
4937          * enabled, but in practice it seems to have problems
4938          * when going from primary only to sprite only and vice
4939          * versa.
4940          */
4941         hsw_enable_ips(intel_crtc);
4942
4943         /*
4944          * Gen2 reports pipe underruns whenever all planes are disabled.
4945          * So don't enable underrun reporting before at least some planes
4946          * are enabled.
4947          * FIXME: Need to fix the logic to work when we turn off all planes
4948          * but leave the pipe running.
4949          */
4950         if (IS_GEN2(dev_priv))
4951                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4952
4953         /* Underruns don't always raise interrupts, so check manually. */
4954         intel_check_cpu_fifo_underruns(dev_priv);
4955         intel_check_pch_fifo_underruns(dev_priv);
4956 }
4957
4958 /* FIXME move all this to pre_plane_update() with proper state tracking */
4959 static void
4960 intel_pre_disable_primary(struct drm_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->dev;
4963         struct drm_i915_private *dev_priv = to_i915(dev);
4964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965         int pipe = intel_crtc->pipe;
4966
4967         /*
4968          * Gen2 reports pipe underruns whenever all planes are disabled.
4969          * So diasble underrun reporting before all the planes get disabled.
4970          * FIXME: Need to fix the logic to work when we turn off all planes
4971          * but leave the pipe running.
4972          */
4973         if (IS_GEN2(dev_priv))
4974                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4975
4976         /*
4977          * FIXME IPS should be fine as long as one plane is
4978          * enabled, but in practice it seems to have problems
4979          * when going from primary only to sprite only and vice
4980          * versa.
4981          */
4982         hsw_disable_ips(intel_crtc);
4983 }
4984
4985 /* FIXME get rid of this and use pre_plane_update */
4986 static void
4987 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4988 {
4989         struct drm_device *dev = crtc->dev;
4990         struct drm_i915_private *dev_priv = to_i915(dev);
4991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992         int pipe = intel_crtc->pipe;
4993
4994         intel_pre_disable_primary(crtc);
4995
4996         /*
4997          * Vblank time updates from the shadow to live plane control register
4998          * are blocked if the memory self-refresh mode is active at that
4999          * moment. So to make sure the plane gets truly disabled, disable
5000          * first the self-refresh mode. The self-refresh enable bit in turn
5001          * will be checked/applied by the HW only at the next frame start
5002          * event which is after the vblank start event, so we need to have a
5003          * wait-for-vblank between disabling the plane and the pipe.
5004          */
5005         if (HAS_GMCH_DISPLAY(dev_priv) &&
5006             intel_set_memory_cxsr(dev_priv, false))
5007                 intel_wait_for_vblank(dev_priv, pipe);
5008 }
5009
5010 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5011 {
5012         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5013         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5014         struct intel_crtc_state *pipe_config =
5015                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5016                                                 crtc);
5017         struct drm_plane *primary = crtc->base.primary;
5018         struct drm_plane_state *old_pri_state =
5019                 drm_atomic_get_existing_plane_state(old_state, primary);
5020
5021         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5022
5023         if (pipe_config->update_wm_post && pipe_config->base.active)
5024                 intel_update_watermarks(crtc);
5025
5026         if (old_pri_state) {
5027                 struct intel_plane_state *primary_state =
5028                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5029                                                          to_intel_plane(primary));
5030                 struct intel_plane_state *old_primary_state =
5031                         to_intel_plane_state(old_pri_state);
5032
5033                 intel_fbc_post_update(crtc);
5034
5035                 if (primary_state->base.visible &&
5036                     (needs_modeset(&pipe_config->base) ||
5037                      !old_primary_state->base.visible))
5038                         intel_post_enable_primary(&crtc->base);
5039         }
5040 }
5041
5042 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5043                                    struct intel_crtc_state *pipe_config)
5044 {
5045         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5046         struct drm_device *dev = crtc->base.dev;
5047         struct drm_i915_private *dev_priv = to_i915(dev);
5048         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5049         struct drm_plane *primary = crtc->base.primary;
5050         struct drm_plane_state *old_pri_state =
5051                 drm_atomic_get_existing_plane_state(old_state, primary);
5052         bool modeset = needs_modeset(&pipe_config->base);
5053         struct intel_atomic_state *old_intel_state =
5054                 to_intel_atomic_state(old_state);
5055
5056         if (old_pri_state) {
5057                 struct intel_plane_state *primary_state =
5058                         intel_atomic_get_new_plane_state(old_intel_state,
5059                                                          to_intel_plane(primary));
5060                 struct intel_plane_state *old_primary_state =
5061                         to_intel_plane_state(old_pri_state);
5062
5063                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5064
5065                 if (old_primary_state->base.visible &&
5066                     (modeset || !primary_state->base.visible))
5067                         intel_pre_disable_primary(&crtc->base);
5068         }
5069
5070         /*
5071          * Vblank time updates from the shadow to live plane control register
5072          * are blocked if the memory self-refresh mode is active at that
5073          * moment. So to make sure the plane gets truly disabled, disable
5074          * first the self-refresh mode. The self-refresh enable bit in turn
5075          * will be checked/applied by the HW only at the next frame start
5076          * event which is after the vblank start event, so we need to have a
5077          * wait-for-vblank between disabling the plane and the pipe.
5078          */
5079         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5080             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5081                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5082
5083         /*
5084          * IVB workaround: must disable low power watermarks for at least
5085          * one frame before enabling scaling.  LP watermarks can be re-enabled
5086          * when scaling is disabled.
5087          *
5088          * WaCxSRDisabledForSpriteScaling:ivb
5089          */
5090         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5091                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5092
5093         /*
5094          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5095          * watermark programming here.
5096          */
5097         if (needs_modeset(&pipe_config->base))
5098                 return;
5099
5100         /*
5101          * For platforms that support atomic watermarks, program the
5102          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5103          * will be the intermediate values that are safe for both pre- and
5104          * post- vblank; when vblank happens, the 'active' values will be set
5105          * to the final 'target' values and we'll do this again to get the
5106          * optimal watermarks.  For gen9+ platforms, the values we program here
5107          * will be the final target values which will get automatically latched
5108          * at vblank time; no further programming will be necessary.
5109          *
5110          * If a platform hasn't been transitioned to atomic watermarks yet,
5111          * we'll continue to update watermarks the old way, if flags tell
5112          * us to.
5113          */
5114         if (dev_priv->display.initial_watermarks != NULL)
5115                 dev_priv->display.initial_watermarks(old_intel_state,
5116                                                      pipe_config);
5117         else if (pipe_config->update_wm_pre)
5118                 intel_update_watermarks(crtc);
5119 }
5120
5121 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5122 {
5123         struct drm_device *dev = crtc->dev;
5124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5125         struct drm_plane *p;
5126         int pipe = intel_crtc->pipe;
5127
5128         intel_crtc_dpms_overlay_disable(intel_crtc);
5129
5130         drm_for_each_plane_mask(p, dev, plane_mask)
5131                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5132
5133         /*
5134          * FIXME: Once we grow proper nuclear flip support out of this we need
5135          * to compute the mask of flip planes precisely. For the time being
5136          * consider this a flip to a NULL plane.
5137          */
5138         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5139 }
5140
5141 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5142                                           struct intel_crtc_state *crtc_state,
5143                                           struct drm_atomic_state *old_state)
5144 {
5145         struct drm_connector_state *conn_state;
5146         struct drm_connector *conn;
5147         int i;
5148
5149         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5150                 struct intel_encoder *encoder =
5151                         to_intel_encoder(conn_state->best_encoder);
5152
5153                 if (conn_state->crtc != crtc)
5154                         continue;
5155
5156                 if (encoder->pre_pll_enable)
5157                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5158         }
5159 }
5160
5161 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5162                                       struct intel_crtc_state *crtc_state,
5163                                       struct drm_atomic_state *old_state)
5164 {
5165         struct drm_connector_state *conn_state;
5166         struct drm_connector *conn;
5167         int i;
5168
5169         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5170                 struct intel_encoder *encoder =
5171                         to_intel_encoder(conn_state->best_encoder);
5172
5173                 if (conn_state->crtc != crtc)
5174                         continue;
5175
5176                 if (encoder->pre_enable)
5177                         encoder->pre_enable(encoder, crtc_state, conn_state);
5178         }
5179 }
5180
5181 static void intel_encoders_enable(struct drm_crtc *crtc,
5182                                   struct intel_crtc_state *crtc_state,
5183                                   struct drm_atomic_state *old_state)
5184 {
5185         struct drm_connector_state *conn_state;
5186         struct drm_connector *conn;
5187         int i;
5188
5189         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5190                 struct intel_encoder *encoder =
5191                         to_intel_encoder(conn_state->best_encoder);
5192
5193                 if (conn_state->crtc != crtc)
5194                         continue;
5195
5196                 encoder->enable(encoder, crtc_state, conn_state);
5197                 intel_opregion_notify_encoder(encoder, true);
5198         }
5199 }
5200
5201 static void intel_encoders_disable(struct drm_crtc *crtc,
5202                                    struct intel_crtc_state *old_crtc_state,
5203                                    struct drm_atomic_state *old_state)
5204 {
5205         struct drm_connector_state *old_conn_state;
5206         struct drm_connector *conn;
5207         int i;
5208
5209         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5210                 struct intel_encoder *encoder =
5211                         to_intel_encoder(old_conn_state->best_encoder);
5212
5213                 if (old_conn_state->crtc != crtc)
5214                         continue;
5215
5216                 intel_opregion_notify_encoder(encoder, false);
5217                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5218         }
5219 }
5220
5221 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5222                                         struct intel_crtc_state *old_crtc_state,
5223                                         struct drm_atomic_state *old_state)
5224 {
5225         struct drm_connector_state *old_conn_state;
5226         struct drm_connector *conn;
5227         int i;
5228
5229         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5230                 struct intel_encoder *encoder =
5231                         to_intel_encoder(old_conn_state->best_encoder);
5232
5233                 if (old_conn_state->crtc != crtc)
5234                         continue;
5235
5236                 if (encoder->post_disable)
5237                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5238         }
5239 }
5240
5241 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5242                                             struct intel_crtc_state *old_crtc_state,
5243                                             struct drm_atomic_state *old_state)
5244 {
5245         struct drm_connector_state *old_conn_state;
5246         struct drm_connector *conn;
5247         int i;
5248
5249         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5250                 struct intel_encoder *encoder =
5251                         to_intel_encoder(old_conn_state->best_encoder);
5252
5253                 if (old_conn_state->crtc != crtc)
5254                         continue;
5255
5256                 if (encoder->post_pll_disable)
5257                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5258         }
5259 }
5260
5261 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5262                                  struct drm_atomic_state *old_state)
5263 {
5264         struct drm_crtc *crtc = pipe_config->base.crtc;
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = to_i915(dev);
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         int pipe = intel_crtc->pipe;
5269         struct intel_atomic_state *old_intel_state =
5270                 to_intel_atomic_state(old_state);
5271
5272         if (WARN_ON(intel_crtc->active))
5273                 return;
5274
5275         /*
5276          * Sometimes spurious CPU pipe underruns happen during FDI
5277          * training, at least with VGA+HDMI cloning. Suppress them.
5278          *
5279          * On ILK we get an occasional spurious CPU pipe underruns
5280          * between eDP port A enable and vdd enable. Also PCH port
5281          * enable seems to result in the occasional CPU pipe underrun.
5282          *
5283          * Spurious PCH underruns also occur during PCH enabling.
5284          */
5285         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5286                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5287         if (intel_crtc->config->has_pch_encoder)
5288                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5289
5290         if (intel_crtc->config->has_pch_encoder)
5291                 intel_prepare_shared_dpll(intel_crtc);
5292
5293         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5294                 intel_dp_set_m_n(intel_crtc, M1_N1);
5295
5296         intel_set_pipe_timings(intel_crtc);
5297         intel_set_pipe_src_size(intel_crtc);
5298
5299         if (intel_crtc->config->has_pch_encoder) {
5300                 intel_cpu_transcoder_set_m_n(intel_crtc,
5301                                      &intel_crtc->config->fdi_m_n, NULL);
5302         }
5303
5304         ironlake_set_pipeconf(crtc);
5305
5306         intel_crtc->active = true;
5307
5308         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5309
5310         if (intel_crtc->config->has_pch_encoder) {
5311                 /* Note: FDI PLL enabling _must_ be done before we enable the
5312                  * cpu pipes, hence this is separate from all the other fdi/pch
5313                  * enabling. */
5314                 ironlake_fdi_pll_enable(intel_crtc);
5315         } else {
5316                 assert_fdi_tx_disabled(dev_priv, pipe);
5317                 assert_fdi_rx_disabled(dev_priv, pipe);
5318         }
5319
5320         ironlake_pfit_enable(intel_crtc);
5321
5322         /*
5323          * On ILK+ LUT must be loaded before the pipe is running but with
5324          * clocks enabled
5325          */
5326         intel_color_load_luts(&pipe_config->base);
5327
5328         if (dev_priv->display.initial_watermarks != NULL)
5329                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5330         intel_enable_pipe(intel_crtc);
5331
5332         if (intel_crtc->config->has_pch_encoder)
5333                 ironlake_pch_enable(pipe_config);
5334
5335         assert_vblank_disabled(crtc);
5336         drm_crtc_vblank_on(crtc);
5337
5338         intel_encoders_enable(crtc, pipe_config, old_state);
5339
5340         if (HAS_PCH_CPT(dev_priv))
5341                 cpt_verify_modeset(dev, intel_crtc->pipe);
5342
5343         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5344         if (intel_crtc->config->has_pch_encoder)
5345                 intel_wait_for_vblank(dev_priv, pipe);
5346         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5347         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5348 }
5349
5350 /* IPS only exists on ULT machines and is tied to pipe A. */
5351 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5352 {
5353         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5354 }
5355
5356 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5357                                             enum pipe pipe, bool apply)
5358 {
5359         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5360         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5361
5362         if (apply)
5363                 val |= mask;
5364         else
5365                 val &= ~mask;
5366
5367         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5368 }
5369
5370 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5371                                 struct drm_atomic_state *old_state)
5372 {
5373         struct drm_crtc *crtc = pipe_config->base.crtc;
5374         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5377         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5378         struct intel_atomic_state *old_intel_state =
5379                 to_intel_atomic_state(old_state);
5380         bool psl_clkgate_wa;
5381
5382         if (WARN_ON(intel_crtc->active))
5383                 return;
5384
5385         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5386
5387         if (intel_crtc->config->shared_dpll)
5388                 intel_enable_shared_dpll(intel_crtc);
5389
5390         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5391                 intel_dp_set_m_n(intel_crtc, M1_N1);
5392
5393         if (!transcoder_is_dsi(cpu_transcoder))
5394                 intel_set_pipe_timings(intel_crtc);
5395
5396         intel_set_pipe_src_size(intel_crtc);
5397
5398         if (cpu_transcoder != TRANSCODER_EDP &&
5399             !transcoder_is_dsi(cpu_transcoder)) {
5400                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5401                            intel_crtc->config->pixel_multiplier - 1);
5402         }
5403
5404         if (intel_crtc->config->has_pch_encoder) {
5405                 intel_cpu_transcoder_set_m_n(intel_crtc,
5406                                      &intel_crtc->config->fdi_m_n, NULL);
5407         }
5408
5409         if (!transcoder_is_dsi(cpu_transcoder))
5410                 haswell_set_pipeconf(crtc);
5411
5412         haswell_set_pipemisc(crtc);
5413
5414         intel_color_set_csc(&pipe_config->base);
5415
5416         intel_crtc->active = true;
5417
5418         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5419
5420         if (!transcoder_is_dsi(cpu_transcoder))
5421                 intel_ddi_enable_pipe_clock(pipe_config);
5422
5423         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5424         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5425                          intel_crtc->config->pch_pfit.enabled;
5426         if (psl_clkgate_wa)
5427                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5428
5429         if (INTEL_GEN(dev_priv) >= 9)
5430                 skylake_pfit_enable(intel_crtc);
5431         else
5432                 ironlake_pfit_enable(intel_crtc);
5433
5434         /*
5435          * On ILK+ LUT must be loaded before the pipe is running but with
5436          * clocks enabled
5437          */
5438         intel_color_load_luts(&pipe_config->base);
5439
5440         intel_ddi_set_pipe_settings(pipe_config);
5441         if (!transcoder_is_dsi(cpu_transcoder))
5442                 intel_ddi_enable_transcoder_func(pipe_config);
5443
5444         if (dev_priv->display.initial_watermarks != NULL)
5445                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5446
5447         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5448         if (!transcoder_is_dsi(cpu_transcoder))
5449                 intel_enable_pipe(intel_crtc);
5450
5451         if (intel_crtc->config->has_pch_encoder)
5452                 lpt_pch_enable(pipe_config);
5453
5454         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5455                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5456
5457         assert_vblank_disabled(crtc);
5458         drm_crtc_vblank_on(crtc);
5459
5460         intel_encoders_enable(crtc, pipe_config, old_state);
5461
5462         if (psl_clkgate_wa) {
5463                 intel_wait_for_vblank(dev_priv, pipe);
5464                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5465         }
5466
5467         /* If we change the relative order between pipe/planes enabling, we need
5468          * to change the workaround. */
5469         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5470         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5471                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5472                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5473         }
5474 }
5475
5476 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5477 {
5478         struct drm_device *dev = crtc->base.dev;
5479         struct drm_i915_private *dev_priv = to_i915(dev);
5480         int pipe = crtc->pipe;
5481
5482         /* To avoid upsetting the power well on haswell only disable the pfit if
5483          * it's in use. The hw state code will make sure we get this right. */
5484         if (force || crtc->config->pch_pfit.enabled) {
5485                 I915_WRITE(PF_CTL(pipe), 0);
5486                 I915_WRITE(PF_WIN_POS(pipe), 0);
5487                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5488         }
5489 }
5490
5491 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5492                                   struct drm_atomic_state *old_state)
5493 {
5494         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5495         struct drm_device *dev = crtc->dev;
5496         struct drm_i915_private *dev_priv = to_i915(dev);
5497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5498         int pipe = intel_crtc->pipe;
5499
5500         /*
5501          * Sometimes spurious CPU pipe underruns happen when the
5502          * pipe is already disabled, but FDI RX/TX is still enabled.
5503          * Happens at least with VGA+HDMI cloning. Suppress them.
5504          */
5505         if (intel_crtc->config->has_pch_encoder) {
5506                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5507                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5508         }
5509
5510         intel_encoders_disable(crtc, old_crtc_state, old_state);
5511
5512         drm_crtc_vblank_off(crtc);
5513         assert_vblank_disabled(crtc);
5514
5515         intel_disable_pipe(intel_crtc);
5516
5517         ironlake_pfit_disable(intel_crtc, false);
5518
5519         if (intel_crtc->config->has_pch_encoder)
5520                 ironlake_fdi_disable(crtc);
5521
5522         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5523
5524         if (intel_crtc->config->has_pch_encoder) {
5525                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5526
5527                 if (HAS_PCH_CPT(dev_priv)) {
5528                         i915_reg_t reg;
5529                         u32 temp;
5530
5531                         /* disable TRANS_DP_CTL */
5532                         reg = TRANS_DP_CTL(pipe);
5533                         temp = I915_READ(reg);
5534                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5535                                   TRANS_DP_PORT_SEL_MASK);
5536                         temp |= TRANS_DP_PORT_SEL_NONE;
5537                         I915_WRITE(reg, temp);
5538
5539                         /* disable DPLL_SEL */
5540                         temp = I915_READ(PCH_DPLL_SEL);
5541                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5542                         I915_WRITE(PCH_DPLL_SEL, temp);
5543                 }
5544
5545                 ironlake_fdi_pll_disable(intel_crtc);
5546         }
5547
5548         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5549         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5550 }
5551
5552 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5553                                  struct drm_atomic_state *old_state)
5554 {
5555         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5556         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5559
5560         intel_encoders_disable(crtc, old_crtc_state, old_state);
5561
5562         drm_crtc_vblank_off(crtc);
5563         assert_vblank_disabled(crtc);
5564
5565         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5566         if (!transcoder_is_dsi(cpu_transcoder))
5567                 intel_disable_pipe(intel_crtc);
5568
5569         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5570                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5571
5572         if (!transcoder_is_dsi(cpu_transcoder))
5573                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5574
5575         if (INTEL_GEN(dev_priv) >= 9)
5576                 skylake_scaler_disable(intel_crtc);
5577         else
5578                 ironlake_pfit_disable(intel_crtc, false);
5579
5580         if (!transcoder_is_dsi(cpu_transcoder))
5581                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5582
5583         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5584 }
5585
5586 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5587 {
5588         struct drm_device *dev = crtc->base.dev;
5589         struct drm_i915_private *dev_priv = to_i915(dev);
5590         struct intel_crtc_state *pipe_config = crtc->config;
5591
5592         if (!pipe_config->gmch_pfit.control)
5593                 return;
5594
5595         /*
5596          * The panel fitter should only be adjusted whilst the pipe is disabled,
5597          * according to register description and PRM.
5598          */
5599         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5600         assert_pipe_disabled(dev_priv, crtc->pipe);
5601
5602         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5603         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5604
5605         /* Border color in case we don't scale up to the full screen. Black by
5606          * default, change to something else for debugging. */
5607         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5608 }
5609
5610 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5611 {
5612         switch (port) {
5613         case PORT_A:
5614                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5615         case PORT_B:
5616                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5617         case PORT_C:
5618                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5619         case PORT_D:
5620                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5621         case PORT_E:
5622                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5623         default:
5624                 MISSING_CASE(port);
5625                 return POWER_DOMAIN_PORT_OTHER;
5626         }
5627 }
5628
5629 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5630                                   struct intel_crtc_state *crtc_state)
5631 {
5632         struct drm_device *dev = crtc->dev;
5633         struct drm_i915_private *dev_priv = to_i915(dev);
5634         struct drm_encoder *encoder;
5635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636         enum pipe pipe = intel_crtc->pipe;
5637         u64 mask;
5638         enum transcoder transcoder = crtc_state->cpu_transcoder;
5639
5640         if (!crtc_state->base.active)
5641                 return 0;
5642
5643         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5644         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5645         if (crtc_state->pch_pfit.enabled ||
5646             crtc_state->pch_pfit.force_thru)
5647                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5648
5649         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5650                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5651
5652                 mask |= BIT_ULL(intel_encoder->power_domain);
5653         }
5654
5655         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5656                 mask |= BIT(POWER_DOMAIN_AUDIO);
5657
5658         if (crtc_state->shared_dpll)
5659                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5660
5661         return mask;
5662 }
5663
5664 static u64
5665 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5666                                struct intel_crtc_state *crtc_state)
5667 {
5668         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5670         enum intel_display_power_domain domain;
5671         u64 domains, new_domains, old_domains;
5672
5673         old_domains = intel_crtc->enabled_power_domains;
5674         intel_crtc->enabled_power_domains = new_domains =
5675                 get_crtc_power_domains(crtc, crtc_state);
5676
5677         domains = new_domains & ~old_domains;
5678
5679         for_each_power_domain(domain, domains)
5680                 intel_display_power_get(dev_priv, domain);
5681
5682         return old_domains & ~new_domains;
5683 }
5684
5685 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5686                                       u64 domains)
5687 {
5688         enum intel_display_power_domain domain;
5689
5690         for_each_power_domain(domain, domains)
5691                 intel_display_power_put(dev_priv, domain);
5692 }
5693
5694 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5695                                    struct drm_atomic_state *old_state)
5696 {
5697         struct intel_atomic_state *old_intel_state =
5698                 to_intel_atomic_state(old_state);
5699         struct drm_crtc *crtc = pipe_config->base.crtc;
5700         struct drm_device *dev = crtc->dev;
5701         struct drm_i915_private *dev_priv = to_i915(dev);
5702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703         int pipe = intel_crtc->pipe;
5704
5705         if (WARN_ON(intel_crtc->active))
5706                 return;
5707
5708         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5709                 intel_dp_set_m_n(intel_crtc, M1_N1);
5710
5711         intel_set_pipe_timings(intel_crtc);
5712         intel_set_pipe_src_size(intel_crtc);
5713
5714         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5715                 struct drm_i915_private *dev_priv = to_i915(dev);
5716
5717                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5718                 I915_WRITE(CHV_CANVAS(pipe), 0);
5719         }
5720
5721         i9xx_set_pipeconf(intel_crtc);
5722
5723         intel_crtc->active = true;
5724
5725         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5726
5727         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5728
5729         if (IS_CHERRYVIEW(dev_priv)) {
5730                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5731                 chv_enable_pll(intel_crtc, intel_crtc->config);
5732         } else {
5733                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5734                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5735         }
5736
5737         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5738
5739         i9xx_pfit_enable(intel_crtc);
5740
5741         intel_color_load_luts(&pipe_config->base);
5742
5743         dev_priv->display.initial_watermarks(old_intel_state,
5744                                              pipe_config);
5745         intel_enable_pipe(intel_crtc);
5746
5747         assert_vblank_disabled(crtc);
5748         drm_crtc_vblank_on(crtc);
5749
5750         intel_encoders_enable(crtc, pipe_config, old_state);
5751 }
5752
5753 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5754 {
5755         struct drm_device *dev = crtc->base.dev;
5756         struct drm_i915_private *dev_priv = to_i915(dev);
5757
5758         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5759         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5760 }
5761
5762 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5763                              struct drm_atomic_state *old_state)
5764 {
5765         struct intel_atomic_state *old_intel_state =
5766                 to_intel_atomic_state(old_state);
5767         struct drm_crtc *crtc = pipe_config->base.crtc;
5768         struct drm_device *dev = crtc->dev;
5769         struct drm_i915_private *dev_priv = to_i915(dev);
5770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771         enum pipe pipe = intel_crtc->pipe;
5772
5773         if (WARN_ON(intel_crtc->active))
5774                 return;
5775
5776         i9xx_set_pll_dividers(intel_crtc);
5777
5778         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5779                 intel_dp_set_m_n(intel_crtc, M1_N1);
5780
5781         intel_set_pipe_timings(intel_crtc);
5782         intel_set_pipe_src_size(intel_crtc);
5783
5784         i9xx_set_pipeconf(intel_crtc);
5785
5786         intel_crtc->active = true;
5787
5788         if (!IS_GEN2(dev_priv))
5789                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5790
5791         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5792
5793         i9xx_enable_pll(intel_crtc, pipe_config);
5794
5795         i9xx_pfit_enable(intel_crtc);
5796
5797         intel_color_load_luts(&pipe_config->base);
5798
5799         if (dev_priv->display.initial_watermarks != NULL)
5800                 dev_priv->display.initial_watermarks(old_intel_state,
5801                                                      intel_crtc->config);
5802         else
5803                 intel_update_watermarks(intel_crtc);
5804         intel_enable_pipe(intel_crtc);
5805
5806         assert_vblank_disabled(crtc);
5807         drm_crtc_vblank_on(crtc);
5808
5809         intel_encoders_enable(crtc, pipe_config, old_state);
5810 }
5811
5812 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5813 {
5814         struct drm_device *dev = crtc->base.dev;
5815         struct drm_i915_private *dev_priv = to_i915(dev);
5816
5817         if (!crtc->config->gmch_pfit.control)
5818                 return;
5819
5820         assert_pipe_disabled(dev_priv, crtc->pipe);
5821
5822         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5823                          I915_READ(PFIT_CONTROL));
5824         I915_WRITE(PFIT_CONTROL, 0);
5825 }
5826
5827 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5828                               struct drm_atomic_state *old_state)
5829 {
5830         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5831         struct drm_device *dev = crtc->dev;
5832         struct drm_i915_private *dev_priv = to_i915(dev);
5833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5834         int pipe = intel_crtc->pipe;
5835
5836         /*
5837          * On gen2 planes are double buffered but the pipe isn't, so we must
5838          * wait for planes to fully turn off before disabling the pipe.
5839          */
5840         if (IS_GEN2(dev_priv))
5841                 intel_wait_for_vblank(dev_priv, pipe);
5842
5843         intel_encoders_disable(crtc, old_crtc_state, old_state);
5844
5845         drm_crtc_vblank_off(crtc);
5846         assert_vblank_disabled(crtc);
5847
5848         intel_disable_pipe(intel_crtc);
5849
5850         i9xx_pfit_disable(intel_crtc);
5851
5852         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5853
5854         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5855                 if (IS_CHERRYVIEW(dev_priv))
5856                         chv_disable_pll(dev_priv, pipe);
5857                 else if (IS_VALLEYVIEW(dev_priv))
5858                         vlv_disable_pll(dev_priv, pipe);
5859                 else
5860                         i9xx_disable_pll(intel_crtc);
5861         }
5862
5863         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5864
5865         if (!IS_GEN2(dev_priv))
5866                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5867
5868         if (!dev_priv->display.initial_watermarks)
5869                 intel_update_watermarks(intel_crtc);
5870
5871         /* clock the pipe down to 640x480@60 to potentially save power */
5872         if (IS_I830(dev_priv))
5873                 i830_enable_pipe(dev_priv, pipe);
5874 }
5875
5876 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5877                                         struct drm_modeset_acquire_ctx *ctx)
5878 {
5879         struct intel_encoder *encoder;
5880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5882         enum intel_display_power_domain domain;
5883         u64 domains;
5884         struct drm_atomic_state *state;
5885         struct intel_crtc_state *crtc_state;
5886         int ret;
5887
5888         if (!intel_crtc->active)
5889                 return;
5890
5891         if (crtc->primary->state->visible) {
5892                 intel_pre_disable_primary_noatomic(crtc);
5893
5894                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5895                 crtc->primary->state->visible = false;
5896         }
5897
5898         state = drm_atomic_state_alloc(crtc->dev);
5899         if (!state) {
5900                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5901                               crtc->base.id, crtc->name);
5902                 return;
5903         }
5904
5905         state->acquire_ctx = ctx;
5906
5907         /* Everything's already locked, -EDEADLK can't happen. */
5908         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5909         ret = drm_atomic_add_affected_connectors(state, crtc);
5910
5911         WARN_ON(IS_ERR(crtc_state) || ret);
5912
5913         dev_priv->display.crtc_disable(crtc_state, state);
5914
5915         drm_atomic_state_put(state);
5916
5917         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5918                       crtc->base.id, crtc->name);
5919
5920         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5921         crtc->state->active = false;
5922         intel_crtc->active = false;
5923         crtc->enabled = false;
5924         crtc->state->connector_mask = 0;
5925         crtc->state->encoder_mask = 0;
5926
5927         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5928                 encoder->base.crtc = NULL;
5929
5930         intel_fbc_disable(intel_crtc);
5931         intel_update_watermarks(intel_crtc);
5932         intel_disable_shared_dpll(intel_crtc);
5933
5934         domains = intel_crtc->enabled_power_domains;
5935         for_each_power_domain(domain, domains)
5936                 intel_display_power_put(dev_priv, domain);
5937         intel_crtc->enabled_power_domains = 0;
5938
5939         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5940         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5941         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
5942 }
5943
5944 /*
5945  * turn all crtc's off, but do not adjust state
5946  * This has to be paired with a call to intel_modeset_setup_hw_state.
5947  */
5948 int intel_display_suspend(struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = to_i915(dev);
5951         struct drm_atomic_state *state;
5952         int ret;
5953
5954         state = drm_atomic_helper_suspend(dev);
5955         ret = PTR_ERR_OR_ZERO(state);
5956         if (ret)
5957                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5958         else
5959                 dev_priv->modeset_restore_state = state;
5960         return ret;
5961 }
5962
5963 void intel_encoder_destroy(struct drm_encoder *encoder)
5964 {
5965         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5966
5967         drm_encoder_cleanup(encoder);
5968         kfree(intel_encoder);
5969 }
5970
5971 /* Cross check the actual hw state with our own modeset state tracking (and it's
5972  * internal consistency). */
5973 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5974                                          struct drm_connector_state *conn_state)
5975 {
5976         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5977
5978         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5979                       connector->base.base.id,
5980                       connector->base.name);
5981
5982         if (connector->get_hw_state(connector)) {
5983                 struct intel_encoder *encoder = connector->encoder;
5984
5985                 I915_STATE_WARN(!crtc_state,
5986                          "connector enabled without attached crtc\n");
5987
5988                 if (!crtc_state)
5989                         return;
5990
5991                 I915_STATE_WARN(!crtc_state->active,
5992                       "connector is active, but attached crtc isn't\n");
5993
5994                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5995                         return;
5996
5997                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5998                         "atomic encoder doesn't match attached encoder\n");
5999
6000                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6001                         "attached encoder crtc differs from connector crtc\n");
6002         } else {
6003                 I915_STATE_WARN(crtc_state && crtc_state->active,
6004                         "attached crtc is active, but connector isn't\n");
6005                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6006                         "best encoder set without crtc!\n");
6007         }
6008 }
6009
6010 int intel_connector_init(struct intel_connector *connector)
6011 {
6012         struct intel_digital_connector_state *conn_state;
6013
6014         /*
6015          * Allocate enough memory to hold intel_digital_connector_state,
6016          * This might be a few bytes too many, but for connectors that don't
6017          * need it we'll free the state and allocate a smaller one on the first
6018          * succesful commit anyway.
6019          */
6020         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6021         if (!conn_state)
6022                 return -ENOMEM;
6023
6024         __drm_atomic_helper_connector_reset(&connector->base,
6025                                             &conn_state->base);
6026
6027         return 0;
6028 }
6029
6030 struct intel_connector *intel_connector_alloc(void)
6031 {
6032         struct intel_connector *connector;
6033
6034         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6035         if (!connector)
6036                 return NULL;
6037
6038         if (intel_connector_init(connector) < 0) {
6039                 kfree(connector);
6040                 return NULL;
6041         }
6042
6043         return connector;
6044 }
6045
6046 /*
6047  * Free the bits allocated by intel_connector_alloc.
6048  * This should only be used after intel_connector_alloc has returned
6049  * successfully, and before drm_connector_init returns successfully.
6050  * Otherwise the destroy callbacks for the connector and the state should
6051  * take care of proper cleanup/free
6052  */
6053 void intel_connector_free(struct intel_connector *connector)
6054 {
6055         kfree(to_intel_digital_connector_state(connector->base.state));
6056         kfree(connector);
6057 }
6058
6059 /* Simple connector->get_hw_state implementation for encoders that support only
6060  * one connector and no cloning and hence the encoder state determines the state
6061  * of the connector. */
6062 bool intel_connector_get_hw_state(struct intel_connector *connector)
6063 {
6064         enum pipe pipe = 0;
6065         struct intel_encoder *encoder = connector->encoder;
6066
6067         return encoder->get_hw_state(encoder, &pipe);
6068 }
6069
6070 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6071 {
6072         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6073                 return crtc_state->fdi_lanes;
6074
6075         return 0;
6076 }
6077
6078 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6079                                      struct intel_crtc_state *pipe_config)
6080 {
6081         struct drm_i915_private *dev_priv = to_i915(dev);
6082         struct drm_atomic_state *state = pipe_config->base.state;
6083         struct intel_crtc *other_crtc;
6084         struct intel_crtc_state *other_crtc_state;
6085
6086         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6087                       pipe_name(pipe), pipe_config->fdi_lanes);
6088         if (pipe_config->fdi_lanes > 4) {
6089                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6090                               pipe_name(pipe), pipe_config->fdi_lanes);
6091                 return -EINVAL;
6092         }
6093
6094         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6095                 if (pipe_config->fdi_lanes > 2) {
6096                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6097                                       pipe_config->fdi_lanes);
6098                         return -EINVAL;
6099                 } else {
6100                         return 0;
6101                 }
6102         }
6103
6104         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6105                 return 0;
6106
6107         /* Ivybridge 3 pipe is really complicated */
6108         switch (pipe) {
6109         case PIPE_A:
6110                 return 0;
6111         case PIPE_B:
6112                 if (pipe_config->fdi_lanes <= 2)
6113                         return 0;
6114
6115                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6116                 other_crtc_state =
6117                         intel_atomic_get_crtc_state(state, other_crtc);
6118                 if (IS_ERR(other_crtc_state))
6119                         return PTR_ERR(other_crtc_state);
6120
6121                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6122                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6123                                       pipe_name(pipe), pipe_config->fdi_lanes);
6124                         return -EINVAL;
6125                 }
6126                 return 0;
6127         case PIPE_C:
6128                 if (pipe_config->fdi_lanes > 2) {
6129                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6130                                       pipe_name(pipe), pipe_config->fdi_lanes);
6131                         return -EINVAL;
6132                 }
6133
6134                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6135                 other_crtc_state =
6136                         intel_atomic_get_crtc_state(state, other_crtc);
6137                 if (IS_ERR(other_crtc_state))
6138                         return PTR_ERR(other_crtc_state);
6139
6140                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6141                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6142                         return -EINVAL;
6143                 }
6144                 return 0;
6145         default:
6146                 BUG();
6147         }
6148 }
6149
6150 #define RETRY 1
6151 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6152                                        struct intel_crtc_state *pipe_config)
6153 {
6154         struct drm_device *dev = intel_crtc->base.dev;
6155         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6156         int lane, link_bw, fdi_dotclock, ret;
6157         bool needs_recompute = false;
6158
6159 retry:
6160         /* FDI is a binary signal running at ~2.7GHz, encoding
6161          * each output octet as 10 bits. The actual frequency
6162          * is stored as a divider into a 100MHz clock, and the
6163          * mode pixel clock is stored in units of 1KHz.
6164          * Hence the bw of each lane in terms of the mode signal
6165          * is:
6166          */
6167         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6168
6169         fdi_dotclock = adjusted_mode->crtc_clock;
6170
6171         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6172                                            pipe_config->pipe_bpp);
6173
6174         pipe_config->fdi_lanes = lane;
6175
6176         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6177                                link_bw, &pipe_config->fdi_m_n, false);
6178
6179         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6180         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6181                 pipe_config->pipe_bpp -= 2*3;
6182                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6183                               pipe_config->pipe_bpp);
6184                 needs_recompute = true;
6185                 pipe_config->bw_constrained = true;
6186
6187                 goto retry;
6188         }
6189
6190         if (needs_recompute)
6191                 return RETRY;
6192
6193         return ret;
6194 }
6195
6196 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6197                                      struct intel_crtc_state *pipe_config)
6198 {
6199         if (pipe_config->ips_force_disable)
6200                 return false;
6201
6202         if (pipe_config->pipe_bpp > 24)
6203                 return false;
6204
6205         /* HSW can handle pixel rate up to cdclk? */
6206         if (IS_HASWELL(dev_priv))
6207                 return true;
6208
6209         /*
6210          * We compare against max which means we must take
6211          * the increased cdclk requirement into account when
6212          * calculating the new cdclk.
6213          *
6214          * Should measure whether using a lower cdclk w/o IPS
6215          */
6216         return pipe_config->pixel_rate <=
6217                 dev_priv->max_cdclk_freq * 95 / 100;
6218 }
6219
6220 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6221                                    struct intel_crtc_state *pipe_config)
6222 {
6223         struct drm_device *dev = crtc->base.dev;
6224         struct drm_i915_private *dev_priv = to_i915(dev);
6225
6226         pipe_config->ips_enabled = i915_modparams.enable_ips &&
6227                 hsw_crtc_supports_ips(crtc) &&
6228                 pipe_config_supports_ips(dev_priv, pipe_config);
6229 }
6230
6231 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6232 {
6233         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6234
6235         /* GDG double wide on either pipe, otherwise pipe A only */
6236         return INTEL_INFO(dev_priv)->gen < 4 &&
6237                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6238 }
6239
6240 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6241 {
6242         uint32_t pixel_rate;
6243
6244         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6245
6246         /*
6247          * We only use IF-ID interlacing. If we ever use
6248          * PF-ID we'll need to adjust the pixel_rate here.
6249          */
6250
6251         if (pipe_config->pch_pfit.enabled) {
6252                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6253                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6254
6255                 pipe_w = pipe_config->pipe_src_w;
6256                 pipe_h = pipe_config->pipe_src_h;
6257
6258                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6259                 pfit_h = pfit_size & 0xFFFF;
6260                 if (pipe_w < pfit_w)
6261                         pipe_w = pfit_w;
6262                 if (pipe_h < pfit_h)
6263                         pipe_h = pfit_h;
6264
6265                 if (WARN_ON(!pfit_w || !pfit_h))
6266                         return pixel_rate;
6267
6268                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6269                                      pfit_w * pfit_h);
6270         }
6271
6272         return pixel_rate;
6273 }
6274
6275 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6276 {
6277         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6278
6279         if (HAS_GMCH_DISPLAY(dev_priv))
6280                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6281                 crtc_state->pixel_rate =
6282                         crtc_state->base.adjusted_mode.crtc_clock;
6283         else
6284                 crtc_state->pixel_rate =
6285                         ilk_pipe_pixel_rate(crtc_state);
6286 }
6287
6288 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6289                                      struct intel_crtc_state *pipe_config)
6290 {
6291         struct drm_device *dev = crtc->base.dev;
6292         struct drm_i915_private *dev_priv = to_i915(dev);
6293         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6294         int clock_limit = dev_priv->max_dotclk_freq;
6295
6296         if (INTEL_GEN(dev_priv) < 4) {
6297                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6298
6299                 /*
6300                  * Enable double wide mode when the dot clock
6301                  * is > 90% of the (display) core speed.
6302                  */
6303                 if (intel_crtc_supports_double_wide(crtc) &&
6304                     adjusted_mode->crtc_clock > clock_limit) {
6305                         clock_limit = dev_priv->max_dotclk_freq;
6306                         pipe_config->double_wide = true;
6307                 }
6308         }
6309
6310         if (adjusted_mode->crtc_clock > clock_limit) {
6311                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6312                               adjusted_mode->crtc_clock, clock_limit,
6313                               yesno(pipe_config->double_wide));
6314                 return -EINVAL;
6315         }
6316
6317         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6318                 /*
6319                  * There is only one pipe CSC unit per pipe, and we need that
6320                  * for output conversion from RGB->YCBCR. So if CTM is already
6321                  * applied we can't support YCBCR420 output.
6322                  */
6323                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6324                 return -EINVAL;
6325         }
6326
6327         /*
6328          * Pipe horizontal size must be even in:
6329          * - DVO ganged mode
6330          * - LVDS dual channel mode
6331          * - Double wide pipe
6332          */
6333         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6334              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6335                 pipe_config->pipe_src_w &= ~1;
6336
6337         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6338          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6339          */
6340         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6341                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6342                 return -EINVAL;
6343
6344         intel_crtc_compute_pixel_rate(pipe_config);
6345
6346         if (HAS_IPS(dev_priv))
6347                 hsw_compute_ips_config(crtc, pipe_config);
6348
6349         if (pipe_config->has_pch_encoder)
6350                 return ironlake_fdi_compute_config(crtc, pipe_config);
6351
6352         return 0;
6353 }
6354
6355 static void
6356 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6357 {
6358         while (*num > DATA_LINK_M_N_MASK ||
6359                *den > DATA_LINK_M_N_MASK) {
6360                 *num >>= 1;
6361                 *den >>= 1;
6362         }
6363 }
6364
6365 static void compute_m_n(unsigned int m, unsigned int n,
6366                         uint32_t *ret_m, uint32_t *ret_n,
6367                         bool reduce_m_n)
6368 {
6369         /*
6370          * Reduce M/N as much as possible without loss in precision. Several DP
6371          * dongles in particular seem to be fussy about too large *link* M/N
6372          * values. The passed in values are more likely to have the least
6373          * significant bits zero than M after rounding below, so do this first.
6374          */
6375         if (reduce_m_n) {
6376                 while ((m & 1) == 0 && (n & 1) == 0) {
6377                         m >>= 1;
6378                         n >>= 1;
6379                 }
6380         }
6381
6382         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6383         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6384         intel_reduce_m_n_ratio(ret_m, ret_n);
6385 }
6386
6387 void
6388 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6389                        int pixel_clock, int link_clock,
6390                        struct intel_link_m_n *m_n,
6391                        bool reduce_m_n)
6392 {
6393         m_n->tu = 64;
6394
6395         compute_m_n(bits_per_pixel * pixel_clock,
6396                     link_clock * nlanes * 8,
6397                     &m_n->gmch_m, &m_n->gmch_n,
6398                     reduce_m_n);
6399
6400         compute_m_n(pixel_clock, link_clock,
6401                     &m_n->link_m, &m_n->link_n,
6402                     reduce_m_n);
6403 }
6404
6405 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6406 {
6407         if (i915_modparams.panel_use_ssc >= 0)
6408                 return i915_modparams.panel_use_ssc != 0;
6409         return dev_priv->vbt.lvds_use_ssc
6410                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6411 }
6412
6413 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6414 {
6415         return (1 << dpll->n) << 16 | dpll->m2;
6416 }
6417
6418 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6419 {
6420         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6421 }
6422
6423 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6424                                      struct intel_crtc_state *crtc_state,
6425                                      struct dpll *reduced_clock)
6426 {
6427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6428         u32 fp, fp2 = 0;
6429
6430         if (IS_PINEVIEW(dev_priv)) {
6431                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6432                 if (reduced_clock)
6433                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6434         } else {
6435                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6436                 if (reduced_clock)
6437                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6438         }
6439
6440         crtc_state->dpll_hw_state.fp0 = fp;
6441
6442         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6443             reduced_clock) {
6444                 crtc_state->dpll_hw_state.fp1 = fp2;
6445         } else {
6446                 crtc_state->dpll_hw_state.fp1 = fp;
6447         }
6448 }
6449
6450 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6451                 pipe)
6452 {
6453         u32 reg_val;
6454
6455         /*
6456          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6457          * and set it to a reasonable value instead.
6458          */
6459         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6460         reg_val &= 0xffffff00;
6461         reg_val |= 0x00000030;
6462         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6463
6464         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6465         reg_val &= 0x00ffffff;
6466         reg_val |= 0x8c000000;
6467         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6468
6469         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6470         reg_val &= 0xffffff00;
6471         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6472
6473         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6474         reg_val &= 0x00ffffff;
6475         reg_val |= 0xb0000000;
6476         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6477 }
6478
6479 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6480                                          struct intel_link_m_n *m_n)
6481 {
6482         struct drm_device *dev = crtc->base.dev;
6483         struct drm_i915_private *dev_priv = to_i915(dev);
6484         int pipe = crtc->pipe;
6485
6486         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6487         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6488         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6489         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6490 }
6491
6492 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6493                                          struct intel_link_m_n *m_n,
6494                                          struct intel_link_m_n *m2_n2)
6495 {
6496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6497         int pipe = crtc->pipe;
6498         enum transcoder transcoder = crtc->config->cpu_transcoder;
6499
6500         if (INTEL_GEN(dev_priv) >= 5) {
6501                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6502                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6503                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6504                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6505                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6506                  * for gen < 8) and if DRRS is supported (to make sure the
6507                  * registers are not unnecessarily accessed).
6508                  */
6509                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6510                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6511                         I915_WRITE(PIPE_DATA_M2(transcoder),
6512                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6513                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6514                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6515                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6516                 }
6517         } else {
6518                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6519                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6520                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6521                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6522         }
6523 }
6524
6525 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6526 {
6527         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6528
6529         if (m_n == M1_N1) {
6530                 dp_m_n = &crtc->config->dp_m_n;
6531                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6532         } else if (m_n == M2_N2) {
6533
6534                 /*
6535                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6536                  * needs to be programmed into M1_N1.
6537                  */
6538                 dp_m_n = &crtc->config->dp_m2_n2;
6539         } else {
6540                 DRM_ERROR("Unsupported divider value\n");
6541                 return;
6542         }
6543
6544         if (crtc->config->has_pch_encoder)
6545                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6546         else
6547                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6548 }
6549
6550 static void vlv_compute_dpll(struct intel_crtc *crtc,
6551                              struct intel_crtc_state *pipe_config)
6552 {
6553         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6554                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6555         if (crtc->pipe != PIPE_A)
6556                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6557
6558         /* DPLL not used with DSI, but still need the rest set up */
6559         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6560                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6561                         DPLL_EXT_BUFFER_ENABLE_VLV;
6562
6563         pipe_config->dpll_hw_state.dpll_md =
6564                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6565 }
6566
6567 static void chv_compute_dpll(struct intel_crtc *crtc,
6568                              struct intel_crtc_state *pipe_config)
6569 {
6570         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6571                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6572         if (crtc->pipe != PIPE_A)
6573                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6574
6575         /* DPLL not used with DSI, but still need the rest set up */
6576         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6577                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6578
6579         pipe_config->dpll_hw_state.dpll_md =
6580                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6581 }
6582
6583 static void vlv_prepare_pll(struct intel_crtc *crtc,
6584                             const struct intel_crtc_state *pipe_config)
6585 {
6586         struct drm_device *dev = crtc->base.dev;
6587         struct drm_i915_private *dev_priv = to_i915(dev);
6588         enum pipe pipe = crtc->pipe;
6589         u32 mdiv;
6590         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6591         u32 coreclk, reg_val;
6592
6593         /* Enable Refclk */
6594         I915_WRITE(DPLL(pipe),
6595                    pipe_config->dpll_hw_state.dpll &
6596                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6597
6598         /* No need to actually set up the DPLL with DSI */
6599         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6600                 return;
6601
6602         mutex_lock(&dev_priv->sb_lock);
6603
6604         bestn = pipe_config->dpll.n;
6605         bestm1 = pipe_config->dpll.m1;
6606         bestm2 = pipe_config->dpll.m2;
6607         bestp1 = pipe_config->dpll.p1;
6608         bestp2 = pipe_config->dpll.p2;
6609
6610         /* See eDP HDMI DPIO driver vbios notes doc */
6611
6612         /* PLL B needs special handling */
6613         if (pipe == PIPE_B)
6614                 vlv_pllb_recal_opamp(dev_priv, pipe);
6615
6616         /* Set up Tx target for periodic Rcomp update */
6617         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6618
6619         /* Disable target IRef on PLL */
6620         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6621         reg_val &= 0x00ffffff;
6622         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6623
6624         /* Disable fast lock */
6625         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6626
6627         /* Set idtafcrecal before PLL is enabled */
6628         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6629         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6630         mdiv |= ((bestn << DPIO_N_SHIFT));
6631         mdiv |= (1 << DPIO_K_SHIFT);
6632
6633         /*
6634          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6635          * but we don't support that).
6636          * Note: don't use the DAC post divider as it seems unstable.
6637          */
6638         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6639         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6640
6641         mdiv |= DPIO_ENABLE_CALIBRATION;
6642         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6643
6644         /* Set HBR and RBR LPF coefficients */
6645         if (pipe_config->port_clock == 162000 ||
6646             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6647             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6648                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6649                                  0x009f0003);
6650         else
6651                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6652                                  0x00d0000f);
6653
6654         if (intel_crtc_has_dp_encoder(pipe_config)) {
6655                 /* Use SSC source */
6656                 if (pipe == PIPE_A)
6657                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6658                                          0x0df40000);
6659                 else
6660                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6661                                          0x0df70000);
6662         } else { /* HDMI or VGA */
6663                 /* Use bend source */
6664                 if (pipe == PIPE_A)
6665                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6666                                          0x0df70000);
6667                 else
6668                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6669                                          0x0df40000);
6670         }
6671
6672         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6673         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6674         if (intel_crtc_has_dp_encoder(crtc->config))
6675                 coreclk |= 0x01000000;
6676         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6677
6678         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6679         mutex_unlock(&dev_priv->sb_lock);
6680 }
6681
6682 static void chv_prepare_pll(struct intel_crtc *crtc,
6683                             const struct intel_crtc_state *pipe_config)
6684 {
6685         struct drm_device *dev = crtc->base.dev;
6686         struct drm_i915_private *dev_priv = to_i915(dev);
6687         enum pipe pipe = crtc->pipe;
6688         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6689         u32 loopfilter, tribuf_calcntr;
6690         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6691         u32 dpio_val;
6692         int vco;
6693
6694         /* Enable Refclk and SSC */
6695         I915_WRITE(DPLL(pipe),
6696                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6697
6698         /* No need to actually set up the DPLL with DSI */
6699         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6700                 return;
6701
6702         bestn = pipe_config->dpll.n;
6703         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6704         bestm1 = pipe_config->dpll.m1;
6705         bestm2 = pipe_config->dpll.m2 >> 22;
6706         bestp1 = pipe_config->dpll.p1;
6707         bestp2 = pipe_config->dpll.p2;
6708         vco = pipe_config->dpll.vco;
6709         dpio_val = 0;
6710         loopfilter = 0;
6711
6712         mutex_lock(&dev_priv->sb_lock);
6713
6714         /* p1 and p2 divider */
6715         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6716                         5 << DPIO_CHV_S1_DIV_SHIFT |
6717                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6718                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6719                         1 << DPIO_CHV_K_DIV_SHIFT);
6720
6721         /* Feedback post-divider - m2 */
6722         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6723
6724         /* Feedback refclk divider - n and m1 */
6725         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6726                         DPIO_CHV_M1_DIV_BY_2 |
6727                         1 << DPIO_CHV_N_DIV_SHIFT);
6728
6729         /* M2 fraction division */
6730         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6731
6732         /* M2 fraction division enable */
6733         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6734         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6735         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6736         if (bestm2_frac)
6737                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6738         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6739
6740         /* Program digital lock detect threshold */
6741         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6742         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6743                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6744         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6745         if (!bestm2_frac)
6746                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6747         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6748
6749         /* Loop filter */
6750         if (vco == 5400000) {
6751                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6752                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6753                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6754                 tribuf_calcntr = 0x9;
6755         } else if (vco <= 6200000) {
6756                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6757                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6758                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6759                 tribuf_calcntr = 0x9;
6760         } else if (vco <= 6480000) {
6761                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6762                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6763                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6764                 tribuf_calcntr = 0x8;
6765         } else {
6766                 /* Not supported. Apply the same limits as in the max case */
6767                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6768                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6769                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6770                 tribuf_calcntr = 0;
6771         }
6772         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6773
6774         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6775         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6776         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6777         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6778
6779         /* AFC Recal */
6780         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6781                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6782                         DPIO_AFC_RECAL);
6783
6784         mutex_unlock(&dev_priv->sb_lock);
6785 }
6786
6787 /**
6788  * vlv_force_pll_on - forcibly enable just the PLL
6789  * @dev_priv: i915 private structure
6790  * @pipe: pipe PLL to enable
6791  * @dpll: PLL configuration
6792  *
6793  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6794  * in cases where we need the PLL enabled even when @pipe is not going to
6795  * be enabled.
6796  */
6797 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6798                      const struct dpll *dpll)
6799 {
6800         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6801         struct intel_crtc_state *pipe_config;
6802
6803         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6804         if (!pipe_config)
6805                 return -ENOMEM;
6806
6807         pipe_config->base.crtc = &crtc->base;
6808         pipe_config->pixel_multiplier = 1;
6809         pipe_config->dpll = *dpll;
6810
6811         if (IS_CHERRYVIEW(dev_priv)) {
6812                 chv_compute_dpll(crtc, pipe_config);
6813                 chv_prepare_pll(crtc, pipe_config);
6814                 chv_enable_pll(crtc, pipe_config);
6815         } else {
6816                 vlv_compute_dpll(crtc, pipe_config);
6817                 vlv_prepare_pll(crtc, pipe_config);
6818                 vlv_enable_pll(crtc, pipe_config);
6819         }
6820
6821         kfree(pipe_config);
6822
6823         return 0;
6824 }
6825
6826 /**
6827  * vlv_force_pll_off - forcibly disable just the PLL
6828  * @dev_priv: i915 private structure
6829  * @pipe: pipe PLL to disable
6830  *
6831  * Disable the PLL for @pipe. To be used in cases where we need
6832  * the PLL enabled even when @pipe is not going to be enabled.
6833  */
6834 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6835 {
6836         if (IS_CHERRYVIEW(dev_priv))
6837                 chv_disable_pll(dev_priv, pipe);
6838         else
6839                 vlv_disable_pll(dev_priv, pipe);
6840 }
6841
6842 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6843                               struct intel_crtc_state *crtc_state,
6844                               struct dpll *reduced_clock)
6845 {
6846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6847         u32 dpll;
6848         struct dpll *clock = &crtc_state->dpll;
6849
6850         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6851
6852         dpll = DPLL_VGA_MODE_DIS;
6853
6854         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6855                 dpll |= DPLLB_MODE_LVDS;
6856         else
6857                 dpll |= DPLLB_MODE_DAC_SERIAL;
6858
6859         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6860             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6861                 dpll |= (crtc_state->pixel_multiplier - 1)
6862                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6863         }
6864
6865         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6866             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6867                 dpll |= DPLL_SDVO_HIGH_SPEED;
6868
6869         if (intel_crtc_has_dp_encoder(crtc_state))
6870                 dpll |= DPLL_SDVO_HIGH_SPEED;
6871
6872         /* compute bitmask from p1 value */
6873         if (IS_PINEVIEW(dev_priv))
6874                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6875         else {
6876                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6877                 if (IS_G4X(dev_priv) && reduced_clock)
6878                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6879         }
6880         switch (clock->p2) {
6881         case 5:
6882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6883                 break;
6884         case 7:
6885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6886                 break;
6887         case 10:
6888                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6889                 break;
6890         case 14:
6891                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6892                 break;
6893         }
6894         if (INTEL_GEN(dev_priv) >= 4)
6895                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6896
6897         if (crtc_state->sdvo_tv_clock)
6898                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6899         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6900                  intel_panel_use_ssc(dev_priv))
6901                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6902         else
6903                 dpll |= PLL_REF_INPUT_DREFCLK;
6904
6905         dpll |= DPLL_VCO_ENABLE;
6906         crtc_state->dpll_hw_state.dpll = dpll;
6907
6908         if (INTEL_GEN(dev_priv) >= 4) {
6909                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6910                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6911                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6912         }
6913 }
6914
6915 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6916                               struct intel_crtc_state *crtc_state,
6917                               struct dpll *reduced_clock)
6918 {
6919         struct drm_device *dev = crtc->base.dev;
6920         struct drm_i915_private *dev_priv = to_i915(dev);
6921         u32 dpll;
6922         struct dpll *clock = &crtc_state->dpll;
6923
6924         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6925
6926         dpll = DPLL_VGA_MODE_DIS;
6927
6928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6929                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6930         } else {
6931                 if (clock->p1 == 2)
6932                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6933                 else
6934                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6935                 if (clock->p2 == 4)
6936                         dpll |= PLL_P2_DIVIDE_BY_4;
6937         }
6938
6939         if (!IS_I830(dev_priv) &&
6940             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6941                 dpll |= DPLL_DVO_2X_MODE;
6942
6943         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6944             intel_panel_use_ssc(dev_priv))
6945                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6946         else
6947                 dpll |= PLL_REF_INPUT_DREFCLK;
6948
6949         dpll |= DPLL_VCO_ENABLE;
6950         crtc_state->dpll_hw_state.dpll = dpll;
6951 }
6952
6953 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6954 {
6955         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6956         enum pipe pipe = intel_crtc->pipe;
6957         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6958         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6959         uint32_t crtc_vtotal, crtc_vblank_end;
6960         int vsyncshift = 0;
6961
6962         /* We need to be careful not to changed the adjusted mode, for otherwise
6963          * the hw state checker will get angry at the mismatch. */
6964         crtc_vtotal = adjusted_mode->crtc_vtotal;
6965         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6966
6967         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6968                 /* the chip adds 2 halflines automatically */
6969                 crtc_vtotal -= 1;
6970                 crtc_vblank_end -= 1;
6971
6972                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6973                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6974                 else
6975                         vsyncshift = adjusted_mode->crtc_hsync_start -
6976                                 adjusted_mode->crtc_htotal / 2;
6977                 if (vsyncshift < 0)
6978                         vsyncshift += adjusted_mode->crtc_htotal;
6979         }
6980
6981         if (INTEL_GEN(dev_priv) > 3)
6982                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6983
6984         I915_WRITE(HTOTAL(cpu_transcoder),
6985                    (adjusted_mode->crtc_hdisplay - 1) |
6986                    ((adjusted_mode->crtc_htotal - 1) << 16));
6987         I915_WRITE(HBLANK(cpu_transcoder),
6988                    (adjusted_mode->crtc_hblank_start - 1) |
6989                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6990         I915_WRITE(HSYNC(cpu_transcoder),
6991                    (adjusted_mode->crtc_hsync_start - 1) |
6992                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6993
6994         I915_WRITE(VTOTAL(cpu_transcoder),
6995                    (adjusted_mode->crtc_vdisplay - 1) |
6996                    ((crtc_vtotal - 1) << 16));
6997         I915_WRITE(VBLANK(cpu_transcoder),
6998                    (adjusted_mode->crtc_vblank_start - 1) |
6999                    ((crtc_vblank_end - 1) << 16));
7000         I915_WRITE(VSYNC(cpu_transcoder),
7001                    (adjusted_mode->crtc_vsync_start - 1) |
7002                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7003
7004         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7005          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7006          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7007          * bits. */
7008         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7009             (pipe == PIPE_B || pipe == PIPE_C))
7010                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7011
7012 }
7013
7014 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7015 {
7016         struct drm_device *dev = intel_crtc->base.dev;
7017         struct drm_i915_private *dev_priv = to_i915(dev);
7018         enum pipe pipe = intel_crtc->pipe;
7019
7020         /* pipesrc controls the size that is scaled from, which should
7021          * always be the user's requested size.
7022          */
7023         I915_WRITE(PIPESRC(pipe),
7024                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7025                    (intel_crtc->config->pipe_src_h - 1));
7026 }
7027
7028 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7029                                    struct intel_crtc_state *pipe_config)
7030 {
7031         struct drm_device *dev = crtc->base.dev;
7032         struct drm_i915_private *dev_priv = to_i915(dev);
7033         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7034         uint32_t tmp;
7035
7036         tmp = I915_READ(HTOTAL(cpu_transcoder));
7037         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7038         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7039         tmp = I915_READ(HBLANK(cpu_transcoder));
7040         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7041         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7042         tmp = I915_READ(HSYNC(cpu_transcoder));
7043         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7044         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7045
7046         tmp = I915_READ(VTOTAL(cpu_transcoder));
7047         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7048         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7049         tmp = I915_READ(VBLANK(cpu_transcoder));
7050         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7051         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7052         tmp = I915_READ(VSYNC(cpu_transcoder));
7053         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7054         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7055
7056         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7057                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7058                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7059                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7060         }
7061 }
7062
7063 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7064                                     struct intel_crtc_state *pipe_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = to_i915(dev);
7068         u32 tmp;
7069
7070         tmp = I915_READ(PIPESRC(crtc->pipe));
7071         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7072         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7073
7074         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7075         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7076 }
7077
7078 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7079                                  struct intel_crtc_state *pipe_config)
7080 {
7081         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7082         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7083         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7084         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7085
7086         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7087         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7088         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7089         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7090
7091         mode->flags = pipe_config->base.adjusted_mode.flags;
7092         mode->type = DRM_MODE_TYPE_DRIVER;
7093
7094         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7095
7096         mode->hsync = drm_mode_hsync(mode);
7097         mode->vrefresh = drm_mode_vrefresh(mode);
7098         drm_mode_set_name(mode);
7099 }
7100
7101 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7102 {
7103         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7104         uint32_t pipeconf;
7105
7106         pipeconf = 0;
7107
7108         /* we keep both pipes enabled on 830 */
7109         if (IS_I830(dev_priv))
7110                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7111
7112         if (intel_crtc->config->double_wide)
7113                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7114
7115         /* only g4x and later have fancy bpc/dither controls */
7116         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7117             IS_CHERRYVIEW(dev_priv)) {
7118                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7119                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7120                         pipeconf |= PIPECONF_DITHER_EN |
7121                                     PIPECONF_DITHER_TYPE_SP;
7122
7123                 switch (intel_crtc->config->pipe_bpp) {
7124                 case 18:
7125                         pipeconf |= PIPECONF_6BPC;
7126                         break;
7127                 case 24:
7128                         pipeconf |= PIPECONF_8BPC;
7129                         break;
7130                 case 30:
7131                         pipeconf |= PIPECONF_10BPC;
7132                         break;
7133                 default:
7134                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7135                         BUG();
7136                 }
7137         }
7138
7139         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7140                 if (INTEL_GEN(dev_priv) < 4 ||
7141                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7142                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7143                 else
7144                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7145         } else
7146                 pipeconf |= PIPECONF_PROGRESSIVE;
7147
7148         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7149              intel_crtc->config->limited_color_range)
7150                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7151
7152         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7153         POSTING_READ(PIPECONF(intel_crtc->pipe));
7154 }
7155
7156 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7157                                    struct intel_crtc_state *crtc_state)
7158 {
7159         struct drm_device *dev = crtc->base.dev;
7160         struct drm_i915_private *dev_priv = to_i915(dev);
7161         const struct intel_limit *limit;
7162         int refclk = 48000;
7163
7164         memset(&crtc_state->dpll_hw_state, 0,
7165                sizeof(crtc_state->dpll_hw_state));
7166
7167         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7168                 if (intel_panel_use_ssc(dev_priv)) {
7169                         refclk = dev_priv->vbt.lvds_ssc_freq;
7170                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7171                 }
7172
7173                 limit = &intel_limits_i8xx_lvds;
7174         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7175                 limit = &intel_limits_i8xx_dvo;
7176         } else {
7177                 limit = &intel_limits_i8xx_dac;
7178         }
7179
7180         if (!crtc_state->clock_set &&
7181             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7182                                  refclk, NULL, &crtc_state->dpll)) {
7183                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7184                 return -EINVAL;
7185         }
7186
7187         i8xx_compute_dpll(crtc, crtc_state, NULL);
7188
7189         return 0;
7190 }
7191
7192 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7193                                   struct intel_crtc_state *crtc_state)
7194 {
7195         struct drm_device *dev = crtc->base.dev;
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         const struct intel_limit *limit;
7198         int refclk = 96000;
7199
7200         memset(&crtc_state->dpll_hw_state, 0,
7201                sizeof(crtc_state->dpll_hw_state));
7202
7203         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7204                 if (intel_panel_use_ssc(dev_priv)) {
7205                         refclk = dev_priv->vbt.lvds_ssc_freq;
7206                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7207                 }
7208
7209                 if (intel_is_dual_link_lvds(dev))
7210                         limit = &intel_limits_g4x_dual_channel_lvds;
7211                 else
7212                         limit = &intel_limits_g4x_single_channel_lvds;
7213         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7214                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7215                 limit = &intel_limits_g4x_hdmi;
7216         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7217                 limit = &intel_limits_g4x_sdvo;
7218         } else {
7219                 /* The option is for other outputs */
7220                 limit = &intel_limits_i9xx_sdvo;
7221         }
7222
7223         if (!crtc_state->clock_set &&
7224             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7225                                 refclk, NULL, &crtc_state->dpll)) {
7226                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7227                 return -EINVAL;
7228         }
7229
7230         i9xx_compute_dpll(crtc, crtc_state, NULL);
7231
7232         return 0;
7233 }
7234
7235 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7236                                   struct intel_crtc_state *crtc_state)
7237 {
7238         struct drm_device *dev = crtc->base.dev;
7239         struct drm_i915_private *dev_priv = to_i915(dev);
7240         const struct intel_limit *limit;
7241         int refclk = 96000;
7242
7243         memset(&crtc_state->dpll_hw_state, 0,
7244                sizeof(crtc_state->dpll_hw_state));
7245
7246         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7247                 if (intel_panel_use_ssc(dev_priv)) {
7248                         refclk = dev_priv->vbt.lvds_ssc_freq;
7249                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7250                 }
7251
7252                 limit = &intel_limits_pineview_lvds;
7253         } else {
7254                 limit = &intel_limits_pineview_sdvo;
7255         }
7256
7257         if (!crtc_state->clock_set &&
7258             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7259                                 refclk, NULL, &crtc_state->dpll)) {
7260                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7261                 return -EINVAL;
7262         }
7263
7264         i9xx_compute_dpll(crtc, crtc_state, NULL);
7265
7266         return 0;
7267 }
7268
7269 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7270                                    struct intel_crtc_state *crtc_state)
7271 {
7272         struct drm_device *dev = crtc->base.dev;
7273         struct drm_i915_private *dev_priv = to_i915(dev);
7274         const struct intel_limit *limit;
7275         int refclk = 96000;
7276
7277         memset(&crtc_state->dpll_hw_state, 0,
7278                sizeof(crtc_state->dpll_hw_state));
7279
7280         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7281                 if (intel_panel_use_ssc(dev_priv)) {
7282                         refclk = dev_priv->vbt.lvds_ssc_freq;
7283                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7284                 }
7285
7286                 limit = &intel_limits_i9xx_lvds;
7287         } else {
7288                 limit = &intel_limits_i9xx_sdvo;
7289         }
7290
7291         if (!crtc_state->clock_set &&
7292             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7293                                  refclk, NULL, &crtc_state->dpll)) {
7294                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7295                 return -EINVAL;
7296         }
7297
7298         i9xx_compute_dpll(crtc, crtc_state, NULL);
7299
7300         return 0;
7301 }
7302
7303 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7304                                   struct intel_crtc_state *crtc_state)
7305 {
7306         int refclk = 100000;
7307         const struct intel_limit *limit = &intel_limits_chv;
7308
7309         memset(&crtc_state->dpll_hw_state, 0,
7310                sizeof(crtc_state->dpll_hw_state));
7311
7312         if (!crtc_state->clock_set &&
7313             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7314                                 refclk, NULL, &crtc_state->dpll)) {
7315                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7316                 return -EINVAL;
7317         }
7318
7319         chv_compute_dpll(crtc, crtc_state);
7320
7321         return 0;
7322 }
7323
7324 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7325                                   struct intel_crtc_state *crtc_state)
7326 {
7327         int refclk = 100000;
7328         const struct intel_limit *limit = &intel_limits_vlv;
7329
7330         memset(&crtc_state->dpll_hw_state, 0,
7331                sizeof(crtc_state->dpll_hw_state));
7332
7333         if (!crtc_state->clock_set &&
7334             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7335                                 refclk, NULL, &crtc_state->dpll)) {
7336                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7337                 return -EINVAL;
7338         }
7339
7340         vlv_compute_dpll(crtc, crtc_state);
7341
7342         return 0;
7343 }
7344
7345 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7346                                  struct intel_crtc_state *pipe_config)
7347 {
7348         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7349         uint32_t tmp;
7350
7351         if (INTEL_GEN(dev_priv) <= 3 &&
7352             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7353                 return;
7354
7355         tmp = I915_READ(PFIT_CONTROL);
7356         if (!(tmp & PFIT_ENABLE))
7357                 return;
7358
7359         /* Check whether the pfit is attached to our pipe. */
7360         if (INTEL_GEN(dev_priv) < 4) {
7361                 if (crtc->pipe != PIPE_B)
7362                         return;
7363         } else {
7364                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7365                         return;
7366         }
7367
7368         pipe_config->gmch_pfit.control = tmp;
7369         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7370 }
7371
7372 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7373                                struct intel_crtc_state *pipe_config)
7374 {
7375         struct drm_device *dev = crtc->base.dev;
7376         struct drm_i915_private *dev_priv = to_i915(dev);
7377         int pipe = pipe_config->cpu_transcoder;
7378         struct dpll clock;
7379         u32 mdiv;
7380         int refclk = 100000;
7381
7382         /* In case of DSI, DPLL will not be used */
7383         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7384                 return;
7385
7386         mutex_lock(&dev_priv->sb_lock);
7387         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7388         mutex_unlock(&dev_priv->sb_lock);
7389
7390         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7391         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7392         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7393         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7394         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7395
7396         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7397 }
7398
7399 static void
7400 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7401                               struct intel_initial_plane_config *plane_config)
7402 {
7403         struct drm_device *dev = crtc->base.dev;
7404         struct drm_i915_private *dev_priv = to_i915(dev);
7405         u32 val, base, offset;
7406         int pipe = crtc->pipe, plane = crtc->plane;
7407         int fourcc, pixel_format;
7408         unsigned int aligned_height;
7409         struct drm_framebuffer *fb;
7410         struct intel_framebuffer *intel_fb;
7411
7412         val = I915_READ(DSPCNTR(plane));
7413         if (!(val & DISPLAY_PLANE_ENABLE))
7414                 return;
7415
7416         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7417         if (!intel_fb) {
7418                 DRM_DEBUG_KMS("failed to alloc fb\n");
7419                 return;
7420         }
7421
7422         fb = &intel_fb->base;
7423
7424         fb->dev = dev;
7425
7426         if (INTEL_GEN(dev_priv) >= 4) {
7427                 if (val & DISPPLANE_TILED) {
7428                         plane_config->tiling = I915_TILING_X;
7429                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7430                 }
7431         }
7432
7433         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7434         fourcc = i9xx_format_to_fourcc(pixel_format);
7435         fb->format = drm_format_info(fourcc);
7436
7437         if (INTEL_GEN(dev_priv) >= 4) {
7438                 if (plane_config->tiling)
7439                         offset = I915_READ(DSPTILEOFF(plane));
7440                 else
7441                         offset = I915_READ(DSPLINOFF(plane));
7442                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7443         } else {
7444                 base = I915_READ(DSPADDR(plane));
7445         }
7446         plane_config->base = base;
7447
7448         val = I915_READ(PIPESRC(pipe));
7449         fb->width = ((val >> 16) & 0xfff) + 1;
7450         fb->height = ((val >> 0) & 0xfff) + 1;
7451
7452         val = I915_READ(DSPSTRIDE(pipe));
7453         fb->pitches[0] = val & 0xffffffc0;
7454
7455         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7456
7457         plane_config->size = fb->pitches[0] * aligned_height;
7458
7459         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7460                       pipe_name(pipe), plane, fb->width, fb->height,
7461                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7462                       plane_config->size);
7463
7464         plane_config->fb = intel_fb;
7465 }
7466
7467 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7468                                struct intel_crtc_state *pipe_config)
7469 {
7470         struct drm_device *dev = crtc->base.dev;
7471         struct drm_i915_private *dev_priv = to_i915(dev);
7472         int pipe = pipe_config->cpu_transcoder;
7473         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7474         struct dpll clock;
7475         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7476         int refclk = 100000;
7477
7478         /* In case of DSI, DPLL will not be used */
7479         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7480                 return;
7481
7482         mutex_lock(&dev_priv->sb_lock);
7483         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7484         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7485         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7486         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7487         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7488         mutex_unlock(&dev_priv->sb_lock);
7489
7490         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7491         clock.m2 = (pll_dw0 & 0xff) << 22;
7492         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7493                 clock.m2 |= pll_dw2 & 0x3fffff;
7494         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7495         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7496         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7497
7498         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7499 }
7500
7501 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7502                                  struct intel_crtc_state *pipe_config)
7503 {
7504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7505         enum intel_display_power_domain power_domain;
7506         uint32_t tmp;
7507         bool ret;
7508
7509         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7510         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7511                 return false;
7512
7513         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7514         pipe_config->shared_dpll = NULL;
7515
7516         ret = false;
7517
7518         tmp = I915_READ(PIPECONF(crtc->pipe));
7519         if (!(tmp & PIPECONF_ENABLE))
7520                 goto out;
7521
7522         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7523             IS_CHERRYVIEW(dev_priv)) {
7524                 switch (tmp & PIPECONF_BPC_MASK) {
7525                 case PIPECONF_6BPC:
7526                         pipe_config->pipe_bpp = 18;
7527                         break;
7528                 case PIPECONF_8BPC:
7529                         pipe_config->pipe_bpp = 24;
7530                         break;
7531                 case PIPECONF_10BPC:
7532                         pipe_config->pipe_bpp = 30;
7533                         break;
7534                 default:
7535                         break;
7536                 }
7537         }
7538
7539         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7540             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7541                 pipe_config->limited_color_range = true;
7542
7543         if (INTEL_GEN(dev_priv) < 4)
7544                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7545
7546         intel_get_pipe_timings(crtc, pipe_config);
7547         intel_get_pipe_src_size(crtc, pipe_config);
7548
7549         i9xx_get_pfit_config(crtc, pipe_config);
7550
7551         if (INTEL_GEN(dev_priv) >= 4) {
7552                 /* No way to read it out on pipes B and C */
7553                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7554                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7555                 else
7556                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7557                 pipe_config->pixel_multiplier =
7558                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7559                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7560                 pipe_config->dpll_hw_state.dpll_md = tmp;
7561         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7562                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7563                 tmp = I915_READ(DPLL(crtc->pipe));
7564                 pipe_config->pixel_multiplier =
7565                         ((tmp & SDVO_MULTIPLIER_MASK)
7566                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7567         } else {
7568                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7569                  * port and will be fixed up in the encoder->get_config
7570                  * function. */
7571                 pipe_config->pixel_multiplier = 1;
7572         }
7573         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7574         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7575                 /*
7576                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7577                  * on 830. Filter it out here so that we don't
7578                  * report errors due to that.
7579                  */
7580                 if (IS_I830(dev_priv))
7581                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7582
7583                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7584                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7585         } else {
7586                 /* Mask out read-only status bits. */
7587                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7588                                                      DPLL_PORTC_READY_MASK |
7589                                                      DPLL_PORTB_READY_MASK);
7590         }
7591
7592         if (IS_CHERRYVIEW(dev_priv))
7593                 chv_crtc_clock_get(crtc, pipe_config);
7594         else if (IS_VALLEYVIEW(dev_priv))
7595                 vlv_crtc_clock_get(crtc, pipe_config);
7596         else
7597                 i9xx_crtc_clock_get(crtc, pipe_config);
7598
7599         /*
7600          * Normally the dotclock is filled in by the encoder .get_config()
7601          * but in case the pipe is enabled w/o any ports we need a sane
7602          * default.
7603          */
7604         pipe_config->base.adjusted_mode.crtc_clock =
7605                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7606
7607         ret = true;
7608
7609 out:
7610         intel_display_power_put(dev_priv, power_domain);
7611
7612         return ret;
7613 }
7614
7615 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7616 {
7617         struct intel_encoder *encoder;
7618         int i;
7619         u32 val, final;
7620         bool has_lvds = false;
7621         bool has_cpu_edp = false;
7622         bool has_panel = false;
7623         bool has_ck505 = false;
7624         bool can_ssc = false;
7625         bool using_ssc_source = false;
7626
7627         /* We need to take the global config into account */
7628         for_each_intel_encoder(&dev_priv->drm, encoder) {
7629                 switch (encoder->type) {
7630                 case INTEL_OUTPUT_LVDS:
7631                         has_panel = true;
7632                         has_lvds = true;
7633                         break;
7634                 case INTEL_OUTPUT_EDP:
7635                         has_panel = true;
7636                         if (encoder->port == PORT_A)
7637                                 has_cpu_edp = true;
7638                         break;
7639                 default:
7640                         break;
7641                 }
7642         }
7643
7644         if (HAS_PCH_IBX(dev_priv)) {
7645                 has_ck505 = dev_priv->vbt.display_clock_mode;
7646                 can_ssc = has_ck505;
7647         } else {
7648                 has_ck505 = false;
7649                 can_ssc = true;
7650         }
7651
7652         /* Check if any DPLLs are using the SSC source */
7653         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7654                 u32 temp = I915_READ(PCH_DPLL(i));
7655
7656                 if (!(temp & DPLL_VCO_ENABLE))
7657                         continue;
7658
7659                 if ((temp & PLL_REF_INPUT_MASK) ==
7660                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7661                         using_ssc_source = true;
7662                         break;
7663                 }
7664         }
7665
7666         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7667                       has_panel, has_lvds, has_ck505, using_ssc_source);
7668
7669         /* Ironlake: try to setup display ref clock before DPLL
7670          * enabling. This is only under driver's control after
7671          * PCH B stepping, previous chipset stepping should be
7672          * ignoring this setting.
7673          */
7674         val = I915_READ(PCH_DREF_CONTROL);
7675
7676         /* As we must carefully and slowly disable/enable each source in turn,
7677          * compute the final state we want first and check if we need to
7678          * make any changes at all.
7679          */
7680         final = val;
7681         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7682         if (has_ck505)
7683                 final |= DREF_NONSPREAD_CK505_ENABLE;
7684         else
7685                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7686
7687         final &= ~DREF_SSC_SOURCE_MASK;
7688         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7689         final &= ~DREF_SSC1_ENABLE;
7690
7691         if (has_panel) {
7692                 final |= DREF_SSC_SOURCE_ENABLE;
7693
7694                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7695                         final |= DREF_SSC1_ENABLE;
7696
7697                 if (has_cpu_edp) {
7698                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7699                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7700                         else
7701                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7702                 } else
7703                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7704         } else if (using_ssc_source) {
7705                 final |= DREF_SSC_SOURCE_ENABLE;
7706                 final |= DREF_SSC1_ENABLE;
7707         }
7708
7709         if (final == val)
7710                 return;
7711
7712         /* Always enable nonspread source */
7713         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7714
7715         if (has_ck505)
7716                 val |= DREF_NONSPREAD_CK505_ENABLE;
7717         else
7718                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7719
7720         if (has_panel) {
7721                 val &= ~DREF_SSC_SOURCE_MASK;
7722                 val |= DREF_SSC_SOURCE_ENABLE;
7723
7724                 /* SSC must be turned on before enabling the CPU output  */
7725                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7726                         DRM_DEBUG_KMS("Using SSC on panel\n");
7727                         val |= DREF_SSC1_ENABLE;
7728                 } else
7729                         val &= ~DREF_SSC1_ENABLE;
7730
7731                 /* Get SSC going before enabling the outputs */
7732                 I915_WRITE(PCH_DREF_CONTROL, val);
7733                 POSTING_READ(PCH_DREF_CONTROL);
7734                 udelay(200);
7735
7736                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7737
7738                 /* Enable CPU source on CPU attached eDP */
7739                 if (has_cpu_edp) {
7740                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7741                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7742                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7743                         } else
7744                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7745                 } else
7746                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7747
7748                 I915_WRITE(PCH_DREF_CONTROL, val);
7749                 POSTING_READ(PCH_DREF_CONTROL);
7750                 udelay(200);
7751         } else {
7752                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7753
7754                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7755
7756                 /* Turn off CPU output */
7757                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7758
7759                 I915_WRITE(PCH_DREF_CONTROL, val);
7760                 POSTING_READ(PCH_DREF_CONTROL);
7761                 udelay(200);
7762
7763                 if (!using_ssc_source) {
7764                         DRM_DEBUG_KMS("Disabling SSC source\n");
7765
7766                         /* Turn off the SSC source */
7767                         val &= ~DREF_SSC_SOURCE_MASK;
7768                         val |= DREF_SSC_SOURCE_DISABLE;
7769
7770                         /* Turn off SSC1 */
7771                         val &= ~DREF_SSC1_ENABLE;
7772
7773                         I915_WRITE(PCH_DREF_CONTROL, val);
7774                         POSTING_READ(PCH_DREF_CONTROL);
7775                         udelay(200);
7776                 }
7777         }
7778
7779         BUG_ON(val != final);
7780 }
7781
7782 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7783 {
7784         uint32_t tmp;
7785
7786         tmp = I915_READ(SOUTH_CHICKEN2);
7787         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7788         I915_WRITE(SOUTH_CHICKEN2, tmp);
7789
7790         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7791                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7792                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7793
7794         tmp = I915_READ(SOUTH_CHICKEN2);
7795         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7796         I915_WRITE(SOUTH_CHICKEN2, tmp);
7797
7798         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7799                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7800                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7801 }
7802
7803 /* WaMPhyProgramming:hsw */
7804 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7805 {
7806         uint32_t tmp;
7807
7808         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7809         tmp &= ~(0xFF << 24);
7810         tmp |= (0x12 << 24);
7811         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7812
7813         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7814         tmp |= (1 << 11);
7815         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7816
7817         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7818         tmp |= (1 << 11);
7819         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7820
7821         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7822         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7823         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7824
7825         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7826         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7827         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7828
7829         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7830         tmp &= ~(7 << 13);
7831         tmp |= (5 << 13);
7832         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7833
7834         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7835         tmp &= ~(7 << 13);
7836         tmp |= (5 << 13);
7837         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7838
7839         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7840         tmp &= ~0xFF;
7841         tmp |= 0x1C;
7842         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7843
7844         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7845         tmp &= ~0xFF;
7846         tmp |= 0x1C;
7847         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7848
7849         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7850         tmp &= ~(0xFF << 16);
7851         tmp |= (0x1C << 16);
7852         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7853
7854         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7855         tmp &= ~(0xFF << 16);
7856         tmp |= (0x1C << 16);
7857         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7858
7859         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7860         tmp |= (1 << 27);
7861         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7862
7863         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7864         tmp |= (1 << 27);
7865         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7866
7867         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7868         tmp &= ~(0xF << 28);
7869         tmp |= (4 << 28);
7870         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7871
7872         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7873         tmp &= ~(0xF << 28);
7874         tmp |= (4 << 28);
7875         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7876 }
7877
7878 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7879  * Programming" based on the parameters passed:
7880  * - Sequence to enable CLKOUT_DP
7881  * - Sequence to enable CLKOUT_DP without spread
7882  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7883  */
7884 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7885                                  bool with_spread, bool with_fdi)
7886 {
7887         uint32_t reg, tmp;
7888
7889         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7890                 with_spread = true;
7891         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7892             with_fdi, "LP PCH doesn't have FDI\n"))
7893                 with_fdi = false;
7894
7895         mutex_lock(&dev_priv->sb_lock);
7896
7897         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7898         tmp &= ~SBI_SSCCTL_DISABLE;
7899         tmp |= SBI_SSCCTL_PATHALT;
7900         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7901
7902         udelay(24);
7903
7904         if (with_spread) {
7905                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7906                 tmp &= ~SBI_SSCCTL_PATHALT;
7907                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7908
7909                 if (with_fdi) {
7910                         lpt_reset_fdi_mphy(dev_priv);
7911                         lpt_program_fdi_mphy(dev_priv);
7912                 }
7913         }
7914
7915         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7916         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7917         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7918         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7919
7920         mutex_unlock(&dev_priv->sb_lock);
7921 }
7922
7923 /* Sequence to disable CLKOUT_DP */
7924 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7925 {
7926         uint32_t reg, tmp;
7927
7928         mutex_lock(&dev_priv->sb_lock);
7929
7930         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7931         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7932         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7933         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7934
7935         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7936         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7937                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7938                         tmp |= SBI_SSCCTL_PATHALT;
7939                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7940                         udelay(32);
7941                 }
7942                 tmp |= SBI_SSCCTL_DISABLE;
7943                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7944         }
7945
7946         mutex_unlock(&dev_priv->sb_lock);
7947 }
7948
7949 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7950
7951 static const uint16_t sscdivintphase[] = {
7952         [BEND_IDX( 50)] = 0x3B23,
7953         [BEND_IDX( 45)] = 0x3B23,
7954         [BEND_IDX( 40)] = 0x3C23,
7955         [BEND_IDX( 35)] = 0x3C23,
7956         [BEND_IDX( 30)] = 0x3D23,
7957         [BEND_IDX( 25)] = 0x3D23,
7958         [BEND_IDX( 20)] = 0x3E23,
7959         [BEND_IDX( 15)] = 0x3E23,
7960         [BEND_IDX( 10)] = 0x3F23,
7961         [BEND_IDX(  5)] = 0x3F23,
7962         [BEND_IDX(  0)] = 0x0025,
7963         [BEND_IDX( -5)] = 0x0025,
7964         [BEND_IDX(-10)] = 0x0125,
7965         [BEND_IDX(-15)] = 0x0125,
7966         [BEND_IDX(-20)] = 0x0225,
7967         [BEND_IDX(-25)] = 0x0225,
7968         [BEND_IDX(-30)] = 0x0325,
7969         [BEND_IDX(-35)] = 0x0325,
7970         [BEND_IDX(-40)] = 0x0425,
7971         [BEND_IDX(-45)] = 0x0425,
7972         [BEND_IDX(-50)] = 0x0525,
7973 };
7974
7975 /*
7976  * Bend CLKOUT_DP
7977  * steps -50 to 50 inclusive, in steps of 5
7978  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7979  * change in clock period = -(steps / 10) * 5.787 ps
7980  */
7981 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7982 {
7983         uint32_t tmp;
7984         int idx = BEND_IDX(steps);
7985
7986         if (WARN_ON(steps % 5 != 0))
7987                 return;
7988
7989         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7990                 return;
7991
7992         mutex_lock(&dev_priv->sb_lock);
7993
7994         if (steps % 10 != 0)
7995                 tmp = 0xAAAAAAAB;
7996         else
7997                 tmp = 0x00000000;
7998         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7999
8000         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8001         tmp &= 0xffff0000;
8002         tmp |= sscdivintphase[idx];
8003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8004
8005         mutex_unlock(&dev_priv->sb_lock);
8006 }
8007
8008 #undef BEND_IDX
8009
8010 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8011 {
8012         struct intel_encoder *encoder;
8013         bool has_vga = false;
8014
8015         for_each_intel_encoder(&dev_priv->drm, encoder) {
8016                 switch (encoder->type) {
8017                 case INTEL_OUTPUT_ANALOG:
8018                         has_vga = true;
8019                         break;
8020                 default:
8021                         break;
8022                 }
8023         }
8024
8025         if (has_vga) {
8026                 lpt_bend_clkout_dp(dev_priv, 0);
8027                 lpt_enable_clkout_dp(dev_priv, true, true);
8028         } else {
8029                 lpt_disable_clkout_dp(dev_priv);
8030         }
8031 }
8032
8033 /*
8034  * Initialize reference clocks when the driver loads
8035  */
8036 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8037 {
8038         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8039                 ironlake_init_pch_refclk(dev_priv);
8040         else if (HAS_PCH_LPT(dev_priv))
8041                 lpt_init_pch_refclk(dev_priv);
8042 }
8043
8044 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8045 {
8046         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8048         int pipe = intel_crtc->pipe;
8049         uint32_t val;
8050
8051         val = 0;
8052
8053         switch (intel_crtc->config->pipe_bpp) {
8054         case 18:
8055                 val |= PIPECONF_6BPC;
8056                 break;
8057         case 24:
8058                 val |= PIPECONF_8BPC;
8059                 break;
8060         case 30:
8061                 val |= PIPECONF_10BPC;
8062                 break;
8063         case 36:
8064                 val |= PIPECONF_12BPC;
8065                 break;
8066         default:
8067                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8068                 BUG();
8069         }
8070
8071         if (intel_crtc->config->dither)
8072                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8073
8074         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8075                 val |= PIPECONF_INTERLACED_ILK;
8076         else
8077                 val |= PIPECONF_PROGRESSIVE;
8078
8079         if (intel_crtc->config->limited_color_range)
8080                 val |= PIPECONF_COLOR_RANGE_SELECT;
8081
8082         I915_WRITE(PIPECONF(pipe), val);
8083         POSTING_READ(PIPECONF(pipe));
8084 }
8085
8086 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8087 {
8088         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8090         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8091         u32 val = 0;
8092
8093         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8094                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8095
8096         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8097                 val |= PIPECONF_INTERLACED_ILK;
8098         else
8099                 val |= PIPECONF_PROGRESSIVE;
8100
8101         I915_WRITE(PIPECONF(cpu_transcoder), val);
8102         POSTING_READ(PIPECONF(cpu_transcoder));
8103 }
8104
8105 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8106 {
8107         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109         struct intel_crtc_state *config = intel_crtc->config;
8110
8111         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8112                 u32 val = 0;
8113
8114                 switch (intel_crtc->config->pipe_bpp) {
8115                 case 18:
8116                         val |= PIPEMISC_DITHER_6_BPC;
8117                         break;
8118                 case 24:
8119                         val |= PIPEMISC_DITHER_8_BPC;
8120                         break;
8121                 case 30:
8122                         val |= PIPEMISC_DITHER_10_BPC;
8123                         break;
8124                 case 36:
8125                         val |= PIPEMISC_DITHER_12_BPC;
8126                         break;
8127                 default:
8128                         /* Case prevented by pipe_config_set_bpp. */
8129                         BUG();
8130                 }
8131
8132                 if (intel_crtc->config->dither)
8133                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8134
8135                 if (config->ycbcr420) {
8136                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8137                                 PIPEMISC_YUV420_ENABLE |
8138                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8139                 }
8140
8141                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8142         }
8143 }
8144
8145 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8146 {
8147         /*
8148          * Account for spread spectrum to avoid
8149          * oversubscribing the link. Max center spread
8150          * is 2.5%; use 5% for safety's sake.
8151          */
8152         u32 bps = target_clock * bpp * 21 / 20;
8153         return DIV_ROUND_UP(bps, link_bw * 8);
8154 }
8155
8156 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8157 {
8158         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8159 }
8160
8161 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8162                                   struct intel_crtc_state *crtc_state,
8163                                   struct dpll *reduced_clock)
8164 {
8165         struct drm_crtc *crtc = &intel_crtc->base;
8166         struct drm_device *dev = crtc->dev;
8167         struct drm_i915_private *dev_priv = to_i915(dev);
8168         u32 dpll, fp, fp2;
8169         int factor;
8170
8171         /* Enable autotuning of the PLL clock (if permissible) */
8172         factor = 21;
8173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8174                 if ((intel_panel_use_ssc(dev_priv) &&
8175                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8176                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8177                         factor = 25;
8178         } else if (crtc_state->sdvo_tv_clock)
8179                 factor = 20;
8180
8181         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8182
8183         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8184                 fp |= FP_CB_TUNE;
8185
8186         if (reduced_clock) {
8187                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8188
8189                 if (reduced_clock->m < factor * reduced_clock->n)
8190                         fp2 |= FP_CB_TUNE;
8191         } else {
8192                 fp2 = fp;
8193         }
8194
8195         dpll = 0;
8196
8197         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8198                 dpll |= DPLLB_MODE_LVDS;
8199         else
8200                 dpll |= DPLLB_MODE_DAC_SERIAL;
8201
8202         dpll |= (crtc_state->pixel_multiplier - 1)
8203                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8204
8205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8206             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8207                 dpll |= DPLL_SDVO_HIGH_SPEED;
8208
8209         if (intel_crtc_has_dp_encoder(crtc_state))
8210                 dpll |= DPLL_SDVO_HIGH_SPEED;
8211
8212         /*
8213          * The high speed IO clock is only really required for
8214          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8215          * possible to share the DPLL between CRT and HDMI. Enabling
8216          * the clock needlessly does no real harm, except use up a
8217          * bit of power potentially.
8218          *
8219          * We'll limit this to IVB with 3 pipes, since it has only two
8220          * DPLLs and so DPLL sharing is the only way to get three pipes
8221          * driving PCH ports at the same time. On SNB we could do this,
8222          * and potentially avoid enabling the second DPLL, but it's not
8223          * clear if it''s a win or loss power wise. No point in doing
8224          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8225          */
8226         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8227             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8228                 dpll |= DPLL_SDVO_HIGH_SPEED;
8229
8230         /* compute bitmask from p1 value */
8231         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232         /* also FPA1 */
8233         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8234
8235         switch (crtc_state->dpll.p2) {
8236         case 5:
8237                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8238                 break;
8239         case 7:
8240                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8241                 break;
8242         case 10:
8243                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8244                 break;
8245         case 14:
8246                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8247                 break;
8248         }
8249
8250         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8251             intel_panel_use_ssc(dev_priv))
8252                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8253         else
8254                 dpll |= PLL_REF_INPUT_DREFCLK;
8255
8256         dpll |= DPLL_VCO_ENABLE;
8257
8258         crtc_state->dpll_hw_state.dpll = dpll;
8259         crtc_state->dpll_hw_state.fp0 = fp;
8260         crtc_state->dpll_hw_state.fp1 = fp2;
8261 }
8262
8263 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8264                                        struct intel_crtc_state *crtc_state)
8265 {
8266         struct drm_device *dev = crtc->base.dev;
8267         struct drm_i915_private *dev_priv = to_i915(dev);
8268         const struct intel_limit *limit;
8269         int refclk = 120000;
8270
8271         memset(&crtc_state->dpll_hw_state, 0,
8272                sizeof(crtc_state->dpll_hw_state));
8273
8274         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8275         if (!crtc_state->has_pch_encoder)
8276                 return 0;
8277
8278         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8279                 if (intel_panel_use_ssc(dev_priv)) {
8280                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8281                                       dev_priv->vbt.lvds_ssc_freq);
8282                         refclk = dev_priv->vbt.lvds_ssc_freq;
8283                 }
8284
8285                 if (intel_is_dual_link_lvds(dev)) {
8286                         if (refclk == 100000)
8287                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8288                         else
8289                                 limit = &intel_limits_ironlake_dual_lvds;
8290                 } else {
8291                         if (refclk == 100000)
8292                                 limit = &intel_limits_ironlake_single_lvds_100m;
8293                         else
8294                                 limit = &intel_limits_ironlake_single_lvds;
8295                 }
8296         } else {
8297                 limit = &intel_limits_ironlake_dac;
8298         }
8299
8300         if (!crtc_state->clock_set &&
8301             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8302                                 refclk, NULL, &crtc_state->dpll)) {
8303                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8304                 return -EINVAL;
8305         }
8306
8307         ironlake_compute_dpll(crtc, crtc_state, NULL);
8308
8309         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8310                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8311                                  pipe_name(crtc->pipe));
8312                 return -EINVAL;
8313         }
8314
8315         return 0;
8316 }
8317
8318 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8319                                          struct intel_link_m_n *m_n)
8320 {
8321         struct drm_device *dev = crtc->base.dev;
8322         struct drm_i915_private *dev_priv = to_i915(dev);
8323         enum pipe pipe = crtc->pipe;
8324
8325         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8326         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8327         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8328                 & ~TU_SIZE_MASK;
8329         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8330         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8331                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8332 }
8333
8334 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8335                                          enum transcoder transcoder,
8336                                          struct intel_link_m_n *m_n,
8337                                          struct intel_link_m_n *m2_n2)
8338 {
8339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8340         enum pipe pipe = crtc->pipe;
8341
8342         if (INTEL_GEN(dev_priv) >= 5) {
8343                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8344                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8345                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8346                         & ~TU_SIZE_MASK;
8347                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8348                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8349                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8350                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8351                  * gen < 8) and if DRRS is supported (to make sure the
8352                  * registers are not unnecessarily read).
8353                  */
8354                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8355                         crtc->config->has_drrs) {
8356                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8357                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8358                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8359                                         & ~TU_SIZE_MASK;
8360                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8361                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8362                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8363                 }
8364         } else {
8365                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8366                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8367                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8368                         & ~TU_SIZE_MASK;
8369                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8370                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8371                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8372         }
8373 }
8374
8375 void intel_dp_get_m_n(struct intel_crtc *crtc,
8376                       struct intel_crtc_state *pipe_config)
8377 {
8378         if (pipe_config->has_pch_encoder)
8379                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8380         else
8381                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8382                                              &pipe_config->dp_m_n,
8383                                              &pipe_config->dp_m2_n2);
8384 }
8385
8386 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8387                                         struct intel_crtc_state *pipe_config)
8388 {
8389         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8390                                      &pipe_config->fdi_m_n, NULL);
8391 }
8392
8393 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8394                                     struct intel_crtc_state *pipe_config)
8395 {
8396         struct drm_device *dev = crtc->base.dev;
8397         struct drm_i915_private *dev_priv = to_i915(dev);
8398         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8399         uint32_t ps_ctrl = 0;
8400         int id = -1;
8401         int i;
8402
8403         /* find scaler attached to this pipe */
8404         for (i = 0; i < crtc->num_scalers; i++) {
8405                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8406                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8407                         id = i;
8408                         pipe_config->pch_pfit.enabled = true;
8409                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8410                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8411                         break;
8412                 }
8413         }
8414
8415         scaler_state->scaler_id = id;
8416         if (id >= 0) {
8417                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8418         } else {
8419                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8420         }
8421 }
8422
8423 static void
8424 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8425                                  struct intel_initial_plane_config *plane_config)
8426 {
8427         struct drm_device *dev = crtc->base.dev;
8428         struct drm_i915_private *dev_priv = to_i915(dev);
8429         u32 val, base, offset, stride_mult, tiling;
8430         int pipe = crtc->pipe;
8431         int fourcc, pixel_format;
8432         unsigned int aligned_height;
8433         struct drm_framebuffer *fb;
8434         struct intel_framebuffer *intel_fb;
8435
8436         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8437         if (!intel_fb) {
8438                 DRM_DEBUG_KMS("failed to alloc fb\n");
8439                 return;
8440         }
8441
8442         fb = &intel_fb->base;
8443
8444         fb->dev = dev;
8445
8446         val = I915_READ(PLANE_CTL(pipe, 0));
8447         if (!(val & PLANE_CTL_ENABLE))
8448                 goto error;
8449
8450         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8451         fourcc = skl_format_to_fourcc(pixel_format,
8452                                       val & PLANE_CTL_ORDER_RGBX,
8453                                       val & PLANE_CTL_ALPHA_MASK);
8454         fb->format = drm_format_info(fourcc);
8455
8456         tiling = val & PLANE_CTL_TILED_MASK;
8457         switch (tiling) {
8458         case PLANE_CTL_TILED_LINEAR:
8459                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8460                 break;
8461         case PLANE_CTL_TILED_X:
8462                 plane_config->tiling = I915_TILING_X;
8463                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8464                 break;
8465         case PLANE_CTL_TILED_Y:
8466                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8467                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8468                 else
8469                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8470                 break;
8471         case PLANE_CTL_TILED_YF:
8472                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8473                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8474                 else
8475                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8476                 break;
8477         default:
8478                 MISSING_CASE(tiling);
8479                 goto error;
8480         }
8481
8482         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8483         plane_config->base = base;
8484
8485         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8486
8487         val = I915_READ(PLANE_SIZE(pipe, 0));
8488         fb->height = ((val >> 16) & 0xfff) + 1;
8489         fb->width = ((val >> 0) & 0x1fff) + 1;
8490
8491         val = I915_READ(PLANE_STRIDE(pipe, 0));
8492         stride_mult = intel_fb_stride_alignment(fb, 0);
8493         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8494
8495         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8496
8497         plane_config->size = fb->pitches[0] * aligned_height;
8498
8499         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8500                       pipe_name(pipe), fb->width, fb->height,
8501                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8502                       plane_config->size);
8503
8504         plane_config->fb = intel_fb;
8505         return;
8506
8507 error:
8508         kfree(intel_fb);
8509 }
8510
8511 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8512                                      struct intel_crtc_state *pipe_config)
8513 {
8514         struct drm_device *dev = crtc->base.dev;
8515         struct drm_i915_private *dev_priv = to_i915(dev);
8516         uint32_t tmp;
8517
8518         tmp = I915_READ(PF_CTL(crtc->pipe));
8519
8520         if (tmp & PF_ENABLE) {
8521                 pipe_config->pch_pfit.enabled = true;
8522                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8523                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8524
8525                 /* We currently do not free assignements of panel fitters on
8526                  * ivb/hsw (since we don't use the higher upscaling modes which
8527                  * differentiates them) so just WARN about this case for now. */
8528                 if (IS_GEN7(dev_priv)) {
8529                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8530                                 PF_PIPE_SEL_IVB(crtc->pipe));
8531                 }
8532         }
8533 }
8534
8535 static void
8536 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8537                                   struct intel_initial_plane_config *plane_config)
8538 {
8539         struct drm_device *dev = crtc->base.dev;
8540         struct drm_i915_private *dev_priv = to_i915(dev);
8541         u32 val, base, offset;
8542         int pipe = crtc->pipe;
8543         int fourcc, pixel_format;
8544         unsigned int aligned_height;
8545         struct drm_framebuffer *fb;
8546         struct intel_framebuffer *intel_fb;
8547
8548         val = I915_READ(DSPCNTR(pipe));
8549         if (!(val & DISPLAY_PLANE_ENABLE))
8550                 return;
8551
8552         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8553         if (!intel_fb) {
8554                 DRM_DEBUG_KMS("failed to alloc fb\n");
8555                 return;
8556         }
8557
8558         fb = &intel_fb->base;
8559
8560         fb->dev = dev;
8561
8562         if (INTEL_GEN(dev_priv) >= 4) {
8563                 if (val & DISPPLANE_TILED) {
8564                         plane_config->tiling = I915_TILING_X;
8565                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8566                 }
8567         }
8568
8569         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8570         fourcc = i9xx_format_to_fourcc(pixel_format);
8571         fb->format = drm_format_info(fourcc);
8572
8573         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8574         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8575                 offset = I915_READ(DSPOFFSET(pipe));
8576         } else {
8577                 if (plane_config->tiling)
8578                         offset = I915_READ(DSPTILEOFF(pipe));
8579                 else
8580                         offset = I915_READ(DSPLINOFF(pipe));
8581         }
8582         plane_config->base = base;
8583
8584         val = I915_READ(PIPESRC(pipe));
8585         fb->width = ((val >> 16) & 0xfff) + 1;
8586         fb->height = ((val >> 0) & 0xfff) + 1;
8587
8588         val = I915_READ(DSPSTRIDE(pipe));
8589         fb->pitches[0] = val & 0xffffffc0;
8590
8591         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8592
8593         plane_config->size = fb->pitches[0] * aligned_height;
8594
8595         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8596                       pipe_name(pipe), fb->width, fb->height,
8597                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8598                       plane_config->size);
8599
8600         plane_config->fb = intel_fb;
8601 }
8602
8603 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8604                                      struct intel_crtc_state *pipe_config)
8605 {
8606         struct drm_device *dev = crtc->base.dev;
8607         struct drm_i915_private *dev_priv = to_i915(dev);
8608         enum intel_display_power_domain power_domain;
8609         uint32_t tmp;
8610         bool ret;
8611
8612         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8613         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8614                 return false;
8615
8616         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8617         pipe_config->shared_dpll = NULL;
8618
8619         ret = false;
8620         tmp = I915_READ(PIPECONF(crtc->pipe));
8621         if (!(tmp & PIPECONF_ENABLE))
8622                 goto out;
8623
8624         switch (tmp & PIPECONF_BPC_MASK) {
8625         case PIPECONF_6BPC:
8626                 pipe_config->pipe_bpp = 18;
8627                 break;
8628         case PIPECONF_8BPC:
8629                 pipe_config->pipe_bpp = 24;
8630                 break;
8631         case PIPECONF_10BPC:
8632                 pipe_config->pipe_bpp = 30;
8633                 break;
8634         case PIPECONF_12BPC:
8635                 pipe_config->pipe_bpp = 36;
8636                 break;
8637         default:
8638                 break;
8639         }
8640
8641         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8642                 pipe_config->limited_color_range = true;
8643
8644         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8645                 struct intel_shared_dpll *pll;
8646                 enum intel_dpll_id pll_id;
8647
8648                 pipe_config->has_pch_encoder = true;
8649
8650                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8651                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8652                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8653
8654                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8655
8656                 if (HAS_PCH_IBX(dev_priv)) {
8657                         /*
8658                          * The pipe->pch transcoder and pch transcoder->pll
8659                          * mapping is fixed.
8660                          */
8661                         pll_id = (enum intel_dpll_id) crtc->pipe;
8662                 } else {
8663                         tmp = I915_READ(PCH_DPLL_SEL);
8664                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8665                                 pll_id = DPLL_ID_PCH_PLL_B;
8666                         else
8667                                 pll_id= DPLL_ID_PCH_PLL_A;
8668                 }
8669
8670                 pipe_config->shared_dpll =
8671                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8672                 pll = pipe_config->shared_dpll;
8673
8674                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8675                                                  &pipe_config->dpll_hw_state));
8676
8677                 tmp = pipe_config->dpll_hw_state.dpll;
8678                 pipe_config->pixel_multiplier =
8679                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8680                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8681
8682                 ironlake_pch_clock_get(crtc, pipe_config);
8683         } else {
8684                 pipe_config->pixel_multiplier = 1;
8685         }
8686
8687         intel_get_pipe_timings(crtc, pipe_config);
8688         intel_get_pipe_src_size(crtc, pipe_config);
8689
8690         ironlake_get_pfit_config(crtc, pipe_config);
8691
8692         ret = true;
8693
8694 out:
8695         intel_display_power_put(dev_priv, power_domain);
8696
8697         return ret;
8698 }
8699
8700 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8701 {
8702         struct drm_device *dev = &dev_priv->drm;
8703         struct intel_crtc *crtc;
8704
8705         for_each_intel_crtc(dev, crtc)
8706                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8707                      pipe_name(crtc->pipe));
8708
8709         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8710                         "Display power well on\n");
8711         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8712         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8713         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8714         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8715         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8716              "CPU PWM1 enabled\n");
8717         if (IS_HASWELL(dev_priv))
8718                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8719                      "CPU PWM2 enabled\n");
8720         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8721              "PCH PWM1 enabled\n");
8722         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8723              "Utility pin enabled\n");
8724         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8725
8726         /*
8727          * In theory we can still leave IRQs enabled, as long as only the HPD
8728          * interrupts remain enabled. We used to check for that, but since it's
8729          * gen-specific and since we only disable LCPLL after we fully disable
8730          * the interrupts, the check below should be enough.
8731          */
8732         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8733 }
8734
8735 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8736 {
8737         if (IS_HASWELL(dev_priv))
8738                 return I915_READ(D_COMP_HSW);
8739         else
8740                 return I915_READ(D_COMP_BDW);
8741 }
8742
8743 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8744 {
8745         if (IS_HASWELL(dev_priv)) {
8746                 mutex_lock(&dev_priv->pcu_lock);
8747                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8748                                             val))
8749                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8750                 mutex_unlock(&dev_priv->pcu_lock);
8751         } else {
8752                 I915_WRITE(D_COMP_BDW, val);
8753                 POSTING_READ(D_COMP_BDW);
8754         }
8755 }
8756
8757 /*
8758  * This function implements pieces of two sequences from BSpec:
8759  * - Sequence for display software to disable LCPLL
8760  * - Sequence for display software to allow package C8+
8761  * The steps implemented here are just the steps that actually touch the LCPLL
8762  * register. Callers should take care of disabling all the display engine
8763  * functions, doing the mode unset, fixing interrupts, etc.
8764  */
8765 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8766                               bool switch_to_fclk, bool allow_power_down)
8767 {
8768         uint32_t val;
8769
8770         assert_can_disable_lcpll(dev_priv);
8771
8772         val = I915_READ(LCPLL_CTL);
8773
8774         if (switch_to_fclk) {
8775                 val |= LCPLL_CD_SOURCE_FCLK;
8776                 I915_WRITE(LCPLL_CTL, val);
8777
8778                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8779                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8780                         DRM_ERROR("Switching to FCLK failed\n");
8781
8782                 val = I915_READ(LCPLL_CTL);
8783         }
8784
8785         val |= LCPLL_PLL_DISABLE;
8786         I915_WRITE(LCPLL_CTL, val);
8787         POSTING_READ(LCPLL_CTL);
8788
8789         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8790                 DRM_ERROR("LCPLL still locked\n");
8791
8792         val = hsw_read_dcomp(dev_priv);
8793         val |= D_COMP_COMP_DISABLE;
8794         hsw_write_dcomp(dev_priv, val);
8795         ndelay(100);
8796
8797         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8798                      1))
8799                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8800
8801         if (allow_power_down) {
8802                 val = I915_READ(LCPLL_CTL);
8803                 val |= LCPLL_POWER_DOWN_ALLOW;
8804                 I915_WRITE(LCPLL_CTL, val);
8805                 POSTING_READ(LCPLL_CTL);
8806         }
8807 }
8808
8809 /*
8810  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8811  * source.
8812  */
8813 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8814 {
8815         uint32_t val;
8816
8817         val = I915_READ(LCPLL_CTL);
8818
8819         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8820                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8821                 return;
8822
8823         /*
8824          * Make sure we're not on PC8 state before disabling PC8, otherwise
8825          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8826          */
8827         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8828
8829         if (val & LCPLL_POWER_DOWN_ALLOW) {
8830                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8831                 I915_WRITE(LCPLL_CTL, val);
8832                 POSTING_READ(LCPLL_CTL);
8833         }
8834
8835         val = hsw_read_dcomp(dev_priv);
8836         val |= D_COMP_COMP_FORCE;
8837         val &= ~D_COMP_COMP_DISABLE;
8838         hsw_write_dcomp(dev_priv, val);
8839
8840         val = I915_READ(LCPLL_CTL);
8841         val &= ~LCPLL_PLL_DISABLE;
8842         I915_WRITE(LCPLL_CTL, val);
8843
8844         if (intel_wait_for_register(dev_priv,
8845                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8846                                     5))
8847                 DRM_ERROR("LCPLL not locked yet\n");
8848
8849         if (val & LCPLL_CD_SOURCE_FCLK) {
8850                 val = I915_READ(LCPLL_CTL);
8851                 val &= ~LCPLL_CD_SOURCE_FCLK;
8852                 I915_WRITE(LCPLL_CTL, val);
8853
8854                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8855                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8856                         DRM_ERROR("Switching back to LCPLL failed\n");
8857         }
8858
8859         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8860
8861         intel_update_cdclk(dev_priv);
8862         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
8863 }
8864
8865 /*
8866  * Package states C8 and deeper are really deep PC states that can only be
8867  * reached when all the devices on the system allow it, so even if the graphics
8868  * device allows PC8+, it doesn't mean the system will actually get to these
8869  * states. Our driver only allows PC8+ when going into runtime PM.
8870  *
8871  * The requirements for PC8+ are that all the outputs are disabled, the power
8872  * well is disabled and most interrupts are disabled, and these are also
8873  * requirements for runtime PM. When these conditions are met, we manually do
8874  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8875  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8876  * hang the machine.
8877  *
8878  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8879  * the state of some registers, so when we come back from PC8+ we need to
8880  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8881  * need to take care of the registers kept by RC6. Notice that this happens even
8882  * if we don't put the device in PCI D3 state (which is what currently happens
8883  * because of the runtime PM support).
8884  *
8885  * For more, read "Display Sequences for Package C8" on the hardware
8886  * documentation.
8887  */
8888 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8889 {
8890         uint32_t val;
8891
8892         DRM_DEBUG_KMS("Enabling package C8+\n");
8893
8894         if (HAS_PCH_LPT_LP(dev_priv)) {
8895                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8896                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8897                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8898         }
8899
8900         lpt_disable_clkout_dp(dev_priv);
8901         hsw_disable_lcpll(dev_priv, true, true);
8902 }
8903
8904 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8905 {
8906         uint32_t val;
8907
8908         DRM_DEBUG_KMS("Disabling package C8+\n");
8909
8910         hsw_restore_lcpll(dev_priv);
8911         lpt_init_pch_refclk(dev_priv);
8912
8913         if (HAS_PCH_LPT_LP(dev_priv)) {
8914                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8915                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8916                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8917         }
8918 }
8919
8920 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8921                                       struct intel_crtc_state *crtc_state)
8922 {
8923         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8924                 struct intel_encoder *encoder =
8925                         intel_ddi_get_crtc_new_encoder(crtc_state);
8926
8927                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8928                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8929                                          pipe_name(crtc->pipe));
8930                         return -EINVAL;
8931                 }
8932         }
8933
8934         return 0;
8935 }
8936
8937 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8938                                    enum port port,
8939                                    struct intel_crtc_state *pipe_config)
8940 {
8941         enum intel_dpll_id id;
8942         u32 temp;
8943
8944         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8945         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8946
8947         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8948                 return;
8949
8950         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8951 }
8952
8953 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8954                                 enum port port,
8955                                 struct intel_crtc_state *pipe_config)
8956 {
8957         enum intel_dpll_id id;
8958
8959         switch (port) {
8960         case PORT_A:
8961                 id = DPLL_ID_SKL_DPLL0;
8962                 break;
8963         case PORT_B:
8964                 id = DPLL_ID_SKL_DPLL1;
8965                 break;
8966         case PORT_C:
8967                 id = DPLL_ID_SKL_DPLL2;
8968                 break;
8969         default:
8970                 DRM_ERROR("Incorrect port type\n");
8971                 return;
8972         }
8973
8974         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8975 }
8976
8977 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8978                                 enum port port,
8979                                 struct intel_crtc_state *pipe_config)
8980 {
8981         enum intel_dpll_id id;
8982         u32 temp;
8983
8984         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8985         id = temp >> (port * 3 + 1);
8986
8987         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8988                 return;
8989
8990         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8994                                 enum port port,
8995                                 struct intel_crtc_state *pipe_config)
8996 {
8997         enum intel_dpll_id id;
8998         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8999
9000         switch (ddi_pll_sel) {
9001         case PORT_CLK_SEL_WRPLL1:
9002                 id = DPLL_ID_WRPLL1;
9003                 break;
9004         case PORT_CLK_SEL_WRPLL2:
9005                 id = DPLL_ID_WRPLL2;
9006                 break;
9007         case PORT_CLK_SEL_SPLL:
9008                 id = DPLL_ID_SPLL;
9009                 break;
9010         case PORT_CLK_SEL_LCPLL_810:
9011                 id = DPLL_ID_LCPLL_810;
9012                 break;
9013         case PORT_CLK_SEL_LCPLL_1350:
9014                 id = DPLL_ID_LCPLL_1350;
9015                 break;
9016         case PORT_CLK_SEL_LCPLL_2700:
9017                 id = DPLL_ID_LCPLL_2700;
9018                 break;
9019         default:
9020                 MISSING_CASE(ddi_pll_sel);
9021                 /* fall through */
9022         case PORT_CLK_SEL_NONE:
9023                 return;
9024         }
9025
9026         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9027 }
9028
9029 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9030                                      struct intel_crtc_state *pipe_config,
9031                                      u64 *power_domain_mask)
9032 {
9033         struct drm_device *dev = crtc->base.dev;
9034         struct drm_i915_private *dev_priv = to_i915(dev);
9035         enum intel_display_power_domain power_domain;
9036         u32 tmp;
9037
9038         /*
9039          * The pipe->transcoder mapping is fixed with the exception of the eDP
9040          * transcoder handled below.
9041          */
9042         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9043
9044         /*
9045          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9046          * consistency and less surprising code; it's in always on power).
9047          */
9048         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9049         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9050                 enum pipe trans_edp_pipe;
9051                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9052                 default:
9053                         WARN(1, "unknown pipe linked to edp transcoder\n");
9054                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9055                 case TRANS_DDI_EDP_INPUT_A_ON:
9056                         trans_edp_pipe = PIPE_A;
9057                         break;
9058                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9059                         trans_edp_pipe = PIPE_B;
9060                         break;
9061                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9062                         trans_edp_pipe = PIPE_C;
9063                         break;
9064                 }
9065
9066                 if (trans_edp_pipe == crtc->pipe)
9067                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9068         }
9069
9070         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9071         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9072                 return false;
9073         *power_domain_mask |= BIT_ULL(power_domain);
9074
9075         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9076
9077         return tmp & PIPECONF_ENABLE;
9078 }
9079
9080 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9081                                          struct intel_crtc_state *pipe_config,
9082                                          u64 *power_domain_mask)
9083 {
9084         struct drm_device *dev = crtc->base.dev;
9085         struct drm_i915_private *dev_priv = to_i915(dev);
9086         enum intel_display_power_domain power_domain;
9087         enum port port;
9088         enum transcoder cpu_transcoder;
9089         u32 tmp;
9090
9091         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9092                 if (port == PORT_A)
9093                         cpu_transcoder = TRANSCODER_DSI_A;
9094                 else
9095                         cpu_transcoder = TRANSCODER_DSI_C;
9096
9097                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9098                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9099                         continue;
9100                 *power_domain_mask |= BIT_ULL(power_domain);
9101
9102                 /*
9103                  * The PLL needs to be enabled with a valid divider
9104                  * configuration, otherwise accessing DSI registers will hang
9105                  * the machine. See BSpec North Display Engine
9106                  * registers/MIPI[BXT]. We can break out here early, since we
9107                  * need the same DSI PLL to be enabled for both DSI ports.
9108                  */
9109                 if (!intel_dsi_pll_is_enabled(dev_priv))
9110                         break;
9111
9112                 /* XXX: this works for video mode only */
9113                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9114                 if (!(tmp & DPI_ENABLE))
9115                         continue;
9116
9117                 tmp = I915_READ(MIPI_CTRL(port));
9118                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9119                         continue;
9120
9121                 pipe_config->cpu_transcoder = cpu_transcoder;
9122                 break;
9123         }
9124
9125         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9126 }
9127
9128 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9129                                        struct intel_crtc_state *pipe_config)
9130 {
9131         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9132         struct intel_shared_dpll *pll;
9133         enum port port;
9134         uint32_t tmp;
9135
9136         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9137
9138         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9139
9140         if (IS_CANNONLAKE(dev_priv))
9141                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9142         else if (IS_GEN9_BC(dev_priv))
9143                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9144         else if (IS_GEN9_LP(dev_priv))
9145                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9146         else
9147                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9148
9149         pll = pipe_config->shared_dpll;
9150         if (pll) {
9151                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9152                                                  &pipe_config->dpll_hw_state));
9153         }
9154
9155         /*
9156          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9157          * DDI E. So just check whether this pipe is wired to DDI E and whether
9158          * the PCH transcoder is on.
9159          */
9160         if (INTEL_GEN(dev_priv) < 9 &&
9161             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9162                 pipe_config->has_pch_encoder = true;
9163
9164                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9165                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9166                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9167
9168                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9169         }
9170 }
9171
9172 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9173                                     struct intel_crtc_state *pipe_config)
9174 {
9175         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9176         enum intel_display_power_domain power_domain;
9177         u64 power_domain_mask;
9178         bool active;
9179
9180         intel_crtc_init_scalers(crtc, pipe_config);
9181
9182         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9183         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9184                 return false;
9185         power_domain_mask = BIT_ULL(power_domain);
9186
9187         pipe_config->shared_dpll = NULL;
9188
9189         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9190
9191         if (IS_GEN9_LP(dev_priv) &&
9192             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9193                 WARN_ON(active);
9194                 active = true;
9195         }
9196
9197         if (!active)
9198                 goto out;
9199
9200         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9201                 haswell_get_ddi_port_state(crtc, pipe_config);
9202                 intel_get_pipe_timings(crtc, pipe_config);
9203         }
9204
9205         intel_get_pipe_src_size(crtc, pipe_config);
9206
9207         pipe_config->gamma_mode =
9208                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9209
9210         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9211                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9212                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9213
9214                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9215                         bool blend_mode_420 = tmp &
9216                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9217
9218                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9219                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9220                             pipe_config->ycbcr420 != blend_mode_420)
9221                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9222                 } else if (clrspace_yuv) {
9223                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9224                 }
9225         }
9226
9227         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9228         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9229                 power_domain_mask |= BIT_ULL(power_domain);
9230                 if (INTEL_GEN(dev_priv) >= 9)
9231                         skylake_get_pfit_config(crtc, pipe_config);
9232                 else
9233                         ironlake_get_pfit_config(crtc, pipe_config);
9234         }
9235
9236         if (IS_HASWELL(dev_priv))
9237                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9238                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9239
9240         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9241             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9242                 pipe_config->pixel_multiplier =
9243                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9244         } else {
9245                 pipe_config->pixel_multiplier = 1;
9246         }
9247
9248 out:
9249         for_each_power_domain(power_domain, power_domain_mask)
9250                 intel_display_power_put(dev_priv, power_domain);
9251
9252         return active;
9253 }
9254
9255 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9256 {
9257         struct drm_i915_private *dev_priv =
9258                 to_i915(plane_state->base.plane->dev);
9259         const struct drm_framebuffer *fb = plane_state->base.fb;
9260         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9261         u32 base;
9262
9263         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9264                 base = obj->phys_handle->busaddr;
9265         else
9266                 base = intel_plane_ggtt_offset(plane_state);
9267
9268         base += plane_state->main.offset;
9269
9270         /* ILK+ do this automagically */
9271         if (HAS_GMCH_DISPLAY(dev_priv) &&
9272             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9273                 base += (plane_state->base.crtc_h *
9274                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9275
9276         return base;
9277 }
9278
9279 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9280 {
9281         int x = plane_state->base.crtc_x;
9282         int y = plane_state->base.crtc_y;
9283         u32 pos = 0;
9284
9285         if (x < 0) {
9286                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9287                 x = -x;
9288         }
9289         pos |= x << CURSOR_X_SHIFT;
9290
9291         if (y < 0) {
9292                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9293                 y = -y;
9294         }
9295         pos |= y << CURSOR_Y_SHIFT;
9296
9297         return pos;
9298 }
9299
9300 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9301 {
9302         const struct drm_mode_config *config =
9303                 &plane_state->base.plane->dev->mode_config;
9304         int width = plane_state->base.crtc_w;
9305         int height = plane_state->base.crtc_h;
9306
9307         return width > 0 && width <= config->cursor_width &&
9308                 height > 0 && height <= config->cursor_height;
9309 }
9310
9311 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9312                               struct intel_plane_state *plane_state)
9313 {
9314         const struct drm_framebuffer *fb = plane_state->base.fb;
9315         int src_x, src_y;
9316         u32 offset;
9317         int ret;
9318
9319         ret = drm_plane_helper_check_state(&plane_state->base,
9320                                            &plane_state->clip,
9321                                            DRM_PLANE_HELPER_NO_SCALING,
9322                                            DRM_PLANE_HELPER_NO_SCALING,
9323                                            true, true);
9324         if (ret)
9325                 return ret;
9326
9327         if (!fb)
9328                 return 0;
9329
9330         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9331                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9332                 return -EINVAL;
9333         }
9334
9335         src_x = plane_state->base.src_x >> 16;
9336         src_y = plane_state->base.src_y >> 16;
9337
9338         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9339         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9340
9341         if (src_x != 0 || src_y != 0) {
9342                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9343                 return -EINVAL;
9344         }
9345
9346         plane_state->main.offset = offset;
9347
9348         return 0;
9349 }
9350
9351 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9352                            const struct intel_plane_state *plane_state)
9353 {
9354         const struct drm_framebuffer *fb = plane_state->base.fb;
9355
9356         return CURSOR_ENABLE |
9357                 CURSOR_GAMMA_ENABLE |
9358                 CURSOR_FORMAT_ARGB |
9359                 CURSOR_STRIDE(fb->pitches[0]);
9360 }
9361
9362 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9363 {
9364         int width = plane_state->base.crtc_w;
9365
9366         /*
9367          * 845g/865g are only limited by the width of their cursors,
9368          * the height is arbitrary up to the precision of the register.
9369          */
9370         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9371 }
9372
9373 static int i845_check_cursor(struct intel_plane *plane,
9374                              struct intel_crtc_state *crtc_state,
9375                              struct intel_plane_state *plane_state)
9376 {
9377         const struct drm_framebuffer *fb = plane_state->base.fb;
9378         int ret;
9379
9380         ret = intel_check_cursor(crtc_state, plane_state);
9381         if (ret)
9382                 return ret;
9383
9384         /* if we want to turn off the cursor ignore width and height */
9385         if (!fb)
9386                 return 0;
9387
9388         /* Check for which cursor types we support */
9389         if (!i845_cursor_size_ok(plane_state)) {
9390                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9391                           plane_state->base.crtc_w,
9392                           plane_state->base.crtc_h);
9393                 return -EINVAL;
9394         }
9395
9396         switch (fb->pitches[0]) {
9397         case 256:
9398         case 512:
9399         case 1024:
9400         case 2048:
9401                 break;
9402         default:
9403                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9404                               fb->pitches[0]);
9405                 return -EINVAL;
9406         }
9407
9408         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9409
9410         return 0;
9411 }
9412
9413 static void i845_update_cursor(struct intel_plane *plane,
9414                                const struct intel_crtc_state *crtc_state,
9415                                const struct intel_plane_state *plane_state)
9416 {
9417         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9418         u32 cntl = 0, base = 0, pos = 0, size = 0;
9419         unsigned long irqflags;
9420
9421         if (plane_state && plane_state->base.visible) {
9422                 unsigned int width = plane_state->base.crtc_w;
9423                 unsigned int height = plane_state->base.crtc_h;
9424
9425                 cntl = plane_state->ctl;
9426                 size = (height << 12) | width;
9427
9428                 base = intel_cursor_base(plane_state);
9429                 pos = intel_cursor_position(plane_state);
9430         }
9431
9432         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9433
9434         /* On these chipsets we can only modify the base/size/stride
9435          * whilst the cursor is disabled.
9436          */
9437         if (plane->cursor.base != base ||
9438             plane->cursor.size != size ||
9439             plane->cursor.cntl != cntl) {
9440                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9441                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9442                 I915_WRITE_FW(CURSIZE, size);
9443                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9444                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9445
9446                 plane->cursor.base = base;
9447                 plane->cursor.size = size;
9448                 plane->cursor.cntl = cntl;
9449         } else {
9450                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9451         }
9452
9453         POSTING_READ_FW(CURCNTR(PIPE_A));
9454
9455         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9456 }
9457
9458 static void i845_disable_cursor(struct intel_plane *plane,
9459                                 struct intel_crtc *crtc)
9460 {
9461         i845_update_cursor(plane, NULL, NULL);
9462 }
9463
9464 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9465                            const struct intel_plane_state *plane_state)
9466 {
9467         struct drm_i915_private *dev_priv =
9468                 to_i915(plane_state->base.plane->dev);
9469         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9470         u32 cntl;
9471
9472         cntl = MCURSOR_GAMMA_ENABLE;
9473
9474         if (HAS_DDI(dev_priv))
9475                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9476
9477         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9478
9479         switch (plane_state->base.crtc_w) {
9480         case 64:
9481                 cntl |= CURSOR_MODE_64_ARGB_AX;
9482                 break;
9483         case 128:
9484                 cntl |= CURSOR_MODE_128_ARGB_AX;
9485                 break;
9486         case 256:
9487                 cntl |= CURSOR_MODE_256_ARGB_AX;
9488                 break;
9489         default:
9490                 MISSING_CASE(plane_state->base.crtc_w);
9491                 return 0;
9492         }
9493
9494         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9495                 cntl |= CURSOR_ROTATE_180;
9496
9497         return cntl;
9498 }
9499
9500 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9501 {
9502         struct drm_i915_private *dev_priv =
9503                 to_i915(plane_state->base.plane->dev);
9504         int width = plane_state->base.crtc_w;
9505         int height = plane_state->base.crtc_h;
9506
9507         if (!intel_cursor_size_ok(plane_state))
9508                 return false;
9509
9510         /* Cursor width is limited to a few power-of-two sizes */
9511         switch (width) {
9512         case 256:
9513         case 128:
9514         case 64:
9515                 break;
9516         default:
9517                 return false;
9518         }
9519
9520         /*
9521          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9522          * height from 8 lines up to the cursor width, when the
9523          * cursor is not rotated. Everything else requires square
9524          * cursors.
9525          */
9526         if (HAS_CUR_FBC(dev_priv) &&
9527             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9528                 if (height < 8 || height > width)
9529                         return false;
9530         } else {
9531                 if (height != width)
9532                         return false;
9533         }
9534
9535         return true;
9536 }
9537
9538 static int i9xx_check_cursor(struct intel_plane *plane,
9539                              struct intel_crtc_state *crtc_state,
9540                              struct intel_plane_state *plane_state)
9541 {
9542         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9543         const struct drm_framebuffer *fb = plane_state->base.fb;
9544         enum pipe pipe = plane->pipe;
9545         int ret;
9546
9547         ret = intel_check_cursor(crtc_state, plane_state);
9548         if (ret)
9549                 return ret;
9550
9551         /* if we want to turn off the cursor ignore width and height */
9552         if (!fb)
9553                 return 0;
9554
9555         /* Check for which cursor types we support */
9556         if (!i9xx_cursor_size_ok(plane_state)) {
9557                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9558                           plane_state->base.crtc_w,
9559                           plane_state->base.crtc_h);
9560                 return -EINVAL;
9561         }
9562
9563         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9564                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9565                               fb->pitches[0], plane_state->base.crtc_w);
9566                 return -EINVAL;
9567         }
9568
9569         /*
9570          * There's something wrong with the cursor on CHV pipe C.
9571          * If it straddles the left edge of the screen then
9572          * moving it away from the edge or disabling it often
9573          * results in a pipe underrun, and often that can lead to
9574          * dead pipe (constant underrun reported, and it scans
9575          * out just a solid color). To recover from that, the
9576          * display power well must be turned off and on again.
9577          * Refuse the put the cursor into that compromised position.
9578          */
9579         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9580             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9581                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9582                 return -EINVAL;
9583         }
9584
9585         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9586
9587         return 0;
9588 }
9589
9590 static void i9xx_update_cursor(struct intel_plane *plane,
9591                                const struct intel_crtc_state *crtc_state,
9592                                const struct intel_plane_state *plane_state)
9593 {
9594         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9595         enum pipe pipe = plane->pipe;
9596         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9597         unsigned long irqflags;
9598
9599         if (plane_state && plane_state->base.visible) {
9600                 cntl = plane_state->ctl;
9601
9602                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9603                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9604
9605                 base = intel_cursor_base(plane_state);
9606                 pos = intel_cursor_position(plane_state);
9607         }
9608
9609         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9610
9611         /*
9612          * On some platforms writing CURCNTR first will also
9613          * cause CURPOS to be armed by the CURBASE write.
9614          * Without the CURCNTR write the CURPOS write would
9615          * arm itself. Thus we always start the full update
9616          * with a CURCNTR write.
9617          *
9618          * On other platforms CURPOS always requires the
9619          * CURBASE write to arm the update. Additonally
9620          * a write to any of the cursor register will cancel
9621          * an already armed cursor update. Thus leaving out
9622          * the CURBASE write after CURPOS could lead to a
9623          * cursor that doesn't appear to move, or even change
9624          * shape. Thus we always write CURBASE.
9625          *
9626          * CURCNTR and CUR_FBC_CTL are always
9627          * armed by the CURBASE write only.
9628          */
9629         if (plane->cursor.base != base ||
9630             plane->cursor.size != fbc_ctl ||
9631             plane->cursor.cntl != cntl) {
9632                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9633                 if (HAS_CUR_FBC(dev_priv))
9634                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9635                 I915_WRITE_FW(CURPOS(pipe), pos);
9636                 I915_WRITE_FW(CURBASE(pipe), base);
9637
9638                 plane->cursor.base = base;
9639                 plane->cursor.size = fbc_ctl;
9640                 plane->cursor.cntl = cntl;
9641         } else {
9642                 I915_WRITE_FW(CURPOS(pipe), pos);
9643                 I915_WRITE_FW(CURBASE(pipe), base);
9644         }
9645
9646         POSTING_READ_FW(CURBASE(pipe));
9647
9648         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9649 }
9650
9651 static void i9xx_disable_cursor(struct intel_plane *plane,
9652                                 struct intel_crtc *crtc)
9653 {
9654         i9xx_update_cursor(plane, NULL, NULL);
9655 }
9656
9657
9658 /* VESA 640x480x72Hz mode to set on the pipe */
9659 static const struct drm_display_mode load_detect_mode = {
9660         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9661                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9662 };
9663
9664 struct drm_framebuffer *
9665 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9666                          struct drm_mode_fb_cmd2 *mode_cmd)
9667 {
9668         struct intel_framebuffer *intel_fb;
9669         int ret;
9670
9671         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9672         if (!intel_fb)
9673                 return ERR_PTR(-ENOMEM);
9674
9675         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9676         if (ret)
9677                 goto err;
9678
9679         return &intel_fb->base;
9680
9681 err:
9682         kfree(intel_fb);
9683         return ERR_PTR(ret);
9684 }
9685
9686 static u32
9687 intel_framebuffer_pitch_for_width(int width, int bpp)
9688 {
9689         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9690         return ALIGN(pitch, 64);
9691 }
9692
9693 static u32
9694 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9695 {
9696         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9697         return PAGE_ALIGN(pitch * mode->vdisplay);
9698 }
9699
9700 static struct drm_framebuffer *
9701 intel_framebuffer_create_for_mode(struct drm_device *dev,
9702                                   const struct drm_display_mode *mode,
9703                                   int depth, int bpp)
9704 {
9705         struct drm_framebuffer *fb;
9706         struct drm_i915_gem_object *obj;
9707         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9708
9709         obj = i915_gem_object_create(to_i915(dev),
9710                                     intel_framebuffer_size_for_mode(mode, bpp));
9711         if (IS_ERR(obj))
9712                 return ERR_CAST(obj);
9713
9714         mode_cmd.width = mode->hdisplay;
9715         mode_cmd.height = mode->vdisplay;
9716         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9717                                                                 bpp);
9718         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9719
9720         fb = intel_framebuffer_create(obj, &mode_cmd);
9721         if (IS_ERR(fb))
9722                 i915_gem_object_put(obj);
9723
9724         return fb;
9725 }
9726
9727 static struct drm_framebuffer *
9728 mode_fits_in_fbdev(struct drm_device *dev,
9729                    const struct drm_display_mode *mode)
9730 {
9731 #ifdef CONFIG_DRM_FBDEV_EMULATION
9732         struct drm_i915_private *dev_priv = to_i915(dev);
9733         struct drm_i915_gem_object *obj;
9734         struct drm_framebuffer *fb;
9735
9736         if (!dev_priv->fbdev)
9737                 return NULL;
9738
9739         if (!dev_priv->fbdev->fb)
9740                 return NULL;
9741
9742         obj = dev_priv->fbdev->fb->obj;
9743         BUG_ON(!obj);
9744
9745         fb = &dev_priv->fbdev->fb->base;
9746         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9747                                                                fb->format->cpp[0] * 8))
9748                 return NULL;
9749
9750         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9751                 return NULL;
9752
9753         drm_framebuffer_get(fb);
9754         return fb;
9755 #else
9756         return NULL;
9757 #endif
9758 }
9759
9760 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9761                                            struct drm_crtc *crtc,
9762                                            const struct drm_display_mode *mode,
9763                                            struct drm_framebuffer *fb,
9764                                            int x, int y)
9765 {
9766         struct drm_plane_state *plane_state;
9767         int hdisplay, vdisplay;
9768         int ret;
9769
9770         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9771         if (IS_ERR(plane_state))
9772                 return PTR_ERR(plane_state);
9773
9774         if (mode)
9775                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9776         else
9777                 hdisplay = vdisplay = 0;
9778
9779         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9780         if (ret)
9781                 return ret;
9782         drm_atomic_set_fb_for_plane(plane_state, fb);
9783         plane_state->crtc_x = 0;
9784         plane_state->crtc_y = 0;
9785         plane_state->crtc_w = hdisplay;
9786         plane_state->crtc_h = vdisplay;
9787         plane_state->src_x = x << 16;
9788         plane_state->src_y = y << 16;
9789         plane_state->src_w = hdisplay << 16;
9790         plane_state->src_h = vdisplay << 16;
9791
9792         return 0;
9793 }
9794
9795 int intel_get_load_detect_pipe(struct drm_connector *connector,
9796                                const struct drm_display_mode *mode,
9797                                struct intel_load_detect_pipe *old,
9798                                struct drm_modeset_acquire_ctx *ctx)
9799 {
9800         struct intel_crtc *intel_crtc;
9801         struct intel_encoder *intel_encoder =
9802                 intel_attached_encoder(connector);
9803         struct drm_crtc *possible_crtc;
9804         struct drm_encoder *encoder = &intel_encoder->base;
9805         struct drm_crtc *crtc = NULL;
9806         struct drm_device *dev = encoder->dev;
9807         struct drm_i915_private *dev_priv = to_i915(dev);
9808         struct drm_framebuffer *fb;
9809         struct drm_mode_config *config = &dev->mode_config;
9810         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9811         struct drm_connector_state *connector_state;
9812         struct intel_crtc_state *crtc_state;
9813         int ret, i = -1;
9814
9815         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9816                       connector->base.id, connector->name,
9817                       encoder->base.id, encoder->name);
9818
9819         old->restore_state = NULL;
9820
9821         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9822
9823         /*
9824          * Algorithm gets a little messy:
9825          *
9826          *   - if the connector already has an assigned crtc, use it (but make
9827          *     sure it's on first)
9828          *
9829          *   - try to find the first unused crtc that can drive this connector,
9830          *     and use that if we find one
9831          */
9832
9833         /* See if we already have a CRTC for this connector */
9834         if (connector->state->crtc) {
9835                 crtc = connector->state->crtc;
9836
9837                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9838                 if (ret)
9839                         goto fail;
9840
9841                 /* Make sure the crtc and connector are running */
9842                 goto found;
9843         }
9844
9845         /* Find an unused one (if possible) */
9846         for_each_crtc(dev, possible_crtc) {
9847                 i++;
9848                 if (!(encoder->possible_crtcs & (1 << i)))
9849                         continue;
9850
9851                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9852                 if (ret)
9853                         goto fail;
9854
9855                 if (possible_crtc->state->enable) {
9856                         drm_modeset_unlock(&possible_crtc->mutex);
9857                         continue;
9858                 }
9859
9860                 crtc = possible_crtc;
9861                 break;
9862         }
9863
9864         /*
9865          * If we didn't find an unused CRTC, don't use any.
9866          */
9867         if (!crtc) {
9868                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9869                 ret = -ENODEV;
9870                 goto fail;
9871         }
9872
9873 found:
9874         intel_crtc = to_intel_crtc(crtc);
9875
9876         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9877         if (ret)
9878                 goto fail;
9879
9880         state = drm_atomic_state_alloc(dev);
9881         restore_state = drm_atomic_state_alloc(dev);
9882         if (!state || !restore_state) {
9883                 ret = -ENOMEM;
9884                 goto fail;
9885         }
9886
9887         state->acquire_ctx = ctx;
9888         restore_state->acquire_ctx = ctx;
9889
9890         connector_state = drm_atomic_get_connector_state(state, connector);
9891         if (IS_ERR(connector_state)) {
9892                 ret = PTR_ERR(connector_state);
9893                 goto fail;
9894         }
9895
9896         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9897         if (ret)
9898                 goto fail;
9899
9900         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9901         if (IS_ERR(crtc_state)) {
9902                 ret = PTR_ERR(crtc_state);
9903                 goto fail;
9904         }
9905
9906         crtc_state->base.active = crtc_state->base.enable = true;
9907
9908         if (!mode)
9909                 mode = &load_detect_mode;
9910
9911         /* We need a framebuffer large enough to accommodate all accesses
9912          * that the plane may generate whilst we perform load detection.
9913          * We can not rely on the fbcon either being present (we get called
9914          * during its initialisation to detect all boot displays, or it may
9915          * not even exist) or that it is large enough to satisfy the
9916          * requested mode.
9917          */
9918         fb = mode_fits_in_fbdev(dev, mode);
9919         if (fb == NULL) {
9920                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9921                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9922         } else
9923                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9924         if (IS_ERR(fb)) {
9925                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9926                 ret = PTR_ERR(fb);
9927                 goto fail;
9928         }
9929
9930         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9931         if (ret)
9932                 goto fail;
9933
9934         drm_framebuffer_put(fb);
9935
9936         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9937         if (ret)
9938                 goto fail;
9939
9940         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9941         if (!ret)
9942                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9943         if (!ret)
9944                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9945         if (ret) {
9946                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9947                 goto fail;
9948         }
9949
9950         ret = drm_atomic_commit(state);
9951         if (ret) {
9952                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9953                 goto fail;
9954         }
9955
9956         old->restore_state = restore_state;
9957         drm_atomic_state_put(state);
9958
9959         /* let the connector get through one full cycle before testing */
9960         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9961         return true;
9962
9963 fail:
9964         if (state) {
9965                 drm_atomic_state_put(state);
9966                 state = NULL;
9967         }
9968         if (restore_state) {
9969                 drm_atomic_state_put(restore_state);
9970                 restore_state = NULL;
9971         }
9972
9973         if (ret == -EDEADLK)
9974                 return ret;
9975
9976         return false;
9977 }
9978
9979 void intel_release_load_detect_pipe(struct drm_connector *connector,
9980                                     struct intel_load_detect_pipe *old,
9981                                     struct drm_modeset_acquire_ctx *ctx)
9982 {
9983         struct intel_encoder *intel_encoder =
9984                 intel_attached_encoder(connector);
9985         struct drm_encoder *encoder = &intel_encoder->base;
9986         struct drm_atomic_state *state = old->restore_state;
9987         int ret;
9988
9989         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9990                       connector->base.id, connector->name,
9991                       encoder->base.id, encoder->name);
9992
9993         if (!state)
9994                 return;
9995
9996         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9997         if (ret)
9998                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9999         drm_atomic_state_put(state);
10000 }
10001
10002 static int i9xx_pll_refclk(struct drm_device *dev,
10003                            const struct intel_crtc_state *pipe_config)
10004 {
10005         struct drm_i915_private *dev_priv = to_i915(dev);
10006         u32 dpll = pipe_config->dpll_hw_state.dpll;
10007
10008         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10009                 return dev_priv->vbt.lvds_ssc_freq;
10010         else if (HAS_PCH_SPLIT(dev_priv))
10011                 return 120000;
10012         else if (!IS_GEN2(dev_priv))
10013                 return 96000;
10014         else
10015                 return 48000;
10016 }
10017
10018 /* Returns the clock of the currently programmed mode of the given pipe. */
10019 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10020                                 struct intel_crtc_state *pipe_config)
10021 {
10022         struct drm_device *dev = crtc->base.dev;
10023         struct drm_i915_private *dev_priv = to_i915(dev);
10024         int pipe = pipe_config->cpu_transcoder;
10025         u32 dpll = pipe_config->dpll_hw_state.dpll;
10026         u32 fp;
10027         struct dpll clock;
10028         int port_clock;
10029         int refclk = i9xx_pll_refclk(dev, pipe_config);
10030
10031         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10032                 fp = pipe_config->dpll_hw_state.fp0;
10033         else
10034                 fp = pipe_config->dpll_hw_state.fp1;
10035
10036         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10037         if (IS_PINEVIEW(dev_priv)) {
10038                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10039                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10040         } else {
10041                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10042                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10043         }
10044
10045         if (!IS_GEN2(dev_priv)) {
10046                 if (IS_PINEVIEW(dev_priv))
10047                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10048                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10049                 else
10050                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10051                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10052
10053                 switch (dpll & DPLL_MODE_MASK) {
10054                 case DPLLB_MODE_DAC_SERIAL:
10055                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10056                                 5 : 10;
10057                         break;
10058                 case DPLLB_MODE_LVDS:
10059                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10060                                 7 : 14;
10061                         break;
10062                 default:
10063                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10064                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10065                         return;
10066                 }
10067
10068                 if (IS_PINEVIEW(dev_priv))
10069                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10070                 else
10071                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10072         } else {
10073                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10074                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10075
10076                 if (is_lvds) {
10077                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10078                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10079
10080                         if (lvds & LVDS_CLKB_POWER_UP)
10081                                 clock.p2 = 7;
10082                         else
10083                                 clock.p2 = 14;
10084                 } else {
10085                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10086                                 clock.p1 = 2;
10087                         else {
10088                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10089                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10090                         }
10091                         if (dpll & PLL_P2_DIVIDE_BY_4)
10092                                 clock.p2 = 4;
10093                         else
10094                                 clock.p2 = 2;
10095                 }
10096
10097                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10098         }
10099
10100         /*
10101          * This value includes pixel_multiplier. We will use
10102          * port_clock to compute adjusted_mode.crtc_clock in the
10103          * encoder's get_config() function.
10104          */
10105         pipe_config->port_clock = port_clock;
10106 }
10107
10108 int intel_dotclock_calculate(int link_freq,
10109                              const struct intel_link_m_n *m_n)
10110 {
10111         /*
10112          * The calculation for the data clock is:
10113          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10114          * But we want to avoid losing precison if possible, so:
10115          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10116          *
10117          * and the link clock is simpler:
10118          * link_clock = (m * link_clock) / n
10119          */
10120
10121         if (!m_n->link_n)
10122                 return 0;
10123
10124         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10125 }
10126
10127 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10128                                    struct intel_crtc_state *pipe_config)
10129 {
10130         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10131
10132         /* read out port_clock from the DPLL */
10133         i9xx_crtc_clock_get(crtc, pipe_config);
10134
10135         /*
10136          * In case there is an active pipe without active ports,
10137          * we may need some idea for the dotclock anyway.
10138          * Calculate one based on the FDI configuration.
10139          */
10140         pipe_config->base.adjusted_mode.crtc_clock =
10141                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10142                                          &pipe_config->fdi_m_n);
10143 }
10144
10145 /* Returns the currently programmed mode of the given encoder. */
10146 struct drm_display_mode *
10147 intel_encoder_current_mode(struct intel_encoder *encoder)
10148 {
10149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10150         struct intel_crtc_state *crtc_state;
10151         struct drm_display_mode *mode;
10152         struct intel_crtc *crtc;
10153         enum pipe pipe;
10154
10155         if (!encoder->get_hw_state(encoder, &pipe))
10156                 return NULL;
10157
10158         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10159
10160         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10161         if (!mode)
10162                 return NULL;
10163
10164         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10165         if (!crtc_state) {
10166                 kfree(mode);
10167                 return NULL;
10168         }
10169
10170         crtc_state->base.crtc = &crtc->base;
10171
10172         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10173                 kfree(crtc_state);
10174                 kfree(mode);
10175                 return NULL;
10176         }
10177
10178         encoder->get_config(encoder, crtc_state);
10179
10180         intel_mode_from_pipe_config(mode, crtc_state);
10181
10182         kfree(crtc_state);
10183
10184         return mode;
10185 }
10186
10187 static void intel_crtc_destroy(struct drm_crtc *crtc)
10188 {
10189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10190
10191         drm_crtc_cleanup(crtc);
10192         kfree(intel_crtc);
10193 }
10194
10195 /**
10196  * intel_wm_need_update - Check whether watermarks need updating
10197  * @plane: drm plane
10198  * @state: new plane state
10199  *
10200  * Check current plane state versus the new one to determine whether
10201  * watermarks need to be recalculated.
10202  *
10203  * Returns true or false.
10204  */
10205 static bool intel_wm_need_update(struct drm_plane *plane,
10206                                  struct drm_plane_state *state)
10207 {
10208         struct intel_plane_state *new = to_intel_plane_state(state);
10209         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10210
10211         /* Update watermarks on tiling or size changes. */
10212         if (new->base.visible != cur->base.visible)
10213                 return true;
10214
10215         if (!cur->base.fb || !new->base.fb)
10216                 return false;
10217
10218         if (cur->base.fb->modifier != new->base.fb->modifier ||
10219             cur->base.rotation != new->base.rotation ||
10220             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10221             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10222             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10223             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10224                 return true;
10225
10226         return false;
10227 }
10228
10229 static bool needs_scaling(const struct intel_plane_state *state)
10230 {
10231         int src_w = drm_rect_width(&state->base.src) >> 16;
10232         int src_h = drm_rect_height(&state->base.src) >> 16;
10233         int dst_w = drm_rect_width(&state->base.dst);
10234         int dst_h = drm_rect_height(&state->base.dst);
10235
10236         return (src_w != dst_w || src_h != dst_h);
10237 }
10238
10239 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10240                                     struct drm_crtc_state *crtc_state,
10241                                     const struct intel_plane_state *old_plane_state,
10242                                     struct drm_plane_state *plane_state)
10243 {
10244         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10245         struct drm_crtc *crtc = crtc_state->crtc;
10246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10247         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10248         struct drm_device *dev = crtc->dev;
10249         struct drm_i915_private *dev_priv = to_i915(dev);
10250         bool mode_changed = needs_modeset(crtc_state);
10251         bool was_crtc_enabled = old_crtc_state->base.active;
10252         bool is_crtc_enabled = crtc_state->active;
10253         bool turn_off, turn_on, visible, was_visible;
10254         struct drm_framebuffer *fb = plane_state->fb;
10255         int ret;
10256
10257         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10258                 ret = skl_update_scaler_plane(
10259                         to_intel_crtc_state(crtc_state),
10260                         to_intel_plane_state(plane_state));
10261                 if (ret)
10262                         return ret;
10263         }
10264
10265         was_visible = old_plane_state->base.visible;
10266         visible = plane_state->visible;
10267
10268         if (!was_crtc_enabled && WARN_ON(was_visible))
10269                 was_visible = false;
10270
10271         /*
10272          * Visibility is calculated as if the crtc was on, but
10273          * after scaler setup everything depends on it being off
10274          * when the crtc isn't active.
10275          *
10276          * FIXME this is wrong for watermarks. Watermarks should also
10277          * be computed as if the pipe would be active. Perhaps move
10278          * per-plane wm computation to the .check_plane() hook, and
10279          * only combine the results from all planes in the current place?
10280          */
10281         if (!is_crtc_enabled) {
10282                 plane_state->visible = visible = false;
10283                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10284         }
10285
10286         if (!was_visible && !visible)
10287                 return 0;
10288
10289         if (fb != old_plane_state->base.fb)
10290                 pipe_config->fb_changed = true;
10291
10292         turn_off = was_visible && (!visible || mode_changed);
10293         turn_on = visible && (!was_visible || mode_changed);
10294
10295         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10296                          intel_crtc->base.base.id, intel_crtc->base.name,
10297                          plane->base.base.id, plane->base.name,
10298                          fb ? fb->base.id : -1);
10299
10300         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10301                          plane->base.base.id, plane->base.name,
10302                          was_visible, visible,
10303                          turn_off, turn_on, mode_changed);
10304
10305         if (turn_on) {
10306                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10307                         pipe_config->update_wm_pre = true;
10308
10309                 /* must disable cxsr around plane enable/disable */
10310                 if (plane->id != PLANE_CURSOR)
10311                         pipe_config->disable_cxsr = true;
10312         } else if (turn_off) {
10313                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10314                         pipe_config->update_wm_post = true;
10315
10316                 /* must disable cxsr around plane enable/disable */
10317                 if (plane->id != PLANE_CURSOR)
10318                         pipe_config->disable_cxsr = true;
10319         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10320                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10321                         /* FIXME bollocks */
10322                         pipe_config->update_wm_pre = true;
10323                         pipe_config->update_wm_post = true;
10324                 }
10325         }
10326
10327         if (visible || was_visible)
10328                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10329
10330         /*
10331          * WaCxSRDisabledForSpriteScaling:ivb
10332          *
10333          * cstate->update_wm was already set above, so this flag will
10334          * take effect when we commit and program watermarks.
10335          */
10336         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10337             needs_scaling(to_intel_plane_state(plane_state)) &&
10338             !needs_scaling(old_plane_state))
10339                 pipe_config->disable_lp_wm = true;
10340
10341         return 0;
10342 }
10343
10344 static bool encoders_cloneable(const struct intel_encoder *a,
10345                                const struct intel_encoder *b)
10346 {
10347         /* masks could be asymmetric, so check both ways */
10348         return a == b || (a->cloneable & (1 << b->type) &&
10349                           b->cloneable & (1 << a->type));
10350 }
10351
10352 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10353                                          struct intel_crtc *crtc,
10354                                          struct intel_encoder *encoder)
10355 {
10356         struct intel_encoder *source_encoder;
10357         struct drm_connector *connector;
10358         struct drm_connector_state *connector_state;
10359         int i;
10360
10361         for_each_new_connector_in_state(state, connector, connector_state, i) {
10362                 if (connector_state->crtc != &crtc->base)
10363                         continue;
10364
10365                 source_encoder =
10366                         to_intel_encoder(connector_state->best_encoder);
10367                 if (!encoders_cloneable(encoder, source_encoder))
10368                         return false;
10369         }
10370
10371         return true;
10372 }
10373
10374 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10375                                    struct drm_crtc_state *crtc_state)
10376 {
10377         struct drm_device *dev = crtc->dev;
10378         struct drm_i915_private *dev_priv = to_i915(dev);
10379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10380         struct intel_crtc_state *pipe_config =
10381                 to_intel_crtc_state(crtc_state);
10382         struct drm_atomic_state *state = crtc_state->state;
10383         int ret;
10384         bool mode_changed = needs_modeset(crtc_state);
10385
10386         if (mode_changed && !crtc_state->active)
10387                 pipe_config->update_wm_post = true;
10388
10389         if (mode_changed && crtc_state->enable &&
10390             dev_priv->display.crtc_compute_clock &&
10391             !WARN_ON(pipe_config->shared_dpll)) {
10392                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10393                                                            pipe_config);
10394                 if (ret)
10395                         return ret;
10396         }
10397
10398         if (crtc_state->color_mgmt_changed) {
10399                 ret = intel_color_check(crtc, crtc_state);
10400                 if (ret)
10401                         return ret;
10402
10403                 /*
10404                  * Changing color management on Intel hardware is
10405                  * handled as part of planes update.
10406                  */
10407                 crtc_state->planes_changed = true;
10408         }
10409
10410         ret = 0;
10411         if (dev_priv->display.compute_pipe_wm) {
10412                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10413                 if (ret) {
10414                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10415                         return ret;
10416                 }
10417         }
10418
10419         if (dev_priv->display.compute_intermediate_wm &&
10420             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10421                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10422                         return 0;
10423
10424                 /*
10425                  * Calculate 'intermediate' watermarks that satisfy both the
10426                  * old state and the new state.  We can program these
10427                  * immediately.
10428                  */
10429                 ret = dev_priv->display.compute_intermediate_wm(dev,
10430                                                                 intel_crtc,
10431                                                                 pipe_config);
10432                 if (ret) {
10433                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10434                         return ret;
10435                 }
10436         } else if (dev_priv->display.compute_intermediate_wm) {
10437                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10438                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10439         }
10440
10441         if (INTEL_GEN(dev_priv) >= 9) {
10442                 if (mode_changed)
10443                         ret = skl_update_scaler_crtc(pipe_config);
10444
10445                 if (!ret)
10446                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10447                                                             pipe_config);
10448                 if (!ret)
10449                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10450                                                          pipe_config);
10451         }
10452
10453         return ret;
10454 }
10455
10456 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10457         .atomic_begin = intel_begin_crtc_commit,
10458         .atomic_flush = intel_finish_crtc_commit,
10459         .atomic_check = intel_crtc_atomic_check,
10460 };
10461
10462 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10463 {
10464         struct intel_connector *connector;
10465         struct drm_connector_list_iter conn_iter;
10466
10467         drm_connector_list_iter_begin(dev, &conn_iter);
10468         for_each_intel_connector_iter(connector, &conn_iter) {
10469                 if (connector->base.state->crtc)
10470                         drm_connector_unreference(&connector->base);
10471
10472                 if (connector->base.encoder) {
10473                         connector->base.state->best_encoder =
10474                                 connector->base.encoder;
10475                         connector->base.state->crtc =
10476                                 connector->base.encoder->crtc;
10477
10478                         drm_connector_reference(&connector->base);
10479                 } else {
10480                         connector->base.state->best_encoder = NULL;
10481                         connector->base.state->crtc = NULL;
10482                 }
10483         }
10484         drm_connector_list_iter_end(&conn_iter);
10485 }
10486
10487 static void
10488 connected_sink_compute_bpp(struct intel_connector *connector,
10489                            struct intel_crtc_state *pipe_config)
10490 {
10491         const struct drm_display_info *info = &connector->base.display_info;
10492         int bpp = pipe_config->pipe_bpp;
10493
10494         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10495                       connector->base.base.id,
10496                       connector->base.name);
10497
10498         /* Don't use an invalid EDID bpc value */
10499         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10500                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10501                               bpp, info->bpc * 3);
10502                 pipe_config->pipe_bpp = info->bpc * 3;
10503         }
10504
10505         /* Clamp bpp to 8 on screens without EDID 1.4 */
10506         if (info->bpc == 0 && bpp > 24) {
10507                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10508                               bpp);
10509                 pipe_config->pipe_bpp = 24;
10510         }
10511 }
10512
10513 static int
10514 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10515                           struct intel_crtc_state *pipe_config)
10516 {
10517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10518         struct drm_atomic_state *state;
10519         struct drm_connector *connector;
10520         struct drm_connector_state *connector_state;
10521         int bpp, i;
10522
10523         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10524             IS_CHERRYVIEW(dev_priv)))
10525                 bpp = 10*3;
10526         else if (INTEL_GEN(dev_priv) >= 5)
10527                 bpp = 12*3;
10528         else
10529                 bpp = 8*3;
10530
10531
10532         pipe_config->pipe_bpp = bpp;
10533
10534         state = pipe_config->base.state;
10535
10536         /* Clamp display bpp to EDID value */
10537         for_each_new_connector_in_state(state, connector, connector_state, i) {
10538                 if (connector_state->crtc != &crtc->base)
10539                         continue;
10540
10541                 connected_sink_compute_bpp(to_intel_connector(connector),
10542                                            pipe_config);
10543         }
10544
10545         return bpp;
10546 }
10547
10548 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10549 {
10550         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10551                         "type: 0x%x flags: 0x%x\n",
10552                 mode->crtc_clock,
10553                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10554                 mode->crtc_hsync_end, mode->crtc_htotal,
10555                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10556                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10557 }
10558
10559 static inline void
10560 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10561                       unsigned int lane_count, struct intel_link_m_n *m_n)
10562 {
10563         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10564                       id, lane_count,
10565                       m_n->gmch_m, m_n->gmch_n,
10566                       m_n->link_m, m_n->link_n, m_n->tu);
10567 }
10568
10569 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10570
10571 static const char * const output_type_str[] = {
10572         OUTPUT_TYPE(UNUSED),
10573         OUTPUT_TYPE(ANALOG),
10574         OUTPUT_TYPE(DVO),
10575         OUTPUT_TYPE(SDVO),
10576         OUTPUT_TYPE(LVDS),
10577         OUTPUT_TYPE(TVOUT),
10578         OUTPUT_TYPE(HDMI),
10579         OUTPUT_TYPE(DP),
10580         OUTPUT_TYPE(EDP),
10581         OUTPUT_TYPE(DSI),
10582         OUTPUT_TYPE(DDI),
10583         OUTPUT_TYPE(DP_MST),
10584 };
10585
10586 #undef OUTPUT_TYPE
10587
10588 static void snprintf_output_types(char *buf, size_t len,
10589                                   unsigned int output_types)
10590 {
10591         char *str = buf;
10592         int i;
10593
10594         str[0] = '\0';
10595
10596         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10597                 int r;
10598
10599                 if ((output_types & BIT(i)) == 0)
10600                         continue;
10601
10602                 r = snprintf(str, len, "%s%s",
10603                              str != buf ? "," : "", output_type_str[i]);
10604                 if (r >= len)
10605                         break;
10606                 str += r;
10607                 len -= r;
10608
10609                 output_types &= ~BIT(i);
10610         }
10611
10612         WARN_ON_ONCE(output_types != 0);
10613 }
10614
10615 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10616                                    struct intel_crtc_state *pipe_config,
10617                                    const char *context)
10618 {
10619         struct drm_device *dev = crtc->base.dev;
10620         struct drm_i915_private *dev_priv = to_i915(dev);
10621         struct drm_plane *plane;
10622         struct intel_plane *intel_plane;
10623         struct intel_plane_state *state;
10624         struct drm_framebuffer *fb;
10625         char buf[64];
10626
10627         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10628                       crtc->base.base.id, crtc->base.name, context);
10629
10630         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10631         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10632                       buf, pipe_config->output_types);
10633
10634         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10635                       transcoder_name(pipe_config->cpu_transcoder),
10636                       pipe_config->pipe_bpp, pipe_config->dither);
10637
10638         if (pipe_config->has_pch_encoder)
10639                 intel_dump_m_n_config(pipe_config, "fdi",
10640                                       pipe_config->fdi_lanes,
10641                                       &pipe_config->fdi_m_n);
10642
10643         if (pipe_config->ycbcr420)
10644                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10645
10646         if (intel_crtc_has_dp_encoder(pipe_config)) {
10647                 intel_dump_m_n_config(pipe_config, "dp m_n",
10648                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10649                 if (pipe_config->has_drrs)
10650                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10651                                               pipe_config->lane_count,
10652                                               &pipe_config->dp_m2_n2);
10653         }
10654
10655         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10656                       pipe_config->has_audio, pipe_config->has_infoframe);
10657
10658         DRM_DEBUG_KMS("requested mode:\n");
10659         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10660         DRM_DEBUG_KMS("adjusted mode:\n");
10661         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10662         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10663         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10664                       pipe_config->port_clock,
10665                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10666                       pipe_config->pixel_rate);
10667
10668         if (INTEL_GEN(dev_priv) >= 9)
10669                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10670                               crtc->num_scalers,
10671                               pipe_config->scaler_state.scaler_users,
10672                               pipe_config->scaler_state.scaler_id);
10673
10674         if (HAS_GMCH_DISPLAY(dev_priv))
10675                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10676                               pipe_config->gmch_pfit.control,
10677                               pipe_config->gmch_pfit.pgm_ratios,
10678                               pipe_config->gmch_pfit.lvds_border_bits);
10679         else
10680                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10681                               pipe_config->pch_pfit.pos,
10682                               pipe_config->pch_pfit.size,
10683                               enableddisabled(pipe_config->pch_pfit.enabled));
10684
10685         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10686                       pipe_config->ips_enabled, pipe_config->double_wide);
10687
10688         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10689
10690         DRM_DEBUG_KMS("planes on this crtc\n");
10691         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10692                 struct drm_format_name_buf format_name;
10693                 intel_plane = to_intel_plane(plane);
10694                 if (intel_plane->pipe != crtc->pipe)
10695                         continue;
10696
10697                 state = to_intel_plane_state(plane->state);
10698                 fb = state->base.fb;
10699                 if (!fb) {
10700                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10701                                       plane->base.id, plane->name, state->scaler_id);
10702                         continue;
10703                 }
10704
10705                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10706                               plane->base.id, plane->name,
10707                               fb->base.id, fb->width, fb->height,
10708                               drm_get_format_name(fb->format->format, &format_name));
10709                 if (INTEL_GEN(dev_priv) >= 9)
10710                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10711                                       state->scaler_id,
10712                                       state->base.src.x1 >> 16,
10713                                       state->base.src.y1 >> 16,
10714                                       drm_rect_width(&state->base.src) >> 16,
10715                                       drm_rect_height(&state->base.src) >> 16,
10716                                       state->base.dst.x1, state->base.dst.y1,
10717                                       drm_rect_width(&state->base.dst),
10718                                       drm_rect_height(&state->base.dst));
10719         }
10720 }
10721
10722 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10723 {
10724         struct drm_device *dev = state->dev;
10725         struct drm_connector *connector;
10726         struct drm_connector_list_iter conn_iter;
10727         unsigned int used_ports = 0;
10728         unsigned int used_mst_ports = 0;
10729
10730         /*
10731          * Walk the connector list instead of the encoder
10732          * list to detect the problem on ddi platforms
10733          * where there's just one encoder per digital port.
10734          */
10735         drm_connector_list_iter_begin(dev, &conn_iter);
10736         drm_for_each_connector_iter(connector, &conn_iter) {
10737                 struct drm_connector_state *connector_state;
10738                 struct intel_encoder *encoder;
10739
10740                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10741                 if (!connector_state)
10742                         connector_state = connector->state;
10743
10744                 if (!connector_state->best_encoder)
10745                         continue;
10746
10747                 encoder = to_intel_encoder(connector_state->best_encoder);
10748
10749                 WARN_ON(!connector_state->crtc);
10750
10751                 switch (encoder->type) {
10752                         unsigned int port_mask;
10753                 case INTEL_OUTPUT_DDI:
10754                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10755                                 break;
10756                 case INTEL_OUTPUT_DP:
10757                 case INTEL_OUTPUT_HDMI:
10758                 case INTEL_OUTPUT_EDP:
10759                         port_mask = 1 << encoder->port;
10760
10761                         /* the same port mustn't appear more than once */
10762                         if (used_ports & port_mask)
10763                                 return false;
10764
10765                         used_ports |= port_mask;
10766                         break;
10767                 case INTEL_OUTPUT_DP_MST:
10768                         used_mst_ports |=
10769                                 1 << encoder->port;
10770                         break;
10771                 default:
10772                         break;
10773                 }
10774         }
10775         drm_connector_list_iter_end(&conn_iter);
10776
10777         /* can't mix MST and SST/HDMI on the same port */
10778         if (used_ports & used_mst_ports)
10779                 return false;
10780
10781         return true;
10782 }
10783
10784 static void
10785 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10786 {
10787         struct drm_i915_private *dev_priv =
10788                 to_i915(crtc_state->base.crtc->dev);
10789         struct intel_crtc_scaler_state scaler_state;
10790         struct intel_dpll_hw_state dpll_hw_state;
10791         struct intel_shared_dpll *shared_dpll;
10792         struct intel_crtc_wm_state wm_state;
10793         bool force_thru, ips_force_disable;
10794
10795         /* FIXME: before the switch to atomic started, a new pipe_config was
10796          * kzalloc'd. Code that depends on any field being zero should be
10797          * fixed, so that the crtc_state can be safely duplicated. For now,
10798          * only fields that are know to not cause problems are preserved. */
10799
10800         scaler_state = crtc_state->scaler_state;
10801         shared_dpll = crtc_state->shared_dpll;
10802         dpll_hw_state = crtc_state->dpll_hw_state;
10803         force_thru = crtc_state->pch_pfit.force_thru;
10804         ips_force_disable = crtc_state->ips_force_disable;
10805         if (IS_G4X(dev_priv) ||
10806             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10807                 wm_state = crtc_state->wm;
10808
10809         /* Keep base drm_crtc_state intact, only clear our extended struct */
10810         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10811         memset(&crtc_state->base + 1, 0,
10812                sizeof(*crtc_state) - sizeof(crtc_state->base));
10813
10814         crtc_state->scaler_state = scaler_state;
10815         crtc_state->shared_dpll = shared_dpll;
10816         crtc_state->dpll_hw_state = dpll_hw_state;
10817         crtc_state->pch_pfit.force_thru = force_thru;
10818         crtc_state->ips_force_disable = ips_force_disable;
10819         if (IS_G4X(dev_priv) ||
10820             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10821                 crtc_state->wm = wm_state;
10822 }
10823
10824 static int
10825 intel_modeset_pipe_config(struct drm_crtc *crtc,
10826                           struct intel_crtc_state *pipe_config)
10827 {
10828         struct drm_atomic_state *state = pipe_config->base.state;
10829         struct intel_encoder *encoder;
10830         struct drm_connector *connector;
10831         struct drm_connector_state *connector_state;
10832         int base_bpp, ret = -EINVAL;
10833         int i;
10834         bool retry = true;
10835
10836         clear_intel_crtc_state(pipe_config);
10837
10838         pipe_config->cpu_transcoder =
10839                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10840
10841         /*
10842          * Sanitize sync polarity flags based on requested ones. If neither
10843          * positive or negative polarity is requested, treat this as meaning
10844          * negative polarity.
10845          */
10846         if (!(pipe_config->base.adjusted_mode.flags &
10847               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10848                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10849
10850         if (!(pipe_config->base.adjusted_mode.flags &
10851               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10852                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10853
10854         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10855                                              pipe_config);
10856         if (base_bpp < 0)
10857                 goto fail;
10858
10859         /*
10860          * Determine the real pipe dimensions. Note that stereo modes can
10861          * increase the actual pipe size due to the frame doubling and
10862          * insertion of additional space for blanks between the frame. This
10863          * is stored in the crtc timings. We use the requested mode to do this
10864          * computation to clearly distinguish it from the adjusted mode, which
10865          * can be changed by the connectors in the below retry loop.
10866          */
10867         drm_mode_get_hv_timing(&pipe_config->base.mode,
10868                                &pipe_config->pipe_src_w,
10869                                &pipe_config->pipe_src_h);
10870
10871         for_each_new_connector_in_state(state, connector, connector_state, i) {
10872                 if (connector_state->crtc != crtc)
10873                         continue;
10874
10875                 encoder = to_intel_encoder(connector_state->best_encoder);
10876
10877                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10878                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10879                         goto fail;
10880                 }
10881
10882                 /*
10883                  * Determine output_types before calling the .compute_config()
10884                  * hooks so that the hooks can use this information safely.
10885                  */
10886                 if (encoder->compute_output_type)
10887                         pipe_config->output_types |=
10888                                 BIT(encoder->compute_output_type(encoder, pipe_config,
10889                                                                  connector_state));
10890                 else
10891                         pipe_config->output_types |= BIT(encoder->type);
10892         }
10893
10894 encoder_retry:
10895         /* Ensure the port clock defaults are reset when retrying. */
10896         pipe_config->port_clock = 0;
10897         pipe_config->pixel_multiplier = 1;
10898
10899         /* Fill in default crtc timings, allow encoders to overwrite them. */
10900         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10901                               CRTC_STEREO_DOUBLE);
10902
10903         /* Pass our mode to the connectors and the CRTC to give them a chance to
10904          * adjust it according to limitations or connector properties, and also
10905          * a chance to reject the mode entirely.
10906          */
10907         for_each_new_connector_in_state(state, connector, connector_state, i) {
10908                 if (connector_state->crtc != crtc)
10909                         continue;
10910
10911                 encoder = to_intel_encoder(connector_state->best_encoder);
10912
10913                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10914                         DRM_DEBUG_KMS("Encoder config failure\n");
10915                         goto fail;
10916                 }
10917         }
10918
10919         /* Set default port clock if not overwritten by the encoder. Needs to be
10920          * done afterwards in case the encoder adjusts the mode. */
10921         if (!pipe_config->port_clock)
10922                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10923                         * pipe_config->pixel_multiplier;
10924
10925         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10926         if (ret < 0) {
10927                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10928                 goto fail;
10929         }
10930
10931         if (ret == RETRY) {
10932                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10933                         ret = -EINVAL;
10934                         goto fail;
10935                 }
10936
10937                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10938                 retry = false;
10939                 goto encoder_retry;
10940         }
10941
10942         /* Dithering seems to not pass-through bits correctly when it should, so
10943          * only enable it on 6bpc panels and when its not a compliance
10944          * test requesting 6bpc video pattern.
10945          */
10946         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10947                 !pipe_config->dither_force_disable;
10948         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10949                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10950
10951 fail:
10952         return ret;
10953 }
10954
10955 static void
10956 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10957 {
10958         struct drm_crtc *crtc;
10959         struct drm_crtc_state *new_crtc_state;
10960         int i;
10961
10962         /* Double check state. */
10963         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10964                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10965
10966                 /*
10967                  * Update legacy state to satisfy fbc code. This can
10968                  * be removed when fbc uses the atomic state.
10969                  */
10970                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10971                         struct drm_plane_state *plane_state = crtc->primary->state;
10972
10973                         crtc->primary->fb = plane_state->fb;
10974                         crtc->x = plane_state->src_x >> 16;
10975                         crtc->y = plane_state->src_y >> 16;
10976                 }
10977         }
10978 }
10979
10980 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10981 {
10982         int diff;
10983
10984         if (clock1 == clock2)
10985                 return true;
10986
10987         if (!clock1 || !clock2)
10988                 return false;
10989
10990         diff = abs(clock1 - clock2);
10991
10992         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10993                 return true;
10994
10995         return false;
10996 }
10997
10998 static bool
10999 intel_compare_m_n(unsigned int m, unsigned int n,
11000                   unsigned int m2, unsigned int n2,
11001                   bool exact)
11002 {
11003         if (m == m2 && n == n2)
11004                 return true;
11005
11006         if (exact || !m || !n || !m2 || !n2)
11007                 return false;
11008
11009         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11010
11011         if (n > n2) {
11012                 while (n > n2) {
11013                         m2 <<= 1;
11014                         n2 <<= 1;
11015                 }
11016         } else if (n < n2) {
11017                 while (n < n2) {
11018                         m <<= 1;
11019                         n <<= 1;
11020                 }
11021         }
11022
11023         if (n != n2)
11024                 return false;
11025
11026         return intel_fuzzy_clock_check(m, m2);
11027 }
11028
11029 static bool
11030 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11031                        struct intel_link_m_n *m2_n2,
11032                        bool adjust)
11033 {
11034         if (m_n->tu == m2_n2->tu &&
11035             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11036                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11037             intel_compare_m_n(m_n->link_m, m_n->link_n,
11038                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11039                 if (adjust)
11040                         *m2_n2 = *m_n;
11041
11042                 return true;
11043         }
11044
11045         return false;
11046 }
11047
11048 static void __printf(3, 4)
11049 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11050 {
11051         char *level;
11052         unsigned int category;
11053         struct va_format vaf;
11054         va_list args;
11055
11056         if (adjust) {
11057                 level = KERN_DEBUG;
11058                 category = DRM_UT_KMS;
11059         } else {
11060                 level = KERN_ERR;
11061                 category = DRM_UT_NONE;
11062         }
11063
11064         va_start(args, format);
11065         vaf.fmt = format;
11066         vaf.va = &args;
11067
11068         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11069
11070         va_end(args);
11071 }
11072
11073 static bool
11074 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11075                           struct intel_crtc_state *current_config,
11076                           struct intel_crtc_state *pipe_config,
11077                           bool adjust)
11078 {
11079         bool ret = true;
11080
11081 #define PIPE_CONF_CHECK_X(name) \
11082         if (current_config->name != pipe_config->name) { \
11083                 pipe_config_err(adjust, __stringify(name), \
11084                           "(expected 0x%08x, found 0x%08x)\n", \
11085                           current_config->name, \
11086                           pipe_config->name); \
11087                 ret = false; \
11088         }
11089
11090 #define PIPE_CONF_CHECK_I(name) \
11091         if (current_config->name != pipe_config->name) { \
11092                 pipe_config_err(adjust, __stringify(name), \
11093                           "(expected %i, found %i)\n", \
11094                           current_config->name, \
11095                           pipe_config->name); \
11096                 ret = false; \
11097         }
11098
11099 #define PIPE_CONF_CHECK_P(name) \
11100         if (current_config->name != pipe_config->name) { \
11101                 pipe_config_err(adjust, __stringify(name), \
11102                           "(expected %p, found %p)\n", \
11103                           current_config->name, \
11104                           pipe_config->name); \
11105                 ret = false; \
11106         }
11107
11108 #define PIPE_CONF_CHECK_M_N(name) \
11109         if (!intel_compare_link_m_n(&current_config->name, \
11110                                     &pipe_config->name,\
11111                                     adjust)) { \
11112                 pipe_config_err(adjust, __stringify(name), \
11113                           "(expected tu %i gmch %i/%i link %i/%i, " \
11114                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11115                           current_config->name.tu, \
11116                           current_config->name.gmch_m, \
11117                           current_config->name.gmch_n, \
11118                           current_config->name.link_m, \
11119                           current_config->name.link_n, \
11120                           pipe_config->name.tu, \
11121                           pipe_config->name.gmch_m, \
11122                           pipe_config->name.gmch_n, \
11123                           pipe_config->name.link_m, \
11124                           pipe_config->name.link_n); \
11125                 ret = false; \
11126         }
11127
11128 /* This is required for BDW+ where there is only one set of registers for
11129  * switching between high and low RR.
11130  * This macro can be used whenever a comparison has to be made between one
11131  * hw state and multiple sw state variables.
11132  */
11133 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11134         if (!intel_compare_link_m_n(&current_config->name, \
11135                                     &pipe_config->name, adjust) && \
11136             !intel_compare_link_m_n(&current_config->alt_name, \
11137                                     &pipe_config->name, adjust)) { \
11138                 pipe_config_err(adjust, __stringify(name), \
11139                           "(expected tu %i gmch %i/%i link %i/%i, " \
11140                           "or tu %i gmch %i/%i link %i/%i, " \
11141                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11142                           current_config->name.tu, \
11143                           current_config->name.gmch_m, \
11144                           current_config->name.gmch_n, \
11145                           current_config->name.link_m, \
11146                           current_config->name.link_n, \
11147                           current_config->alt_name.tu, \
11148                           current_config->alt_name.gmch_m, \
11149                           current_config->alt_name.gmch_n, \
11150                           current_config->alt_name.link_m, \
11151                           current_config->alt_name.link_n, \
11152                           pipe_config->name.tu, \
11153                           pipe_config->name.gmch_m, \
11154                           pipe_config->name.gmch_n, \
11155                           pipe_config->name.link_m, \
11156                           pipe_config->name.link_n); \
11157                 ret = false; \
11158         }
11159
11160 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11161         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11162                 pipe_config_err(adjust, __stringify(name), \
11163                           "(%x) (expected %i, found %i)\n", \
11164                           (mask), \
11165                           current_config->name & (mask), \
11166                           pipe_config->name & (mask)); \
11167                 ret = false; \
11168         }
11169
11170 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11171         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11172                 pipe_config_err(adjust, __stringify(name), \
11173                           "(expected %i, found %i)\n", \
11174                           current_config->name, \
11175                           pipe_config->name); \
11176                 ret = false; \
11177         }
11178
11179 #define PIPE_CONF_QUIRK(quirk)  \
11180         ((current_config->quirks | pipe_config->quirks) & (quirk))
11181
11182         PIPE_CONF_CHECK_I(cpu_transcoder);
11183
11184         PIPE_CONF_CHECK_I(has_pch_encoder);
11185         PIPE_CONF_CHECK_I(fdi_lanes);
11186         PIPE_CONF_CHECK_M_N(fdi_m_n);
11187
11188         PIPE_CONF_CHECK_I(lane_count);
11189         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11190
11191         if (INTEL_GEN(dev_priv) < 8) {
11192                 PIPE_CONF_CHECK_M_N(dp_m_n);
11193
11194                 if (current_config->has_drrs)
11195                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11196         } else
11197                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11198
11199         PIPE_CONF_CHECK_X(output_types);
11200
11201         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11202         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11203         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11204         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11205         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11206         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11207
11208         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11209         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11210         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11211         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11212         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11213         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11214
11215         PIPE_CONF_CHECK_I(pixel_multiplier);
11216         PIPE_CONF_CHECK_I(has_hdmi_sink);
11217         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11218             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11219                 PIPE_CONF_CHECK_I(limited_color_range);
11220
11221         PIPE_CONF_CHECK_I(hdmi_scrambling);
11222         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11223         PIPE_CONF_CHECK_I(has_infoframe);
11224         PIPE_CONF_CHECK_I(ycbcr420);
11225
11226         PIPE_CONF_CHECK_I(has_audio);
11227
11228         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11229                               DRM_MODE_FLAG_INTERLACE);
11230
11231         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11232                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11233                                       DRM_MODE_FLAG_PHSYNC);
11234                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11235                                       DRM_MODE_FLAG_NHSYNC);
11236                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11237                                       DRM_MODE_FLAG_PVSYNC);
11238                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11239                                       DRM_MODE_FLAG_NVSYNC);
11240         }
11241
11242         PIPE_CONF_CHECK_X(gmch_pfit.control);
11243         /* pfit ratios are autocomputed by the hw on gen4+ */
11244         if (INTEL_GEN(dev_priv) < 4)
11245                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11246         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11247
11248         if (!adjust) {
11249                 PIPE_CONF_CHECK_I(pipe_src_w);
11250                 PIPE_CONF_CHECK_I(pipe_src_h);
11251
11252                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11253                 if (current_config->pch_pfit.enabled) {
11254                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11255                         PIPE_CONF_CHECK_X(pch_pfit.size);
11256                 }
11257
11258                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11259                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11260         }
11261
11262         /* BDW+ don't expose a synchronous way to read the state */
11263         if (IS_HASWELL(dev_priv))
11264                 PIPE_CONF_CHECK_I(ips_enabled);
11265
11266         PIPE_CONF_CHECK_I(double_wide);
11267
11268         PIPE_CONF_CHECK_P(shared_dpll);
11269         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11270         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11271         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11272         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11273         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11274         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11275         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11276         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11277         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11278         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11279         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11280         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11281         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11282         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11283         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11284         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11285         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11286         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11287         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11288         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11289         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11290
11291         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11292         PIPE_CONF_CHECK_X(dsi_pll.div);
11293
11294         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11295                 PIPE_CONF_CHECK_I(pipe_bpp);
11296
11297         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11298         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11299
11300         PIPE_CONF_CHECK_I(min_voltage_level);
11301
11302 #undef PIPE_CONF_CHECK_X
11303 #undef PIPE_CONF_CHECK_I
11304 #undef PIPE_CONF_CHECK_P
11305 #undef PIPE_CONF_CHECK_FLAGS
11306 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11307 #undef PIPE_CONF_QUIRK
11308
11309         return ret;
11310 }
11311
11312 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11313                                            const struct intel_crtc_state *pipe_config)
11314 {
11315         if (pipe_config->has_pch_encoder) {
11316                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11317                                                             &pipe_config->fdi_m_n);
11318                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11319
11320                 /*
11321                  * FDI already provided one idea for the dotclock.
11322                  * Yell if the encoder disagrees.
11323                  */
11324                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11325                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11326                      fdi_dotclock, dotclock);
11327         }
11328 }
11329
11330 static void verify_wm_state(struct drm_crtc *crtc,
11331                             struct drm_crtc_state *new_state)
11332 {
11333         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11334         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11335         struct skl_pipe_wm hw_wm, *sw_wm;
11336         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11337         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11339         const enum pipe pipe = intel_crtc->pipe;
11340         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11341
11342         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11343                 return;
11344
11345         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11346         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11347
11348         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11349         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11350
11351         /* planes */
11352         for_each_universal_plane(dev_priv, pipe, plane) {
11353                 hw_plane_wm = &hw_wm.planes[plane];
11354                 sw_plane_wm = &sw_wm->planes[plane];
11355
11356                 /* Watermarks */
11357                 for (level = 0; level <= max_level; level++) {
11358                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11359                                                 &sw_plane_wm->wm[level]))
11360                                 continue;
11361
11362                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11363                                   pipe_name(pipe), plane + 1, level,
11364                                   sw_plane_wm->wm[level].plane_en,
11365                                   sw_plane_wm->wm[level].plane_res_b,
11366                                   sw_plane_wm->wm[level].plane_res_l,
11367                                   hw_plane_wm->wm[level].plane_en,
11368                                   hw_plane_wm->wm[level].plane_res_b,
11369                                   hw_plane_wm->wm[level].plane_res_l);
11370                 }
11371
11372                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11373                                          &sw_plane_wm->trans_wm)) {
11374                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11375                                   pipe_name(pipe), plane + 1,
11376                                   sw_plane_wm->trans_wm.plane_en,
11377                                   sw_plane_wm->trans_wm.plane_res_b,
11378                                   sw_plane_wm->trans_wm.plane_res_l,
11379                                   hw_plane_wm->trans_wm.plane_en,
11380                                   hw_plane_wm->trans_wm.plane_res_b,
11381                                   hw_plane_wm->trans_wm.plane_res_l);
11382                 }
11383
11384                 /* DDB */
11385                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11386                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11387
11388                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11389                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11390                                   pipe_name(pipe), plane + 1,
11391                                   sw_ddb_entry->start, sw_ddb_entry->end,
11392                                   hw_ddb_entry->start, hw_ddb_entry->end);
11393                 }
11394         }
11395
11396         /*
11397          * cursor
11398          * If the cursor plane isn't active, we may not have updated it's ddb
11399          * allocation. In that case since the ddb allocation will be updated
11400          * once the plane becomes visible, we can skip this check
11401          */
11402         if (1) {
11403                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11404                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11405
11406                 /* Watermarks */
11407                 for (level = 0; level <= max_level; level++) {
11408                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11409                                                 &sw_plane_wm->wm[level]))
11410                                 continue;
11411
11412                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11413                                   pipe_name(pipe), level,
11414                                   sw_plane_wm->wm[level].plane_en,
11415                                   sw_plane_wm->wm[level].plane_res_b,
11416                                   sw_plane_wm->wm[level].plane_res_l,
11417                                   hw_plane_wm->wm[level].plane_en,
11418                                   hw_plane_wm->wm[level].plane_res_b,
11419                                   hw_plane_wm->wm[level].plane_res_l);
11420                 }
11421
11422                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11423                                          &sw_plane_wm->trans_wm)) {
11424                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11425                                   pipe_name(pipe),
11426                                   sw_plane_wm->trans_wm.plane_en,
11427                                   sw_plane_wm->trans_wm.plane_res_b,
11428                                   sw_plane_wm->trans_wm.plane_res_l,
11429                                   hw_plane_wm->trans_wm.plane_en,
11430                                   hw_plane_wm->trans_wm.plane_res_b,
11431                                   hw_plane_wm->trans_wm.plane_res_l);
11432                 }
11433
11434                 /* DDB */
11435                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11436                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11437
11438                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11439                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11440                                   pipe_name(pipe),
11441                                   sw_ddb_entry->start, sw_ddb_entry->end,
11442                                   hw_ddb_entry->start, hw_ddb_entry->end);
11443                 }
11444         }
11445 }
11446
11447 static void
11448 verify_connector_state(struct drm_device *dev,
11449                        struct drm_atomic_state *state,
11450                        struct drm_crtc *crtc)
11451 {
11452         struct drm_connector *connector;
11453         struct drm_connector_state *new_conn_state;
11454         int i;
11455
11456         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11457                 struct drm_encoder *encoder = connector->encoder;
11458                 struct drm_crtc_state *crtc_state = NULL;
11459
11460                 if (new_conn_state->crtc != crtc)
11461                         continue;
11462
11463                 if (crtc)
11464                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11465
11466                 intel_connector_verify_state(crtc_state, new_conn_state);
11467
11468                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11469                      "connector's atomic encoder doesn't match legacy encoder\n");
11470         }
11471 }
11472
11473 static void
11474 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11475 {
11476         struct intel_encoder *encoder;
11477         struct drm_connector *connector;
11478         struct drm_connector_state *old_conn_state, *new_conn_state;
11479         int i;
11480
11481         for_each_intel_encoder(dev, encoder) {
11482                 bool enabled = false, found = false;
11483                 enum pipe pipe;
11484
11485                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11486                               encoder->base.base.id,
11487                               encoder->base.name);
11488
11489                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11490                                                    new_conn_state, i) {
11491                         if (old_conn_state->best_encoder == &encoder->base)
11492                                 found = true;
11493
11494                         if (new_conn_state->best_encoder != &encoder->base)
11495                                 continue;
11496                         found = enabled = true;
11497
11498                         I915_STATE_WARN(new_conn_state->crtc !=
11499                                         encoder->base.crtc,
11500                              "connector's crtc doesn't match encoder crtc\n");
11501                 }
11502
11503                 if (!found)
11504                         continue;
11505
11506                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11507                      "encoder's enabled state mismatch "
11508                      "(expected %i, found %i)\n",
11509                      !!encoder->base.crtc, enabled);
11510
11511                 if (!encoder->base.crtc) {
11512                         bool active;
11513
11514                         active = encoder->get_hw_state(encoder, &pipe);
11515                         I915_STATE_WARN(active,
11516                              "encoder detached but still enabled on pipe %c.\n",
11517                              pipe_name(pipe));
11518                 }
11519         }
11520 }
11521
11522 static void
11523 verify_crtc_state(struct drm_crtc *crtc,
11524                   struct drm_crtc_state *old_crtc_state,
11525                   struct drm_crtc_state *new_crtc_state)
11526 {
11527         struct drm_device *dev = crtc->dev;
11528         struct drm_i915_private *dev_priv = to_i915(dev);
11529         struct intel_encoder *encoder;
11530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11531         struct intel_crtc_state *pipe_config, *sw_config;
11532         struct drm_atomic_state *old_state;
11533         bool active;
11534
11535         old_state = old_crtc_state->state;
11536         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11537         pipe_config = to_intel_crtc_state(old_crtc_state);
11538         memset(pipe_config, 0, sizeof(*pipe_config));
11539         pipe_config->base.crtc = crtc;
11540         pipe_config->base.state = old_state;
11541
11542         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11543
11544         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11545
11546         /* we keep both pipes enabled on 830 */
11547         if (IS_I830(dev_priv))
11548                 active = new_crtc_state->active;
11549
11550         I915_STATE_WARN(new_crtc_state->active != active,
11551              "crtc active state doesn't match with hw state "
11552              "(expected %i, found %i)\n", new_crtc_state->active, active);
11553
11554         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11555              "transitional active state does not match atomic hw state "
11556              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11557
11558         for_each_encoder_on_crtc(dev, crtc, encoder) {
11559                 enum pipe pipe;
11560
11561                 active = encoder->get_hw_state(encoder, &pipe);
11562                 I915_STATE_WARN(active != new_crtc_state->active,
11563                         "[ENCODER:%i] active %i with crtc active %i\n",
11564                         encoder->base.base.id, active, new_crtc_state->active);
11565
11566                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11567                                 "Encoder connected to wrong pipe %c\n",
11568                                 pipe_name(pipe));
11569
11570                 if (active)
11571                         encoder->get_config(encoder, pipe_config);
11572         }
11573
11574         intel_crtc_compute_pixel_rate(pipe_config);
11575
11576         if (!new_crtc_state->active)
11577                 return;
11578
11579         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11580
11581         sw_config = to_intel_crtc_state(new_crtc_state);
11582         if (!intel_pipe_config_compare(dev_priv, sw_config,
11583                                        pipe_config, false)) {
11584                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11585                 intel_dump_pipe_config(intel_crtc, pipe_config,
11586                                        "[hw state]");
11587                 intel_dump_pipe_config(intel_crtc, sw_config,
11588                                        "[sw state]");
11589         }
11590 }
11591
11592 static void
11593 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11594                          struct intel_shared_dpll *pll,
11595                          struct drm_crtc *crtc,
11596                          struct drm_crtc_state *new_state)
11597 {
11598         struct intel_dpll_hw_state dpll_hw_state;
11599         unsigned crtc_mask;
11600         bool active;
11601
11602         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11603
11604         DRM_DEBUG_KMS("%s\n", pll->name);
11605
11606         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11607
11608         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11609                 I915_STATE_WARN(!pll->on && pll->active_mask,
11610                      "pll in active use but not on in sw tracking\n");
11611                 I915_STATE_WARN(pll->on && !pll->active_mask,
11612                      "pll is on but not used by any active crtc\n");
11613                 I915_STATE_WARN(pll->on != active,
11614                      "pll on state mismatch (expected %i, found %i)\n",
11615                      pll->on, active);
11616         }
11617
11618         if (!crtc) {
11619                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11620                                 "more active pll users than references: %x vs %x\n",
11621                                 pll->active_mask, pll->state.crtc_mask);
11622
11623                 return;
11624         }
11625
11626         crtc_mask = 1 << drm_crtc_index(crtc);
11627
11628         if (new_state->active)
11629                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11630                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11631                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11632         else
11633                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11634                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11635                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11636
11637         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11638                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11639                         crtc_mask, pll->state.crtc_mask);
11640
11641         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11642                                           &dpll_hw_state,
11643                                           sizeof(dpll_hw_state)),
11644                         "pll hw state mismatch\n");
11645 }
11646
11647 static void
11648 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11649                          struct drm_crtc_state *old_crtc_state,
11650                          struct drm_crtc_state *new_crtc_state)
11651 {
11652         struct drm_i915_private *dev_priv = to_i915(dev);
11653         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11654         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11655
11656         if (new_state->shared_dpll)
11657                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11658
11659         if (old_state->shared_dpll &&
11660             old_state->shared_dpll != new_state->shared_dpll) {
11661                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11662                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11663
11664                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11665                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11666                                 pipe_name(drm_crtc_index(crtc)));
11667                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11668                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11669                                 pipe_name(drm_crtc_index(crtc)));
11670         }
11671 }
11672
11673 static void
11674 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11675                           struct drm_atomic_state *state,
11676                           struct drm_crtc_state *old_state,
11677                           struct drm_crtc_state *new_state)
11678 {
11679         if (!needs_modeset(new_state) &&
11680             !to_intel_crtc_state(new_state)->update_pipe)
11681                 return;
11682
11683         verify_wm_state(crtc, new_state);
11684         verify_connector_state(crtc->dev, state, crtc);
11685         verify_crtc_state(crtc, old_state, new_state);
11686         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11687 }
11688
11689 static void
11690 verify_disabled_dpll_state(struct drm_device *dev)
11691 {
11692         struct drm_i915_private *dev_priv = to_i915(dev);
11693         int i;
11694
11695         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11696                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11697 }
11698
11699 static void
11700 intel_modeset_verify_disabled(struct drm_device *dev,
11701                               struct drm_atomic_state *state)
11702 {
11703         verify_encoder_state(dev, state);
11704         verify_connector_state(dev, state, NULL);
11705         verify_disabled_dpll_state(dev);
11706 }
11707
11708 static void update_scanline_offset(struct intel_crtc *crtc)
11709 {
11710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11711
11712         /*
11713          * The scanline counter increments at the leading edge of hsync.
11714          *
11715          * On most platforms it starts counting from vtotal-1 on the
11716          * first active line. That means the scanline counter value is
11717          * always one less than what we would expect. Ie. just after
11718          * start of vblank, which also occurs at start of hsync (on the
11719          * last active line), the scanline counter will read vblank_start-1.
11720          *
11721          * On gen2 the scanline counter starts counting from 1 instead
11722          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11723          * to keep the value positive), instead of adding one.
11724          *
11725          * On HSW+ the behaviour of the scanline counter depends on the output
11726          * type. For DP ports it behaves like most other platforms, but on HDMI
11727          * there's an extra 1 line difference. So we need to add two instead of
11728          * one to the value.
11729          *
11730          * On VLV/CHV DSI the scanline counter would appear to increment
11731          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11732          * that means we can't tell whether we're in vblank or not while
11733          * we're on that particular line. We must still set scanline_offset
11734          * to 1 so that the vblank timestamps come out correct when we query
11735          * the scanline counter from within the vblank interrupt handler.
11736          * However if queried just before the start of vblank we'll get an
11737          * answer that's slightly in the future.
11738          */
11739         if (IS_GEN2(dev_priv)) {
11740                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11741                 int vtotal;
11742
11743                 vtotal = adjusted_mode->crtc_vtotal;
11744                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11745                         vtotal /= 2;
11746
11747                 crtc->scanline_offset = vtotal - 1;
11748         } else if (HAS_DDI(dev_priv) &&
11749                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11750                 crtc->scanline_offset = 2;
11751         } else
11752                 crtc->scanline_offset = 1;
11753 }
11754
11755 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11756 {
11757         struct drm_device *dev = state->dev;
11758         struct drm_i915_private *dev_priv = to_i915(dev);
11759         struct drm_crtc *crtc;
11760         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11761         int i;
11762
11763         if (!dev_priv->display.crtc_compute_clock)
11764                 return;
11765
11766         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11767                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11768                 struct intel_shared_dpll *old_dpll =
11769                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11770
11771                 if (!needs_modeset(new_crtc_state))
11772                         continue;
11773
11774                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11775
11776                 if (!old_dpll)
11777                         continue;
11778
11779                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11780         }
11781 }
11782
11783 /*
11784  * This implements the workaround described in the "notes" section of the mode
11785  * set sequence documentation. When going from no pipes or single pipe to
11786  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11787  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11788  */
11789 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11790 {
11791         struct drm_crtc_state *crtc_state;
11792         struct intel_crtc *intel_crtc;
11793         struct drm_crtc *crtc;
11794         struct intel_crtc_state *first_crtc_state = NULL;
11795         struct intel_crtc_state *other_crtc_state = NULL;
11796         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11797         int i;
11798
11799         /* look at all crtc's that are going to be enabled in during modeset */
11800         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11801                 intel_crtc = to_intel_crtc(crtc);
11802
11803                 if (!crtc_state->active || !needs_modeset(crtc_state))
11804                         continue;
11805
11806                 if (first_crtc_state) {
11807                         other_crtc_state = to_intel_crtc_state(crtc_state);
11808                         break;
11809                 } else {
11810                         first_crtc_state = to_intel_crtc_state(crtc_state);
11811                         first_pipe = intel_crtc->pipe;
11812                 }
11813         }
11814
11815         /* No workaround needed? */
11816         if (!first_crtc_state)
11817                 return 0;
11818
11819         /* w/a possibly needed, check how many crtc's are already enabled. */
11820         for_each_intel_crtc(state->dev, intel_crtc) {
11821                 struct intel_crtc_state *pipe_config;
11822
11823                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11824                 if (IS_ERR(pipe_config))
11825                         return PTR_ERR(pipe_config);
11826
11827                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11828
11829                 if (!pipe_config->base.active ||
11830                     needs_modeset(&pipe_config->base))
11831                         continue;
11832
11833                 /* 2 or more enabled crtcs means no need for w/a */
11834                 if (enabled_pipe != INVALID_PIPE)
11835                         return 0;
11836
11837                 enabled_pipe = intel_crtc->pipe;
11838         }
11839
11840         if (enabled_pipe != INVALID_PIPE)
11841                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11842         else if (other_crtc_state)
11843                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11844
11845         return 0;
11846 }
11847
11848 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11849 {
11850         struct drm_crtc *crtc;
11851
11852         /* Add all pipes to the state */
11853         for_each_crtc(state->dev, crtc) {
11854                 struct drm_crtc_state *crtc_state;
11855
11856                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11857                 if (IS_ERR(crtc_state))
11858                         return PTR_ERR(crtc_state);
11859         }
11860
11861         return 0;
11862 }
11863
11864 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11865 {
11866         struct drm_crtc *crtc;
11867
11868         /*
11869          * Add all pipes to the state, and force
11870          * a modeset on all the active ones.
11871          */
11872         for_each_crtc(state->dev, crtc) {
11873                 struct drm_crtc_state *crtc_state;
11874                 int ret;
11875
11876                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11877                 if (IS_ERR(crtc_state))
11878                         return PTR_ERR(crtc_state);
11879
11880                 if (!crtc_state->active || needs_modeset(crtc_state))
11881                         continue;
11882
11883                 crtc_state->mode_changed = true;
11884
11885                 ret = drm_atomic_add_affected_connectors(state, crtc);
11886                 if (ret)
11887                         return ret;
11888
11889                 ret = drm_atomic_add_affected_planes(state, crtc);
11890                 if (ret)
11891                         return ret;
11892         }
11893
11894         return 0;
11895 }
11896
11897 static int intel_modeset_checks(struct drm_atomic_state *state)
11898 {
11899         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11900         struct drm_i915_private *dev_priv = to_i915(state->dev);
11901         struct drm_crtc *crtc;
11902         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11903         int ret = 0, i;
11904
11905         if (!check_digital_port_conflicts(state)) {
11906                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11907                 return -EINVAL;
11908         }
11909
11910         intel_state->modeset = true;
11911         intel_state->active_crtcs = dev_priv->active_crtcs;
11912         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11913         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11914
11915         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11916                 if (new_crtc_state->active)
11917                         intel_state->active_crtcs |= 1 << i;
11918                 else
11919                         intel_state->active_crtcs &= ~(1 << i);
11920
11921                 if (old_crtc_state->active != new_crtc_state->active)
11922                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11923         }
11924
11925         /*
11926          * See if the config requires any additional preparation, e.g.
11927          * to adjust global state with pipes off.  We need to do this
11928          * here so we can get the modeset_pipe updated config for the new
11929          * mode set on this crtc.  For other crtcs we need to use the
11930          * adjusted_mode bits in the crtc directly.
11931          */
11932         if (dev_priv->display.modeset_calc_cdclk) {
11933                 ret = dev_priv->display.modeset_calc_cdclk(state);
11934                 if (ret < 0)
11935                         return ret;
11936
11937                 /*
11938                  * Writes to dev_priv->cdclk.logical must protected by
11939                  * holding all the crtc locks, even if we don't end up
11940                  * touching the hardware
11941                  */
11942                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
11943                                         &intel_state->cdclk.logical)) {
11944                         ret = intel_lock_all_pipes(state);
11945                         if (ret < 0)
11946                                 return ret;
11947                 }
11948
11949                 /* All pipes must be switched off while we change the cdclk. */
11950                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
11951                                               &intel_state->cdclk.actual)) {
11952                         ret = intel_modeset_all_pipes(state);
11953                         if (ret < 0)
11954                                 return ret;
11955                 }
11956
11957                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11958                               intel_state->cdclk.logical.cdclk,
11959                               intel_state->cdclk.actual.cdclk);
11960                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
11961                               intel_state->cdclk.logical.voltage_level,
11962                               intel_state->cdclk.actual.voltage_level);
11963         } else {
11964                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11965         }
11966
11967         intel_modeset_clear_plls(state);
11968
11969         if (IS_HASWELL(dev_priv))
11970                 return haswell_mode_set_planes_workaround(state);
11971
11972         return 0;
11973 }
11974
11975 /*
11976  * Handle calculation of various watermark data at the end of the atomic check
11977  * phase.  The code here should be run after the per-crtc and per-plane 'check'
11978  * handlers to ensure that all derived state has been updated.
11979  */
11980 static int calc_watermark_data(struct drm_atomic_state *state)
11981 {
11982         struct drm_device *dev = state->dev;
11983         struct drm_i915_private *dev_priv = to_i915(dev);
11984
11985         /* Is there platform-specific watermark information to calculate? */
11986         if (dev_priv->display.compute_global_watermarks)
11987                 return dev_priv->display.compute_global_watermarks(state);
11988
11989         return 0;
11990 }
11991
11992 /**
11993  * intel_atomic_check - validate state object
11994  * @dev: drm device
11995  * @state: state to validate
11996  */
11997 static int intel_atomic_check(struct drm_device *dev,
11998                               struct drm_atomic_state *state)
11999 {
12000         struct drm_i915_private *dev_priv = to_i915(dev);
12001         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12002         struct drm_crtc *crtc;
12003         struct drm_crtc_state *old_crtc_state, *crtc_state;
12004         int ret, i;
12005         bool any_ms = false;
12006
12007         ret = drm_atomic_helper_check_modeset(dev, state);
12008         if (ret)
12009                 return ret;
12010
12011         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12012                 struct intel_crtc_state *pipe_config =
12013                         to_intel_crtc_state(crtc_state);
12014
12015                 /* Catch I915_MODE_FLAG_INHERITED */
12016                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12017                         crtc_state->mode_changed = true;
12018
12019                 if (!needs_modeset(crtc_state))
12020                         continue;
12021
12022                 if (!crtc_state->enable) {
12023                         any_ms = true;
12024                         continue;
12025                 }
12026
12027                 /* FIXME: For only active_changed we shouldn't need to do any
12028                  * state recomputation at all. */
12029
12030                 ret = drm_atomic_add_affected_connectors(state, crtc);
12031                 if (ret)
12032                         return ret;
12033
12034                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12035                 if (ret) {
12036                         intel_dump_pipe_config(to_intel_crtc(crtc),
12037                                                pipe_config, "[failed]");
12038                         return ret;
12039                 }
12040
12041                 if (i915_modparams.fastboot &&
12042                     intel_pipe_config_compare(dev_priv,
12043                                         to_intel_crtc_state(old_crtc_state),
12044                                         pipe_config, true)) {
12045                         crtc_state->mode_changed = false;
12046                         pipe_config->update_pipe = true;
12047                 }
12048
12049                 if (needs_modeset(crtc_state))
12050                         any_ms = true;
12051
12052                 ret = drm_atomic_add_affected_planes(state, crtc);
12053                 if (ret)
12054                         return ret;
12055
12056                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12057                                        needs_modeset(crtc_state) ?
12058                                        "[modeset]" : "[fastset]");
12059         }
12060
12061         if (any_ms) {
12062                 ret = intel_modeset_checks(state);
12063
12064                 if (ret)
12065                         return ret;
12066         } else {
12067                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12068         }
12069
12070         ret = drm_atomic_helper_check_planes(dev, state);
12071         if (ret)
12072                 return ret;
12073
12074         intel_fbc_choose_crtc(dev_priv, state);
12075         return calc_watermark_data(state);
12076 }
12077
12078 static int intel_atomic_prepare_commit(struct drm_device *dev,
12079                                        struct drm_atomic_state *state)
12080 {
12081         return drm_atomic_helper_prepare_planes(dev, state);
12082 }
12083
12084 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12085 {
12086         struct drm_device *dev = crtc->base.dev;
12087
12088         if (!dev->max_vblank_count)
12089                 return drm_crtc_accurate_vblank_count(&crtc->base);
12090
12091         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12092 }
12093
12094 static void intel_update_crtc(struct drm_crtc *crtc,
12095                               struct drm_atomic_state *state,
12096                               struct drm_crtc_state *old_crtc_state,
12097                               struct drm_crtc_state *new_crtc_state)
12098 {
12099         struct drm_device *dev = crtc->dev;
12100         struct drm_i915_private *dev_priv = to_i915(dev);
12101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12102         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12103         bool modeset = needs_modeset(new_crtc_state);
12104
12105         if (modeset) {
12106                 update_scanline_offset(intel_crtc);
12107                 dev_priv->display.crtc_enable(pipe_config, state);
12108         } else {
12109                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12110                                        pipe_config);
12111         }
12112
12113         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12114                 intel_fbc_enable(
12115                     intel_crtc, pipe_config,
12116                     to_intel_plane_state(crtc->primary->state));
12117         }
12118
12119         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12120 }
12121
12122 static void intel_update_crtcs(struct drm_atomic_state *state)
12123 {
12124         struct drm_crtc *crtc;
12125         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12126         int i;
12127
12128         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12129                 if (!new_crtc_state->active)
12130                         continue;
12131
12132                 intel_update_crtc(crtc, state, old_crtc_state,
12133                                   new_crtc_state);
12134         }
12135 }
12136
12137 static void skl_update_crtcs(struct drm_atomic_state *state)
12138 {
12139         struct drm_i915_private *dev_priv = to_i915(state->dev);
12140         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12141         struct drm_crtc *crtc;
12142         struct intel_crtc *intel_crtc;
12143         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12144         struct intel_crtc_state *cstate;
12145         unsigned int updated = 0;
12146         bool progress;
12147         enum pipe pipe;
12148         int i;
12149
12150         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12151
12152         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12153                 /* ignore allocations for crtc's that have been turned off. */
12154                 if (new_crtc_state->active)
12155                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12156
12157         /*
12158          * Whenever the number of active pipes changes, we need to make sure we
12159          * update the pipes in the right order so that their ddb allocations
12160          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12161          * cause pipe underruns and other bad stuff.
12162          */
12163         do {
12164                 progress = false;
12165
12166                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12167                         bool vbl_wait = false;
12168                         unsigned int cmask = drm_crtc_mask(crtc);
12169
12170                         intel_crtc = to_intel_crtc(crtc);
12171                         cstate = to_intel_crtc_state(new_crtc_state);
12172                         pipe = intel_crtc->pipe;
12173
12174                         if (updated & cmask || !cstate->base.active)
12175                                 continue;
12176
12177                         if (skl_ddb_allocation_overlaps(dev_priv,
12178                                                         entries,
12179                                                         &cstate->wm.skl.ddb,
12180                                                         i))
12181                                 continue;
12182
12183                         updated |= cmask;
12184                         entries[i] = &cstate->wm.skl.ddb;
12185
12186                         /*
12187                          * If this is an already active pipe, it's DDB changed,
12188                          * and this isn't the last pipe that needs updating
12189                          * then we need to wait for a vblank to pass for the
12190                          * new ddb allocation to take effect.
12191                          */
12192                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12193                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12194                             !new_crtc_state->active_changed &&
12195                             intel_state->wm_results.dirty_pipes != updated)
12196                                 vbl_wait = true;
12197
12198                         intel_update_crtc(crtc, state, old_crtc_state,
12199                                           new_crtc_state);
12200
12201                         if (vbl_wait)
12202                                 intel_wait_for_vblank(dev_priv, pipe);
12203
12204                         progress = true;
12205                 }
12206         } while (progress);
12207 }
12208
12209 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12210 {
12211         struct intel_atomic_state *state, *next;
12212         struct llist_node *freed;
12213
12214         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12215         llist_for_each_entry_safe(state, next, freed, freed)
12216                 drm_atomic_state_put(&state->base);
12217 }
12218
12219 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12220 {
12221         struct drm_i915_private *dev_priv =
12222                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12223
12224         intel_atomic_helper_free_state(dev_priv);
12225 }
12226
12227 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12228 {
12229         struct wait_queue_entry wait_fence, wait_reset;
12230         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12231
12232         init_wait_entry(&wait_fence, 0);
12233         init_wait_entry(&wait_reset, 0);
12234         for (;;) {
12235                 prepare_to_wait(&intel_state->commit_ready.wait,
12236                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12237                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12238                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12239
12240
12241                 if (i915_sw_fence_done(&intel_state->commit_ready)
12242                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12243                         break;
12244
12245                 schedule();
12246         }
12247         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12248         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12249 }
12250
12251 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12252 {
12253         struct drm_device *dev = state->dev;
12254         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12255         struct drm_i915_private *dev_priv = to_i915(dev);
12256         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12257         struct drm_crtc *crtc;
12258         struct intel_crtc_state *intel_cstate;
12259         u64 put_domains[I915_MAX_PIPES] = {};
12260         int i;
12261
12262         intel_atomic_commit_fence_wait(intel_state);
12263
12264         drm_atomic_helper_wait_for_dependencies(state);
12265
12266         if (intel_state->modeset)
12267                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12268
12269         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12270                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12271
12272                 if (needs_modeset(new_crtc_state) ||
12273                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12274
12275                         put_domains[to_intel_crtc(crtc)->pipe] =
12276                                 modeset_get_crtc_power_domains(crtc,
12277                                         to_intel_crtc_state(new_crtc_state));
12278                 }
12279
12280                 if (!needs_modeset(new_crtc_state))
12281                         continue;
12282
12283                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12284                                        to_intel_crtc_state(new_crtc_state));
12285
12286                 if (old_crtc_state->active) {
12287                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12288                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12289                         intel_crtc->active = false;
12290                         intel_fbc_disable(intel_crtc);
12291                         intel_disable_shared_dpll(intel_crtc);
12292
12293                         /*
12294                          * Underruns don't always raise
12295                          * interrupts, so check manually.
12296                          */
12297                         intel_check_cpu_fifo_underruns(dev_priv);
12298                         intel_check_pch_fifo_underruns(dev_priv);
12299
12300                         if (!new_crtc_state->active) {
12301                                 /*
12302                                  * Make sure we don't call initial_watermarks
12303                                  * for ILK-style watermark updates.
12304                                  *
12305                                  * No clue what this is supposed to achieve.
12306                                  */
12307                                 if (INTEL_GEN(dev_priv) >= 9)
12308                                         dev_priv->display.initial_watermarks(intel_state,
12309                                                                              to_intel_crtc_state(new_crtc_state));
12310                         }
12311                 }
12312         }
12313
12314         /* Only after disabling all output pipelines that will be changed can we
12315          * update the the output configuration. */
12316         intel_modeset_update_crtc_state(state);
12317
12318         if (intel_state->modeset) {
12319                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12320
12321                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12322
12323                 /*
12324                  * SKL workaround: bspec recommends we disable the SAGV when we
12325                  * have more then one pipe enabled
12326                  */
12327                 if (!intel_can_enable_sagv(state))
12328                         intel_disable_sagv(dev_priv);
12329
12330                 intel_modeset_verify_disabled(dev, state);
12331         }
12332
12333         /* Complete the events for pipes that have now been disabled */
12334         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12335                 bool modeset = needs_modeset(new_crtc_state);
12336
12337                 /* Complete events for now disable pipes here. */
12338                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12339                         spin_lock_irq(&dev->event_lock);
12340                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12341                         spin_unlock_irq(&dev->event_lock);
12342
12343                         new_crtc_state->event = NULL;
12344                 }
12345         }
12346
12347         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12348         dev_priv->display.update_crtcs(state);
12349
12350         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12351          * already, but still need the state for the delayed optimization. To
12352          * fix this:
12353          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12354          * - schedule that vblank worker _before_ calling hw_done
12355          * - at the start of commit_tail, cancel it _synchrously
12356          * - switch over to the vblank wait helper in the core after that since
12357          *   we don't need out special handling any more.
12358          */
12359         drm_atomic_helper_wait_for_flip_done(dev, state);
12360
12361         /*
12362          * Now that the vblank has passed, we can go ahead and program the
12363          * optimal watermarks on platforms that need two-step watermark
12364          * programming.
12365          *
12366          * TODO: Move this (and other cleanup) to an async worker eventually.
12367          */
12368         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12369                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12370
12371                 if (dev_priv->display.optimize_watermarks)
12372                         dev_priv->display.optimize_watermarks(intel_state,
12373                                                               intel_cstate);
12374         }
12375
12376         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12377                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12378
12379                 if (put_domains[i])
12380                         modeset_put_power_domains(dev_priv, put_domains[i]);
12381
12382                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12383         }
12384
12385         if (intel_state->modeset && intel_can_enable_sagv(state))
12386                 intel_enable_sagv(dev_priv);
12387
12388         drm_atomic_helper_commit_hw_done(state);
12389
12390         if (intel_state->modeset) {
12391                 /* As one of the primary mmio accessors, KMS has a high
12392                  * likelihood of triggering bugs in unclaimed access. After we
12393                  * finish modesetting, see if an error has been flagged, and if
12394                  * so enable debugging for the next modeset - and hope we catch
12395                  * the culprit.
12396                  */
12397                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12398                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12399         }
12400
12401         drm_atomic_helper_cleanup_planes(dev, state);
12402
12403         drm_atomic_helper_commit_cleanup_done(state);
12404
12405         drm_atomic_state_put(state);
12406
12407         intel_atomic_helper_free_state(dev_priv);
12408 }
12409
12410 static void intel_atomic_commit_work(struct work_struct *work)
12411 {
12412         struct drm_atomic_state *state =
12413                 container_of(work, struct drm_atomic_state, commit_work);
12414
12415         intel_atomic_commit_tail(state);
12416 }
12417
12418 static int __i915_sw_fence_call
12419 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12420                           enum i915_sw_fence_notify notify)
12421 {
12422         struct intel_atomic_state *state =
12423                 container_of(fence, struct intel_atomic_state, commit_ready);
12424
12425         switch (notify) {
12426         case FENCE_COMPLETE:
12427                 /* we do blocking waits in the worker, nothing to do here */
12428                 break;
12429         case FENCE_FREE:
12430                 {
12431                         struct intel_atomic_helper *helper =
12432                                 &to_i915(state->base.dev)->atomic_helper;
12433
12434                         if (llist_add(&state->freed, &helper->free_list))
12435                                 schedule_work(&helper->free_work);
12436                         break;
12437                 }
12438         }
12439
12440         return NOTIFY_DONE;
12441 }
12442
12443 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12444 {
12445         struct drm_plane_state *old_plane_state, *new_plane_state;
12446         struct drm_plane *plane;
12447         int i;
12448
12449         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12450                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12451                                   intel_fb_obj(new_plane_state->fb),
12452                                   to_intel_plane(plane)->frontbuffer_bit);
12453 }
12454
12455 /**
12456  * intel_atomic_commit - commit validated state object
12457  * @dev: DRM device
12458  * @state: the top-level driver state object
12459  * @nonblock: nonblocking commit
12460  *
12461  * This function commits a top-level state object that has been validated
12462  * with drm_atomic_helper_check().
12463  *
12464  * RETURNS
12465  * Zero for success or -errno.
12466  */
12467 static int intel_atomic_commit(struct drm_device *dev,
12468                                struct drm_atomic_state *state,
12469                                bool nonblock)
12470 {
12471         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12472         struct drm_i915_private *dev_priv = to_i915(dev);
12473         int ret = 0;
12474
12475         drm_atomic_state_get(state);
12476         i915_sw_fence_init(&intel_state->commit_ready,
12477                            intel_atomic_commit_ready);
12478
12479         /*
12480          * The intel_legacy_cursor_update() fast path takes care
12481          * of avoiding the vblank waits for simple cursor
12482          * movement and flips. For cursor on/off and size changes,
12483          * we want to perform the vblank waits so that watermark
12484          * updates happen during the correct frames. Gen9+ have
12485          * double buffered watermarks and so shouldn't need this.
12486          *
12487          * Unset state->legacy_cursor_update before the call to
12488          * drm_atomic_helper_setup_commit() because otherwise
12489          * drm_atomic_helper_wait_for_flip_done() is a noop and
12490          * we get FIFO underruns because we didn't wait
12491          * for vblank.
12492          *
12493          * FIXME doing watermarks and fb cleanup from a vblank worker
12494          * (assuming we had any) would solve these problems.
12495          */
12496         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12497                 struct intel_crtc_state *new_crtc_state;
12498                 struct intel_crtc *crtc;
12499                 int i;
12500
12501                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12502                         if (new_crtc_state->wm.need_postvbl_update ||
12503                             new_crtc_state->update_wm_post)
12504                                 state->legacy_cursor_update = false;
12505         }
12506
12507         ret = intel_atomic_prepare_commit(dev, state);
12508         if (ret) {
12509                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12510                 i915_sw_fence_commit(&intel_state->commit_ready);
12511                 return ret;
12512         }
12513
12514         ret = drm_atomic_helper_setup_commit(state, nonblock);
12515         if (!ret)
12516                 ret = drm_atomic_helper_swap_state(state, true);
12517
12518         if (ret) {
12519                 i915_sw_fence_commit(&intel_state->commit_ready);
12520
12521                 drm_atomic_helper_cleanup_planes(dev, state);
12522                 return ret;
12523         }
12524         dev_priv->wm.distrust_bios_wm = false;
12525         intel_shared_dpll_swap_state(state);
12526         intel_atomic_track_fbs(state);
12527
12528         if (intel_state->modeset) {
12529                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12530                        sizeof(intel_state->min_cdclk));
12531                 memcpy(dev_priv->min_voltage_level,
12532                        intel_state->min_voltage_level,
12533                        sizeof(intel_state->min_voltage_level));
12534                 dev_priv->active_crtcs = intel_state->active_crtcs;
12535                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12536                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12537         }
12538
12539         drm_atomic_state_get(state);
12540         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12541
12542         i915_sw_fence_commit(&intel_state->commit_ready);
12543         if (nonblock)
12544                 queue_work(system_unbound_wq, &state->commit_work);
12545         else
12546                 intel_atomic_commit_tail(state);
12547
12548
12549         return 0;
12550 }
12551
12552 static const struct drm_crtc_funcs intel_crtc_funcs = {
12553         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12554         .set_config = drm_atomic_helper_set_config,
12555         .destroy = intel_crtc_destroy,
12556         .page_flip = drm_atomic_helper_page_flip,
12557         .atomic_duplicate_state = intel_crtc_duplicate_state,
12558         .atomic_destroy_state = intel_crtc_destroy_state,
12559         .set_crc_source = intel_crtc_set_crc_source,
12560 };
12561
12562 struct wait_rps_boost {
12563         struct wait_queue_entry wait;
12564
12565         struct drm_crtc *crtc;
12566         struct drm_i915_gem_request *request;
12567 };
12568
12569 static int do_rps_boost(struct wait_queue_entry *_wait,
12570                         unsigned mode, int sync, void *key)
12571 {
12572         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12573         struct drm_i915_gem_request *rq = wait->request;
12574
12575         gen6_rps_boost(rq, NULL);
12576         i915_gem_request_put(rq);
12577
12578         drm_crtc_vblank_put(wait->crtc);
12579
12580         list_del(&wait->wait.entry);
12581         kfree(wait);
12582         return 1;
12583 }
12584
12585 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12586                                        struct dma_fence *fence)
12587 {
12588         struct wait_rps_boost *wait;
12589
12590         if (!dma_fence_is_i915(fence))
12591                 return;
12592
12593         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12594                 return;
12595
12596         if (drm_crtc_vblank_get(crtc))
12597                 return;
12598
12599         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12600         if (!wait) {
12601                 drm_crtc_vblank_put(crtc);
12602                 return;
12603         }
12604
12605         wait->request = to_request(dma_fence_get(fence));
12606         wait->crtc = crtc;
12607
12608         wait->wait.func = do_rps_boost;
12609         wait->wait.flags = 0;
12610
12611         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12612 }
12613
12614 /**
12615  * intel_prepare_plane_fb - Prepare fb for usage on plane
12616  * @plane: drm plane to prepare for
12617  * @fb: framebuffer to prepare for presentation
12618  *
12619  * Prepares a framebuffer for usage on a display plane.  Generally this
12620  * involves pinning the underlying object and updating the frontbuffer tracking
12621  * bits.  Some older platforms need special physical address handling for
12622  * cursor planes.
12623  *
12624  * Must be called with struct_mutex held.
12625  *
12626  * Returns 0 on success, negative error code on failure.
12627  */
12628 int
12629 intel_prepare_plane_fb(struct drm_plane *plane,
12630                        struct drm_plane_state *new_state)
12631 {
12632         struct intel_atomic_state *intel_state =
12633                 to_intel_atomic_state(new_state->state);
12634         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12635         struct drm_framebuffer *fb = new_state->fb;
12636         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12637         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12638         int ret;
12639
12640         if (old_obj) {
12641                 struct drm_crtc_state *crtc_state =
12642                         drm_atomic_get_existing_crtc_state(new_state->state,
12643                                                            plane->state->crtc);
12644
12645                 /* Big Hammer, we also need to ensure that any pending
12646                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12647                  * current scanout is retired before unpinning the old
12648                  * framebuffer. Note that we rely on userspace rendering
12649                  * into the buffer attached to the pipe they are waiting
12650                  * on. If not, userspace generates a GPU hang with IPEHR
12651                  * point to the MI_WAIT_FOR_EVENT.
12652                  *
12653                  * This should only fail upon a hung GPU, in which case we
12654                  * can safely continue.
12655                  */
12656                 if (needs_modeset(crtc_state)) {
12657                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12658                                                               old_obj->resv, NULL,
12659                                                               false, 0,
12660                                                               GFP_KERNEL);
12661                         if (ret < 0)
12662                                 return ret;
12663                 }
12664         }
12665
12666         if (new_state->fence) { /* explicit fencing */
12667                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12668                                                     new_state->fence,
12669                                                     I915_FENCE_TIMEOUT,
12670                                                     GFP_KERNEL);
12671                 if (ret < 0)
12672                         return ret;
12673         }
12674
12675         if (!obj)
12676                 return 0;
12677
12678         ret = i915_gem_object_pin_pages(obj);
12679         if (ret)
12680                 return ret;
12681
12682         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12683         if (ret) {
12684                 i915_gem_object_unpin_pages(obj);
12685                 return ret;
12686         }
12687
12688         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12689             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12690                 const int align = intel_cursor_alignment(dev_priv);
12691
12692                 ret = i915_gem_object_attach_phys(obj, align);
12693         } else {
12694                 struct i915_vma *vma;
12695
12696                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12697                 if (!IS_ERR(vma))
12698                         to_intel_plane_state(new_state)->vma = vma;
12699                 else
12700                         ret =  PTR_ERR(vma);
12701         }
12702
12703         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12704
12705         mutex_unlock(&dev_priv->drm.struct_mutex);
12706         i915_gem_object_unpin_pages(obj);
12707         if (ret)
12708                 return ret;
12709
12710         if (!new_state->fence) { /* implicit fencing */
12711                 struct dma_fence *fence;
12712
12713                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12714                                                       obj->resv, NULL,
12715                                                       false, I915_FENCE_TIMEOUT,
12716                                                       GFP_KERNEL);
12717                 if (ret < 0)
12718                         return ret;
12719
12720                 fence = reservation_object_get_excl_rcu(obj->resv);
12721                 if (fence) {
12722                         add_rps_boost_after_vblank(new_state->crtc, fence);
12723                         dma_fence_put(fence);
12724                 }
12725         } else {
12726                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12727         }
12728
12729         return 0;
12730 }
12731
12732 /**
12733  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12734  * @plane: drm plane to clean up for
12735  * @fb: old framebuffer that was on plane
12736  *
12737  * Cleans up a framebuffer that has just been removed from a plane.
12738  *
12739  * Must be called with struct_mutex held.
12740  */
12741 void
12742 intel_cleanup_plane_fb(struct drm_plane *plane,
12743                        struct drm_plane_state *old_state)
12744 {
12745         struct i915_vma *vma;
12746
12747         /* Should only be called after a successful intel_prepare_plane_fb()! */
12748         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12749         if (vma) {
12750                 mutex_lock(&plane->dev->struct_mutex);
12751                 intel_unpin_fb_vma(vma);
12752                 mutex_unlock(&plane->dev->struct_mutex);
12753         }
12754 }
12755
12756 int
12757 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12758 {
12759         struct drm_i915_private *dev_priv;
12760         int max_scale;
12761         int crtc_clock, max_dotclk;
12762
12763         if (!intel_crtc || !crtc_state->base.enable)
12764                 return DRM_PLANE_HELPER_NO_SCALING;
12765
12766         dev_priv = to_i915(intel_crtc->base.dev);
12767
12768         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12769         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12770
12771         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12772                 max_dotclk *= 2;
12773
12774         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12775                 return DRM_PLANE_HELPER_NO_SCALING;
12776
12777         /*
12778          * skl max scale is lower of:
12779          *    close to 3 but not 3, -1 is for that purpose
12780          *            or
12781          *    cdclk/crtc_clock
12782          */
12783         max_scale = min((1 << 16) * 3 - 1,
12784                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12785
12786         return max_scale;
12787 }
12788
12789 static int
12790 intel_check_primary_plane(struct intel_plane *plane,
12791                           struct intel_crtc_state *crtc_state,
12792                           struct intel_plane_state *state)
12793 {
12794         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12795         struct drm_crtc *crtc = state->base.crtc;
12796         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12797         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12798         bool can_position = false;
12799         int ret;
12800
12801         if (INTEL_GEN(dev_priv) >= 9) {
12802                 /* use scaler when colorkey is not required */
12803                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12804                         min_scale = 1;
12805                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12806                 }
12807                 can_position = true;
12808         }
12809
12810         ret = drm_plane_helper_check_state(&state->base,
12811                                            &state->clip,
12812                                            min_scale, max_scale,
12813                                            can_position, true);
12814         if (ret)
12815                 return ret;
12816
12817         if (!state->base.fb)
12818                 return 0;
12819
12820         if (INTEL_GEN(dev_priv) >= 9) {
12821                 ret = skl_check_plane_surface(state);
12822                 if (ret)
12823                         return ret;
12824
12825                 state->ctl = skl_plane_ctl(crtc_state, state);
12826         } else {
12827                 ret = i9xx_check_plane_surface(state);
12828                 if (ret)
12829                         return ret;
12830
12831                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12832         }
12833
12834         return 0;
12835 }
12836
12837 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12838                                     struct drm_crtc_state *old_crtc_state)
12839 {
12840         struct drm_device *dev = crtc->dev;
12841         struct drm_i915_private *dev_priv = to_i915(dev);
12842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12843         struct intel_crtc_state *old_intel_cstate =
12844                 to_intel_crtc_state(old_crtc_state);
12845         struct intel_atomic_state *old_intel_state =
12846                 to_intel_atomic_state(old_crtc_state->state);
12847         struct intel_crtc_state *intel_cstate =
12848                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12849         bool modeset = needs_modeset(&intel_cstate->base);
12850
12851         if (!modeset &&
12852             (intel_cstate->base.color_mgmt_changed ||
12853              intel_cstate->update_pipe)) {
12854                 intel_color_set_csc(&intel_cstate->base);
12855                 intel_color_load_luts(&intel_cstate->base);
12856         }
12857
12858         /* Perform vblank evasion around commit operation */
12859         intel_pipe_update_start(intel_cstate);
12860
12861         if (modeset)
12862                 goto out;
12863
12864         if (intel_cstate->update_pipe)
12865                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12866         else if (INTEL_GEN(dev_priv) >= 9)
12867                 skl_detach_scalers(intel_crtc);
12868
12869 out:
12870         if (dev_priv->display.atomic_update_watermarks)
12871                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12872                                                            intel_cstate);
12873 }
12874
12875 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12876                                      struct drm_crtc_state *old_crtc_state)
12877 {
12878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12879         struct intel_atomic_state *old_intel_state =
12880                 to_intel_atomic_state(old_crtc_state->state);
12881         struct intel_crtc_state *new_crtc_state =
12882                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12883
12884         intel_pipe_update_end(new_crtc_state);
12885 }
12886
12887 /**
12888  * intel_plane_destroy - destroy a plane
12889  * @plane: plane to destroy
12890  *
12891  * Common destruction function for all types of planes (primary, cursor,
12892  * sprite).
12893  */
12894 void intel_plane_destroy(struct drm_plane *plane)
12895 {
12896         drm_plane_cleanup(plane);
12897         kfree(to_intel_plane(plane));
12898 }
12899
12900 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12901 {
12902         switch (format) {
12903         case DRM_FORMAT_C8:
12904         case DRM_FORMAT_RGB565:
12905         case DRM_FORMAT_XRGB1555:
12906         case DRM_FORMAT_XRGB8888:
12907                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12908                         modifier == I915_FORMAT_MOD_X_TILED;
12909         default:
12910                 return false;
12911         }
12912 }
12913
12914 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12915 {
12916         switch (format) {
12917         case DRM_FORMAT_C8:
12918         case DRM_FORMAT_RGB565:
12919         case DRM_FORMAT_XRGB8888:
12920         case DRM_FORMAT_XBGR8888:
12921         case DRM_FORMAT_XRGB2101010:
12922         case DRM_FORMAT_XBGR2101010:
12923                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12924                         modifier == I915_FORMAT_MOD_X_TILED;
12925         default:
12926                 return false;
12927         }
12928 }
12929
12930 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12931 {
12932         switch (format) {
12933         case DRM_FORMAT_XRGB8888:
12934         case DRM_FORMAT_XBGR8888:
12935         case DRM_FORMAT_ARGB8888:
12936         case DRM_FORMAT_ABGR8888:
12937                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12938                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12939                         return true;
12940                 /* fall through */
12941         case DRM_FORMAT_RGB565:
12942         case DRM_FORMAT_XRGB2101010:
12943         case DRM_FORMAT_XBGR2101010:
12944         case DRM_FORMAT_YUYV:
12945         case DRM_FORMAT_YVYU:
12946         case DRM_FORMAT_UYVY:
12947         case DRM_FORMAT_VYUY:
12948                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12949                         return true;
12950                 /* fall through */
12951         case DRM_FORMAT_C8:
12952                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12953                     modifier == I915_FORMAT_MOD_X_TILED ||
12954                     modifier == I915_FORMAT_MOD_Y_TILED)
12955                         return true;
12956                 /* fall through */
12957         default:
12958                 return false;
12959         }
12960 }
12961
12962 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12963                                                      uint32_t format,
12964                                                      uint64_t modifier)
12965 {
12966         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12967
12968         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12969                 return false;
12970
12971         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12972             modifier != DRM_FORMAT_MOD_LINEAR)
12973                 return false;
12974
12975         if (INTEL_GEN(dev_priv) >= 9)
12976                 return skl_mod_supported(format, modifier);
12977         else if (INTEL_GEN(dev_priv) >= 4)
12978                 return i965_mod_supported(format, modifier);
12979         else
12980                 return i8xx_mod_supported(format, modifier);
12981
12982         unreachable();
12983 }
12984
12985 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12986                                                     uint32_t format,
12987                                                     uint64_t modifier)
12988 {
12989         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12990                 return false;
12991
12992         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12993 }
12994
12995 static struct drm_plane_funcs intel_plane_funcs = {
12996         .update_plane = drm_atomic_helper_update_plane,
12997         .disable_plane = drm_atomic_helper_disable_plane,
12998         .destroy = intel_plane_destroy,
12999         .atomic_get_property = intel_plane_atomic_get_property,
13000         .atomic_set_property = intel_plane_atomic_set_property,
13001         .atomic_duplicate_state = intel_plane_duplicate_state,
13002         .atomic_destroy_state = intel_plane_destroy_state,
13003         .format_mod_supported = intel_primary_plane_format_mod_supported,
13004 };
13005
13006 static int
13007 intel_legacy_cursor_update(struct drm_plane *plane,
13008                            struct drm_crtc *crtc,
13009                            struct drm_framebuffer *fb,
13010                            int crtc_x, int crtc_y,
13011                            unsigned int crtc_w, unsigned int crtc_h,
13012                            uint32_t src_x, uint32_t src_y,
13013                            uint32_t src_w, uint32_t src_h,
13014                            struct drm_modeset_acquire_ctx *ctx)
13015 {
13016         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13017         int ret;
13018         struct drm_plane_state *old_plane_state, *new_plane_state;
13019         struct intel_plane *intel_plane = to_intel_plane(plane);
13020         struct drm_framebuffer *old_fb;
13021         struct drm_crtc_state *crtc_state = crtc->state;
13022         struct i915_vma *old_vma, *vma;
13023
13024         /*
13025          * When crtc is inactive or there is a modeset pending,
13026          * wait for it to complete in the slowpath
13027          */
13028         if (!crtc_state->active || needs_modeset(crtc_state) ||
13029             to_intel_crtc_state(crtc_state)->update_pipe)
13030                 goto slow;
13031
13032         old_plane_state = plane->state;
13033         /*
13034          * Don't do an async update if there is an outstanding commit modifying
13035          * the plane.  This prevents our async update's changes from getting
13036          * overridden by a previous synchronous update's state.
13037          */
13038         if (old_plane_state->commit &&
13039             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13040                 goto slow;
13041
13042         /*
13043          * If any parameters change that may affect watermarks,
13044          * take the slowpath. Only changing fb or position should be
13045          * in the fastpath.
13046          */
13047         if (old_plane_state->crtc != crtc ||
13048             old_plane_state->src_w != src_w ||
13049             old_plane_state->src_h != src_h ||
13050             old_plane_state->crtc_w != crtc_w ||
13051             old_plane_state->crtc_h != crtc_h ||
13052             !old_plane_state->fb != !fb)
13053                 goto slow;
13054
13055         new_plane_state = intel_plane_duplicate_state(plane);
13056         if (!new_plane_state)
13057                 return -ENOMEM;
13058
13059         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13060
13061         new_plane_state->src_x = src_x;
13062         new_plane_state->src_y = src_y;
13063         new_plane_state->src_w = src_w;
13064         new_plane_state->src_h = src_h;
13065         new_plane_state->crtc_x = crtc_x;
13066         new_plane_state->crtc_y = crtc_y;
13067         new_plane_state->crtc_w = crtc_w;
13068         new_plane_state->crtc_h = crtc_h;
13069
13070         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13071                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13072                                                   to_intel_plane_state(plane->state),
13073                                                   to_intel_plane_state(new_plane_state));
13074         if (ret)
13075                 goto out_free;
13076
13077         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13078         if (ret)
13079                 goto out_free;
13080
13081         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13082                 int align = intel_cursor_alignment(dev_priv);
13083
13084                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13085                 if (ret) {
13086                         DRM_DEBUG_KMS("failed to attach phys object\n");
13087                         goto out_unlock;
13088                 }
13089         } else {
13090                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13091                 if (IS_ERR(vma)) {
13092                         DRM_DEBUG_KMS("failed to pin object\n");
13093
13094                         ret = PTR_ERR(vma);
13095                         goto out_unlock;
13096                 }
13097
13098                 to_intel_plane_state(new_plane_state)->vma = vma;
13099         }
13100
13101         old_fb = old_plane_state->fb;
13102
13103         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13104                           intel_plane->frontbuffer_bit);
13105
13106         /* Swap plane state */
13107         plane->state = new_plane_state;
13108
13109         if (plane->state->visible) {
13110                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13111                 intel_plane->update_plane(intel_plane,
13112                                           to_intel_crtc_state(crtc->state),
13113                                           to_intel_plane_state(plane->state));
13114         } else {
13115                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13116                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13117         }
13118
13119         old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13120         if (old_vma)
13121                 intel_unpin_fb_vma(old_vma);
13122
13123 out_unlock:
13124         mutex_unlock(&dev_priv->drm.struct_mutex);
13125 out_free:
13126         if (ret)
13127                 intel_plane_destroy_state(plane, new_plane_state);
13128         else
13129                 intel_plane_destroy_state(plane, old_plane_state);
13130         return ret;
13131
13132 slow:
13133         return drm_atomic_helper_update_plane(plane, crtc, fb,
13134                                               crtc_x, crtc_y, crtc_w, crtc_h,
13135                                               src_x, src_y, src_w, src_h, ctx);
13136 }
13137
13138 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13139         .update_plane = intel_legacy_cursor_update,
13140         .disable_plane = drm_atomic_helper_disable_plane,
13141         .destroy = intel_plane_destroy,
13142         .atomic_get_property = intel_plane_atomic_get_property,
13143         .atomic_set_property = intel_plane_atomic_set_property,
13144         .atomic_duplicate_state = intel_plane_duplicate_state,
13145         .atomic_destroy_state = intel_plane_destroy_state,
13146         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13147 };
13148
13149 static struct intel_plane *
13150 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13151 {
13152         struct intel_plane *primary = NULL;
13153         struct intel_plane_state *state = NULL;
13154         const uint32_t *intel_primary_formats;
13155         unsigned int supported_rotations;
13156         unsigned int num_formats;
13157         const uint64_t *modifiers;
13158         int ret;
13159
13160         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13161         if (!primary) {
13162                 ret = -ENOMEM;
13163                 goto fail;
13164         }
13165
13166         state = intel_create_plane_state(&primary->base);
13167         if (!state) {
13168                 ret = -ENOMEM;
13169                 goto fail;
13170         }
13171
13172         primary->base.state = &state->base;
13173
13174         primary->can_scale = false;
13175         primary->max_downscale = 1;
13176         if (INTEL_GEN(dev_priv) >= 9) {
13177                 primary->can_scale = true;
13178                 state->scaler_id = -1;
13179         }
13180         primary->pipe = pipe;
13181         /*
13182          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13183          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13184          */
13185         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13186                 primary->plane = (enum plane) !pipe;
13187         else
13188                 primary->plane = (enum plane) pipe;
13189         primary->id = PLANE_PRIMARY;
13190         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13191         primary->check_plane = intel_check_primary_plane;
13192
13193         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13194                 intel_primary_formats = skl_primary_formats;
13195                 num_formats = ARRAY_SIZE(skl_primary_formats);
13196                 modifiers = skl_format_modifiers_ccs;
13197
13198                 primary->update_plane = skl_update_plane;
13199                 primary->disable_plane = skl_disable_plane;
13200         } else if (INTEL_GEN(dev_priv) >= 9) {
13201                 intel_primary_formats = skl_primary_formats;
13202                 num_formats = ARRAY_SIZE(skl_primary_formats);
13203                 if (pipe < PIPE_C)
13204                         modifiers = skl_format_modifiers_ccs;
13205                 else
13206                         modifiers = skl_format_modifiers_noccs;
13207
13208                 primary->update_plane = skl_update_plane;
13209                 primary->disable_plane = skl_disable_plane;
13210         } else if (INTEL_GEN(dev_priv) >= 4) {
13211                 intel_primary_formats = i965_primary_formats;
13212                 num_formats = ARRAY_SIZE(i965_primary_formats);
13213                 modifiers = i9xx_format_modifiers;
13214
13215                 primary->update_plane = i9xx_update_primary_plane;
13216                 primary->disable_plane = i9xx_disable_primary_plane;
13217         } else {
13218                 intel_primary_formats = i8xx_primary_formats;
13219                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13220                 modifiers = i9xx_format_modifiers;
13221
13222                 primary->update_plane = i9xx_update_primary_plane;
13223                 primary->disable_plane = i9xx_disable_primary_plane;
13224         }
13225
13226         if (INTEL_GEN(dev_priv) >= 9)
13227                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13228                                                0, &intel_plane_funcs,
13229                                                intel_primary_formats, num_formats,
13230                                                modifiers,
13231                                                DRM_PLANE_TYPE_PRIMARY,
13232                                                "plane 1%c", pipe_name(pipe));
13233         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13234                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13235                                                0, &intel_plane_funcs,
13236                                                intel_primary_formats, num_formats,
13237                                                modifiers,
13238                                                DRM_PLANE_TYPE_PRIMARY,
13239                                                "primary %c", pipe_name(pipe));
13240         else
13241                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13242                                                0, &intel_plane_funcs,
13243                                                intel_primary_formats, num_formats,
13244                                                modifiers,
13245                                                DRM_PLANE_TYPE_PRIMARY,
13246                                                "plane %c", plane_name(primary->plane));
13247         if (ret)
13248                 goto fail;
13249
13250         if (INTEL_GEN(dev_priv) >= 9) {
13251                 supported_rotations =
13252                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13253                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13254         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13255                 supported_rotations =
13256                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13257                         DRM_MODE_REFLECT_X;
13258         } else if (INTEL_GEN(dev_priv) >= 4) {
13259                 supported_rotations =
13260                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13261         } else {
13262                 supported_rotations = DRM_MODE_ROTATE_0;
13263         }
13264
13265         if (INTEL_GEN(dev_priv) >= 4)
13266                 drm_plane_create_rotation_property(&primary->base,
13267                                                    DRM_MODE_ROTATE_0,
13268                                                    supported_rotations);
13269
13270         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13271
13272         return primary;
13273
13274 fail:
13275         kfree(state);
13276         kfree(primary);
13277
13278         return ERR_PTR(ret);
13279 }
13280
13281 static struct intel_plane *
13282 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13283                           enum pipe pipe)
13284 {
13285         struct intel_plane *cursor = NULL;
13286         struct intel_plane_state *state = NULL;
13287         int ret;
13288
13289         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13290         if (!cursor) {
13291                 ret = -ENOMEM;
13292                 goto fail;
13293         }
13294
13295         state = intel_create_plane_state(&cursor->base);
13296         if (!state) {
13297                 ret = -ENOMEM;
13298                 goto fail;
13299         }
13300
13301         cursor->base.state = &state->base;
13302
13303         cursor->can_scale = false;
13304         cursor->max_downscale = 1;
13305         cursor->pipe = pipe;
13306         cursor->plane = pipe;
13307         cursor->id = PLANE_CURSOR;
13308         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13309
13310         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13311                 cursor->update_plane = i845_update_cursor;
13312                 cursor->disable_plane = i845_disable_cursor;
13313                 cursor->check_plane = i845_check_cursor;
13314         } else {
13315                 cursor->update_plane = i9xx_update_cursor;
13316                 cursor->disable_plane = i9xx_disable_cursor;
13317                 cursor->check_plane = i9xx_check_cursor;
13318         }
13319
13320         cursor->cursor.base = ~0;
13321         cursor->cursor.cntl = ~0;
13322
13323         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13324                 cursor->cursor.size = ~0;
13325
13326         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13327                                        0, &intel_cursor_plane_funcs,
13328                                        intel_cursor_formats,
13329                                        ARRAY_SIZE(intel_cursor_formats),
13330                                        cursor_format_modifiers,
13331                                        DRM_PLANE_TYPE_CURSOR,
13332                                        "cursor %c", pipe_name(pipe));
13333         if (ret)
13334                 goto fail;
13335
13336         if (INTEL_GEN(dev_priv) >= 4)
13337                 drm_plane_create_rotation_property(&cursor->base,
13338                                                    DRM_MODE_ROTATE_0,
13339                                                    DRM_MODE_ROTATE_0 |
13340                                                    DRM_MODE_ROTATE_180);
13341
13342         if (INTEL_GEN(dev_priv) >= 9)
13343                 state->scaler_id = -1;
13344
13345         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13346
13347         return cursor;
13348
13349 fail:
13350         kfree(state);
13351         kfree(cursor);
13352
13353         return ERR_PTR(ret);
13354 }
13355
13356 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13357                                     struct intel_crtc_state *crtc_state)
13358 {
13359         struct intel_crtc_scaler_state *scaler_state =
13360                 &crtc_state->scaler_state;
13361         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13362         int i;
13363
13364         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13365         if (!crtc->num_scalers)
13366                 return;
13367
13368         for (i = 0; i < crtc->num_scalers; i++) {
13369                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13370
13371                 scaler->in_use = 0;
13372                 scaler->mode = PS_SCALER_MODE_DYN;
13373         }
13374
13375         scaler_state->scaler_id = -1;
13376 }
13377
13378 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13379 {
13380         struct intel_crtc *intel_crtc;
13381         struct intel_crtc_state *crtc_state = NULL;
13382         struct intel_plane *primary = NULL;
13383         struct intel_plane *cursor = NULL;
13384         int sprite, ret;
13385
13386         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13387         if (!intel_crtc)
13388                 return -ENOMEM;
13389
13390         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13391         if (!crtc_state) {
13392                 ret = -ENOMEM;
13393                 goto fail;
13394         }
13395         intel_crtc->config = crtc_state;
13396         intel_crtc->base.state = &crtc_state->base;
13397         crtc_state->base.crtc = &intel_crtc->base;
13398
13399         primary = intel_primary_plane_create(dev_priv, pipe);
13400         if (IS_ERR(primary)) {
13401                 ret = PTR_ERR(primary);
13402                 goto fail;
13403         }
13404         intel_crtc->plane_ids_mask |= BIT(primary->id);
13405
13406         for_each_sprite(dev_priv, pipe, sprite) {
13407                 struct intel_plane *plane;
13408
13409                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13410                 if (IS_ERR(plane)) {
13411                         ret = PTR_ERR(plane);
13412                         goto fail;
13413                 }
13414                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13415         }
13416
13417         cursor = intel_cursor_plane_create(dev_priv, pipe);
13418         if (IS_ERR(cursor)) {
13419                 ret = PTR_ERR(cursor);
13420                 goto fail;
13421         }
13422         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13423
13424         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13425                                         &primary->base, &cursor->base,
13426                                         &intel_crtc_funcs,
13427                                         "pipe %c", pipe_name(pipe));
13428         if (ret)
13429                 goto fail;
13430
13431         intel_crtc->pipe = pipe;
13432         intel_crtc->plane = primary->plane;
13433
13434         /* initialize shared scalers */
13435         intel_crtc_init_scalers(intel_crtc, crtc_state);
13436
13437         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13438                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13439         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13440         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13441
13442         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13443
13444         intel_color_init(&intel_crtc->base);
13445
13446         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13447
13448         return 0;
13449
13450 fail:
13451         /*
13452          * drm_mode_config_cleanup() will free up any
13453          * crtcs/planes already initialized.
13454          */
13455         kfree(crtc_state);
13456         kfree(intel_crtc);
13457
13458         return ret;
13459 }
13460
13461 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13462 {
13463         struct drm_device *dev = connector->base.dev;
13464
13465         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13466
13467         if (!connector->base.state->crtc)
13468                 return INVALID_PIPE;
13469
13470         return to_intel_crtc(connector->base.state->crtc)->pipe;
13471 }
13472
13473 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13474                                 struct drm_file *file)
13475 {
13476         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13477         struct drm_crtc *drmmode_crtc;
13478         struct intel_crtc *crtc;
13479
13480         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13481         if (!drmmode_crtc)
13482                 return -ENOENT;
13483
13484         crtc = to_intel_crtc(drmmode_crtc);
13485         pipe_from_crtc_id->pipe = crtc->pipe;
13486
13487         return 0;
13488 }
13489
13490 static int intel_encoder_clones(struct intel_encoder *encoder)
13491 {
13492         struct drm_device *dev = encoder->base.dev;
13493         struct intel_encoder *source_encoder;
13494         int index_mask = 0;
13495         int entry = 0;
13496
13497         for_each_intel_encoder(dev, source_encoder) {
13498                 if (encoders_cloneable(encoder, source_encoder))
13499                         index_mask |= (1 << entry);
13500
13501                 entry++;
13502         }
13503
13504         return index_mask;
13505 }
13506
13507 static bool has_edp_a(struct drm_i915_private *dev_priv)
13508 {
13509         if (!IS_MOBILE(dev_priv))
13510                 return false;
13511
13512         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13513                 return false;
13514
13515         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13516                 return false;
13517
13518         return true;
13519 }
13520
13521 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13522 {
13523         if (INTEL_GEN(dev_priv) >= 9)
13524                 return false;
13525
13526         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13527                 return false;
13528
13529         if (IS_CHERRYVIEW(dev_priv))
13530                 return false;
13531
13532         if (HAS_PCH_LPT_H(dev_priv) &&
13533             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13534                 return false;
13535
13536         /* DDI E can't be used if DDI A requires 4 lanes */
13537         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13538                 return false;
13539
13540         if (!dev_priv->vbt.int_crt_support)
13541                 return false;
13542
13543         return true;
13544 }
13545
13546 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13547 {
13548         int pps_num;
13549         int pps_idx;
13550
13551         if (HAS_DDI(dev_priv))
13552                 return;
13553         /*
13554          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13555          * everywhere where registers can be write protected.
13556          */
13557         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13558                 pps_num = 2;
13559         else
13560                 pps_num = 1;
13561
13562         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13563                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13564
13565                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13566                 I915_WRITE(PP_CONTROL(pps_idx), val);
13567         }
13568 }
13569
13570 static void intel_pps_init(struct drm_i915_private *dev_priv)
13571 {
13572         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13573                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13574         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13575                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13576         else
13577                 dev_priv->pps_mmio_base = PPS_BASE;
13578
13579         intel_pps_unlock_regs_wa(dev_priv);
13580 }
13581
13582 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13583 {
13584         struct intel_encoder *encoder;
13585         bool dpd_is_edp = false;
13586
13587         intel_pps_init(dev_priv);
13588
13589         /*
13590          * intel_edp_init_connector() depends on this completing first, to
13591          * prevent the registeration of both eDP and LVDS and the incorrect
13592          * sharing of the PPS.
13593          */
13594         intel_lvds_init(dev_priv);
13595
13596         if (intel_crt_present(dev_priv))
13597                 intel_crt_init(dev_priv);
13598
13599         if (IS_GEN9_LP(dev_priv)) {
13600                 /*
13601                  * FIXME: Broxton doesn't support port detection via the
13602                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13603                  * detect the ports.
13604                  */
13605                 intel_ddi_init(dev_priv, PORT_A);
13606                 intel_ddi_init(dev_priv, PORT_B);
13607                 intel_ddi_init(dev_priv, PORT_C);
13608
13609                 intel_dsi_init(dev_priv);
13610         } else if (HAS_DDI(dev_priv)) {
13611                 int found;
13612
13613                 /*
13614                  * Haswell uses DDI functions to detect digital outputs.
13615                  * On SKL pre-D0 the strap isn't connected, so we assume
13616                  * it's there.
13617                  */
13618                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13619                 /* WaIgnoreDDIAStrap: skl */
13620                 if (found || IS_GEN9_BC(dev_priv))
13621                         intel_ddi_init(dev_priv, PORT_A);
13622
13623                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13624                  * register */
13625                 found = I915_READ(SFUSE_STRAP);
13626
13627                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13628                         intel_ddi_init(dev_priv, PORT_B);
13629                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13630                         intel_ddi_init(dev_priv, PORT_C);
13631                 if (found & SFUSE_STRAP_DDID_DETECTED)
13632                         intel_ddi_init(dev_priv, PORT_D);
13633                 /*
13634                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13635                  */
13636                 if (IS_GEN9_BC(dev_priv) &&
13637                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13638                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13639                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13640                         intel_ddi_init(dev_priv, PORT_E);
13641
13642         } else if (HAS_PCH_SPLIT(dev_priv)) {
13643                 int found;
13644                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13645
13646                 if (has_edp_a(dev_priv))
13647                         intel_dp_init(dev_priv, DP_A, PORT_A);
13648
13649                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13650                         /* PCH SDVOB multiplex with HDMIB */
13651                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13652                         if (!found)
13653                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13654                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13655                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13656                 }
13657
13658                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13659                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13660
13661                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13662                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13663
13664                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13665                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13666
13667                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13668                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13669         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13670                 bool has_edp, has_port;
13671
13672                 /*
13673                  * The DP_DETECTED bit is the latched state of the DDC
13674                  * SDA pin at boot. However since eDP doesn't require DDC
13675                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13676                  * eDP ports may have been muxed to an alternate function.
13677                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13678                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13679                  * detect eDP ports.
13680                  *
13681                  * Sadly the straps seem to be missing sometimes even for HDMI
13682                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13683                  * and VBT for the presence of the port. Additionally we can't
13684                  * trust the port type the VBT declares as we've seen at least
13685                  * HDMI ports that the VBT claim are DP or eDP.
13686                  */
13687                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13688                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13689                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13690                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13691                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13692                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13693
13694                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13695                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13696                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13697                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13698                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13699                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13700
13701                 if (IS_CHERRYVIEW(dev_priv)) {
13702                         /*
13703                          * eDP not supported on port D,
13704                          * so no need to worry about it
13705                          */
13706                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13707                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13708                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13709                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13710                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13711                 }
13712
13713                 intel_dsi_init(dev_priv);
13714         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13715                 bool found = false;
13716
13717                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13718                         DRM_DEBUG_KMS("probing SDVOB\n");
13719                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13720                         if (!found && IS_G4X(dev_priv)) {
13721                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13722                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13723                         }
13724
13725                         if (!found && IS_G4X(dev_priv))
13726                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13727                 }
13728
13729                 /* Before G4X SDVOC doesn't have its own detect register */
13730
13731                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13732                         DRM_DEBUG_KMS("probing SDVOC\n");
13733                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13734                 }
13735
13736                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13737
13738                         if (IS_G4X(dev_priv)) {
13739                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13740                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13741                         }
13742                         if (IS_G4X(dev_priv))
13743                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13744                 }
13745
13746                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13747                         intel_dp_init(dev_priv, DP_D, PORT_D);
13748         } else if (IS_GEN2(dev_priv))
13749                 intel_dvo_init(dev_priv);
13750
13751         if (SUPPORTS_TV(dev_priv))
13752                 intel_tv_init(dev_priv);
13753
13754         intel_psr_init(dev_priv);
13755
13756         for_each_intel_encoder(&dev_priv->drm, encoder) {
13757                 encoder->base.possible_crtcs = encoder->crtc_mask;
13758                 encoder->base.possible_clones =
13759                         intel_encoder_clones(encoder);
13760         }
13761
13762         intel_init_pch_refclk(dev_priv);
13763
13764         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13765 }
13766
13767 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13768 {
13769         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13770
13771         drm_framebuffer_cleanup(fb);
13772
13773         i915_gem_object_lock(intel_fb->obj);
13774         WARN_ON(!intel_fb->obj->framebuffer_references--);
13775         i915_gem_object_unlock(intel_fb->obj);
13776
13777         i915_gem_object_put(intel_fb->obj);
13778
13779         kfree(intel_fb);
13780 }
13781
13782 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13783                                                 struct drm_file *file,
13784                                                 unsigned int *handle)
13785 {
13786         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13787         struct drm_i915_gem_object *obj = intel_fb->obj;
13788
13789         if (obj->userptr.mm) {
13790                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13791                 return -EINVAL;
13792         }
13793
13794         return drm_gem_handle_create(file, &obj->base, handle);
13795 }
13796
13797 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13798                                         struct drm_file *file,
13799                                         unsigned flags, unsigned color,
13800                                         struct drm_clip_rect *clips,
13801                                         unsigned num_clips)
13802 {
13803         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13804
13805         i915_gem_object_flush_if_display(obj);
13806         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13807
13808         return 0;
13809 }
13810
13811 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13812         .destroy = intel_user_framebuffer_destroy,
13813         .create_handle = intel_user_framebuffer_create_handle,
13814         .dirty = intel_user_framebuffer_dirty,
13815 };
13816
13817 static
13818 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13819                          uint64_t fb_modifier, uint32_t pixel_format)
13820 {
13821         u32 gen = INTEL_GEN(dev_priv);
13822
13823         if (gen >= 9) {
13824                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13825
13826                 /* "The stride in bytes must not exceed the of the size of 8K
13827                  *  pixels and 32K bytes."
13828                  */
13829                 return min(8192 * cpp, 32768);
13830         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13831                 return 32*1024;
13832         } else if (gen >= 4) {
13833                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13834                         return 16*1024;
13835                 else
13836                         return 32*1024;
13837         } else if (gen >= 3) {
13838                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13839                         return 8*1024;
13840                 else
13841                         return 16*1024;
13842         } else {
13843                 /* XXX DSPC is limited to 4k tiled */
13844                 return 8*1024;
13845         }
13846 }
13847
13848 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13849                                   struct drm_i915_gem_object *obj,
13850                                   struct drm_mode_fb_cmd2 *mode_cmd)
13851 {
13852         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13853         struct drm_framebuffer *fb = &intel_fb->base;
13854         struct drm_format_name_buf format_name;
13855         u32 pitch_limit;
13856         unsigned int tiling, stride;
13857         int ret = -EINVAL;
13858         int i;
13859
13860         i915_gem_object_lock(obj);
13861         obj->framebuffer_references++;
13862         tiling = i915_gem_object_get_tiling(obj);
13863         stride = i915_gem_object_get_stride(obj);
13864         i915_gem_object_unlock(obj);
13865
13866         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13867                 /*
13868                  * If there's a fence, enforce that
13869                  * the fb modifier and tiling mode match.
13870                  */
13871                 if (tiling != I915_TILING_NONE &&
13872                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13873                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13874                         goto err;
13875                 }
13876         } else {
13877                 if (tiling == I915_TILING_X) {
13878                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13879                 } else if (tiling == I915_TILING_Y) {
13880                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13881                         goto err;
13882                 }
13883         }
13884
13885         /* Passed in modifier sanity checking. */
13886         switch (mode_cmd->modifier[0]) {
13887         case I915_FORMAT_MOD_Y_TILED_CCS:
13888         case I915_FORMAT_MOD_Yf_TILED_CCS:
13889                 switch (mode_cmd->pixel_format) {
13890                 case DRM_FORMAT_XBGR8888:
13891                 case DRM_FORMAT_ABGR8888:
13892                 case DRM_FORMAT_XRGB8888:
13893                 case DRM_FORMAT_ARGB8888:
13894                         break;
13895                 default:
13896                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13897                         goto err;
13898                 }
13899                 /* fall through */
13900         case I915_FORMAT_MOD_Y_TILED:
13901         case I915_FORMAT_MOD_Yf_TILED:
13902                 if (INTEL_GEN(dev_priv) < 9) {
13903                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13904                                       mode_cmd->modifier[0]);
13905                         goto err;
13906                 }
13907         case DRM_FORMAT_MOD_LINEAR:
13908         case I915_FORMAT_MOD_X_TILED:
13909                 break;
13910         default:
13911                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13912                               mode_cmd->modifier[0]);
13913                 goto err;
13914         }
13915
13916         /*
13917          * gen2/3 display engine uses the fence if present,
13918          * so the tiling mode must match the fb modifier exactly.
13919          */
13920         if (INTEL_INFO(dev_priv)->gen < 4 &&
13921             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13922                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13923                 goto err;
13924         }
13925
13926         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13927                                            mode_cmd->pixel_format);
13928         if (mode_cmd->pitches[0] > pitch_limit) {
13929                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13930                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13931                               "tiled" : "linear",
13932                               mode_cmd->pitches[0], pitch_limit);
13933                 goto err;
13934         }
13935
13936         /*
13937          * If there's a fence, enforce that
13938          * the fb pitch and fence stride match.
13939          */
13940         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13941                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13942                               mode_cmd->pitches[0], stride);
13943                 goto err;
13944         }
13945
13946         /* Reject formats not supported by any plane early. */
13947         switch (mode_cmd->pixel_format) {
13948         case DRM_FORMAT_C8:
13949         case DRM_FORMAT_RGB565:
13950         case DRM_FORMAT_XRGB8888:
13951         case DRM_FORMAT_ARGB8888:
13952                 break;
13953         case DRM_FORMAT_XRGB1555:
13954                 if (INTEL_GEN(dev_priv) > 3) {
13955                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13956                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13957                         goto err;
13958                 }
13959                 break;
13960         case DRM_FORMAT_ABGR8888:
13961                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13962                     INTEL_GEN(dev_priv) < 9) {
13963                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13964                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13965                         goto err;
13966                 }
13967                 break;
13968         case DRM_FORMAT_XBGR8888:
13969         case DRM_FORMAT_XRGB2101010:
13970         case DRM_FORMAT_XBGR2101010:
13971                 if (INTEL_GEN(dev_priv) < 4) {
13972                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13973                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13974                         goto err;
13975                 }
13976                 break;
13977         case DRM_FORMAT_ABGR2101010:
13978                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13979                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13980                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13981                         goto err;
13982                 }
13983                 break;
13984         case DRM_FORMAT_YUYV:
13985         case DRM_FORMAT_UYVY:
13986         case DRM_FORMAT_YVYU:
13987         case DRM_FORMAT_VYUY:
13988                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13989                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13990                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13991                         goto err;
13992                 }
13993                 break;
13994         default:
13995                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13996                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
13997                 goto err;
13998         }
13999
14000         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14001         if (mode_cmd->offsets[0] != 0)
14002                 goto err;
14003
14004         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14005
14006         for (i = 0; i < fb->format->num_planes; i++) {
14007                 u32 stride_alignment;
14008
14009                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14010                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14011                         goto err;
14012                 }
14013
14014                 stride_alignment = intel_fb_stride_alignment(fb, i);
14015
14016                 /*
14017                  * Display WA #0531: skl,bxt,kbl,glk
14018                  *
14019                  * Render decompression and plane width > 3840
14020                  * combined with horizontal panning requires the
14021                  * plane stride to be a multiple of 4. We'll just
14022                  * require the entire fb to accommodate that to avoid
14023                  * potential runtime errors at plane configuration time.
14024                  */
14025                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14026                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14027                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14028                         stride_alignment *= 4;
14029
14030                 if (fb->pitches[i] & (stride_alignment - 1)) {
14031                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14032                                       i, fb->pitches[i], stride_alignment);
14033                         goto err;
14034                 }
14035         }
14036
14037         intel_fb->obj = obj;
14038
14039         ret = intel_fill_fb_info(dev_priv, fb);
14040         if (ret)
14041                 goto err;
14042
14043         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14044         if (ret) {
14045                 DRM_ERROR("framebuffer init failed %d\n", ret);
14046                 goto err;
14047         }
14048
14049         return 0;
14050
14051 err:
14052         i915_gem_object_lock(obj);
14053         obj->framebuffer_references--;
14054         i915_gem_object_unlock(obj);
14055         return ret;
14056 }
14057
14058 static struct drm_framebuffer *
14059 intel_user_framebuffer_create(struct drm_device *dev,
14060                               struct drm_file *filp,
14061                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14062 {
14063         struct drm_framebuffer *fb;
14064         struct drm_i915_gem_object *obj;
14065         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14066
14067         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14068         if (!obj)
14069                 return ERR_PTR(-ENOENT);
14070
14071         fb = intel_framebuffer_create(obj, &mode_cmd);
14072         if (IS_ERR(fb))
14073                 i915_gem_object_put(obj);
14074
14075         return fb;
14076 }
14077
14078 static void intel_atomic_state_free(struct drm_atomic_state *state)
14079 {
14080         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14081
14082         drm_atomic_state_default_release(state);
14083
14084         i915_sw_fence_fini(&intel_state->commit_ready);
14085
14086         kfree(state);
14087 }
14088
14089 static const struct drm_mode_config_funcs intel_mode_funcs = {
14090         .fb_create = intel_user_framebuffer_create,
14091         .get_format_info = intel_get_format_info,
14092         .output_poll_changed = intel_fbdev_output_poll_changed,
14093         .atomic_check = intel_atomic_check,
14094         .atomic_commit = intel_atomic_commit,
14095         .atomic_state_alloc = intel_atomic_state_alloc,
14096         .atomic_state_clear = intel_atomic_state_clear,
14097         .atomic_state_free = intel_atomic_state_free,
14098 };
14099
14100 /**
14101  * intel_init_display_hooks - initialize the display modesetting hooks
14102  * @dev_priv: device private
14103  */
14104 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14105 {
14106         intel_init_cdclk_hooks(dev_priv);
14107
14108         if (INTEL_INFO(dev_priv)->gen >= 9) {
14109                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14110                 dev_priv->display.get_initial_plane_config =
14111                         skylake_get_initial_plane_config;
14112                 dev_priv->display.crtc_compute_clock =
14113                         haswell_crtc_compute_clock;
14114                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14115                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14116         } else if (HAS_DDI(dev_priv)) {
14117                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14118                 dev_priv->display.get_initial_plane_config =
14119                         ironlake_get_initial_plane_config;
14120                 dev_priv->display.crtc_compute_clock =
14121                         haswell_crtc_compute_clock;
14122                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14123                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14124         } else if (HAS_PCH_SPLIT(dev_priv)) {
14125                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14126                 dev_priv->display.get_initial_plane_config =
14127                         ironlake_get_initial_plane_config;
14128                 dev_priv->display.crtc_compute_clock =
14129                         ironlake_crtc_compute_clock;
14130                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14131                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14132         } else if (IS_CHERRYVIEW(dev_priv)) {
14133                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14134                 dev_priv->display.get_initial_plane_config =
14135                         i9xx_get_initial_plane_config;
14136                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14137                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14138                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14139         } else if (IS_VALLEYVIEW(dev_priv)) {
14140                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14141                 dev_priv->display.get_initial_plane_config =
14142                         i9xx_get_initial_plane_config;
14143                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14144                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14145                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14146         } else if (IS_G4X(dev_priv)) {
14147                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14148                 dev_priv->display.get_initial_plane_config =
14149                         i9xx_get_initial_plane_config;
14150                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14151                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14152                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14153         } else if (IS_PINEVIEW(dev_priv)) {
14154                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14155                 dev_priv->display.get_initial_plane_config =
14156                         i9xx_get_initial_plane_config;
14157                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14158                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14159                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14160         } else if (!IS_GEN2(dev_priv)) {
14161                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14162                 dev_priv->display.get_initial_plane_config =
14163                         i9xx_get_initial_plane_config;
14164                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14165                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14166                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14167         } else {
14168                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14169                 dev_priv->display.get_initial_plane_config =
14170                         i9xx_get_initial_plane_config;
14171                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14172                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14173                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14174         }
14175
14176         if (IS_GEN5(dev_priv)) {
14177                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14178         } else if (IS_GEN6(dev_priv)) {
14179                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14180         } else if (IS_IVYBRIDGE(dev_priv)) {
14181                 /* FIXME: detect B0+ stepping and use auto training */
14182                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14183         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14184                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14185         }
14186
14187         if (INTEL_GEN(dev_priv) >= 9)
14188                 dev_priv->display.update_crtcs = skl_update_crtcs;
14189         else
14190                 dev_priv->display.update_crtcs = intel_update_crtcs;
14191 }
14192
14193 /*
14194  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14195  */
14196 static void quirk_ssc_force_disable(struct drm_device *dev)
14197 {
14198         struct drm_i915_private *dev_priv = to_i915(dev);
14199         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14200         DRM_INFO("applying lvds SSC disable quirk\n");
14201 }
14202
14203 /*
14204  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14205  * brightness value
14206  */
14207 static void quirk_invert_brightness(struct drm_device *dev)
14208 {
14209         struct drm_i915_private *dev_priv = to_i915(dev);
14210         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14211         DRM_INFO("applying inverted panel brightness quirk\n");
14212 }
14213
14214 /* Some VBT's incorrectly indicate no backlight is present */
14215 static void quirk_backlight_present(struct drm_device *dev)
14216 {
14217         struct drm_i915_private *dev_priv = to_i915(dev);
14218         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14219         DRM_INFO("applying backlight present quirk\n");
14220 }
14221
14222 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14223  * which is 300 ms greater than eDP spec T12 min.
14224  */
14225 static void quirk_increase_t12_delay(struct drm_device *dev)
14226 {
14227         struct drm_i915_private *dev_priv = to_i915(dev);
14228
14229         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14230         DRM_INFO("Applying T12 delay quirk\n");
14231 }
14232
14233 struct intel_quirk {
14234         int device;
14235         int subsystem_vendor;
14236         int subsystem_device;
14237         void (*hook)(struct drm_device *dev);
14238 };
14239
14240 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14241 struct intel_dmi_quirk {
14242         void (*hook)(struct drm_device *dev);
14243         const struct dmi_system_id (*dmi_id_list)[];
14244 };
14245
14246 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14247 {
14248         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14249         return 1;
14250 }
14251
14252 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14253         {
14254                 .dmi_id_list = &(const struct dmi_system_id[]) {
14255                         {
14256                                 .callback = intel_dmi_reverse_brightness,
14257                                 .ident = "NCR Corporation",
14258                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14259                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14260                                 },
14261                         },
14262                         { }  /* terminating entry */
14263                 },
14264                 .hook = quirk_invert_brightness,
14265         },
14266 };
14267
14268 static struct intel_quirk intel_quirks[] = {
14269         /* Lenovo U160 cannot use SSC on LVDS */
14270         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14271
14272         /* Sony Vaio Y cannot use SSC on LVDS */
14273         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14274
14275         /* Acer Aspire 5734Z must invert backlight brightness */
14276         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14277
14278         /* Acer/eMachines G725 */
14279         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14280
14281         /* Acer/eMachines e725 */
14282         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14283
14284         /* Acer/Packard Bell NCL20 */
14285         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14286
14287         /* Acer Aspire 4736Z */
14288         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14289
14290         /* Acer Aspire 5336 */
14291         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14292
14293         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14294         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14295
14296         /* Acer C720 Chromebook (Core i3 4005U) */
14297         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14298
14299         /* Apple Macbook 2,1 (Core 2 T7400) */
14300         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14301
14302         /* Apple Macbook 4,1 */
14303         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14304
14305         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14306         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14307
14308         /* HP Chromebook 14 (Celeron 2955U) */
14309         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14310
14311         /* Dell Chromebook 11 */
14312         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14313
14314         /* Dell Chromebook 11 (2015 version) */
14315         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14316
14317         /* Toshiba Satellite P50-C-18C */
14318         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14319 };
14320
14321 static void intel_init_quirks(struct drm_device *dev)
14322 {
14323         struct pci_dev *d = dev->pdev;
14324         int i;
14325
14326         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14327                 struct intel_quirk *q = &intel_quirks[i];
14328
14329                 if (d->device == q->device &&
14330                     (d->subsystem_vendor == q->subsystem_vendor ||
14331                      q->subsystem_vendor == PCI_ANY_ID) &&
14332                     (d->subsystem_device == q->subsystem_device ||
14333                      q->subsystem_device == PCI_ANY_ID))
14334                         q->hook(dev);
14335         }
14336         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14337                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14338                         intel_dmi_quirks[i].hook(dev);
14339         }
14340 }
14341
14342 /* Disable the VGA plane that we never use */
14343 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14344 {
14345         struct pci_dev *pdev = dev_priv->drm.pdev;
14346         u8 sr1;
14347         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14348
14349         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14350         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14351         outb(SR01, VGA_SR_INDEX);
14352         sr1 = inb(VGA_SR_DATA);
14353         outb(sr1 | 1<<5, VGA_SR_DATA);
14354         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14355         udelay(300);
14356
14357         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14358         POSTING_READ(vga_reg);
14359 }
14360
14361 void intel_modeset_init_hw(struct drm_device *dev)
14362 {
14363         struct drm_i915_private *dev_priv = to_i915(dev);
14364
14365         intel_update_cdclk(dev_priv);
14366         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14367         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14368 }
14369
14370 /*
14371  * Calculate what we think the watermarks should be for the state we've read
14372  * out of the hardware and then immediately program those watermarks so that
14373  * we ensure the hardware settings match our internal state.
14374  *
14375  * We can calculate what we think WM's should be by creating a duplicate of the
14376  * current state (which was constructed during hardware readout) and running it
14377  * through the atomic check code to calculate new watermark values in the
14378  * state object.
14379  */
14380 static void sanitize_watermarks(struct drm_device *dev)
14381 {
14382         struct drm_i915_private *dev_priv = to_i915(dev);
14383         struct drm_atomic_state *state;
14384         struct intel_atomic_state *intel_state;
14385         struct drm_crtc *crtc;
14386         struct drm_crtc_state *cstate;
14387         struct drm_modeset_acquire_ctx ctx;
14388         int ret;
14389         int i;
14390
14391         /* Only supported on platforms that use atomic watermark design */
14392         if (!dev_priv->display.optimize_watermarks)
14393                 return;
14394
14395         /*
14396          * We need to hold connection_mutex before calling duplicate_state so
14397          * that the connector loop is protected.
14398          */
14399         drm_modeset_acquire_init(&ctx, 0);
14400 retry:
14401         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14402         if (ret == -EDEADLK) {
14403                 drm_modeset_backoff(&ctx);
14404                 goto retry;
14405         } else if (WARN_ON(ret)) {
14406                 goto fail;
14407         }
14408
14409         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14410         if (WARN_ON(IS_ERR(state)))
14411                 goto fail;
14412
14413         intel_state = to_intel_atomic_state(state);
14414
14415         /*
14416          * Hardware readout is the only time we don't want to calculate
14417          * intermediate watermarks (since we don't trust the current
14418          * watermarks).
14419          */
14420         if (!HAS_GMCH_DISPLAY(dev_priv))
14421                 intel_state->skip_intermediate_wm = true;
14422
14423         ret = intel_atomic_check(dev, state);
14424         if (ret) {
14425                 /*
14426                  * If we fail here, it means that the hardware appears to be
14427                  * programmed in a way that shouldn't be possible, given our
14428                  * understanding of watermark requirements.  This might mean a
14429                  * mistake in the hardware readout code or a mistake in the
14430                  * watermark calculations for a given platform.  Raise a WARN
14431                  * so that this is noticeable.
14432                  *
14433                  * If this actually happens, we'll have to just leave the
14434                  * BIOS-programmed watermarks untouched and hope for the best.
14435                  */
14436                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14437                 goto put_state;
14438         }
14439
14440         /* Write calculated watermark values back */
14441         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14442                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14443
14444                 cs->wm.need_postvbl_update = true;
14445                 dev_priv->display.optimize_watermarks(intel_state, cs);
14446         }
14447
14448 put_state:
14449         drm_atomic_state_put(state);
14450 fail:
14451         drm_modeset_drop_locks(&ctx);
14452         drm_modeset_acquire_fini(&ctx);
14453 }
14454
14455 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14456 {
14457         if (IS_GEN5(dev_priv)) {
14458                 u32 fdi_pll_clk =
14459                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14460
14461                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14462         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14463                 dev_priv->fdi_pll_freq = 270000;
14464         } else {
14465                 return;
14466         }
14467
14468         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14469 }
14470
14471 int intel_modeset_init(struct drm_device *dev)
14472 {
14473         struct drm_i915_private *dev_priv = to_i915(dev);
14474         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14475         enum pipe pipe;
14476         struct intel_crtc *crtc;
14477
14478         drm_mode_config_init(dev);
14479
14480         dev->mode_config.min_width = 0;
14481         dev->mode_config.min_height = 0;
14482
14483         dev->mode_config.preferred_depth = 24;
14484         dev->mode_config.prefer_shadow = 1;
14485
14486         dev->mode_config.allow_fb_modifiers = true;
14487
14488         dev->mode_config.funcs = &intel_mode_funcs;
14489
14490         init_llist_head(&dev_priv->atomic_helper.free_list);
14491         INIT_WORK(&dev_priv->atomic_helper.free_work,
14492                   intel_atomic_helper_free_state_worker);
14493
14494         intel_init_quirks(dev);
14495
14496         intel_init_pm(dev_priv);
14497
14498         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14499                 return 0;
14500
14501         /*
14502          * There may be no VBT; and if the BIOS enabled SSC we can
14503          * just keep using it to avoid unnecessary flicker.  Whereas if the
14504          * BIOS isn't using it, don't assume it will work even if the VBT
14505          * indicates as much.
14506          */
14507         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14508                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14509                                             DREF_SSC1_ENABLE);
14510
14511                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14512                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14513                                      bios_lvds_use_ssc ? "en" : "dis",
14514                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14515                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14516                 }
14517         }
14518
14519         if (IS_GEN2(dev_priv)) {
14520                 dev->mode_config.max_width = 2048;
14521                 dev->mode_config.max_height = 2048;
14522         } else if (IS_GEN3(dev_priv)) {
14523                 dev->mode_config.max_width = 4096;
14524                 dev->mode_config.max_height = 4096;
14525         } else {
14526                 dev->mode_config.max_width = 8192;
14527                 dev->mode_config.max_height = 8192;
14528         }
14529
14530         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14531                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14532                 dev->mode_config.cursor_height = 1023;
14533         } else if (IS_GEN2(dev_priv)) {
14534                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14535                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14536         } else {
14537                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14538                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14539         }
14540
14541         dev->mode_config.fb_base = ggtt->mappable_base;
14542
14543         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14544                       INTEL_INFO(dev_priv)->num_pipes,
14545                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14546
14547         for_each_pipe(dev_priv, pipe) {
14548                 int ret;
14549
14550                 ret = intel_crtc_init(dev_priv, pipe);
14551                 if (ret) {
14552                         drm_mode_config_cleanup(dev);
14553                         return ret;
14554                 }
14555         }
14556
14557         intel_shared_dpll_init(dev);
14558         intel_update_fdi_pll_freq(dev_priv);
14559
14560         intel_update_czclk(dev_priv);
14561         intel_modeset_init_hw(dev);
14562
14563         if (dev_priv->max_cdclk_freq == 0)
14564                 intel_update_max_cdclk(dev_priv);
14565
14566         /* Just disable it once at startup */
14567         i915_disable_vga(dev_priv);
14568         intel_setup_outputs(dev_priv);
14569
14570         drm_modeset_lock_all(dev);
14571         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14572         drm_modeset_unlock_all(dev);
14573
14574         for_each_intel_crtc(dev, crtc) {
14575                 struct intel_initial_plane_config plane_config = {};
14576
14577                 if (!crtc->active)
14578                         continue;
14579
14580                 /*
14581                  * Note that reserving the BIOS fb up front prevents us
14582                  * from stuffing other stolen allocations like the ring
14583                  * on top.  This prevents some ugliness at boot time, and
14584                  * can even allow for smooth boot transitions if the BIOS
14585                  * fb is large enough for the active pipe configuration.
14586                  */
14587                 dev_priv->display.get_initial_plane_config(crtc,
14588                                                            &plane_config);
14589
14590                 /*
14591                  * If the fb is shared between multiple heads, we'll
14592                  * just get the first one.
14593                  */
14594                 intel_find_initial_plane_obj(crtc, &plane_config);
14595         }
14596
14597         /*
14598          * Make sure hardware watermarks really match the state we read out.
14599          * Note that we need to do this after reconstructing the BIOS fb's
14600          * since the watermark calculation done here will use pstate->fb.
14601          */
14602         if (!HAS_GMCH_DISPLAY(dev_priv))
14603                 sanitize_watermarks(dev);
14604
14605         return 0;
14606 }
14607
14608 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14609 {
14610         /* 640x480@60Hz, ~25175 kHz */
14611         struct dpll clock = {
14612                 .m1 = 18,
14613                 .m2 = 7,
14614                 .p1 = 13,
14615                 .p2 = 4,
14616                 .n = 2,
14617         };
14618         u32 dpll, fp;
14619         int i;
14620
14621         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14622
14623         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14624                       pipe_name(pipe), clock.vco, clock.dot);
14625
14626         fp = i9xx_dpll_compute_fp(&clock);
14627         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14628                 DPLL_VGA_MODE_DIS |
14629                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14630                 PLL_P2_DIVIDE_BY_4 |
14631                 PLL_REF_INPUT_DREFCLK |
14632                 DPLL_VCO_ENABLE;
14633
14634         I915_WRITE(FP0(pipe), fp);
14635         I915_WRITE(FP1(pipe), fp);
14636
14637         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14638         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14639         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14640         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14641         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14642         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14643         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14644
14645         /*
14646          * Apparently we need to have VGA mode enabled prior to changing
14647          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14648          * dividers, even though the register value does change.
14649          */
14650         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14651         I915_WRITE(DPLL(pipe), dpll);
14652
14653         /* Wait for the clocks to stabilize. */
14654         POSTING_READ(DPLL(pipe));
14655         udelay(150);
14656
14657         /* The pixel multiplier can only be updated once the
14658          * DPLL is enabled and the clocks are stable.
14659          *
14660          * So write it again.
14661          */
14662         I915_WRITE(DPLL(pipe), dpll);
14663
14664         /* We do this three times for luck */
14665         for (i = 0; i < 3 ; i++) {
14666                 I915_WRITE(DPLL(pipe), dpll);
14667                 POSTING_READ(DPLL(pipe));
14668                 udelay(150); /* wait for warmup */
14669         }
14670
14671         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14672         POSTING_READ(PIPECONF(pipe));
14673 }
14674
14675 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14676 {
14677         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14678                       pipe_name(pipe));
14679
14680         assert_plane_disabled(dev_priv, PLANE_A);
14681         assert_plane_disabled(dev_priv, PLANE_B);
14682
14683         I915_WRITE(PIPECONF(pipe), 0);
14684         POSTING_READ(PIPECONF(pipe));
14685
14686         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14687                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14688
14689         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14690         POSTING_READ(DPLL(pipe));
14691 }
14692
14693 static bool
14694 intel_check_plane_mapping(struct intel_crtc *crtc)
14695 {
14696         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14697         u32 val;
14698
14699         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14700                 return true;
14701
14702         val = I915_READ(DSPCNTR(!crtc->plane));
14703
14704         if ((val & DISPLAY_PLANE_ENABLE) &&
14705             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14706                 return false;
14707
14708         return true;
14709 }
14710
14711 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14712 {
14713         struct drm_device *dev = crtc->base.dev;
14714         struct intel_encoder *encoder;
14715
14716         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14717                 return true;
14718
14719         return false;
14720 }
14721
14722 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14723 {
14724         struct drm_device *dev = encoder->base.dev;
14725         struct intel_connector *connector;
14726
14727         for_each_connector_on_encoder(dev, &encoder->base, connector)
14728                 return connector;
14729
14730         return NULL;
14731 }
14732
14733 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14734                               enum pipe pch_transcoder)
14735 {
14736         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14737                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14738 }
14739
14740 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14741                                 struct drm_modeset_acquire_ctx *ctx)
14742 {
14743         struct drm_device *dev = crtc->base.dev;
14744         struct drm_i915_private *dev_priv = to_i915(dev);
14745         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14746
14747         /* Clear any frame start delays used for debugging left by the BIOS */
14748         if (!transcoder_is_dsi(cpu_transcoder)) {
14749                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14750
14751                 I915_WRITE(reg,
14752                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14753         }
14754
14755         /* restore vblank interrupts to correct state */
14756         drm_crtc_vblank_reset(&crtc->base);
14757         if (crtc->active) {
14758                 struct intel_plane *plane;
14759
14760                 drm_crtc_vblank_on(&crtc->base);
14761
14762                 /* Disable everything but the primary plane */
14763                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14764                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14765                                 continue;
14766
14767                         trace_intel_disable_plane(&plane->base, crtc);
14768                         plane->disable_plane(plane, crtc);
14769                 }
14770         }
14771
14772         /* We need to sanitize the plane -> pipe mapping first because this will
14773          * disable the crtc (and hence change the state) if it is wrong. Note
14774          * that gen4+ has a fixed plane -> pipe mapping.  */
14775         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14776                 bool plane;
14777
14778                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14779                               crtc->base.base.id, crtc->base.name);
14780
14781                 /* Pipe has the wrong plane attached and the plane is active.
14782                  * Temporarily change the plane mapping and disable everything
14783                  * ...  */
14784                 plane = crtc->plane;
14785                 crtc->base.primary->state->visible = true;
14786                 crtc->plane = !plane;
14787                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14788                 crtc->plane = plane;
14789         }
14790
14791         /* Adjust the state of the output pipe according to whether we
14792          * have active connectors/encoders. */
14793         if (crtc->active && !intel_crtc_has_encoders(crtc))
14794                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14795
14796         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14797                 /*
14798                  * We start out with underrun reporting disabled to avoid races.
14799                  * For correct bookkeeping mark this on active crtcs.
14800                  *
14801                  * Also on gmch platforms we dont have any hardware bits to
14802                  * disable the underrun reporting. Which means we need to start
14803                  * out with underrun reporting disabled also on inactive pipes,
14804                  * since otherwise we'll complain about the garbage we read when
14805                  * e.g. coming up after runtime pm.
14806                  *
14807                  * No protection against concurrent access is required - at
14808                  * worst a fifo underrun happens which also sets this to false.
14809                  */
14810                 crtc->cpu_fifo_underrun_disabled = true;
14811                 /*
14812                  * We track the PCH trancoder underrun reporting state
14813                  * within the crtc. With crtc for pipe A housing the underrun
14814                  * reporting state for PCH transcoder A, crtc for pipe B housing
14815                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14816                  * and marking underrun reporting as disabled for the non-existing
14817                  * PCH transcoders B and C would prevent enabling the south
14818                  * error interrupt (see cpt_can_enable_serr_int()).
14819                  */
14820                 if (has_pch_trancoder(dev_priv, crtc->pipe))
14821                         crtc->pch_fifo_underrun_disabled = true;
14822         }
14823 }
14824
14825 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14826 {
14827         struct intel_connector *connector;
14828
14829         /* We need to check both for a crtc link (meaning that the
14830          * encoder is active and trying to read from a pipe) and the
14831          * pipe itself being active. */
14832         bool has_active_crtc = encoder->base.crtc &&
14833                 to_intel_crtc(encoder->base.crtc)->active;
14834
14835         connector = intel_encoder_find_connector(encoder);
14836         if (connector && !has_active_crtc) {
14837                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14838                               encoder->base.base.id,
14839                               encoder->base.name);
14840
14841                 /* Connector is active, but has no active pipe. This is
14842                  * fallout from our resume register restoring. Disable
14843                  * the encoder manually again. */
14844                 if (encoder->base.crtc) {
14845                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14846
14847                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14848                                       encoder->base.base.id,
14849                                       encoder->base.name);
14850                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14851                         if (encoder->post_disable)
14852                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14853                 }
14854                 encoder->base.crtc = NULL;
14855
14856                 /* Inconsistent output/port/pipe state happens presumably due to
14857                  * a bug in one of the get_hw_state functions. Or someplace else
14858                  * in our code, like the register restore mess on resume. Clamp
14859                  * things to off as a safer default. */
14860
14861                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14862                 connector->base.encoder = NULL;
14863         }
14864         /* Enabled encoders without active connectors will be fixed in
14865          * the crtc fixup. */
14866 }
14867
14868 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14869 {
14870         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14871
14872         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14873                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14874                 i915_disable_vga(dev_priv);
14875         }
14876 }
14877
14878 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14879 {
14880         /* This function can be called both from intel_modeset_setup_hw_state or
14881          * at a very early point in our resume sequence, where the power well
14882          * structures are not yet restored. Since this function is at a very
14883          * paranoid "someone might have enabled VGA while we were not looking"
14884          * level, just check if the power well is enabled instead of trying to
14885          * follow the "don't touch the power well if we don't need it" policy
14886          * the rest of the driver uses. */
14887         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14888                 return;
14889
14890         i915_redisable_vga_power_on(dev_priv);
14891
14892         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14893 }
14894
14895 static bool primary_get_hw_state(struct intel_plane *plane)
14896 {
14897         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14898
14899         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14900 }
14901
14902 /* FIXME read out full plane state for all planes */
14903 static void readout_plane_state(struct intel_crtc *crtc)
14904 {
14905         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14906         bool visible;
14907
14908         visible = crtc->active && primary_get_hw_state(primary);
14909
14910         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14911                                 to_intel_plane_state(primary->base.state),
14912                                 visible);
14913 }
14914
14915 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14916 {
14917         struct drm_i915_private *dev_priv = to_i915(dev);
14918         enum pipe pipe;
14919         struct intel_crtc *crtc;
14920         struct intel_encoder *encoder;
14921         struct intel_connector *connector;
14922         struct drm_connector_list_iter conn_iter;
14923         int i;
14924
14925         dev_priv->active_crtcs = 0;
14926
14927         for_each_intel_crtc(dev, crtc) {
14928                 struct intel_crtc_state *crtc_state =
14929                         to_intel_crtc_state(crtc->base.state);
14930
14931                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14932                 memset(crtc_state, 0, sizeof(*crtc_state));
14933                 crtc_state->base.crtc = &crtc->base;
14934
14935                 crtc_state->base.active = crtc_state->base.enable =
14936                         dev_priv->display.get_pipe_config(crtc, crtc_state);
14937
14938                 crtc->base.enabled = crtc_state->base.enable;
14939                 crtc->active = crtc_state->base.active;
14940
14941                 if (crtc_state->base.active)
14942                         dev_priv->active_crtcs |= 1 << crtc->pipe;
14943
14944                 readout_plane_state(crtc);
14945
14946                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14947                               crtc->base.base.id, crtc->base.name,
14948                               enableddisabled(crtc_state->base.active));
14949         }
14950
14951         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14952                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14953
14954                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14955                                                   &pll->state.hw_state);
14956                 pll->state.crtc_mask = 0;
14957                 for_each_intel_crtc(dev, crtc) {
14958                         struct intel_crtc_state *crtc_state =
14959                                 to_intel_crtc_state(crtc->base.state);
14960
14961                         if (crtc_state->base.active &&
14962                             crtc_state->shared_dpll == pll)
14963                                 pll->state.crtc_mask |= 1 << crtc->pipe;
14964                 }
14965                 pll->active_mask = pll->state.crtc_mask;
14966
14967                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14968                               pll->name, pll->state.crtc_mask, pll->on);
14969         }
14970
14971         for_each_intel_encoder(dev, encoder) {
14972                 pipe = 0;
14973
14974                 if (encoder->get_hw_state(encoder, &pipe)) {
14975                         struct intel_crtc_state *crtc_state;
14976
14977                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14978                         crtc_state = to_intel_crtc_state(crtc->base.state);
14979
14980                         encoder->base.crtc = &crtc->base;
14981                         encoder->get_config(encoder, crtc_state);
14982                 } else {
14983                         encoder->base.crtc = NULL;
14984                 }
14985
14986                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14987                               encoder->base.base.id, encoder->base.name,
14988                               enableddisabled(encoder->base.crtc),
14989                               pipe_name(pipe));
14990         }
14991
14992         drm_connector_list_iter_begin(dev, &conn_iter);
14993         for_each_intel_connector_iter(connector, &conn_iter) {
14994                 if (connector->get_hw_state(connector)) {
14995                         connector->base.dpms = DRM_MODE_DPMS_ON;
14996
14997                         encoder = connector->encoder;
14998                         connector->base.encoder = &encoder->base;
14999
15000                         if (encoder->base.crtc &&
15001                             encoder->base.crtc->state->active) {
15002                                 /*
15003                                  * This has to be done during hardware readout
15004                                  * because anything calling .crtc_disable may
15005                                  * rely on the connector_mask being accurate.
15006                                  */
15007                                 encoder->base.crtc->state->connector_mask |=
15008                                         1 << drm_connector_index(&connector->base);
15009                                 encoder->base.crtc->state->encoder_mask |=
15010                                         1 << drm_encoder_index(&encoder->base);
15011                         }
15012
15013                 } else {
15014                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15015                         connector->base.encoder = NULL;
15016                 }
15017                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15018                               connector->base.base.id, connector->base.name,
15019                               enableddisabled(connector->base.encoder));
15020         }
15021         drm_connector_list_iter_end(&conn_iter);
15022
15023         for_each_intel_crtc(dev, crtc) {
15024                 struct intel_crtc_state *crtc_state =
15025                         to_intel_crtc_state(crtc->base.state);
15026                 int min_cdclk = 0;
15027
15028                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15029                 if (crtc_state->base.active) {
15030                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15031                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15032                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15033
15034                         /*
15035                          * The initial mode needs to be set in order to keep
15036                          * the atomic core happy. It wants a valid mode if the
15037                          * crtc's enabled, so we do the above call.
15038                          *
15039                          * But we don't set all the derived state fully, hence
15040                          * set a flag to indicate that a full recalculation is
15041                          * needed on the next commit.
15042                          */
15043                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15044
15045                         intel_crtc_compute_pixel_rate(crtc_state);
15046
15047                         if (dev_priv->display.modeset_calc_cdclk) {
15048                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15049                                 if (WARN_ON(min_cdclk < 0))
15050                                         min_cdclk = 0;
15051                         }
15052
15053                         drm_calc_timestamping_constants(&crtc->base,
15054                                                         &crtc_state->base.adjusted_mode);
15055                         update_scanline_offset(crtc);
15056                 }
15057
15058                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15059                 dev_priv->min_voltage_level[crtc->pipe] =
15060                         crtc_state->min_voltage_level;
15061
15062                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15063         }
15064 }
15065
15066 static void
15067 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15068 {
15069         struct intel_encoder *encoder;
15070
15071         for_each_intel_encoder(&dev_priv->drm, encoder) {
15072                 u64 get_domains;
15073                 enum intel_display_power_domain domain;
15074
15075                 if (!encoder->get_power_domains)
15076                         continue;
15077
15078                 get_domains = encoder->get_power_domains(encoder);
15079                 for_each_power_domain(domain, get_domains)
15080                         intel_display_power_get(dev_priv, domain);
15081         }
15082 }
15083
15084 /* Scan out the current hw modeset state,
15085  * and sanitizes it to the current state
15086  */
15087 static void
15088 intel_modeset_setup_hw_state(struct drm_device *dev,
15089                              struct drm_modeset_acquire_ctx *ctx)
15090 {
15091         struct drm_i915_private *dev_priv = to_i915(dev);
15092         enum pipe pipe;
15093         struct intel_crtc *crtc;
15094         struct intel_encoder *encoder;
15095         int i;
15096
15097         if (IS_HASWELL(dev_priv)) {
15098                 /*
15099                  * WaRsPkgCStateDisplayPMReq:hsw
15100                  * System hang if this isn't done before disabling all planes!
15101                  */
15102                 I915_WRITE(CHICKEN_PAR1_1,
15103                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15104         }
15105
15106         intel_modeset_readout_hw_state(dev);
15107
15108         /* HW state is read out, now we need to sanitize this mess. */
15109         get_encoder_power_domains(dev_priv);
15110
15111         for_each_intel_encoder(dev, encoder) {
15112                 intel_sanitize_encoder(encoder);
15113         }
15114
15115         for_each_pipe(dev_priv, pipe) {
15116                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15117
15118                 intel_sanitize_crtc(crtc, ctx);
15119                 intel_dump_pipe_config(crtc, crtc->config,
15120                                        "[setup_hw_state]");
15121         }
15122
15123         intel_modeset_update_connector_atomic_state(dev);
15124
15125         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15126                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15127
15128                 if (!pll->on || pll->active_mask)
15129                         continue;
15130
15131                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15132
15133                 pll->funcs.disable(dev_priv, pll);
15134                 pll->on = false;
15135         }
15136
15137         if (IS_G4X(dev_priv)) {
15138                 g4x_wm_get_hw_state(dev);
15139                 g4x_wm_sanitize(dev_priv);
15140         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15141                 vlv_wm_get_hw_state(dev);
15142                 vlv_wm_sanitize(dev_priv);
15143         } else if (INTEL_GEN(dev_priv) >= 9) {
15144                 skl_wm_get_hw_state(dev);
15145         } else if (HAS_PCH_SPLIT(dev_priv)) {
15146                 ilk_wm_get_hw_state(dev);
15147         }
15148
15149         for_each_intel_crtc(dev, crtc) {
15150                 u64 put_domains;
15151
15152                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15153                 if (WARN_ON(put_domains))
15154                         modeset_put_power_domains(dev_priv, put_domains);
15155         }
15156         intel_display_set_init_power(dev_priv, false);
15157
15158         intel_power_domains_verify_state(dev_priv);
15159
15160         intel_fbc_init_pipe_state(dev_priv);
15161 }
15162
15163 void intel_display_resume(struct drm_device *dev)
15164 {
15165         struct drm_i915_private *dev_priv = to_i915(dev);
15166         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15167         struct drm_modeset_acquire_ctx ctx;
15168         int ret;
15169
15170         dev_priv->modeset_restore_state = NULL;
15171         if (state)
15172                 state->acquire_ctx = &ctx;
15173
15174         drm_modeset_acquire_init(&ctx, 0);
15175
15176         while (1) {
15177                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15178                 if (ret != -EDEADLK)
15179                         break;
15180
15181                 drm_modeset_backoff(&ctx);
15182         }
15183
15184         if (!ret)
15185                 ret = __intel_display_resume(dev, state, &ctx);
15186
15187         intel_enable_ipc(dev_priv);
15188         drm_modeset_drop_locks(&ctx);
15189         drm_modeset_acquire_fini(&ctx);
15190
15191         if (ret)
15192                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15193         if (state)
15194                 drm_atomic_state_put(state);
15195 }
15196
15197 int intel_connector_register(struct drm_connector *connector)
15198 {
15199         struct intel_connector *intel_connector = to_intel_connector(connector);
15200         int ret;
15201
15202         ret = intel_backlight_device_register(intel_connector);
15203         if (ret)
15204                 goto err;
15205
15206         return 0;
15207
15208 err:
15209         return ret;
15210 }
15211
15212 void intel_connector_unregister(struct drm_connector *connector)
15213 {
15214         struct intel_connector *intel_connector = to_intel_connector(connector);
15215
15216         intel_backlight_device_unregister(intel_connector);
15217         intel_panel_destroy_backlight(connector);
15218 }
15219
15220 static void intel_hpd_poll_fini(struct drm_device *dev)
15221 {
15222         struct intel_connector *connector;
15223         struct drm_connector_list_iter conn_iter;
15224
15225         /* First disable polling... */
15226         drm_kms_helper_poll_fini(dev);
15227
15228         /* Then kill the work that may have been queued by hpd. */
15229         drm_connector_list_iter_begin(dev, &conn_iter);
15230         for_each_intel_connector_iter(connector, &conn_iter) {
15231                 if (connector->modeset_retry_work.func)
15232                         cancel_work_sync(&connector->modeset_retry_work);
15233         }
15234         drm_connector_list_iter_end(&conn_iter);
15235 }
15236
15237 void intel_modeset_cleanup(struct drm_device *dev)
15238 {
15239         struct drm_i915_private *dev_priv = to_i915(dev);
15240
15241         flush_work(&dev_priv->atomic_helper.free_work);
15242         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15243
15244         intel_disable_gt_powersave(dev_priv);
15245
15246         /*
15247          * Interrupts and polling as the first thing to avoid creating havoc.
15248          * Too much stuff here (turning of connectors, ...) would
15249          * experience fancy races otherwise.
15250          */
15251         intel_irq_uninstall(dev_priv);
15252
15253         /*
15254          * Due to the hpd irq storm handling the hotplug work can re-arm the
15255          * poll handlers. Hence disable polling after hpd handling is shut down.
15256          */
15257         intel_hpd_poll_fini(dev);
15258
15259         /* poll work can call into fbdev, hence clean that up afterwards */
15260         intel_fbdev_fini(dev_priv);
15261
15262         intel_unregister_dsm_handler();
15263
15264         intel_fbc_global_disable(dev_priv);
15265
15266         /* flush any delayed tasks or pending work */
15267         flush_scheduled_work();
15268
15269         drm_mode_config_cleanup(dev);
15270
15271         intel_cleanup_overlay(dev_priv);
15272
15273         intel_cleanup_gt_powersave(dev_priv);
15274
15275         intel_teardown_gmbus(dev_priv);
15276 }
15277
15278 void intel_connector_attach_encoder(struct intel_connector *connector,
15279                                     struct intel_encoder *encoder)
15280 {
15281         connector->encoder = encoder;
15282         drm_mode_connector_attach_encoder(&connector->base,
15283                                           &encoder->base);
15284 }
15285
15286 /*
15287  * set vga decode state - true == enable VGA decode
15288  */
15289 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15290 {
15291         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15292         u16 gmch_ctrl;
15293
15294         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15295                 DRM_ERROR("failed to read control word\n");
15296                 return -EIO;
15297         }
15298
15299         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15300                 return 0;
15301
15302         if (state)
15303                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15304         else
15305                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15306
15307         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15308                 DRM_ERROR("failed to write control word\n");
15309                 return -EIO;
15310         }
15311
15312         return 0;
15313 }
15314
15315 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15316
15317 struct intel_display_error_state {
15318
15319         u32 power_well_driver;
15320
15321         int num_transcoders;
15322
15323         struct intel_cursor_error_state {
15324                 u32 control;
15325                 u32 position;
15326                 u32 base;
15327                 u32 size;
15328         } cursor[I915_MAX_PIPES];
15329
15330         struct intel_pipe_error_state {
15331                 bool power_domain_on;
15332                 u32 source;
15333                 u32 stat;
15334         } pipe[I915_MAX_PIPES];
15335
15336         struct intel_plane_error_state {
15337                 u32 control;
15338                 u32 stride;
15339                 u32 size;
15340                 u32 pos;
15341                 u32 addr;
15342                 u32 surface;
15343                 u32 tile_offset;
15344         } plane[I915_MAX_PIPES];
15345
15346         struct intel_transcoder_error_state {
15347                 bool power_domain_on;
15348                 enum transcoder cpu_transcoder;
15349
15350                 u32 conf;
15351
15352                 u32 htotal;
15353                 u32 hblank;
15354                 u32 hsync;
15355                 u32 vtotal;
15356                 u32 vblank;
15357                 u32 vsync;
15358         } transcoder[4];
15359 };
15360
15361 struct intel_display_error_state *
15362 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15363 {
15364         struct intel_display_error_state *error;
15365         int transcoders[] = {
15366                 TRANSCODER_A,
15367                 TRANSCODER_B,
15368                 TRANSCODER_C,
15369                 TRANSCODER_EDP,
15370         };
15371         int i;
15372
15373         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15374                 return NULL;
15375
15376         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15377         if (error == NULL)
15378                 return NULL;
15379
15380         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15381                 error->power_well_driver =
15382                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15383
15384         for_each_pipe(dev_priv, i) {
15385                 error->pipe[i].power_domain_on =
15386                         __intel_display_power_is_enabled(dev_priv,
15387                                                          POWER_DOMAIN_PIPE(i));
15388                 if (!error->pipe[i].power_domain_on)
15389                         continue;
15390
15391                 error->cursor[i].control = I915_READ(CURCNTR(i));
15392                 error->cursor[i].position = I915_READ(CURPOS(i));
15393                 error->cursor[i].base = I915_READ(CURBASE(i));
15394
15395                 error->plane[i].control = I915_READ(DSPCNTR(i));
15396                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15397                 if (INTEL_GEN(dev_priv) <= 3) {
15398                         error->plane[i].size = I915_READ(DSPSIZE(i));
15399                         error->plane[i].pos = I915_READ(DSPPOS(i));
15400                 }
15401                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15402                         error->plane[i].addr = I915_READ(DSPADDR(i));
15403                 if (INTEL_GEN(dev_priv) >= 4) {
15404                         error->plane[i].surface = I915_READ(DSPSURF(i));
15405                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15406                 }
15407
15408                 error->pipe[i].source = I915_READ(PIPESRC(i));
15409
15410                 if (HAS_GMCH_DISPLAY(dev_priv))
15411                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15412         }
15413
15414         /* Note: this does not include DSI transcoders. */
15415         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15416         if (HAS_DDI(dev_priv))
15417                 error->num_transcoders++; /* Account for eDP. */
15418
15419         for (i = 0; i < error->num_transcoders; i++) {
15420                 enum transcoder cpu_transcoder = transcoders[i];
15421
15422                 error->transcoder[i].power_domain_on =
15423                         __intel_display_power_is_enabled(dev_priv,
15424                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15425                 if (!error->transcoder[i].power_domain_on)
15426                         continue;
15427
15428                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15429
15430                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15431                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15432                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15433                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15434                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15435                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15436                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15437         }
15438
15439         return error;
15440 }
15441
15442 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15443
15444 void
15445 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15446                                 struct intel_display_error_state *error)
15447 {
15448         struct drm_i915_private *dev_priv = m->i915;
15449         int i;
15450
15451         if (!error)
15452                 return;
15453
15454         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15455         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15456                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15457                            error->power_well_driver);
15458         for_each_pipe(dev_priv, i) {
15459                 err_printf(m, "Pipe [%d]:\n", i);
15460                 err_printf(m, "  Power: %s\n",
15461                            onoff(error->pipe[i].power_domain_on));
15462                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15463                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15464
15465                 err_printf(m, "Plane [%d]:\n", i);
15466                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15467                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15468                 if (INTEL_GEN(dev_priv) <= 3) {
15469                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15470                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15471                 }
15472                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15473                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15474                 if (INTEL_GEN(dev_priv) >= 4) {
15475                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15476                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15477                 }
15478
15479                 err_printf(m, "Cursor [%d]:\n", i);
15480                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15481                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15482                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15483         }
15484
15485         for (i = 0; i < error->num_transcoders; i++) {
15486                 err_printf(m, "CPU transcoder: %s\n",
15487                            transcoder_name(error->transcoder[i].cpu_transcoder));
15488                 err_printf(m, "  Power: %s\n",
15489                            onoff(error->transcoder[i].power_domain_on));
15490                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15491                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15492                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15493                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15494                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15495                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15496                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15497         }
15498 }
15499
15500 #endif