drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else
 223                 return dev_priv->fdi_pll_freq;
 224 }
 225
 226 static const struct intel_limit intel_limits_i8xx_dac = {
 227         .dot = { .min = 25000, .max = 350000 },
 228         .vco = { .min = 908000, .max = 1512000 },
 229         .n = { .min = 2, .max = 16 },
 230         .m = { .min = 96, .max = 140 },
 231         .m1 = { .min = 18, .max = 26 },
 232         .m2 = { .min = 6, .max = 16 },
 233         .p = { .min = 4, .max = 128 },
 234         .p1 = { .min = 2, .max = 33 },
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 4, .p2_fast = 2 },
 237 };
 238
 239 static const struct intel_limit intel_limits_i8xx_dvo = {
 240         .dot = { .min = 25000, .max = 350000 },
 241         .vco = { .min = 908000, .max = 1512000 },
 242         .n = { .min = 2, .max = 16 },
 243         .m = { .min = 96, .max = 140 },
 244         .m1 = { .min = 18, .max = 26 },
 245         .m2 = { .min = 6, .max = 16 },
 246         .p = { .min = 4, .max = 128 },
 247         .p1 = { .min = 2, .max = 33 },
 248         .p2 = { .dot_limit = 165000,
 249                 .p2_slow = 4, .p2_fast = 4 },
 250 };
 251
 252 static const struct intel_limit intel_limits_i8xx_lvds = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 1, .max = 6 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 14, .p2_fast = 7 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i9xx_sdvo = {
 266         .dot = { .min = 20000, .max = 400000 },
 267         .vco = { .min = 1400000, .max = 2800000 },
 268         .n = { .min = 1, .max = 6 },
 269         .m = { .min = 70, .max = 120 },
 270         .m1 = { .min = 8, .max = 18 },
 271         .m2 = { .min = 3, .max = 7 },
 272         .p = { .min = 5, .max = 80 },
 273         .p1 = { .min = 1, .max = 8 },
 274         .p2 = { .dot_limit = 200000,
 275                 .p2_slow = 10, .p2_fast = 5 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i9xx_lvds = {
 279         .dot = { .min = 20000, .max = 400000 },
 280         .vco = { .min = 1400000, .max = 2800000 },
 281         .n = { .min = 1, .max = 6 },
 282         .m = { .min = 70, .max = 120 },
 283         .m1 = { .min = 8, .max = 18 },
 284         .m2 = { .min = 3, .max = 7 },
 285         .p = { .min = 7, .max = 98 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 112000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291
 292 static const struct intel_limit intel_limits_g4x_sdvo = {
 293         .dot = { .min = 25000, .max = 270000 },
 294         .vco = { .min = 1750000, .max = 3500000},
 295         .n = { .min = 1, .max = 4 },
 296         .m = { .min = 104, .max = 138 },
 297         .m1 = { .min = 17, .max = 23 },
 298         .m2 = { .min = 5, .max = 11 },
 299         .p = { .min = 10, .max = 30 },
 300         .p1 = { .min = 1, .max = 3},
 301         .p2 = { .dot_limit = 270000,
 302                 .p2_slow = 10,
 303                 .p2_fast = 10
 304         },
 305 };
 306
 307 static const struct intel_limit intel_limits_g4x_hdmi = {
 308         .dot = { .min = 22000, .max = 400000 },
 309         .vco = { .min = 1750000, .max = 3500000},
 310         .n = { .min = 1, .max = 4 },
 311         .m = { .min = 104, .max = 138 },
 312         .m1 = { .min = 16, .max = 23 },
 313         .m2 = { .min = 5, .max = 11 },
 314         .p = { .min = 5, .max = 80 },
 315         .p1 = { .min = 1, .max = 8},
 316         .p2 = { .dot_limit = 165000,
 317                 .p2_slow = 10, .p2_fast = 5 },
 318 };
 319
 320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 321         .dot = { .min = 20000, .max = 115000 },
 322         .vco = { .min = 1750000, .max = 3500000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 0,
 330                 .p2_slow = 14, .p2_fast = 14
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 335         .dot = { .min = 80000, .max = 224000 },
 336         .vco = { .min = 1750000, .max = 3500000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 17, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 0,
 344                 .p2_slow = 7, .p2_fast = 7
 345         },
 346 };
 347
 348 static const struct intel_limit intel_limits_pineview_sdvo = {
 349         .dot = { .min = 20000, .max = 400000},
 350         .vco = { .min = 1700000, .max = 3500000 },
 351         /* Pineview's Ncounter is a ring counter */
 352         .n = { .min = 3, .max = 6 },
 353         .m = { .min = 2, .max = 256 },
 354         /* Pineview only has one combined m divider, which we treat as m2. */
 355         .m1 = { .min = 0, .max = 0 },
 356         .m2 = { .min = 0, .max = 254 },
 357         .p = { .min = 5, .max = 80 },
 358         .p1 = { .min = 1, .max = 8 },
 359         .p2 = { .dot_limit = 200000,
 360                 .p2_slow = 10, .p2_fast = 5 },
 361 };
 362
 363 static const struct intel_limit intel_limits_pineview_lvds = {
 364         .dot = { .min = 20000, .max = 400000 },
 365         .vco = { .min = 1700000, .max = 3500000 },
 366         .n = { .min = 3, .max = 6 },
 367         .m = { .min = 2, .max = 256 },
 368         .m1 = { .min = 0, .max = 0 },
 369         .m2 = { .min = 0, .max = 254 },
 370         .p = { .min = 7, .max = 112 },
 371         .p1 = { .min = 1, .max = 8 },
 372         .p2 = { .dot_limit = 112000,
 373                 .p2_slow = 14, .p2_fast = 14 },
 374 };
 375
 376 /* Ironlake / Sandybridge
 377  *
 378  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 379  * the range value for them is (actual_value - 2).
 380  */
 381 static const struct intel_limit intel_limits_ironlake_dac = {
 382         .dot = { .min = 25000, .max = 350000 },
 383         .vco = { .min = 1760000, .max = 3510000 },
 384         .n = { .min = 1, .max = 5 },
 385         .m = { .min = 79, .max = 127 },
 386         .m1 = { .min = 12, .max = 22 },
 387         .m2 = { .min = 5, .max = 9 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 225000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 395         .dot = { .min = 25000, .max = 350000 },
 396         .vco = { .min = 1760000, .max = 3510000 },
 397         .n = { .min = 1, .max = 3 },
 398         .m = { .min = 79, .max = 118 },
 399         .m1 = { .min = 12, .max = 22 },
 400         .m2 = { .min = 5, .max = 9 },
 401         .p = { .min = 28, .max = 112 },
 402         .p1 = { .min = 2, .max = 8 },
 403         .p2 = { .dot_limit = 225000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 3 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 14, .max = 56 },
 415         .p1 = { .min = 2, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 7, .p2_fast = 7 },
 418 };
 419
 420 /* LVDS 100mhz refclk limits. */
 421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 2 },
 425         .m = { .min = 79, .max = 126 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 126 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 42 },
 442         .p1 = { .min = 2, .max = 6 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 static const struct intel_limit intel_limits_vlv = {
 448          /*
 449           * These are the data rate limits (measured in fast clocks)
 450           * since those are the strictest limits we have. The fast
 451           * clock and actual rate limits are more relaxed, so checking
 452           * them would make no difference.
 453           */
 454         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 455         .vco = { .min = 4000000, .max = 6000000 },
 456         .n = { .min = 1, .max = 7 },
 457         .m1 = { .min = 2, .max = 3 },
 458         .m2 = { .min = 11, .max = 156 },
 459         .p1 = { .min = 2, .max = 3 },
 460         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 461 };
 462
 463 static const struct intel_limit intel_limits_chv = {
 464         /*
 465          * These are the data rate limits (measured in fast clocks)
 466          * since those are the strictest limits we have.  The fast
 467          * clock and actual rate limits are more relaxed, so checking
 468          * them would make no difference.
 469          */
 470         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 471         .vco = { .min = 4800000, .max = 6480000 },
 472         .n = { .min = 1, .max = 1 },
 473         .m1 = { .min = 2, .max = 2 },
 474         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 475         .p1 = { .min = 2, .max = 4 },
 476         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 477 };
 478
 479 static const struct intel_limit intel_limits_bxt = {
 480         /* FIXME: find real dot limits */
 481         .dot = { .min = 0, .max = INT_MAX },
 482         .vco = { .min = 4800000, .max = 6700000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         /* FIXME: find real m2 limits */
 486         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 487         .p1 = { .min = 2, .max = 4 },
 488         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 489 };
 490
 491 static bool
 492 needs_modeset(struct drm_crtc_state *state)
 493 {
 494         return drm_atomic_crtc_needs_modeset(state);
 495 }
 496
 497 /*
 498  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 499  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 500  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 501  * The helpers' return value is the rate of the clock that is fed to the
 502  * display engine's pipe which can be the above fast dot clock rate or a
 503  * divided-down version of it.
 504  */
 505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 506 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 507 {
 508         clock->m = clock->m2 + 2;
 509         clock->p = clock->p1 * clock->p2;
 510         if (WARN_ON(clock->n == 0 || clock->p == 0))
 511                 return 0;
 512         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 513         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 514
 515         return clock->dot;
 516 }
 517
 518 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 519 {
 520         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 521 }
 522
 523 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 524 {
 525         clock->m = i9xx_dpll_compute_m(clock);
 526         clock->p = clock->p1 * clock->p2;
 527         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 528                 return 0;
 529         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 530         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 531
 532         return clock->dot;
 533 }
 534
 535 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 536 {
 537         clock->m = clock->m1 * clock->m2;
 538         clock->p = clock->p1 * clock->p2;
 539         if (WARN_ON(clock->n == 0 || clock->p == 0))
 540                 return 0;
 541         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 542         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 543
 544         return clock->dot / 5;
 545 }
 546
 547 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 548 {
 549         clock->m = clock->m1 * clock->m2;
 550         clock->p = clock->p1 * clock->p2;
 551         if (WARN_ON(clock->n == 0 || clock->p == 0))
 552                 return 0;
 553         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 554                         clock->n << 22);
 555         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 556
 557         return clock->dot / 5;
 558 }
 559
 560 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 561 /**
 562  * Returns whether the given set of divisors are valid for a given refclk with
 563  * the given connectors.
 564  */
 565
 566 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 567                                const struct intel_limit *limit,
 568                                const struct dpll *clock)
 569 {
 570         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 571                 INTELPllInvalid("n out of range\n");
 572         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 573                 INTELPllInvalid("p1 out of range\n");
 574         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 575                 INTELPllInvalid("m2 out of range\n");
 576         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 577                 INTELPllInvalid("m1 out of range\n");
 578
 579         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 580             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 581                 if (clock->m1 <= clock->m2)
 582                         INTELPllInvalid("m1 <= m2\n");
 583
 584         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 585             !IS_GEN9_LP(dev_priv)) {
 586                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 587                         INTELPllInvalid("p out of range\n");
 588                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 589                         INTELPllInvalid("m out of range\n");
 590         }
 591
 592         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 593                 INTELPllInvalid("vco out of range\n");
 594         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 595          * connector, etc., rather than just a single range.
 596          */
 597         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 598                 INTELPllInvalid("dot out of range\n");
 599
 600         return true;
 601 }
 602
 603 static int
 604 i9xx_select_p2_div(const struct intel_limit *limit,
 605                    const struct intel_crtc_state *crtc_state,
 606                    int target)
 607 {
 608         struct drm_device *dev = crtc_state->base.crtc->dev;
 609
 610         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 611                 /*
 612                  * For LVDS just rely on its current settings for dual-channel.
 613                  * We haven't figured out how to reliably set up different
 614                  * single/dual channel state, if we even can.
 615                  */
 616                 if (intel_is_dual_link_lvds(dev))
 617                         return limit->p2.p2_fast;
 618                 else
 619                         return limit->p2.p2_slow;
 620         } else {
 621                 if (target < limit->p2.dot_limit)
 622                         return limit->p2.p2_slow;
 623                 else
 624                         return limit->p2.p2_fast;
 625         }
 626 }
 627
 628 /*
 629  * Returns a set of divisors for the desired target clock with the given
 630  * refclk, or FALSE.  The returned values represent the clock equation:
 631  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 632  *
 633  * Target and reference clocks are specified in kHz.
 634  *
 635  * If match_clock is provided, then best_clock P divider must match the P
 636  * divider from @match_clock used for LVDS downclocking.
 637  */
 638 static bool
 639 i9xx_find_best_dpll(const struct intel_limit *limit,
 640                     struct intel_crtc_state *crtc_state,
 641                     int target, int refclk, struct dpll *match_clock,
 642                     struct dpll *best_clock)
 643 {
 644         struct drm_device *dev = crtc_state->base.crtc->dev;
 645         struct dpll clock;
 646         int err = target;
 647
 648         memset(best_clock, 0, sizeof(*best_clock));
 649
 650         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 651
 652         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 653              clock.m1++) {
 654                 for (clock.m2 = limit->m2.min;
 655                      clock.m2 <= limit->m2.max; clock.m2++) {
 656                         if (clock.m2 >= clock.m1)
 657                                 break;
 658                         for (clock.n = limit->n.min;
 659                              clock.n <= limit->n.max; clock.n++) {
 660                                 for (clock.p1 = limit->p1.min;
 661                                         clock.p1 <= limit->p1.max; clock.p1++) {
 662                                         int this_err;
 663
 664                                         i9xx_calc_dpll_params(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(to_i915(dev),
 666                                                                 limit,
 667                                                                 &clock))
 668                                                 continue;
 669                                         if (match_clock &&
 670                                             clock.p != match_clock->p)
 671                                                 continue;
 672
 673                                         this_err = abs(clock.dot - target);
 674                                         if (this_err < err) {
 675                                                 *best_clock = clock;
 676                                                 err = this_err;
 677                                         }
 678                                 }
 679                         }
 680                 }
 681         }
 682
 683         return (err != target);
 684 }
 685
 686 /*
 687  * Returns a set of divisors for the desired target clock with the given
 688  * refclk, or FALSE.  The returned values represent the clock equation:
 689  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 690  *
 691  * Target and reference clocks are specified in kHz.
 692  *
 693  * If match_clock is provided, then best_clock P divider must match the P
 694  * divider from @match_clock used for LVDS downclocking.
 695  */
 696 static bool
 697 pnv_find_best_dpll(const struct intel_limit *limit,
 698                    struct intel_crtc_state *crtc_state,
 699                    int target, int refclk, struct dpll *match_clock,
 700                    struct dpll *best_clock)
 701 {
 702         struct drm_device *dev = crtc_state->base.crtc->dev;
 703         struct dpll clock;
 704         int err = target;
 705
 706         memset(best_clock, 0, sizeof(*best_clock));
 707
 708         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 709
 710         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711              clock.m1++) {
 712                 for (clock.m2 = limit->m2.min;
 713                      clock.m2 <= limit->m2.max; clock.m2++) {
 714                         for (clock.n = limit->n.min;
 715                              clock.n <= limit->n.max; clock.n++) {
 716                                 for (clock.p1 = limit->p1.min;
 717                                         clock.p1 <= limit->p1.max; clock.p1++) {
 718                                         int this_err;
 719
 720                                         pnv_calc_dpll_params(refclk, &clock);
 721                                         if (!intel_PLL_is_valid(to_i915(dev),
 722                                                                 limit,
 723                                                                 &clock))
 724                                                 continue;
 725                                         if (match_clock &&
 726                                             clock.p != match_clock->p)
 727                                                 continue;
 728
 729                                         this_err = abs(clock.dot - target);
 730                                         if (this_err < err) {
 731                                                 *best_clock = clock;
 732                                                 err = this_err;
 733                                         }
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         return (err != target);
 740 }
 741
 742 /*
 743  * Returns a set of divisors for the desired target clock with the given
 744  * refclk, or FALSE.  The returned values represent the clock equation:
 745  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 746  *
 747  * Target and reference clocks are specified in kHz.
 748  *
 749  * If match_clock is provided, then best_clock P divider must match the P
 750  * divider from @match_clock used for LVDS downclocking.
 751  */
 752 static bool
 753 g4x_find_best_dpll(const struct intel_limit *limit,
 754                    struct intel_crtc_state *crtc_state,
 755                    int target, int refclk, struct dpll *match_clock,
 756                    struct dpll *best_clock)
 757 {
 758         struct drm_device *dev = crtc_state->base.crtc->dev;
 759         struct dpll clock;
 760         int max_n;
 761         bool found = false;
 762         /* approximately equals target * 0.00585 */
 763         int err_most = (target >> 8) + (target >> 9);
 764
 765         memset(best_clock, 0, sizeof(*best_clock));
 766
 767         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 768
 769         max_n = limit->n.max;
 770         /* based on hardware requirement, prefer smaller n to precision */
 771         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 772                 /* based on hardware requirement, prefere larger m1,m2 */
 773                 for (clock.m1 = limit->m1.max;
 774                      clock.m1 >= limit->m1.min; clock.m1--) {
 775                         for (clock.m2 = limit->m2.max;
 776                              clock.m2 >= limit->m2.min; clock.m2--) {
 777                                 for (clock.p1 = limit->p1.max;
 778                                      clock.p1 >= limit->p1.min; clock.p1--) {
 779                                         int this_err;
 780
 781                                         i9xx_calc_dpll_params(refclk, &clock);
 782                                         if (!intel_PLL_is_valid(to_i915(dev),
 783                                                                 limit,
 784                                                                 &clock))
 785                                                 continue;
 786
 787                                         this_err = abs(clock.dot - target);
 788                                         if (this_err < err_most) {
 789                                                 *best_clock = clock;
 790                                                 err_most = this_err;
 791                                                 max_n = clock.n;
 792                                                 found = true;
 793                                         }
 794                                 }
 795                         }
 796                 }
 797         }
 798         return found;
 799 }
 800
 801 /*
 802  * Check if the calculated PLL configuration is more optimal compared to the
 803  * best configuration and error found so far. Return the calculated error.
 804  */
 805 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 806                                const struct dpll *calculated_clock,
 807                                const struct dpll *best_clock,
 808                                unsigned int best_error_ppm,
 809                                unsigned int *error_ppm)
 810 {
 811         /*
 812          * For CHV ignore the error and consider only the P value.
 813          * Prefer a bigger P value based on HW requirements.
 814          */
 815         if (IS_CHERRYVIEW(to_i915(dev))) {
 816                 *error_ppm = 0;
 817
 818                 return calculated_clock->p > best_clock->p;
 819         }
 820
 821         if (WARN_ON_ONCE(!target_freq))
 822                 return false;
 823
 824         *error_ppm = div_u64(1000000ULL *
 825                                 abs(target_freq - calculated_clock->dot),
 826                              target_freq);
 827         /*
 828          * Prefer a better P value over a better (smaller) error if the error
 829          * is small. Ensure this preference for future configurations too by
 830          * setting the error to 0.
 831          */
 832         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 833                 *error_ppm = 0;
 834
 835                 return true;
 836         }
 837
 838         return *error_ppm + 10 < best_error_ppm;
 839 }
 840
 841 /*
 842  * Returns a set of divisors for the desired target clock with the given
 843  * refclk, or FALSE.  The returned values represent the clock equation:
 844  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 845  */
 846 static bool
 847 vlv_find_best_dpll(const struct intel_limit *limit,
 848                    struct intel_crtc_state *crtc_state,
 849                    int target, int refclk, struct dpll *match_clock,
 850                    struct dpll *best_clock)
 851 {
 852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 853         struct drm_device *dev = crtc->base.dev;
 854         struct dpll clock;
 855         unsigned int bestppm = 1000000;
 856         /* min update 19.2 MHz */
 857         int max_n = min(limit->n.max, refclk / 19200);
 858         bool found = false;
 859
 860         target *= 5; /* fast clock */
 861
 862         memset(best_clock, 0, sizeof(*best_clock));
 863
 864         /* based on hardware requirement, prefer smaller n to precision */
 865         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 866                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 867                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 868                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 869                                 clock.p = clock.p1 * clock.p2;
 870                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 871                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 872                                         unsigned int ppm;
 873
 874                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 875                                                                      refclk * clock.m1);
 876
 877                                         vlv_calc_dpll_params(refclk, &clock);
 878
 879                                         if (!intel_PLL_is_valid(to_i915(dev),
 880                                                                 limit,
 881                                                                 &clock))
 882                                                 continue;
 883
 884                                         if (!vlv_PLL_is_optimal(dev, target,
 885                                                                 &clock,
 886                                                                 best_clock,
 887                                                                 bestppm, &ppm))
 888                                                 continue;
 889
 890                                         *best_clock = clock;
 891                                         bestppm = ppm;
 892                                         found = true;
 893                                 }
 894                         }
 895                 }
 896         }
 897
 898         return found;
 899 }
 900
 901 /*
 902  * Returns a set of divisors for the desired target clock with the given
 903  * refclk, or FALSE.  The returned values represent the clock equation:
 904  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 905  */
 906 static bool
 907 chv_find_best_dpll(const struct intel_limit *limit,
 908                    struct intel_crtc_state *crtc_state,
 909                    int target, int refclk, struct dpll *match_clock,
 910                    struct dpll *best_clock)
 911 {
 912         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 913         struct drm_device *dev = crtc->base.dev;
 914         unsigned int best_error_ppm;
 915         struct dpll clock;
 916         uint64_t m2;
 917         int found = false;
 918
 919         memset(best_clock, 0, sizeof(*best_clock));
 920         best_error_ppm = 1000000;
 921
 922         /*
 923          * Based on hardware doc, the n always set to 1, and m1 always
 924          * set to 2.  If requires to support 200Mhz refclk, we need to
 925          * revisit this because n may not 1 anymore.
 926          */
 927         clock.n = 1, clock.m1 = 2;
 928         target *= 5;    /* fast clock */
 929
 930         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 931                 for (clock.p2 = limit->p2.p2_fast;
 932                                 clock.p2 >= limit->p2.p2_slow;
 933                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 934                         unsigned int error_ppm;
 935
 936                         clock.p = clock.p1 * clock.p2;
 937
 938                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 939                                         clock.n) << 22, refclk * clock.m1);
 940
 941                         if (m2 > INT_MAX/clock.m1)
 942                                 continue;
 943
 944                         clock.m2 = m2;
 945
 946                         chv_calc_dpll_params(refclk, &clock);
 947
 948                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 949                                 continue;
 950
 951                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 952                                                 best_error_ppm, &error_ppm))
 953                                 continue;
 954
 955                         *best_clock = clock;
 956                         best_error_ppm = error_ppm;
 957                         found = true;
 958                 }
 959         }
 960
 961         return found;
 962 }
 963
 964 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 965                         struct dpll *best_clock)
 966 {
 967         int refclk = 100000;
 968         const struct intel_limit *limit = &intel_limits_bxt;
 969
 970         return chv_find_best_dpll(limit, crtc_state,
 971                                   target_clock, refclk, NULL, best_clock);
 972 }
 973
 974 bool intel_crtc_active(struct intel_crtc *crtc)
 975 {
 976         /* Be paranoid as we can arrive here with only partial
 977          * state retrieved from the hardware during setup.
 978          *
 979          * We can ditch the adjusted_mode.crtc_clock check as soon
 980          * as Haswell has gained clock readout/fastboot support.
 981          *
 982          * We can ditch the crtc->primary->fb check as soon as we can
 983          * properly reconstruct framebuffers.
 984          *
 985          * FIXME: The intel_crtc->active here should be switched to
 986          * crtc->state->active once we have proper CRTC states wired up
 987          * for atomic.
 988          */
 989         return crtc->active && crtc->base.primary->state->fb &&
 990                 crtc->config->base.adjusted_mode.crtc_clock;
 991 }
 992
 993 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 994                                              enum pipe pipe)
 995 {
 996         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 997
 998         return crtc->config->cpu_transcoder;
 999 }
1000
1001 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1002 {
1003         i915_reg_t reg = PIPEDSL(pipe);
1004         u32 line1, line2;
1005         u32 line_mask;
1006
1007         if (IS_GEN2(dev_priv))
1008                 line_mask = DSL_LINEMASK_GEN2;
1009         else
1010                 line_mask = DSL_LINEMASK_GEN3;
1011
1012         line1 = I915_READ(reg) & line_mask;
1013         msleep(5);
1014         line2 = I915_READ(reg) & line_mask;
1015
1016         return line1 == line2;
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @crtc: crtc whose pipe to wait for
1022  *
1023  * After disabling a pipe, we can't wait for vblank in the usual way,
1024  * spinning on the vblank interrupt status bit, since we won't actually
1025  * see an interrupt when the pipe is disabled.
1026  *
1027  * On Gen4 and above:
1028  *   wait for the pipe register state bit to turn off
1029  *
1030  * Otherwise:
1031  *   wait for the display line value to settle (it usually
1032  *   ends up stopping at the start of the next frame).
1033  *
1034  */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1038         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1039         enum pipe pipe = crtc->pipe;
1040
1041         if (INTEL_GEN(dev_priv) >= 4) {
1042                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1043
1044                 /* Wait for the Pipe State to go off */
1045                 if (intel_wait_for_register(dev_priv,
1046                                             reg, I965_PIPECONF_ACTIVE, 0,
1047                                             100))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         } else {
1050                 /* Wait for the display line to settle */
1051                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1052                         WARN(1, "pipe_off wait timed out\n");
1053         }
1054 }
1055
1056 /* Only for pre-ILK configs */
1057 void assert_pll(struct drm_i915_private *dev_priv,
1058                 enum pipe pipe, bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         val = I915_READ(DPLL(pipe));
1064         cur_state = !!(val & DPLL_VCO_ENABLE);
1065         I915_STATE_WARN(cur_state != state,
1066              "PLL state assertion failure (expected %s, current %s)\n",
1067                         onoff(state), onoff(cur_state));
1068 }
1069
1070 /* XXX: the dsi pll is shared between MIPI DSI ports */
1071 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1072 {
1073         u32 val;
1074         bool cur_state;
1075
1076         mutex_lock(&dev_priv->sb_lock);
1077         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1078         mutex_unlock(&dev_priv->sb_lock);
1079
1080         cur_state = val & DSI_PLL_VCO_EN;
1081         I915_STATE_WARN(cur_state != state,
1082              "DSI PLL state assertion failure (expected %s, current %s)\n",
1083                         onoff(state), onoff(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087                           enum pipe pipe, bool state)
1088 {
1089         bool cur_state;
1090         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1091                                                                       pipe);
1092
1093         if (HAS_DDI(dev_priv)) {
1094                 /* DDI does not have a specific FDI_TX register */
1095                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1096                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1097         } else {
1098                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1099                 cur_state = !!(val & FDI_TX_ENABLE);
1100         }
1101         I915_STATE_WARN(cur_state != state,
1102              "FDI TX state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109                           enum pipe pipe, bool state)
1110 {
1111         u32 val;
1112         bool cur_state;
1113
1114         val = I915_READ(FDI_RX_CTL(pipe));
1115         cur_state = !!(val & FDI_RX_ENABLE);
1116         I915_STATE_WARN(cur_state != state,
1117              "FDI RX state assertion failure (expected %s, current %s)\n",
1118                         onoff(state), onoff(cur_state));
1119 }
1120 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1121 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122
1123 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1124                                       enum pipe pipe)
1125 {
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (IS_GEN5(dev_priv))
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv))
1134                 return;
1135
1136         val = I915_READ(FDI_TX_CTL(pipe));
1137         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1138 }
1139
1140 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1141                        enum pipe pipe, bool state)
1142 {
1143         u32 val;
1144         bool cur_state;
1145
1146         val = I915_READ(FDI_RX_CTL(pipe));
1147         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1148         I915_STATE_WARN(cur_state != state,
1149              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1150                         onoff(state), onoff(cur_state));
1151 }
1152
1153 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1154 {
1155         i915_reg_t pp_reg;
1156         u32 val;
1157         enum pipe panel_pipe = PIPE_A;
1158         bool locked = true;
1159
1160         if (WARN_ON(HAS_DDI(dev_priv)))
1161                 return;
1162
1163         if (HAS_PCH_SPLIT(dev_priv)) {
1164                 u32 port_sel;
1165
1166                 pp_reg = PP_CONTROL(0);
1167                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1168
1169                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1170                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1171                         panel_pipe = PIPE_B;
1172                 /* XXX: else fix for eDP */
1173         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1174                 /* presumably write lock depends on pipe, not port select */
1175                 pp_reg = PP_CONTROL(pipe);
1176                 panel_pipe = pipe;
1177         } else {
1178                 pp_reg = PP_CONTROL(0);
1179                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1180                         panel_pipe = PIPE_B;
1181         }
1182
1183         val = I915_READ(pp_reg);
1184         if (!(val & PANEL_POWER_ON) ||
1185             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1186                 locked = false;
1187
1188         I915_STATE_WARN(panel_pipe == pipe && locked,
1189              "panel assertion failure, pipe %c regs locked\n",
1190              pipe_name(pipe));
1191 }
1192
1193 static void assert_cursor(struct drm_i915_private *dev_priv,
1194                           enum pipe pipe, bool state)
1195 {
1196         bool cur_state;
1197
1198         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1199                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1200         else
1201                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1202
1203         I915_STATE_WARN(cur_state != state,
1204              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1205                         pipe_name(pipe), onoff(state), onoff(cur_state));
1206 }
1207 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1208 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1209
1210 void assert_pipe(struct drm_i915_private *dev_priv,
1211                  enum pipe pipe, bool state)
1212 {
1213         bool cur_state;
1214         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1215                                                                       pipe);
1216         enum intel_display_power_domain power_domain;
1217
1218         /* we keep both pipes enabled on 830 */
1219         if (IS_I830(dev_priv))
1220                 state = true;
1221
1222         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1223         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1224                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1225                 cur_state = !!(val & PIPECONF_ENABLE);
1226
1227                 intel_display_power_put(dev_priv, power_domain);
1228         } else {
1229                 cur_state = false;
1230         }
1231
1232         I915_STATE_WARN(cur_state != state,
1233              "pipe %c assertion failure (expected %s, current %s)\n",
1234                         pipe_name(pipe), onoff(state), onoff(cur_state));
1235 }
1236
1237 static void assert_plane(struct drm_i915_private *dev_priv,
1238                          enum plane plane, bool state)
1239 {
1240         u32 val;
1241         bool cur_state;
1242
1243         val = I915_READ(DSPCNTR(plane));
1244         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1245         I915_STATE_WARN(cur_state != state,
1246              "plane %c assertion failure (expected %s, current %s)\n",
1247                         plane_name(plane), onoff(state), onoff(cur_state));
1248 }
1249
1250 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1251 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1252
1253 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1254                                    enum pipe pipe)
1255 {
1256         int i;
1257
1258         /* Primary planes are fixed to pipes on gen4+ */
1259         if (INTEL_GEN(dev_priv) >= 4) {
1260                 u32 val = I915_READ(DSPCNTR(pipe));
1261                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1262                      "plane %c assertion failure, should be disabled but not\n",
1263                      plane_name(pipe));
1264                 return;
1265         }
1266
1267         /* Need to check both planes against the pipe */
1268         for_each_pipe(dev_priv, i) {
1269                 u32 val = I915_READ(DSPCNTR(i));
1270                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         int sprite;
1282
1283         if (INTEL_GEN(dev_priv) >= 9) {
1284                 for_each_sprite(dev_priv, pipe, sprite) {
1285                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1286                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1287                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1288                              sprite, pipe_name(pipe));
1289                 }
1290         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1291                 for_each_sprite(dev_priv, pipe, sprite) {
1292                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1293                         I915_STATE_WARN(val & SP_ENABLE,
1294                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1295                              sprite_name(pipe, sprite), pipe_name(pipe));
1296                 }
1297         } else if (INTEL_GEN(dev_priv) >= 7) {
1298                 u32 val = I915_READ(SPRCTL(pipe));
1299                 I915_STATE_WARN(val & SPRITE_ENABLE,
1300                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1301                      plane_name(pipe), pipe_name(pipe));
1302         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1303                 u32 val = I915_READ(DVSCNTR(pipe));
1304                 I915_STATE_WARN(val & DVS_ENABLE,
1305                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306                      plane_name(pipe), pipe_name(pipe));
1307         }
1308 }
1309
1310 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 {
1312         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1313                 drm_crtc_vblank_put(crtc);
1314 }
1315
1316 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                     enum pipe pipe)
1318 {
1319         u32 val;
1320         bool enabled;
1321
1322         val = I915_READ(PCH_TRANSCONF(pipe));
1323         enabled = !!(val & TRANS_ENABLE);
1324         I915_STATE_WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv)) {
1336                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1337                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1338                         return false;
1339         } else if (IS_CHERRYVIEW(dev_priv)) {
1340                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & SDVO_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv)) {
1356                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1357                         return false;
1358         } else if (IS_CHERRYVIEW(dev_priv)) {
1359                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1360                         return false;
1361         } else {
1362                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1363                         return false;
1364         }
1365         return true;
1366 }
1367
1368 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1369                               enum pipe pipe, u32 val)
1370 {
1371         if ((val & LVDS_PORT_EN) == 0)
1372                 return false;
1373
1374         if (HAS_PCH_CPT(dev_priv)) {
1375                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & ADPA_DAC_ENABLE) == 0)
1388                 return false;
1389         if (HAS_PCH_CPT(dev_priv)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1400                                    enum pipe pipe, i915_reg_t reg,
1401                                    u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              i915_mmio_reg_offset(reg), pipe_name(pipe));
1407
1408         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, i915_reg_t reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              i915_mmio_reg_offset(reg), pipe_name(pipe));
1420
1421         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         u32 val;
1430
1431         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1434
1435         val = I915_READ(PCH_ADPA);
1436         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1437              "PCH VGA enabled on transcoder %c, should be disabled\n",
1438              pipe_name(pipe));
1439
1440         val = I915_READ(PCH_LVDS);
1441         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1442              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1443              pipe_name(pipe));
1444
1445         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1448 }
1449
1450 static void _vlv_enable_pll(struct intel_crtc *crtc,
1451                             const struct intel_crtc_state *pipe_config)
1452 {
1453         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1454         enum pipe pipe = crtc->pipe;
1455
1456         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457         POSTING_READ(DPLL(pipe));
1458         udelay(150);
1459
1460         if (intel_wait_for_register(dev_priv,
1461                                     DPLL(pipe),
1462                                     DPLL_LOCK_VLV,
1463                                     DPLL_LOCK_VLV,
1464                                     1))
1465                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1466 }
1467
1468 static void vlv_enable_pll(struct intel_crtc *crtc,
1469                            const struct intel_crtc_state *pipe_config)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1472         enum pipe pipe = crtc->pipe;
1473
1474         assert_pipe_disabled(dev_priv, pipe);
1475
1476         /* PLL is protected by panel, make sure we can write it */
1477         assert_panel_unlocked(dev_priv, pipe);
1478
1479         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1480                 _vlv_enable_pll(crtc, pipe_config);
1481
1482         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1483         POSTING_READ(DPLL_MD(pipe));
1484 }
1485
1486
1487 static void _chv_enable_pll(struct intel_crtc *crtc,
1488                             const struct intel_crtc_state *pipe_config)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1491         enum pipe pipe = crtc->pipe;
1492         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1493         u32 tmp;
1494
1495         mutex_lock(&dev_priv->sb_lock);
1496
1497         /* Enable back the 10bit clock to display controller */
1498         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1499         tmp |= DPIO_DCLKP_EN;
1500         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1501
1502         mutex_unlock(&dev_priv->sb_lock);
1503
1504         /*
1505          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1506          */
1507         udelay(1);
1508
1509         /* Enable PLL */
1510         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1511
1512         /* Check PLL is locked */
1513         if (intel_wait_for_register(dev_priv,
1514                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1515                                     1))
1516                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1517 }
1518
1519 static void chv_enable_pll(struct intel_crtc *crtc,
1520                            const struct intel_crtc_state *pipe_config)
1521 {
1522         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1523         enum pipe pipe = crtc->pipe;
1524
1525         assert_pipe_disabled(dev_priv, pipe);
1526
1527         /* PLL is protected by panel, make sure we can write it */
1528         assert_panel_unlocked(dev_priv, pipe);
1529
1530         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1531                 _chv_enable_pll(crtc, pipe_config);
1532
1533         if (pipe != PIPE_A) {
1534                 /*
1535                  * WaPixelRepeatModeFixForC0:chv
1536                  *
1537                  * DPLLCMD is AWOL. Use chicken bits to propagate
1538                  * the value from DPLLBMD to either pipe B or C.
1539                  */
1540                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1541                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1542                 I915_WRITE(CBR4_VLV, 0);
1543                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1544
1545                 /*
1546                  * DPLLB VGA mode also seems to cause problems.
1547                  * We should always have it disabled.
1548                  */
1549                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1550         } else {
1551                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1552                 POSTING_READ(DPLL_MD(pipe));
1553         }
1554 }
1555
1556 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1557 {
1558         struct intel_crtc *crtc;
1559         int count = 0;
1560
1561         for_each_intel_crtc(&dev_priv->drm, crtc) {
1562                 count += crtc->base.state->active &&
1563                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1564         }
1565
1566         return count;
1567 }
1568
1569 static void i9xx_enable_pll(struct intel_crtc *crtc,
1570                             const struct intel_crtc_state *crtc_state)
1571 {
1572         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1573         i915_reg_t reg = DPLL(crtc->pipe);
1574         u32 dpll = crtc_state->dpll_hw_state.dpll;
1575         int i;
1576
1577         assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579         /* PLL is protected by panel, make sure we can write it */
1580         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1581                 assert_panel_unlocked(dev_priv, crtc->pipe);
1582
1583         /* Enable DVO 2x clock on both PLLs if necessary */
1584         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1585                 /*
1586                  * It appears to be important that we don't enable this
1587                  * for the current pipe before otherwise configuring the
1588                  * PLL. No idea how this should be handled if multiple
1589                  * DVO outputs are enabled simultaneosly.
1590                  */
1591                 dpll |= DPLL_DVO_2X_MODE;
1592                 I915_WRITE(DPLL(!crtc->pipe),
1593                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1594         }
1595
1596         /*
1597          * Apparently we need to have VGA mode enabled prior to changing
1598          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1599          * dividers, even though the register value does change.
1600          */
1601         I915_WRITE(reg, 0);
1602
1603         I915_WRITE(reg, dpll);
1604
1605         /* Wait for the clocks to stabilize. */
1606         POSTING_READ(reg);
1607         udelay(150);
1608
1609         if (INTEL_GEN(dev_priv) >= 4) {
1610                 I915_WRITE(DPLL_MD(crtc->pipe),
1611                            crtc_state->dpll_hw_state.dpll_md);
1612         } else {
1613                 /* The pixel multiplier can only be updated once the
1614                  * DPLL is enabled and the clocks are stable.
1615                  *
1616                  * So write it again.
1617                  */
1618                 I915_WRITE(reg, dpll);
1619         }
1620
1621         /* We do this three times for luck */
1622         for (i = 0; i < 3; i++) {
1623                 I915_WRITE(reg, dpll);
1624                 POSTING_READ(reg);
1625                 udelay(150); /* wait for warmup */
1626         }
1627 }
1628
1629 static void i9xx_disable_pll(struct intel_crtc *crtc)
1630 {
1631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1632         enum pipe pipe = crtc->pipe;
1633
1634         /* Disable DVO 2x clock on both PLLs if necessary */
1635         if (IS_I830(dev_priv) &&
1636             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1637             !intel_num_dvo_pipes(dev_priv)) {
1638                 I915_WRITE(DPLL(PIPE_B),
1639                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1640                 I915_WRITE(DPLL(PIPE_A),
1641                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1642         }
1643
1644         /* Don't disable pipe or pipe PLLs if needed */
1645         if (IS_I830(dev_priv))
1646                 return;
1647
1648         /* Make sure the pipe isn't still relying on us */
1649         assert_pipe_disabled(dev_priv, pipe);
1650
1651         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1652         POSTING_READ(DPLL(pipe));
1653 }
1654
1655 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1656 {
1657         u32 val;
1658
1659         /* Make sure the pipe isn't still relying on us */
1660         assert_pipe_disabled(dev_priv, pipe);
1661
1662         val = DPLL_INTEGRATED_REF_CLK_VLV |
1663                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1664         if (pipe != PIPE_A)
1665                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1666
1667         I915_WRITE(DPLL(pipe), val);
1668         POSTING_READ(DPLL(pipe));
1669 }
1670
1671 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1672 {
1673         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1674         u32 val;
1675
1676         /* Make sure the pipe isn't still relying on us */
1677         assert_pipe_disabled(dev_priv, pipe);
1678
1679         val = DPLL_SSC_REF_CLK_CHV |
1680                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1681         if (pipe != PIPE_A)
1682                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1683
1684         I915_WRITE(DPLL(pipe), val);
1685         POSTING_READ(DPLL(pipe));
1686
1687         mutex_lock(&dev_priv->sb_lock);
1688
1689         /* Disable 10bit clock to display controller */
1690         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1691         val &= ~DPIO_DCLKP_EN;
1692         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1693
1694         mutex_unlock(&dev_priv->sb_lock);
1695 }
1696
1697 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1698                          struct intel_digital_port *dport,
1699                          unsigned int expected_mask)
1700 {
1701         u32 port_mask;
1702         i915_reg_t dpll_reg;
1703
1704         switch (dport->base.port) {
1705         case PORT_B:
1706                 port_mask = DPLL_PORTB_READY_MASK;
1707                 dpll_reg = DPLL(0);
1708                 break;
1709         case PORT_C:
1710                 port_mask = DPLL_PORTC_READY_MASK;
1711                 dpll_reg = DPLL(0);
1712                 expected_mask <<= 4;
1713                 break;
1714         case PORT_D:
1715                 port_mask = DPLL_PORTD_READY_MASK;
1716                 dpll_reg = DPIO_PHY_STATUS;
1717                 break;
1718         default:
1719                 BUG();
1720         }
1721
1722         if (intel_wait_for_register(dev_priv,
1723                                     dpll_reg, port_mask, expected_mask,
1724                                     1000))
1725                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1726                      port_name(dport->base.port),
1727                      I915_READ(dpll_reg) & port_mask, expected_mask);
1728 }
1729
1730 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1731                                            enum pipe pipe)
1732 {
1733         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1734                                                                 pipe);
1735         i915_reg_t reg;
1736         uint32_t val, pipeconf_val;
1737
1738         /* Make sure PCH DPLL is enabled */
1739         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1740
1741         /* FDI must be feeding us bits for PCH ports */
1742         assert_fdi_tx_enabled(dev_priv, pipe);
1743         assert_fdi_rx_enabled(dev_priv, pipe);
1744
1745         if (HAS_PCH_CPT(dev_priv)) {
1746                 /* Workaround: Set the timing override bit before enabling the
1747                  * pch transcoder. */
1748                 reg = TRANS_CHICKEN2(pipe);
1749                 val = I915_READ(reg);
1750                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751                 I915_WRITE(reg, val);
1752         }
1753
1754         reg = PCH_TRANSCONF(pipe);
1755         val = I915_READ(reg);
1756         pipeconf_val = I915_READ(PIPECONF(pipe));
1757
1758         if (HAS_PCH_IBX(dev_priv)) {
1759                 /*
1760                  * Make the BPC in transcoder be consistent with
1761                  * that in pipeconf reg. For HDMI we must use 8bpc
1762                  * here for both 8bpc and 12bpc.
1763                  */
1764                 val &= ~PIPECONF_BPC_MASK;
1765                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1766                         val |= PIPECONF_8BPC;
1767                 else
1768                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1769         }
1770
1771         val &= ~TRANS_INTERLACE_MASK;
1772         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1773                 if (HAS_PCH_IBX(dev_priv) &&
1774                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1775                         val |= TRANS_LEGACY_INTERLACED_ILK;
1776                 else
1777                         val |= TRANS_INTERLACED;
1778         else
1779                 val |= TRANS_PROGRESSIVE;
1780
1781         I915_WRITE(reg, val | TRANS_ENABLE);
1782         if (intel_wait_for_register(dev_priv,
1783                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1784                                     100))
1785                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1786 }
1787
1788 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789                                       enum transcoder cpu_transcoder)
1790 {
1791         u32 val, pipeconf_val;
1792
1793         /* FDI must be feeding us bits for PCH ports */
1794         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1795         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1796
1797         /* Workaround: set timing override bit. */
1798         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1799         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1800         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1801
1802         val = TRANS_ENABLE;
1803         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1804
1805         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1806             PIPECONF_INTERLACED_ILK)
1807                 val |= TRANS_INTERLACED;
1808         else
1809                 val |= TRANS_PROGRESSIVE;
1810
1811         I915_WRITE(LPT_TRANSCONF, val);
1812         if (intel_wait_for_register(dev_priv,
1813                                     LPT_TRANSCONF,
1814                                     TRANS_STATE_ENABLE,
1815                                     TRANS_STATE_ENABLE,
1816                                     100))
1817                 DRM_ERROR("Failed to enable PCH transcoder\n");
1818 }
1819
1820 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1821                                             enum pipe pipe)
1822 {
1823         i915_reg_t reg;
1824         uint32_t val;
1825
1826         /* FDI relies on the transcoder */
1827         assert_fdi_tx_disabled(dev_priv, pipe);
1828         assert_fdi_rx_disabled(dev_priv, pipe);
1829
1830         /* Ports must be off as well */
1831         assert_pch_ports_disabled(dev_priv, pipe);
1832
1833         reg = PCH_TRANSCONF(pipe);
1834         val = I915_READ(reg);
1835         val &= ~TRANS_ENABLE;
1836         I915_WRITE(reg, val);
1837         /* wait for PCH transcoder off, transcoder state */
1838         if (intel_wait_for_register(dev_priv,
1839                                     reg, TRANS_STATE_ENABLE, 0,
1840                                     50))
1841                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1842
1843         if (HAS_PCH_CPT(dev_priv)) {
1844                 /* Workaround: Clear the timing override chicken bit again. */
1845                 reg = TRANS_CHICKEN2(pipe);
1846                 val = I915_READ(reg);
1847                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1848                 I915_WRITE(reg, val);
1849         }
1850 }
1851
1852 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1853 {
1854         u32 val;
1855
1856         val = I915_READ(LPT_TRANSCONF);
1857         val &= ~TRANS_ENABLE;
1858         I915_WRITE(LPT_TRANSCONF, val);
1859         /* wait for PCH transcoder off, transcoder state */
1860         if (intel_wait_for_register(dev_priv,
1861                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1862                                     50))
1863                 DRM_ERROR("Failed to disable PCH transcoder\n");
1864
1865         /* Workaround: clear timing override bit. */
1866         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1867         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1868         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1869 }
1870
1871 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1872 {
1873         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874
1875         WARN_ON(!crtc->config->has_pch_encoder);
1876
1877         if (HAS_PCH_LPT(dev_priv))
1878                 return PIPE_A;
1879         else
1880                 return crtc->pipe;
1881 }
1882
1883 /**
1884  * intel_enable_pipe - enable a pipe, asserting requirements
1885  * @crtc: crtc responsible for the pipe
1886  *
1887  * Enable @crtc's pipe, making sure that various hardware specific requirements
1888  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1889  */
1890 static void intel_enable_pipe(struct intel_crtc *crtc)
1891 {
1892         struct drm_device *dev = crtc->base.dev;
1893         struct drm_i915_private *dev_priv = to_i915(dev);
1894         enum pipe pipe = crtc->pipe;
1895         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1896         i915_reg_t reg;
1897         u32 val;
1898
1899         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1900
1901         assert_planes_disabled(dev_priv, pipe);
1902         assert_cursor_disabled(dev_priv, pipe);
1903         assert_sprites_disabled(dev_priv, pipe);
1904
1905         /*
1906          * A pipe without a PLL won't actually be able to drive bits from
1907          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1908          * need the check.
1909          */
1910         if (HAS_GMCH_DISPLAY(dev_priv)) {
1911                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1912                         assert_dsi_pll_enabled(dev_priv);
1913                 else
1914                         assert_pll_enabled(dev_priv, pipe);
1915         } else {
1916                 if (crtc->config->has_pch_encoder) {
1917                         /* if driving the PCH, we need FDI enabled */
1918                         assert_fdi_rx_pll_enabled(dev_priv,
1919                                                   intel_crtc_pch_transcoder(crtc));
1920                         assert_fdi_tx_pll_enabled(dev_priv,
1921                                                   (enum pipe) cpu_transcoder);
1922                 }
1923                 /* FIXME: assert CPU port conditions for SNB+ */
1924         }
1925
1926         reg = PIPECONF(cpu_transcoder);
1927         val = I915_READ(reg);
1928         if (val & PIPECONF_ENABLE) {
1929                 /* we keep both pipes enabled on 830 */
1930                 WARN_ON(!IS_I830(dev_priv));
1931                 return;
1932         }
1933
1934         I915_WRITE(reg, val | PIPECONF_ENABLE);
1935         POSTING_READ(reg);
1936
1937         /*
1938          * Until the pipe starts DSL will read as 0, which would cause
1939          * an apparent vblank timestamp jump, which messes up also the
1940          * frame count when it's derived from the timestamps. So let's
1941          * wait for the pipe to start properly before we call
1942          * drm_crtc_vblank_on()
1943          */
1944         if (dev->max_vblank_count == 0 &&
1945             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1946                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1947 }
1948
1949 /**
1950  * intel_disable_pipe - disable a pipe, asserting requirements
1951  * @crtc: crtc whose pipes is to be disabled
1952  *
1953  * Disable the pipe of @crtc, making sure that various hardware
1954  * specific requirements are met, if applicable, e.g. plane
1955  * disabled, panel fitter off, etc.
1956  *
1957  * Will wait until the pipe has shut down before returning.
1958  */
1959 static void intel_disable_pipe(struct intel_crtc *crtc)
1960 {
1961         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1962         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1963         enum pipe pipe = crtc->pipe;
1964         i915_reg_t reg;
1965         u32 val;
1966
1967         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1968
1969         /*
1970          * Make sure planes won't keep trying to pump pixels to us,
1971          * or we might hang the display.
1972          */
1973         assert_planes_disabled(dev_priv, pipe);
1974         assert_cursor_disabled(dev_priv, pipe);
1975         assert_sprites_disabled(dev_priv, pipe);
1976
1977         reg = PIPECONF(cpu_transcoder);
1978         val = I915_READ(reg);
1979         if ((val & PIPECONF_ENABLE) == 0)
1980                 return;
1981
1982         /*
1983          * Double wide has implications for planes
1984          * so best keep it disabled when not needed.
1985          */
1986         if (crtc->config->double_wide)
1987                 val &= ~PIPECONF_DOUBLE_WIDE;
1988
1989         /* Don't disable pipe or pipe PLLs if needed */
1990         if (!IS_I830(dev_priv))
1991                 val &= ~PIPECONF_ENABLE;
1992
1993         I915_WRITE(reg, val);
1994         if ((val & PIPECONF_ENABLE) == 0)
1995                 intel_wait_for_pipe_off(crtc);
1996 }
1997
1998 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1999 {
2000         return IS_GEN2(dev_priv) ? 2048 : 4096;
2001 }
2002
2003 static unsigned int
2004 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2005 {
2006         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2007         unsigned int cpp = fb->format->cpp[plane];
2008
2009         switch (fb->modifier) {
2010         case DRM_FORMAT_MOD_LINEAR:
2011                 return cpp;
2012         case I915_FORMAT_MOD_X_TILED:
2013                 if (IS_GEN2(dev_priv))
2014                         return 128;
2015                 else
2016                         return 512;
2017         case I915_FORMAT_MOD_Y_TILED_CCS:
2018                 if (plane == 1)
2019                         return 128;
2020                 /* fall through */
2021         case I915_FORMAT_MOD_Y_TILED:
2022                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2023                         return 128;
2024                 else
2025                         return 512;
2026         case I915_FORMAT_MOD_Yf_TILED_CCS:
2027                 if (plane == 1)
2028                         return 128;
2029                 /* fall through */
2030         case I915_FORMAT_MOD_Yf_TILED:
2031                 switch (cpp) {
2032                 case 1:
2033                         return 64;
2034                 case 2:
2035                 case 4:
2036                         return 128;
2037                 case 8:
2038                 case 16:
2039                         return 256;
2040                 default:
2041                         MISSING_CASE(cpp);
2042                         return cpp;
2043                 }
2044                 break;
2045         default:
2046                 MISSING_CASE(fb->modifier);
2047                 return cpp;
2048         }
2049 }
2050
2051 static unsigned int
2052 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2053 {
2054         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2055                 return 1;
2056         else
2057                 return intel_tile_size(to_i915(fb->dev)) /
2058                         intel_tile_width_bytes(fb, plane);
2059 }
2060
2061 /* Return the tile dimensions in pixel units */
2062 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2063                             unsigned int *tile_width,
2064                             unsigned int *tile_height)
2065 {
2066         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2067         unsigned int cpp = fb->format->cpp[plane];
2068
2069         *tile_width = tile_width_bytes / cpp;
2070         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2071 }
2072
2073 unsigned int
2074 intel_fb_align_height(const struct drm_framebuffer *fb,
2075                       int plane, unsigned int height)
2076 {
2077         unsigned int tile_height = intel_tile_height(fb, plane);
2078
2079         return ALIGN(height, tile_height);
2080 }
2081
2082 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2083 {
2084         unsigned int size = 0;
2085         int i;
2086
2087         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2088                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2089
2090         return size;
2091 }
2092
2093 static void
2094 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2095                         const struct drm_framebuffer *fb,
2096                         unsigned int rotation)
2097 {
2098         view->type = I915_GGTT_VIEW_NORMAL;
2099         if (drm_rotation_90_or_270(rotation)) {
2100                 view->type = I915_GGTT_VIEW_ROTATED;
2101                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2102         }
2103 }
2104
2105 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2106 {
2107         if (IS_I830(dev_priv))
2108                 return 16 * 1024;
2109         else if (IS_I85X(dev_priv))
2110                 return 256;
2111         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2112                 return 32;
2113         else
2114                 return 4 * 1024;
2115 }
2116
2117 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2118 {
2119         if (INTEL_INFO(dev_priv)->gen >= 9)
2120                 return 256 * 1024;
2121         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2122                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2123                 return 128 * 1024;
2124         else if (INTEL_INFO(dev_priv)->gen >= 4)
2125                 return 4 * 1024;
2126         else
2127                 return 0;
2128 }
2129
2130 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2131                                          int plane)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2134
2135         /* AUX_DIST needs only 4K alignment */
2136         if (plane == 1)
2137                 return 4096;
2138
2139         switch (fb->modifier) {
2140         case DRM_FORMAT_MOD_LINEAR:
2141                 return intel_linear_alignment(dev_priv);
2142         case I915_FORMAT_MOD_X_TILED:
2143                 if (INTEL_GEN(dev_priv) >= 9)
2144                         return 256 * 1024;
2145                 return 0;
2146         case I915_FORMAT_MOD_Y_TILED_CCS:
2147         case I915_FORMAT_MOD_Yf_TILED_CCS:
2148         case I915_FORMAT_MOD_Y_TILED:
2149         case I915_FORMAT_MOD_Yf_TILED:
2150                 return 1 * 1024 * 1024;
2151         default:
2152                 MISSING_CASE(fb->modifier);
2153                 return 0;
2154         }
2155 }
2156
2157 struct i915_vma *
2158 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2159 {
2160         struct drm_device *dev = fb->dev;
2161         struct drm_i915_private *dev_priv = to_i915(dev);
2162         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2163         struct i915_ggtt_view view;
2164         struct i915_vma *vma;
2165         u32 alignment;
2166
2167         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2168
2169         alignment = intel_surf_alignment(fb, 0);
2170
2171         intel_fill_fb_ggtt_view(&view, fb, rotation);
2172
2173         /* Note that the w/a also requires 64 PTE of padding following the
2174          * bo. We currently fill all unused PTE with the shadow page and so
2175          * we should always have valid PTE following the scanout preventing
2176          * the VT-d warning.
2177          */
2178         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2179                 alignment = 256 * 1024;
2180
2181         /*
2182          * Global gtt pte registers are special registers which actually forward
2183          * writes to a chunk of system memory. Which means that there is no risk
2184          * that the register values disappear as soon as we call
2185          * intel_runtime_pm_put(), so it is correct to wrap only the
2186          * pin/unpin/fence and not more.
2187          */
2188         intel_runtime_pm_get(dev_priv);
2189
2190         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2191
2192         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2193         if (IS_ERR(vma))
2194                 goto err;
2195
2196         if (i915_vma_is_map_and_fenceable(vma)) {
2197                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2198                  * fence, whereas 965+ only requires a fence if using
2199                  * framebuffer compression.  For simplicity, we always, when
2200                  * possible, install a fence as the cost is not that onerous.
2201                  *
2202                  * If we fail to fence the tiled scanout, then either the
2203                  * modeset will reject the change (which is highly unlikely as
2204                  * the affected systems, all but one, do not have unmappable
2205                  * space) or we will not be able to enable full powersaving
2206                  * techniques (also likely not to apply due to various limits
2207                  * FBC and the like impose on the size of the buffer, which
2208                  * presumably we violated anyway with this unmappable buffer).
2209                  * Anyway, it is presumably better to stumble onwards with
2210                  * something and try to run the system in a "less than optimal"
2211                  * mode that matches the user configuration.
2212                  */
2213                 i915_vma_pin_fence(vma);
2214         }
2215
2216         i915_vma_get(vma);
2217 err:
2218         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2219
2220         intel_runtime_pm_put(dev_priv);
2221         return vma;
2222 }
2223
2224 void intel_unpin_fb_vma(struct i915_vma *vma)
2225 {
2226         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2227
2228         i915_vma_unpin_fence(vma);
2229         i915_gem_object_unpin_from_display_plane(vma);
2230         i915_vma_put(vma);
2231 }
2232
2233 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2234                           unsigned int rotation)
2235 {
2236         if (drm_rotation_90_or_270(rotation))
2237                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2238         else
2239                 return fb->pitches[plane];
2240 }
2241
2242 /*
2243  * Convert the x/y offsets into a linear offset.
2244  * Only valid with 0/180 degree rotation, which is fine since linear
2245  * offset is only used with linear buffers on pre-hsw and tiled buffers
2246  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2247  */
2248 u32 intel_fb_xy_to_linear(int x, int y,
2249                           const struct intel_plane_state *state,
2250                           int plane)
2251 {
2252         const struct drm_framebuffer *fb = state->base.fb;
2253         unsigned int cpp = fb->format->cpp[plane];
2254         unsigned int pitch = fb->pitches[plane];
2255
2256         return y * pitch + x * cpp;
2257 }
2258
2259 /*
2260  * Add the x/y offsets derived from fb->offsets[] to the user
2261  * specified plane src x/y offsets. The resulting x/y offsets
2262  * specify the start of scanout from the beginning of the gtt mapping.
2263  */
2264 void intel_add_fb_offsets(int *x, int *y,
2265                           const struct intel_plane_state *state,
2266                           int plane)
2267
2268 {
2269         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2270         unsigned int rotation = state->base.rotation;
2271
2272         if (drm_rotation_90_or_270(rotation)) {
2273                 *x += intel_fb->rotated[plane].x;
2274                 *y += intel_fb->rotated[plane].y;
2275         } else {
2276                 *x += intel_fb->normal[plane].x;
2277                 *y += intel_fb->normal[plane].y;
2278         }
2279 }
2280
2281 static u32 __intel_adjust_tile_offset(int *x, int *y,
2282                                       unsigned int tile_width,
2283                                       unsigned int tile_height,
2284                                       unsigned int tile_size,
2285                                       unsigned int pitch_tiles,
2286                                       u32 old_offset,
2287                                       u32 new_offset)
2288 {
2289         unsigned int pitch_pixels = pitch_tiles * tile_width;
2290         unsigned int tiles;
2291
2292         WARN_ON(old_offset & (tile_size - 1));
2293         WARN_ON(new_offset & (tile_size - 1));
2294         WARN_ON(new_offset > old_offset);
2295
2296         tiles = (old_offset - new_offset) / tile_size;
2297
2298         *y += tiles / pitch_tiles * tile_height;
2299         *x += tiles % pitch_tiles * tile_width;
2300
2301         /* minimize x in case it got needlessly big */
2302         *y += *x / pitch_pixels * tile_height;
2303         *x %= pitch_pixels;
2304
2305         return new_offset;
2306 }
2307
2308 static u32 _intel_adjust_tile_offset(int *x, int *y,
2309                                      const struct drm_framebuffer *fb, int plane,
2310                                      unsigned int rotation,
2311                                      u32 old_offset, u32 new_offset)
2312 {
2313         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2314         unsigned int cpp = fb->format->cpp[plane];
2315         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2316
2317         WARN_ON(new_offset > old_offset);
2318
2319         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2320                 unsigned int tile_size, tile_width, tile_height;
2321                 unsigned int pitch_tiles;
2322
2323                 tile_size = intel_tile_size(dev_priv);
2324                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2325
2326                 if (drm_rotation_90_or_270(rotation)) {
2327                         pitch_tiles = pitch / tile_height;
2328                         swap(tile_width, tile_height);
2329                 } else {
2330                         pitch_tiles = pitch / (tile_width * cpp);
2331                 }
2332
2333                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2334                                            tile_size, pitch_tiles,
2335                                            old_offset, new_offset);
2336         } else {
2337                 old_offset += *y * pitch + *x * cpp;
2338
2339                 *y = (old_offset - new_offset) / pitch;
2340                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2341         }
2342
2343         return new_offset;
2344 }
2345
2346 /*
2347  * Adjust the tile offset by moving the difference into
2348  * the x/y offsets.
2349  */
2350 static u32 intel_adjust_tile_offset(int *x, int *y,
2351                                     const struct intel_plane_state *state, int plane,
2352                                     u32 old_offset, u32 new_offset)
2353 {
2354         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2355                                          state->base.rotation,
2356                                          old_offset, new_offset);
2357 }
2358
2359 /*
2360  * Computes the linear offset to the base tile and adjusts
2361  * x, y. bytes per pixel is assumed to be a power-of-two.
2362  *
2363  * In the 90/270 rotated case, x and y are assumed
2364  * to be already rotated to match the rotated GTT view, and
2365  * pitch is the tile_height aligned framebuffer height.
2366  *
2367  * This function is used when computing the derived information
2368  * under intel_framebuffer, so using any of that information
2369  * here is not allowed. Anything under drm_framebuffer can be
2370  * used. This is why the user has to pass in the pitch since it
2371  * is specified in the rotated orientation.
2372  */
2373 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2374                                       int *x, int *y,
2375                                       const struct drm_framebuffer *fb, int plane,
2376                                       unsigned int pitch,
2377                                       unsigned int rotation,
2378                                       u32 alignment)
2379 {
2380         uint64_t fb_modifier = fb->modifier;
2381         unsigned int cpp = fb->format->cpp[plane];
2382         u32 offset, offset_aligned;
2383
2384         if (alignment)
2385                 alignment--;
2386
2387         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2388                 unsigned int tile_size, tile_width, tile_height;
2389                 unsigned int tile_rows, tiles, pitch_tiles;
2390
2391                 tile_size = intel_tile_size(dev_priv);
2392                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2393
2394                 if (drm_rotation_90_or_270(rotation)) {
2395                         pitch_tiles = pitch / tile_height;
2396                         swap(tile_width, tile_height);
2397                 } else {
2398                         pitch_tiles = pitch / (tile_width * cpp);
2399                 }
2400
2401                 tile_rows = *y / tile_height;
2402                 *y %= tile_height;
2403
2404                 tiles = *x / tile_width;
2405                 *x %= tile_width;
2406
2407                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2408                 offset_aligned = offset & ~alignment;
2409
2410                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2411                                            tile_size, pitch_tiles,
2412                                            offset, offset_aligned);
2413         } else {
2414                 offset = *y * pitch + *x * cpp;
2415                 offset_aligned = offset & ~alignment;
2416
2417                 *y = (offset & alignment) / pitch;
2418                 *x = ((offset & alignment) - *y * pitch) / cpp;
2419         }
2420
2421         return offset_aligned;
2422 }
2423
2424 u32 intel_compute_tile_offset(int *x, int *y,
2425                               const struct intel_plane_state *state,
2426                               int plane)
2427 {
2428         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2429         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2430         const struct drm_framebuffer *fb = state->base.fb;
2431         unsigned int rotation = state->base.rotation;
2432         int pitch = intel_fb_pitch(fb, plane, rotation);
2433         u32 alignment;
2434
2435         if (intel_plane->id == PLANE_CURSOR)
2436                 alignment = intel_cursor_alignment(dev_priv);
2437         else
2438                 alignment = intel_surf_alignment(fb, plane);
2439
2440         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2441                                           rotation, alignment);
2442 }
2443
2444 /* Convert the fb->offset[] into x/y offsets */
2445 static int intel_fb_offset_to_xy(int *x, int *y,
2446                                  const struct drm_framebuffer *fb, int plane)
2447 {
2448         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2449
2450         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2451             fb->offsets[plane] % intel_tile_size(dev_priv))
2452                 return -EINVAL;
2453
2454         *x = 0;
2455         *y = 0;
2456
2457         _intel_adjust_tile_offset(x, y,
2458                                   fb, plane, DRM_MODE_ROTATE_0,
2459                                   fb->offsets[plane], 0);
2460
2461         return 0;
2462 }
2463
2464 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2465 {
2466         switch (fb_modifier) {
2467         case I915_FORMAT_MOD_X_TILED:
2468                 return I915_TILING_X;
2469         case I915_FORMAT_MOD_Y_TILED:
2470         case I915_FORMAT_MOD_Y_TILED_CCS:
2471                 return I915_TILING_Y;
2472         default:
2473                 return I915_TILING_NONE;
2474         }
2475 }
2476
2477 static const struct drm_format_info ccs_formats[] = {
2478         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2479         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2480         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2481         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2482 };
2483
2484 static const struct drm_format_info *
2485 lookup_format_info(const struct drm_format_info formats[],
2486                    int num_formats, u32 format)
2487 {
2488         int i;
2489
2490         for (i = 0; i < num_formats; i++) {
2491                 if (formats[i].format == format)
2492                         return &formats[i];
2493         }
2494
2495         return NULL;
2496 }
2497
2498 static const struct drm_format_info *
2499 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2500 {
2501         switch (cmd->modifier[0]) {
2502         case I915_FORMAT_MOD_Y_TILED_CCS:
2503         case I915_FORMAT_MOD_Yf_TILED_CCS:
2504                 return lookup_format_info(ccs_formats,
2505                                           ARRAY_SIZE(ccs_formats),
2506                                           cmd->pixel_format);
2507         default:
2508                 return NULL;
2509         }
2510 }
2511
2512 static int
2513 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2514                    struct drm_framebuffer *fb)
2515 {
2516         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2517         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2518         u32 gtt_offset_rotated = 0;
2519         unsigned int max_size = 0;
2520         int i, num_planes = fb->format->num_planes;
2521         unsigned int tile_size = intel_tile_size(dev_priv);
2522
2523         for (i = 0; i < num_planes; i++) {
2524                 unsigned int width, height;
2525                 unsigned int cpp, size;
2526                 u32 offset;
2527                 int x, y;
2528                 int ret;
2529
2530                 cpp = fb->format->cpp[i];
2531                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2532                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2533
2534                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2535                 if (ret) {
2536                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2537                                       i, fb->offsets[i]);
2538                         return ret;
2539                 }
2540
2541                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2542                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2543                         int hsub = fb->format->hsub;
2544                         int vsub = fb->format->vsub;
2545                         int tile_width, tile_height;
2546                         int main_x, main_y;
2547                         int ccs_x, ccs_y;
2548
2549                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2550                         tile_width *= hsub;
2551                         tile_height *= vsub;
2552
2553                         ccs_x = (x * hsub) % tile_width;
2554                         ccs_y = (y * vsub) % tile_height;
2555                         main_x = intel_fb->normal[0].x % tile_width;
2556                         main_y = intel_fb->normal[0].y % tile_height;
2557
2558                         /*
2559                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2560                          * x/y offsets must match between CCS and the main surface.
2561                          */
2562                         if (main_x != ccs_x || main_y != ccs_y) {
2563                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2564                                               main_x, main_y,
2565                                               ccs_x, ccs_y,
2566                                               intel_fb->normal[0].x,
2567                                               intel_fb->normal[0].y,
2568                                               x, y);
2569                                 return -EINVAL;
2570                         }
2571                 }
2572
2573                 /*
2574                  * The fence (if used) is aligned to the start of the object
2575                  * so having the framebuffer wrap around across the edge of the
2576                  * fenced region doesn't really work. We have no API to configure
2577                  * the fence start offset within the object (nor could we probably
2578                  * on gen2/3). So it's just easier if we just require that the
2579                  * fb layout agrees with the fence layout. We already check that the
2580                  * fb stride matches the fence stride elsewhere.
2581                  */
2582                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2583                     (x + width) * cpp > fb->pitches[i]) {
2584                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2585                                       i, fb->offsets[i]);
2586                         return -EINVAL;
2587                 }
2588
2589                 /*
2590                  * First pixel of the framebuffer from
2591                  * the start of the normal gtt mapping.
2592                  */
2593                 intel_fb->normal[i].x = x;
2594                 intel_fb->normal[i].y = y;
2595
2596                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2597                                                     fb, i, fb->pitches[i],
2598                                                     DRM_MODE_ROTATE_0, tile_size);
2599                 offset /= tile_size;
2600
2601                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2602                         unsigned int tile_width, tile_height;
2603                         unsigned int pitch_tiles;
2604                         struct drm_rect r;
2605
2606                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2607
2608                         rot_info->plane[i].offset = offset;
2609                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2610                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2611                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2612
2613                         intel_fb->rotated[i].pitch =
2614                                 rot_info->plane[i].height * tile_height;
2615
2616                         /* how many tiles does this plane need */
2617                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2618                         /*
2619                          * If the plane isn't horizontally tile aligned,
2620                          * we need one more tile.
2621                          */
2622                         if (x != 0)
2623                                 size++;
2624
2625                         /* rotate the x/y offsets to match the GTT view */
2626                         r.x1 = x;
2627                         r.y1 = y;
2628                         r.x2 = x + width;
2629                         r.y2 = y + height;
2630                         drm_rect_rotate(&r,
2631                                         rot_info->plane[i].width * tile_width,
2632                                         rot_info->plane[i].height * tile_height,
2633                                         DRM_MODE_ROTATE_270);
2634                         x = r.x1;
2635                         y = r.y1;
2636
2637                         /* rotate the tile dimensions to match the GTT view */
2638                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2639                         swap(tile_width, tile_height);
2640
2641                         /*
2642                          * We only keep the x/y offsets, so push all of the
2643                          * gtt offset into the x/y offsets.
2644                          */
2645                         __intel_adjust_tile_offset(&x, &y,
2646                                                    tile_width, tile_height,
2647                                                    tile_size, pitch_tiles,
2648                                                    gtt_offset_rotated * tile_size, 0);
2649
2650                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2651
2652                         /*
2653                          * First pixel of the framebuffer from
2654                          * the start of the rotated gtt mapping.
2655                          */
2656                         intel_fb->rotated[i].x = x;
2657                         intel_fb->rotated[i].y = y;
2658                 } else {
2659                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2660                                             x * cpp, tile_size);
2661                 }
2662
2663                 /* how many tiles in total needed in the bo */
2664                 max_size = max(max_size, offset + size);
2665         }
2666
2667         if (max_size * tile_size > intel_fb->obj->base.size) {
2668                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2669                               max_size * tile_size, intel_fb->obj->base.size);
2670                 return -EINVAL;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int i9xx_format_to_fourcc(int format)
2677 {
2678         switch (format) {
2679         case DISPPLANE_8BPP:
2680                 return DRM_FORMAT_C8;
2681         case DISPPLANE_BGRX555:
2682                 return DRM_FORMAT_XRGB1555;
2683         case DISPPLANE_BGRX565:
2684                 return DRM_FORMAT_RGB565;
2685         default:
2686         case DISPPLANE_BGRX888:
2687                 return DRM_FORMAT_XRGB8888;
2688         case DISPPLANE_RGBX888:
2689                 return DRM_FORMAT_XBGR8888;
2690         case DISPPLANE_BGRX101010:
2691                 return DRM_FORMAT_XRGB2101010;
2692         case DISPPLANE_RGBX101010:
2693                 return DRM_FORMAT_XBGR2101010;
2694         }
2695 }
2696
2697 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2698 {
2699         switch (format) {
2700         case PLANE_CTL_FORMAT_RGB_565:
2701                 return DRM_FORMAT_RGB565;
2702         default:
2703         case PLANE_CTL_FORMAT_XRGB_8888:
2704                 if (rgb_order) {
2705                         if (alpha)
2706                                 return DRM_FORMAT_ABGR8888;
2707                         else
2708                                 return DRM_FORMAT_XBGR8888;
2709                 } else {
2710                         if (alpha)
2711                                 return DRM_FORMAT_ARGB8888;
2712                         else
2713                                 return DRM_FORMAT_XRGB8888;
2714                 }
2715         case PLANE_CTL_FORMAT_XRGB_2101010:
2716                 if (rgb_order)
2717                         return DRM_FORMAT_XBGR2101010;
2718                 else
2719                         return DRM_FORMAT_XRGB2101010;
2720         }
2721 }
2722
2723 static bool
2724 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2725                               struct intel_initial_plane_config *plane_config)
2726 {
2727         struct drm_device *dev = crtc->base.dev;
2728         struct drm_i915_private *dev_priv = to_i915(dev);
2729         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2730         struct drm_i915_gem_object *obj = NULL;
2731         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2732         struct drm_framebuffer *fb = &plane_config->fb->base;
2733         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2734         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2735                                     PAGE_SIZE);
2736
2737         size_aligned -= base_aligned;
2738
2739         if (plane_config->size == 0)
2740                 return false;
2741
2742         /* If the FB is too big, just don't use it since fbdev is not very
2743          * important and we should probably use that space with FBC or other
2744          * features. */
2745         if (size_aligned * 2 > ggtt->stolen_usable_size)
2746                 return false;
2747
2748         mutex_lock(&dev->struct_mutex);
2749         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2750                                                              base_aligned,
2751                                                              base_aligned,
2752                                                              size_aligned);
2753         mutex_unlock(&dev->struct_mutex);
2754         if (!obj)
2755                 return false;
2756
2757         if (plane_config->tiling == I915_TILING_X)
2758                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2759
2760         mode_cmd.pixel_format = fb->format->format;
2761         mode_cmd.width = fb->width;
2762         mode_cmd.height = fb->height;
2763         mode_cmd.pitches[0] = fb->pitches[0];
2764         mode_cmd.modifier[0] = fb->modifier;
2765         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2766
2767         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2768                 DRM_DEBUG_KMS("intel fb init failed\n");
2769                 goto out_unref_obj;
2770         }
2771
2772
2773         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2774         return true;
2775
2776 out_unref_obj:
2777         i915_gem_object_put(obj);
2778         return false;
2779 }
2780
2781 static void
2782 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2783                         struct intel_plane_state *plane_state,
2784                         bool visible)
2785 {
2786         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2787
2788         plane_state->base.visible = visible;
2789
2790         /* FIXME pre-g4x don't work like this */
2791         if (visible) {
2792                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2793                 crtc_state->active_planes |= BIT(plane->id);
2794         } else {
2795                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2796                 crtc_state->active_planes &= ~BIT(plane->id);
2797         }
2798
2799         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2800                       crtc_state->base.crtc->name,
2801                       crtc_state->active_planes);
2802 }
2803
2804 static void
2805 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2806                              struct intel_initial_plane_config *plane_config)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = to_i915(dev);
2810         struct drm_crtc *c;
2811         struct drm_i915_gem_object *obj;
2812         struct drm_plane *primary = intel_crtc->base.primary;
2813         struct drm_plane_state *plane_state = primary->state;
2814         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2815         struct intel_plane *intel_plane = to_intel_plane(primary);
2816         struct intel_plane_state *intel_state =
2817                 to_intel_plane_state(plane_state);
2818         struct drm_framebuffer *fb;
2819
2820         if (!plane_config->fb)
2821                 return;
2822
2823         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2824                 fb = &plane_config->fb->base;
2825                 goto valid_fb;
2826         }
2827
2828         kfree(plane_config->fb);
2829
2830         /*
2831          * Failed to alloc the obj, check to see if we should share
2832          * an fb with another CRTC instead
2833          */
2834         for_each_crtc(dev, c) {
2835                 struct intel_plane_state *state;
2836
2837                 if (c == &intel_crtc->base)
2838                         continue;
2839
2840                 if (!to_intel_crtc(c)->active)
2841                         continue;
2842
2843                 state = to_intel_plane_state(c->primary->state);
2844                 if (!state->vma)
2845                         continue;
2846
2847                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2848                         fb = c->primary->fb;
2849                         drm_framebuffer_get(fb);
2850                         goto valid_fb;
2851                 }
2852         }
2853
2854         /*
2855          * We've failed to reconstruct the BIOS FB.  Current display state
2856          * indicates that the primary plane is visible, but has a NULL FB,
2857          * which will lead to problems later if we don't fix it up.  The
2858          * simplest solution is to just disable the primary plane now and
2859          * pretend the BIOS never had it enabled.
2860          */
2861         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2862                                 to_intel_plane_state(plane_state),
2863                                 false);
2864         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2865         trace_intel_disable_plane(primary, intel_crtc);
2866         intel_plane->disable_plane(intel_plane, intel_crtc);
2867
2868         return;
2869
2870 valid_fb:
2871         mutex_lock(&dev->struct_mutex);
2872         intel_state->vma =
2873                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2874         mutex_unlock(&dev->struct_mutex);
2875         if (IS_ERR(intel_state->vma)) {
2876                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2877                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2878
2879                 intel_state->vma = NULL;
2880                 drm_framebuffer_put(fb);
2881                 return;
2882         }
2883
2884         plane_state->src_x = 0;
2885         plane_state->src_y = 0;
2886         plane_state->src_w = fb->width << 16;
2887         plane_state->src_h = fb->height << 16;
2888
2889         plane_state->crtc_x = 0;
2890         plane_state->crtc_y = 0;
2891         plane_state->crtc_w = fb->width;
2892         plane_state->crtc_h = fb->height;
2893
2894         intel_state->base.src = drm_plane_state_src(plane_state);
2895         intel_state->base.dst = drm_plane_state_dest(plane_state);
2896
2897         obj = intel_fb_obj(fb);
2898         if (i915_gem_object_is_tiled(obj))
2899                 dev_priv->preserve_bios_swizzle = true;
2900
2901         drm_framebuffer_get(fb);
2902         primary->fb = primary->state->fb = fb;
2903         primary->crtc = primary->state->crtc = &intel_crtc->base;
2904
2905         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2906                                 to_intel_plane_state(plane_state),
2907                                 true);
2908
2909         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2910                   &obj->frontbuffer_bits);
2911 }
2912
2913 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2914                                unsigned int rotation)
2915 {
2916         int cpp = fb->format->cpp[plane];
2917
2918         switch (fb->modifier) {
2919         case DRM_FORMAT_MOD_LINEAR:
2920         case I915_FORMAT_MOD_X_TILED:
2921                 switch (cpp) {
2922                 case 8:
2923                         return 4096;
2924                 case 4:
2925                 case 2:
2926                 case 1:
2927                         return 8192;
2928                 default:
2929                         MISSING_CASE(cpp);
2930                         break;
2931                 }
2932                 break;
2933         case I915_FORMAT_MOD_Y_TILED_CCS:
2934         case I915_FORMAT_MOD_Yf_TILED_CCS:
2935                 /* FIXME AUX plane? */
2936         case I915_FORMAT_MOD_Y_TILED:
2937         case I915_FORMAT_MOD_Yf_TILED:
2938                 switch (cpp) {
2939                 case 8:
2940                         return 2048;
2941                 case 4:
2942                         return 4096;
2943                 case 2:
2944                 case 1:
2945                         return 8192;
2946                 default:
2947                         MISSING_CASE(cpp);
2948                         break;
2949                 }
2950                 break;
2951         default:
2952                 MISSING_CASE(fb->modifier);
2953         }
2954
2955         return 2048;
2956 }
2957
2958 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2959                                            int main_x, int main_y, u32 main_offset)
2960 {
2961         const struct drm_framebuffer *fb = plane_state->base.fb;
2962         int hsub = fb->format->hsub;
2963         int vsub = fb->format->vsub;
2964         int aux_x = plane_state->aux.x;
2965         int aux_y = plane_state->aux.y;
2966         u32 aux_offset = plane_state->aux.offset;
2967         u32 alignment = intel_surf_alignment(fb, 1);
2968
2969         while (aux_offset >= main_offset && aux_y <= main_y) {
2970                 int x, y;
2971
2972                 if (aux_x == main_x && aux_y == main_y)
2973                         break;
2974
2975                 if (aux_offset == 0)
2976                         break;
2977
2978                 x = aux_x / hsub;
2979                 y = aux_y / vsub;
2980                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2981                                                       aux_offset, aux_offset - alignment);
2982                 aux_x = x * hsub + aux_x % hsub;
2983                 aux_y = y * vsub + aux_y % vsub;
2984         }
2985
2986         if (aux_x != main_x || aux_y != main_y)
2987                 return false;
2988
2989         plane_state->aux.offset = aux_offset;
2990         plane_state->aux.x = aux_x;
2991         plane_state->aux.y = aux_y;
2992
2993         return true;
2994 }
2995
2996 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2997 {
2998         const struct drm_framebuffer *fb = plane_state->base.fb;
2999         unsigned int rotation = plane_state->base.rotation;
3000         int x = plane_state->base.src.x1 >> 16;
3001         int y = plane_state->base.src.y1 >> 16;
3002         int w = drm_rect_width(&plane_state->base.src) >> 16;
3003         int h = drm_rect_height(&plane_state->base.src) >> 16;
3004         int max_width = skl_max_plane_width(fb, 0, rotation);
3005         int max_height = 4096;
3006         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3007
3008         if (w > max_width || h > max_height) {
3009                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3010                               w, h, max_width, max_height);
3011                 return -EINVAL;
3012         }
3013
3014         intel_add_fb_offsets(&x, &y, plane_state, 0);
3015         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3016         alignment = intel_surf_alignment(fb, 0);
3017
3018         /*
3019          * AUX surface offset is specified as the distance from the
3020          * main surface offset, and it must be non-negative. Make
3021          * sure that is what we will get.
3022          */
3023         if (offset > aux_offset)
3024                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3025                                                   offset, aux_offset & ~(alignment - 1));
3026
3027         /*
3028          * When using an X-tiled surface, the plane blows up
3029          * if the x offset + width exceed the stride.
3030          *
3031          * TODO: linear and Y-tiled seem fine, Yf untested,
3032          */
3033         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3034                 int cpp = fb->format->cpp[0];
3035
3036                 while ((x + w) * cpp > fb->pitches[0]) {
3037                         if (offset == 0) {
3038                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3039                                 return -EINVAL;
3040                         }
3041
3042                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3043                                                           offset, offset - alignment);
3044                 }
3045         }
3046
3047         /*
3048          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3049          * they match with the main surface x/y offsets.
3050          */
3051         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3052             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3053                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3054                         if (offset == 0)
3055                                 break;
3056
3057                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3058                                                           offset, offset - alignment);
3059                 }
3060
3061                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3062                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3063                         return -EINVAL;
3064                 }
3065         }
3066
3067         plane_state->main.offset = offset;
3068         plane_state->main.x = x;
3069         plane_state->main.y = y;
3070
3071         return 0;
3072 }
3073
3074 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3075 {
3076         const struct drm_framebuffer *fb = plane_state->base.fb;
3077         unsigned int rotation = plane_state->base.rotation;
3078         int max_width = skl_max_plane_width(fb, 1, rotation);
3079         int max_height = 4096;
3080         int x = plane_state->base.src.x1 >> 17;
3081         int y = plane_state->base.src.y1 >> 17;
3082         int w = drm_rect_width(&plane_state->base.src) >> 17;
3083         int h = drm_rect_height(&plane_state->base.src) >> 17;
3084         u32 offset;
3085
3086         intel_add_fb_offsets(&x, &y, plane_state, 1);
3087         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3088
3089         /* FIXME not quite sure how/if these apply to the chroma plane */
3090         if (w > max_width || h > max_height) {
3091                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3092                               w, h, max_width, max_height);
3093                 return -EINVAL;
3094         }
3095
3096         plane_state->aux.offset = offset;
3097         plane_state->aux.x = x;
3098         plane_state->aux.y = y;
3099
3100         return 0;
3101 }
3102
3103 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3104 {
3105         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3106         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3107         const struct drm_framebuffer *fb = plane_state->base.fb;
3108         int src_x = plane_state->base.src.x1 >> 16;
3109         int src_y = plane_state->base.src.y1 >> 16;
3110         int hsub = fb->format->hsub;
3111         int vsub = fb->format->vsub;
3112         int x = src_x / hsub;
3113         int y = src_y / vsub;
3114         u32 offset;
3115
3116         switch (plane->id) {
3117         case PLANE_PRIMARY:
3118         case PLANE_SPRITE0:
3119                 break;
3120         default:
3121                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3122                 return -EINVAL;
3123         }
3124
3125         if (crtc->pipe == PIPE_C) {
3126                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3127                 return -EINVAL;
3128         }
3129
3130         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3131                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3132                               plane_state->base.rotation);
3133                 return -EINVAL;
3134         }
3135
3136         intel_add_fb_offsets(&x, &y, plane_state, 1);
3137         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3138
3139         plane_state->aux.offset = offset;
3140         plane_state->aux.x = x * hsub + src_x % hsub;
3141         plane_state->aux.y = y * vsub + src_y % vsub;
3142
3143         return 0;
3144 }
3145
3146 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3147 {
3148         const struct drm_framebuffer *fb = plane_state->base.fb;
3149         unsigned int rotation = plane_state->base.rotation;
3150         int ret;
3151
3152         if (!plane_state->base.visible)
3153                 return 0;
3154
3155         /* Rotate src coordinates to match rotated GTT view */
3156         if (drm_rotation_90_or_270(rotation))
3157                 drm_rect_rotate(&plane_state->base.src,
3158                                 fb->width << 16, fb->height << 16,
3159                                 DRM_MODE_ROTATE_270);
3160
3161         /*
3162          * Handle the AUX surface first since
3163          * the main surface setup depends on it.
3164          */
3165         if (fb->format->format == DRM_FORMAT_NV12) {
3166                 ret = skl_check_nv12_aux_surface(plane_state);
3167                 if (ret)
3168                         return ret;
3169         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3170                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3171                 ret = skl_check_ccs_aux_surface(plane_state);
3172                 if (ret)
3173                         return ret;
3174         } else {
3175                 plane_state->aux.offset = ~0xfff;
3176                 plane_state->aux.x = 0;
3177                 plane_state->aux.y = 0;
3178         }
3179
3180         ret = skl_check_main_surface(plane_state);
3181         if (ret)
3182                 return ret;
3183
3184         return 0;
3185 }
3186
3187 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3188                           const struct intel_plane_state *plane_state)
3189 {
3190         struct drm_i915_private *dev_priv =
3191                 to_i915(plane_state->base.plane->dev);
3192         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3193         const struct drm_framebuffer *fb = plane_state->base.fb;
3194         unsigned int rotation = plane_state->base.rotation;
3195         u32 dspcntr;
3196
3197         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3198
3199         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3200             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3201                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3202
3203         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3204                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3205
3206         if (INTEL_GEN(dev_priv) < 4)
3207                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3208
3209         switch (fb->format->format) {
3210         case DRM_FORMAT_C8:
3211                 dspcntr |= DISPPLANE_8BPP;
3212                 break;
3213         case DRM_FORMAT_XRGB1555:
3214                 dspcntr |= DISPPLANE_BGRX555;
3215                 break;
3216         case DRM_FORMAT_RGB565:
3217                 dspcntr |= DISPPLANE_BGRX565;
3218                 break;
3219         case DRM_FORMAT_XRGB8888:
3220                 dspcntr |= DISPPLANE_BGRX888;
3221                 break;
3222         case DRM_FORMAT_XBGR8888:
3223                 dspcntr |= DISPPLANE_RGBX888;
3224                 break;
3225         case DRM_FORMAT_XRGB2101010:
3226                 dspcntr |= DISPPLANE_BGRX101010;
3227                 break;
3228         case DRM_FORMAT_XBGR2101010:
3229                 dspcntr |= DISPPLANE_RGBX101010;
3230                 break;
3231         default:
3232                 MISSING_CASE(fb->format->format);
3233                 return 0;
3234         }
3235
3236         if (INTEL_GEN(dev_priv) >= 4 &&
3237             fb->modifier == I915_FORMAT_MOD_X_TILED)
3238                 dspcntr |= DISPPLANE_TILED;
3239
3240         if (rotation & DRM_MODE_ROTATE_180)
3241                 dspcntr |= DISPPLANE_ROTATE_180;
3242
3243         if (rotation & DRM_MODE_REFLECT_X)
3244                 dspcntr |= DISPPLANE_MIRROR;
3245
3246         return dspcntr;
3247 }
3248
3249 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3250 {
3251         struct drm_i915_private *dev_priv =
3252                 to_i915(plane_state->base.plane->dev);
3253         int src_x = plane_state->base.src.x1 >> 16;
3254         int src_y = plane_state->base.src.y1 >> 16;
3255         u32 offset;
3256
3257         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3258
3259         if (INTEL_GEN(dev_priv) >= 4)
3260                 offset = intel_compute_tile_offset(&src_x, &src_y,
3261                                                    plane_state, 0);
3262         else
3263                 offset = 0;
3264
3265         /* HSW/BDW do this automagically in hardware */
3266         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3267                 unsigned int rotation = plane_state->base.rotation;
3268                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3269                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3270
3271                 if (rotation & DRM_MODE_ROTATE_180) {
3272                         src_x += src_w - 1;
3273                         src_y += src_h - 1;
3274                 } else if (rotation & DRM_MODE_REFLECT_X) {
3275                         src_x += src_w - 1;
3276                 }
3277         }
3278
3279         plane_state->main.offset = offset;
3280         plane_state->main.x = src_x;
3281         plane_state->main.y = src_y;
3282
3283         return 0;
3284 }
3285
3286 static void i9xx_update_primary_plane(struct intel_plane *primary,
3287                                       const struct intel_crtc_state *crtc_state,
3288                                       const struct intel_plane_state *plane_state)
3289 {
3290         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3291         const struct drm_framebuffer *fb = plane_state->base.fb;
3292         enum plane plane = primary->plane;
3293         u32 linear_offset;
3294         u32 dspcntr = plane_state->ctl;
3295         i915_reg_t reg = DSPCNTR(plane);
3296         int x = plane_state->main.x;
3297         int y = plane_state->main.y;
3298         unsigned long irqflags;
3299         u32 dspaddr_offset;
3300
3301         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3302
3303         if (INTEL_GEN(dev_priv) >= 4)
3304                 dspaddr_offset = plane_state->main.offset;
3305         else
3306                 dspaddr_offset = linear_offset;
3307
3308         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3309
3310         if (INTEL_GEN(dev_priv) < 4) {
3311                 /* pipesrc and dspsize control the size that is scaled from,
3312                  * which should always be the user's requested size.
3313                  */
3314                 I915_WRITE_FW(DSPSIZE(plane),
3315                               ((crtc_state->pipe_src_h - 1) << 16) |
3316                               (crtc_state->pipe_src_w - 1));
3317                 I915_WRITE_FW(DSPPOS(plane), 0);
3318         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3319                 I915_WRITE_FW(PRIMSIZE(plane),
3320                               ((crtc_state->pipe_src_h - 1) << 16) |
3321                               (crtc_state->pipe_src_w - 1));
3322                 I915_WRITE_FW(PRIMPOS(plane), 0);
3323                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3324         }
3325
3326         I915_WRITE_FW(reg, dspcntr);
3327
3328         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3329         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3330                 I915_WRITE_FW(DSPSURF(plane),
3331                               intel_plane_ggtt_offset(plane_state) +
3332                               dspaddr_offset);
3333                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3334         } else if (INTEL_GEN(dev_priv) >= 4) {
3335                 I915_WRITE_FW(DSPSURF(plane),
3336                               intel_plane_ggtt_offset(plane_state) +
3337                               dspaddr_offset);
3338                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3339                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3340         } else {
3341                 I915_WRITE_FW(DSPADDR(plane),
3342                               intel_plane_ggtt_offset(plane_state) +
3343                               dspaddr_offset);
3344         }
3345         POSTING_READ_FW(reg);
3346
3347         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3348 }
3349
3350 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3351                                        struct intel_crtc *crtc)
3352 {
3353         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3354         enum plane plane = primary->plane;
3355         unsigned long irqflags;
3356
3357         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3358
3359         I915_WRITE_FW(DSPCNTR(plane), 0);
3360         if (INTEL_INFO(dev_priv)->gen >= 4)
3361                 I915_WRITE_FW(DSPSURF(plane), 0);
3362         else
3363                 I915_WRITE_FW(DSPADDR(plane), 0);
3364         POSTING_READ_FW(DSPCNTR(plane));
3365
3366         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3367 }
3368
3369 static u32
3370 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3371 {
3372         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3373                 return 64;
3374         else
3375                 return intel_tile_width_bytes(fb, plane);
3376 }
3377
3378 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3379 {
3380         struct drm_device *dev = intel_crtc->base.dev;
3381         struct drm_i915_private *dev_priv = to_i915(dev);
3382
3383         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3384         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3385         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3386 }
3387
3388 /*
3389  * This function detaches (aka. unbinds) unused scalers in hardware
3390  */
3391 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3392 {
3393         struct intel_crtc_scaler_state *scaler_state;
3394         int i;
3395
3396         scaler_state = &intel_crtc->config->scaler_state;
3397
3398         /* loop through and disable scalers that aren't in use */
3399         for (i = 0; i < intel_crtc->num_scalers; i++) {
3400                 if (!scaler_state->scalers[i].in_use)
3401                         skl_detach_scaler(intel_crtc, i);
3402         }
3403 }
3404
3405 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3406                      unsigned int rotation)
3407 {
3408         u32 stride;
3409
3410         if (plane >= fb->format->num_planes)
3411                 return 0;
3412
3413         stride = intel_fb_pitch(fb, plane, rotation);
3414
3415         /*
3416          * The stride is either expressed as a multiple of 64 bytes chunks for
3417          * linear buffers or in number of tiles for tiled buffers.
3418          */
3419         if (drm_rotation_90_or_270(rotation))
3420                 stride /= intel_tile_height(fb, plane);
3421         else
3422                 stride /= intel_fb_stride_alignment(fb, plane);
3423
3424         return stride;
3425 }
3426
3427 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3428 {
3429         switch (pixel_format) {
3430         case DRM_FORMAT_C8:
3431                 return PLANE_CTL_FORMAT_INDEXED;
3432         case DRM_FORMAT_RGB565:
3433                 return PLANE_CTL_FORMAT_RGB_565;
3434         case DRM_FORMAT_XBGR8888:
3435                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3436         case DRM_FORMAT_XRGB8888:
3437                 return PLANE_CTL_FORMAT_XRGB_8888;
3438         /*
3439          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3440          * to be already pre-multiplied. We need to add a knob (or a different
3441          * DRM_FORMAT) for user-space to configure that.
3442          */
3443         case DRM_FORMAT_ABGR8888:
3444                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3445                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3446         case DRM_FORMAT_ARGB8888:
3447                 return PLANE_CTL_FORMAT_XRGB_8888 |
3448                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3449         case DRM_FORMAT_XRGB2101010:
3450                 return PLANE_CTL_FORMAT_XRGB_2101010;
3451         case DRM_FORMAT_XBGR2101010:
3452                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3453         case DRM_FORMAT_YUYV:
3454                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3455         case DRM_FORMAT_YVYU:
3456                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3457         case DRM_FORMAT_UYVY:
3458                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3459         case DRM_FORMAT_VYUY:
3460                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3461         default:
3462                 MISSING_CASE(pixel_format);
3463         }
3464
3465         return 0;
3466 }
3467
3468 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3469 {
3470         switch (fb_modifier) {
3471         case DRM_FORMAT_MOD_LINEAR:
3472                 break;
3473         case I915_FORMAT_MOD_X_TILED:
3474                 return PLANE_CTL_TILED_X;
3475         case I915_FORMAT_MOD_Y_TILED:
3476                 return PLANE_CTL_TILED_Y;
3477         case I915_FORMAT_MOD_Y_TILED_CCS:
3478                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3479         case I915_FORMAT_MOD_Yf_TILED:
3480                 return PLANE_CTL_TILED_YF;
3481         case I915_FORMAT_MOD_Yf_TILED_CCS:
3482                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3483         default:
3484                 MISSING_CASE(fb_modifier);
3485         }
3486
3487         return 0;
3488 }
3489
3490 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3491 {
3492         switch (rotation) {
3493         case DRM_MODE_ROTATE_0:
3494                 break;
3495         /*
3496          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3497          * while i915 HW rotation is clockwise, thats why this swapping.
3498          */
3499         case DRM_MODE_ROTATE_90:
3500                 return PLANE_CTL_ROTATE_270;
3501         case DRM_MODE_ROTATE_180:
3502                 return PLANE_CTL_ROTATE_180;
3503         case DRM_MODE_ROTATE_270:
3504                 return PLANE_CTL_ROTATE_90;
3505         default:
3506                 MISSING_CASE(rotation);
3507         }
3508
3509         return 0;
3510 }
3511
3512 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3513                   const struct intel_plane_state *plane_state)
3514 {
3515         struct drm_i915_private *dev_priv =
3516                 to_i915(plane_state->base.plane->dev);
3517         const struct drm_framebuffer *fb = plane_state->base.fb;
3518         unsigned int rotation = plane_state->base.rotation;
3519         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3520         u32 plane_ctl;
3521
3522         plane_ctl = PLANE_CTL_ENABLE;
3523
3524         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3525                 plane_ctl |=
3526                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3527                         PLANE_CTL_PIPE_CSC_ENABLE |
3528                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3529         }
3530
3531         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3532         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3533         plane_ctl |= skl_plane_ctl_rotation(rotation);
3534
3535         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3536                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3537         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3538                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3539
3540         return plane_ctl;
3541 }
3542
3543 static int
3544 __intel_display_resume(struct drm_device *dev,
3545                        struct drm_atomic_state *state,
3546                        struct drm_modeset_acquire_ctx *ctx)
3547 {
3548         struct drm_crtc_state *crtc_state;
3549         struct drm_crtc *crtc;
3550         int i, ret;
3551
3552         intel_modeset_setup_hw_state(dev, ctx);
3553         i915_redisable_vga(to_i915(dev));
3554
3555         if (!state)
3556                 return 0;
3557
3558         /*
3559          * We've duplicated the state, pointers to the old state are invalid.
3560          *
3561          * Don't attempt to use the old state until we commit the duplicated state.
3562          */
3563         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3564                 /*
3565                  * Force recalculation even if we restore
3566                  * current state. With fast modeset this may not result
3567                  * in a modeset when the state is compatible.
3568                  */
3569                 crtc_state->mode_changed = true;
3570         }
3571
3572         /* ignore any reset values/BIOS leftovers in the WM registers */
3573         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3574                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3575
3576         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3577
3578         WARN_ON(ret == -EDEADLK);
3579         return ret;
3580 }
3581
3582 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3583 {
3584         return intel_has_gpu_reset(dev_priv) &&
3585                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3586 }
3587
3588 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3589 {
3590         struct drm_device *dev = &dev_priv->drm;
3591         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3592         struct drm_atomic_state *state;
3593         int ret;
3594
3595
3596         /* reset doesn't touch the display */
3597         if (!i915_modparams.force_reset_modeset_test &&
3598             !gpu_reset_clobbers_display(dev_priv))
3599                 return;
3600
3601         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3602         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3603         wake_up_all(&dev_priv->gpu_error.wait_queue);
3604
3605         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3606                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3607                 i915_gem_set_wedged(dev_priv);
3608         }
3609
3610         /*
3611          * Need mode_config.mutex so that we don't
3612          * trample ongoing ->detect() and whatnot.
3613          */
3614         mutex_lock(&dev->mode_config.mutex);
3615         drm_modeset_acquire_init(ctx, 0);
3616         while (1) {
3617                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3618                 if (ret != -EDEADLK)
3619                         break;
3620
3621                 drm_modeset_backoff(ctx);
3622         }
3623         /*
3624          * Disabling the crtcs gracefully seems nicer. Also the
3625          * g33 docs say we should at least disable all the planes.
3626          */
3627         state = drm_atomic_helper_duplicate_state(dev, ctx);
3628         if (IS_ERR(state)) {
3629                 ret = PTR_ERR(state);
3630                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3631                 return;
3632         }
3633
3634         ret = drm_atomic_helper_disable_all(dev, ctx);
3635         if (ret) {
3636                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3637                 drm_atomic_state_put(state);
3638                 return;
3639         }
3640
3641         dev_priv->modeset_restore_state = state;
3642         state->acquire_ctx = ctx;
3643 }
3644
3645 void intel_finish_reset(struct drm_i915_private *dev_priv)
3646 {
3647         struct drm_device *dev = &dev_priv->drm;
3648         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3649         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3650         int ret;
3651
3652         /* reset doesn't touch the display */
3653         if (!i915_modparams.force_reset_modeset_test &&
3654             !gpu_reset_clobbers_display(dev_priv))
3655                 return;
3656
3657         if (!state)
3658                 goto unlock;
3659
3660         dev_priv->modeset_restore_state = NULL;
3661
3662         /* reset doesn't touch the display */
3663         if (!gpu_reset_clobbers_display(dev_priv)) {
3664                 /* for testing only restore the display */
3665                 ret = __intel_display_resume(dev, state, ctx);
3666                 if (ret)
3667                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3668         } else {
3669                 /*
3670                  * The display has been reset as well,
3671                  * so need a full re-initialization.
3672                  */
3673                 intel_runtime_pm_disable_interrupts(dev_priv);
3674                 intel_runtime_pm_enable_interrupts(dev_priv);
3675
3676                 intel_pps_unlock_regs_wa(dev_priv);
3677                 intel_modeset_init_hw(dev);
3678                 intel_init_clock_gating(dev_priv);
3679
3680                 spin_lock_irq(&dev_priv->irq_lock);
3681                 if (dev_priv->display.hpd_irq_setup)
3682                         dev_priv->display.hpd_irq_setup(dev_priv);
3683                 spin_unlock_irq(&dev_priv->irq_lock);
3684
3685                 ret = __intel_display_resume(dev, state, ctx);
3686                 if (ret)
3687                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3688
3689                 intel_hpd_init(dev_priv);
3690         }
3691
3692         drm_atomic_state_put(state);
3693 unlock:
3694         drm_modeset_drop_locks(ctx);
3695         drm_modeset_acquire_fini(ctx);
3696         mutex_unlock(&dev->mode_config.mutex);
3697
3698         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3699 }
3700
3701 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3702                                      const struct intel_crtc_state *new_crtc_state)
3703 {
3704         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3705         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3706
3707         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3708         crtc->base.mode = new_crtc_state->base.mode;
3709
3710         /*
3711          * Update pipe size and adjust fitter if needed: the reason for this is
3712          * that in compute_mode_changes we check the native mode (not the pfit
3713          * mode) to see if we can flip rather than do a full mode set. In the
3714          * fastboot case, we'll flip, but if we don't update the pipesrc and
3715          * pfit state, we'll end up with a big fb scanned out into the wrong
3716          * sized surface.
3717          */
3718
3719         I915_WRITE(PIPESRC(crtc->pipe),
3720                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3721                    (new_crtc_state->pipe_src_h - 1));
3722
3723         /* on skylake this is done by detaching scalers */
3724         if (INTEL_GEN(dev_priv) >= 9) {
3725                 skl_detach_scalers(crtc);
3726
3727                 if (new_crtc_state->pch_pfit.enabled)
3728                         skylake_pfit_enable(crtc);
3729         } else if (HAS_PCH_SPLIT(dev_priv)) {
3730                 if (new_crtc_state->pch_pfit.enabled)
3731                         ironlake_pfit_enable(crtc);
3732                 else if (old_crtc_state->pch_pfit.enabled)
3733                         ironlake_pfit_disable(crtc, true);
3734         }
3735 }
3736
3737 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->base.dev;
3740         struct drm_i915_private *dev_priv = to_i915(dev);
3741         int pipe = crtc->pipe;
3742         i915_reg_t reg;
3743         u32 temp;
3744
3745         /* enable normal train */
3746         reg = FDI_TX_CTL(pipe);
3747         temp = I915_READ(reg);
3748         if (IS_IVYBRIDGE(dev_priv)) {
3749                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3750                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3751         } else {
3752                 temp &= ~FDI_LINK_TRAIN_NONE;
3753                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3754         }
3755         I915_WRITE(reg, temp);
3756
3757         reg = FDI_RX_CTL(pipe);
3758         temp = I915_READ(reg);
3759         if (HAS_PCH_CPT(dev_priv)) {
3760                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3761                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3762         } else {
3763                 temp &= ~FDI_LINK_TRAIN_NONE;
3764                 temp |= FDI_LINK_TRAIN_NONE;
3765         }
3766         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3767
3768         /* wait one idle pattern time */
3769         POSTING_READ(reg);
3770         udelay(1000);
3771
3772         /* IVB wants error correction enabled */
3773         if (IS_IVYBRIDGE(dev_priv))
3774                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3775                            FDI_FE_ERRC_ENABLE);
3776 }
3777
3778 /* The FDI link training functions for ILK/Ibexpeak. */
3779 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3780                                     const struct intel_crtc_state *crtc_state)
3781 {
3782         struct drm_device *dev = crtc->base.dev;
3783         struct drm_i915_private *dev_priv = to_i915(dev);
3784         int pipe = crtc->pipe;
3785         i915_reg_t reg;
3786         u32 temp, tries;
3787
3788         /* FDI needs bits from pipe first */
3789         assert_pipe_enabled(dev_priv, pipe);
3790
3791         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3792            for train result */
3793         reg = FDI_RX_IMR(pipe);
3794         temp = I915_READ(reg);
3795         temp &= ~FDI_RX_SYMBOL_LOCK;
3796         temp &= ~FDI_RX_BIT_LOCK;
3797         I915_WRITE(reg, temp);
3798         I915_READ(reg);
3799         udelay(150);
3800
3801         /* enable CPU FDI TX and PCH FDI RX */
3802         reg = FDI_TX_CTL(pipe);
3803         temp = I915_READ(reg);
3804         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3805         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3806         temp &= ~FDI_LINK_TRAIN_NONE;
3807         temp |= FDI_LINK_TRAIN_PATTERN_1;
3808         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3809
3810         reg = FDI_RX_CTL(pipe);
3811         temp = I915_READ(reg);
3812         temp &= ~FDI_LINK_TRAIN_NONE;
3813         temp |= FDI_LINK_TRAIN_PATTERN_1;
3814         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3815
3816         POSTING_READ(reg);
3817         udelay(150);
3818
3819         /* Ironlake workaround, enable clock pointer after FDI enable*/
3820         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3821         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3822                    FDI_RX_PHASE_SYNC_POINTER_EN);
3823
3824         reg = FDI_RX_IIR(pipe);
3825         for (tries = 0; tries < 5; tries++) {
3826                 temp = I915_READ(reg);
3827                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3828
3829                 if ((temp & FDI_RX_BIT_LOCK)) {
3830                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3831                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3832                         break;
3833                 }
3834         }
3835         if (tries == 5)
3836                 DRM_ERROR("FDI train 1 fail!\n");
3837
3838         /* Train 2 */
3839         reg = FDI_TX_CTL(pipe);
3840         temp = I915_READ(reg);
3841         temp &= ~FDI_LINK_TRAIN_NONE;
3842         temp |= FDI_LINK_TRAIN_PATTERN_2;
3843         I915_WRITE(reg, temp);
3844
3845         reg = FDI_RX_CTL(pipe);
3846         temp = I915_READ(reg);
3847         temp &= ~FDI_LINK_TRAIN_NONE;
3848         temp |= FDI_LINK_TRAIN_PATTERN_2;
3849         I915_WRITE(reg, temp);
3850
3851         POSTING_READ(reg);
3852         udelay(150);
3853
3854         reg = FDI_RX_IIR(pipe);
3855         for (tries = 0; tries < 5; tries++) {
3856                 temp = I915_READ(reg);
3857                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3858
3859                 if (temp & FDI_RX_SYMBOL_LOCK) {
3860                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3861                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3862                         break;
3863                 }
3864         }
3865         if (tries == 5)
3866                 DRM_ERROR("FDI train 2 fail!\n");
3867
3868         DRM_DEBUG_KMS("FDI train done\n");
3869
3870 }
3871
3872 static const int snb_b_fdi_train_param[] = {
3873         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3874         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3875         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3876         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3877 };
3878
3879 /* The FDI link training functions for SNB/Cougarpoint. */
3880 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3881                                 const struct intel_crtc_state *crtc_state)
3882 {
3883         struct drm_device *dev = crtc->base.dev;
3884         struct drm_i915_private *dev_priv = to_i915(dev);
3885         int pipe = crtc->pipe;
3886         i915_reg_t reg;
3887         u32 temp, i, retry;
3888
3889         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3890            for train result */
3891         reg = FDI_RX_IMR(pipe);
3892         temp = I915_READ(reg);
3893         temp &= ~FDI_RX_SYMBOL_LOCK;
3894         temp &= ~FDI_RX_BIT_LOCK;
3895         I915_WRITE(reg, temp);
3896
3897         POSTING_READ(reg);
3898         udelay(150);
3899
3900         /* enable CPU FDI TX and PCH FDI RX */
3901         reg = FDI_TX_CTL(pipe);
3902         temp = I915_READ(reg);
3903         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3904         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3905         temp &= ~FDI_LINK_TRAIN_NONE;
3906         temp |= FDI_LINK_TRAIN_PATTERN_1;
3907         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3908         /* SNB-B */
3909         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3910         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3911
3912         I915_WRITE(FDI_RX_MISC(pipe),
3913                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3914
3915         reg = FDI_RX_CTL(pipe);
3916         temp = I915_READ(reg);
3917         if (HAS_PCH_CPT(dev_priv)) {
3918                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3919                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3920         } else {
3921                 temp &= ~FDI_LINK_TRAIN_NONE;
3922                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3923         }
3924         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3925
3926         POSTING_READ(reg);
3927         udelay(150);
3928
3929         for (i = 0; i < 4; i++) {
3930                 reg = FDI_TX_CTL(pipe);
3931                 temp = I915_READ(reg);
3932                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3933                 temp |= snb_b_fdi_train_param[i];
3934                 I915_WRITE(reg, temp);
3935
3936                 POSTING_READ(reg);
3937                 udelay(500);
3938
3939                 for (retry = 0; retry < 5; retry++) {
3940                         reg = FDI_RX_IIR(pipe);
3941                         temp = I915_READ(reg);
3942                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3943                         if (temp & FDI_RX_BIT_LOCK) {
3944                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3945                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3946                                 break;
3947                         }
3948                         udelay(50);
3949                 }
3950                 if (retry < 5)
3951                         break;
3952         }
3953         if (i == 4)
3954                 DRM_ERROR("FDI train 1 fail!\n");
3955
3956         /* Train 2 */
3957         reg = FDI_TX_CTL(pipe);
3958         temp = I915_READ(reg);
3959         temp &= ~FDI_LINK_TRAIN_NONE;
3960         temp |= FDI_LINK_TRAIN_PATTERN_2;
3961         if (IS_GEN6(dev_priv)) {
3962                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3963                 /* SNB-B */
3964                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3965         }
3966         I915_WRITE(reg, temp);
3967
3968         reg = FDI_RX_CTL(pipe);
3969         temp = I915_READ(reg);
3970         if (HAS_PCH_CPT(dev_priv)) {
3971                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3972                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3973         } else {
3974                 temp &= ~FDI_LINK_TRAIN_NONE;
3975                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3976         }
3977         I915_WRITE(reg, temp);
3978
3979         POSTING_READ(reg);
3980         udelay(150);
3981
3982         for (i = 0; i < 4; i++) {
3983                 reg = FDI_TX_CTL(pipe);
3984                 temp = I915_READ(reg);
3985                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3986                 temp |= snb_b_fdi_train_param[i];
3987                 I915_WRITE(reg, temp);
3988
3989                 POSTING_READ(reg);
3990                 udelay(500);
3991
3992                 for (retry = 0; retry < 5; retry++) {
3993                         reg = FDI_RX_IIR(pipe);
3994                         temp = I915_READ(reg);
3995                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3996                         if (temp & FDI_RX_SYMBOL_LOCK) {
3997                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3998                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3999                                 break;
4000                         }
4001                         udelay(50);
4002                 }
4003                 if (retry < 5)
4004                         break;
4005         }
4006         if (i == 4)
4007                 DRM_ERROR("FDI train 2 fail!\n");
4008
4009         DRM_DEBUG_KMS("FDI train done.\n");
4010 }
4011
4012 /* Manual link training for Ivy Bridge A0 parts */
4013 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4014                                       const struct intel_crtc_state *crtc_state)
4015 {
4016         struct drm_device *dev = crtc->base.dev;
4017         struct drm_i915_private *dev_priv = to_i915(dev);
4018         int pipe = crtc->pipe;
4019         i915_reg_t reg;
4020         u32 temp, i, j;
4021
4022         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4023            for train result */
4024         reg = FDI_RX_IMR(pipe);
4025         temp = I915_READ(reg);
4026         temp &= ~FDI_RX_SYMBOL_LOCK;
4027         temp &= ~FDI_RX_BIT_LOCK;
4028         I915_WRITE(reg, temp);
4029
4030         POSTING_READ(reg);
4031         udelay(150);
4032
4033         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4034                       I915_READ(FDI_RX_IIR(pipe)));
4035
4036         /* Try each vswing and preemphasis setting twice before moving on */
4037         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4038                 /* disable first in case we need to retry */
4039                 reg = FDI_TX_CTL(pipe);
4040                 temp = I915_READ(reg);
4041                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4042                 temp &= ~FDI_TX_ENABLE;
4043                 I915_WRITE(reg, temp);
4044
4045                 reg = FDI_RX_CTL(pipe);
4046                 temp = I915_READ(reg);
4047                 temp &= ~FDI_LINK_TRAIN_AUTO;
4048                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4049                 temp &= ~FDI_RX_ENABLE;
4050                 I915_WRITE(reg, temp);
4051
4052                 /* enable CPU FDI TX and PCH FDI RX */
4053                 reg = FDI_TX_CTL(pipe);
4054                 temp = I915_READ(reg);
4055                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4056                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4057                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4058                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4059                 temp |= snb_b_fdi_train_param[j/2];
4060                 temp |= FDI_COMPOSITE_SYNC;
4061                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4062
4063                 I915_WRITE(FDI_RX_MISC(pipe),
4064                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4065
4066                 reg = FDI_RX_CTL(pipe);
4067                 temp = I915_READ(reg);
4068                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4069                 temp |= FDI_COMPOSITE_SYNC;
4070                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4071
4072                 POSTING_READ(reg);
4073                 udelay(1); /* should be 0.5us */
4074
4075                 for (i = 0; i < 4; i++) {
4076                         reg = FDI_RX_IIR(pipe);
4077                         temp = I915_READ(reg);
4078                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4079
4080                         if (temp & FDI_RX_BIT_LOCK ||
4081                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4082                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4083                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4084                                               i);
4085                                 break;
4086                         }
4087                         udelay(1); /* should be 0.5us */
4088                 }
4089                 if (i == 4) {
4090                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4091                         continue;
4092                 }
4093
4094                 /* Train 2 */
4095                 reg = FDI_TX_CTL(pipe);
4096                 temp = I915_READ(reg);
4097                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4098                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4099                 I915_WRITE(reg, temp);
4100
4101                 reg = FDI_RX_CTL(pipe);
4102                 temp = I915_READ(reg);
4103                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4104                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4105                 I915_WRITE(reg, temp);
4106
4107                 POSTING_READ(reg);
4108                 udelay(2); /* should be 1.5us */
4109
4110                 for (i = 0; i < 4; i++) {
4111                         reg = FDI_RX_IIR(pipe);
4112                         temp = I915_READ(reg);
4113                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4114
4115                         if (temp & FDI_RX_SYMBOL_LOCK ||
4116                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4117                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4118                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4119                                               i);
4120                                 goto train_done;
4121                         }
4122                         udelay(2); /* should be 1.5us */
4123                 }
4124                 if (i == 4)
4125                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4126         }
4127
4128 train_done:
4129         DRM_DEBUG_KMS("FDI train done.\n");
4130 }
4131
4132 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4133 {
4134         struct drm_device *dev = intel_crtc->base.dev;
4135         struct drm_i915_private *dev_priv = to_i915(dev);
4136         int pipe = intel_crtc->pipe;
4137         i915_reg_t reg;
4138         u32 temp;
4139
4140         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4141         reg = FDI_RX_CTL(pipe);
4142         temp = I915_READ(reg);
4143         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4144         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4145         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4146         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4147
4148         POSTING_READ(reg);
4149         udelay(200);
4150
4151         /* Switch from Rawclk to PCDclk */
4152         temp = I915_READ(reg);
4153         I915_WRITE(reg, temp | FDI_PCDCLK);
4154
4155         POSTING_READ(reg);
4156         udelay(200);
4157
4158         /* Enable CPU FDI TX PLL, always on for Ironlake */
4159         reg = FDI_TX_CTL(pipe);
4160         temp = I915_READ(reg);
4161         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4162                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4163
4164                 POSTING_READ(reg);
4165                 udelay(100);
4166         }
4167 }
4168
4169 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4170 {
4171         struct drm_device *dev = intel_crtc->base.dev;
4172         struct drm_i915_private *dev_priv = to_i915(dev);
4173         int pipe = intel_crtc->pipe;
4174         i915_reg_t reg;
4175         u32 temp;
4176
4177         /* Switch from PCDclk to Rawclk */
4178         reg = FDI_RX_CTL(pipe);
4179         temp = I915_READ(reg);
4180         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4181
4182         /* Disable CPU FDI TX PLL */
4183         reg = FDI_TX_CTL(pipe);
4184         temp = I915_READ(reg);
4185         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4186
4187         POSTING_READ(reg);
4188         udelay(100);
4189
4190         reg = FDI_RX_CTL(pipe);
4191         temp = I915_READ(reg);
4192         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4193
4194         /* Wait for the clocks to turn off. */
4195         POSTING_READ(reg);
4196         udelay(100);
4197 }
4198
4199 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = to_i915(dev);
4203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4204         int pipe = intel_crtc->pipe;
4205         i915_reg_t reg;
4206         u32 temp;
4207
4208         /* disable CPU FDI tx and PCH FDI rx */
4209         reg = FDI_TX_CTL(pipe);
4210         temp = I915_READ(reg);
4211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4212         POSTING_READ(reg);
4213
4214         reg = FDI_RX_CTL(pipe);
4215         temp = I915_READ(reg);
4216         temp &= ~(0x7 << 16);
4217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4219
4220         POSTING_READ(reg);
4221         udelay(100);
4222
4223         /* Ironlake workaround, disable clock pointer after downing FDI */
4224         if (HAS_PCH_IBX(dev_priv))
4225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4226
4227         /* still set train pattern 1 */
4228         reg = FDI_TX_CTL(pipe);
4229         temp = I915_READ(reg);
4230         temp &= ~FDI_LINK_TRAIN_NONE;
4231         temp |= FDI_LINK_TRAIN_PATTERN_1;
4232         I915_WRITE(reg, temp);
4233
4234         reg = FDI_RX_CTL(pipe);
4235         temp = I915_READ(reg);
4236         if (HAS_PCH_CPT(dev_priv)) {
4237                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4238                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4239         } else {
4240                 temp &= ~FDI_LINK_TRAIN_NONE;
4241                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4242         }
4243         /* BPC in FDI rx is consistent with that in PIPECONF */
4244         temp &= ~(0x07 << 16);
4245         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4246         I915_WRITE(reg, temp);
4247
4248         POSTING_READ(reg);
4249         udelay(100);
4250 }
4251
4252 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4253 {
4254         struct drm_crtc *crtc;
4255         bool cleanup_done;
4256
4257         drm_for_each_crtc(crtc, &dev_priv->drm) {
4258                 struct drm_crtc_commit *commit;
4259                 spin_lock(&crtc->commit_lock);
4260                 commit = list_first_entry_or_null(&crtc->commit_list,
4261                                                   struct drm_crtc_commit, commit_entry);
4262                 cleanup_done = commit ?
4263                         try_wait_for_completion(&commit->cleanup_done) : true;
4264                 spin_unlock(&crtc->commit_lock);
4265
4266                 if (cleanup_done)
4267                         continue;
4268
4269                 drm_crtc_wait_one_vblank(crtc);
4270
4271                 return true;
4272         }
4273
4274         return false;
4275 }
4276
4277 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4278 {
4279         u32 temp;
4280
4281         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4282
4283         mutex_lock(&dev_priv->sb_lock);
4284
4285         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4286         temp |= SBI_SSCCTL_DISABLE;
4287         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4288
4289         mutex_unlock(&dev_priv->sb_lock);
4290 }
4291
4292 /* Program iCLKIP clock to the desired frequency */
4293 static void lpt_program_iclkip(struct intel_crtc *crtc)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4296         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4297         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4298         u32 temp;
4299
4300         lpt_disable_iclkip(dev_priv);
4301
4302         /* The iCLK virtual clock root frequency is in MHz,
4303          * but the adjusted_mode->crtc_clock in in KHz. To get the
4304          * divisors, it is necessary to divide one by another, so we
4305          * convert the virtual clock precision to KHz here for higher
4306          * precision.
4307          */
4308         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4309                 u32 iclk_virtual_root_freq = 172800 * 1000;
4310                 u32 iclk_pi_range = 64;
4311                 u32 desired_divisor;
4312
4313                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4314                                                     clock << auxdiv);
4315                 divsel = (desired_divisor / iclk_pi_range) - 2;
4316                 phaseinc = desired_divisor % iclk_pi_range;
4317
4318                 /*
4319                  * Near 20MHz is a corner case which is
4320                  * out of range for the 7-bit divisor
4321                  */
4322                 if (divsel <= 0x7f)
4323                         break;
4324         }
4325
4326         /* This should not happen with any sane values */
4327         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4328                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4329         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4330                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4331
4332         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4333                         clock,
4334                         auxdiv,
4335                         divsel,
4336                         phasedir,
4337                         phaseinc);
4338
4339         mutex_lock(&dev_priv->sb_lock);
4340
4341         /* Program SSCDIVINTPHASE6 */
4342         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4343         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4344         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4345         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4346         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4347         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4348         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4349         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4350
4351         /* Program SSCAUXDIV */
4352         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4353         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4354         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4355         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4356
4357         /* Enable modulator and associated divider */
4358         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4359         temp &= ~SBI_SSCCTL_DISABLE;
4360         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4361
4362         mutex_unlock(&dev_priv->sb_lock);
4363
4364         /* Wait for initialization time */
4365         udelay(24);
4366
4367         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4368 }
4369
4370 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4371 {
4372         u32 divsel, phaseinc, auxdiv;
4373         u32 iclk_virtual_root_freq = 172800 * 1000;
4374         u32 iclk_pi_range = 64;
4375         u32 desired_divisor;
4376         u32 temp;
4377
4378         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4379                 return 0;
4380
4381         mutex_lock(&dev_priv->sb_lock);
4382
4383         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4384         if (temp & SBI_SSCCTL_DISABLE) {
4385                 mutex_unlock(&dev_priv->sb_lock);
4386                 return 0;
4387         }
4388
4389         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4390         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4391                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4392         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4393                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4394
4395         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4396         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4397                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4398
4399         mutex_unlock(&dev_priv->sb_lock);
4400
4401         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4402
4403         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4404                                  desired_divisor << auxdiv);
4405 }
4406
4407 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4408                                                 enum pipe pch_transcoder)
4409 {
4410         struct drm_device *dev = crtc->base.dev;
4411         struct drm_i915_private *dev_priv = to_i915(dev);
4412         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4413
4414         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4415                    I915_READ(HTOTAL(cpu_transcoder)));
4416         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4417                    I915_READ(HBLANK(cpu_transcoder)));
4418         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4419                    I915_READ(HSYNC(cpu_transcoder)));
4420
4421         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4422                    I915_READ(VTOTAL(cpu_transcoder)));
4423         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4424                    I915_READ(VBLANK(cpu_transcoder)));
4425         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4426                    I915_READ(VSYNC(cpu_transcoder)));
4427         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4428                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4429 }
4430
4431 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4432 {
4433         struct drm_i915_private *dev_priv = to_i915(dev);
4434         uint32_t temp;
4435
4436         temp = I915_READ(SOUTH_CHICKEN1);
4437         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4438                 return;
4439
4440         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4441         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4442
4443         temp &= ~FDI_BC_BIFURCATION_SELECT;
4444         if (enable)
4445                 temp |= FDI_BC_BIFURCATION_SELECT;
4446
4447         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4448         I915_WRITE(SOUTH_CHICKEN1, temp);
4449         POSTING_READ(SOUTH_CHICKEN1);
4450 }
4451
4452 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4453 {
4454         struct drm_device *dev = intel_crtc->base.dev;
4455
4456         switch (intel_crtc->pipe) {
4457         case PIPE_A:
4458                 break;
4459         case PIPE_B:
4460                 if (intel_crtc->config->fdi_lanes > 2)
4461                         cpt_set_fdi_bc_bifurcation(dev, false);
4462                 else
4463                         cpt_set_fdi_bc_bifurcation(dev, true);
4464
4465                 break;
4466         case PIPE_C:
4467                 cpt_set_fdi_bc_bifurcation(dev, true);
4468
4469                 break;
4470         default:
4471                 BUG();
4472         }
4473 }
4474
4475 /* Return which DP Port should be selected for Transcoder DP control */
4476 static enum port
4477 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4478 {
4479         struct drm_device *dev = crtc->base.dev;
4480         struct intel_encoder *encoder;
4481
4482         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4483                 if (encoder->type == INTEL_OUTPUT_DP ||
4484                     encoder->type == INTEL_OUTPUT_EDP)
4485                         return encoder->port;
4486         }
4487
4488         return -1;
4489 }
4490
4491 /*
4492  * Enable PCH resources required for PCH ports:
4493  *   - PCH PLLs
4494  *   - FDI training & RX/TX
4495  *   - update transcoder timings
4496  *   - DP transcoding bits
4497  *   - transcoder
4498  */
4499 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4500 {
4501         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4502         struct drm_device *dev = crtc->base.dev;
4503         struct drm_i915_private *dev_priv = to_i915(dev);
4504         int pipe = crtc->pipe;
4505         u32 temp;
4506
4507         assert_pch_transcoder_disabled(dev_priv, pipe);
4508
4509         if (IS_IVYBRIDGE(dev_priv))
4510                 ivybridge_update_fdi_bc_bifurcation(crtc);
4511
4512         /* Write the TU size bits before fdi link training, so that error
4513          * detection works. */
4514         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4515                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4516
4517         /* For PCH output, training FDI link */
4518         dev_priv->display.fdi_link_train(crtc, crtc_state);
4519
4520         /* We need to program the right clock selection before writing the pixel
4521          * mutliplier into the DPLL. */
4522         if (HAS_PCH_CPT(dev_priv)) {
4523                 u32 sel;
4524
4525                 temp = I915_READ(PCH_DPLL_SEL);
4526                 temp |= TRANS_DPLL_ENABLE(pipe);
4527                 sel = TRANS_DPLLB_SEL(pipe);
4528                 if (crtc_state->shared_dpll ==
4529                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4530                         temp |= sel;
4531                 else
4532                         temp &= ~sel;
4533                 I915_WRITE(PCH_DPLL_SEL, temp);
4534         }
4535
4536         /* XXX: pch pll's can be enabled any time before we enable the PCH
4537          * transcoder, and we actually should do this to not upset any PCH
4538          * transcoder that already use the clock when we share it.
4539          *
4540          * Note that enable_shared_dpll tries to do the right thing, but
4541          * get_shared_dpll unconditionally resets the pll - we need that to have
4542          * the right LVDS enable sequence. */
4543         intel_enable_shared_dpll(crtc);
4544
4545         /* set transcoder timing, panel must allow it */
4546         assert_panel_unlocked(dev_priv, pipe);
4547         ironlake_pch_transcoder_set_timings(crtc, pipe);
4548
4549         intel_fdi_normal_train(crtc);
4550
4551         /* For PCH DP, enable TRANS_DP_CTL */
4552         if (HAS_PCH_CPT(dev_priv) &&
4553             intel_crtc_has_dp_encoder(crtc_state)) {
4554                 const struct drm_display_mode *adjusted_mode =
4555                         &crtc_state->base.adjusted_mode;
4556                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4557                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4558                 temp = I915_READ(reg);
4559                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4560                           TRANS_DP_SYNC_MASK |
4561                           TRANS_DP_BPC_MASK);
4562                 temp |= TRANS_DP_OUTPUT_ENABLE;
4563                 temp |= bpc << 9; /* same format but at 11:9 */
4564
4565                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4566                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4567                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4568                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4569
4570                 switch (intel_trans_dp_port_sel(crtc)) {
4571                 case PORT_B:
4572                         temp |= TRANS_DP_PORT_SEL_B;
4573                         break;
4574                 case PORT_C:
4575                         temp |= TRANS_DP_PORT_SEL_C;
4576                         break;
4577                 case PORT_D:
4578                         temp |= TRANS_DP_PORT_SEL_D;
4579                         break;
4580                 default:
4581                         BUG();
4582                 }
4583
4584                 I915_WRITE(reg, temp);
4585         }
4586
4587         ironlake_enable_pch_transcoder(dev_priv, pipe);
4588 }
4589
4590 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4591 {
4592         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4594         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4595
4596         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4597
4598         lpt_program_iclkip(crtc);
4599
4600         /* Set transcoder timing. */
4601         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4602
4603         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4604 }
4605
4606 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4607 {
4608         struct drm_i915_private *dev_priv = to_i915(dev);
4609         i915_reg_t dslreg = PIPEDSL(pipe);
4610         u32 temp;
4611
4612         temp = I915_READ(dslreg);
4613         udelay(500);
4614         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4615                 if (wait_for(I915_READ(dslreg) != temp, 5))
4616                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4617         }
4618 }
4619
4620 static int
4621 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4622                   unsigned int scaler_user, int *scaler_id,
4623                   int src_w, int src_h, int dst_w, int dst_h)
4624 {
4625         struct intel_crtc_scaler_state *scaler_state =
4626                 &crtc_state->scaler_state;
4627         struct intel_crtc *intel_crtc =
4628                 to_intel_crtc(crtc_state->base.crtc);
4629         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4630         const struct drm_display_mode *adjusted_mode =
4631                 &crtc_state->base.adjusted_mode;
4632         int need_scaling;
4633
4634         /*
4635          * Src coordinates are already rotated by 270 degrees for
4636          * the 90/270 degree plane rotation cases (to match the
4637          * GTT mapping), hence no need to account for rotation here.
4638          */
4639         need_scaling = src_w != dst_w || src_h != dst_h;
4640
4641         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4642                 need_scaling = true;
4643
4644         /*
4645          * Scaling/fitting not supported in IF-ID mode in GEN9+
4646          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4647          * Once NV12 is enabled, handle it here while allocating scaler
4648          * for NV12.
4649          */
4650         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4651             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4653                 return -EINVAL;
4654         }
4655
4656         /*
4657          * if plane is being disabled or scaler is no more required or force detach
4658          *  - free scaler binded to this plane/crtc
4659          *  - in order to do this, update crtc->scaler_usage
4660          *
4661          * Here scaler state in crtc_state is set free so that
4662          * scaler can be assigned to other user. Actual register
4663          * update to free the scaler is done in plane/panel-fit programming.
4664          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4665          */
4666         if (force_detach || !need_scaling) {
4667                 if (*scaler_id >= 0) {
4668                         scaler_state->scaler_users &= ~(1 << scaler_user);
4669                         scaler_state->scalers[*scaler_id].in_use = 0;
4670
4671                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4672                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4673                                 intel_crtc->pipe, scaler_user, *scaler_id,
4674                                 scaler_state->scaler_users);
4675                         *scaler_id = -1;
4676                 }
4677                 return 0;
4678         }
4679
4680         /* range checks */
4681         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4682                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4683
4684                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4685                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4686                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4687                         "size is out of scaler range\n",
4688                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4689                 return -EINVAL;
4690         }
4691
4692         /* mark this plane as a scaler user in crtc_state */
4693         scaler_state->scaler_users |= (1 << scaler_user);
4694         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4695                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4696                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4697                 scaler_state->scaler_users);
4698
4699         return 0;
4700 }
4701
4702 /**
4703  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4704  *
4705  * @state: crtc's scaler state
4706  *
4707  * Return
4708  *     0 - scaler_usage updated successfully
4709  *    error - requested scaling cannot be supported or other error condition
4710  */
4711 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4712 {
4713         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4714
4715         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4716                 &state->scaler_state.scaler_id,
4717                 state->pipe_src_w, state->pipe_src_h,
4718                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4719 }
4720
4721 /**
4722  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4723  *
4724  * @state: crtc's scaler state
4725  * @plane_state: atomic plane state to update
4726  *
4727  * Return
4728  *     0 - scaler_usage updated successfully
4729  *    error - requested scaling cannot be supported or other error condition
4730  */
4731 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4732                                    struct intel_plane_state *plane_state)
4733 {
4734
4735         struct intel_plane *intel_plane =
4736                 to_intel_plane(plane_state->base.plane);
4737         struct drm_framebuffer *fb = plane_state->base.fb;
4738         int ret;
4739
4740         bool force_detach = !fb || !plane_state->base.visible;
4741
4742         ret = skl_update_scaler(crtc_state, force_detach,
4743                                 drm_plane_index(&intel_plane->base),
4744                                 &plane_state->scaler_id,
4745                                 drm_rect_width(&plane_state->base.src) >> 16,
4746                                 drm_rect_height(&plane_state->base.src) >> 16,
4747                                 drm_rect_width(&plane_state->base.dst),
4748                                 drm_rect_height(&plane_state->base.dst));
4749
4750         if (ret || plane_state->scaler_id < 0)
4751                 return ret;
4752
4753         /* check colorkey */
4754         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4755                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4756                               intel_plane->base.base.id,
4757                               intel_plane->base.name);
4758                 return -EINVAL;
4759         }
4760
4761         /* Check src format */
4762         switch (fb->format->format) {
4763         case DRM_FORMAT_RGB565:
4764         case DRM_FORMAT_XBGR8888:
4765         case DRM_FORMAT_XRGB8888:
4766         case DRM_FORMAT_ABGR8888:
4767         case DRM_FORMAT_ARGB8888:
4768         case DRM_FORMAT_XRGB2101010:
4769         case DRM_FORMAT_XBGR2101010:
4770         case DRM_FORMAT_YUYV:
4771         case DRM_FORMAT_YVYU:
4772         case DRM_FORMAT_UYVY:
4773         case DRM_FORMAT_VYUY:
4774                 break;
4775         default:
4776                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4777                               intel_plane->base.base.id, intel_plane->base.name,
4778                               fb->base.id, fb->format->format);
4779                 return -EINVAL;
4780         }
4781
4782         return 0;
4783 }
4784
4785 static void skylake_scaler_disable(struct intel_crtc *crtc)
4786 {
4787         int i;
4788
4789         for (i = 0; i < crtc->num_scalers; i++)
4790                 skl_detach_scaler(crtc, i);
4791 }
4792
4793 static void skylake_pfit_enable(struct intel_crtc *crtc)
4794 {
4795         struct drm_device *dev = crtc->base.dev;
4796         struct drm_i915_private *dev_priv = to_i915(dev);
4797         int pipe = crtc->pipe;
4798         struct intel_crtc_scaler_state *scaler_state =
4799                 &crtc->config->scaler_state;
4800
4801         if (crtc->config->pch_pfit.enabled) {
4802                 int id;
4803
4804                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4805                         return;
4806
4807                 id = scaler_state->scaler_id;
4808                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4809                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4810                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4811                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4812         }
4813 }
4814
4815 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4816 {
4817         struct drm_device *dev = crtc->base.dev;
4818         struct drm_i915_private *dev_priv = to_i915(dev);
4819         int pipe = crtc->pipe;
4820
4821         if (crtc->config->pch_pfit.enabled) {
4822                 /* Force use of hard-coded filter coefficients
4823                  * as some pre-programmed values are broken,
4824                  * e.g. x201.
4825                  */
4826                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4827                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4828                                                  PF_PIPE_SEL_IVB(pipe));
4829                 else
4830                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4831                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4832                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4833         }
4834 }
4835
4836 void hsw_enable_ips(struct intel_crtc *crtc)
4837 {
4838         struct drm_device *dev = crtc->base.dev;
4839         struct drm_i915_private *dev_priv = to_i915(dev);
4840
4841         if (!crtc->config->ips_enabled)
4842                 return;
4843
4844         /*
4845          * We can only enable IPS after we enable a plane and wait for a vblank
4846          * This function is called from post_plane_update, which is run after
4847          * a vblank wait.
4848          */
4849
4850         assert_plane_enabled(dev_priv, crtc->plane);
4851         if (IS_BROADWELL(dev_priv)) {
4852                 mutex_lock(&dev_priv->pcu_lock);
4853                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4854                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4855                 mutex_unlock(&dev_priv->pcu_lock);
4856                 /* Quoting Art Runyan: "its not safe to expect any particular
4857                  * value in IPS_CTL bit 31 after enabling IPS through the
4858                  * mailbox." Moreover, the mailbox may return a bogus state,
4859                  * so we need to just enable it and continue on.
4860                  */
4861         } else {
4862                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4863                 /* The bit only becomes 1 in the next vblank, so this wait here
4864                  * is essentially intel_wait_for_vblank. If we don't have this
4865                  * and don't wait for vblanks until the end of crtc_enable, then
4866                  * the HW state readout code will complain that the expected
4867                  * IPS_CTL value is not the one we read. */
4868                 if (intel_wait_for_register(dev_priv,
4869                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4870                                             50))
4871                         DRM_ERROR("Timed out waiting for IPS enable\n");
4872         }
4873 }
4874
4875 void hsw_disable_ips(struct intel_crtc *crtc)
4876 {
4877         struct drm_device *dev = crtc->base.dev;
4878         struct drm_i915_private *dev_priv = to_i915(dev);
4879
4880         if (!crtc->config->ips_enabled)
4881                 return;
4882
4883         assert_plane_enabled(dev_priv, crtc->plane);
4884         if (IS_BROADWELL(dev_priv)) {
4885                 mutex_lock(&dev_priv->pcu_lock);
4886                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4887                 mutex_unlock(&dev_priv->pcu_lock);
4888                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4889                 if (intel_wait_for_register(dev_priv,
4890                                             IPS_CTL, IPS_ENABLE, 0,
4891                                             42))
4892                         DRM_ERROR("Timed out waiting for IPS disable\n");
4893         } else {
4894                 I915_WRITE(IPS_CTL, 0);
4895                 POSTING_READ(IPS_CTL);
4896         }
4897
4898         /* We need to wait for a vblank before we can disable the plane. */
4899         intel_wait_for_vblank(dev_priv, crtc->pipe);
4900 }
4901
4902 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4903 {
4904         if (intel_crtc->overlay) {
4905                 struct drm_device *dev = intel_crtc->base.dev;
4906
4907                 mutex_lock(&dev->struct_mutex);
4908                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4909                 mutex_unlock(&dev->struct_mutex);
4910         }
4911
4912         /* Let userspace switch the overlay on again. In most cases userspace
4913          * has to recompute where to put it anyway.
4914          */
4915 }
4916
4917 /**
4918  * intel_post_enable_primary - Perform operations after enabling primary plane
4919  * @crtc: the CRTC whose primary plane was just enabled
4920  *
4921  * Performs potentially sleeping operations that must be done after the primary
4922  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4923  * called due to an explicit primary plane update, or due to an implicit
4924  * re-enable that is caused when a sprite plane is updated to no longer
4925  * completely hide the primary plane.
4926  */
4927 static void
4928 intel_post_enable_primary(struct drm_crtc *crtc)
4929 {
4930         struct drm_device *dev = crtc->dev;
4931         struct drm_i915_private *dev_priv = to_i915(dev);
4932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933         int pipe = intel_crtc->pipe;
4934
4935         /*
4936          * FIXME IPS should be fine as long as one plane is
4937          * enabled, but in practice it seems to have problems
4938          * when going from primary only to sprite only and vice
4939          * versa.
4940          */
4941         hsw_enable_ips(intel_crtc);
4942
4943         /*
4944          * Gen2 reports pipe underruns whenever all planes are disabled.
4945          * So don't enable underrun reporting before at least some planes
4946          * are enabled.
4947          * FIXME: Need to fix the logic to work when we turn off all planes
4948          * but leave the pipe running.
4949          */
4950         if (IS_GEN2(dev_priv))
4951                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4952
4953         /* Underruns don't always raise interrupts, so check manually. */
4954         intel_check_cpu_fifo_underruns(dev_priv);
4955         intel_check_pch_fifo_underruns(dev_priv);
4956 }
4957
4958 /* FIXME move all this to pre_plane_update() with proper state tracking */
4959 static void
4960 intel_pre_disable_primary(struct drm_crtc *crtc)
4961 {
4962         struct drm_device *dev = crtc->dev;
4963         struct drm_i915_private *dev_priv = to_i915(dev);
4964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965         int pipe = intel_crtc->pipe;
4966
4967         /*
4968          * Gen2 reports pipe underruns whenever all planes are disabled.
4969          * So diasble underrun reporting before all the planes get disabled.
4970          * FIXME: Need to fix the logic to work when we turn off all planes
4971          * but leave the pipe running.
4972          */
4973         if (IS_GEN2(dev_priv))
4974                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4975
4976         /*
4977          * FIXME IPS should be fine as long as one plane is
4978          * enabled, but in practice it seems to have problems
4979          * when going from primary only to sprite only and vice
4980          * versa.
4981          */
4982         hsw_disable_ips(intel_crtc);
4983 }
4984
4985 /* FIXME get rid of this and use pre_plane_update */
4986 static void
4987 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4988 {
4989         struct drm_device *dev = crtc->dev;
4990         struct drm_i915_private *dev_priv = to_i915(dev);
4991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992         int pipe = intel_crtc->pipe;
4993
4994         intel_pre_disable_primary(crtc);
4995
4996         /*
4997          * Vblank time updates from the shadow to live plane control register
4998          * are blocked if the memory self-refresh mode is active at that
4999          * moment. So to make sure the plane gets truly disabled, disable
5000          * first the self-refresh mode. The self-refresh enable bit in turn
5001          * will be checked/applied by the HW only at the next frame start
5002          * event which is after the vblank start event, so we need to have a
5003          * wait-for-vblank between disabling the plane and the pipe.
5004          */
5005         if (HAS_GMCH_DISPLAY(dev_priv) &&
5006             intel_set_memory_cxsr(dev_priv, false))
5007                 intel_wait_for_vblank(dev_priv, pipe);
5008 }
5009
5010 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5011 {
5012         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5013         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5014         struct intel_crtc_state *pipe_config =
5015                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5016                                                 crtc);
5017         struct drm_plane *primary = crtc->base.primary;
5018         struct drm_plane_state *old_pri_state =
5019                 drm_atomic_get_existing_plane_state(old_state, primary);
5020
5021         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5022
5023         if (pipe_config->update_wm_post && pipe_config->base.active)
5024                 intel_update_watermarks(crtc);
5025
5026         if (old_pri_state) {
5027                 struct intel_plane_state *primary_state =
5028                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5029                                                          to_intel_plane(primary));
5030                 struct intel_plane_state *old_primary_state =
5031                         to_intel_plane_state(old_pri_state);
5032
5033                 intel_fbc_post_update(crtc);
5034
5035                 if (primary_state->base.visible &&
5036                     (needs_modeset(&pipe_config->base) ||
5037                      !old_primary_state->base.visible))
5038                         intel_post_enable_primary(&crtc->base);
5039         }
5040 }
5041
5042 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5043                                    struct intel_crtc_state *pipe_config)
5044 {
5045         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5046         struct drm_device *dev = crtc->base.dev;
5047         struct drm_i915_private *dev_priv = to_i915(dev);
5048         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5049         struct drm_plane *primary = crtc->base.primary;
5050         struct drm_plane_state *old_pri_state =
5051                 drm_atomic_get_existing_plane_state(old_state, primary);
5052         bool modeset = needs_modeset(&pipe_config->base);
5053         struct intel_atomic_state *old_intel_state =
5054                 to_intel_atomic_state(old_state);
5055
5056         if (old_pri_state) {
5057                 struct intel_plane_state *primary_state =
5058                         intel_atomic_get_new_plane_state(old_intel_state,
5059                                                          to_intel_plane(primary));
5060                 struct intel_plane_state *old_primary_state =
5061                         to_intel_plane_state(old_pri_state);
5062
5063                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5064
5065                 if (old_primary_state->base.visible &&
5066                     (modeset || !primary_state->base.visible))
5067                         intel_pre_disable_primary(&crtc->base);
5068         }
5069
5070         /*
5071          * Vblank time updates from the shadow to live plane control register
5072          * are blocked if the memory self-refresh mode is active at that
5073          * moment. So to make sure the plane gets truly disabled, disable
5074          * first the self-refresh mode. The self-refresh enable bit in turn
5075          * will be checked/applied by the HW only at the next frame start
5076          * event which is after the vblank start event, so we need to have a
5077          * wait-for-vblank between disabling the plane and the pipe.
5078          */
5079         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5080             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5081                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5082
5083         /*
5084          * IVB workaround: must disable low power watermarks for at least
5085          * one frame before enabling scaling.  LP watermarks can be re-enabled
5086          * when scaling is disabled.
5087          *
5088          * WaCxSRDisabledForSpriteScaling:ivb
5089          */
5090         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5091                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5092
5093         /*
5094          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5095          * watermark programming here.
5096          */
5097         if (needs_modeset(&pipe_config->base))
5098                 return;
5099
5100         /*
5101          * For platforms that support atomic watermarks, program the
5102          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5103          * will be the intermediate values that are safe for both pre- and
5104          * post- vblank; when vblank happens, the 'active' values will be set
5105          * to the final 'target' values and we'll do this again to get the
5106          * optimal watermarks.  For gen9+ platforms, the values we program here
5107          * will be the final target values which will get automatically latched
5108          * at vblank time; no further programming will be necessary.
5109          *
5110          * If a platform hasn't been transitioned to atomic watermarks yet,
5111          * we'll continue to update watermarks the old way, if flags tell
5112          * us to.
5113          */
5114         if (dev_priv->display.initial_watermarks != NULL)
5115                 dev_priv->display.initial_watermarks(old_intel_state,
5116                                                      pipe_config);
5117         else if (pipe_config->update_wm_pre)
5118                 intel_update_watermarks(crtc);
5119 }
5120
5121 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5122 {
5123         struct drm_device *dev = crtc->dev;
5124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5125         struct drm_plane *p;
5126         int pipe = intel_crtc->pipe;
5127
5128         intel_crtc_dpms_overlay_disable(intel_crtc);
5129
5130         drm_for_each_plane_mask(p, dev, plane_mask)
5131                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5132
5133         /*
5134          * FIXME: Once we grow proper nuclear flip support out of this we need
5135          * to compute the mask of flip planes precisely. For the time being
5136          * consider this a flip to a NULL plane.
5137          */
5138         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5139 }
5140
5141 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5142                                           struct intel_crtc_state *crtc_state,
5143                                           struct drm_atomic_state *old_state)
5144 {
5145         struct drm_connector_state *conn_state;
5146         struct drm_connector *conn;
5147         int i;
5148
5149         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5150                 struct intel_encoder *encoder =
5151                         to_intel_encoder(conn_state->best_encoder);
5152
5153                 if (conn_state->crtc != crtc)
5154                         continue;
5155
5156                 if (encoder->pre_pll_enable)
5157                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5158         }
5159 }
5160
5161 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5162                                       struct intel_crtc_state *crtc_state,
5163                                       struct drm_atomic_state *old_state)
5164 {
5165         struct drm_connector_state *conn_state;
5166         struct drm_connector *conn;
5167         int i;
5168
5169         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5170                 struct intel_encoder *encoder =
5171                         to_intel_encoder(conn_state->best_encoder);
5172
5173                 if (conn_state->crtc != crtc)
5174                         continue;
5175
5176                 if (encoder->pre_enable)
5177                         encoder->pre_enable(encoder, crtc_state, conn_state);
5178         }
5179 }
5180
5181 static void intel_encoders_enable(struct drm_crtc *crtc,
5182                                   struct intel_crtc_state *crtc_state,
5183                                   struct drm_atomic_state *old_state)
5184 {
5185         struct drm_connector_state *conn_state;
5186         struct drm_connector *conn;
5187         int i;
5188
5189         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5190                 struct intel_encoder *encoder =
5191                         to_intel_encoder(conn_state->best_encoder);
5192
5193                 if (conn_state->crtc != crtc)
5194                         continue;
5195
5196                 encoder->enable(encoder, crtc_state, conn_state);
5197                 intel_opregion_notify_encoder(encoder, true);
5198         }
5199 }
5200
5201 static void intel_encoders_disable(struct drm_crtc *crtc,
5202                                    struct intel_crtc_state *old_crtc_state,
5203                                    struct drm_atomic_state *old_state)
5204 {
5205         struct drm_connector_state *old_conn_state;
5206         struct drm_connector *conn;
5207         int i;
5208
5209         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5210                 struct intel_encoder *encoder =
5211                         to_intel_encoder(old_conn_state->best_encoder);
5212
5213                 if (old_conn_state->crtc != crtc)
5214                         continue;
5215
5216                 intel_opregion_notify_encoder(encoder, false);
5217                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5218         }
5219 }
5220
5221 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5222                                         struct intel_crtc_state *old_crtc_state,
5223                                         struct drm_atomic_state *old_state)
5224 {
5225         struct drm_connector_state *old_conn_state;
5226         struct drm_connector *conn;
5227         int i;
5228
5229         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5230                 struct intel_encoder *encoder =
5231                         to_intel_encoder(old_conn_state->best_encoder);
5232
5233                 if (old_conn_state->crtc != crtc)
5234                         continue;
5235
5236                 if (encoder->post_disable)
5237                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5238         }
5239 }
5240
5241 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5242                                             struct intel_crtc_state *old_crtc_state,
5243                                             struct drm_atomic_state *old_state)
5244 {
5245         struct drm_connector_state *old_conn_state;
5246         struct drm_connector *conn;
5247         int i;
5248
5249         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5250                 struct intel_encoder *encoder =
5251                         to_intel_encoder(old_conn_state->best_encoder);
5252
5253                 if (old_conn_state->crtc != crtc)
5254                         continue;
5255
5256                 if (encoder->post_pll_disable)
5257                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5258         }
5259 }
5260
5261 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5262                                  struct drm_atomic_state *old_state)
5263 {
5264         struct drm_crtc *crtc = pipe_config->base.crtc;
5265         struct drm_device *dev = crtc->dev;
5266         struct drm_i915_private *dev_priv = to_i915(dev);
5267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268         int pipe = intel_crtc->pipe;
5269         struct intel_atomic_state *old_intel_state =
5270                 to_intel_atomic_state(old_state);
5271
5272         if (WARN_ON(intel_crtc->active))
5273                 return;
5274
5275         /*
5276          * Sometimes spurious CPU pipe underruns happen during FDI
5277          * training, at least with VGA+HDMI cloning. Suppress them.
5278          *
5279          * On ILK we get an occasional spurious CPU pipe underruns
5280          * between eDP port A enable and vdd enable. Also PCH port
5281          * enable seems to result in the occasional CPU pipe underrun.
5282          *
5283          * Spurious PCH underruns also occur during PCH enabling.
5284          */
5285         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5286                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5287         if (intel_crtc->config->has_pch_encoder)
5288                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5289
5290         if (intel_crtc->config->has_pch_encoder)
5291                 intel_prepare_shared_dpll(intel_crtc);
5292
5293         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5294                 intel_dp_set_m_n(intel_crtc, M1_N1);
5295
5296         intel_set_pipe_timings(intel_crtc);
5297         intel_set_pipe_src_size(intel_crtc);
5298
5299         if (intel_crtc->config->has_pch_encoder) {
5300                 intel_cpu_transcoder_set_m_n(intel_crtc,
5301                                      &intel_crtc->config->fdi_m_n, NULL);
5302         }
5303
5304         ironlake_set_pipeconf(crtc);
5305
5306         intel_crtc->active = true;
5307
5308         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5309
5310         if (intel_crtc->config->has_pch_encoder) {
5311                 /* Note: FDI PLL enabling _must_ be done before we enable the
5312                  * cpu pipes, hence this is separate from all the other fdi/pch
5313                  * enabling. */
5314                 ironlake_fdi_pll_enable(intel_crtc);
5315         } else {
5316                 assert_fdi_tx_disabled(dev_priv, pipe);
5317                 assert_fdi_rx_disabled(dev_priv, pipe);
5318         }
5319
5320         ironlake_pfit_enable(intel_crtc);
5321
5322         /*
5323          * On ILK+ LUT must be loaded before the pipe is running but with
5324          * clocks enabled
5325          */
5326         intel_color_load_luts(&pipe_config->base);
5327
5328         if (dev_priv->display.initial_watermarks != NULL)
5329                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5330         intel_enable_pipe(intel_crtc);
5331
5332         if (intel_crtc->config->has_pch_encoder)
5333                 ironlake_pch_enable(pipe_config);
5334
5335         assert_vblank_disabled(crtc);
5336         drm_crtc_vblank_on(crtc);
5337
5338         intel_encoders_enable(crtc, pipe_config, old_state);
5339
5340         if (HAS_PCH_CPT(dev_priv))
5341                 cpt_verify_modeset(dev, intel_crtc->pipe);
5342
5343         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5344         if (intel_crtc->config->has_pch_encoder)
5345                 intel_wait_for_vblank(dev_priv, pipe);
5346         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5347         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5348 }
5349
5350 /* IPS only exists on ULT machines and is tied to pipe A. */
5351 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5352 {
5353         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5354 }
5355
5356 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5357                                             enum pipe pipe, bool apply)
5358 {
5359         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5360         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5361
5362         if (apply)
5363                 val |= mask;
5364         else
5365                 val &= ~mask;
5366
5367         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5368 }
5369
5370 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5371                                 struct drm_atomic_state *old_state)
5372 {
5373         struct drm_crtc *crtc = pipe_config->base.crtc;
5374         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5377         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5378         struct intel_atomic_state *old_intel_state =
5379                 to_intel_atomic_state(old_state);
5380         bool psl_clkgate_wa;
5381
5382         if (WARN_ON(intel_crtc->active))
5383                 return;
5384
5385         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5386
5387         if (intel_crtc->config->shared_dpll)
5388                 intel_enable_shared_dpll(intel_crtc);
5389
5390         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5391                 intel_dp_set_m_n(intel_crtc, M1_N1);
5392
5393         if (!transcoder_is_dsi(cpu_transcoder))
5394                 intel_set_pipe_timings(intel_crtc);
5395
5396         intel_set_pipe_src_size(intel_crtc);
5397
5398         if (cpu_transcoder != TRANSCODER_EDP &&
5399             !transcoder_is_dsi(cpu_transcoder)) {
5400                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5401                            intel_crtc->config->pixel_multiplier - 1);
5402         }
5403
5404         if (intel_crtc->config->has_pch_encoder) {
5405                 intel_cpu_transcoder_set_m_n(intel_crtc,
5406                                      &intel_crtc->config->fdi_m_n, NULL);
5407         }
5408
5409         if (!transcoder_is_dsi(cpu_transcoder))
5410                 haswell_set_pipeconf(crtc);
5411
5412         haswell_set_pipemisc(crtc);
5413
5414         intel_color_set_csc(&pipe_config->base);
5415
5416         intel_crtc->active = true;
5417
5418         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5419
5420         if (!transcoder_is_dsi(cpu_transcoder))
5421                 intel_ddi_enable_pipe_clock(pipe_config);
5422
5423         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5424         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5425                          intel_crtc->config->pch_pfit.enabled;
5426         if (psl_clkgate_wa)
5427                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5428
5429         if (INTEL_GEN(dev_priv) >= 9)
5430                 skylake_pfit_enable(intel_crtc);
5431         else
5432                 ironlake_pfit_enable(intel_crtc);
5433
5434         /*
5435          * On ILK+ LUT must be loaded before the pipe is running but with
5436          * clocks enabled
5437          */
5438         intel_color_load_luts(&pipe_config->base);
5439
5440         intel_ddi_set_pipe_settings(pipe_config);
5441         if (!transcoder_is_dsi(cpu_transcoder))
5442                 intel_ddi_enable_transcoder_func(pipe_config);
5443
5444         if (dev_priv->display.initial_watermarks != NULL)
5445                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5446
5447         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5448         if (!transcoder_is_dsi(cpu_transcoder))
5449                 intel_enable_pipe(intel_crtc);
5450
5451         if (intel_crtc->config->has_pch_encoder)
5452                 lpt_pch_enable(pipe_config);
5453
5454         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5455                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5456
5457         assert_vblank_disabled(crtc);
5458         drm_crtc_vblank_on(crtc);
5459
5460         intel_encoders_enable(crtc, pipe_config, old_state);
5461
5462         if (psl_clkgate_wa) {
5463                 intel_wait_for_vblank(dev_priv, pipe);
5464                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5465         }
5466
5467         /* If we change the relative order between pipe/planes enabling, we need
5468          * to change the workaround. */
5469         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5470         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5471                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5472                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5473         }
5474 }
5475
5476 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5477 {
5478         struct drm_device *dev = crtc->base.dev;
5479         struct drm_i915_private *dev_priv = to_i915(dev);
5480         int pipe = crtc->pipe;
5481
5482         /* To avoid upsetting the power well on haswell only disable the pfit if
5483          * it's in use. The hw state code will make sure we get this right. */
5484         if (force || crtc->config->pch_pfit.enabled) {
5485                 I915_WRITE(PF_CTL(pipe), 0);
5486                 I915_WRITE(PF_WIN_POS(pipe), 0);
5487                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5488         }
5489 }
5490
5491 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5492                                   struct drm_atomic_state *old_state)
5493 {
5494         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5495         struct drm_device *dev = crtc->dev;
5496         struct drm_i915_private *dev_priv = to_i915(dev);
5497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5498         int pipe = intel_crtc->pipe;
5499
5500         /*
5501          * Sometimes spurious CPU pipe underruns happen when the
5502          * pipe is already disabled, but FDI RX/TX is still enabled.
5503          * Happens at least with VGA+HDMI cloning. Suppress them.
5504          */
5505         if (intel_crtc->config->has_pch_encoder) {
5506                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5507                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5508         }
5509
5510         intel_encoders_disable(crtc, old_crtc_state, old_state);
5511
5512         drm_crtc_vblank_off(crtc);
5513         assert_vblank_disabled(crtc);
5514
5515         intel_disable_pipe(intel_crtc);
5516
5517         ironlake_pfit_disable(intel_crtc, false);
5518
5519         if (intel_crtc->config->has_pch_encoder)
5520                 ironlake_fdi_disable(crtc);
5521
5522         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5523
5524         if (intel_crtc->config->has_pch_encoder) {
5525                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5526
5527                 if (HAS_PCH_CPT(dev_priv)) {
5528                         i915_reg_t reg;
5529                         u32 temp;
5530
5531                         /* disable TRANS_DP_CTL */
5532                         reg = TRANS_DP_CTL(pipe);
5533                         temp = I915_READ(reg);
5534                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5535                                   TRANS_DP_PORT_SEL_MASK);
5536                         temp |= TRANS_DP_PORT_SEL_NONE;
5537                         I915_WRITE(reg, temp);
5538
5539                         /* disable DPLL_SEL */
5540                         temp = I915_READ(PCH_DPLL_SEL);
5541                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5542                         I915_WRITE(PCH_DPLL_SEL, temp);
5543                 }
5544
5545                 ironlake_fdi_pll_disable(intel_crtc);
5546         }
5547
5548         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5549         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5550 }
5551
5552 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5553                                  struct drm_atomic_state *old_state)
5554 {
5555         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5556         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5559
5560         intel_encoders_disable(crtc, old_crtc_state, old_state);
5561
5562         drm_crtc_vblank_off(crtc);
5563         assert_vblank_disabled(crtc);
5564
5565         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5566         if (!transcoder_is_dsi(cpu_transcoder))
5567                 intel_disable_pipe(intel_crtc);
5568
5569         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5570                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5571
5572         if (!transcoder_is_dsi(cpu_transcoder))
5573                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5574
5575         if (INTEL_GEN(dev_priv) >= 9)
5576                 skylake_scaler_disable(intel_crtc);
5577         else
5578                 ironlake_pfit_disable(intel_crtc, false);
5579
5580         if (!transcoder_is_dsi(cpu_transcoder))
5581                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5582
5583         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5584 }
5585
5586 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5587 {
5588         struct drm_device *dev = crtc->base.dev;
5589         struct drm_i915_private *dev_priv = to_i915(dev);
5590         struct intel_crtc_state *pipe_config = crtc->config;
5591
5592         if (!pipe_config->gmch_pfit.control)
5593                 return;
5594
5595         /*
5596          * The panel fitter should only be adjusted whilst the pipe is disabled,
5597          * according to register description and PRM.
5598          */
5599         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5600         assert_pipe_disabled(dev_priv, crtc->pipe);
5601
5602         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5603         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5604
5605         /* Border color in case we don't scale up to the full screen. Black by
5606          * default, change to something else for debugging. */
5607         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5608 }
5609
5610 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5611 {
5612         switch (port) {
5613         case PORT_A:
5614                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5615         case PORT_B:
5616                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5617         case PORT_C:
5618                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5619         case PORT_D:
5620                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5621         case PORT_E:
5622                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5623         default:
5624                 MISSING_CASE(port);
5625                 return POWER_DOMAIN_PORT_OTHER;
5626         }
5627 }
5628
5629 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5630                                   struct intel_crtc_state *crtc_state)
5631 {
5632         struct drm_device *dev = crtc->dev;
5633         struct drm_i915_private *dev_priv = to_i915(dev);
5634         struct drm_encoder *encoder;
5635         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5636         enum pipe pipe = intel_crtc->pipe;
5637         u64 mask;
5638         enum transcoder transcoder = crtc_state->cpu_transcoder;
5639
5640         if (!crtc_state->base.active)
5641                 return 0;
5642
5643         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5644         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5645         if (crtc_state->pch_pfit.enabled ||
5646             crtc_state->pch_pfit.force_thru)
5647                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5648
5649         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5650                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5651
5652                 mask |= BIT_ULL(intel_encoder->power_domain);
5653         }
5654
5655         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5656                 mask |= BIT(POWER_DOMAIN_AUDIO);
5657
5658         if (crtc_state->shared_dpll)
5659                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5660
5661         return mask;
5662 }
5663
5664 static u64
5665 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5666                                struct intel_crtc_state *crtc_state)
5667 {
5668         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5670         enum intel_display_power_domain domain;
5671         u64 domains, new_domains, old_domains;
5672
5673         old_domains = intel_crtc->enabled_power_domains;
5674         intel_crtc->enabled_power_domains = new_domains =
5675                 get_crtc_power_domains(crtc, crtc_state);
5676
5677         domains = new_domains & ~old_domains;
5678
5679         for_each_power_domain(domain, domains)
5680                 intel_display_power_get(dev_priv, domain);
5681
5682         return old_domains & ~new_domains;
5683 }
5684
5685 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5686                                       u64 domains)
5687 {
5688         enum intel_display_power_domain domain;
5689
5690         for_each_power_domain(domain, domains)
5691                 intel_display_power_put(dev_priv, domain);
5692 }
5693
5694 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5695                                    struct drm_atomic_state *old_state)
5696 {
5697         struct intel_atomic_state *old_intel_state =
5698                 to_intel_atomic_state(old_state);
5699         struct drm_crtc *crtc = pipe_config->base.crtc;
5700         struct drm_device *dev = crtc->dev;
5701         struct drm_i915_private *dev_priv = to_i915(dev);
5702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703         int pipe = intel_crtc->pipe;
5704
5705         if (WARN_ON(intel_crtc->active))
5706                 return;
5707
5708         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5709                 intel_dp_set_m_n(intel_crtc, M1_N1);
5710
5711         intel_set_pipe_timings(intel_crtc);
5712         intel_set_pipe_src_size(intel_crtc);
5713
5714         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5715                 struct drm_i915_private *dev_priv = to_i915(dev);
5716
5717                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5718                 I915_WRITE(CHV_CANVAS(pipe), 0);
5719         }
5720
5721         i9xx_set_pipeconf(intel_crtc);
5722
5723         intel_crtc->active = true;
5724
5725         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5726
5727         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5728
5729         if (IS_CHERRYVIEW(dev_priv)) {
5730                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5731                 chv_enable_pll(intel_crtc, intel_crtc->config);
5732         } else {
5733                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5734                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5735         }
5736
5737         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5738
5739         i9xx_pfit_enable(intel_crtc);
5740
5741         intel_color_load_luts(&pipe_config->base);
5742
5743         dev_priv->display.initial_watermarks(old_intel_state,
5744                                              pipe_config);
5745         intel_enable_pipe(intel_crtc);
5746
5747         assert_vblank_disabled(crtc);
5748         drm_crtc_vblank_on(crtc);
5749
5750         intel_encoders_enable(crtc, pipe_config, old_state);
5751 }
5752
5753 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5754 {
5755         struct drm_device *dev = crtc->base.dev;
5756         struct drm_i915_private *dev_priv = to_i915(dev);
5757
5758         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5759         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5760 }
5761
5762 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5763                              struct drm_atomic_state *old_state)
5764 {
5765         struct intel_atomic_state *old_intel_state =
5766                 to_intel_atomic_state(old_state);
5767         struct drm_crtc *crtc = pipe_config->base.crtc;
5768         struct drm_device *dev = crtc->dev;
5769         struct drm_i915_private *dev_priv = to_i915(dev);
5770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771         enum pipe pipe = intel_crtc->pipe;
5772
5773         if (WARN_ON(intel_crtc->active))
5774                 return;
5775
5776         i9xx_set_pll_dividers(intel_crtc);
5777
5778         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5779                 intel_dp_set_m_n(intel_crtc, M1_N1);
5780
5781         intel_set_pipe_timings(intel_crtc);
5782         intel_set_pipe_src_size(intel_crtc);
5783
5784         i9xx_set_pipeconf(intel_crtc);
5785
5786         intel_crtc->active = true;
5787
5788         if (!IS_GEN2(dev_priv))
5789                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5790
5791         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5792
5793         i9xx_enable_pll(intel_crtc, pipe_config);
5794
5795         i9xx_pfit_enable(intel_crtc);
5796
5797         intel_color_load_luts(&pipe_config->base);
5798
5799         if (dev_priv->display.initial_watermarks != NULL)
5800                 dev_priv->display.initial_watermarks(old_intel_state,
5801                                                      intel_crtc->config);
5802         else
5803                 intel_update_watermarks(intel_crtc);
5804         intel_enable_pipe(intel_crtc);
5805
5806         assert_vblank_disabled(crtc);
5807         drm_crtc_vblank_on(crtc);
5808
5809         intel_encoders_enable(crtc, pipe_config, old_state);
5810 }
5811
5812 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5813 {
5814         struct drm_device *dev = crtc->base.dev;
5815         struct drm_i915_private *dev_priv = to_i915(dev);
5816
5817         if (!crtc->config->gmch_pfit.control)
5818                 return;
5819
5820         assert_pipe_disabled(dev_priv, crtc->pipe);
5821
5822         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5823                          I915_READ(PFIT_CONTROL));
5824         I915_WRITE(PFIT_CONTROL, 0);
5825 }
5826
5827 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5828                               struct drm_atomic_state *old_state)
5829 {
5830         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5831         struct drm_device *dev = crtc->dev;
5832         struct drm_i915_private *dev_priv = to_i915(dev);
5833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5834         int pipe = intel_crtc->pipe;
5835
5836         /*
5837          * On gen2 planes are double buffered but the pipe isn't, so we must
5838          * wait for planes to fully turn off before disabling the pipe.
5839          */
5840         if (IS_GEN2(dev_priv))
5841                 intel_wait_for_vblank(dev_priv, pipe);
5842
5843         intel_encoders_disable(crtc, old_crtc_state, old_state);
5844
5845         drm_crtc_vblank_off(crtc);
5846         assert_vblank_disabled(crtc);
5847
5848         intel_disable_pipe(intel_crtc);
5849
5850         i9xx_pfit_disable(intel_crtc);
5851
5852         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5853
5854         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5855                 if (IS_CHERRYVIEW(dev_priv))
5856                         chv_disable_pll(dev_priv, pipe);
5857                 else if (IS_VALLEYVIEW(dev_priv))
5858                         vlv_disable_pll(dev_priv, pipe);
5859                 else
5860                         i9xx_disable_pll(intel_crtc);
5861         }
5862
5863         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5864
5865         if (!IS_GEN2(dev_priv))
5866                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5867
5868         if (!dev_priv->display.initial_watermarks)
5869                 intel_update_watermarks(intel_crtc);
5870
5871         /* clock the pipe down to 640x480@60 to potentially save power */
5872         if (IS_I830(dev_priv))
5873                 i830_enable_pipe(dev_priv, pipe);
5874 }
5875
5876 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5877                                         struct drm_modeset_acquire_ctx *ctx)
5878 {
5879         struct intel_encoder *encoder;
5880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5882         enum intel_display_power_domain domain;
5883         u64 domains;
5884         struct drm_atomic_state *state;
5885         struct intel_crtc_state *crtc_state;
5886         int ret;
5887
5888         if (!intel_crtc->active)
5889                 return;
5890
5891         if (crtc->primary->state->visible) {
5892                 intel_pre_disable_primary_noatomic(crtc);
5893
5894                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5895                 crtc->primary->state->visible = false;
5896         }
5897
5898         state = drm_atomic_state_alloc(crtc->dev);
5899         if (!state) {
5900                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5901                               crtc->base.id, crtc->name);
5902                 return;
5903         }
5904
5905         state->acquire_ctx = ctx;
5906
5907         /* Everything's already locked, -EDEADLK can't happen. */
5908         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5909         ret = drm_atomic_add_affected_connectors(state, crtc);
5910
5911         WARN_ON(IS_ERR(crtc_state) || ret);
5912
5913         dev_priv->display.crtc_disable(crtc_state, state);
5914
5915         drm_atomic_state_put(state);
5916
5917         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5918                       crtc->base.id, crtc->name);
5919
5920         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5921         crtc->state->active = false;
5922         intel_crtc->active = false;
5923         crtc->enabled = false;
5924         crtc->state->connector_mask = 0;
5925         crtc->state->encoder_mask = 0;
5926
5927         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5928                 encoder->base.crtc = NULL;
5929
5930         intel_fbc_disable(intel_crtc);
5931         intel_update_watermarks(intel_crtc);
5932         intel_disable_shared_dpll(intel_crtc);
5933
5934         domains = intel_crtc->enabled_power_domains;
5935         for_each_power_domain(domain, domains)
5936                 intel_display_power_put(dev_priv, domain);
5937         intel_crtc->enabled_power_domains = 0;
5938
5939         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5940         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
5941         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
5942 }
5943
5944 /*
5945  * turn all crtc's off, but do not adjust state
5946  * This has to be paired with a call to intel_modeset_setup_hw_state.
5947  */
5948 int intel_display_suspend(struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = to_i915(dev);
5951         struct drm_atomic_state *state;
5952         int ret;
5953
5954         state = drm_atomic_helper_suspend(dev);
5955         ret = PTR_ERR_OR_ZERO(state);
5956         if (ret)
5957                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5958         else
5959                 dev_priv->modeset_restore_state = state;
5960         return ret;
5961 }
5962
5963 void intel_encoder_destroy(struct drm_encoder *encoder)
5964 {
5965         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5966
5967         drm_encoder_cleanup(encoder);
5968         kfree(intel_encoder);
5969 }
5970
5971 /* Cross check the actual hw state with our own modeset state tracking (and it's
5972  * internal consistency). */
5973 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
5974                                          struct drm_connector_state *conn_state)
5975 {
5976         struct intel_connector *connector = to_intel_connector(conn_state->connector);
5977
5978         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5979                       connector->base.base.id,
5980                       connector->base.name);
5981
5982         if (connector->get_hw_state(connector)) {
5983                 struct intel_encoder *encoder = connector->encoder;
5984
5985                 I915_STATE_WARN(!crtc_state,
5986                          "connector enabled without attached crtc\n");
5987
5988                 if (!crtc_state)
5989                         return;
5990
5991                 I915_STATE_WARN(!crtc_state->active,
5992                       "connector is active, but attached crtc isn't\n");
5993
5994                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5995                         return;
5996
5997                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5998                         "atomic encoder doesn't match attached encoder\n");
5999
6000                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6001                         "attached encoder crtc differs from connector crtc\n");
6002         } else {
6003                 I915_STATE_WARN(crtc_state && crtc_state->active,
6004                         "attached crtc is active, but connector isn't\n");
6005                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6006                         "best encoder set without crtc!\n");
6007         }
6008 }
6009
6010 int intel_connector_init(struct intel_connector *connector)
6011 {
6012         struct intel_digital_connector_state *conn_state;
6013
6014         /*
6015          * Allocate enough memory to hold intel_digital_connector_state,
6016          * This might be a few bytes too many, but for connectors that don't
6017          * need it we'll free the state and allocate a smaller one on the first
6018          * succesful commit anyway.
6019          */
6020         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6021         if (!conn_state)
6022                 return -ENOMEM;
6023
6024         __drm_atomic_helper_connector_reset(&connector->base,
6025                                             &conn_state->base);
6026
6027         return 0;
6028 }
6029
6030 struct intel_connector *intel_connector_alloc(void)
6031 {
6032         struct intel_connector *connector;
6033
6034         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6035         if (!connector)
6036                 return NULL;
6037
6038         if (intel_connector_init(connector) < 0) {
6039                 kfree(connector);
6040                 return NULL;
6041         }
6042
6043         return connector;
6044 }
6045
6046 /*
6047  * Free the bits allocated by intel_connector_alloc.
6048  * This should only be used after intel_connector_alloc has returned
6049  * successfully, and before drm_connector_init returns successfully.
6050  * Otherwise the destroy callbacks for the connector and the state should
6051  * take care of proper cleanup/free
6052  */
6053 void intel_connector_free(struct intel_connector *connector)
6054 {
6055         kfree(to_intel_digital_connector_state(connector->base.state));
6056         kfree(connector);
6057 }
6058
6059 /* Simple connector->get_hw_state implementation for encoders that support only
6060  * one connector and no cloning and hence the encoder state determines the state
6061  * of the connector. */
6062 bool intel_connector_get_hw_state(struct intel_connector *connector)
6063 {
6064         enum pipe pipe = 0;
6065         struct intel_encoder *encoder = connector->encoder;
6066
6067         return encoder->get_hw_state(encoder, &pipe);
6068 }
6069
6070 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6071 {
6072         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6073                 return crtc_state->fdi_lanes;
6074
6075         return 0;
6076 }
6077
6078 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6079                                      struct intel_crtc_state *pipe_config)
6080 {
6081         struct drm_i915_private *dev_priv = to_i915(dev);
6082         struct drm_atomic_state *state = pipe_config->base.state;
6083         struct intel_crtc *other_crtc;
6084         struct intel_crtc_state *other_crtc_state;
6085
6086         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6087                       pipe_name(pipe), pipe_config->fdi_lanes);
6088         if (pipe_config->fdi_lanes > 4) {
6089                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6090                               pipe_name(pipe), pipe_config->fdi_lanes);
6091                 return -EINVAL;
6092         }
6093
6094         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6095                 if (pipe_config->fdi_lanes > 2) {
6096                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6097                                       pipe_config->fdi_lanes);
6098                         return -EINVAL;
6099                 } else {
6100                         return 0;
6101                 }
6102         }
6103
6104         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6105                 return 0;
6106
6107         /* Ivybridge 3 pipe is really complicated */
6108         switch (pipe) {
6109         case PIPE_A:
6110                 return 0;
6111         case PIPE_B:
6112                 if (pipe_config->fdi_lanes <= 2)
6113                         return 0;
6114
6115                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6116                 other_crtc_state =
6117                         intel_atomic_get_crtc_state(state, other_crtc);
6118                 if (IS_ERR(other_crtc_state))
6119                         return PTR_ERR(other_crtc_state);
6120
6121                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6122                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6123                                       pipe_name(pipe), pipe_config->fdi_lanes);
6124                         return -EINVAL;
6125                 }
6126                 return 0;
6127         case PIPE_C:
6128                 if (pipe_config->fdi_lanes > 2) {
6129                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6130                                       pipe_name(pipe), pipe_config->fdi_lanes);
6131                         return -EINVAL;
6132                 }
6133
6134                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6135                 other_crtc_state =
6136                         intel_atomic_get_crtc_state(state, other_crtc);
6137                 if (IS_ERR(other_crtc_state))
6138                         return PTR_ERR(other_crtc_state);
6139
6140                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6141                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6142                         return -EINVAL;
6143                 }
6144                 return 0;
6145         default:
6146                 BUG();
6147         }
6148 }
6149
6150 #define RETRY 1
6151 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6152                                        struct intel_crtc_state *pipe_config)
6153 {
6154         struct drm_device *dev = intel_crtc->base.dev;
6155         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6156         int lane, link_bw, fdi_dotclock, ret;
6157         bool needs_recompute = false;
6158
6159 retry:
6160         /* FDI is a binary signal running at ~2.7GHz, encoding
6161          * each output octet as 10 bits. The actual frequency
6162          * is stored as a divider into a 100MHz clock, and the
6163          * mode pixel clock is stored in units of 1KHz.
6164          * Hence the bw of each lane in terms of the mode signal
6165          * is:
6166          */
6167         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6168
6169         fdi_dotclock = adjusted_mode->crtc_clock;
6170
6171         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6172                                            pipe_config->pipe_bpp);
6173
6174         pipe_config->fdi_lanes = lane;
6175
6176         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6177                                link_bw, &pipe_config->fdi_m_n, false);
6178
6179         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6180         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6181                 pipe_config->pipe_bpp -= 2*3;
6182                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6183                               pipe_config->pipe_bpp);
6184                 needs_recompute = true;
6185                 pipe_config->bw_constrained = true;
6186
6187                 goto retry;
6188         }
6189
6190         if (needs_recompute)
6191                 return RETRY;
6192
6193         return ret;
6194 }
6195
6196 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6197                                      struct intel_crtc_state *pipe_config)
6198 {
6199         if (pipe_config->ips_force_disable)
6200                 return false;
6201
6202         if (pipe_config->pipe_bpp > 24)
6203                 return false;
6204
6205         /* HSW can handle pixel rate up to cdclk? */
6206         if (IS_HASWELL(dev_priv))
6207                 return true;
6208
6209         /*
6210          * We compare against max which means we must take
6211          * the increased cdclk requirement into account when
6212          * calculating the new cdclk.
6213          *
6214          * Should measure whether using a lower cdclk w/o IPS
6215          */
6216         return pipe_config->pixel_rate <=
6217                 dev_priv->max_cdclk_freq * 95 / 100;
6218 }
6219
6220 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6221                                    struct intel_crtc_state *pipe_config)
6222 {
6223         struct drm_device *dev = crtc->base.dev;
6224         struct drm_i915_private *dev_priv = to_i915(dev);
6225
6226         pipe_config->ips_enabled = i915_modparams.enable_ips &&
6227                 hsw_crtc_supports_ips(crtc) &&
6228                 pipe_config_supports_ips(dev_priv, pipe_config);
6229 }
6230
6231 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6232 {
6233         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6234
6235         /* GDG double wide on either pipe, otherwise pipe A only */
6236         return INTEL_INFO(dev_priv)->gen < 4 &&
6237                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6238 }
6239
6240 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6241 {
6242         uint32_t pixel_rate;
6243
6244         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6245
6246         /*
6247          * We only use IF-ID interlacing. If we ever use
6248          * PF-ID we'll need to adjust the pixel_rate here.
6249          */
6250
6251         if (pipe_config->pch_pfit.enabled) {
6252                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6253                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6254
6255                 pipe_w = pipe_config->pipe_src_w;
6256                 pipe_h = pipe_config->pipe_src_h;
6257
6258                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6259                 pfit_h = pfit_size & 0xFFFF;
6260                 if (pipe_w < pfit_w)
6261                         pipe_w = pfit_w;
6262                 if (pipe_h < pfit_h)
6263                         pipe_h = pfit_h;
6264
6265                 if (WARN_ON(!pfit_w || !pfit_h))
6266                         return pixel_rate;
6267
6268                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6269                                      pfit_w * pfit_h);
6270         }
6271
6272         return pixel_rate;
6273 }
6274
6275 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6276 {
6277         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6278
6279         if (HAS_GMCH_DISPLAY(dev_priv))
6280                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6281                 crtc_state->pixel_rate =
6282                         crtc_state->base.adjusted_mode.crtc_clock;
6283         else
6284                 crtc_state->pixel_rate =
6285                         ilk_pipe_pixel_rate(crtc_state);
6286 }
6287
6288 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6289                                      struct intel_crtc_state *pipe_config)
6290 {
6291         struct drm_device *dev = crtc->base.dev;
6292         struct drm_i915_private *dev_priv = to_i915(dev);
6293         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6294         int clock_limit = dev_priv->max_dotclk_freq;
6295
6296         if (INTEL_GEN(dev_priv) < 4) {
6297                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6298
6299                 /*
6300                  * Enable double wide mode when the dot clock
6301                  * is > 90% of the (display) core speed.
6302                  */
6303                 if (intel_crtc_supports_double_wide(crtc) &&
6304                     adjusted_mode->crtc_clock > clock_limit) {
6305                         clock_limit = dev_priv->max_dotclk_freq;
6306                         pipe_config->double_wide = true;
6307                 }
6308         }
6309
6310         if (adjusted_mode->crtc_clock > clock_limit) {
6311                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6312                               adjusted_mode->crtc_clock, clock_limit,
6313                               yesno(pipe_config->double_wide));
6314                 return -EINVAL;
6315         }
6316
6317         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6318                 /*
6319                  * There is only one pipe CSC unit per pipe, and we need that
6320                  * for output conversion from RGB->YCBCR. So if CTM is already
6321                  * applied we can't support YCBCR420 output.
6322                  */
6323                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6324                 return -EINVAL;
6325         }
6326
6327         /*
6328          * Pipe horizontal size must be even in:
6329          * - DVO ganged mode
6330          * - LVDS dual channel mode
6331          * - Double wide pipe
6332          */
6333         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6334              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6335                 pipe_config->pipe_src_w &= ~1;
6336
6337         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6338          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6339          */
6340         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6341                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6342                 return -EINVAL;
6343
6344         intel_crtc_compute_pixel_rate(pipe_config);
6345
6346         if (HAS_IPS(dev_priv))
6347                 hsw_compute_ips_config(crtc, pipe_config);
6348
6349         if (pipe_config->has_pch_encoder)
6350                 return ironlake_fdi_compute_config(crtc, pipe_config);
6351
6352         return 0;
6353 }
6354
6355 static void
6356 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6357 {
6358         while (*num > DATA_LINK_M_N_MASK ||
6359                *den > DATA_LINK_M_N_MASK) {
6360                 *num >>= 1;
6361                 *den >>= 1;
6362         }
6363 }
6364
6365 static void compute_m_n(unsigned int m, unsigned int n,
6366                         uint32_t *ret_m, uint32_t *ret_n,
6367                         bool reduce_m_n)
6368 {
6369         /*
6370          * Reduce M/N as much as possible without loss in precision. Several DP
6371          * dongles in particular seem to be fussy about too large *link* M/N
6372          * values. The passed in values are more likely to have the least
6373          * significant bits zero than M after rounding below, so do this first.
6374          */
6375         if (reduce_m_n) {
6376                 while ((m & 1) == 0 && (n & 1) == 0) {
6377                         m >>= 1;
6378                         n >>= 1;
6379                 }
6380         }
6381
6382         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6383         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6384         intel_reduce_m_n_ratio(ret_m, ret_n);
6385 }
6386
6387 void
6388 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6389                        int pixel_clock, int link_clock,
6390                        struct intel_link_m_n *m_n,
6391                        bool reduce_m_n)
6392 {
6393         m_n->tu = 64;
6394
6395         compute_m_n(bits_per_pixel * pixel_clock,
6396                     link_clock * nlanes * 8,
6397                     &m_n->gmch_m, &m_n->gmch_n,
6398                     reduce_m_n);
6399
6400         compute_m_n(pixel_clock, link_clock,
6401                     &m_n->link_m, &m_n->link_n,
6402                     reduce_m_n);
6403 }
6404
6405 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6406 {
6407         if (i915_modparams.panel_use_ssc >= 0)
6408                 return i915_modparams.panel_use_ssc != 0;
6409         return dev_priv->vbt.lvds_use_ssc
6410                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6411 }
6412
6413 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6414 {
6415         return (1 << dpll->n) << 16 | dpll->m2;
6416 }
6417
6418 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6419 {
6420         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6421 }
6422
6423 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6424                                      struct intel_crtc_state *crtc_state,
6425                                      struct dpll *reduced_clock)
6426 {
6427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6428         u32 fp, fp2 = 0;
6429
6430         if (IS_PINEVIEW(dev_priv)) {
6431                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6432                 if (reduced_clock)
6433                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6434         } else {
6435                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6436                 if (reduced_clock)
6437                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6438         }
6439
6440         crtc_state->dpll_hw_state.fp0 = fp;
6441
6442         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6443             reduced_clock) {
6444                 crtc_state->dpll_hw_state.fp1 = fp2;
6445         } else {
6446                 crtc_state->dpll_hw_state.fp1 = fp;
6447         }
6448 }
6449
6450 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6451                 pipe)
6452 {
6453         u32 reg_val;
6454
6455         /*
6456          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6457          * and set it to a reasonable value instead.
6458          */
6459         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6460         reg_val &= 0xffffff00;
6461         reg_val |= 0x00000030;
6462         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6463
6464         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6465         reg_val &= 0x00ffffff;
6466         reg_val |= 0x8c000000;
6467         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6468
6469         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6470         reg_val &= 0xffffff00;
6471         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6472
6473         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6474         reg_val &= 0x00ffffff;
6475         reg_val |= 0xb0000000;
6476         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6477 }
6478
6479 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6480                                          struct intel_link_m_n *m_n)
6481 {
6482         struct drm_device *dev = crtc->base.dev;
6483         struct drm_i915_private *dev_priv = to_i915(dev);
6484         int pipe = crtc->pipe;
6485
6486         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6487         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6488         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6489         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6490 }
6491
6492 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6493                                          struct intel_link_m_n *m_n,
6494                                          struct intel_link_m_n *m2_n2)
6495 {
6496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6497         int pipe = crtc->pipe;
6498         enum transcoder transcoder = crtc->config->cpu_transcoder;
6499
6500         if (INTEL_GEN(dev_priv) >= 5) {
6501                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6502                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6503                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6504                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6505                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6506                  * for gen < 8) and if DRRS is supported (to make sure the
6507                  * registers are not unnecessarily accessed).
6508                  */
6509                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6510                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6511                         I915_WRITE(PIPE_DATA_M2(transcoder),
6512                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6513                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6514                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6515                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6516                 }
6517         } else {
6518                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6519                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6520                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6521                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6522         }
6523 }
6524
6525 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6526 {
6527         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6528
6529         if (m_n == M1_N1) {
6530                 dp_m_n = &crtc->config->dp_m_n;
6531                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6532         } else if (m_n == M2_N2) {
6533
6534                 /*
6535                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6536                  * needs to be programmed into M1_N1.
6537                  */
6538                 dp_m_n = &crtc->config->dp_m2_n2;
6539         } else {
6540                 DRM_ERROR("Unsupported divider value\n");
6541                 return;
6542         }
6543
6544         if (crtc->config->has_pch_encoder)
6545                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6546         else
6547                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6548 }
6549
6550 static void vlv_compute_dpll(struct intel_crtc *crtc,
6551                              struct intel_crtc_state *pipe_config)
6552 {
6553         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6554                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6555         if (crtc->pipe != PIPE_A)
6556                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6557
6558         /* DPLL not used with DSI, but still need the rest set up */
6559         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6560                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6561                         DPLL_EXT_BUFFER_ENABLE_VLV;
6562
6563         pipe_config->dpll_hw_state.dpll_md =
6564                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6565 }
6566
6567 static void chv_compute_dpll(struct intel_crtc *crtc,
6568                              struct intel_crtc_state *pipe_config)
6569 {
6570         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6571                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6572         if (crtc->pipe != PIPE_A)
6573                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6574
6575         /* DPLL not used with DSI, but still need the rest set up */
6576         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6577                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6578
6579         pipe_config->dpll_hw_state.dpll_md =
6580                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6581 }
6582
6583 static void vlv_prepare_pll(struct intel_crtc *crtc,
6584                             const struct intel_crtc_state *pipe_config)
6585 {
6586         struct drm_device *dev = crtc->base.dev;
6587         struct drm_i915_private *dev_priv = to_i915(dev);
6588         enum pipe pipe = crtc->pipe;
6589         u32 mdiv;
6590         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6591         u32 coreclk, reg_val;
6592
6593         /* Enable Refclk */
6594         I915_WRITE(DPLL(pipe),
6595                    pipe_config->dpll_hw_state.dpll &
6596                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6597
6598         /* No need to actually set up the DPLL with DSI */
6599         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6600                 return;
6601
6602         mutex_lock(&dev_priv->sb_lock);
6603
6604         bestn = pipe_config->dpll.n;
6605         bestm1 = pipe_config->dpll.m1;
6606         bestm2 = pipe_config->dpll.m2;
6607         bestp1 = pipe_config->dpll.p1;
6608         bestp2 = pipe_config->dpll.p2;
6609
6610         /* See eDP HDMI DPIO driver vbios notes doc */
6611
6612         /* PLL B needs special handling */
6613         if (pipe == PIPE_B)
6614                 vlv_pllb_recal_opamp(dev_priv, pipe);
6615
6616         /* Set up Tx target for periodic Rcomp update */
6617         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6618
6619         /* Disable target IRef on PLL */
6620         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6621         reg_val &= 0x00ffffff;
6622         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6623
6624         /* Disable fast lock */
6625         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6626
6627         /* Set idtafcrecal before PLL is enabled */
6628         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6629         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6630         mdiv |= ((bestn << DPIO_N_SHIFT));
6631         mdiv |= (1 << DPIO_K_SHIFT);
6632
6633         /*
6634          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6635          * but we don't support that).
6636          * Note: don't use the DAC post divider as it seems unstable.
6637          */
6638         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6639         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6640
6641         mdiv |= DPIO_ENABLE_CALIBRATION;
6642         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6643
6644         /* Set HBR and RBR LPF coefficients */
6645         if (pipe_config->port_clock == 162000 ||
6646             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6647             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6648                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6649                                  0x009f0003);
6650         else
6651                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6652                                  0x00d0000f);
6653
6654         if (intel_crtc_has_dp_encoder(pipe_config)) {
6655                 /* Use SSC source */
6656                 if (pipe == PIPE_A)
6657                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6658                                          0x0df40000);
6659                 else
6660                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6661                                          0x0df70000);
6662         } else { /* HDMI or VGA */
6663                 /* Use bend source */
6664                 if (pipe == PIPE_A)
6665                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6666                                          0x0df70000);
6667                 else
6668                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6669                                          0x0df40000);
6670         }
6671
6672         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6673         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6674         if (intel_crtc_has_dp_encoder(crtc->config))
6675                 coreclk |= 0x01000000;
6676         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6677
6678         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6679         mutex_unlock(&dev_priv->sb_lock);
6680 }
6681
6682 static void chv_prepare_pll(struct intel_crtc *crtc,
6683                             const struct intel_crtc_state *pipe_config)
6684 {
6685         struct drm_device *dev = crtc->base.dev;
6686         struct drm_i915_private *dev_priv = to_i915(dev);
6687         enum pipe pipe = crtc->pipe;
6688         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6689         u32 loopfilter, tribuf_calcntr;
6690         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6691         u32 dpio_val;
6692         int vco;
6693
6694         /* Enable Refclk and SSC */
6695         I915_WRITE(DPLL(pipe),
6696                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6697
6698         /* No need to actually set up the DPLL with DSI */
6699         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6700                 return;
6701
6702         bestn = pipe_config->dpll.n;
6703         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6704         bestm1 = pipe_config->dpll.m1;
6705         bestm2 = pipe_config->dpll.m2 >> 22;
6706         bestp1 = pipe_config->dpll.p1;
6707         bestp2 = pipe_config->dpll.p2;
6708         vco = pipe_config->dpll.vco;
6709         dpio_val = 0;
6710         loopfilter = 0;
6711
6712         mutex_lock(&dev_priv->sb_lock);
6713
6714         /* p1 and p2 divider */
6715         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6716                         5 << DPIO_CHV_S1_DIV_SHIFT |
6717                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6718                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6719                         1 << DPIO_CHV_K_DIV_SHIFT);
6720
6721         /* Feedback post-divider - m2 */
6722         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6723
6724         /* Feedback refclk divider - n and m1 */
6725         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6726                         DPIO_CHV_M1_DIV_BY_2 |
6727                         1 << DPIO_CHV_N_DIV_SHIFT);
6728
6729         /* M2 fraction division */
6730         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6731
6732         /* M2 fraction division enable */
6733         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6734         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6735         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6736         if (bestm2_frac)
6737                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6738         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6739
6740         /* Program digital lock detect threshold */
6741         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6742         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6743                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6744         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6745         if (!bestm2_frac)
6746                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6747         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6748
6749         /* Loop filter */
6750         if (vco == 5400000) {
6751                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6752                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6753                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6754                 tribuf_calcntr = 0x9;
6755         } else if (vco <= 6200000) {
6756                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6757                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6758                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6759                 tribuf_calcntr = 0x9;
6760         } else if (vco <= 6480000) {
6761                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6762                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6763                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6764                 tribuf_calcntr = 0x8;
6765         } else {
6766                 /* Not supported. Apply the same limits as in the max case */
6767                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6768                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6769                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6770                 tribuf_calcntr = 0;
6771         }
6772         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6773
6774         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6775         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6776         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6777         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6778
6779         /* AFC Recal */
6780         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6781                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6782                         DPIO_AFC_RECAL);
6783
6784         mutex_unlock(&dev_priv->sb_lock);
6785 }
6786
6787 /**
6788  * vlv_force_pll_on - forcibly enable just the PLL
6789  * @dev_priv: i915 private structure
6790  * @pipe: pipe PLL to enable
6791  * @dpll: PLL configuration
6792  *
6793  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6794  * in cases where we need the PLL enabled even when @pipe is not going to
6795  * be enabled.
6796  */
6797 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6798                      const struct dpll *dpll)
6799 {
6800         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6801         struct intel_crtc_state *pipe_config;
6802
6803         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6804         if (!pipe_config)
6805                 return -ENOMEM;
6806
6807         pipe_config->base.crtc = &crtc->base;
6808         pipe_config->pixel_multiplier = 1;
6809         pipe_config->dpll = *dpll;
6810
6811         if (IS_CHERRYVIEW(dev_priv)) {
6812                 chv_compute_dpll(crtc, pipe_config);
6813                 chv_prepare_pll(crtc, pipe_config);
6814                 chv_enable_pll(crtc, pipe_config);
6815         } else {
6816                 vlv_compute_dpll(crtc, pipe_config);
6817                 vlv_prepare_pll(crtc, pipe_config);
6818                 vlv_enable_pll(crtc, pipe_config);
6819         }
6820
6821         kfree(pipe_config);
6822
6823         return 0;
6824 }
6825
6826 /**
6827  * vlv_force_pll_off - forcibly disable just the PLL
6828  * @dev_priv: i915 private structure
6829  * @pipe: pipe PLL to disable
6830  *
6831  * Disable the PLL for @pipe. To be used in cases where we need
6832  * the PLL enabled even when @pipe is not going to be enabled.
6833  */
6834 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6835 {
6836         if (IS_CHERRYVIEW(dev_priv))
6837                 chv_disable_pll(dev_priv, pipe);
6838         else
6839                 vlv_disable_pll(dev_priv, pipe);
6840 }
6841
6842 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6843                               struct intel_crtc_state *crtc_state,
6844                               struct dpll *reduced_clock)
6845 {
6846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6847         u32 dpll;
6848         struct dpll *clock = &crtc_state->dpll;
6849
6850         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6851
6852         dpll = DPLL_VGA_MODE_DIS;
6853
6854         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6855                 dpll |= DPLLB_MODE_LVDS;
6856         else
6857                 dpll |= DPLLB_MODE_DAC_SERIAL;
6858
6859         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6860             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6861                 dpll |= (crtc_state->pixel_multiplier - 1)
6862                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6863         }
6864
6865         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6866             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6867                 dpll |= DPLL_SDVO_HIGH_SPEED;
6868
6869         if (intel_crtc_has_dp_encoder(crtc_state))
6870                 dpll |= DPLL_SDVO_HIGH_SPEED;
6871
6872         /* compute bitmask from p1 value */
6873         if (IS_PINEVIEW(dev_priv))
6874                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6875         else {
6876                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6877                 if (IS_G4X(dev_priv) && reduced_clock)
6878                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6879         }
6880         switch (clock->p2) {
6881         case 5:
6882                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6883                 break;
6884         case 7:
6885                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6886                 break;
6887         case 10:
6888                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6889                 break;
6890         case 14:
6891                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6892                 break;
6893         }
6894         if (INTEL_GEN(dev_priv) >= 4)
6895                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6896
6897         if (crtc_state->sdvo_tv_clock)
6898                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6899         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6900                  intel_panel_use_ssc(dev_priv))
6901                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6902         else
6903                 dpll |= PLL_REF_INPUT_DREFCLK;
6904
6905         dpll |= DPLL_VCO_ENABLE;
6906         crtc_state->dpll_hw_state.dpll = dpll;
6907
6908         if (INTEL_GEN(dev_priv) >= 4) {
6909                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6910                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6911                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6912         }
6913 }
6914
6915 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6916                               struct intel_crtc_state *crtc_state,
6917                               struct dpll *reduced_clock)
6918 {
6919         struct drm_device *dev = crtc->base.dev;
6920         struct drm_i915_private *dev_priv = to_i915(dev);
6921         u32 dpll;
6922         struct dpll *clock = &crtc_state->dpll;
6923
6924         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6925
6926         dpll = DPLL_VGA_MODE_DIS;
6927
6928         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6929                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6930         } else {
6931                 if (clock->p1 == 2)
6932                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6933                 else
6934                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6935                 if (clock->p2 == 4)
6936                         dpll |= PLL_P2_DIVIDE_BY_4;
6937         }
6938
6939         if (!IS_I830(dev_priv) &&
6940             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6941                 dpll |= DPLL_DVO_2X_MODE;
6942
6943         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6944             intel_panel_use_ssc(dev_priv))
6945                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6946         else
6947                 dpll |= PLL_REF_INPUT_DREFCLK;
6948
6949         dpll |= DPLL_VCO_ENABLE;
6950         crtc_state->dpll_hw_state.dpll = dpll;
6951 }
6952
6953 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6954 {
6955         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6956         enum pipe pipe = intel_crtc->pipe;
6957         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6958         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6959         uint32_t crtc_vtotal, crtc_vblank_end;
6960         int vsyncshift = 0;
6961
6962         /* We need to be careful not to changed the adjusted mode, for otherwise
6963          * the hw state checker will get angry at the mismatch. */
6964         crtc_vtotal = adjusted_mode->crtc_vtotal;
6965         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6966
6967         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6968                 /* the chip adds 2 halflines automatically */
6969                 crtc_vtotal -= 1;
6970                 crtc_vblank_end -= 1;
6971
6972                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6973                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6974                 else
6975                         vsyncshift = adjusted_mode->crtc_hsync_start -
6976                                 adjusted_mode->crtc_htotal / 2;
6977                 if (vsyncshift < 0)
6978                         vsyncshift += adjusted_mode->crtc_htotal;
6979         }
6980
6981         if (INTEL_GEN(dev_priv) > 3)
6982                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6983
6984         I915_WRITE(HTOTAL(cpu_transcoder),
6985                    (adjusted_mode->crtc_hdisplay - 1) |
6986                    ((adjusted_mode->crtc_htotal - 1) << 16));
6987         I915_WRITE(HBLANK(cpu_transcoder),
6988                    (adjusted_mode->crtc_hblank_start - 1) |
6989                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6990         I915_WRITE(HSYNC(cpu_transcoder),
6991                    (adjusted_mode->crtc_hsync_start - 1) |
6992                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6993
6994         I915_WRITE(VTOTAL(cpu_transcoder),
6995                    (adjusted_mode->crtc_vdisplay - 1) |
6996                    ((crtc_vtotal - 1) << 16));
6997         I915_WRITE(VBLANK(cpu_transcoder),
6998                    (adjusted_mode->crtc_vblank_start - 1) |
6999                    ((crtc_vblank_end - 1) << 16));
7000         I915_WRITE(VSYNC(cpu_transcoder),
7001                    (adjusted_mode->crtc_vsync_start - 1) |
7002                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7003
7004         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7005          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7006          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7007          * bits. */
7008         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7009             (pipe == PIPE_B || pipe == PIPE_C))
7010                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7011
7012 }
7013
7014 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7015 {
7016         struct drm_device *dev = intel_crtc->base.dev;
7017         struct drm_i915_private *dev_priv = to_i915(dev);
7018         enum pipe pipe = intel_crtc->pipe;
7019
7020         /* pipesrc controls the size that is scaled from, which should
7021          * always be the user's requested size.
7022          */
7023         I915_WRITE(PIPESRC(pipe),
7024                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7025                    (intel_crtc->config->pipe_src_h - 1));
7026 }
7027
7028 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7029                                    struct intel_crtc_state *pipe_config)
7030 {
7031         struct drm_device *dev = crtc->base.dev;
7032         struct drm_i915_private *dev_priv = to_i915(dev);
7033         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7034         uint32_t tmp;
7035
7036         tmp = I915_READ(HTOTAL(cpu_transcoder));
7037         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7038         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7039         tmp = I915_READ(HBLANK(cpu_transcoder));
7040         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7041         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7042         tmp = I915_READ(HSYNC(cpu_transcoder));
7043         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7044         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7045
7046         tmp = I915_READ(VTOTAL(cpu_transcoder));
7047         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7048         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7049         tmp = I915_READ(VBLANK(cpu_transcoder));
7050         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7051         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7052         tmp = I915_READ(VSYNC(cpu_transcoder));
7053         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7054         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7055
7056         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7057                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7058                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7059                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7060         }
7061 }
7062
7063 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7064                                     struct intel_crtc_state *pipe_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = to_i915(dev);
7068         u32 tmp;
7069
7070         tmp = I915_READ(PIPESRC(crtc->pipe));
7071         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7072         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7073
7074         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7075         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7076 }
7077
7078 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7079                                  struct intel_crtc_state *pipe_config)
7080 {
7081         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7082         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7083         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7084         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7085
7086         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7087         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7088         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7089         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7090
7091         mode->flags = pipe_config->base.adjusted_mode.flags;
7092         mode->type = DRM_MODE_TYPE_DRIVER;
7093
7094         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7095
7096         mode->hsync = drm_mode_hsync(mode);
7097         mode->vrefresh = drm_mode_vrefresh(mode);
7098         drm_mode_set_name(mode);
7099 }
7100
7101 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7102 {
7103         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7104         uint32_t pipeconf;
7105
7106         pipeconf = 0;
7107
7108         /* we keep both pipes enabled on 830 */
7109         if (IS_I830(dev_priv))
7110                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7111
7112         if (intel_crtc->config->double_wide)
7113                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7114
7115         /* only g4x and later have fancy bpc/dither controls */
7116         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7117             IS_CHERRYVIEW(dev_priv)) {
7118                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7119                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7120                         pipeconf |= PIPECONF_DITHER_EN |
7121                                     PIPECONF_DITHER_TYPE_SP;
7122
7123                 switch (intel_crtc->config->pipe_bpp) {
7124                 case 18:
7125                         pipeconf |= PIPECONF_6BPC;
7126                         break;
7127                 case 24:
7128                         pipeconf |= PIPECONF_8BPC;
7129                         break;
7130                 case 30:
7131                         pipeconf |= PIPECONF_10BPC;
7132                         break;
7133                 default:
7134                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7135                         BUG();
7136                 }
7137         }
7138
7139         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7140                 if (INTEL_GEN(dev_priv) < 4 ||
7141                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7142                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7143                 else
7144                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7145         } else
7146                 pipeconf |= PIPECONF_PROGRESSIVE;
7147
7148         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7149              intel_crtc->config->limited_color_range)
7150                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7151
7152         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7153         POSTING_READ(PIPECONF(intel_crtc->pipe));
7154 }
7155
7156 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7157                                    struct intel_crtc_state *crtc_state)
7158 {
7159         struct drm_device *dev = crtc->base.dev;
7160         struct drm_i915_private *dev_priv = to_i915(dev);
7161         const struct intel_limit *limit;
7162         int refclk = 48000;
7163
7164         memset(&crtc_state->dpll_hw_state, 0,
7165                sizeof(crtc_state->dpll_hw_state));
7166
7167         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7168                 if (intel_panel_use_ssc(dev_priv)) {
7169                         refclk = dev_priv->vbt.lvds_ssc_freq;
7170                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7171                 }
7172
7173                 limit = &intel_limits_i8xx_lvds;
7174         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7175                 limit = &intel_limits_i8xx_dvo;
7176         } else {
7177                 limit = &intel_limits_i8xx_dac;
7178         }
7179
7180         if (!crtc_state->clock_set &&
7181             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7182                                  refclk, NULL, &crtc_state->dpll)) {
7183                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7184                 return -EINVAL;
7185         }
7186
7187         i8xx_compute_dpll(crtc, crtc_state, NULL);
7188
7189         return 0;
7190 }
7191
7192 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7193                                   struct intel_crtc_state *crtc_state)
7194 {
7195         struct drm_device *dev = crtc->base.dev;
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         const struct intel_limit *limit;
7198         int refclk = 96000;
7199
7200         memset(&crtc_state->dpll_hw_state, 0,
7201                sizeof(crtc_state->dpll_hw_state));
7202
7203         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7204                 if (intel_panel_use_ssc(dev_priv)) {
7205                         refclk = dev_priv->vbt.lvds_ssc_freq;
7206                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7207                 }
7208
7209                 if (intel_is_dual_link_lvds(dev))
7210                         limit = &intel_limits_g4x_dual_channel_lvds;
7211                 else
7212                         limit = &intel_limits_g4x_single_channel_lvds;
7213         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7214                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7215                 limit = &intel_limits_g4x_hdmi;
7216         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7217                 limit = &intel_limits_g4x_sdvo;
7218         } else {
7219                 /* The option is for other outputs */
7220                 limit = &intel_limits_i9xx_sdvo;
7221         }
7222
7223         if (!crtc_state->clock_set &&
7224             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7225                                 refclk, NULL, &crtc_state->dpll)) {
7226                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7227                 return -EINVAL;
7228         }
7229
7230         i9xx_compute_dpll(crtc, crtc_state, NULL);
7231
7232         return 0;
7233 }
7234
7235 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7236                                   struct intel_crtc_state *crtc_state)
7237 {
7238         struct drm_device *dev = crtc->base.dev;
7239         struct drm_i915_private *dev_priv = to_i915(dev);
7240         const struct intel_limit *limit;
7241         int refclk = 96000;
7242
7243         memset(&crtc_state->dpll_hw_state, 0,
7244                sizeof(crtc_state->dpll_hw_state));
7245
7246         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7247                 if (intel_panel_use_ssc(dev_priv)) {
7248                         refclk = dev_priv->vbt.lvds_ssc_freq;
7249                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7250                 }
7251
7252                 limit = &intel_limits_pineview_lvds;
7253         } else {
7254                 limit = &intel_limits_pineview_sdvo;
7255         }
7256
7257         if (!crtc_state->clock_set &&
7258             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7259                                 refclk, NULL, &crtc_state->dpll)) {
7260                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7261                 return -EINVAL;
7262         }
7263
7264         i9xx_compute_dpll(crtc, crtc_state, NULL);
7265
7266         return 0;
7267 }
7268
7269 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7270                                    struct intel_crtc_state *crtc_state)
7271 {
7272         struct drm_device *dev = crtc->base.dev;
7273         struct drm_i915_private *dev_priv = to_i915(dev);
7274         const struct intel_limit *limit;
7275         int refclk = 96000;
7276
7277         memset(&crtc_state->dpll_hw_state, 0,
7278                sizeof(crtc_state->dpll_hw_state));
7279
7280         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7281                 if (intel_panel_use_ssc(dev_priv)) {
7282                         refclk = dev_priv->vbt.lvds_ssc_freq;
7283                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7284                 }
7285
7286                 limit = &intel_limits_i9xx_lvds;
7287         } else {
7288                 limit = &intel_limits_i9xx_sdvo;
7289         }
7290
7291         if (!crtc_state->clock_set &&
7292             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7293                                  refclk, NULL, &crtc_state->dpll)) {
7294                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7295                 return -EINVAL;
7296         }
7297
7298         i9xx_compute_dpll(crtc, crtc_state, NULL);
7299
7300         return 0;
7301 }
7302
7303 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7304                                   struct intel_crtc_state *crtc_state)
7305 {
7306         int refclk = 100000;
7307         const struct intel_limit *limit = &intel_limits_chv;
7308
7309         memset(&crtc_state->dpll_hw_state, 0,
7310                sizeof(crtc_state->dpll_hw_state));
7311
7312         if (!crtc_state->clock_set &&
7313             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7314                                 refclk, NULL, &crtc_state->dpll)) {
7315                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7316                 return -EINVAL;
7317         }
7318
7319         chv_compute_dpll(crtc, crtc_state);
7320
7321         return 0;
7322 }
7323
7324 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7325                                   struct intel_crtc_state *crtc_state)
7326 {
7327         int refclk = 100000;
7328         const struct intel_limit *limit = &intel_limits_vlv;
7329
7330         memset(&crtc_state->dpll_hw_state, 0,
7331                sizeof(crtc_state->dpll_hw_state));
7332
7333         if (!crtc_state->clock_set &&
7334             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7335                                 refclk, NULL, &crtc_state->dpll)) {
7336                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7337                 return -EINVAL;
7338         }
7339
7340         vlv_compute_dpll(crtc, crtc_state);
7341
7342         return 0;
7343 }
7344
7345 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7346                                  struct intel_crtc_state *pipe_config)
7347 {
7348         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7349         uint32_t tmp;
7350
7351         if (INTEL_GEN(dev_priv) <= 3 &&
7352             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7353                 return;
7354
7355         tmp = I915_READ(PFIT_CONTROL);
7356         if (!(tmp & PFIT_ENABLE))
7357                 return;
7358
7359         /* Check whether the pfit is attached to our pipe. */
7360         if (INTEL_GEN(dev_priv) < 4) {
7361                 if (crtc->pipe != PIPE_B)
7362                         return;
7363         } else {
7364                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7365                         return;
7366         }
7367
7368         pipe_config->gmch_pfit.control = tmp;
7369         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7370 }
7371
7372 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7373                                struct intel_crtc_state *pipe_config)
7374 {
7375         struct drm_device *dev = crtc->base.dev;
7376         struct drm_i915_private *dev_priv = to_i915(dev);
7377         int pipe = pipe_config->cpu_transcoder;
7378         struct dpll clock;
7379         u32 mdiv;
7380         int refclk = 100000;
7381
7382         /* In case of DSI, DPLL will not be used */
7383         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7384                 return;
7385
7386         mutex_lock(&dev_priv->sb_lock);
7387         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7388         mutex_unlock(&dev_priv->sb_lock);
7389
7390         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7391         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7392         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7393         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7394         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7395
7396         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7397 }
7398
7399 static void
7400 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7401                               struct intel_initial_plane_config *plane_config)
7402 {
7403         struct drm_device *dev = crtc->base.dev;
7404         struct drm_i915_private *dev_priv = to_i915(dev);
7405         u32 val, base, offset;
7406         int pipe = crtc->pipe, plane = crtc->plane;
7407         int fourcc, pixel_format;
7408         unsigned int aligned_height;
7409         struct drm_framebuffer *fb;
7410         struct intel_framebuffer *intel_fb;
7411
7412         val = I915_READ(DSPCNTR(plane));
7413         if (!(val & DISPLAY_PLANE_ENABLE))
7414                 return;
7415
7416         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7417         if (!intel_fb) {
7418                 DRM_DEBUG_KMS("failed to alloc fb\n");
7419                 return;
7420         }
7421
7422         fb = &intel_fb->base;
7423
7424         fb->dev = dev;
7425
7426         if (INTEL_GEN(dev_priv) >= 4) {
7427                 if (val & DISPPLANE_TILED) {
7428                         plane_config->tiling = I915_TILING_X;
7429                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7430                 }
7431         }
7432
7433         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7434         fourcc = i9xx_format_to_fourcc(pixel_format);
7435         fb->format = drm_format_info(fourcc);
7436
7437         if (INTEL_GEN(dev_priv) >= 4) {
7438                 if (plane_config->tiling)
7439                         offset = I915_READ(DSPTILEOFF(plane));
7440                 else
7441                         offset = I915_READ(DSPLINOFF(plane));
7442                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7443         } else {
7444                 base = I915_READ(DSPADDR(plane));
7445         }
7446         plane_config->base = base;
7447
7448         val = I915_READ(PIPESRC(pipe));
7449         fb->width = ((val >> 16) & 0xfff) + 1;
7450         fb->height = ((val >> 0) & 0xfff) + 1;
7451
7452         val = I915_READ(DSPSTRIDE(pipe));
7453         fb->pitches[0] = val & 0xffffffc0;
7454
7455         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7456
7457         plane_config->size = fb->pitches[0] * aligned_height;
7458
7459         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7460                       pipe_name(pipe), plane, fb->width, fb->height,
7461                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7462                       plane_config->size);
7463
7464         plane_config->fb = intel_fb;
7465 }
7466
7467 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7468                                struct intel_crtc_state *pipe_config)
7469 {
7470         struct drm_device *dev = crtc->base.dev;
7471         struct drm_i915_private *dev_priv = to_i915(dev);
7472         int pipe = pipe_config->cpu_transcoder;
7473         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7474         struct dpll clock;
7475         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7476         int refclk = 100000;
7477
7478         /* In case of DSI, DPLL will not be used */
7479         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7480                 return;
7481
7482         mutex_lock(&dev_priv->sb_lock);
7483         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7484         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7485         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7486         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7487         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7488         mutex_unlock(&dev_priv->sb_lock);
7489
7490         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7491         clock.m2 = (pll_dw0 & 0xff) << 22;
7492         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7493                 clock.m2 |= pll_dw2 & 0x3fffff;
7494         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7495         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7496         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7497
7498         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7499 }
7500
7501 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7502                                  struct intel_crtc_state *pipe_config)
7503 {
7504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7505         enum intel_display_power_domain power_domain;
7506         uint32_t tmp;
7507         bool ret;
7508
7509         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7510         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7511                 return false;
7512
7513         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7514         pipe_config->shared_dpll = NULL;
7515
7516         ret = false;
7517
7518         tmp = I915_READ(PIPECONF(crtc->pipe));
7519         if (!(tmp & PIPECONF_ENABLE))
7520                 goto out;
7521
7522         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7523             IS_CHERRYVIEW(dev_priv)) {
7524                 switch (tmp & PIPECONF_BPC_MASK) {
7525                 case PIPECONF_6BPC:
7526                         pipe_config->pipe_bpp = 18;
7527                         break;
7528                 case PIPECONF_8BPC:
7529                         pipe_config->pipe_bpp = 24;
7530                         break;
7531                 case PIPECONF_10BPC:
7532                         pipe_config->pipe_bpp = 30;
7533                         break;
7534                 default:
7535                         break;
7536                 }
7537         }
7538
7539         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7540             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7541                 pipe_config->limited_color_range = true;
7542
7543         if (INTEL_GEN(dev_priv) < 4)
7544                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7545
7546         intel_get_pipe_timings(crtc, pipe_config);
7547         intel_get_pipe_src_size(crtc, pipe_config);
7548
7549         i9xx_get_pfit_config(crtc, pipe_config);
7550
7551         if (INTEL_GEN(dev_priv) >= 4) {
7552                 /* No way to read it out on pipes B and C */
7553                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7554                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7555                 else
7556                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7557                 pipe_config->pixel_multiplier =
7558                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7559                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7560                 pipe_config->dpll_hw_state.dpll_md = tmp;
7561         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7562                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7563                 tmp = I915_READ(DPLL(crtc->pipe));
7564                 pipe_config->pixel_multiplier =
7565                         ((tmp & SDVO_MULTIPLIER_MASK)
7566                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7567         } else {
7568                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7569                  * port and will be fixed up in the encoder->get_config
7570                  * function. */
7571                 pipe_config->pixel_multiplier = 1;
7572         }
7573         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7574         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7575                 /*
7576                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7577                  * on 830. Filter it out here so that we don't
7578                  * report errors due to that.
7579                  */
7580                 if (IS_I830(dev_priv))
7581                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7582
7583                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7584                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7585         } else {
7586                 /* Mask out read-only status bits. */
7587                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7588                                                      DPLL_PORTC_READY_MASK |
7589                                                      DPLL_PORTB_READY_MASK);
7590         }
7591
7592         if (IS_CHERRYVIEW(dev_priv))
7593                 chv_crtc_clock_get(crtc, pipe_config);
7594         else if (IS_VALLEYVIEW(dev_priv))
7595                 vlv_crtc_clock_get(crtc, pipe_config);
7596         else
7597                 i9xx_crtc_clock_get(crtc, pipe_config);
7598
7599         /*
7600          * Normally the dotclock is filled in by the encoder .get_config()
7601          * but in case the pipe is enabled w/o any ports we need a sane
7602          * default.
7603          */
7604         pipe_config->base.adjusted_mode.crtc_clock =
7605                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7606
7607         ret = true;
7608
7609 out:
7610         intel_display_power_put(dev_priv, power_domain);
7611
7612         return ret;
7613 }
7614
7615 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7616 {
7617         struct intel_encoder *encoder;
7618         int i;
7619         u32 val, final;
7620         bool has_lvds = false;
7621         bool has_cpu_edp = false;
7622         bool has_panel = false;
7623         bool has_ck505 = false;
7624         bool can_ssc = false;
7625         bool using_ssc_source = false;
7626
7627         /* We need to take the global config into account */
7628         for_each_intel_encoder(&dev_priv->drm, encoder) {
7629                 switch (encoder->type) {
7630                 case INTEL_OUTPUT_LVDS:
7631                         has_panel = true;
7632                         has_lvds = true;
7633                         break;
7634                 case INTEL_OUTPUT_EDP:
7635                         has_panel = true;
7636                         if (encoder->port == PORT_A)
7637                                 has_cpu_edp = true;
7638                         break;
7639                 default:
7640                         break;
7641                 }
7642         }
7643
7644         if (HAS_PCH_IBX(dev_priv)) {
7645                 has_ck505 = dev_priv->vbt.display_clock_mode;
7646                 can_ssc = has_ck505;
7647         } else {
7648                 has_ck505 = false;
7649                 can_ssc = true;
7650         }
7651
7652         /* Check if any DPLLs are using the SSC source */
7653         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7654                 u32 temp = I915_READ(PCH_DPLL(i));
7655
7656                 if (!(temp & DPLL_VCO_ENABLE))
7657                         continue;
7658
7659                 if ((temp & PLL_REF_INPUT_MASK) ==
7660                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7661                         using_ssc_source = true;
7662                         break;
7663                 }
7664         }
7665
7666         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7667                       has_panel, has_lvds, has_ck505, using_ssc_source);
7668
7669         /* Ironlake: try to setup display ref clock before DPLL
7670          * enabling. This is only under driver's control after
7671          * PCH B stepping, previous chipset stepping should be
7672          * ignoring this setting.
7673          */
7674         val = I915_READ(PCH_DREF_CONTROL);
7675
7676         /* As we must carefully and slowly disable/enable each source in turn,
7677          * compute the final state we want first and check if we need to
7678          * make any changes at all.
7679          */
7680         final = val;
7681         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7682         if (has_ck505)
7683                 final |= DREF_NONSPREAD_CK505_ENABLE;
7684         else
7685                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7686
7687         final &= ~DREF_SSC_SOURCE_MASK;
7688         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7689         final &= ~DREF_SSC1_ENABLE;
7690
7691         if (has_panel) {
7692                 final |= DREF_SSC_SOURCE_ENABLE;
7693
7694                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7695                         final |= DREF_SSC1_ENABLE;
7696
7697                 if (has_cpu_edp) {
7698                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7699                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7700                         else
7701                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7702                 } else
7703                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7704         } else if (using_ssc_source) {
7705                 final |= DREF_SSC_SOURCE_ENABLE;
7706                 final |= DREF_SSC1_ENABLE;
7707         }
7708
7709         if (final == val)
7710                 return;
7711
7712         /* Always enable nonspread source */
7713         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7714
7715         if (has_ck505)
7716                 val |= DREF_NONSPREAD_CK505_ENABLE;
7717         else
7718                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7719
7720         if (has_panel) {
7721                 val &= ~DREF_SSC_SOURCE_MASK;
7722                 val |= DREF_SSC_SOURCE_ENABLE;
7723
7724                 /* SSC must be turned on before enabling the CPU output  */
7725                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7726                         DRM_DEBUG_KMS("Using SSC on panel\n");
7727                         val |= DREF_SSC1_ENABLE;
7728                 } else
7729                         val &= ~DREF_SSC1_ENABLE;
7730
7731                 /* Get SSC going before enabling the outputs */
7732                 I915_WRITE(PCH_DREF_CONTROL, val);
7733                 POSTING_READ(PCH_DREF_CONTROL);
7734                 udelay(200);
7735
7736                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7737
7738                 /* Enable CPU source on CPU attached eDP */
7739                 if (has_cpu_edp) {
7740                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7741                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7742                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7743                         } else
7744                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7745                 } else
7746                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7747
7748                 I915_WRITE(PCH_DREF_CONTROL, val);
7749                 POSTING_READ(PCH_DREF_CONTROL);
7750                 udelay(200);
7751         } else {
7752                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7753
7754                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7755
7756                 /* Turn off CPU output */
7757                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7758
7759                 I915_WRITE(PCH_DREF_CONTROL, val);
7760                 POSTING_READ(PCH_DREF_CONTROL);
7761                 udelay(200);
7762
7763                 if (!using_ssc_source) {
7764                         DRM_DEBUG_KMS("Disabling SSC source\n");
7765
7766                         /* Turn off the SSC source */
7767                         val &= ~DREF_SSC_SOURCE_MASK;
7768                         val |= DREF_SSC_SOURCE_DISABLE;
7769
7770                         /* Turn off SSC1 */
7771                         val &= ~DREF_SSC1_ENABLE;
7772
7773                         I915_WRITE(PCH_DREF_CONTROL, val);
7774                         POSTING_READ(PCH_DREF_CONTROL);
7775                         udelay(200);
7776                 }
7777         }
7778
7779         BUG_ON(val != final);
7780 }
7781
7782 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7783 {
7784         uint32_t tmp;
7785
7786         tmp = I915_READ(SOUTH_CHICKEN2);
7787         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7788         I915_WRITE(SOUTH_CHICKEN2, tmp);
7789
7790         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7791                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7792                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7793
7794         tmp = I915_READ(SOUTH_CHICKEN2);
7795         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7796         I915_WRITE(SOUTH_CHICKEN2, tmp);
7797
7798         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7799                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7800                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7801 }
7802
7803 /* WaMPhyProgramming:hsw */
7804 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7805 {
7806         uint32_t tmp;
7807
7808         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7809         tmp &= ~(0xFF << 24);
7810         tmp |= (0x12 << 24);
7811         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7812
7813         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7814         tmp |= (1 << 11);
7815         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7816
7817         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7818         tmp |= (1 << 11);
7819         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7820
7821         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7822         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7823         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7824
7825         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7826         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7827         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7828
7829         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7830         tmp &= ~(7 << 13);
7831         tmp |= (5 << 13);
7832         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7833
7834         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7835         tmp &= ~(7 << 13);
7836         tmp |= (5 << 13);
7837         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7838
7839         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7840         tmp &= ~0xFF;
7841         tmp |= 0x1C;
7842         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7843
7844         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7845         tmp &= ~0xFF;
7846         tmp |= 0x1C;
7847         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7848
7849         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7850         tmp &= ~(0xFF << 16);
7851         tmp |= (0x1C << 16);
7852         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7853
7854         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7855         tmp &= ~(0xFF << 16);
7856         tmp |= (0x1C << 16);
7857         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7858
7859         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7860         tmp |= (1 << 27);
7861         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7862
7863         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7864         tmp |= (1 << 27);
7865         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7866
7867         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7868         tmp &= ~(0xF << 28);
7869         tmp |= (4 << 28);
7870         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7871
7872         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7873         tmp &= ~(0xF << 28);
7874         tmp |= (4 << 28);
7875         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7876 }
7877
7878 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7879  * Programming" based on the parameters passed:
7880  * - Sequence to enable CLKOUT_DP
7881  * - Sequence to enable CLKOUT_DP without spread
7882  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7883  */
7884 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7885                                  bool with_spread, bool with_fdi)
7886 {
7887         uint32_t reg, tmp;
7888
7889         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7890                 with_spread = true;
7891         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7892             with_fdi, "LP PCH doesn't have FDI\n"))
7893                 with_fdi = false;
7894
7895         mutex_lock(&dev_priv->sb_lock);
7896
7897         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7898         tmp &= ~SBI_SSCCTL_DISABLE;
7899         tmp |= SBI_SSCCTL_PATHALT;
7900         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7901
7902         udelay(24);
7903
7904         if (with_spread) {
7905                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7906                 tmp &= ~SBI_SSCCTL_PATHALT;
7907                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7908
7909                 if (with_fdi) {
7910                         lpt_reset_fdi_mphy(dev_priv);
7911                         lpt_program_fdi_mphy(dev_priv);
7912                 }
7913         }
7914
7915         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7916         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7917         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7918         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7919
7920         mutex_unlock(&dev_priv->sb_lock);
7921 }
7922
7923 /* Sequence to disable CLKOUT_DP */
7924 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7925 {
7926         uint32_t reg, tmp;
7927
7928         mutex_lock(&dev_priv->sb_lock);
7929
7930         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7931         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7932         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7933         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7934
7935         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7936         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7937                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7938                         tmp |= SBI_SSCCTL_PATHALT;
7939                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7940                         udelay(32);
7941                 }
7942                 tmp |= SBI_SSCCTL_DISABLE;
7943                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7944         }
7945
7946         mutex_unlock(&dev_priv->sb_lock);
7947 }
7948
7949 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7950
7951 static const uint16_t sscdivintphase[] = {
7952         [BEND_IDX( 50)] = 0x3B23,
7953         [BEND_IDX( 45)] = 0x3B23,
7954         [BEND_IDX( 40)] = 0x3C23,
7955         [BEND_IDX( 35)] = 0x3C23,
7956         [BEND_IDX( 30)] = 0x3D23,
7957         [BEND_IDX( 25)] = 0x3D23,
7958         [BEND_IDX( 20)] = 0x3E23,
7959         [BEND_IDX( 15)] = 0x3E23,
7960         [BEND_IDX( 10)] = 0x3F23,
7961         [BEND_IDX(  5)] = 0x3F23,
7962         [BEND_IDX(  0)] = 0x0025,
7963         [BEND_IDX( -5)] = 0x0025,
7964         [BEND_IDX(-10)] = 0x0125,
7965         [BEND_IDX(-15)] = 0x0125,
7966         [BEND_IDX(-20)] = 0x0225,
7967         [BEND_IDX(-25)] = 0x0225,
7968         [BEND_IDX(-30)] = 0x0325,
7969         [BEND_IDX(-35)] = 0x0325,
7970         [BEND_IDX(-40)] = 0x0425,
7971         [BEND_IDX(-45)] = 0x0425,
7972         [BEND_IDX(-50)] = 0x0525,
7973 };
7974
7975 /*
7976  * Bend CLKOUT_DP
7977  * steps -50 to 50 inclusive, in steps of 5
7978  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7979  * change in clock period = -(steps / 10) * 5.787 ps
7980  */
7981 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7982 {
7983         uint32_t tmp;
7984         int idx = BEND_IDX(steps);
7985
7986         if (WARN_ON(steps % 5 != 0))
7987                 return;
7988
7989         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7990                 return;
7991
7992         mutex_lock(&dev_priv->sb_lock);
7993
7994         if (steps % 10 != 0)
7995                 tmp = 0xAAAAAAAB;
7996         else
7997                 tmp = 0x00000000;
7998         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7999
8000         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8001         tmp &= 0xffff0000;
8002         tmp |= sscdivintphase[idx];
8003         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8004
8005         mutex_unlock(&dev_priv->sb_lock);
8006 }
8007
8008 #undef BEND_IDX
8009
8010 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8011 {
8012         struct intel_encoder *encoder;
8013         bool has_vga = false;
8014
8015         for_each_intel_encoder(&dev_priv->drm, encoder) {
8016                 switch (encoder->type) {
8017                 case INTEL_OUTPUT_ANALOG:
8018                         has_vga = true;
8019                         break;
8020                 default:
8021                         break;
8022                 }
8023         }
8024
8025         if (has_vga) {
8026                 lpt_bend_clkout_dp(dev_priv, 0);
8027                 lpt_enable_clkout_dp(dev_priv, true, true);
8028         } else {
8029                 lpt_disable_clkout_dp(dev_priv);
8030         }
8031 }
8032
8033 /*
8034  * Initialize reference clocks when the driver loads
8035  */
8036 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8037 {
8038         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8039                 ironlake_init_pch_refclk(dev_priv);
8040         else if (HAS_PCH_LPT(dev_priv))
8041                 lpt_init_pch_refclk(dev_priv);
8042 }
8043
8044 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8045 {
8046         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8048         int pipe = intel_crtc->pipe;
8049         uint32_t val;
8050
8051         val = 0;
8052
8053         switch (intel_crtc->config->pipe_bpp) {
8054         case 18:
8055                 val |= PIPECONF_6BPC;
8056                 break;
8057         case 24:
8058                 val |= PIPECONF_8BPC;
8059                 break;
8060         case 30:
8061                 val |= PIPECONF_10BPC;
8062                 break;
8063         case 36:
8064                 val |= PIPECONF_12BPC;
8065                 break;
8066         default:
8067                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8068                 BUG();
8069         }
8070
8071         if (intel_crtc->config->dither)
8072                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8073
8074         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8075                 val |= PIPECONF_INTERLACED_ILK;
8076         else
8077                 val |= PIPECONF_PROGRESSIVE;
8078
8079         if (intel_crtc->config->limited_color_range)
8080                 val |= PIPECONF_COLOR_RANGE_SELECT;
8081
8082         I915_WRITE(PIPECONF(pipe), val);
8083         POSTING_READ(PIPECONF(pipe));
8084 }
8085
8086 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8087 {
8088         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8090         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8091         u32 val = 0;
8092
8093         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8094                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8095
8096         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8097                 val |= PIPECONF_INTERLACED_ILK;
8098         else
8099                 val |= PIPECONF_PROGRESSIVE;
8100
8101         I915_WRITE(PIPECONF(cpu_transcoder), val);
8102         POSTING_READ(PIPECONF(cpu_transcoder));
8103 }
8104
8105 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8106 {
8107         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109         struct intel_crtc_state *config = intel_crtc->config;
8110
8111         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8112                 u32 val = 0;
8113
8114                 switch (intel_crtc->config->pipe_bpp) {
8115                 case 18:
8116                         val |= PIPEMISC_DITHER_6_BPC;
8117                         break;
8118                 case 24:
8119                         val |= PIPEMISC_DITHER_8_BPC;
8120                         break;
8121                 case 30:
8122                         val |= PIPEMISC_DITHER_10_BPC;
8123                         break;
8124                 case 36:
8125                         val |= PIPEMISC_DITHER_12_BPC;
8126                         break;
8127                 default:
8128                         /* Case prevented by pipe_config_set_bpp. */
8129                         BUG();
8130                 }
8131
8132                 if (intel_crtc->config->dither)
8133                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8134
8135                 if (config->ycbcr420) {
8136                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8137                                 PIPEMISC_YUV420_ENABLE |
8138                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8139                 }
8140
8141                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8142         }
8143 }
8144
8145 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8146 {
8147         /*
8148          * Account for spread spectrum to avoid
8149          * oversubscribing the link. Max center spread
8150          * is 2.5%; use 5% for safety's sake.
8151          */
8152         u32 bps = target_clock * bpp * 21 / 20;
8153         return DIV_ROUND_UP(bps, link_bw * 8);
8154 }
8155
8156 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8157 {
8158         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8159 }
8160
8161 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8162                                   struct intel_crtc_state *crtc_state,
8163                                   struct dpll *reduced_clock)
8164 {
8165         struct drm_crtc *crtc = &intel_crtc->base;
8166         struct drm_device *dev = crtc->dev;
8167         struct drm_i915_private *dev_priv = to_i915(dev);
8168         u32 dpll, fp, fp2;
8169         int factor;
8170
8171         /* Enable autotuning of the PLL clock (if permissible) */
8172         factor = 21;
8173         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8174                 if ((intel_panel_use_ssc(dev_priv) &&
8175                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8176                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8177                         factor = 25;
8178         } else if (crtc_state->sdvo_tv_clock)
8179                 factor = 20;
8180
8181         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8182
8183         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8184                 fp |= FP_CB_TUNE;
8185
8186         if (reduced_clock) {
8187                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8188
8189                 if (reduced_clock->m < factor * reduced_clock->n)
8190                         fp2 |= FP_CB_TUNE;
8191         } else {
8192                 fp2 = fp;
8193         }
8194
8195         dpll = 0;
8196
8197         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8198                 dpll |= DPLLB_MODE_LVDS;
8199         else
8200                 dpll |= DPLLB_MODE_DAC_SERIAL;
8201
8202         dpll |= (crtc_state->pixel_multiplier - 1)
8203                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8204
8205         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8206             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8207                 dpll |= DPLL_SDVO_HIGH_SPEED;
8208
8209         if (intel_crtc_has_dp_encoder(crtc_state))
8210                 dpll |= DPLL_SDVO_HIGH_SPEED;
8211
8212         /*
8213          * The high speed IO clock is only really required for
8214          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8215          * possible to share the DPLL between CRT and HDMI. Enabling
8216          * the clock needlessly does no real harm, except use up a
8217          * bit of power potentially.
8218          *
8219          * We'll limit this to IVB with 3 pipes, since it has only two
8220          * DPLLs and so DPLL sharing is the only way to get three pipes
8221          * driving PCH ports at the same time. On SNB we could do this,
8222          * and potentially avoid enabling the second DPLL, but it's not
8223          * clear if it''s a win or loss power wise. No point in doing
8224          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8225          */
8226         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8227             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8228                 dpll |= DPLL_SDVO_HIGH_SPEED;
8229
8230         /* compute bitmask from p1 value */
8231         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8232         /* also FPA1 */
8233         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8234
8235         switch (crtc_state->dpll.p2) {
8236         case 5:
8237                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8238                 break;
8239         case 7:
8240                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8241                 break;
8242         case 10:
8243                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8244                 break;
8245         case 14:
8246                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8247                 break;
8248         }
8249
8250         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8251             intel_panel_use_ssc(dev_priv))
8252                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8253         else
8254                 dpll |= PLL_REF_INPUT_DREFCLK;
8255
8256         dpll |= DPLL_VCO_ENABLE;
8257
8258         crtc_state->dpll_hw_state.dpll = dpll;
8259         crtc_state->dpll_hw_state.fp0 = fp;
8260         crtc_state->dpll_hw_state.fp1 = fp2;
8261 }
8262
8263 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8264                                        struct intel_crtc_state *crtc_state)
8265 {
8266         struct drm_device *dev = crtc->base.dev;
8267         struct drm_i915_private *dev_priv = to_i915(dev);
8268         const struct intel_limit *limit;
8269         int refclk = 120000;
8270
8271         memset(&crtc_state->dpll_hw_state, 0,
8272                sizeof(crtc_state->dpll_hw_state));
8273
8274         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8275         if (!crtc_state->has_pch_encoder)
8276                 return 0;
8277
8278         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8279                 if (intel_panel_use_ssc(dev_priv)) {
8280                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8281                                       dev_priv->vbt.lvds_ssc_freq);
8282                         refclk = dev_priv->vbt.lvds_ssc_freq;
8283                 }
8284
8285                 if (intel_is_dual_link_lvds(dev)) {
8286                         if (refclk == 100000)
8287                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8288                         else
8289                                 limit = &intel_limits_ironlake_dual_lvds;
8290                 } else {
8291                         if (refclk == 100000)
8292                                 limit = &intel_limits_ironlake_single_lvds_100m;
8293                         else
8294                                 limit = &intel_limits_ironlake_single_lvds;
8295                 }
8296         } else {
8297                 limit = &intel_limits_ironlake_dac;
8298         }
8299
8300         if (!crtc_state->clock_set &&
8301             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8302                                 refclk, NULL, &crtc_state->dpll)) {
8303                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8304                 return -EINVAL;
8305         }
8306
8307         ironlake_compute_dpll(crtc, crtc_state, NULL);
8308
8309         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8310                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8311                                  pipe_name(crtc->pipe));
8312                 return -EINVAL;
8313         }
8314
8315         return 0;
8316 }
8317
8318 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8319                                          struct intel_link_m_n *m_n)
8320 {
8321         struct drm_device *dev = crtc->base.dev;
8322         struct drm_i915_private *dev_priv = to_i915(dev);
8323         enum pipe pipe = crtc->pipe;
8324
8325         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8326         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8327         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8328                 & ~TU_SIZE_MASK;
8329         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8330         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8331                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8332 }
8333
8334 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8335                                          enum transcoder transcoder,
8336                                          struct intel_link_m_n *m_n,
8337                                          struct intel_link_m_n *m2_n2)
8338 {
8339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8340         enum pipe pipe = crtc->pipe;
8341
8342         if (INTEL_GEN(dev_priv) >= 5) {
8343                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8344                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8345                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8346                         & ~TU_SIZE_MASK;
8347                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8348                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8349                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8350                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8351                  * gen < 8) and if DRRS is supported (to make sure the
8352                  * registers are not unnecessarily read).
8353                  */
8354                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8355                         crtc->config->has_drrs) {
8356                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8357                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8358                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8359                                         & ~TU_SIZE_MASK;
8360                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8361                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8362                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8363                 }
8364         } else {
8365                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8366                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8367                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8368                         & ~TU_SIZE_MASK;
8369                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8370                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8371                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8372         }
8373 }
8374
8375 void intel_dp_get_m_n(struct intel_crtc *crtc,
8376                       struct intel_crtc_state *pipe_config)
8377 {
8378         if (pipe_config->has_pch_encoder)
8379                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8380         else
8381                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8382                                              &pipe_config->dp_m_n,
8383                                              &pipe_config->dp_m2_n2);
8384 }
8385
8386 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8387                                         struct intel_crtc_state *pipe_config)
8388 {
8389         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8390                                      &pipe_config->fdi_m_n, NULL);
8391 }
8392
8393 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8394                                     struct intel_crtc_state *pipe_config)
8395 {
8396         struct drm_device *dev = crtc->base.dev;
8397         struct drm_i915_private *dev_priv = to_i915(dev);
8398         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8399         uint32_t ps_ctrl = 0;
8400         int id = -1;
8401         int i;
8402
8403         /* find scaler attached to this pipe */
8404         for (i = 0; i < crtc->num_scalers; i++) {
8405                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8406                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8407                         id = i;
8408                         pipe_config->pch_pfit.enabled = true;
8409                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8410                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8411                         break;
8412                 }
8413         }
8414
8415         scaler_state->scaler_id = id;
8416         if (id >= 0) {
8417                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8418         } else {
8419                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8420         }
8421 }
8422
8423 static void
8424 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8425                                  struct intel_initial_plane_config *plane_config)
8426 {
8427         struct drm_device *dev = crtc->base.dev;
8428         struct drm_i915_private *dev_priv = to_i915(dev);
8429         u32 val, base, offset, stride_mult, tiling;
8430         int pipe = crtc->pipe;
8431         int fourcc, pixel_format;
8432         unsigned int aligned_height;
8433         struct drm_framebuffer *fb;
8434         struct intel_framebuffer *intel_fb;
8435
8436         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8437         if (!intel_fb) {
8438                 DRM_DEBUG_KMS("failed to alloc fb\n");
8439                 return;
8440         }
8441
8442         fb = &intel_fb->base;
8443
8444         fb->dev = dev;
8445
8446         val = I915_READ(PLANE_CTL(pipe, 0));
8447         if (!(val & PLANE_CTL_ENABLE))
8448                 goto error;
8449
8450         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8451         fourcc = skl_format_to_fourcc(pixel_format,
8452                                       val & PLANE_CTL_ORDER_RGBX,
8453                                       val & PLANE_CTL_ALPHA_MASK);
8454         fb->format = drm_format_info(fourcc);
8455
8456         tiling = val & PLANE_CTL_TILED_MASK;
8457         switch (tiling) {
8458         case PLANE_CTL_TILED_LINEAR:
8459                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8460                 break;
8461         case PLANE_CTL_TILED_X:
8462                 plane_config->tiling = I915_TILING_X;
8463                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8464                 break;
8465         case PLANE_CTL_TILED_Y:
8466                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8467                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8468                 else
8469                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8470                 break;
8471         case PLANE_CTL_TILED_YF:
8472                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8473                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8474                 else
8475                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8476                 break;
8477         default:
8478                 MISSING_CASE(tiling);
8479                 goto error;
8480         }
8481
8482         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8483         plane_config->base = base;
8484
8485         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8486
8487         val = I915_READ(PLANE_SIZE(pipe, 0));
8488         fb->height = ((val >> 16) & 0xfff) + 1;
8489         fb->width = ((val >> 0) & 0x1fff) + 1;
8490
8491         val = I915_READ(PLANE_STRIDE(pipe, 0));
8492         stride_mult = intel_fb_stride_alignment(fb, 0);
8493         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8494
8495         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8496
8497         plane_config->size = fb->pitches[0] * aligned_height;
8498
8499         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8500                       pipe_name(pipe), fb->width, fb->height,
8501                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8502                       plane_config->size);
8503
8504         plane_config->fb = intel_fb;
8505         return;
8506
8507 error:
8508         kfree(intel_fb);
8509 }
8510
8511 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8512                                      struct intel_crtc_state *pipe_config)
8513 {
8514         struct drm_device *dev = crtc->base.dev;
8515         struct drm_i915_private *dev_priv = to_i915(dev);
8516         uint32_t tmp;
8517
8518         tmp = I915_READ(PF_CTL(crtc->pipe));
8519
8520         if (tmp & PF_ENABLE) {
8521                 pipe_config->pch_pfit.enabled = true;
8522                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8523                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8524
8525                 /* We currently do not free assignements of panel fitters on
8526                  * ivb/hsw (since we don't use the higher upscaling modes which
8527                  * differentiates them) so just WARN about this case for now. */
8528                 if (IS_GEN7(dev_priv)) {
8529                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8530                                 PF_PIPE_SEL_IVB(crtc->pipe));
8531                 }
8532         }
8533 }
8534
8535 static void
8536 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8537                                   struct intel_initial_plane_config *plane_config)
8538 {
8539         struct drm_device *dev = crtc->base.dev;
8540         struct drm_i915_private *dev_priv = to_i915(dev);
8541         u32 val, base, offset;
8542         int pipe = crtc->pipe;
8543         int fourcc, pixel_format;
8544         unsigned int aligned_height;
8545         struct drm_framebuffer *fb;
8546         struct intel_framebuffer *intel_fb;
8547
8548         val = I915_READ(DSPCNTR(pipe));
8549         if (!(val & DISPLAY_PLANE_ENABLE))
8550                 return;
8551
8552         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8553         if (!intel_fb) {
8554                 DRM_DEBUG_KMS("failed to alloc fb\n");
8555                 return;
8556         }
8557
8558         fb = &intel_fb->base;
8559
8560         fb->dev = dev;
8561
8562         if (INTEL_GEN(dev_priv) >= 4) {
8563                 if (val & DISPPLANE_TILED) {
8564                         plane_config->tiling = I915_TILING_X;
8565                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8566                 }
8567         }
8568
8569         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8570         fourcc = i9xx_format_to_fourcc(pixel_format);
8571         fb->format = drm_format_info(fourcc);
8572
8573         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8574         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8575                 offset = I915_READ(DSPOFFSET(pipe));
8576         } else {
8577                 if (plane_config->tiling)
8578                         offset = I915_READ(DSPTILEOFF(pipe));
8579                 else
8580                         offset = I915_READ(DSPLINOFF(pipe));
8581         }
8582         plane_config->base = base;
8583
8584         val = I915_READ(PIPESRC(pipe));
8585         fb->width = ((val >> 16) & 0xfff) + 1;
8586         fb->height = ((val >> 0) & 0xfff) + 1;
8587
8588         val = I915_READ(DSPSTRIDE(pipe));
8589         fb->pitches[0] = val & 0xffffffc0;
8590
8591         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8592
8593         plane_config->size = fb->pitches[0] * aligned_height;
8594
8595         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8596                       pipe_name(pipe), fb->width, fb->height,
8597                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8598                       plane_config->size);
8599
8600         plane_config->fb = intel_fb;
8601 }
8602
8603 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8604                                      struct intel_crtc_state *pipe_config)
8605 {
8606         struct drm_device *dev = crtc->base.dev;
8607         struct drm_i915_private *dev_priv = to_i915(dev);
8608         enum intel_display_power_domain power_domain;
8609         uint32_t tmp;
8610         bool ret;
8611
8612         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8613         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8614                 return false;
8615
8616         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8617         pipe_config->shared_dpll = NULL;
8618
8619         ret = false;
8620         tmp = I915_READ(PIPECONF(crtc->pipe));
8621         if (!(tmp & PIPECONF_ENABLE))
8622                 goto out;
8623
8624         switch (tmp & PIPECONF_BPC_MASK) {
8625         case PIPECONF_6BPC:
8626                 pipe_config->pipe_bpp = 18;
8627                 break;
8628         case PIPECONF_8BPC:
8629                 pipe_config->pipe_bpp = 24;
8630                 break;
8631         case PIPECONF_10BPC:
8632                 pipe_config->pipe_bpp = 30;
8633                 break;
8634         case PIPECONF_12BPC:
8635                 pipe_config->pipe_bpp = 36;
8636                 break;
8637         default:
8638                 break;
8639         }
8640
8641         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8642                 pipe_config->limited_color_range = true;
8643
8644         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8645                 struct intel_shared_dpll *pll;
8646                 enum intel_dpll_id pll_id;
8647
8648                 pipe_config->has_pch_encoder = true;
8649
8650                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8651                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8652                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8653
8654                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8655
8656                 if (HAS_PCH_IBX(dev_priv)) {
8657                         /*
8658                          * The pipe->pch transcoder and pch transcoder->pll
8659                          * mapping is fixed.
8660                          */
8661                         pll_id = (enum intel_dpll_id) crtc->pipe;
8662                 } else {
8663                         tmp = I915_READ(PCH_DPLL_SEL);
8664                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8665                                 pll_id = DPLL_ID_PCH_PLL_B;
8666                         else
8667                                 pll_id= DPLL_ID_PCH_PLL_A;
8668                 }
8669
8670                 pipe_config->shared_dpll =
8671                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8672                 pll = pipe_config->shared_dpll;
8673
8674                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8675                                                  &pipe_config->dpll_hw_state));
8676
8677                 tmp = pipe_config->dpll_hw_state.dpll;
8678                 pipe_config->pixel_multiplier =
8679                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8680                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8681
8682                 ironlake_pch_clock_get(crtc, pipe_config);
8683         } else {
8684                 pipe_config->pixel_multiplier = 1;
8685         }
8686
8687         intel_get_pipe_timings(crtc, pipe_config);
8688         intel_get_pipe_src_size(crtc, pipe_config);
8689
8690         ironlake_get_pfit_config(crtc, pipe_config);
8691
8692         ret = true;
8693
8694 out:
8695         intel_display_power_put(dev_priv, power_domain);
8696
8697         return ret;
8698 }
8699
8700 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8701 {
8702         struct drm_device *dev = &dev_priv->drm;
8703         struct intel_crtc *crtc;
8704
8705         for_each_intel_crtc(dev, crtc)
8706                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8707                      pipe_name(crtc->pipe));
8708
8709         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8710                         "Display power well on\n");
8711         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8712         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8713         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8714         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8715         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8716              "CPU PWM1 enabled\n");
8717         if (IS_HASWELL(dev_priv))
8718                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8719                      "CPU PWM2 enabled\n");
8720         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8721              "PCH PWM1 enabled\n");
8722         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8723              "Utility pin enabled\n");
8724         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8725
8726         /*
8727          * In theory we can still leave IRQs enabled, as long as only the HPD
8728          * interrupts remain enabled. We used to check for that, but since it's
8729          * gen-specific and since we only disable LCPLL after we fully disable
8730          * the interrupts, the check below should be enough.
8731          */
8732         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8733 }
8734
8735 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8736 {
8737         if (IS_HASWELL(dev_priv))
8738                 return I915_READ(D_COMP_HSW);
8739         else
8740                 return I915_READ(D_COMP_BDW);
8741 }
8742
8743 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8744 {
8745         if (IS_HASWELL(dev_priv)) {
8746                 mutex_lock(&dev_priv->pcu_lock);
8747                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8748                                             val))
8749                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8750                 mutex_unlock(&dev_priv->pcu_lock);
8751         } else {
8752                 I915_WRITE(D_COMP_BDW, val);
8753                 POSTING_READ(D_COMP_BDW);
8754         }
8755 }
8756
8757 /*
8758  * This function implements pieces of two sequences from BSpec:
8759  * - Sequence for display software to disable LCPLL
8760  * - Sequence for display software to allow package C8+
8761  * The steps implemented here are just the steps that actually touch the LCPLL
8762  * register. Callers should take care of disabling all the display engine
8763  * functions, doing the mode unset, fixing interrupts, etc.
8764  */
8765 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8766                               bool switch_to_fclk, bool allow_power_down)
8767 {
8768         uint32_t val;
8769
8770         assert_can_disable_lcpll(dev_priv);
8771
8772         val = I915_READ(LCPLL_CTL);
8773
8774         if (switch_to_fclk) {
8775                 val |= LCPLL_CD_SOURCE_FCLK;
8776                 I915_WRITE(LCPLL_CTL, val);
8777
8778                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8779                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8780                         DRM_ERROR("Switching to FCLK failed\n");
8781
8782                 val = I915_READ(LCPLL_CTL);
8783         }
8784
8785         val |= LCPLL_PLL_DISABLE;
8786         I915_WRITE(LCPLL_CTL, val);
8787         POSTING_READ(LCPLL_CTL);
8788
8789         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8790                 DRM_ERROR("LCPLL still locked\n");
8791
8792         val = hsw_read_dcomp(dev_priv);
8793         val |= D_COMP_COMP_DISABLE;
8794         hsw_write_dcomp(dev_priv, val);
8795         ndelay(100);
8796
8797         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8798                      1))
8799                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8800
8801         if (allow_power_down) {
8802                 val = I915_READ(LCPLL_CTL);
8803                 val |= LCPLL_POWER_DOWN_ALLOW;
8804                 I915_WRITE(LCPLL_CTL, val);
8805                 POSTING_READ(LCPLL_CTL);
8806         }
8807 }
8808
8809 /*
8810  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8811  * source.
8812  */
8813 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8814 {
8815         uint32_t val;
8816
8817         val = I915_READ(LCPLL_CTL);
8818
8819         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8820                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8821                 return;
8822
8823         /*
8824          * Make sure we're not on PC8 state before disabling PC8, otherwise
8825          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8826          */
8827         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8828
8829         if (val & LCPLL_POWER_DOWN_ALLOW) {
8830                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8831                 I915_WRITE(LCPLL_CTL, val);
8832                 POSTING_READ(LCPLL_CTL);
8833         }
8834
8835         val = hsw_read_dcomp(dev_priv);
8836         val |= D_COMP_COMP_FORCE;
8837         val &= ~D_COMP_COMP_DISABLE;
8838         hsw_write_dcomp(dev_priv, val);
8839
8840         val = I915_READ(LCPLL_CTL);
8841         val &= ~LCPLL_PLL_DISABLE;
8842         I915_WRITE(LCPLL_CTL, val);
8843
8844         if (intel_wait_for_register(dev_priv,
8845                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8846                                     5))
8847                 DRM_ERROR("LCPLL not locked yet\n");
8848
8849         if (val & LCPLL_CD_SOURCE_FCLK) {
8850                 val = I915_READ(LCPLL_CTL);
8851                 val &= ~LCPLL_CD_SOURCE_FCLK;
8852                 I915_WRITE(LCPLL_CTL, val);
8853
8854                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8855                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8856                         DRM_ERROR("Switching back to LCPLL failed\n");
8857         }
8858
8859         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8860
8861         intel_update_cdclk(dev_priv);
8862         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
8863 }
8864
8865 /*
8866  * Package states C8 and deeper are really deep PC states that can only be
8867  * reached when all the devices on the system allow it, so even if the graphics
8868  * device allows PC8+, it doesn't mean the system will actually get to these
8869  * states. Our driver only allows PC8+ when going into runtime PM.
8870  *
8871  * The requirements for PC8+ are that all the outputs are disabled, the power
8872  * well is disabled and most interrupts are disabled, and these are also
8873  * requirements for runtime PM. When these conditions are met, we manually do
8874  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8875  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8876  * hang the machine.
8877  *
8878  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8879  * the state of some registers, so when we come back from PC8+ we need to
8880  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8881  * need to take care of the registers kept by RC6. Notice that this happens even
8882  * if we don't put the device in PCI D3 state (which is what currently happens
8883  * because of the runtime PM support).
8884  *
8885  * For more, read "Display Sequences for Package C8" on the hardware
8886  * documentation.
8887  */
8888 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8889 {
8890         uint32_t val;
8891
8892         DRM_DEBUG_KMS("Enabling package C8+\n");
8893
8894         if (HAS_PCH_LPT_LP(dev_priv)) {
8895                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8896                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8897                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8898         }
8899
8900         lpt_disable_clkout_dp(dev_priv);
8901         hsw_disable_lcpll(dev_priv, true, true);
8902 }
8903
8904 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8905 {
8906         uint32_t val;
8907
8908         DRM_DEBUG_KMS("Disabling package C8+\n");
8909
8910         hsw_restore_lcpll(dev_priv);
8911         lpt_init_pch_refclk(dev_priv);
8912
8913         if (HAS_PCH_LPT_LP(dev_priv)) {
8914                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8915                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8916                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8917         }
8918 }
8919
8920 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8921                                       struct intel_crtc_state *crtc_state)
8922 {
8923         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8924                 struct intel_encoder *encoder =
8925                         intel_ddi_get_crtc_new_encoder(crtc_state);
8926
8927                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8928                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8929                                          pipe_name(crtc->pipe));
8930                         return -EINVAL;
8931                 }
8932         }
8933
8934         return 0;
8935 }
8936
8937 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
8938                                    enum port port,
8939                                    struct intel_crtc_state *pipe_config)
8940 {
8941         enum intel_dpll_id id;
8942         u32 temp;
8943
8944         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
8945         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
8946
8947         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
8948                 return;
8949
8950         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8951 }
8952
8953 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8954                                 enum port port,
8955                                 struct intel_crtc_state *pipe_config)
8956 {
8957         enum intel_dpll_id id;
8958
8959         switch (port) {
8960         case PORT_A:
8961                 id = DPLL_ID_SKL_DPLL0;
8962                 break;
8963         case PORT_B:
8964                 id = DPLL_ID_SKL_DPLL1;
8965                 break;
8966         case PORT_C:
8967                 id = DPLL_ID_SKL_DPLL2;
8968                 break;
8969         default:
8970                 DRM_ERROR("Incorrect port type\n");
8971                 return;
8972         }
8973
8974         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8975 }
8976
8977 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8978                                 enum port port,
8979                                 struct intel_crtc_state *pipe_config)
8980 {
8981         enum intel_dpll_id id;
8982         u32 temp;
8983
8984         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8985         id = temp >> (port * 3 + 1);
8986
8987         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8988                 return;
8989
8990         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8991 }
8992
8993 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8994                                 enum port port,
8995                                 struct intel_crtc_state *pipe_config)
8996 {
8997         enum intel_dpll_id id;
8998         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8999
9000         switch (ddi_pll_sel) {
9001         case PORT_CLK_SEL_WRPLL1:
9002                 id = DPLL_ID_WRPLL1;
9003                 break;
9004         case PORT_CLK_SEL_WRPLL2:
9005                 id = DPLL_ID_WRPLL2;
9006                 break;
9007         case PORT_CLK_SEL_SPLL:
9008                 id = DPLL_ID_SPLL;
9009                 break;
9010         case PORT_CLK_SEL_LCPLL_810:
9011                 id = DPLL_ID_LCPLL_810;
9012                 break;
9013         case PORT_CLK_SEL_LCPLL_1350:
9014                 id = DPLL_ID_LCPLL_1350;
9015                 break;
9016         case PORT_CLK_SEL_LCPLL_2700:
9017                 id = DPLL_ID_LCPLL_2700;
9018                 break;
9019         default:
9020                 MISSING_CASE(ddi_pll_sel);
9021                 /* fall through */
9022         case PORT_CLK_SEL_NONE:
9023                 return;
9024         }
9025
9026         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9027 }
9028
9029 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9030                                      struct intel_crtc_state *pipe_config,
9031                                      u64 *power_domain_mask)
9032 {
9033         struct drm_device *dev = crtc->base.dev;
9034         struct drm_i915_private *dev_priv = to_i915(dev);
9035         enum intel_display_power_domain power_domain;
9036         u32 tmp;
9037
9038         /*
9039          * The pipe->transcoder mapping is fixed with the exception of the eDP
9040          * transcoder handled below.
9041          */
9042         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9043
9044         /*
9045          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9046          * consistency and less surprising code; it's in always on power).
9047          */
9048         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9049         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9050                 enum pipe trans_edp_pipe;
9051                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9052                 default:
9053                         WARN(1, "unknown pipe linked to edp transcoder\n");
9054                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9055                 case TRANS_DDI_EDP_INPUT_A_ON:
9056                         trans_edp_pipe = PIPE_A;
9057                         break;
9058                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9059                         trans_edp_pipe = PIPE_B;
9060                         break;
9061                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9062                         trans_edp_pipe = PIPE_C;
9063                         break;
9064                 }
9065
9066                 if (trans_edp_pipe == crtc->pipe)
9067                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9068         }
9069
9070         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9071         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9072                 return false;
9073         *power_domain_mask |= BIT_ULL(power_domain);
9074
9075         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9076
9077         return tmp & PIPECONF_ENABLE;
9078 }
9079
9080 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9081                                          struct intel_crtc_state *pipe_config,
9082                                          u64 *power_domain_mask)
9083 {
9084         struct drm_device *dev = crtc->base.dev;
9085         struct drm_i915_private *dev_priv = to_i915(dev);
9086         enum intel_display_power_domain power_domain;
9087         enum port port;
9088         enum transcoder cpu_transcoder;
9089         u32 tmp;
9090
9091         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9092                 if (port == PORT_A)
9093                         cpu_transcoder = TRANSCODER_DSI_A;
9094                 else
9095                         cpu_transcoder = TRANSCODER_DSI_C;
9096
9097                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9098                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9099                         continue;
9100                 *power_domain_mask |= BIT_ULL(power_domain);
9101
9102                 /*
9103                  * The PLL needs to be enabled with a valid divider
9104                  * configuration, otherwise accessing DSI registers will hang
9105                  * the machine. See BSpec North Display Engine
9106                  * registers/MIPI[BXT]. We can break out here early, since we
9107                  * need the same DSI PLL to be enabled for both DSI ports.
9108                  */
9109                 if (!intel_dsi_pll_is_enabled(dev_priv))
9110                         break;
9111
9112                 /* XXX: this works for video mode only */
9113                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9114                 if (!(tmp & DPI_ENABLE))
9115                         continue;
9116
9117                 tmp = I915_READ(MIPI_CTRL(port));
9118                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9119                         continue;
9120
9121                 pipe_config->cpu_transcoder = cpu_transcoder;
9122                 break;
9123         }
9124
9125         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9126 }
9127
9128 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9129                                        struct intel_crtc_state *pipe_config)
9130 {
9131         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9132         struct intel_shared_dpll *pll;
9133         enum port port;
9134         uint32_t tmp;
9135
9136         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9137
9138         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9139
9140         if (IS_CANNONLAKE(dev_priv))
9141                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9142         else if (IS_GEN9_BC(dev_priv))
9143                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9144         else if (IS_GEN9_LP(dev_priv))
9145                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9146         else
9147                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9148
9149         pll = pipe_config->shared_dpll;
9150         if (pll) {
9151                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9152                                                  &pipe_config->dpll_hw_state));
9153         }
9154
9155         /*
9156          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9157          * DDI E. So just check whether this pipe is wired to DDI E and whether
9158          * the PCH transcoder is on.
9159          */
9160         if (INTEL_GEN(dev_priv) < 9 &&
9161             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9162                 pipe_config->has_pch_encoder = true;
9163
9164                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9165                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9166                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9167
9168                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9169         }
9170 }
9171
9172 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9173                                     struct intel_crtc_state *pipe_config)
9174 {
9175         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9176         enum intel_display_power_domain power_domain;
9177         u64 power_domain_mask;
9178         bool active;
9179
9180         intel_crtc_init_scalers(crtc, pipe_config);
9181
9182         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9183         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9184                 return false;
9185         power_domain_mask = BIT_ULL(power_domain);
9186
9187         pipe_config->shared_dpll = NULL;
9188
9189         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9190
9191         if (IS_GEN9_LP(dev_priv) &&
9192             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9193                 WARN_ON(active);
9194                 active = true;
9195         }
9196
9197         if (!active)
9198                 goto out;
9199
9200         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9201                 haswell_get_ddi_port_state(crtc, pipe_config);
9202                 intel_get_pipe_timings(crtc, pipe_config);
9203         }
9204
9205         intel_get_pipe_src_size(crtc, pipe_config);
9206
9207         pipe_config->gamma_mode =
9208                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9209
9210         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9211                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9212                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9213
9214                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9215                         bool blend_mode_420 = tmp &
9216                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9217
9218                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9219                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9220                             pipe_config->ycbcr420 != blend_mode_420)
9221                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9222                 } else if (clrspace_yuv) {
9223                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9224                 }
9225         }
9226
9227         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9228         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9229                 power_domain_mask |= BIT_ULL(power_domain);
9230                 if (INTEL_GEN(dev_priv) >= 9)
9231                         skylake_get_pfit_config(crtc, pipe_config);
9232                 else
9233                         ironlake_get_pfit_config(crtc, pipe_config);
9234         }
9235
9236         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9237             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9238                 pipe_config->pixel_multiplier =
9239                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9240         } else {
9241                 pipe_config->pixel_multiplier = 1;
9242         }
9243
9244 out:
9245         for_each_power_domain(power_domain, power_domain_mask)
9246                 intel_display_power_put(dev_priv, power_domain);
9247
9248         return active;
9249 }
9250
9251 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9252 {
9253         struct drm_i915_private *dev_priv =
9254                 to_i915(plane_state->base.plane->dev);
9255         const struct drm_framebuffer *fb = plane_state->base.fb;
9256         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9257         u32 base;
9258
9259         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9260                 base = obj->phys_handle->busaddr;
9261         else
9262                 base = intel_plane_ggtt_offset(plane_state);
9263
9264         base += plane_state->main.offset;
9265
9266         /* ILK+ do this automagically */
9267         if (HAS_GMCH_DISPLAY(dev_priv) &&
9268             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9269                 base += (plane_state->base.crtc_h *
9270                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9271
9272         return base;
9273 }
9274
9275 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9276 {
9277         int x = plane_state->base.crtc_x;
9278         int y = plane_state->base.crtc_y;
9279         u32 pos = 0;
9280
9281         if (x < 0) {
9282                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9283                 x = -x;
9284         }
9285         pos |= x << CURSOR_X_SHIFT;
9286
9287         if (y < 0) {
9288                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9289                 y = -y;
9290         }
9291         pos |= y << CURSOR_Y_SHIFT;
9292
9293         return pos;
9294 }
9295
9296 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9297 {
9298         const struct drm_mode_config *config =
9299                 &plane_state->base.plane->dev->mode_config;
9300         int width = plane_state->base.crtc_w;
9301         int height = plane_state->base.crtc_h;
9302
9303         return width > 0 && width <= config->cursor_width &&
9304                 height > 0 && height <= config->cursor_height;
9305 }
9306
9307 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9308                               struct intel_plane_state *plane_state)
9309 {
9310         const struct drm_framebuffer *fb = plane_state->base.fb;
9311         int src_x, src_y;
9312         u32 offset;
9313         int ret;
9314
9315         ret = drm_plane_helper_check_state(&plane_state->base,
9316                                            &plane_state->clip,
9317                                            DRM_PLANE_HELPER_NO_SCALING,
9318                                            DRM_PLANE_HELPER_NO_SCALING,
9319                                            true, true);
9320         if (ret)
9321                 return ret;
9322
9323         if (!fb)
9324                 return 0;
9325
9326         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9327                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9328                 return -EINVAL;
9329         }
9330
9331         src_x = plane_state->base.src_x >> 16;
9332         src_y = plane_state->base.src_y >> 16;
9333
9334         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9335         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9336
9337         if (src_x != 0 || src_y != 0) {
9338                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9339                 return -EINVAL;
9340         }
9341
9342         plane_state->main.offset = offset;
9343
9344         return 0;
9345 }
9346
9347 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9348                            const struct intel_plane_state *plane_state)
9349 {
9350         const struct drm_framebuffer *fb = plane_state->base.fb;
9351
9352         return CURSOR_ENABLE |
9353                 CURSOR_GAMMA_ENABLE |
9354                 CURSOR_FORMAT_ARGB |
9355                 CURSOR_STRIDE(fb->pitches[0]);
9356 }
9357
9358 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9359 {
9360         int width = plane_state->base.crtc_w;
9361
9362         /*
9363          * 845g/865g are only limited by the width of their cursors,
9364          * the height is arbitrary up to the precision of the register.
9365          */
9366         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9367 }
9368
9369 static int i845_check_cursor(struct intel_plane *plane,
9370                              struct intel_crtc_state *crtc_state,
9371                              struct intel_plane_state *plane_state)
9372 {
9373         const struct drm_framebuffer *fb = plane_state->base.fb;
9374         int ret;
9375
9376         ret = intel_check_cursor(crtc_state, plane_state);
9377         if (ret)
9378                 return ret;
9379
9380         /* if we want to turn off the cursor ignore width and height */
9381         if (!fb)
9382                 return 0;
9383
9384         /* Check for which cursor types we support */
9385         if (!i845_cursor_size_ok(plane_state)) {
9386                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9387                           plane_state->base.crtc_w,
9388                           plane_state->base.crtc_h);
9389                 return -EINVAL;
9390         }
9391
9392         switch (fb->pitches[0]) {
9393         case 256:
9394         case 512:
9395         case 1024:
9396         case 2048:
9397                 break;
9398         default:
9399                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9400                               fb->pitches[0]);
9401                 return -EINVAL;
9402         }
9403
9404         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9405
9406         return 0;
9407 }
9408
9409 static void i845_update_cursor(struct intel_plane *plane,
9410                                const struct intel_crtc_state *crtc_state,
9411                                const struct intel_plane_state *plane_state)
9412 {
9413         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9414         u32 cntl = 0, base = 0, pos = 0, size = 0;
9415         unsigned long irqflags;
9416
9417         if (plane_state && plane_state->base.visible) {
9418                 unsigned int width = plane_state->base.crtc_w;
9419                 unsigned int height = plane_state->base.crtc_h;
9420
9421                 cntl = plane_state->ctl;
9422                 size = (height << 12) | width;
9423
9424                 base = intel_cursor_base(plane_state);
9425                 pos = intel_cursor_position(plane_state);
9426         }
9427
9428         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9429
9430         /* On these chipsets we can only modify the base/size/stride
9431          * whilst the cursor is disabled.
9432          */
9433         if (plane->cursor.base != base ||
9434             plane->cursor.size != size ||
9435             plane->cursor.cntl != cntl) {
9436                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9437                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9438                 I915_WRITE_FW(CURSIZE, size);
9439                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9440                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9441
9442                 plane->cursor.base = base;
9443                 plane->cursor.size = size;
9444                 plane->cursor.cntl = cntl;
9445         } else {
9446                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9447         }
9448
9449         POSTING_READ_FW(CURCNTR(PIPE_A));
9450
9451         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9452 }
9453
9454 static void i845_disable_cursor(struct intel_plane *plane,
9455                                 struct intel_crtc *crtc)
9456 {
9457         i845_update_cursor(plane, NULL, NULL);
9458 }
9459
9460 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9461                            const struct intel_plane_state *plane_state)
9462 {
9463         struct drm_i915_private *dev_priv =
9464                 to_i915(plane_state->base.plane->dev);
9465         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9466         u32 cntl;
9467
9468         cntl = MCURSOR_GAMMA_ENABLE;
9469
9470         if (HAS_DDI(dev_priv))
9471                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9472
9473         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9474
9475         switch (plane_state->base.crtc_w) {
9476         case 64:
9477                 cntl |= CURSOR_MODE_64_ARGB_AX;
9478                 break;
9479         case 128:
9480                 cntl |= CURSOR_MODE_128_ARGB_AX;
9481                 break;
9482         case 256:
9483                 cntl |= CURSOR_MODE_256_ARGB_AX;
9484                 break;
9485         default:
9486                 MISSING_CASE(plane_state->base.crtc_w);
9487                 return 0;
9488         }
9489
9490         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9491                 cntl |= CURSOR_ROTATE_180;
9492
9493         return cntl;
9494 }
9495
9496 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9497 {
9498         struct drm_i915_private *dev_priv =
9499                 to_i915(plane_state->base.plane->dev);
9500         int width = plane_state->base.crtc_w;
9501         int height = plane_state->base.crtc_h;
9502
9503         if (!intel_cursor_size_ok(plane_state))
9504                 return false;
9505
9506         /* Cursor width is limited to a few power-of-two sizes */
9507         switch (width) {
9508         case 256:
9509         case 128:
9510         case 64:
9511                 break;
9512         default:
9513                 return false;
9514         }
9515
9516         /*
9517          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9518          * height from 8 lines up to the cursor width, when the
9519          * cursor is not rotated. Everything else requires square
9520          * cursors.
9521          */
9522         if (HAS_CUR_FBC(dev_priv) &&
9523             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9524                 if (height < 8 || height > width)
9525                         return false;
9526         } else {
9527                 if (height != width)
9528                         return false;
9529         }
9530
9531         return true;
9532 }
9533
9534 static int i9xx_check_cursor(struct intel_plane *plane,
9535                              struct intel_crtc_state *crtc_state,
9536                              struct intel_plane_state *plane_state)
9537 {
9538         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9539         const struct drm_framebuffer *fb = plane_state->base.fb;
9540         enum pipe pipe = plane->pipe;
9541         int ret;
9542
9543         ret = intel_check_cursor(crtc_state, plane_state);
9544         if (ret)
9545                 return ret;
9546
9547         /* if we want to turn off the cursor ignore width and height */
9548         if (!fb)
9549                 return 0;
9550
9551         /* Check for which cursor types we support */
9552         if (!i9xx_cursor_size_ok(plane_state)) {
9553                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9554                           plane_state->base.crtc_w,
9555                           plane_state->base.crtc_h);
9556                 return -EINVAL;
9557         }
9558
9559         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9560                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9561                               fb->pitches[0], plane_state->base.crtc_w);
9562                 return -EINVAL;
9563         }
9564
9565         /*
9566          * There's something wrong with the cursor on CHV pipe C.
9567          * If it straddles the left edge of the screen then
9568          * moving it away from the edge or disabling it often
9569          * results in a pipe underrun, and often that can lead to
9570          * dead pipe (constant underrun reported, and it scans
9571          * out just a solid color). To recover from that, the
9572          * display power well must be turned off and on again.
9573          * Refuse the put the cursor into that compromised position.
9574          */
9575         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9576             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9577                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9578                 return -EINVAL;
9579         }
9580
9581         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9582
9583         return 0;
9584 }
9585
9586 static void i9xx_update_cursor(struct intel_plane *plane,
9587                                const struct intel_crtc_state *crtc_state,
9588                                const struct intel_plane_state *plane_state)
9589 {
9590         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9591         enum pipe pipe = plane->pipe;
9592         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9593         unsigned long irqflags;
9594
9595         if (plane_state && plane_state->base.visible) {
9596                 cntl = plane_state->ctl;
9597
9598                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9599                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9600
9601                 base = intel_cursor_base(plane_state);
9602                 pos = intel_cursor_position(plane_state);
9603         }
9604
9605         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9606
9607         /*
9608          * On some platforms writing CURCNTR first will also
9609          * cause CURPOS to be armed by the CURBASE write.
9610          * Without the CURCNTR write the CURPOS write would
9611          * arm itself. Thus we always start the full update
9612          * with a CURCNTR write.
9613          *
9614          * On other platforms CURPOS always requires the
9615          * CURBASE write to arm the update. Additonally
9616          * a write to any of the cursor register will cancel
9617          * an already armed cursor update. Thus leaving out
9618          * the CURBASE write after CURPOS could lead to a
9619          * cursor that doesn't appear to move, or even change
9620          * shape. Thus we always write CURBASE.
9621          *
9622          * CURCNTR and CUR_FBC_CTL are always
9623          * armed by the CURBASE write only.
9624          */
9625         if (plane->cursor.base != base ||
9626             plane->cursor.size != fbc_ctl ||
9627             plane->cursor.cntl != cntl) {
9628                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9629                 if (HAS_CUR_FBC(dev_priv))
9630                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9631                 I915_WRITE_FW(CURPOS(pipe), pos);
9632                 I915_WRITE_FW(CURBASE(pipe), base);
9633
9634                 plane->cursor.base = base;
9635                 plane->cursor.size = fbc_ctl;
9636                 plane->cursor.cntl = cntl;
9637         } else {
9638                 I915_WRITE_FW(CURPOS(pipe), pos);
9639                 I915_WRITE_FW(CURBASE(pipe), base);
9640         }
9641
9642         POSTING_READ_FW(CURBASE(pipe));
9643
9644         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9645 }
9646
9647 static void i9xx_disable_cursor(struct intel_plane *plane,
9648                                 struct intel_crtc *crtc)
9649 {
9650         i9xx_update_cursor(plane, NULL, NULL);
9651 }
9652
9653
9654 /* VESA 640x480x72Hz mode to set on the pipe */
9655 static const struct drm_display_mode load_detect_mode = {
9656         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9657                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9658 };
9659
9660 struct drm_framebuffer *
9661 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9662                          struct drm_mode_fb_cmd2 *mode_cmd)
9663 {
9664         struct intel_framebuffer *intel_fb;
9665         int ret;
9666
9667         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9668         if (!intel_fb)
9669                 return ERR_PTR(-ENOMEM);
9670
9671         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9672         if (ret)
9673                 goto err;
9674
9675         return &intel_fb->base;
9676
9677 err:
9678         kfree(intel_fb);
9679         return ERR_PTR(ret);
9680 }
9681
9682 static u32
9683 intel_framebuffer_pitch_for_width(int width, int bpp)
9684 {
9685         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9686         return ALIGN(pitch, 64);
9687 }
9688
9689 static u32
9690 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9691 {
9692         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9693         return PAGE_ALIGN(pitch * mode->vdisplay);
9694 }
9695
9696 static struct drm_framebuffer *
9697 intel_framebuffer_create_for_mode(struct drm_device *dev,
9698                                   const struct drm_display_mode *mode,
9699                                   int depth, int bpp)
9700 {
9701         struct drm_framebuffer *fb;
9702         struct drm_i915_gem_object *obj;
9703         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9704
9705         obj = i915_gem_object_create(to_i915(dev),
9706                                     intel_framebuffer_size_for_mode(mode, bpp));
9707         if (IS_ERR(obj))
9708                 return ERR_CAST(obj);
9709
9710         mode_cmd.width = mode->hdisplay;
9711         mode_cmd.height = mode->vdisplay;
9712         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9713                                                                 bpp);
9714         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9715
9716         fb = intel_framebuffer_create(obj, &mode_cmd);
9717         if (IS_ERR(fb))
9718                 i915_gem_object_put(obj);
9719
9720         return fb;
9721 }
9722
9723 static struct drm_framebuffer *
9724 mode_fits_in_fbdev(struct drm_device *dev,
9725                    const struct drm_display_mode *mode)
9726 {
9727 #ifdef CONFIG_DRM_FBDEV_EMULATION
9728         struct drm_i915_private *dev_priv = to_i915(dev);
9729         struct drm_i915_gem_object *obj;
9730         struct drm_framebuffer *fb;
9731
9732         if (!dev_priv->fbdev)
9733                 return NULL;
9734
9735         if (!dev_priv->fbdev->fb)
9736                 return NULL;
9737
9738         obj = dev_priv->fbdev->fb->obj;
9739         BUG_ON(!obj);
9740
9741         fb = &dev_priv->fbdev->fb->base;
9742         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9743                                                                fb->format->cpp[0] * 8))
9744                 return NULL;
9745
9746         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9747                 return NULL;
9748
9749         drm_framebuffer_get(fb);
9750         return fb;
9751 #else
9752         return NULL;
9753 #endif
9754 }
9755
9756 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9757                                            struct drm_crtc *crtc,
9758                                            const struct drm_display_mode *mode,
9759                                            struct drm_framebuffer *fb,
9760                                            int x, int y)
9761 {
9762         struct drm_plane_state *plane_state;
9763         int hdisplay, vdisplay;
9764         int ret;
9765
9766         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9767         if (IS_ERR(plane_state))
9768                 return PTR_ERR(plane_state);
9769
9770         if (mode)
9771                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9772         else
9773                 hdisplay = vdisplay = 0;
9774
9775         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9776         if (ret)
9777                 return ret;
9778         drm_atomic_set_fb_for_plane(plane_state, fb);
9779         plane_state->crtc_x = 0;
9780         plane_state->crtc_y = 0;
9781         plane_state->crtc_w = hdisplay;
9782         plane_state->crtc_h = vdisplay;
9783         plane_state->src_x = x << 16;
9784         plane_state->src_y = y << 16;
9785         plane_state->src_w = hdisplay << 16;
9786         plane_state->src_h = vdisplay << 16;
9787
9788         return 0;
9789 }
9790
9791 int intel_get_load_detect_pipe(struct drm_connector *connector,
9792                                const struct drm_display_mode *mode,
9793                                struct intel_load_detect_pipe *old,
9794                                struct drm_modeset_acquire_ctx *ctx)
9795 {
9796         struct intel_crtc *intel_crtc;
9797         struct intel_encoder *intel_encoder =
9798                 intel_attached_encoder(connector);
9799         struct drm_crtc *possible_crtc;
9800         struct drm_encoder *encoder = &intel_encoder->base;
9801         struct drm_crtc *crtc = NULL;
9802         struct drm_device *dev = encoder->dev;
9803         struct drm_i915_private *dev_priv = to_i915(dev);
9804         struct drm_framebuffer *fb;
9805         struct drm_mode_config *config = &dev->mode_config;
9806         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9807         struct drm_connector_state *connector_state;
9808         struct intel_crtc_state *crtc_state;
9809         int ret, i = -1;
9810
9811         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9812                       connector->base.id, connector->name,
9813                       encoder->base.id, encoder->name);
9814
9815         old->restore_state = NULL;
9816
9817         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9818
9819         /*
9820          * Algorithm gets a little messy:
9821          *
9822          *   - if the connector already has an assigned crtc, use it (but make
9823          *     sure it's on first)
9824          *
9825          *   - try to find the first unused crtc that can drive this connector,
9826          *     and use that if we find one
9827          */
9828
9829         /* See if we already have a CRTC for this connector */
9830         if (connector->state->crtc) {
9831                 crtc = connector->state->crtc;
9832
9833                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9834                 if (ret)
9835                         goto fail;
9836
9837                 /* Make sure the crtc and connector are running */
9838                 goto found;
9839         }
9840
9841         /* Find an unused one (if possible) */
9842         for_each_crtc(dev, possible_crtc) {
9843                 i++;
9844                 if (!(encoder->possible_crtcs & (1 << i)))
9845                         continue;
9846
9847                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9848                 if (ret)
9849                         goto fail;
9850
9851                 if (possible_crtc->state->enable) {
9852                         drm_modeset_unlock(&possible_crtc->mutex);
9853                         continue;
9854                 }
9855
9856                 crtc = possible_crtc;
9857                 break;
9858         }
9859
9860         /*
9861          * If we didn't find an unused CRTC, don't use any.
9862          */
9863         if (!crtc) {
9864                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9865                 ret = -ENODEV;
9866                 goto fail;
9867         }
9868
9869 found:
9870         intel_crtc = to_intel_crtc(crtc);
9871
9872         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9873         if (ret)
9874                 goto fail;
9875
9876         state = drm_atomic_state_alloc(dev);
9877         restore_state = drm_atomic_state_alloc(dev);
9878         if (!state || !restore_state) {
9879                 ret = -ENOMEM;
9880                 goto fail;
9881         }
9882
9883         state->acquire_ctx = ctx;
9884         restore_state->acquire_ctx = ctx;
9885
9886         connector_state = drm_atomic_get_connector_state(state, connector);
9887         if (IS_ERR(connector_state)) {
9888                 ret = PTR_ERR(connector_state);
9889                 goto fail;
9890         }
9891
9892         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9893         if (ret)
9894                 goto fail;
9895
9896         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9897         if (IS_ERR(crtc_state)) {
9898                 ret = PTR_ERR(crtc_state);
9899                 goto fail;
9900         }
9901
9902         crtc_state->base.active = crtc_state->base.enable = true;
9903
9904         if (!mode)
9905                 mode = &load_detect_mode;
9906
9907         /* We need a framebuffer large enough to accommodate all accesses
9908          * that the plane may generate whilst we perform load detection.
9909          * We can not rely on the fbcon either being present (we get called
9910          * during its initialisation to detect all boot displays, or it may
9911          * not even exist) or that it is large enough to satisfy the
9912          * requested mode.
9913          */
9914         fb = mode_fits_in_fbdev(dev, mode);
9915         if (fb == NULL) {
9916                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9917                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9918         } else
9919                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9920         if (IS_ERR(fb)) {
9921                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9922                 ret = PTR_ERR(fb);
9923                 goto fail;
9924         }
9925
9926         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9927         if (ret)
9928                 goto fail;
9929
9930         drm_framebuffer_put(fb);
9931
9932         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9933         if (ret)
9934                 goto fail;
9935
9936         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9937         if (!ret)
9938                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9939         if (!ret)
9940                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9941         if (ret) {
9942                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9943                 goto fail;
9944         }
9945
9946         ret = drm_atomic_commit(state);
9947         if (ret) {
9948                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9949                 goto fail;
9950         }
9951
9952         old->restore_state = restore_state;
9953         drm_atomic_state_put(state);
9954
9955         /* let the connector get through one full cycle before testing */
9956         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9957         return true;
9958
9959 fail:
9960         if (state) {
9961                 drm_atomic_state_put(state);
9962                 state = NULL;
9963         }
9964         if (restore_state) {
9965                 drm_atomic_state_put(restore_state);
9966                 restore_state = NULL;
9967         }
9968
9969         if (ret == -EDEADLK)
9970                 return ret;
9971
9972         return false;
9973 }
9974
9975 void intel_release_load_detect_pipe(struct drm_connector *connector,
9976                                     struct intel_load_detect_pipe *old,
9977                                     struct drm_modeset_acquire_ctx *ctx)
9978 {
9979         struct intel_encoder *intel_encoder =
9980                 intel_attached_encoder(connector);
9981         struct drm_encoder *encoder = &intel_encoder->base;
9982         struct drm_atomic_state *state = old->restore_state;
9983         int ret;
9984
9985         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9986                       connector->base.id, connector->name,
9987                       encoder->base.id, encoder->name);
9988
9989         if (!state)
9990                 return;
9991
9992         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9993         if (ret)
9994                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9995         drm_atomic_state_put(state);
9996 }
9997
9998 static int i9xx_pll_refclk(struct drm_device *dev,
9999                            const struct intel_crtc_state *pipe_config)
10000 {
10001         struct drm_i915_private *dev_priv = to_i915(dev);
10002         u32 dpll = pipe_config->dpll_hw_state.dpll;
10003
10004         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10005                 return dev_priv->vbt.lvds_ssc_freq;
10006         else if (HAS_PCH_SPLIT(dev_priv))
10007                 return 120000;
10008         else if (!IS_GEN2(dev_priv))
10009                 return 96000;
10010         else
10011                 return 48000;
10012 }
10013
10014 /* Returns the clock of the currently programmed mode of the given pipe. */
10015 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10016                                 struct intel_crtc_state *pipe_config)
10017 {
10018         struct drm_device *dev = crtc->base.dev;
10019         struct drm_i915_private *dev_priv = to_i915(dev);
10020         int pipe = pipe_config->cpu_transcoder;
10021         u32 dpll = pipe_config->dpll_hw_state.dpll;
10022         u32 fp;
10023         struct dpll clock;
10024         int port_clock;
10025         int refclk = i9xx_pll_refclk(dev, pipe_config);
10026
10027         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10028                 fp = pipe_config->dpll_hw_state.fp0;
10029         else
10030                 fp = pipe_config->dpll_hw_state.fp1;
10031
10032         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10033         if (IS_PINEVIEW(dev_priv)) {
10034                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10035                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10036         } else {
10037                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10038                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10039         }
10040
10041         if (!IS_GEN2(dev_priv)) {
10042                 if (IS_PINEVIEW(dev_priv))
10043                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10044                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10045                 else
10046                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10047                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10048
10049                 switch (dpll & DPLL_MODE_MASK) {
10050                 case DPLLB_MODE_DAC_SERIAL:
10051                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10052                                 5 : 10;
10053                         break;
10054                 case DPLLB_MODE_LVDS:
10055                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10056                                 7 : 14;
10057                         break;
10058                 default:
10059                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10060                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10061                         return;
10062                 }
10063
10064                 if (IS_PINEVIEW(dev_priv))
10065                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10066                 else
10067                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10068         } else {
10069                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10070                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10071
10072                 if (is_lvds) {
10073                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10074                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10075
10076                         if (lvds & LVDS_CLKB_POWER_UP)
10077                                 clock.p2 = 7;
10078                         else
10079                                 clock.p2 = 14;
10080                 } else {
10081                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10082                                 clock.p1 = 2;
10083                         else {
10084                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10085                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10086                         }
10087                         if (dpll & PLL_P2_DIVIDE_BY_4)
10088                                 clock.p2 = 4;
10089                         else
10090                                 clock.p2 = 2;
10091                 }
10092
10093                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10094         }
10095
10096         /*
10097          * This value includes pixel_multiplier. We will use
10098          * port_clock to compute adjusted_mode.crtc_clock in the
10099          * encoder's get_config() function.
10100          */
10101         pipe_config->port_clock = port_clock;
10102 }
10103
10104 int intel_dotclock_calculate(int link_freq,
10105                              const struct intel_link_m_n *m_n)
10106 {
10107         /*
10108          * The calculation for the data clock is:
10109          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10110          * But we want to avoid losing precison if possible, so:
10111          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10112          *
10113          * and the link clock is simpler:
10114          * link_clock = (m * link_clock) / n
10115          */
10116
10117         if (!m_n->link_n)
10118                 return 0;
10119
10120         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10121 }
10122
10123 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10124                                    struct intel_crtc_state *pipe_config)
10125 {
10126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10127
10128         /* read out port_clock from the DPLL */
10129         i9xx_crtc_clock_get(crtc, pipe_config);
10130
10131         /*
10132          * In case there is an active pipe without active ports,
10133          * we may need some idea for the dotclock anyway.
10134          * Calculate one based on the FDI configuration.
10135          */
10136         pipe_config->base.adjusted_mode.crtc_clock =
10137                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10138                                          &pipe_config->fdi_m_n);
10139 }
10140
10141 /* Returns the currently programmed mode of the given encoder. */
10142 struct drm_display_mode *
10143 intel_encoder_current_mode(struct intel_encoder *encoder)
10144 {
10145         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10146         struct intel_crtc_state *crtc_state;
10147         struct drm_display_mode *mode;
10148         struct intel_crtc *crtc;
10149         enum pipe pipe;
10150
10151         if (!encoder->get_hw_state(encoder, &pipe))
10152                 return NULL;
10153
10154         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10155
10156         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10157         if (!mode)
10158                 return NULL;
10159
10160         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10161         if (!crtc_state) {
10162                 kfree(mode);
10163                 return NULL;
10164         }
10165
10166         crtc_state->base.crtc = &crtc->base;
10167
10168         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10169                 kfree(crtc_state);
10170                 kfree(mode);
10171                 return NULL;
10172         }
10173
10174         encoder->get_config(encoder, crtc_state);
10175
10176         intel_mode_from_pipe_config(mode, crtc_state);
10177
10178         kfree(crtc_state);
10179
10180         return mode;
10181 }
10182
10183 static void intel_crtc_destroy(struct drm_crtc *crtc)
10184 {
10185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10186
10187         drm_crtc_cleanup(crtc);
10188         kfree(intel_crtc);
10189 }
10190
10191 /**
10192  * intel_wm_need_update - Check whether watermarks need updating
10193  * @plane: drm plane
10194  * @state: new plane state
10195  *
10196  * Check current plane state versus the new one to determine whether
10197  * watermarks need to be recalculated.
10198  *
10199  * Returns true or false.
10200  */
10201 static bool intel_wm_need_update(struct drm_plane *plane,
10202                                  struct drm_plane_state *state)
10203 {
10204         struct intel_plane_state *new = to_intel_plane_state(state);
10205         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10206
10207         /* Update watermarks on tiling or size changes. */
10208         if (new->base.visible != cur->base.visible)
10209                 return true;
10210
10211         if (!cur->base.fb || !new->base.fb)
10212                 return false;
10213
10214         if (cur->base.fb->modifier != new->base.fb->modifier ||
10215             cur->base.rotation != new->base.rotation ||
10216             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10217             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10218             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10219             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10220                 return true;
10221
10222         return false;
10223 }
10224
10225 static bool needs_scaling(const struct intel_plane_state *state)
10226 {
10227         int src_w = drm_rect_width(&state->base.src) >> 16;
10228         int src_h = drm_rect_height(&state->base.src) >> 16;
10229         int dst_w = drm_rect_width(&state->base.dst);
10230         int dst_h = drm_rect_height(&state->base.dst);
10231
10232         return (src_w != dst_w || src_h != dst_h);
10233 }
10234
10235 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10236                                     struct drm_crtc_state *crtc_state,
10237                                     const struct intel_plane_state *old_plane_state,
10238                                     struct drm_plane_state *plane_state)
10239 {
10240         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10241         struct drm_crtc *crtc = crtc_state->crtc;
10242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10243         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10244         struct drm_device *dev = crtc->dev;
10245         struct drm_i915_private *dev_priv = to_i915(dev);
10246         bool mode_changed = needs_modeset(crtc_state);
10247         bool was_crtc_enabled = old_crtc_state->base.active;
10248         bool is_crtc_enabled = crtc_state->active;
10249         bool turn_off, turn_on, visible, was_visible;
10250         struct drm_framebuffer *fb = plane_state->fb;
10251         int ret;
10252
10253         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10254                 ret = skl_update_scaler_plane(
10255                         to_intel_crtc_state(crtc_state),
10256                         to_intel_plane_state(plane_state));
10257                 if (ret)
10258                         return ret;
10259         }
10260
10261         was_visible = old_plane_state->base.visible;
10262         visible = plane_state->visible;
10263
10264         if (!was_crtc_enabled && WARN_ON(was_visible))
10265                 was_visible = false;
10266
10267         /*
10268          * Visibility is calculated as if the crtc was on, but
10269          * after scaler setup everything depends on it being off
10270          * when the crtc isn't active.
10271          *
10272          * FIXME this is wrong for watermarks. Watermarks should also
10273          * be computed as if the pipe would be active. Perhaps move
10274          * per-plane wm computation to the .check_plane() hook, and
10275          * only combine the results from all planes in the current place?
10276          */
10277         if (!is_crtc_enabled) {
10278                 plane_state->visible = visible = false;
10279                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10280         }
10281
10282         if (!was_visible && !visible)
10283                 return 0;
10284
10285         if (fb != old_plane_state->base.fb)
10286                 pipe_config->fb_changed = true;
10287
10288         turn_off = was_visible && (!visible || mode_changed);
10289         turn_on = visible && (!was_visible || mode_changed);
10290
10291         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10292                          intel_crtc->base.base.id, intel_crtc->base.name,
10293                          plane->base.base.id, plane->base.name,
10294                          fb ? fb->base.id : -1);
10295
10296         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10297                          plane->base.base.id, plane->base.name,
10298                          was_visible, visible,
10299                          turn_off, turn_on, mode_changed);
10300
10301         if (turn_on) {
10302                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10303                         pipe_config->update_wm_pre = true;
10304
10305                 /* must disable cxsr around plane enable/disable */
10306                 if (plane->id != PLANE_CURSOR)
10307                         pipe_config->disable_cxsr = true;
10308         } else if (turn_off) {
10309                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10310                         pipe_config->update_wm_post = true;
10311
10312                 /* must disable cxsr around plane enable/disable */
10313                 if (plane->id != PLANE_CURSOR)
10314                         pipe_config->disable_cxsr = true;
10315         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10316                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10317                         /* FIXME bollocks */
10318                         pipe_config->update_wm_pre = true;
10319                         pipe_config->update_wm_post = true;
10320                 }
10321         }
10322
10323         if (visible || was_visible)
10324                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10325
10326         /*
10327          * WaCxSRDisabledForSpriteScaling:ivb
10328          *
10329          * cstate->update_wm was already set above, so this flag will
10330          * take effect when we commit and program watermarks.
10331          */
10332         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10333             needs_scaling(to_intel_plane_state(plane_state)) &&
10334             !needs_scaling(old_plane_state))
10335                 pipe_config->disable_lp_wm = true;
10336
10337         return 0;
10338 }
10339
10340 static bool encoders_cloneable(const struct intel_encoder *a,
10341                                const struct intel_encoder *b)
10342 {
10343         /* masks could be asymmetric, so check both ways */
10344         return a == b || (a->cloneable & (1 << b->type) &&
10345                           b->cloneable & (1 << a->type));
10346 }
10347
10348 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10349                                          struct intel_crtc *crtc,
10350                                          struct intel_encoder *encoder)
10351 {
10352         struct intel_encoder *source_encoder;
10353         struct drm_connector *connector;
10354         struct drm_connector_state *connector_state;
10355         int i;
10356
10357         for_each_new_connector_in_state(state, connector, connector_state, i) {
10358                 if (connector_state->crtc != &crtc->base)
10359                         continue;
10360
10361                 source_encoder =
10362                         to_intel_encoder(connector_state->best_encoder);
10363                 if (!encoders_cloneable(encoder, source_encoder))
10364                         return false;
10365         }
10366
10367         return true;
10368 }
10369
10370 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10371                                    struct drm_crtc_state *crtc_state)
10372 {
10373         struct drm_device *dev = crtc->dev;
10374         struct drm_i915_private *dev_priv = to_i915(dev);
10375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10376         struct intel_crtc_state *pipe_config =
10377                 to_intel_crtc_state(crtc_state);
10378         struct drm_atomic_state *state = crtc_state->state;
10379         int ret;
10380         bool mode_changed = needs_modeset(crtc_state);
10381
10382         if (mode_changed && !crtc_state->active)
10383                 pipe_config->update_wm_post = true;
10384
10385         if (mode_changed && crtc_state->enable &&
10386             dev_priv->display.crtc_compute_clock &&
10387             !WARN_ON(pipe_config->shared_dpll)) {
10388                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10389                                                            pipe_config);
10390                 if (ret)
10391                         return ret;
10392         }
10393
10394         if (crtc_state->color_mgmt_changed) {
10395                 ret = intel_color_check(crtc, crtc_state);
10396                 if (ret)
10397                         return ret;
10398
10399                 /*
10400                  * Changing color management on Intel hardware is
10401                  * handled as part of planes update.
10402                  */
10403                 crtc_state->planes_changed = true;
10404         }
10405
10406         ret = 0;
10407         if (dev_priv->display.compute_pipe_wm) {
10408                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10409                 if (ret) {
10410                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10411                         return ret;
10412                 }
10413         }
10414
10415         if (dev_priv->display.compute_intermediate_wm &&
10416             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10417                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10418                         return 0;
10419
10420                 /*
10421                  * Calculate 'intermediate' watermarks that satisfy both the
10422                  * old state and the new state.  We can program these
10423                  * immediately.
10424                  */
10425                 ret = dev_priv->display.compute_intermediate_wm(dev,
10426                                                                 intel_crtc,
10427                                                                 pipe_config);
10428                 if (ret) {
10429                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10430                         return ret;
10431                 }
10432         } else if (dev_priv->display.compute_intermediate_wm) {
10433                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10434                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10435         }
10436
10437         if (INTEL_GEN(dev_priv) >= 9) {
10438                 if (mode_changed)
10439                         ret = skl_update_scaler_crtc(pipe_config);
10440
10441                 if (!ret)
10442                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10443                                                             pipe_config);
10444                 if (!ret)
10445                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10446                                                          pipe_config);
10447         }
10448
10449         return ret;
10450 }
10451
10452 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10453         .atomic_begin = intel_begin_crtc_commit,
10454         .atomic_flush = intel_finish_crtc_commit,
10455         .atomic_check = intel_crtc_atomic_check,
10456 };
10457
10458 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10459 {
10460         struct intel_connector *connector;
10461         struct drm_connector_list_iter conn_iter;
10462
10463         drm_connector_list_iter_begin(dev, &conn_iter);
10464         for_each_intel_connector_iter(connector, &conn_iter) {
10465                 if (connector->base.state->crtc)
10466                         drm_connector_unreference(&connector->base);
10467
10468                 if (connector->base.encoder) {
10469                         connector->base.state->best_encoder =
10470                                 connector->base.encoder;
10471                         connector->base.state->crtc =
10472                                 connector->base.encoder->crtc;
10473
10474                         drm_connector_reference(&connector->base);
10475                 } else {
10476                         connector->base.state->best_encoder = NULL;
10477                         connector->base.state->crtc = NULL;
10478                 }
10479         }
10480         drm_connector_list_iter_end(&conn_iter);
10481 }
10482
10483 static void
10484 connected_sink_compute_bpp(struct intel_connector *connector,
10485                            struct intel_crtc_state *pipe_config)
10486 {
10487         const struct drm_display_info *info = &connector->base.display_info;
10488         int bpp = pipe_config->pipe_bpp;
10489
10490         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10491                       connector->base.base.id,
10492                       connector->base.name);
10493
10494         /* Don't use an invalid EDID bpc value */
10495         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10496                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10497                               bpp, info->bpc * 3);
10498                 pipe_config->pipe_bpp = info->bpc * 3;
10499         }
10500
10501         /* Clamp bpp to 8 on screens without EDID 1.4 */
10502         if (info->bpc == 0 && bpp > 24) {
10503                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10504                               bpp);
10505                 pipe_config->pipe_bpp = 24;
10506         }
10507 }
10508
10509 static int
10510 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10511                           struct intel_crtc_state *pipe_config)
10512 {
10513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10514         struct drm_atomic_state *state;
10515         struct drm_connector *connector;
10516         struct drm_connector_state *connector_state;
10517         int bpp, i;
10518
10519         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10520             IS_CHERRYVIEW(dev_priv)))
10521                 bpp = 10*3;
10522         else if (INTEL_GEN(dev_priv) >= 5)
10523                 bpp = 12*3;
10524         else
10525                 bpp = 8*3;
10526
10527
10528         pipe_config->pipe_bpp = bpp;
10529
10530         state = pipe_config->base.state;
10531
10532         /* Clamp display bpp to EDID value */
10533         for_each_new_connector_in_state(state, connector, connector_state, i) {
10534                 if (connector_state->crtc != &crtc->base)
10535                         continue;
10536
10537                 connected_sink_compute_bpp(to_intel_connector(connector),
10538                                            pipe_config);
10539         }
10540
10541         return bpp;
10542 }
10543
10544 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10545 {
10546         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10547                         "type: 0x%x flags: 0x%x\n",
10548                 mode->crtc_clock,
10549                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10550                 mode->crtc_hsync_end, mode->crtc_htotal,
10551                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10552                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10553 }
10554
10555 static inline void
10556 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10557                       unsigned int lane_count, struct intel_link_m_n *m_n)
10558 {
10559         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10560                       id, lane_count,
10561                       m_n->gmch_m, m_n->gmch_n,
10562                       m_n->link_m, m_n->link_n, m_n->tu);
10563 }
10564
10565 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10566
10567 static const char * const output_type_str[] = {
10568         OUTPUT_TYPE(UNUSED),
10569         OUTPUT_TYPE(ANALOG),
10570         OUTPUT_TYPE(DVO),
10571         OUTPUT_TYPE(SDVO),
10572         OUTPUT_TYPE(LVDS),
10573         OUTPUT_TYPE(TVOUT),
10574         OUTPUT_TYPE(HDMI),
10575         OUTPUT_TYPE(DP),
10576         OUTPUT_TYPE(EDP),
10577         OUTPUT_TYPE(DSI),
10578         OUTPUT_TYPE(DDI),
10579         OUTPUT_TYPE(DP_MST),
10580 };
10581
10582 #undef OUTPUT_TYPE
10583
10584 static void snprintf_output_types(char *buf, size_t len,
10585                                   unsigned int output_types)
10586 {
10587         char *str = buf;
10588         int i;
10589
10590         str[0] = '\0';
10591
10592         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10593                 int r;
10594
10595                 if ((output_types & BIT(i)) == 0)
10596                         continue;
10597
10598                 r = snprintf(str, len, "%s%s",
10599                              str != buf ? "," : "", output_type_str[i]);
10600                 if (r >= len)
10601                         break;
10602                 str += r;
10603                 len -= r;
10604
10605                 output_types &= ~BIT(i);
10606         }
10607
10608         WARN_ON_ONCE(output_types != 0);
10609 }
10610
10611 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10612                                    struct intel_crtc_state *pipe_config,
10613                                    const char *context)
10614 {
10615         struct drm_device *dev = crtc->base.dev;
10616         struct drm_i915_private *dev_priv = to_i915(dev);
10617         struct drm_plane *plane;
10618         struct intel_plane *intel_plane;
10619         struct intel_plane_state *state;
10620         struct drm_framebuffer *fb;
10621         char buf[64];
10622
10623         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10624                       crtc->base.base.id, crtc->base.name, context);
10625
10626         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10627         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10628                       buf, pipe_config->output_types);
10629
10630         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10631                       transcoder_name(pipe_config->cpu_transcoder),
10632                       pipe_config->pipe_bpp, pipe_config->dither);
10633
10634         if (pipe_config->has_pch_encoder)
10635                 intel_dump_m_n_config(pipe_config, "fdi",
10636                                       pipe_config->fdi_lanes,
10637                                       &pipe_config->fdi_m_n);
10638
10639         if (pipe_config->ycbcr420)
10640                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10641
10642         if (intel_crtc_has_dp_encoder(pipe_config)) {
10643                 intel_dump_m_n_config(pipe_config, "dp m_n",
10644                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10645                 if (pipe_config->has_drrs)
10646                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10647                                               pipe_config->lane_count,
10648                                               &pipe_config->dp_m2_n2);
10649         }
10650
10651         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10652                       pipe_config->has_audio, pipe_config->has_infoframe);
10653
10654         DRM_DEBUG_KMS("requested mode:\n");
10655         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10656         DRM_DEBUG_KMS("adjusted mode:\n");
10657         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10658         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10659         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10660                       pipe_config->port_clock,
10661                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10662                       pipe_config->pixel_rate);
10663
10664         if (INTEL_GEN(dev_priv) >= 9)
10665                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10666                               crtc->num_scalers,
10667                               pipe_config->scaler_state.scaler_users,
10668                               pipe_config->scaler_state.scaler_id);
10669
10670         if (HAS_GMCH_DISPLAY(dev_priv))
10671                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10672                               pipe_config->gmch_pfit.control,
10673                               pipe_config->gmch_pfit.pgm_ratios,
10674                               pipe_config->gmch_pfit.lvds_border_bits);
10675         else
10676                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10677                               pipe_config->pch_pfit.pos,
10678                               pipe_config->pch_pfit.size,
10679                               enableddisabled(pipe_config->pch_pfit.enabled));
10680
10681         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10682                       pipe_config->ips_enabled, pipe_config->double_wide);
10683
10684         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10685
10686         DRM_DEBUG_KMS("planes on this crtc\n");
10687         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10688                 struct drm_format_name_buf format_name;
10689                 intel_plane = to_intel_plane(plane);
10690                 if (intel_plane->pipe != crtc->pipe)
10691                         continue;
10692
10693                 state = to_intel_plane_state(plane->state);
10694                 fb = state->base.fb;
10695                 if (!fb) {
10696                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10697                                       plane->base.id, plane->name, state->scaler_id);
10698                         continue;
10699                 }
10700
10701                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10702                               plane->base.id, plane->name,
10703                               fb->base.id, fb->width, fb->height,
10704                               drm_get_format_name(fb->format->format, &format_name));
10705                 if (INTEL_GEN(dev_priv) >= 9)
10706                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10707                                       state->scaler_id,
10708                                       state->base.src.x1 >> 16,
10709                                       state->base.src.y1 >> 16,
10710                                       drm_rect_width(&state->base.src) >> 16,
10711                                       drm_rect_height(&state->base.src) >> 16,
10712                                       state->base.dst.x1, state->base.dst.y1,
10713                                       drm_rect_width(&state->base.dst),
10714                                       drm_rect_height(&state->base.dst));
10715         }
10716 }
10717
10718 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10719 {
10720         struct drm_device *dev = state->dev;
10721         struct drm_connector *connector;
10722         struct drm_connector_list_iter conn_iter;
10723         unsigned int used_ports = 0;
10724         unsigned int used_mst_ports = 0;
10725
10726         /*
10727          * Walk the connector list instead of the encoder
10728          * list to detect the problem on ddi platforms
10729          * where there's just one encoder per digital port.
10730          */
10731         drm_connector_list_iter_begin(dev, &conn_iter);
10732         drm_for_each_connector_iter(connector, &conn_iter) {
10733                 struct drm_connector_state *connector_state;
10734                 struct intel_encoder *encoder;
10735
10736                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10737                 if (!connector_state)
10738                         connector_state = connector->state;
10739
10740                 if (!connector_state->best_encoder)
10741                         continue;
10742
10743                 encoder = to_intel_encoder(connector_state->best_encoder);
10744
10745                 WARN_ON(!connector_state->crtc);
10746
10747                 switch (encoder->type) {
10748                         unsigned int port_mask;
10749                 case INTEL_OUTPUT_DDI:
10750                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10751                                 break;
10752                 case INTEL_OUTPUT_DP:
10753                 case INTEL_OUTPUT_HDMI:
10754                 case INTEL_OUTPUT_EDP:
10755                         port_mask = 1 << encoder->port;
10756
10757                         /* the same port mustn't appear more than once */
10758                         if (used_ports & port_mask)
10759                                 return false;
10760
10761                         used_ports |= port_mask;
10762                         break;
10763                 case INTEL_OUTPUT_DP_MST:
10764                         used_mst_ports |=
10765                                 1 << encoder->port;
10766                         break;
10767                 default:
10768                         break;
10769                 }
10770         }
10771         drm_connector_list_iter_end(&conn_iter);
10772
10773         /* can't mix MST and SST/HDMI on the same port */
10774         if (used_ports & used_mst_ports)
10775                 return false;
10776
10777         return true;
10778 }
10779
10780 static void
10781 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10782 {
10783         struct drm_i915_private *dev_priv =
10784                 to_i915(crtc_state->base.crtc->dev);
10785         struct intel_crtc_scaler_state scaler_state;
10786         struct intel_dpll_hw_state dpll_hw_state;
10787         struct intel_shared_dpll *shared_dpll;
10788         struct intel_crtc_wm_state wm_state;
10789         bool force_thru, ips_force_disable;
10790
10791         /* FIXME: before the switch to atomic started, a new pipe_config was
10792          * kzalloc'd. Code that depends on any field being zero should be
10793          * fixed, so that the crtc_state can be safely duplicated. For now,
10794          * only fields that are know to not cause problems are preserved. */
10795
10796         scaler_state = crtc_state->scaler_state;
10797         shared_dpll = crtc_state->shared_dpll;
10798         dpll_hw_state = crtc_state->dpll_hw_state;
10799         force_thru = crtc_state->pch_pfit.force_thru;
10800         ips_force_disable = crtc_state->ips_force_disable;
10801         if (IS_G4X(dev_priv) ||
10802             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10803                 wm_state = crtc_state->wm;
10804
10805         /* Keep base drm_crtc_state intact, only clear our extended struct */
10806         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10807         memset(&crtc_state->base + 1, 0,
10808                sizeof(*crtc_state) - sizeof(crtc_state->base));
10809
10810         crtc_state->scaler_state = scaler_state;
10811         crtc_state->shared_dpll = shared_dpll;
10812         crtc_state->dpll_hw_state = dpll_hw_state;
10813         crtc_state->pch_pfit.force_thru = force_thru;
10814         crtc_state->ips_force_disable = ips_force_disable;
10815         if (IS_G4X(dev_priv) ||
10816             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10817                 crtc_state->wm = wm_state;
10818 }
10819
10820 static int
10821 intel_modeset_pipe_config(struct drm_crtc *crtc,
10822                           struct intel_crtc_state *pipe_config)
10823 {
10824         struct drm_atomic_state *state = pipe_config->base.state;
10825         struct intel_encoder *encoder;
10826         struct drm_connector *connector;
10827         struct drm_connector_state *connector_state;
10828         int base_bpp, ret = -EINVAL;
10829         int i;
10830         bool retry = true;
10831
10832         clear_intel_crtc_state(pipe_config);
10833
10834         pipe_config->cpu_transcoder =
10835                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10836
10837         /*
10838          * Sanitize sync polarity flags based on requested ones. If neither
10839          * positive or negative polarity is requested, treat this as meaning
10840          * negative polarity.
10841          */
10842         if (!(pipe_config->base.adjusted_mode.flags &
10843               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10844                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10845
10846         if (!(pipe_config->base.adjusted_mode.flags &
10847               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10848                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10849
10850         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10851                                              pipe_config);
10852         if (base_bpp < 0)
10853                 goto fail;
10854
10855         /*
10856          * Determine the real pipe dimensions. Note that stereo modes can
10857          * increase the actual pipe size due to the frame doubling and
10858          * insertion of additional space for blanks between the frame. This
10859          * is stored in the crtc timings. We use the requested mode to do this
10860          * computation to clearly distinguish it from the adjusted mode, which
10861          * can be changed by the connectors in the below retry loop.
10862          */
10863         drm_mode_get_hv_timing(&pipe_config->base.mode,
10864                                &pipe_config->pipe_src_w,
10865                                &pipe_config->pipe_src_h);
10866
10867         for_each_new_connector_in_state(state, connector, connector_state, i) {
10868                 if (connector_state->crtc != crtc)
10869                         continue;
10870
10871                 encoder = to_intel_encoder(connector_state->best_encoder);
10872
10873                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10874                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10875                         goto fail;
10876                 }
10877
10878                 /*
10879                  * Determine output_types before calling the .compute_config()
10880                  * hooks so that the hooks can use this information safely.
10881                  */
10882                 if (encoder->compute_output_type)
10883                         pipe_config->output_types |=
10884                                 BIT(encoder->compute_output_type(encoder, pipe_config,
10885                                                                  connector_state));
10886                 else
10887                         pipe_config->output_types |= BIT(encoder->type);
10888         }
10889
10890 encoder_retry:
10891         /* Ensure the port clock defaults are reset when retrying. */
10892         pipe_config->port_clock = 0;
10893         pipe_config->pixel_multiplier = 1;
10894
10895         /* Fill in default crtc timings, allow encoders to overwrite them. */
10896         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10897                               CRTC_STEREO_DOUBLE);
10898
10899         /* Pass our mode to the connectors and the CRTC to give them a chance to
10900          * adjust it according to limitations or connector properties, and also
10901          * a chance to reject the mode entirely.
10902          */
10903         for_each_new_connector_in_state(state, connector, connector_state, i) {
10904                 if (connector_state->crtc != crtc)
10905                         continue;
10906
10907                 encoder = to_intel_encoder(connector_state->best_encoder);
10908
10909                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10910                         DRM_DEBUG_KMS("Encoder config failure\n");
10911                         goto fail;
10912                 }
10913         }
10914
10915         /* Set default port clock if not overwritten by the encoder. Needs to be
10916          * done afterwards in case the encoder adjusts the mode. */
10917         if (!pipe_config->port_clock)
10918                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10919                         * pipe_config->pixel_multiplier;
10920
10921         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10922         if (ret < 0) {
10923                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10924                 goto fail;
10925         }
10926
10927         if (ret == RETRY) {
10928                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10929                         ret = -EINVAL;
10930                         goto fail;
10931                 }
10932
10933                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10934                 retry = false;
10935                 goto encoder_retry;
10936         }
10937
10938         /* Dithering seems to not pass-through bits correctly when it should, so
10939          * only enable it on 6bpc panels and when its not a compliance
10940          * test requesting 6bpc video pattern.
10941          */
10942         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
10943                 !pipe_config->dither_force_disable;
10944         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
10945                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10946
10947 fail:
10948         return ret;
10949 }
10950
10951 static void
10952 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
10953 {
10954         struct drm_crtc *crtc;
10955         struct drm_crtc_state *new_crtc_state;
10956         int i;
10957
10958         /* Double check state. */
10959         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10960                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
10961
10962                 /*
10963                  * Update legacy state to satisfy fbc code. This can
10964                  * be removed when fbc uses the atomic state.
10965                  */
10966                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
10967                         struct drm_plane_state *plane_state = crtc->primary->state;
10968
10969                         crtc->primary->fb = plane_state->fb;
10970                         crtc->x = plane_state->src_x >> 16;
10971                         crtc->y = plane_state->src_y >> 16;
10972                 }
10973         }
10974 }
10975
10976 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10977 {
10978         int diff;
10979
10980         if (clock1 == clock2)
10981                 return true;
10982
10983         if (!clock1 || !clock2)
10984                 return false;
10985
10986         diff = abs(clock1 - clock2);
10987
10988         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10989                 return true;
10990
10991         return false;
10992 }
10993
10994 static bool
10995 intel_compare_m_n(unsigned int m, unsigned int n,
10996                   unsigned int m2, unsigned int n2,
10997                   bool exact)
10998 {
10999         if (m == m2 && n == n2)
11000                 return true;
11001
11002         if (exact || !m || !n || !m2 || !n2)
11003                 return false;
11004
11005         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11006
11007         if (n > n2) {
11008                 while (n > n2) {
11009                         m2 <<= 1;
11010                         n2 <<= 1;
11011                 }
11012         } else if (n < n2) {
11013                 while (n < n2) {
11014                         m <<= 1;
11015                         n <<= 1;
11016                 }
11017         }
11018
11019         if (n != n2)
11020                 return false;
11021
11022         return intel_fuzzy_clock_check(m, m2);
11023 }
11024
11025 static bool
11026 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11027                        struct intel_link_m_n *m2_n2,
11028                        bool adjust)
11029 {
11030         if (m_n->tu == m2_n2->tu &&
11031             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11032                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11033             intel_compare_m_n(m_n->link_m, m_n->link_n,
11034                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11035                 if (adjust)
11036                         *m2_n2 = *m_n;
11037
11038                 return true;
11039         }
11040
11041         return false;
11042 }
11043
11044 static void __printf(3, 4)
11045 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11046 {
11047         char *level;
11048         unsigned int category;
11049         struct va_format vaf;
11050         va_list args;
11051
11052         if (adjust) {
11053                 level = KERN_DEBUG;
11054                 category = DRM_UT_KMS;
11055         } else {
11056                 level = KERN_ERR;
11057                 category = DRM_UT_NONE;
11058         }
11059
11060         va_start(args, format);
11061         vaf.fmt = format;
11062         vaf.va = &args;
11063
11064         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11065
11066         va_end(args);
11067 }
11068
11069 static bool
11070 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11071                           struct intel_crtc_state *current_config,
11072                           struct intel_crtc_state *pipe_config,
11073                           bool adjust)
11074 {
11075         bool ret = true;
11076
11077 #define PIPE_CONF_CHECK_X(name) \
11078         if (current_config->name != pipe_config->name) { \
11079                 pipe_config_err(adjust, __stringify(name), \
11080                           "(expected 0x%08x, found 0x%08x)\n", \
11081                           current_config->name, \
11082                           pipe_config->name); \
11083                 ret = false; \
11084         }
11085
11086 #define PIPE_CONF_CHECK_I(name) \
11087         if (current_config->name != pipe_config->name) { \
11088                 pipe_config_err(adjust, __stringify(name), \
11089                           "(expected %i, found %i)\n", \
11090                           current_config->name, \
11091                           pipe_config->name); \
11092                 ret = false; \
11093         }
11094
11095 #define PIPE_CONF_CHECK_P(name) \
11096         if (current_config->name != pipe_config->name) { \
11097                 pipe_config_err(adjust, __stringify(name), \
11098                           "(expected %p, found %p)\n", \
11099                           current_config->name, \
11100                           pipe_config->name); \
11101                 ret = false; \
11102         }
11103
11104 #define PIPE_CONF_CHECK_M_N(name) \
11105         if (!intel_compare_link_m_n(&current_config->name, \
11106                                     &pipe_config->name,\
11107                                     adjust)) { \
11108                 pipe_config_err(adjust, __stringify(name), \
11109                           "(expected tu %i gmch %i/%i link %i/%i, " \
11110                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11111                           current_config->name.tu, \
11112                           current_config->name.gmch_m, \
11113                           current_config->name.gmch_n, \
11114                           current_config->name.link_m, \
11115                           current_config->name.link_n, \
11116                           pipe_config->name.tu, \
11117                           pipe_config->name.gmch_m, \
11118                           pipe_config->name.gmch_n, \
11119                           pipe_config->name.link_m, \
11120                           pipe_config->name.link_n); \
11121                 ret = false; \
11122         }
11123
11124 /* This is required for BDW+ where there is only one set of registers for
11125  * switching between high and low RR.
11126  * This macro can be used whenever a comparison has to be made between one
11127  * hw state and multiple sw state variables.
11128  */
11129 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11130         if (!intel_compare_link_m_n(&current_config->name, \
11131                                     &pipe_config->name, adjust) && \
11132             !intel_compare_link_m_n(&current_config->alt_name, \
11133                                     &pipe_config->name, adjust)) { \
11134                 pipe_config_err(adjust, __stringify(name), \
11135                           "(expected tu %i gmch %i/%i link %i/%i, " \
11136                           "or tu %i gmch %i/%i link %i/%i, " \
11137                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11138                           current_config->name.tu, \
11139                           current_config->name.gmch_m, \
11140                           current_config->name.gmch_n, \
11141                           current_config->name.link_m, \
11142                           current_config->name.link_n, \
11143                           current_config->alt_name.tu, \
11144                           current_config->alt_name.gmch_m, \
11145                           current_config->alt_name.gmch_n, \
11146                           current_config->alt_name.link_m, \
11147                           current_config->alt_name.link_n, \
11148                           pipe_config->name.tu, \
11149                           pipe_config->name.gmch_m, \
11150                           pipe_config->name.gmch_n, \
11151                           pipe_config->name.link_m, \
11152                           pipe_config->name.link_n); \
11153                 ret = false; \
11154         }
11155
11156 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11157         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11158                 pipe_config_err(adjust, __stringify(name), \
11159                           "(%x) (expected %i, found %i)\n", \
11160                           (mask), \
11161                           current_config->name & (mask), \
11162                           pipe_config->name & (mask)); \
11163                 ret = false; \
11164         }
11165
11166 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11167         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11168                 pipe_config_err(adjust, __stringify(name), \
11169                           "(expected %i, found %i)\n", \
11170                           current_config->name, \
11171                           pipe_config->name); \
11172                 ret = false; \
11173         }
11174
11175 #define PIPE_CONF_QUIRK(quirk)  \
11176         ((current_config->quirks | pipe_config->quirks) & (quirk))
11177
11178         PIPE_CONF_CHECK_I(cpu_transcoder);
11179
11180         PIPE_CONF_CHECK_I(has_pch_encoder);
11181         PIPE_CONF_CHECK_I(fdi_lanes);
11182         PIPE_CONF_CHECK_M_N(fdi_m_n);
11183
11184         PIPE_CONF_CHECK_I(lane_count);
11185         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11186
11187         if (INTEL_GEN(dev_priv) < 8) {
11188                 PIPE_CONF_CHECK_M_N(dp_m_n);
11189
11190                 if (current_config->has_drrs)
11191                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11192         } else
11193                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11194
11195         PIPE_CONF_CHECK_X(output_types);
11196
11197         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11198         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11199         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11200         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11201         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11202         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11203
11204         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11205         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11206         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11207         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11208         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11209         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11210
11211         PIPE_CONF_CHECK_I(pixel_multiplier);
11212         PIPE_CONF_CHECK_I(has_hdmi_sink);
11213         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11214             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11215                 PIPE_CONF_CHECK_I(limited_color_range);
11216
11217         PIPE_CONF_CHECK_I(hdmi_scrambling);
11218         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11219         PIPE_CONF_CHECK_I(has_infoframe);
11220         PIPE_CONF_CHECK_I(ycbcr420);
11221
11222         PIPE_CONF_CHECK_I(has_audio);
11223
11224         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11225                               DRM_MODE_FLAG_INTERLACE);
11226
11227         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11228                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11229                                       DRM_MODE_FLAG_PHSYNC);
11230                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11231                                       DRM_MODE_FLAG_NHSYNC);
11232                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11233                                       DRM_MODE_FLAG_PVSYNC);
11234                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11235                                       DRM_MODE_FLAG_NVSYNC);
11236         }
11237
11238         PIPE_CONF_CHECK_X(gmch_pfit.control);
11239         /* pfit ratios are autocomputed by the hw on gen4+ */
11240         if (INTEL_GEN(dev_priv) < 4)
11241                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11242         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11243
11244         if (!adjust) {
11245                 PIPE_CONF_CHECK_I(pipe_src_w);
11246                 PIPE_CONF_CHECK_I(pipe_src_h);
11247
11248                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11249                 if (current_config->pch_pfit.enabled) {
11250                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11251                         PIPE_CONF_CHECK_X(pch_pfit.size);
11252                 }
11253
11254                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11255                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11256         }
11257
11258         PIPE_CONF_CHECK_I(double_wide);
11259
11260         PIPE_CONF_CHECK_P(shared_dpll);
11261         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11262         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11263         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11264         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11265         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11266         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11267         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11268         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11269         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11270         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11271         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11272         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11273         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11274         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11275         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11276         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11277         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11278         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11279         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11280         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11281         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11282
11283         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11284         PIPE_CONF_CHECK_X(dsi_pll.div);
11285
11286         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11287                 PIPE_CONF_CHECK_I(pipe_bpp);
11288
11289         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11290         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11291
11292         PIPE_CONF_CHECK_I(min_voltage_level);
11293
11294 #undef PIPE_CONF_CHECK_X
11295 #undef PIPE_CONF_CHECK_I
11296 #undef PIPE_CONF_CHECK_P
11297 #undef PIPE_CONF_CHECK_FLAGS
11298 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11299 #undef PIPE_CONF_QUIRK
11300
11301         return ret;
11302 }
11303
11304 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11305                                            const struct intel_crtc_state *pipe_config)
11306 {
11307         if (pipe_config->has_pch_encoder) {
11308                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11309                                                             &pipe_config->fdi_m_n);
11310                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11311
11312                 /*
11313                  * FDI already provided one idea for the dotclock.
11314                  * Yell if the encoder disagrees.
11315                  */
11316                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11317                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11318                      fdi_dotclock, dotclock);
11319         }
11320 }
11321
11322 static void verify_wm_state(struct drm_crtc *crtc,
11323                             struct drm_crtc_state *new_state)
11324 {
11325         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11326         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11327         struct skl_pipe_wm hw_wm, *sw_wm;
11328         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11329         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331         const enum pipe pipe = intel_crtc->pipe;
11332         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11333
11334         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11335                 return;
11336
11337         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11338         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11339
11340         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11341         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11342
11343         /* planes */
11344         for_each_universal_plane(dev_priv, pipe, plane) {
11345                 hw_plane_wm = &hw_wm.planes[plane];
11346                 sw_plane_wm = &sw_wm->planes[plane];
11347
11348                 /* Watermarks */
11349                 for (level = 0; level <= max_level; level++) {
11350                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11351                                                 &sw_plane_wm->wm[level]))
11352                                 continue;
11353
11354                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11355                                   pipe_name(pipe), plane + 1, level,
11356                                   sw_plane_wm->wm[level].plane_en,
11357                                   sw_plane_wm->wm[level].plane_res_b,
11358                                   sw_plane_wm->wm[level].plane_res_l,
11359                                   hw_plane_wm->wm[level].plane_en,
11360                                   hw_plane_wm->wm[level].plane_res_b,
11361                                   hw_plane_wm->wm[level].plane_res_l);
11362                 }
11363
11364                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11365                                          &sw_plane_wm->trans_wm)) {
11366                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11367                                   pipe_name(pipe), plane + 1,
11368                                   sw_plane_wm->trans_wm.plane_en,
11369                                   sw_plane_wm->trans_wm.plane_res_b,
11370                                   sw_plane_wm->trans_wm.plane_res_l,
11371                                   hw_plane_wm->trans_wm.plane_en,
11372                                   hw_plane_wm->trans_wm.plane_res_b,
11373                                   hw_plane_wm->trans_wm.plane_res_l);
11374                 }
11375
11376                 /* DDB */
11377                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11378                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11379
11380                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11381                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11382                                   pipe_name(pipe), plane + 1,
11383                                   sw_ddb_entry->start, sw_ddb_entry->end,
11384                                   hw_ddb_entry->start, hw_ddb_entry->end);
11385                 }
11386         }
11387
11388         /*
11389          * cursor
11390          * If the cursor plane isn't active, we may not have updated it's ddb
11391          * allocation. In that case since the ddb allocation will be updated
11392          * once the plane becomes visible, we can skip this check
11393          */
11394         if (1) {
11395                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11396                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11397
11398                 /* Watermarks */
11399                 for (level = 0; level <= max_level; level++) {
11400                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11401                                                 &sw_plane_wm->wm[level]))
11402                                 continue;
11403
11404                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11405                                   pipe_name(pipe), level,
11406                                   sw_plane_wm->wm[level].plane_en,
11407                                   sw_plane_wm->wm[level].plane_res_b,
11408                                   sw_plane_wm->wm[level].plane_res_l,
11409                                   hw_plane_wm->wm[level].plane_en,
11410                                   hw_plane_wm->wm[level].plane_res_b,
11411                                   hw_plane_wm->wm[level].plane_res_l);
11412                 }
11413
11414                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11415                                          &sw_plane_wm->trans_wm)) {
11416                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11417                                   pipe_name(pipe),
11418                                   sw_plane_wm->trans_wm.plane_en,
11419                                   sw_plane_wm->trans_wm.plane_res_b,
11420                                   sw_plane_wm->trans_wm.plane_res_l,
11421                                   hw_plane_wm->trans_wm.plane_en,
11422                                   hw_plane_wm->trans_wm.plane_res_b,
11423                                   hw_plane_wm->trans_wm.plane_res_l);
11424                 }
11425
11426                 /* DDB */
11427                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11428                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11429
11430                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11431                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11432                                   pipe_name(pipe),
11433                                   sw_ddb_entry->start, sw_ddb_entry->end,
11434                                   hw_ddb_entry->start, hw_ddb_entry->end);
11435                 }
11436         }
11437 }
11438
11439 static void
11440 verify_connector_state(struct drm_device *dev,
11441                        struct drm_atomic_state *state,
11442                        struct drm_crtc *crtc)
11443 {
11444         struct drm_connector *connector;
11445         struct drm_connector_state *new_conn_state;
11446         int i;
11447
11448         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11449                 struct drm_encoder *encoder = connector->encoder;
11450                 struct drm_crtc_state *crtc_state = NULL;
11451
11452                 if (new_conn_state->crtc != crtc)
11453                         continue;
11454
11455                 if (crtc)
11456                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11457
11458                 intel_connector_verify_state(crtc_state, new_conn_state);
11459
11460                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11461                      "connector's atomic encoder doesn't match legacy encoder\n");
11462         }
11463 }
11464
11465 static void
11466 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11467 {
11468         struct intel_encoder *encoder;
11469         struct drm_connector *connector;
11470         struct drm_connector_state *old_conn_state, *new_conn_state;
11471         int i;
11472
11473         for_each_intel_encoder(dev, encoder) {
11474                 bool enabled = false, found = false;
11475                 enum pipe pipe;
11476
11477                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11478                               encoder->base.base.id,
11479                               encoder->base.name);
11480
11481                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11482                                                    new_conn_state, i) {
11483                         if (old_conn_state->best_encoder == &encoder->base)
11484                                 found = true;
11485
11486                         if (new_conn_state->best_encoder != &encoder->base)
11487                                 continue;
11488                         found = enabled = true;
11489
11490                         I915_STATE_WARN(new_conn_state->crtc !=
11491                                         encoder->base.crtc,
11492                              "connector's crtc doesn't match encoder crtc\n");
11493                 }
11494
11495                 if (!found)
11496                         continue;
11497
11498                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11499                      "encoder's enabled state mismatch "
11500                      "(expected %i, found %i)\n",
11501                      !!encoder->base.crtc, enabled);
11502
11503                 if (!encoder->base.crtc) {
11504                         bool active;
11505
11506                         active = encoder->get_hw_state(encoder, &pipe);
11507                         I915_STATE_WARN(active,
11508                              "encoder detached but still enabled on pipe %c.\n",
11509                              pipe_name(pipe));
11510                 }
11511         }
11512 }
11513
11514 static void
11515 verify_crtc_state(struct drm_crtc *crtc,
11516                   struct drm_crtc_state *old_crtc_state,
11517                   struct drm_crtc_state *new_crtc_state)
11518 {
11519         struct drm_device *dev = crtc->dev;
11520         struct drm_i915_private *dev_priv = to_i915(dev);
11521         struct intel_encoder *encoder;
11522         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11523         struct intel_crtc_state *pipe_config, *sw_config;
11524         struct drm_atomic_state *old_state;
11525         bool active;
11526
11527         old_state = old_crtc_state->state;
11528         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11529         pipe_config = to_intel_crtc_state(old_crtc_state);
11530         memset(pipe_config, 0, sizeof(*pipe_config));
11531         pipe_config->base.crtc = crtc;
11532         pipe_config->base.state = old_state;
11533
11534         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11535
11536         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11537
11538         /* we keep both pipes enabled on 830 */
11539         if (IS_I830(dev_priv))
11540                 active = new_crtc_state->active;
11541
11542         I915_STATE_WARN(new_crtc_state->active != active,
11543              "crtc active state doesn't match with hw state "
11544              "(expected %i, found %i)\n", new_crtc_state->active, active);
11545
11546         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11547              "transitional active state does not match atomic hw state "
11548              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11549
11550         for_each_encoder_on_crtc(dev, crtc, encoder) {
11551                 enum pipe pipe;
11552
11553                 active = encoder->get_hw_state(encoder, &pipe);
11554                 I915_STATE_WARN(active != new_crtc_state->active,
11555                         "[ENCODER:%i] active %i with crtc active %i\n",
11556                         encoder->base.base.id, active, new_crtc_state->active);
11557
11558                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11559                                 "Encoder connected to wrong pipe %c\n",
11560                                 pipe_name(pipe));
11561
11562                 if (active)
11563                         encoder->get_config(encoder, pipe_config);
11564         }
11565
11566         intel_crtc_compute_pixel_rate(pipe_config);
11567
11568         if (!new_crtc_state->active)
11569                 return;
11570
11571         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11572
11573         sw_config = to_intel_crtc_state(new_crtc_state);
11574         if (!intel_pipe_config_compare(dev_priv, sw_config,
11575                                        pipe_config, false)) {
11576                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11577                 intel_dump_pipe_config(intel_crtc, pipe_config,
11578                                        "[hw state]");
11579                 intel_dump_pipe_config(intel_crtc, sw_config,
11580                                        "[sw state]");
11581         }
11582 }
11583
11584 static void
11585 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11586                          struct intel_shared_dpll *pll,
11587                          struct drm_crtc *crtc,
11588                          struct drm_crtc_state *new_state)
11589 {
11590         struct intel_dpll_hw_state dpll_hw_state;
11591         unsigned crtc_mask;
11592         bool active;
11593
11594         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11595
11596         DRM_DEBUG_KMS("%s\n", pll->name);
11597
11598         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11599
11600         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11601                 I915_STATE_WARN(!pll->on && pll->active_mask,
11602                      "pll in active use but not on in sw tracking\n");
11603                 I915_STATE_WARN(pll->on && !pll->active_mask,
11604                      "pll is on but not used by any active crtc\n");
11605                 I915_STATE_WARN(pll->on != active,
11606                      "pll on state mismatch (expected %i, found %i)\n",
11607                      pll->on, active);
11608         }
11609
11610         if (!crtc) {
11611                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11612                                 "more active pll users than references: %x vs %x\n",
11613                                 pll->active_mask, pll->state.crtc_mask);
11614
11615                 return;
11616         }
11617
11618         crtc_mask = 1 << drm_crtc_index(crtc);
11619
11620         if (new_state->active)
11621                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11622                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11623                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11624         else
11625                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11626                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11627                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11628
11629         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11630                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11631                         crtc_mask, pll->state.crtc_mask);
11632
11633         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11634                                           &dpll_hw_state,
11635                                           sizeof(dpll_hw_state)),
11636                         "pll hw state mismatch\n");
11637 }
11638
11639 static void
11640 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11641                          struct drm_crtc_state *old_crtc_state,
11642                          struct drm_crtc_state *new_crtc_state)
11643 {
11644         struct drm_i915_private *dev_priv = to_i915(dev);
11645         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11646         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11647
11648         if (new_state->shared_dpll)
11649                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11650
11651         if (old_state->shared_dpll &&
11652             old_state->shared_dpll != new_state->shared_dpll) {
11653                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11654                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11655
11656                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11657                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11658                                 pipe_name(drm_crtc_index(crtc)));
11659                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11660                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11661                                 pipe_name(drm_crtc_index(crtc)));
11662         }
11663 }
11664
11665 static void
11666 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11667                           struct drm_atomic_state *state,
11668                           struct drm_crtc_state *old_state,
11669                           struct drm_crtc_state *new_state)
11670 {
11671         if (!needs_modeset(new_state) &&
11672             !to_intel_crtc_state(new_state)->update_pipe)
11673                 return;
11674
11675         verify_wm_state(crtc, new_state);
11676         verify_connector_state(crtc->dev, state, crtc);
11677         verify_crtc_state(crtc, old_state, new_state);
11678         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11679 }
11680
11681 static void
11682 verify_disabled_dpll_state(struct drm_device *dev)
11683 {
11684         struct drm_i915_private *dev_priv = to_i915(dev);
11685         int i;
11686
11687         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11688                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11689 }
11690
11691 static void
11692 intel_modeset_verify_disabled(struct drm_device *dev,
11693                               struct drm_atomic_state *state)
11694 {
11695         verify_encoder_state(dev, state);
11696         verify_connector_state(dev, state, NULL);
11697         verify_disabled_dpll_state(dev);
11698 }
11699
11700 static void update_scanline_offset(struct intel_crtc *crtc)
11701 {
11702         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11703
11704         /*
11705          * The scanline counter increments at the leading edge of hsync.
11706          *
11707          * On most platforms it starts counting from vtotal-1 on the
11708          * first active line. That means the scanline counter value is
11709          * always one less than what we would expect. Ie. just after
11710          * start of vblank, which also occurs at start of hsync (on the
11711          * last active line), the scanline counter will read vblank_start-1.
11712          *
11713          * On gen2 the scanline counter starts counting from 1 instead
11714          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11715          * to keep the value positive), instead of adding one.
11716          *
11717          * On HSW+ the behaviour of the scanline counter depends on the output
11718          * type. For DP ports it behaves like most other platforms, but on HDMI
11719          * there's an extra 1 line difference. So we need to add two instead of
11720          * one to the value.
11721          *
11722          * On VLV/CHV DSI the scanline counter would appear to increment
11723          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11724          * that means we can't tell whether we're in vblank or not while
11725          * we're on that particular line. We must still set scanline_offset
11726          * to 1 so that the vblank timestamps come out correct when we query
11727          * the scanline counter from within the vblank interrupt handler.
11728          * However if queried just before the start of vblank we'll get an
11729          * answer that's slightly in the future.
11730          */
11731         if (IS_GEN2(dev_priv)) {
11732                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11733                 int vtotal;
11734
11735                 vtotal = adjusted_mode->crtc_vtotal;
11736                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11737                         vtotal /= 2;
11738
11739                 crtc->scanline_offset = vtotal - 1;
11740         } else if (HAS_DDI(dev_priv) &&
11741                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11742                 crtc->scanline_offset = 2;
11743         } else
11744                 crtc->scanline_offset = 1;
11745 }
11746
11747 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11748 {
11749         struct drm_device *dev = state->dev;
11750         struct drm_i915_private *dev_priv = to_i915(dev);
11751         struct drm_crtc *crtc;
11752         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11753         int i;
11754
11755         if (!dev_priv->display.crtc_compute_clock)
11756                 return;
11757
11758         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11759                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11760                 struct intel_shared_dpll *old_dpll =
11761                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11762
11763                 if (!needs_modeset(new_crtc_state))
11764                         continue;
11765
11766                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11767
11768                 if (!old_dpll)
11769                         continue;
11770
11771                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11772         }
11773 }
11774
11775 /*
11776  * This implements the workaround described in the "notes" section of the mode
11777  * set sequence documentation. When going from no pipes or single pipe to
11778  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11779  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11780  */
11781 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11782 {
11783         struct drm_crtc_state *crtc_state;
11784         struct intel_crtc *intel_crtc;
11785         struct drm_crtc *crtc;
11786         struct intel_crtc_state *first_crtc_state = NULL;
11787         struct intel_crtc_state *other_crtc_state = NULL;
11788         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11789         int i;
11790
11791         /* look at all crtc's that are going to be enabled in during modeset */
11792         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11793                 intel_crtc = to_intel_crtc(crtc);
11794
11795                 if (!crtc_state->active || !needs_modeset(crtc_state))
11796                         continue;
11797
11798                 if (first_crtc_state) {
11799                         other_crtc_state = to_intel_crtc_state(crtc_state);
11800                         break;
11801                 } else {
11802                         first_crtc_state = to_intel_crtc_state(crtc_state);
11803                         first_pipe = intel_crtc->pipe;
11804                 }
11805         }
11806
11807         /* No workaround needed? */
11808         if (!first_crtc_state)
11809                 return 0;
11810
11811         /* w/a possibly needed, check how many crtc's are already enabled. */
11812         for_each_intel_crtc(state->dev, intel_crtc) {
11813                 struct intel_crtc_state *pipe_config;
11814
11815                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11816                 if (IS_ERR(pipe_config))
11817                         return PTR_ERR(pipe_config);
11818
11819                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11820
11821                 if (!pipe_config->base.active ||
11822                     needs_modeset(&pipe_config->base))
11823                         continue;
11824
11825                 /* 2 or more enabled crtcs means no need for w/a */
11826                 if (enabled_pipe != INVALID_PIPE)
11827                         return 0;
11828
11829                 enabled_pipe = intel_crtc->pipe;
11830         }
11831
11832         if (enabled_pipe != INVALID_PIPE)
11833                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11834         else if (other_crtc_state)
11835                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11836
11837         return 0;
11838 }
11839
11840 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11841 {
11842         struct drm_crtc *crtc;
11843
11844         /* Add all pipes to the state */
11845         for_each_crtc(state->dev, crtc) {
11846                 struct drm_crtc_state *crtc_state;
11847
11848                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11849                 if (IS_ERR(crtc_state))
11850                         return PTR_ERR(crtc_state);
11851         }
11852
11853         return 0;
11854 }
11855
11856 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11857 {
11858         struct drm_crtc *crtc;
11859
11860         /*
11861          * Add all pipes to the state, and force
11862          * a modeset on all the active ones.
11863          */
11864         for_each_crtc(state->dev, crtc) {
11865                 struct drm_crtc_state *crtc_state;
11866                 int ret;
11867
11868                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11869                 if (IS_ERR(crtc_state))
11870                         return PTR_ERR(crtc_state);
11871
11872                 if (!crtc_state->active || needs_modeset(crtc_state))
11873                         continue;
11874
11875                 crtc_state->mode_changed = true;
11876
11877                 ret = drm_atomic_add_affected_connectors(state, crtc);
11878                 if (ret)
11879                         return ret;
11880
11881                 ret = drm_atomic_add_affected_planes(state, crtc);
11882                 if (ret)
11883                         return ret;
11884         }
11885
11886         return 0;
11887 }
11888
11889 static int intel_modeset_checks(struct drm_atomic_state *state)
11890 {
11891         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11892         struct drm_i915_private *dev_priv = to_i915(state->dev);
11893         struct drm_crtc *crtc;
11894         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11895         int ret = 0, i;
11896
11897         if (!check_digital_port_conflicts(state)) {
11898                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11899                 return -EINVAL;
11900         }
11901
11902         intel_state->modeset = true;
11903         intel_state->active_crtcs = dev_priv->active_crtcs;
11904         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11905         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11906
11907         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11908                 if (new_crtc_state->active)
11909                         intel_state->active_crtcs |= 1 << i;
11910                 else
11911                         intel_state->active_crtcs &= ~(1 << i);
11912
11913                 if (old_crtc_state->active != new_crtc_state->active)
11914                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11915         }
11916
11917         /*
11918          * See if the config requires any additional preparation, e.g.
11919          * to adjust global state with pipes off.  We need to do this
11920          * here so we can get the modeset_pipe updated config for the new
11921          * mode set on this crtc.  For other crtcs we need to use the
11922          * adjusted_mode bits in the crtc directly.
11923          */
11924         if (dev_priv->display.modeset_calc_cdclk) {
11925                 ret = dev_priv->display.modeset_calc_cdclk(state);
11926                 if (ret < 0)
11927                         return ret;
11928
11929                 /*
11930                  * Writes to dev_priv->cdclk.logical must protected by
11931                  * holding all the crtc locks, even if we don't end up
11932                  * touching the hardware
11933                  */
11934                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
11935                                         &intel_state->cdclk.logical)) {
11936                         ret = intel_lock_all_pipes(state);
11937                         if (ret < 0)
11938                                 return ret;
11939                 }
11940
11941                 /* All pipes must be switched off while we change the cdclk. */
11942                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
11943                                               &intel_state->cdclk.actual)) {
11944                         ret = intel_modeset_all_pipes(state);
11945                         if (ret < 0)
11946                                 return ret;
11947                 }
11948
11949                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
11950                               intel_state->cdclk.logical.cdclk,
11951                               intel_state->cdclk.actual.cdclk);
11952                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
11953                               intel_state->cdclk.logical.voltage_level,
11954                               intel_state->cdclk.actual.voltage_level);
11955         } else {
11956                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
11957         }
11958
11959         intel_modeset_clear_plls(state);
11960
11961         if (IS_HASWELL(dev_priv))
11962                 return haswell_mode_set_planes_workaround(state);
11963
11964         return 0;
11965 }
11966
11967 /*
11968  * Handle calculation of various watermark data at the end of the atomic check
11969  * phase.  The code here should be run after the per-crtc and per-plane 'check'
11970  * handlers to ensure that all derived state has been updated.
11971  */
11972 static int calc_watermark_data(struct drm_atomic_state *state)
11973 {
11974         struct drm_device *dev = state->dev;
11975         struct drm_i915_private *dev_priv = to_i915(dev);
11976
11977         /* Is there platform-specific watermark information to calculate? */
11978         if (dev_priv->display.compute_global_watermarks)
11979                 return dev_priv->display.compute_global_watermarks(state);
11980
11981         return 0;
11982 }
11983
11984 /**
11985  * intel_atomic_check - validate state object
11986  * @dev: drm device
11987  * @state: state to validate
11988  */
11989 static int intel_atomic_check(struct drm_device *dev,
11990                               struct drm_atomic_state *state)
11991 {
11992         struct drm_i915_private *dev_priv = to_i915(dev);
11993         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11994         struct drm_crtc *crtc;
11995         struct drm_crtc_state *old_crtc_state, *crtc_state;
11996         int ret, i;
11997         bool any_ms = false;
11998
11999         ret = drm_atomic_helper_check_modeset(dev, state);
12000         if (ret)
12001                 return ret;
12002
12003         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12004                 struct intel_crtc_state *pipe_config =
12005                         to_intel_crtc_state(crtc_state);
12006
12007                 /* Catch I915_MODE_FLAG_INHERITED */
12008                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12009                         crtc_state->mode_changed = true;
12010
12011                 if (!needs_modeset(crtc_state))
12012                         continue;
12013
12014                 if (!crtc_state->enable) {
12015                         any_ms = true;
12016                         continue;
12017                 }
12018
12019                 /* FIXME: For only active_changed we shouldn't need to do any
12020                  * state recomputation at all. */
12021
12022                 ret = drm_atomic_add_affected_connectors(state, crtc);
12023                 if (ret)
12024                         return ret;
12025
12026                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12027                 if (ret) {
12028                         intel_dump_pipe_config(to_intel_crtc(crtc),
12029                                                pipe_config, "[failed]");
12030                         return ret;
12031                 }
12032
12033                 if (i915_modparams.fastboot &&
12034                     intel_pipe_config_compare(dev_priv,
12035                                         to_intel_crtc_state(old_crtc_state),
12036                                         pipe_config, true)) {
12037                         crtc_state->mode_changed = false;
12038                         pipe_config->update_pipe = true;
12039                 }
12040
12041                 if (needs_modeset(crtc_state))
12042                         any_ms = true;
12043
12044                 ret = drm_atomic_add_affected_planes(state, crtc);
12045                 if (ret)
12046                         return ret;
12047
12048                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12049                                        needs_modeset(crtc_state) ?
12050                                        "[modeset]" : "[fastset]");
12051         }
12052
12053         if (any_ms) {
12054                 ret = intel_modeset_checks(state);
12055
12056                 if (ret)
12057                         return ret;
12058         } else {
12059                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12060         }
12061
12062         ret = drm_atomic_helper_check_planes(dev, state);
12063         if (ret)
12064                 return ret;
12065
12066         intel_fbc_choose_crtc(dev_priv, state);
12067         return calc_watermark_data(state);
12068 }
12069
12070 static int intel_atomic_prepare_commit(struct drm_device *dev,
12071                                        struct drm_atomic_state *state)
12072 {
12073         return drm_atomic_helper_prepare_planes(dev, state);
12074 }
12075
12076 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12077 {
12078         struct drm_device *dev = crtc->base.dev;
12079
12080         if (!dev->max_vblank_count)
12081                 return drm_crtc_accurate_vblank_count(&crtc->base);
12082
12083         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12084 }
12085
12086 static void intel_update_crtc(struct drm_crtc *crtc,
12087                               struct drm_atomic_state *state,
12088                               struct drm_crtc_state *old_crtc_state,
12089                               struct drm_crtc_state *new_crtc_state)
12090 {
12091         struct drm_device *dev = crtc->dev;
12092         struct drm_i915_private *dev_priv = to_i915(dev);
12093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12094         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12095         bool modeset = needs_modeset(new_crtc_state);
12096
12097         if (modeset) {
12098                 update_scanline_offset(intel_crtc);
12099                 dev_priv->display.crtc_enable(pipe_config, state);
12100         } else {
12101                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12102                                        pipe_config);
12103         }
12104
12105         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12106                 intel_fbc_enable(
12107                     intel_crtc, pipe_config,
12108                     to_intel_plane_state(crtc->primary->state));
12109         }
12110
12111         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12112 }
12113
12114 static void intel_update_crtcs(struct drm_atomic_state *state)
12115 {
12116         struct drm_crtc *crtc;
12117         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12118         int i;
12119
12120         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12121                 if (!new_crtc_state->active)
12122                         continue;
12123
12124                 intel_update_crtc(crtc, state, old_crtc_state,
12125                                   new_crtc_state);
12126         }
12127 }
12128
12129 static void skl_update_crtcs(struct drm_atomic_state *state)
12130 {
12131         struct drm_i915_private *dev_priv = to_i915(state->dev);
12132         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12133         struct drm_crtc *crtc;
12134         struct intel_crtc *intel_crtc;
12135         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12136         struct intel_crtc_state *cstate;
12137         unsigned int updated = 0;
12138         bool progress;
12139         enum pipe pipe;
12140         int i;
12141
12142         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12143
12144         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12145                 /* ignore allocations for crtc's that have been turned off. */
12146                 if (new_crtc_state->active)
12147                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12148
12149         /*
12150          * Whenever the number of active pipes changes, we need to make sure we
12151          * update the pipes in the right order so that their ddb allocations
12152          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12153          * cause pipe underruns and other bad stuff.
12154          */
12155         do {
12156                 progress = false;
12157
12158                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12159                         bool vbl_wait = false;
12160                         unsigned int cmask = drm_crtc_mask(crtc);
12161
12162                         intel_crtc = to_intel_crtc(crtc);
12163                         cstate = to_intel_crtc_state(new_crtc_state);
12164                         pipe = intel_crtc->pipe;
12165
12166                         if (updated & cmask || !cstate->base.active)
12167                                 continue;
12168
12169                         if (skl_ddb_allocation_overlaps(dev_priv,
12170                                                         entries,
12171                                                         &cstate->wm.skl.ddb,
12172                                                         i))
12173                                 continue;
12174
12175                         updated |= cmask;
12176                         entries[i] = &cstate->wm.skl.ddb;
12177
12178                         /*
12179                          * If this is an already active pipe, it's DDB changed,
12180                          * and this isn't the last pipe that needs updating
12181                          * then we need to wait for a vblank to pass for the
12182                          * new ddb allocation to take effect.
12183                          */
12184                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12185                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12186                             !new_crtc_state->active_changed &&
12187                             intel_state->wm_results.dirty_pipes != updated)
12188                                 vbl_wait = true;
12189
12190                         intel_update_crtc(crtc, state, old_crtc_state,
12191                                           new_crtc_state);
12192
12193                         if (vbl_wait)
12194                                 intel_wait_for_vblank(dev_priv, pipe);
12195
12196                         progress = true;
12197                 }
12198         } while (progress);
12199 }
12200
12201 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12202 {
12203         struct intel_atomic_state *state, *next;
12204         struct llist_node *freed;
12205
12206         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12207         llist_for_each_entry_safe(state, next, freed, freed)
12208                 drm_atomic_state_put(&state->base);
12209 }
12210
12211 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12212 {
12213         struct drm_i915_private *dev_priv =
12214                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12215
12216         intel_atomic_helper_free_state(dev_priv);
12217 }
12218
12219 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12220 {
12221         struct wait_queue_entry wait_fence, wait_reset;
12222         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12223
12224         init_wait_entry(&wait_fence, 0);
12225         init_wait_entry(&wait_reset, 0);
12226         for (;;) {
12227                 prepare_to_wait(&intel_state->commit_ready.wait,
12228                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12229                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12230                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12231
12232
12233                 if (i915_sw_fence_done(&intel_state->commit_ready)
12234                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12235                         break;
12236
12237                 schedule();
12238         }
12239         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12240         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12241 }
12242
12243 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12244 {
12245         struct drm_device *dev = state->dev;
12246         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12247         struct drm_i915_private *dev_priv = to_i915(dev);
12248         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12249         struct drm_crtc *crtc;
12250         struct intel_crtc_state *intel_cstate;
12251         u64 put_domains[I915_MAX_PIPES] = {};
12252         int i;
12253
12254         intel_atomic_commit_fence_wait(intel_state);
12255
12256         drm_atomic_helper_wait_for_dependencies(state);
12257
12258         if (intel_state->modeset)
12259                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12260
12261         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12262                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12263
12264                 if (needs_modeset(new_crtc_state) ||
12265                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12266
12267                         put_domains[to_intel_crtc(crtc)->pipe] =
12268                                 modeset_get_crtc_power_domains(crtc,
12269                                         to_intel_crtc_state(new_crtc_state));
12270                 }
12271
12272                 if (!needs_modeset(new_crtc_state))
12273                         continue;
12274
12275                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12276                                        to_intel_crtc_state(new_crtc_state));
12277
12278                 if (old_crtc_state->active) {
12279                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12280                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12281                         intel_crtc->active = false;
12282                         intel_fbc_disable(intel_crtc);
12283                         intel_disable_shared_dpll(intel_crtc);
12284
12285                         /*
12286                          * Underruns don't always raise
12287                          * interrupts, so check manually.
12288                          */
12289                         intel_check_cpu_fifo_underruns(dev_priv);
12290                         intel_check_pch_fifo_underruns(dev_priv);
12291
12292                         if (!new_crtc_state->active) {
12293                                 /*
12294                                  * Make sure we don't call initial_watermarks
12295                                  * for ILK-style watermark updates.
12296                                  *
12297                                  * No clue what this is supposed to achieve.
12298                                  */
12299                                 if (INTEL_GEN(dev_priv) >= 9)
12300                                         dev_priv->display.initial_watermarks(intel_state,
12301                                                                              to_intel_crtc_state(new_crtc_state));
12302                         }
12303                 }
12304         }
12305
12306         /* Only after disabling all output pipelines that will be changed can we
12307          * update the the output configuration. */
12308         intel_modeset_update_crtc_state(state);
12309
12310         if (intel_state->modeset) {
12311                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12312
12313                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12314
12315                 /*
12316                  * SKL workaround: bspec recommends we disable the SAGV when we
12317                  * have more then one pipe enabled
12318                  */
12319                 if (!intel_can_enable_sagv(state))
12320                         intel_disable_sagv(dev_priv);
12321
12322                 intel_modeset_verify_disabled(dev, state);
12323         }
12324
12325         /* Complete the events for pipes that have now been disabled */
12326         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12327                 bool modeset = needs_modeset(new_crtc_state);
12328
12329                 /* Complete events for now disable pipes here. */
12330                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12331                         spin_lock_irq(&dev->event_lock);
12332                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12333                         spin_unlock_irq(&dev->event_lock);
12334
12335                         new_crtc_state->event = NULL;
12336                 }
12337         }
12338
12339         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12340         dev_priv->display.update_crtcs(state);
12341
12342         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12343          * already, but still need the state for the delayed optimization. To
12344          * fix this:
12345          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12346          * - schedule that vblank worker _before_ calling hw_done
12347          * - at the start of commit_tail, cancel it _synchrously
12348          * - switch over to the vblank wait helper in the core after that since
12349          *   we don't need out special handling any more.
12350          */
12351         drm_atomic_helper_wait_for_flip_done(dev, state);
12352
12353         /*
12354          * Now that the vblank has passed, we can go ahead and program the
12355          * optimal watermarks on platforms that need two-step watermark
12356          * programming.
12357          *
12358          * TODO: Move this (and other cleanup) to an async worker eventually.
12359          */
12360         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12361                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12362
12363                 if (dev_priv->display.optimize_watermarks)
12364                         dev_priv->display.optimize_watermarks(intel_state,
12365                                                               intel_cstate);
12366         }
12367
12368         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12369                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12370
12371                 if (put_domains[i])
12372                         modeset_put_power_domains(dev_priv, put_domains[i]);
12373
12374                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12375         }
12376
12377         if (intel_state->modeset && intel_can_enable_sagv(state))
12378                 intel_enable_sagv(dev_priv);
12379
12380         drm_atomic_helper_commit_hw_done(state);
12381
12382         if (intel_state->modeset) {
12383                 /* As one of the primary mmio accessors, KMS has a high
12384                  * likelihood of triggering bugs in unclaimed access. After we
12385                  * finish modesetting, see if an error has been flagged, and if
12386                  * so enable debugging for the next modeset - and hope we catch
12387                  * the culprit.
12388                  */
12389                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12390                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12391         }
12392
12393         drm_atomic_helper_cleanup_planes(dev, state);
12394
12395         drm_atomic_helper_commit_cleanup_done(state);
12396
12397         drm_atomic_state_put(state);
12398
12399         intel_atomic_helper_free_state(dev_priv);
12400 }
12401
12402 static void intel_atomic_commit_work(struct work_struct *work)
12403 {
12404         struct drm_atomic_state *state =
12405                 container_of(work, struct drm_atomic_state, commit_work);
12406
12407         intel_atomic_commit_tail(state);
12408 }
12409
12410 static int __i915_sw_fence_call
12411 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12412                           enum i915_sw_fence_notify notify)
12413 {
12414         struct intel_atomic_state *state =
12415                 container_of(fence, struct intel_atomic_state, commit_ready);
12416
12417         switch (notify) {
12418         case FENCE_COMPLETE:
12419                 /* we do blocking waits in the worker, nothing to do here */
12420                 break;
12421         case FENCE_FREE:
12422                 {
12423                         struct intel_atomic_helper *helper =
12424                                 &to_i915(state->base.dev)->atomic_helper;
12425
12426                         if (llist_add(&state->freed, &helper->free_list))
12427                                 schedule_work(&helper->free_work);
12428                         break;
12429                 }
12430         }
12431
12432         return NOTIFY_DONE;
12433 }
12434
12435 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12436 {
12437         struct drm_plane_state *old_plane_state, *new_plane_state;
12438         struct drm_plane *plane;
12439         int i;
12440
12441         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12442                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12443                                   intel_fb_obj(new_plane_state->fb),
12444                                   to_intel_plane(plane)->frontbuffer_bit);
12445 }
12446
12447 /**
12448  * intel_atomic_commit - commit validated state object
12449  * @dev: DRM device
12450  * @state: the top-level driver state object
12451  * @nonblock: nonblocking commit
12452  *
12453  * This function commits a top-level state object that has been validated
12454  * with drm_atomic_helper_check().
12455  *
12456  * RETURNS
12457  * Zero for success or -errno.
12458  */
12459 static int intel_atomic_commit(struct drm_device *dev,
12460                                struct drm_atomic_state *state,
12461                                bool nonblock)
12462 {
12463         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12464         struct drm_i915_private *dev_priv = to_i915(dev);
12465         int ret = 0;
12466
12467         drm_atomic_state_get(state);
12468         i915_sw_fence_init(&intel_state->commit_ready,
12469                            intel_atomic_commit_ready);
12470
12471         /*
12472          * The intel_legacy_cursor_update() fast path takes care
12473          * of avoiding the vblank waits for simple cursor
12474          * movement and flips. For cursor on/off and size changes,
12475          * we want to perform the vblank waits so that watermark
12476          * updates happen during the correct frames. Gen9+ have
12477          * double buffered watermarks and so shouldn't need this.
12478          *
12479          * Unset state->legacy_cursor_update before the call to
12480          * drm_atomic_helper_setup_commit() because otherwise
12481          * drm_atomic_helper_wait_for_flip_done() is a noop and
12482          * we get FIFO underruns because we didn't wait
12483          * for vblank.
12484          *
12485          * FIXME doing watermarks and fb cleanup from a vblank worker
12486          * (assuming we had any) would solve these problems.
12487          */
12488         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12489                 struct intel_crtc_state *new_crtc_state;
12490                 struct intel_crtc *crtc;
12491                 int i;
12492
12493                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12494                         if (new_crtc_state->wm.need_postvbl_update ||
12495                             new_crtc_state->update_wm_post)
12496                                 state->legacy_cursor_update = false;
12497         }
12498
12499         ret = intel_atomic_prepare_commit(dev, state);
12500         if (ret) {
12501                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12502                 i915_sw_fence_commit(&intel_state->commit_ready);
12503                 return ret;
12504         }
12505
12506         ret = drm_atomic_helper_setup_commit(state, nonblock);
12507         if (!ret)
12508                 ret = drm_atomic_helper_swap_state(state, true);
12509
12510         if (ret) {
12511                 i915_sw_fence_commit(&intel_state->commit_ready);
12512
12513                 drm_atomic_helper_cleanup_planes(dev, state);
12514                 return ret;
12515         }
12516         dev_priv->wm.distrust_bios_wm = false;
12517         intel_shared_dpll_swap_state(state);
12518         intel_atomic_track_fbs(state);
12519
12520         if (intel_state->modeset) {
12521                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12522                        sizeof(intel_state->min_cdclk));
12523                 memcpy(dev_priv->min_voltage_level,
12524                        intel_state->min_voltage_level,
12525                        sizeof(intel_state->min_voltage_level));
12526                 dev_priv->active_crtcs = intel_state->active_crtcs;
12527                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12528                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12529         }
12530
12531         drm_atomic_state_get(state);
12532         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12533
12534         i915_sw_fence_commit(&intel_state->commit_ready);
12535         if (nonblock)
12536                 queue_work(system_unbound_wq, &state->commit_work);
12537         else
12538                 intel_atomic_commit_tail(state);
12539
12540
12541         return 0;
12542 }
12543
12544 static const struct drm_crtc_funcs intel_crtc_funcs = {
12545         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12546         .set_config = drm_atomic_helper_set_config,
12547         .destroy = intel_crtc_destroy,
12548         .page_flip = drm_atomic_helper_page_flip,
12549         .atomic_duplicate_state = intel_crtc_duplicate_state,
12550         .atomic_destroy_state = intel_crtc_destroy_state,
12551         .set_crc_source = intel_crtc_set_crc_source,
12552 };
12553
12554 struct wait_rps_boost {
12555         struct wait_queue_entry wait;
12556
12557         struct drm_crtc *crtc;
12558         struct drm_i915_gem_request *request;
12559 };
12560
12561 static int do_rps_boost(struct wait_queue_entry *_wait,
12562                         unsigned mode, int sync, void *key)
12563 {
12564         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12565         struct drm_i915_gem_request *rq = wait->request;
12566
12567         gen6_rps_boost(rq, NULL);
12568         i915_gem_request_put(rq);
12569
12570         drm_crtc_vblank_put(wait->crtc);
12571
12572         list_del(&wait->wait.entry);
12573         kfree(wait);
12574         return 1;
12575 }
12576
12577 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12578                                        struct dma_fence *fence)
12579 {
12580         struct wait_rps_boost *wait;
12581
12582         if (!dma_fence_is_i915(fence))
12583                 return;
12584
12585         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12586                 return;
12587
12588         if (drm_crtc_vblank_get(crtc))
12589                 return;
12590
12591         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12592         if (!wait) {
12593                 drm_crtc_vblank_put(crtc);
12594                 return;
12595         }
12596
12597         wait->request = to_request(dma_fence_get(fence));
12598         wait->crtc = crtc;
12599
12600         wait->wait.func = do_rps_boost;
12601         wait->wait.flags = 0;
12602
12603         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12604 }
12605
12606 /**
12607  * intel_prepare_plane_fb - Prepare fb for usage on plane
12608  * @plane: drm plane to prepare for
12609  * @fb: framebuffer to prepare for presentation
12610  *
12611  * Prepares a framebuffer for usage on a display plane.  Generally this
12612  * involves pinning the underlying object and updating the frontbuffer tracking
12613  * bits.  Some older platforms need special physical address handling for
12614  * cursor planes.
12615  *
12616  * Must be called with struct_mutex held.
12617  *
12618  * Returns 0 on success, negative error code on failure.
12619  */
12620 int
12621 intel_prepare_plane_fb(struct drm_plane *plane,
12622                        struct drm_plane_state *new_state)
12623 {
12624         struct intel_atomic_state *intel_state =
12625                 to_intel_atomic_state(new_state->state);
12626         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12627         struct drm_framebuffer *fb = new_state->fb;
12628         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12629         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12630         int ret;
12631
12632         if (old_obj) {
12633                 struct drm_crtc_state *crtc_state =
12634                         drm_atomic_get_existing_crtc_state(new_state->state,
12635                                                            plane->state->crtc);
12636
12637                 /* Big Hammer, we also need to ensure that any pending
12638                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12639                  * current scanout is retired before unpinning the old
12640                  * framebuffer. Note that we rely on userspace rendering
12641                  * into the buffer attached to the pipe they are waiting
12642                  * on. If not, userspace generates a GPU hang with IPEHR
12643                  * point to the MI_WAIT_FOR_EVENT.
12644                  *
12645                  * This should only fail upon a hung GPU, in which case we
12646                  * can safely continue.
12647                  */
12648                 if (needs_modeset(crtc_state)) {
12649                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12650                                                               old_obj->resv, NULL,
12651                                                               false, 0,
12652                                                               GFP_KERNEL);
12653                         if (ret < 0)
12654                                 return ret;
12655                 }
12656         }
12657
12658         if (new_state->fence) { /* explicit fencing */
12659                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12660                                                     new_state->fence,
12661                                                     I915_FENCE_TIMEOUT,
12662                                                     GFP_KERNEL);
12663                 if (ret < 0)
12664                         return ret;
12665         }
12666
12667         if (!obj)
12668                 return 0;
12669
12670         ret = i915_gem_object_pin_pages(obj);
12671         if (ret)
12672                 return ret;
12673
12674         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12675         if (ret) {
12676                 i915_gem_object_unpin_pages(obj);
12677                 return ret;
12678         }
12679
12680         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12681             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12682                 const int align = intel_cursor_alignment(dev_priv);
12683
12684                 ret = i915_gem_object_attach_phys(obj, align);
12685         } else {
12686                 struct i915_vma *vma;
12687
12688                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12689                 if (!IS_ERR(vma))
12690                         to_intel_plane_state(new_state)->vma = vma;
12691                 else
12692                         ret =  PTR_ERR(vma);
12693         }
12694
12695         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12696
12697         mutex_unlock(&dev_priv->drm.struct_mutex);
12698         i915_gem_object_unpin_pages(obj);
12699         if (ret)
12700                 return ret;
12701
12702         if (!new_state->fence) { /* implicit fencing */
12703                 struct dma_fence *fence;
12704
12705                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12706                                                       obj->resv, NULL,
12707                                                       false, I915_FENCE_TIMEOUT,
12708                                                       GFP_KERNEL);
12709                 if (ret < 0)
12710                         return ret;
12711
12712                 fence = reservation_object_get_excl_rcu(obj->resv);
12713                 if (fence) {
12714                         add_rps_boost_after_vblank(new_state->crtc, fence);
12715                         dma_fence_put(fence);
12716                 }
12717         } else {
12718                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12719         }
12720
12721         return 0;
12722 }
12723
12724 /**
12725  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12726  * @plane: drm plane to clean up for
12727  * @fb: old framebuffer that was on plane
12728  *
12729  * Cleans up a framebuffer that has just been removed from a plane.
12730  *
12731  * Must be called with struct_mutex held.
12732  */
12733 void
12734 intel_cleanup_plane_fb(struct drm_plane *plane,
12735                        struct drm_plane_state *old_state)
12736 {
12737         struct i915_vma *vma;
12738
12739         /* Should only be called after a successful intel_prepare_plane_fb()! */
12740         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12741         if (vma) {
12742                 mutex_lock(&plane->dev->struct_mutex);
12743                 intel_unpin_fb_vma(vma);
12744                 mutex_unlock(&plane->dev->struct_mutex);
12745         }
12746 }
12747
12748 int
12749 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12750 {
12751         struct drm_i915_private *dev_priv;
12752         int max_scale;
12753         int crtc_clock, max_dotclk;
12754
12755         if (!intel_crtc || !crtc_state->base.enable)
12756                 return DRM_PLANE_HELPER_NO_SCALING;
12757
12758         dev_priv = to_i915(intel_crtc->base.dev);
12759
12760         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12761         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12762
12763         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12764                 max_dotclk *= 2;
12765
12766         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12767                 return DRM_PLANE_HELPER_NO_SCALING;
12768
12769         /*
12770          * skl max scale is lower of:
12771          *    close to 3 but not 3, -1 is for that purpose
12772          *            or
12773          *    cdclk/crtc_clock
12774          */
12775         max_scale = min((1 << 16) * 3 - 1,
12776                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12777
12778         return max_scale;
12779 }
12780
12781 static int
12782 intel_check_primary_plane(struct intel_plane *plane,
12783                           struct intel_crtc_state *crtc_state,
12784                           struct intel_plane_state *state)
12785 {
12786         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12787         struct drm_crtc *crtc = state->base.crtc;
12788         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12789         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12790         bool can_position = false;
12791         int ret;
12792
12793         if (INTEL_GEN(dev_priv) >= 9) {
12794                 /* use scaler when colorkey is not required */
12795                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12796                         min_scale = 1;
12797                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12798                 }
12799                 can_position = true;
12800         }
12801
12802         ret = drm_plane_helper_check_state(&state->base,
12803                                            &state->clip,
12804                                            min_scale, max_scale,
12805                                            can_position, true);
12806         if (ret)
12807                 return ret;
12808
12809         if (!state->base.fb)
12810                 return 0;
12811
12812         if (INTEL_GEN(dev_priv) >= 9) {
12813                 ret = skl_check_plane_surface(state);
12814                 if (ret)
12815                         return ret;
12816
12817                 state->ctl = skl_plane_ctl(crtc_state, state);
12818         } else {
12819                 ret = i9xx_check_plane_surface(state);
12820                 if (ret)
12821                         return ret;
12822
12823                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12824         }
12825
12826         return 0;
12827 }
12828
12829 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12830                                     struct drm_crtc_state *old_crtc_state)
12831 {
12832         struct drm_device *dev = crtc->dev;
12833         struct drm_i915_private *dev_priv = to_i915(dev);
12834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12835         struct intel_crtc_state *old_intel_cstate =
12836                 to_intel_crtc_state(old_crtc_state);
12837         struct intel_atomic_state *old_intel_state =
12838                 to_intel_atomic_state(old_crtc_state->state);
12839         struct intel_crtc_state *intel_cstate =
12840                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12841         bool modeset = needs_modeset(&intel_cstate->base);
12842
12843         if (!modeset &&
12844             (intel_cstate->base.color_mgmt_changed ||
12845              intel_cstate->update_pipe)) {
12846                 intel_color_set_csc(&intel_cstate->base);
12847                 intel_color_load_luts(&intel_cstate->base);
12848         }
12849
12850         /* Perform vblank evasion around commit operation */
12851         intel_pipe_update_start(intel_cstate);
12852
12853         if (modeset)
12854                 goto out;
12855
12856         if (intel_cstate->update_pipe)
12857                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12858         else if (INTEL_GEN(dev_priv) >= 9)
12859                 skl_detach_scalers(intel_crtc);
12860
12861 out:
12862         if (dev_priv->display.atomic_update_watermarks)
12863                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12864                                                            intel_cstate);
12865 }
12866
12867 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12868                                      struct drm_crtc_state *old_crtc_state)
12869 {
12870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12871         struct intel_atomic_state *old_intel_state =
12872                 to_intel_atomic_state(old_crtc_state->state);
12873         struct intel_crtc_state *new_crtc_state =
12874                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12875
12876         intel_pipe_update_end(new_crtc_state);
12877 }
12878
12879 /**
12880  * intel_plane_destroy - destroy a plane
12881  * @plane: plane to destroy
12882  *
12883  * Common destruction function for all types of planes (primary, cursor,
12884  * sprite).
12885  */
12886 void intel_plane_destroy(struct drm_plane *plane)
12887 {
12888         drm_plane_cleanup(plane);
12889         kfree(to_intel_plane(plane));
12890 }
12891
12892 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
12893 {
12894         switch (format) {
12895         case DRM_FORMAT_C8:
12896         case DRM_FORMAT_RGB565:
12897         case DRM_FORMAT_XRGB1555:
12898         case DRM_FORMAT_XRGB8888:
12899                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12900                         modifier == I915_FORMAT_MOD_X_TILED;
12901         default:
12902                 return false;
12903         }
12904 }
12905
12906 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
12907 {
12908         switch (format) {
12909         case DRM_FORMAT_C8:
12910         case DRM_FORMAT_RGB565:
12911         case DRM_FORMAT_XRGB8888:
12912         case DRM_FORMAT_XBGR8888:
12913         case DRM_FORMAT_XRGB2101010:
12914         case DRM_FORMAT_XBGR2101010:
12915                 return modifier == DRM_FORMAT_MOD_LINEAR ||
12916                         modifier == I915_FORMAT_MOD_X_TILED;
12917         default:
12918                 return false;
12919         }
12920 }
12921
12922 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
12923 {
12924         switch (format) {
12925         case DRM_FORMAT_XRGB8888:
12926         case DRM_FORMAT_XBGR8888:
12927         case DRM_FORMAT_ARGB8888:
12928         case DRM_FORMAT_ABGR8888:
12929                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
12930                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
12931                         return true;
12932                 /* fall through */
12933         case DRM_FORMAT_RGB565:
12934         case DRM_FORMAT_XRGB2101010:
12935         case DRM_FORMAT_XBGR2101010:
12936         case DRM_FORMAT_YUYV:
12937         case DRM_FORMAT_YVYU:
12938         case DRM_FORMAT_UYVY:
12939         case DRM_FORMAT_VYUY:
12940                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
12941                         return true;
12942                 /* fall through */
12943         case DRM_FORMAT_C8:
12944                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
12945                     modifier == I915_FORMAT_MOD_X_TILED ||
12946                     modifier == I915_FORMAT_MOD_Y_TILED)
12947                         return true;
12948                 /* fall through */
12949         default:
12950                 return false;
12951         }
12952 }
12953
12954 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
12955                                                      uint32_t format,
12956                                                      uint64_t modifier)
12957 {
12958         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12959
12960         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12961                 return false;
12962
12963         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
12964             modifier != DRM_FORMAT_MOD_LINEAR)
12965                 return false;
12966
12967         if (INTEL_GEN(dev_priv) >= 9)
12968                 return skl_mod_supported(format, modifier);
12969         else if (INTEL_GEN(dev_priv) >= 4)
12970                 return i965_mod_supported(format, modifier);
12971         else
12972                 return i8xx_mod_supported(format, modifier);
12973
12974         unreachable();
12975 }
12976
12977 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
12978                                                     uint32_t format,
12979                                                     uint64_t modifier)
12980 {
12981         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
12982                 return false;
12983
12984         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
12985 }
12986
12987 static struct drm_plane_funcs intel_plane_funcs = {
12988         .update_plane = drm_atomic_helper_update_plane,
12989         .disable_plane = drm_atomic_helper_disable_plane,
12990         .destroy = intel_plane_destroy,
12991         .atomic_get_property = intel_plane_atomic_get_property,
12992         .atomic_set_property = intel_plane_atomic_set_property,
12993         .atomic_duplicate_state = intel_plane_duplicate_state,
12994         .atomic_destroy_state = intel_plane_destroy_state,
12995         .format_mod_supported = intel_primary_plane_format_mod_supported,
12996 };
12997
12998 static int
12999 intel_legacy_cursor_update(struct drm_plane *plane,
13000                            struct drm_crtc *crtc,
13001                            struct drm_framebuffer *fb,
13002                            int crtc_x, int crtc_y,
13003                            unsigned int crtc_w, unsigned int crtc_h,
13004                            uint32_t src_x, uint32_t src_y,
13005                            uint32_t src_w, uint32_t src_h,
13006                            struct drm_modeset_acquire_ctx *ctx)
13007 {
13008         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13009         int ret;
13010         struct drm_plane_state *old_plane_state, *new_plane_state;
13011         struct intel_plane *intel_plane = to_intel_plane(plane);
13012         struct drm_framebuffer *old_fb;
13013         struct drm_crtc_state *crtc_state = crtc->state;
13014         struct i915_vma *old_vma, *vma;
13015
13016         /*
13017          * When crtc is inactive or there is a modeset pending,
13018          * wait for it to complete in the slowpath
13019          */
13020         if (!crtc_state->active || needs_modeset(crtc_state) ||
13021             to_intel_crtc_state(crtc_state)->update_pipe)
13022                 goto slow;
13023
13024         old_plane_state = plane->state;
13025         /*
13026          * Don't do an async update if there is an outstanding commit modifying
13027          * the plane.  This prevents our async update's changes from getting
13028          * overridden by a previous synchronous update's state.
13029          */
13030         if (old_plane_state->commit &&
13031             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13032                 goto slow;
13033
13034         /*
13035          * If any parameters change that may affect watermarks,
13036          * take the slowpath. Only changing fb or position should be
13037          * in the fastpath.
13038          */
13039         if (old_plane_state->crtc != crtc ||
13040             old_plane_state->src_w != src_w ||
13041             old_plane_state->src_h != src_h ||
13042             old_plane_state->crtc_w != crtc_w ||
13043             old_plane_state->crtc_h != crtc_h ||
13044             !old_plane_state->fb != !fb)
13045                 goto slow;
13046
13047         new_plane_state = intel_plane_duplicate_state(plane);
13048         if (!new_plane_state)
13049                 return -ENOMEM;
13050
13051         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13052
13053         new_plane_state->src_x = src_x;
13054         new_plane_state->src_y = src_y;
13055         new_plane_state->src_w = src_w;
13056         new_plane_state->src_h = src_h;
13057         new_plane_state->crtc_x = crtc_x;
13058         new_plane_state->crtc_y = crtc_y;
13059         new_plane_state->crtc_w = crtc_w;
13060         new_plane_state->crtc_h = crtc_h;
13061
13062         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13063                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13064                                                   to_intel_plane_state(plane->state),
13065                                                   to_intel_plane_state(new_plane_state));
13066         if (ret)
13067                 goto out_free;
13068
13069         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13070         if (ret)
13071                 goto out_free;
13072
13073         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13074                 int align = intel_cursor_alignment(dev_priv);
13075
13076                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13077                 if (ret) {
13078                         DRM_DEBUG_KMS("failed to attach phys object\n");
13079                         goto out_unlock;
13080                 }
13081         } else {
13082                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13083                 if (IS_ERR(vma)) {
13084                         DRM_DEBUG_KMS("failed to pin object\n");
13085
13086                         ret = PTR_ERR(vma);
13087                         goto out_unlock;
13088                 }
13089
13090                 to_intel_plane_state(new_plane_state)->vma = vma;
13091         }
13092
13093         old_fb = old_plane_state->fb;
13094
13095         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13096                           intel_plane->frontbuffer_bit);
13097
13098         /* Swap plane state */
13099         plane->state = new_plane_state;
13100
13101         if (plane->state->visible) {
13102                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13103                 intel_plane->update_plane(intel_plane,
13104                                           to_intel_crtc_state(crtc->state),
13105                                           to_intel_plane_state(plane->state));
13106         } else {
13107                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13108                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13109         }
13110
13111         old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
13112         if (old_vma)
13113                 intel_unpin_fb_vma(old_vma);
13114
13115 out_unlock:
13116         mutex_unlock(&dev_priv->drm.struct_mutex);
13117 out_free:
13118         if (ret)
13119                 intel_plane_destroy_state(plane, new_plane_state);
13120         else
13121                 intel_plane_destroy_state(plane, old_plane_state);
13122         return ret;
13123
13124 slow:
13125         return drm_atomic_helper_update_plane(plane, crtc, fb,
13126                                               crtc_x, crtc_y, crtc_w, crtc_h,
13127                                               src_x, src_y, src_w, src_h, ctx);
13128 }
13129
13130 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13131         .update_plane = intel_legacy_cursor_update,
13132         .disable_plane = drm_atomic_helper_disable_plane,
13133         .destroy = intel_plane_destroy,
13134         .atomic_get_property = intel_plane_atomic_get_property,
13135         .atomic_set_property = intel_plane_atomic_set_property,
13136         .atomic_duplicate_state = intel_plane_duplicate_state,
13137         .atomic_destroy_state = intel_plane_destroy_state,
13138         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13139 };
13140
13141 static struct intel_plane *
13142 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13143 {
13144         struct intel_plane *primary = NULL;
13145         struct intel_plane_state *state = NULL;
13146         const uint32_t *intel_primary_formats;
13147         unsigned int supported_rotations;
13148         unsigned int num_formats;
13149         const uint64_t *modifiers;
13150         int ret;
13151
13152         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13153         if (!primary) {
13154                 ret = -ENOMEM;
13155                 goto fail;
13156         }
13157
13158         state = intel_create_plane_state(&primary->base);
13159         if (!state) {
13160                 ret = -ENOMEM;
13161                 goto fail;
13162         }
13163
13164         primary->base.state = &state->base;
13165
13166         primary->can_scale = false;
13167         primary->max_downscale = 1;
13168         if (INTEL_GEN(dev_priv) >= 9) {
13169                 primary->can_scale = true;
13170                 state->scaler_id = -1;
13171         }
13172         primary->pipe = pipe;
13173         /*
13174          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13175          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13176          */
13177         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13178                 primary->plane = (enum plane) !pipe;
13179         else
13180                 primary->plane = (enum plane) pipe;
13181         primary->id = PLANE_PRIMARY;
13182         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13183         primary->check_plane = intel_check_primary_plane;
13184
13185         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13186                 intel_primary_formats = skl_primary_formats;
13187                 num_formats = ARRAY_SIZE(skl_primary_formats);
13188                 modifiers = skl_format_modifiers_ccs;
13189
13190                 primary->update_plane = skl_update_plane;
13191                 primary->disable_plane = skl_disable_plane;
13192         } else if (INTEL_GEN(dev_priv) >= 9) {
13193                 intel_primary_formats = skl_primary_formats;
13194                 num_formats = ARRAY_SIZE(skl_primary_formats);
13195                 if (pipe < PIPE_C)
13196                         modifiers = skl_format_modifiers_ccs;
13197                 else
13198                         modifiers = skl_format_modifiers_noccs;
13199
13200                 primary->update_plane = skl_update_plane;
13201                 primary->disable_plane = skl_disable_plane;
13202         } else if (INTEL_GEN(dev_priv) >= 4) {
13203                 intel_primary_formats = i965_primary_formats;
13204                 num_formats = ARRAY_SIZE(i965_primary_formats);
13205                 modifiers = i9xx_format_modifiers;
13206
13207                 primary->update_plane = i9xx_update_primary_plane;
13208                 primary->disable_plane = i9xx_disable_primary_plane;
13209         } else {
13210                 intel_primary_formats = i8xx_primary_formats;
13211                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13212                 modifiers = i9xx_format_modifiers;
13213
13214                 primary->update_plane = i9xx_update_primary_plane;
13215                 primary->disable_plane = i9xx_disable_primary_plane;
13216         }
13217
13218         if (INTEL_GEN(dev_priv) >= 9)
13219                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13220                                                0, &intel_plane_funcs,
13221                                                intel_primary_formats, num_formats,
13222                                                modifiers,
13223                                                DRM_PLANE_TYPE_PRIMARY,
13224                                                "plane 1%c", pipe_name(pipe));
13225         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13226                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13227                                                0, &intel_plane_funcs,
13228                                                intel_primary_formats, num_formats,
13229                                                modifiers,
13230                                                DRM_PLANE_TYPE_PRIMARY,
13231                                                "primary %c", pipe_name(pipe));
13232         else
13233                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13234                                                0, &intel_plane_funcs,
13235                                                intel_primary_formats, num_formats,
13236                                                modifiers,
13237                                                DRM_PLANE_TYPE_PRIMARY,
13238                                                "plane %c", plane_name(primary->plane));
13239         if (ret)
13240                 goto fail;
13241
13242         if (INTEL_GEN(dev_priv) >= 9) {
13243                 supported_rotations =
13244                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13245                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13246         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13247                 supported_rotations =
13248                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13249                         DRM_MODE_REFLECT_X;
13250         } else if (INTEL_GEN(dev_priv) >= 4) {
13251                 supported_rotations =
13252                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13253         } else {
13254                 supported_rotations = DRM_MODE_ROTATE_0;
13255         }
13256
13257         if (INTEL_GEN(dev_priv) >= 4)
13258                 drm_plane_create_rotation_property(&primary->base,
13259                                                    DRM_MODE_ROTATE_0,
13260                                                    supported_rotations);
13261
13262         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13263
13264         return primary;
13265
13266 fail:
13267         kfree(state);
13268         kfree(primary);
13269
13270         return ERR_PTR(ret);
13271 }
13272
13273 static struct intel_plane *
13274 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13275                           enum pipe pipe)
13276 {
13277         struct intel_plane *cursor = NULL;
13278         struct intel_plane_state *state = NULL;
13279         int ret;
13280
13281         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13282         if (!cursor) {
13283                 ret = -ENOMEM;
13284                 goto fail;
13285         }
13286
13287         state = intel_create_plane_state(&cursor->base);
13288         if (!state) {
13289                 ret = -ENOMEM;
13290                 goto fail;
13291         }
13292
13293         cursor->base.state = &state->base;
13294
13295         cursor->can_scale = false;
13296         cursor->max_downscale = 1;
13297         cursor->pipe = pipe;
13298         cursor->plane = pipe;
13299         cursor->id = PLANE_CURSOR;
13300         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13301
13302         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13303                 cursor->update_plane = i845_update_cursor;
13304                 cursor->disable_plane = i845_disable_cursor;
13305                 cursor->check_plane = i845_check_cursor;
13306         } else {
13307                 cursor->update_plane = i9xx_update_cursor;
13308                 cursor->disable_plane = i9xx_disable_cursor;
13309                 cursor->check_plane = i9xx_check_cursor;
13310         }
13311
13312         cursor->cursor.base = ~0;
13313         cursor->cursor.cntl = ~0;
13314
13315         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13316                 cursor->cursor.size = ~0;
13317
13318         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13319                                        0, &intel_cursor_plane_funcs,
13320                                        intel_cursor_formats,
13321                                        ARRAY_SIZE(intel_cursor_formats),
13322                                        cursor_format_modifiers,
13323                                        DRM_PLANE_TYPE_CURSOR,
13324                                        "cursor %c", pipe_name(pipe));
13325         if (ret)
13326                 goto fail;
13327
13328         if (INTEL_GEN(dev_priv) >= 4)
13329                 drm_plane_create_rotation_property(&cursor->base,
13330                                                    DRM_MODE_ROTATE_0,
13331                                                    DRM_MODE_ROTATE_0 |
13332                                                    DRM_MODE_ROTATE_180);
13333
13334         if (INTEL_GEN(dev_priv) >= 9)
13335                 state->scaler_id = -1;
13336
13337         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13338
13339         return cursor;
13340
13341 fail:
13342         kfree(state);
13343         kfree(cursor);
13344
13345         return ERR_PTR(ret);
13346 }
13347
13348 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13349                                     struct intel_crtc_state *crtc_state)
13350 {
13351         struct intel_crtc_scaler_state *scaler_state =
13352                 &crtc_state->scaler_state;
13353         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13354         int i;
13355
13356         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13357         if (!crtc->num_scalers)
13358                 return;
13359
13360         for (i = 0; i < crtc->num_scalers; i++) {
13361                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13362
13363                 scaler->in_use = 0;
13364                 scaler->mode = PS_SCALER_MODE_DYN;
13365         }
13366
13367         scaler_state->scaler_id = -1;
13368 }
13369
13370 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13371 {
13372         struct intel_crtc *intel_crtc;
13373         struct intel_crtc_state *crtc_state = NULL;
13374         struct intel_plane *primary = NULL;
13375         struct intel_plane *cursor = NULL;
13376         int sprite, ret;
13377
13378         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13379         if (!intel_crtc)
13380                 return -ENOMEM;
13381
13382         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13383         if (!crtc_state) {
13384                 ret = -ENOMEM;
13385                 goto fail;
13386         }
13387         intel_crtc->config = crtc_state;
13388         intel_crtc->base.state = &crtc_state->base;
13389         crtc_state->base.crtc = &intel_crtc->base;
13390
13391         primary = intel_primary_plane_create(dev_priv, pipe);
13392         if (IS_ERR(primary)) {
13393                 ret = PTR_ERR(primary);
13394                 goto fail;
13395         }
13396         intel_crtc->plane_ids_mask |= BIT(primary->id);
13397
13398         for_each_sprite(dev_priv, pipe, sprite) {
13399                 struct intel_plane *plane;
13400
13401                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13402                 if (IS_ERR(plane)) {
13403                         ret = PTR_ERR(plane);
13404                         goto fail;
13405                 }
13406                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13407         }
13408
13409         cursor = intel_cursor_plane_create(dev_priv, pipe);
13410         if (IS_ERR(cursor)) {
13411                 ret = PTR_ERR(cursor);
13412                 goto fail;
13413         }
13414         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13415
13416         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13417                                         &primary->base, &cursor->base,
13418                                         &intel_crtc_funcs,
13419                                         "pipe %c", pipe_name(pipe));
13420         if (ret)
13421                 goto fail;
13422
13423         intel_crtc->pipe = pipe;
13424         intel_crtc->plane = primary->plane;
13425
13426         /* initialize shared scalers */
13427         intel_crtc_init_scalers(intel_crtc, crtc_state);
13428
13429         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13430                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13431         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13432         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13433
13434         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13435
13436         intel_color_init(&intel_crtc->base);
13437
13438         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13439
13440         return 0;
13441
13442 fail:
13443         /*
13444          * drm_mode_config_cleanup() will free up any
13445          * crtcs/planes already initialized.
13446          */
13447         kfree(crtc_state);
13448         kfree(intel_crtc);
13449
13450         return ret;
13451 }
13452
13453 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13454 {
13455         struct drm_device *dev = connector->base.dev;
13456
13457         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13458
13459         if (!connector->base.state->crtc)
13460                 return INVALID_PIPE;
13461
13462         return to_intel_crtc(connector->base.state->crtc)->pipe;
13463 }
13464
13465 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13466                                 struct drm_file *file)
13467 {
13468         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13469         struct drm_crtc *drmmode_crtc;
13470         struct intel_crtc *crtc;
13471
13472         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13473         if (!drmmode_crtc)
13474                 return -ENOENT;
13475
13476         crtc = to_intel_crtc(drmmode_crtc);
13477         pipe_from_crtc_id->pipe = crtc->pipe;
13478
13479         return 0;
13480 }
13481
13482 static int intel_encoder_clones(struct intel_encoder *encoder)
13483 {
13484         struct drm_device *dev = encoder->base.dev;
13485         struct intel_encoder *source_encoder;
13486         int index_mask = 0;
13487         int entry = 0;
13488
13489         for_each_intel_encoder(dev, source_encoder) {
13490                 if (encoders_cloneable(encoder, source_encoder))
13491                         index_mask |= (1 << entry);
13492
13493                 entry++;
13494         }
13495
13496         return index_mask;
13497 }
13498
13499 static bool has_edp_a(struct drm_i915_private *dev_priv)
13500 {
13501         if (!IS_MOBILE(dev_priv))
13502                 return false;
13503
13504         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13505                 return false;
13506
13507         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13508                 return false;
13509
13510         return true;
13511 }
13512
13513 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13514 {
13515         if (INTEL_GEN(dev_priv) >= 9)
13516                 return false;
13517
13518         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13519                 return false;
13520
13521         if (IS_CHERRYVIEW(dev_priv))
13522                 return false;
13523
13524         if (HAS_PCH_LPT_H(dev_priv) &&
13525             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13526                 return false;
13527
13528         /* DDI E can't be used if DDI A requires 4 lanes */
13529         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13530                 return false;
13531
13532         if (!dev_priv->vbt.int_crt_support)
13533                 return false;
13534
13535         return true;
13536 }
13537
13538 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13539 {
13540         int pps_num;
13541         int pps_idx;
13542
13543         if (HAS_DDI(dev_priv))
13544                 return;
13545         /*
13546          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13547          * everywhere where registers can be write protected.
13548          */
13549         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13550                 pps_num = 2;
13551         else
13552                 pps_num = 1;
13553
13554         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13555                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13556
13557                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13558                 I915_WRITE(PP_CONTROL(pps_idx), val);
13559         }
13560 }
13561
13562 static void intel_pps_init(struct drm_i915_private *dev_priv)
13563 {
13564         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13565                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13566         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13567                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13568         else
13569                 dev_priv->pps_mmio_base = PPS_BASE;
13570
13571         intel_pps_unlock_regs_wa(dev_priv);
13572 }
13573
13574 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13575 {
13576         struct intel_encoder *encoder;
13577         bool dpd_is_edp = false;
13578
13579         intel_pps_init(dev_priv);
13580
13581         /*
13582          * intel_edp_init_connector() depends on this completing first, to
13583          * prevent the registeration of both eDP and LVDS and the incorrect
13584          * sharing of the PPS.
13585          */
13586         intel_lvds_init(dev_priv);
13587
13588         if (intel_crt_present(dev_priv))
13589                 intel_crt_init(dev_priv);
13590
13591         if (IS_GEN9_LP(dev_priv)) {
13592                 /*
13593                  * FIXME: Broxton doesn't support port detection via the
13594                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13595                  * detect the ports.
13596                  */
13597                 intel_ddi_init(dev_priv, PORT_A);
13598                 intel_ddi_init(dev_priv, PORT_B);
13599                 intel_ddi_init(dev_priv, PORT_C);
13600
13601                 intel_dsi_init(dev_priv);
13602         } else if (HAS_DDI(dev_priv)) {
13603                 int found;
13604
13605                 /*
13606                  * Haswell uses DDI functions to detect digital outputs.
13607                  * On SKL pre-D0 the strap isn't connected, so we assume
13608                  * it's there.
13609                  */
13610                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13611                 /* WaIgnoreDDIAStrap: skl */
13612                 if (found || IS_GEN9_BC(dev_priv))
13613                         intel_ddi_init(dev_priv, PORT_A);
13614
13615                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13616                  * register */
13617                 found = I915_READ(SFUSE_STRAP);
13618
13619                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13620                         intel_ddi_init(dev_priv, PORT_B);
13621                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13622                         intel_ddi_init(dev_priv, PORT_C);
13623                 if (found & SFUSE_STRAP_DDID_DETECTED)
13624                         intel_ddi_init(dev_priv, PORT_D);
13625                 /*
13626                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13627                  */
13628                 if (IS_GEN9_BC(dev_priv) &&
13629                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13630                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13631                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13632                         intel_ddi_init(dev_priv, PORT_E);
13633
13634         } else if (HAS_PCH_SPLIT(dev_priv)) {
13635                 int found;
13636                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13637
13638                 if (has_edp_a(dev_priv))
13639                         intel_dp_init(dev_priv, DP_A, PORT_A);
13640
13641                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13642                         /* PCH SDVOB multiplex with HDMIB */
13643                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13644                         if (!found)
13645                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13646                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13647                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13648                 }
13649
13650                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13651                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13652
13653                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13654                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13655
13656                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13657                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13658
13659                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13660                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13661         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13662                 bool has_edp, has_port;
13663
13664                 /*
13665                  * The DP_DETECTED bit is the latched state of the DDC
13666                  * SDA pin at boot. However since eDP doesn't require DDC
13667                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13668                  * eDP ports may have been muxed to an alternate function.
13669                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13670                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13671                  * detect eDP ports.
13672                  *
13673                  * Sadly the straps seem to be missing sometimes even for HDMI
13674                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13675                  * and VBT for the presence of the port. Additionally we can't
13676                  * trust the port type the VBT declares as we've seen at least
13677                  * HDMI ports that the VBT claim are DP or eDP.
13678                  */
13679                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13680                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13681                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13682                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13683                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13684                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13685
13686                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13687                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13688                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13689                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13690                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13691                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13692
13693                 if (IS_CHERRYVIEW(dev_priv)) {
13694                         /*
13695                          * eDP not supported on port D,
13696                          * so no need to worry about it
13697                          */
13698                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13699                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13700                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13701                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13702                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13703                 }
13704
13705                 intel_dsi_init(dev_priv);
13706         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13707                 bool found = false;
13708
13709                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13710                         DRM_DEBUG_KMS("probing SDVOB\n");
13711                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13712                         if (!found && IS_G4X(dev_priv)) {
13713                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13714                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13715                         }
13716
13717                         if (!found && IS_G4X(dev_priv))
13718                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13719                 }
13720
13721                 /* Before G4X SDVOC doesn't have its own detect register */
13722
13723                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13724                         DRM_DEBUG_KMS("probing SDVOC\n");
13725                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13726                 }
13727
13728                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13729
13730                         if (IS_G4X(dev_priv)) {
13731                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13732                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13733                         }
13734                         if (IS_G4X(dev_priv))
13735                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13736                 }
13737
13738                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13739                         intel_dp_init(dev_priv, DP_D, PORT_D);
13740         } else if (IS_GEN2(dev_priv))
13741                 intel_dvo_init(dev_priv);
13742
13743         if (SUPPORTS_TV(dev_priv))
13744                 intel_tv_init(dev_priv);
13745
13746         intel_psr_init(dev_priv);
13747
13748         for_each_intel_encoder(&dev_priv->drm, encoder) {
13749                 encoder->base.possible_crtcs = encoder->crtc_mask;
13750                 encoder->base.possible_clones =
13751                         intel_encoder_clones(encoder);
13752         }
13753
13754         intel_init_pch_refclk(dev_priv);
13755
13756         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13757 }
13758
13759 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13760 {
13761         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13762
13763         drm_framebuffer_cleanup(fb);
13764
13765         i915_gem_object_lock(intel_fb->obj);
13766         WARN_ON(!intel_fb->obj->framebuffer_references--);
13767         i915_gem_object_unlock(intel_fb->obj);
13768
13769         i915_gem_object_put(intel_fb->obj);
13770
13771         kfree(intel_fb);
13772 }
13773
13774 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13775                                                 struct drm_file *file,
13776                                                 unsigned int *handle)
13777 {
13778         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13779         struct drm_i915_gem_object *obj = intel_fb->obj;
13780
13781         if (obj->userptr.mm) {
13782                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13783                 return -EINVAL;
13784         }
13785
13786         return drm_gem_handle_create(file, &obj->base, handle);
13787 }
13788
13789 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13790                                         struct drm_file *file,
13791                                         unsigned flags, unsigned color,
13792                                         struct drm_clip_rect *clips,
13793                                         unsigned num_clips)
13794 {
13795         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13796
13797         i915_gem_object_flush_if_display(obj);
13798         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13799
13800         return 0;
13801 }
13802
13803 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13804         .destroy = intel_user_framebuffer_destroy,
13805         .create_handle = intel_user_framebuffer_create_handle,
13806         .dirty = intel_user_framebuffer_dirty,
13807 };
13808
13809 static
13810 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13811                          uint64_t fb_modifier, uint32_t pixel_format)
13812 {
13813         u32 gen = INTEL_GEN(dev_priv);
13814
13815         if (gen >= 9) {
13816                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13817
13818                 /* "The stride in bytes must not exceed the of the size of 8K
13819                  *  pixels and 32K bytes."
13820                  */
13821                 return min(8192 * cpp, 32768);
13822         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13823                 return 32*1024;
13824         } else if (gen >= 4) {
13825                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13826                         return 16*1024;
13827                 else
13828                         return 32*1024;
13829         } else if (gen >= 3) {
13830                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13831                         return 8*1024;
13832                 else
13833                         return 16*1024;
13834         } else {
13835                 /* XXX DSPC is limited to 4k tiled */
13836                 return 8*1024;
13837         }
13838 }
13839
13840 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13841                                   struct drm_i915_gem_object *obj,
13842                                   struct drm_mode_fb_cmd2 *mode_cmd)
13843 {
13844         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13845         struct drm_framebuffer *fb = &intel_fb->base;
13846         struct drm_format_name_buf format_name;
13847         u32 pitch_limit;
13848         unsigned int tiling, stride;
13849         int ret = -EINVAL;
13850         int i;
13851
13852         i915_gem_object_lock(obj);
13853         obj->framebuffer_references++;
13854         tiling = i915_gem_object_get_tiling(obj);
13855         stride = i915_gem_object_get_stride(obj);
13856         i915_gem_object_unlock(obj);
13857
13858         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13859                 /*
13860                  * If there's a fence, enforce that
13861                  * the fb modifier and tiling mode match.
13862                  */
13863                 if (tiling != I915_TILING_NONE &&
13864                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13865                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13866                         goto err;
13867                 }
13868         } else {
13869                 if (tiling == I915_TILING_X) {
13870                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13871                 } else if (tiling == I915_TILING_Y) {
13872                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13873                         goto err;
13874                 }
13875         }
13876
13877         /* Passed in modifier sanity checking. */
13878         switch (mode_cmd->modifier[0]) {
13879         case I915_FORMAT_MOD_Y_TILED_CCS:
13880         case I915_FORMAT_MOD_Yf_TILED_CCS:
13881                 switch (mode_cmd->pixel_format) {
13882                 case DRM_FORMAT_XBGR8888:
13883                 case DRM_FORMAT_ABGR8888:
13884                 case DRM_FORMAT_XRGB8888:
13885                 case DRM_FORMAT_ARGB8888:
13886                         break;
13887                 default:
13888                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13889                         goto err;
13890                 }
13891                 /* fall through */
13892         case I915_FORMAT_MOD_Y_TILED:
13893         case I915_FORMAT_MOD_Yf_TILED:
13894                 if (INTEL_GEN(dev_priv) < 9) {
13895                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
13896                                       mode_cmd->modifier[0]);
13897                         goto err;
13898                 }
13899         case DRM_FORMAT_MOD_LINEAR:
13900         case I915_FORMAT_MOD_X_TILED:
13901                 break;
13902         default:
13903                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
13904                               mode_cmd->modifier[0]);
13905                 goto err;
13906         }
13907
13908         /*
13909          * gen2/3 display engine uses the fence if present,
13910          * so the tiling mode must match the fb modifier exactly.
13911          */
13912         if (INTEL_INFO(dev_priv)->gen < 4 &&
13913             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13914                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
13915                 goto err;
13916         }
13917
13918         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
13919                                            mode_cmd->pixel_format);
13920         if (mode_cmd->pitches[0] > pitch_limit) {
13921                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
13922                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
13923                               "tiled" : "linear",
13924                               mode_cmd->pitches[0], pitch_limit);
13925                 goto err;
13926         }
13927
13928         /*
13929          * If there's a fence, enforce that
13930          * the fb pitch and fence stride match.
13931          */
13932         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
13933                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
13934                               mode_cmd->pitches[0], stride);
13935                 goto err;
13936         }
13937
13938         /* Reject formats not supported by any plane early. */
13939         switch (mode_cmd->pixel_format) {
13940         case DRM_FORMAT_C8:
13941         case DRM_FORMAT_RGB565:
13942         case DRM_FORMAT_XRGB8888:
13943         case DRM_FORMAT_ARGB8888:
13944                 break;
13945         case DRM_FORMAT_XRGB1555:
13946                 if (INTEL_GEN(dev_priv) > 3) {
13947                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13948                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13949                         goto err;
13950                 }
13951                 break;
13952         case DRM_FORMAT_ABGR8888:
13953                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
13954                     INTEL_GEN(dev_priv) < 9) {
13955                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13956                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13957                         goto err;
13958                 }
13959                 break;
13960         case DRM_FORMAT_XBGR8888:
13961         case DRM_FORMAT_XRGB2101010:
13962         case DRM_FORMAT_XBGR2101010:
13963                 if (INTEL_GEN(dev_priv) < 4) {
13964                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13965                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13966                         goto err;
13967                 }
13968                 break;
13969         case DRM_FORMAT_ABGR2101010:
13970                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
13971                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13972                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13973                         goto err;
13974                 }
13975                 break;
13976         case DRM_FORMAT_YUYV:
13977         case DRM_FORMAT_UYVY:
13978         case DRM_FORMAT_YVYU:
13979         case DRM_FORMAT_VYUY:
13980                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
13981                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13982                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
13983                         goto err;
13984                 }
13985                 break;
13986         default:
13987                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
13988                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
13989                 goto err;
13990         }
13991
13992         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13993         if (mode_cmd->offsets[0] != 0)
13994                 goto err;
13995
13996         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
13997
13998         for (i = 0; i < fb->format->num_planes; i++) {
13999                 u32 stride_alignment;
14000
14001                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14002                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14003                         goto err;
14004                 }
14005
14006                 stride_alignment = intel_fb_stride_alignment(fb, i);
14007
14008                 /*
14009                  * Display WA #0531: skl,bxt,kbl,glk
14010                  *
14011                  * Render decompression and plane width > 3840
14012                  * combined with horizontal panning requires the
14013                  * plane stride to be a multiple of 4. We'll just
14014                  * require the entire fb to accommodate that to avoid
14015                  * potential runtime errors at plane configuration time.
14016                  */
14017                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14018                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14019                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14020                         stride_alignment *= 4;
14021
14022                 if (fb->pitches[i] & (stride_alignment - 1)) {
14023                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14024                                       i, fb->pitches[i], stride_alignment);
14025                         goto err;
14026                 }
14027         }
14028
14029         intel_fb->obj = obj;
14030
14031         ret = intel_fill_fb_info(dev_priv, fb);
14032         if (ret)
14033                 goto err;
14034
14035         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14036         if (ret) {
14037                 DRM_ERROR("framebuffer init failed %d\n", ret);
14038                 goto err;
14039         }
14040
14041         return 0;
14042
14043 err:
14044         i915_gem_object_lock(obj);
14045         obj->framebuffer_references--;
14046         i915_gem_object_unlock(obj);
14047         return ret;
14048 }
14049
14050 static struct drm_framebuffer *
14051 intel_user_framebuffer_create(struct drm_device *dev,
14052                               struct drm_file *filp,
14053                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14054 {
14055         struct drm_framebuffer *fb;
14056         struct drm_i915_gem_object *obj;
14057         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14058
14059         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14060         if (!obj)
14061                 return ERR_PTR(-ENOENT);
14062
14063         fb = intel_framebuffer_create(obj, &mode_cmd);
14064         if (IS_ERR(fb))
14065                 i915_gem_object_put(obj);
14066
14067         return fb;
14068 }
14069
14070 static void intel_atomic_state_free(struct drm_atomic_state *state)
14071 {
14072         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14073
14074         drm_atomic_state_default_release(state);
14075
14076         i915_sw_fence_fini(&intel_state->commit_ready);
14077
14078         kfree(state);
14079 }
14080
14081 static const struct drm_mode_config_funcs intel_mode_funcs = {
14082         .fb_create = intel_user_framebuffer_create,
14083         .get_format_info = intel_get_format_info,
14084         .output_poll_changed = intel_fbdev_output_poll_changed,
14085         .atomic_check = intel_atomic_check,
14086         .atomic_commit = intel_atomic_commit,
14087         .atomic_state_alloc = intel_atomic_state_alloc,
14088         .atomic_state_clear = intel_atomic_state_clear,
14089         .atomic_state_free = intel_atomic_state_free,
14090 };
14091
14092 /**
14093  * intel_init_display_hooks - initialize the display modesetting hooks
14094  * @dev_priv: device private
14095  */
14096 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14097 {
14098         intel_init_cdclk_hooks(dev_priv);
14099
14100         if (INTEL_INFO(dev_priv)->gen >= 9) {
14101                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14102                 dev_priv->display.get_initial_plane_config =
14103                         skylake_get_initial_plane_config;
14104                 dev_priv->display.crtc_compute_clock =
14105                         haswell_crtc_compute_clock;
14106                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14107                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14108         } else if (HAS_DDI(dev_priv)) {
14109                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14110                 dev_priv->display.get_initial_plane_config =
14111                         ironlake_get_initial_plane_config;
14112                 dev_priv->display.crtc_compute_clock =
14113                         haswell_crtc_compute_clock;
14114                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14115                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14116         } else if (HAS_PCH_SPLIT(dev_priv)) {
14117                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14118                 dev_priv->display.get_initial_plane_config =
14119                         ironlake_get_initial_plane_config;
14120                 dev_priv->display.crtc_compute_clock =
14121                         ironlake_crtc_compute_clock;
14122                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14123                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14124         } else if (IS_CHERRYVIEW(dev_priv)) {
14125                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14126                 dev_priv->display.get_initial_plane_config =
14127                         i9xx_get_initial_plane_config;
14128                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14129                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14130                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14131         } else if (IS_VALLEYVIEW(dev_priv)) {
14132                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14133                 dev_priv->display.get_initial_plane_config =
14134                         i9xx_get_initial_plane_config;
14135                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14136                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14137                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14138         } else if (IS_G4X(dev_priv)) {
14139                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14140                 dev_priv->display.get_initial_plane_config =
14141                         i9xx_get_initial_plane_config;
14142                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14143                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14144                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14145         } else if (IS_PINEVIEW(dev_priv)) {
14146                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14147                 dev_priv->display.get_initial_plane_config =
14148                         i9xx_get_initial_plane_config;
14149                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14150                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14151                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14152         } else if (!IS_GEN2(dev_priv)) {
14153                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14154                 dev_priv->display.get_initial_plane_config =
14155                         i9xx_get_initial_plane_config;
14156                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14157                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14158                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14159         } else {
14160                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14161                 dev_priv->display.get_initial_plane_config =
14162                         i9xx_get_initial_plane_config;
14163                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14164                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14165                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14166         }
14167
14168         if (IS_GEN5(dev_priv)) {
14169                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14170         } else if (IS_GEN6(dev_priv)) {
14171                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14172         } else if (IS_IVYBRIDGE(dev_priv)) {
14173                 /* FIXME: detect B0+ stepping and use auto training */
14174                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14175         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14176                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14177         }
14178
14179         if (INTEL_GEN(dev_priv) >= 9)
14180                 dev_priv->display.update_crtcs = skl_update_crtcs;
14181         else
14182                 dev_priv->display.update_crtcs = intel_update_crtcs;
14183 }
14184
14185 /*
14186  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14187  */
14188 static void quirk_ssc_force_disable(struct drm_device *dev)
14189 {
14190         struct drm_i915_private *dev_priv = to_i915(dev);
14191         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14192         DRM_INFO("applying lvds SSC disable quirk\n");
14193 }
14194
14195 /*
14196  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14197  * brightness value
14198  */
14199 static void quirk_invert_brightness(struct drm_device *dev)
14200 {
14201         struct drm_i915_private *dev_priv = to_i915(dev);
14202         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14203         DRM_INFO("applying inverted panel brightness quirk\n");
14204 }
14205
14206 /* Some VBT's incorrectly indicate no backlight is present */
14207 static void quirk_backlight_present(struct drm_device *dev)
14208 {
14209         struct drm_i915_private *dev_priv = to_i915(dev);
14210         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14211         DRM_INFO("applying backlight present quirk\n");
14212 }
14213
14214 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14215  * which is 300 ms greater than eDP spec T12 min.
14216  */
14217 static void quirk_increase_t12_delay(struct drm_device *dev)
14218 {
14219         struct drm_i915_private *dev_priv = to_i915(dev);
14220
14221         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14222         DRM_INFO("Applying T12 delay quirk\n");
14223 }
14224
14225 struct intel_quirk {
14226         int device;
14227         int subsystem_vendor;
14228         int subsystem_device;
14229         void (*hook)(struct drm_device *dev);
14230 };
14231
14232 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14233 struct intel_dmi_quirk {
14234         void (*hook)(struct drm_device *dev);
14235         const struct dmi_system_id (*dmi_id_list)[];
14236 };
14237
14238 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14239 {
14240         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14241         return 1;
14242 }
14243
14244 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14245         {
14246                 .dmi_id_list = &(const struct dmi_system_id[]) {
14247                         {
14248                                 .callback = intel_dmi_reverse_brightness,
14249                                 .ident = "NCR Corporation",
14250                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14251                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14252                                 },
14253                         },
14254                         { }  /* terminating entry */
14255                 },
14256                 .hook = quirk_invert_brightness,
14257         },
14258 };
14259
14260 static struct intel_quirk intel_quirks[] = {
14261         /* Lenovo U160 cannot use SSC on LVDS */
14262         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14263
14264         /* Sony Vaio Y cannot use SSC on LVDS */
14265         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14266
14267         /* Acer Aspire 5734Z must invert backlight brightness */
14268         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14269
14270         /* Acer/eMachines G725 */
14271         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14272
14273         /* Acer/eMachines e725 */
14274         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14275
14276         /* Acer/Packard Bell NCL20 */
14277         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14278
14279         /* Acer Aspire 4736Z */
14280         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14281
14282         /* Acer Aspire 5336 */
14283         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14284
14285         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14286         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14287
14288         /* Acer C720 Chromebook (Core i3 4005U) */
14289         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14290
14291         /* Apple Macbook 2,1 (Core 2 T7400) */
14292         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14293
14294         /* Apple Macbook 4,1 */
14295         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14296
14297         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14298         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14299
14300         /* HP Chromebook 14 (Celeron 2955U) */
14301         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14302
14303         /* Dell Chromebook 11 */
14304         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14305
14306         /* Dell Chromebook 11 (2015 version) */
14307         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14308
14309         /* Toshiba Satellite P50-C-18C */
14310         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14311 };
14312
14313 static void intel_init_quirks(struct drm_device *dev)
14314 {
14315         struct pci_dev *d = dev->pdev;
14316         int i;
14317
14318         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14319                 struct intel_quirk *q = &intel_quirks[i];
14320
14321                 if (d->device == q->device &&
14322                     (d->subsystem_vendor == q->subsystem_vendor ||
14323                      q->subsystem_vendor == PCI_ANY_ID) &&
14324                     (d->subsystem_device == q->subsystem_device ||
14325                      q->subsystem_device == PCI_ANY_ID))
14326                         q->hook(dev);
14327         }
14328         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14329                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14330                         intel_dmi_quirks[i].hook(dev);
14331         }
14332 }
14333
14334 /* Disable the VGA plane that we never use */
14335 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14336 {
14337         struct pci_dev *pdev = dev_priv->drm.pdev;
14338         u8 sr1;
14339         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14340
14341         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14342         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14343         outb(SR01, VGA_SR_INDEX);
14344         sr1 = inb(VGA_SR_DATA);
14345         outb(sr1 | 1<<5, VGA_SR_DATA);
14346         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14347         udelay(300);
14348
14349         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14350         POSTING_READ(vga_reg);
14351 }
14352
14353 void intel_modeset_init_hw(struct drm_device *dev)
14354 {
14355         struct drm_i915_private *dev_priv = to_i915(dev);
14356
14357         intel_update_cdclk(dev_priv);
14358         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14359         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14360 }
14361
14362 /*
14363  * Calculate what we think the watermarks should be for the state we've read
14364  * out of the hardware and then immediately program those watermarks so that
14365  * we ensure the hardware settings match our internal state.
14366  *
14367  * We can calculate what we think WM's should be by creating a duplicate of the
14368  * current state (which was constructed during hardware readout) and running it
14369  * through the atomic check code to calculate new watermark values in the
14370  * state object.
14371  */
14372 static void sanitize_watermarks(struct drm_device *dev)
14373 {
14374         struct drm_i915_private *dev_priv = to_i915(dev);
14375         struct drm_atomic_state *state;
14376         struct intel_atomic_state *intel_state;
14377         struct drm_crtc *crtc;
14378         struct drm_crtc_state *cstate;
14379         struct drm_modeset_acquire_ctx ctx;
14380         int ret;
14381         int i;
14382
14383         /* Only supported on platforms that use atomic watermark design */
14384         if (!dev_priv->display.optimize_watermarks)
14385                 return;
14386
14387         /*
14388          * We need to hold connection_mutex before calling duplicate_state so
14389          * that the connector loop is protected.
14390          */
14391         drm_modeset_acquire_init(&ctx, 0);
14392 retry:
14393         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14394         if (ret == -EDEADLK) {
14395                 drm_modeset_backoff(&ctx);
14396                 goto retry;
14397         } else if (WARN_ON(ret)) {
14398                 goto fail;
14399         }
14400
14401         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14402         if (WARN_ON(IS_ERR(state)))
14403                 goto fail;
14404
14405         intel_state = to_intel_atomic_state(state);
14406
14407         /*
14408          * Hardware readout is the only time we don't want to calculate
14409          * intermediate watermarks (since we don't trust the current
14410          * watermarks).
14411          */
14412         if (!HAS_GMCH_DISPLAY(dev_priv))
14413                 intel_state->skip_intermediate_wm = true;
14414
14415         ret = intel_atomic_check(dev, state);
14416         if (ret) {
14417                 /*
14418                  * If we fail here, it means that the hardware appears to be
14419                  * programmed in a way that shouldn't be possible, given our
14420                  * understanding of watermark requirements.  This might mean a
14421                  * mistake in the hardware readout code or a mistake in the
14422                  * watermark calculations for a given platform.  Raise a WARN
14423                  * so that this is noticeable.
14424                  *
14425                  * If this actually happens, we'll have to just leave the
14426                  * BIOS-programmed watermarks untouched and hope for the best.
14427                  */
14428                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14429                 goto put_state;
14430         }
14431
14432         /* Write calculated watermark values back */
14433         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14434                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14435
14436                 cs->wm.need_postvbl_update = true;
14437                 dev_priv->display.optimize_watermarks(intel_state, cs);
14438
14439                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14440         }
14441
14442 put_state:
14443         drm_atomic_state_put(state);
14444 fail:
14445         drm_modeset_drop_locks(&ctx);
14446         drm_modeset_acquire_fini(&ctx);
14447 }
14448
14449 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14450 {
14451         if (IS_GEN5(dev_priv)) {
14452                 u32 fdi_pll_clk =
14453                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14454
14455                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14456         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14457                 dev_priv->fdi_pll_freq = 270000;
14458         } else {
14459                 return;
14460         }
14461
14462         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14463 }
14464
14465 int intel_modeset_init(struct drm_device *dev)
14466 {
14467         struct drm_i915_private *dev_priv = to_i915(dev);
14468         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14469         enum pipe pipe;
14470         struct intel_crtc *crtc;
14471
14472         drm_mode_config_init(dev);
14473
14474         dev->mode_config.min_width = 0;
14475         dev->mode_config.min_height = 0;
14476
14477         dev->mode_config.preferred_depth = 24;
14478         dev->mode_config.prefer_shadow = 1;
14479
14480         dev->mode_config.allow_fb_modifiers = true;
14481
14482         dev->mode_config.funcs = &intel_mode_funcs;
14483
14484         init_llist_head(&dev_priv->atomic_helper.free_list);
14485         INIT_WORK(&dev_priv->atomic_helper.free_work,
14486                   intel_atomic_helper_free_state_worker);
14487
14488         intel_init_quirks(dev);
14489
14490         intel_init_pm(dev_priv);
14491
14492         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14493                 return 0;
14494
14495         /*
14496          * There may be no VBT; and if the BIOS enabled SSC we can
14497          * just keep using it to avoid unnecessary flicker.  Whereas if the
14498          * BIOS isn't using it, don't assume it will work even if the VBT
14499          * indicates as much.
14500          */
14501         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14502                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14503                                             DREF_SSC1_ENABLE);
14504
14505                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14506                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14507                                      bios_lvds_use_ssc ? "en" : "dis",
14508                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14509                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14510                 }
14511         }
14512
14513         if (IS_GEN2(dev_priv)) {
14514                 dev->mode_config.max_width = 2048;
14515                 dev->mode_config.max_height = 2048;
14516         } else if (IS_GEN3(dev_priv)) {
14517                 dev->mode_config.max_width = 4096;
14518                 dev->mode_config.max_height = 4096;
14519         } else {
14520                 dev->mode_config.max_width = 8192;
14521                 dev->mode_config.max_height = 8192;
14522         }
14523
14524         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14525                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14526                 dev->mode_config.cursor_height = 1023;
14527         } else if (IS_GEN2(dev_priv)) {
14528                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14529                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14530         } else {
14531                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14532                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14533         }
14534
14535         dev->mode_config.fb_base = ggtt->mappable_base;
14536
14537         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14538                       INTEL_INFO(dev_priv)->num_pipes,
14539                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14540
14541         for_each_pipe(dev_priv, pipe) {
14542                 int ret;
14543
14544                 ret = intel_crtc_init(dev_priv, pipe);
14545                 if (ret) {
14546                         drm_mode_config_cleanup(dev);
14547                         return ret;
14548                 }
14549         }
14550
14551         intel_shared_dpll_init(dev);
14552         intel_update_fdi_pll_freq(dev_priv);
14553
14554         intel_update_czclk(dev_priv);
14555         intel_modeset_init_hw(dev);
14556
14557         if (dev_priv->max_cdclk_freq == 0)
14558                 intel_update_max_cdclk(dev_priv);
14559
14560         /* Just disable it once at startup */
14561         i915_disable_vga(dev_priv);
14562         intel_setup_outputs(dev_priv);
14563
14564         drm_modeset_lock_all(dev);
14565         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14566         drm_modeset_unlock_all(dev);
14567
14568         for_each_intel_crtc(dev, crtc) {
14569                 struct intel_initial_plane_config plane_config = {};
14570
14571                 if (!crtc->active)
14572                         continue;
14573
14574                 /*
14575                  * Note that reserving the BIOS fb up front prevents us
14576                  * from stuffing other stolen allocations like the ring
14577                  * on top.  This prevents some ugliness at boot time, and
14578                  * can even allow for smooth boot transitions if the BIOS
14579                  * fb is large enough for the active pipe configuration.
14580                  */
14581                 dev_priv->display.get_initial_plane_config(crtc,
14582                                                            &plane_config);
14583
14584                 /*
14585                  * If the fb is shared between multiple heads, we'll
14586                  * just get the first one.
14587                  */
14588                 intel_find_initial_plane_obj(crtc, &plane_config);
14589         }
14590
14591         /*
14592          * Make sure hardware watermarks really match the state we read out.
14593          * Note that we need to do this after reconstructing the BIOS fb's
14594          * since the watermark calculation done here will use pstate->fb.
14595          */
14596         if (!HAS_GMCH_DISPLAY(dev_priv))
14597                 sanitize_watermarks(dev);
14598
14599         return 0;
14600 }
14601
14602 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14603 {
14604         /* 640x480@60Hz, ~25175 kHz */
14605         struct dpll clock = {
14606                 .m1 = 18,
14607                 .m2 = 7,
14608                 .p1 = 13,
14609                 .p2 = 4,
14610                 .n = 2,
14611         };
14612         u32 dpll, fp;
14613         int i;
14614
14615         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14616
14617         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14618                       pipe_name(pipe), clock.vco, clock.dot);
14619
14620         fp = i9xx_dpll_compute_fp(&clock);
14621         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14622                 DPLL_VGA_MODE_DIS |
14623                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14624                 PLL_P2_DIVIDE_BY_4 |
14625                 PLL_REF_INPUT_DREFCLK |
14626                 DPLL_VCO_ENABLE;
14627
14628         I915_WRITE(FP0(pipe), fp);
14629         I915_WRITE(FP1(pipe), fp);
14630
14631         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14632         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14633         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14634         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14635         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14636         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14637         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14638
14639         /*
14640          * Apparently we need to have VGA mode enabled prior to changing
14641          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14642          * dividers, even though the register value does change.
14643          */
14644         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14645         I915_WRITE(DPLL(pipe), dpll);
14646
14647         /* Wait for the clocks to stabilize. */
14648         POSTING_READ(DPLL(pipe));
14649         udelay(150);
14650
14651         /* The pixel multiplier can only be updated once the
14652          * DPLL is enabled and the clocks are stable.
14653          *
14654          * So write it again.
14655          */
14656         I915_WRITE(DPLL(pipe), dpll);
14657
14658         /* We do this three times for luck */
14659         for (i = 0; i < 3 ; i++) {
14660                 I915_WRITE(DPLL(pipe), dpll);
14661                 POSTING_READ(DPLL(pipe));
14662                 udelay(150); /* wait for warmup */
14663         }
14664
14665         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14666         POSTING_READ(PIPECONF(pipe));
14667 }
14668
14669 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14670 {
14671         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14672                       pipe_name(pipe));
14673
14674         assert_plane_disabled(dev_priv, PLANE_A);
14675         assert_plane_disabled(dev_priv, PLANE_B);
14676
14677         I915_WRITE(PIPECONF(pipe), 0);
14678         POSTING_READ(PIPECONF(pipe));
14679
14680         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14681                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14682
14683         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14684         POSTING_READ(DPLL(pipe));
14685 }
14686
14687 static bool
14688 intel_check_plane_mapping(struct intel_crtc *crtc)
14689 {
14690         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14691         u32 val;
14692
14693         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14694                 return true;
14695
14696         val = I915_READ(DSPCNTR(!crtc->plane));
14697
14698         if ((val & DISPLAY_PLANE_ENABLE) &&
14699             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14700                 return false;
14701
14702         return true;
14703 }
14704
14705 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14706 {
14707         struct drm_device *dev = crtc->base.dev;
14708         struct intel_encoder *encoder;
14709
14710         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14711                 return true;
14712
14713         return false;
14714 }
14715
14716 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14717 {
14718         struct drm_device *dev = encoder->base.dev;
14719         struct intel_connector *connector;
14720
14721         for_each_connector_on_encoder(dev, &encoder->base, connector)
14722                 return connector;
14723
14724         return NULL;
14725 }
14726
14727 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14728                               enum pipe pch_transcoder)
14729 {
14730         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14731                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
14732 }
14733
14734 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14735                                 struct drm_modeset_acquire_ctx *ctx)
14736 {
14737         struct drm_device *dev = crtc->base.dev;
14738         struct drm_i915_private *dev_priv = to_i915(dev);
14739         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14740
14741         /* Clear any frame start delays used for debugging left by the BIOS */
14742         if (!transcoder_is_dsi(cpu_transcoder)) {
14743                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14744
14745                 I915_WRITE(reg,
14746                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14747         }
14748
14749         /* restore vblank interrupts to correct state */
14750         drm_crtc_vblank_reset(&crtc->base);
14751         if (crtc->active) {
14752                 struct intel_plane *plane;
14753
14754                 drm_crtc_vblank_on(&crtc->base);
14755
14756                 /* Disable everything but the primary plane */
14757                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14758                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14759                                 continue;
14760
14761                         trace_intel_disable_plane(&plane->base, crtc);
14762                         plane->disable_plane(plane, crtc);
14763                 }
14764         }
14765
14766         /* We need to sanitize the plane -> pipe mapping first because this will
14767          * disable the crtc (and hence change the state) if it is wrong. Note
14768          * that gen4+ has a fixed plane -> pipe mapping.  */
14769         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14770                 bool plane;
14771
14772                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14773                               crtc->base.base.id, crtc->base.name);
14774
14775                 /* Pipe has the wrong plane attached and the plane is active.
14776                  * Temporarily change the plane mapping and disable everything
14777                  * ...  */
14778                 plane = crtc->plane;
14779                 crtc->base.primary->state->visible = true;
14780                 crtc->plane = !plane;
14781                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14782                 crtc->plane = plane;
14783         }
14784
14785         /* Adjust the state of the output pipe according to whether we
14786          * have active connectors/encoders. */
14787         if (crtc->active && !intel_crtc_has_encoders(crtc))
14788                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14789
14790         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14791                 /*
14792                  * We start out with underrun reporting disabled to avoid races.
14793                  * For correct bookkeeping mark this on active crtcs.
14794                  *
14795                  * Also on gmch platforms we dont have any hardware bits to
14796                  * disable the underrun reporting. Which means we need to start
14797                  * out with underrun reporting disabled also on inactive pipes,
14798                  * since otherwise we'll complain about the garbage we read when
14799                  * e.g. coming up after runtime pm.
14800                  *
14801                  * No protection against concurrent access is required - at
14802                  * worst a fifo underrun happens which also sets this to false.
14803                  */
14804                 crtc->cpu_fifo_underrun_disabled = true;
14805                 /*
14806                  * We track the PCH trancoder underrun reporting state
14807                  * within the crtc. With crtc for pipe A housing the underrun
14808                  * reporting state for PCH transcoder A, crtc for pipe B housing
14809                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14810                  * and marking underrun reporting as disabled for the non-existing
14811                  * PCH transcoders B and C would prevent enabling the south
14812                  * error interrupt (see cpt_can_enable_serr_int()).
14813                  */
14814                 if (has_pch_trancoder(dev_priv, crtc->pipe))
14815                         crtc->pch_fifo_underrun_disabled = true;
14816         }
14817 }
14818
14819 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14820 {
14821         struct intel_connector *connector;
14822
14823         /* We need to check both for a crtc link (meaning that the
14824          * encoder is active and trying to read from a pipe) and the
14825          * pipe itself being active. */
14826         bool has_active_crtc = encoder->base.crtc &&
14827                 to_intel_crtc(encoder->base.crtc)->active;
14828
14829         connector = intel_encoder_find_connector(encoder);
14830         if (connector && !has_active_crtc) {
14831                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14832                               encoder->base.base.id,
14833                               encoder->base.name);
14834
14835                 /* Connector is active, but has no active pipe. This is
14836                  * fallout from our resume register restoring. Disable
14837                  * the encoder manually again. */
14838                 if (encoder->base.crtc) {
14839                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14840
14841                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14842                                       encoder->base.base.id,
14843                                       encoder->base.name);
14844                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14845                         if (encoder->post_disable)
14846                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14847                 }
14848                 encoder->base.crtc = NULL;
14849
14850                 /* Inconsistent output/port/pipe state happens presumably due to
14851                  * a bug in one of the get_hw_state functions. Or someplace else
14852                  * in our code, like the register restore mess on resume. Clamp
14853                  * things to off as a safer default. */
14854
14855                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14856                 connector->base.encoder = NULL;
14857         }
14858         /* Enabled encoders without active connectors will be fixed in
14859          * the crtc fixup. */
14860 }
14861
14862 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14863 {
14864         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14865
14866         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14867                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14868                 i915_disable_vga(dev_priv);
14869         }
14870 }
14871
14872 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14873 {
14874         /* This function can be called both from intel_modeset_setup_hw_state or
14875          * at a very early point in our resume sequence, where the power well
14876          * structures are not yet restored. Since this function is at a very
14877          * paranoid "someone might have enabled VGA while we were not looking"
14878          * level, just check if the power well is enabled instead of trying to
14879          * follow the "don't touch the power well if we don't need it" policy
14880          * the rest of the driver uses. */
14881         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14882                 return;
14883
14884         i915_redisable_vga_power_on(dev_priv);
14885
14886         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14887 }
14888
14889 static bool primary_get_hw_state(struct intel_plane *plane)
14890 {
14891         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14892
14893         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14894 }
14895
14896 /* FIXME read out full plane state for all planes */
14897 static void readout_plane_state(struct intel_crtc *crtc)
14898 {
14899         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14900         bool visible;
14901
14902         visible = crtc->active && primary_get_hw_state(primary);
14903
14904         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14905                                 to_intel_plane_state(primary->base.state),
14906                                 visible);
14907 }
14908
14909 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14910 {
14911         struct drm_i915_private *dev_priv = to_i915(dev);
14912         enum pipe pipe;
14913         struct intel_crtc *crtc;
14914         struct intel_encoder *encoder;
14915         struct intel_connector *connector;
14916         struct drm_connector_list_iter conn_iter;
14917         int i;
14918
14919         dev_priv->active_crtcs = 0;
14920
14921         for_each_intel_crtc(dev, crtc) {
14922                 struct intel_crtc_state *crtc_state =
14923                         to_intel_crtc_state(crtc->base.state);
14924
14925                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
14926                 memset(crtc_state, 0, sizeof(*crtc_state));
14927                 crtc_state->base.crtc = &crtc->base;
14928
14929                 crtc_state->base.active = crtc_state->base.enable =
14930                         dev_priv->display.get_pipe_config(crtc, crtc_state);
14931
14932                 crtc->base.enabled = crtc_state->base.enable;
14933                 crtc->active = crtc_state->base.active;
14934
14935                 if (crtc_state->base.active)
14936                         dev_priv->active_crtcs |= 1 << crtc->pipe;
14937
14938                 readout_plane_state(crtc);
14939
14940                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
14941                               crtc->base.base.id, crtc->base.name,
14942                               enableddisabled(crtc_state->base.active));
14943         }
14944
14945         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14946                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14947
14948                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
14949                                                   &pll->state.hw_state);
14950                 pll->state.crtc_mask = 0;
14951                 for_each_intel_crtc(dev, crtc) {
14952                         struct intel_crtc_state *crtc_state =
14953                                 to_intel_crtc_state(crtc->base.state);
14954
14955                         if (crtc_state->base.active &&
14956                             crtc_state->shared_dpll == pll)
14957                                 pll->state.crtc_mask |= 1 << crtc->pipe;
14958                 }
14959                 pll->active_mask = pll->state.crtc_mask;
14960
14961                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14962                               pll->name, pll->state.crtc_mask, pll->on);
14963         }
14964
14965         for_each_intel_encoder(dev, encoder) {
14966                 pipe = 0;
14967
14968                 if (encoder->get_hw_state(encoder, &pipe)) {
14969                         struct intel_crtc_state *crtc_state;
14970
14971                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14972                         crtc_state = to_intel_crtc_state(crtc->base.state);
14973
14974                         encoder->base.crtc = &crtc->base;
14975                         encoder->get_config(encoder, crtc_state);
14976                 } else {
14977                         encoder->base.crtc = NULL;
14978                 }
14979
14980                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14981                               encoder->base.base.id, encoder->base.name,
14982                               enableddisabled(encoder->base.crtc),
14983                               pipe_name(pipe));
14984         }
14985
14986         drm_connector_list_iter_begin(dev, &conn_iter);
14987         for_each_intel_connector_iter(connector, &conn_iter) {
14988                 if (connector->get_hw_state(connector)) {
14989                         connector->base.dpms = DRM_MODE_DPMS_ON;
14990
14991                         encoder = connector->encoder;
14992                         connector->base.encoder = &encoder->base;
14993
14994                         if (encoder->base.crtc &&
14995                             encoder->base.crtc->state->active) {
14996                                 /*
14997                                  * This has to be done during hardware readout
14998                                  * because anything calling .crtc_disable may
14999                                  * rely on the connector_mask being accurate.
15000                                  */
15001                                 encoder->base.crtc->state->connector_mask |=
15002                                         1 << drm_connector_index(&connector->base);
15003                                 encoder->base.crtc->state->encoder_mask |=
15004                                         1 << drm_encoder_index(&encoder->base);
15005                         }
15006
15007                 } else {
15008                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15009                         connector->base.encoder = NULL;
15010                 }
15011                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15012                               connector->base.base.id, connector->base.name,
15013                               enableddisabled(connector->base.encoder));
15014         }
15015         drm_connector_list_iter_end(&conn_iter);
15016
15017         for_each_intel_crtc(dev, crtc) {
15018                 struct intel_crtc_state *crtc_state =
15019                         to_intel_crtc_state(crtc->base.state);
15020                 int min_cdclk = 0;
15021
15022                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15023                 if (crtc_state->base.active) {
15024                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15025                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15026                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15027
15028                         /*
15029                          * The initial mode needs to be set in order to keep
15030                          * the atomic core happy. It wants a valid mode if the
15031                          * crtc's enabled, so we do the above call.
15032                          *
15033                          * But we don't set all the derived state fully, hence
15034                          * set a flag to indicate that a full recalculation is
15035                          * needed on the next commit.
15036                          */
15037                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15038
15039                         intel_crtc_compute_pixel_rate(crtc_state);
15040
15041                         if (dev_priv->display.modeset_calc_cdclk) {
15042                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15043                                 if (WARN_ON(min_cdclk < 0))
15044                                         min_cdclk = 0;
15045                         }
15046
15047                         drm_calc_timestamping_constants(&crtc->base,
15048                                                         &crtc_state->base.adjusted_mode);
15049                         update_scanline_offset(crtc);
15050                 }
15051
15052                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15053                 dev_priv->min_voltage_level[crtc->pipe] =
15054                         crtc_state->min_voltage_level;
15055
15056                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15057         }
15058 }
15059
15060 static void
15061 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15062 {
15063         struct intel_encoder *encoder;
15064
15065         for_each_intel_encoder(&dev_priv->drm, encoder) {
15066                 u64 get_domains;
15067                 enum intel_display_power_domain domain;
15068
15069                 if (!encoder->get_power_domains)
15070                         continue;
15071
15072                 get_domains = encoder->get_power_domains(encoder);
15073                 for_each_power_domain(domain, get_domains)
15074                         intel_display_power_get(dev_priv, domain);
15075         }
15076 }
15077
15078 /* Scan out the current hw modeset state,
15079  * and sanitizes it to the current state
15080  */
15081 static void
15082 intel_modeset_setup_hw_state(struct drm_device *dev,
15083                              struct drm_modeset_acquire_ctx *ctx)
15084 {
15085         struct drm_i915_private *dev_priv = to_i915(dev);
15086         enum pipe pipe;
15087         struct intel_crtc *crtc;
15088         struct intel_encoder *encoder;
15089         int i;
15090
15091         if (IS_HASWELL(dev_priv)) {
15092                 /*
15093                  * WaRsPkgCStateDisplayPMReq:hsw
15094                  * System hang if this isn't done before disabling all planes!
15095                  */
15096                 I915_WRITE(CHICKEN_PAR1_1,
15097                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15098         }
15099
15100         intel_modeset_readout_hw_state(dev);
15101
15102         /* HW state is read out, now we need to sanitize this mess. */
15103         get_encoder_power_domains(dev_priv);
15104
15105         for_each_intel_encoder(dev, encoder) {
15106                 intel_sanitize_encoder(encoder);
15107         }
15108
15109         for_each_pipe(dev_priv, pipe) {
15110                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15111
15112                 intel_sanitize_crtc(crtc, ctx);
15113                 intel_dump_pipe_config(crtc, crtc->config,
15114                                        "[setup_hw_state]");
15115         }
15116
15117         intel_modeset_update_connector_atomic_state(dev);
15118
15119         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15120                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15121
15122                 if (!pll->on || pll->active_mask)
15123                         continue;
15124
15125                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15126
15127                 pll->funcs.disable(dev_priv, pll);
15128                 pll->on = false;
15129         }
15130
15131         if (IS_G4X(dev_priv)) {
15132                 g4x_wm_get_hw_state(dev);
15133                 g4x_wm_sanitize(dev_priv);
15134         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15135                 vlv_wm_get_hw_state(dev);
15136                 vlv_wm_sanitize(dev_priv);
15137         } else if (INTEL_GEN(dev_priv) >= 9) {
15138                 skl_wm_get_hw_state(dev);
15139         } else if (HAS_PCH_SPLIT(dev_priv)) {
15140                 ilk_wm_get_hw_state(dev);
15141         }
15142
15143         for_each_intel_crtc(dev, crtc) {
15144                 u64 put_domains;
15145
15146                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15147                 if (WARN_ON(put_domains))
15148                         modeset_put_power_domains(dev_priv, put_domains);
15149         }
15150         intel_display_set_init_power(dev_priv, false);
15151
15152         intel_power_domains_verify_state(dev_priv);
15153
15154         intel_fbc_init_pipe_state(dev_priv);
15155 }
15156
15157 void intel_display_resume(struct drm_device *dev)
15158 {
15159         struct drm_i915_private *dev_priv = to_i915(dev);
15160         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15161         struct drm_modeset_acquire_ctx ctx;
15162         int ret;
15163
15164         dev_priv->modeset_restore_state = NULL;
15165         if (state)
15166                 state->acquire_ctx = &ctx;
15167
15168         drm_modeset_acquire_init(&ctx, 0);
15169
15170         while (1) {
15171                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15172                 if (ret != -EDEADLK)
15173                         break;
15174
15175                 drm_modeset_backoff(&ctx);
15176         }
15177
15178         if (!ret)
15179                 ret = __intel_display_resume(dev, state, &ctx);
15180
15181         intel_enable_ipc(dev_priv);
15182         drm_modeset_drop_locks(&ctx);
15183         drm_modeset_acquire_fini(&ctx);
15184
15185         if (ret)
15186                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15187         if (state)
15188                 drm_atomic_state_put(state);
15189 }
15190
15191 int intel_connector_register(struct drm_connector *connector)
15192 {
15193         struct intel_connector *intel_connector = to_intel_connector(connector);
15194         int ret;
15195
15196         ret = intel_backlight_device_register(intel_connector);
15197         if (ret)
15198                 goto err;
15199
15200         return 0;
15201
15202 err:
15203         return ret;
15204 }
15205
15206 void intel_connector_unregister(struct drm_connector *connector)
15207 {
15208         struct intel_connector *intel_connector = to_intel_connector(connector);
15209
15210         intel_backlight_device_unregister(intel_connector);
15211         intel_panel_destroy_backlight(connector);
15212 }
15213
15214 static void intel_hpd_poll_fini(struct drm_device *dev)
15215 {
15216         struct intel_connector *connector;
15217         struct drm_connector_list_iter conn_iter;
15218
15219         /* First disable polling... */
15220         drm_kms_helper_poll_fini(dev);
15221
15222         /* Then kill the work that may have been queued by hpd. */
15223         drm_connector_list_iter_begin(dev, &conn_iter);
15224         for_each_intel_connector_iter(connector, &conn_iter) {
15225                 if (connector->modeset_retry_work.func)
15226                         cancel_work_sync(&connector->modeset_retry_work);
15227         }
15228         drm_connector_list_iter_end(&conn_iter);
15229 }
15230
15231 void intel_modeset_cleanup(struct drm_device *dev)
15232 {
15233         struct drm_i915_private *dev_priv = to_i915(dev);
15234
15235         flush_work(&dev_priv->atomic_helper.free_work);
15236         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15237
15238         intel_disable_gt_powersave(dev_priv);
15239
15240         /*
15241          * Interrupts and polling as the first thing to avoid creating havoc.
15242          * Too much stuff here (turning of connectors, ...) would
15243          * experience fancy races otherwise.
15244          */
15245         intel_irq_uninstall(dev_priv);
15246
15247         /*
15248          * Due to the hpd irq storm handling the hotplug work can re-arm the
15249          * poll handlers. Hence disable polling after hpd handling is shut down.
15250          */
15251         intel_hpd_poll_fini(dev);
15252
15253         /* poll work can call into fbdev, hence clean that up afterwards */
15254         intel_fbdev_fini(dev_priv);
15255
15256         intel_unregister_dsm_handler();
15257
15258         intel_fbc_global_disable(dev_priv);
15259
15260         /* flush any delayed tasks or pending work */
15261         flush_scheduled_work();
15262
15263         drm_mode_config_cleanup(dev);
15264
15265         intel_cleanup_overlay(dev_priv);
15266
15267         intel_cleanup_gt_powersave(dev_priv);
15268
15269         intel_teardown_gmbus(dev_priv);
15270 }
15271
15272 void intel_connector_attach_encoder(struct intel_connector *connector,
15273                                     struct intel_encoder *encoder)
15274 {
15275         connector->encoder = encoder;
15276         drm_mode_connector_attach_encoder(&connector->base,
15277                                           &encoder->base);
15278 }
15279
15280 /*
15281  * set vga decode state - true == enable VGA decode
15282  */
15283 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15284 {
15285         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15286         u16 gmch_ctrl;
15287
15288         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15289                 DRM_ERROR("failed to read control word\n");
15290                 return -EIO;
15291         }
15292
15293         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15294                 return 0;
15295
15296         if (state)
15297                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15298         else
15299                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15300
15301         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15302                 DRM_ERROR("failed to write control word\n");
15303                 return -EIO;
15304         }
15305
15306         return 0;
15307 }
15308
15309 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15310
15311 struct intel_display_error_state {
15312
15313         u32 power_well_driver;
15314
15315         int num_transcoders;
15316
15317         struct intel_cursor_error_state {
15318                 u32 control;
15319                 u32 position;
15320                 u32 base;
15321                 u32 size;
15322         } cursor[I915_MAX_PIPES];
15323
15324         struct intel_pipe_error_state {
15325                 bool power_domain_on;
15326                 u32 source;
15327                 u32 stat;
15328         } pipe[I915_MAX_PIPES];
15329
15330         struct intel_plane_error_state {
15331                 u32 control;
15332                 u32 stride;
15333                 u32 size;
15334                 u32 pos;
15335                 u32 addr;
15336                 u32 surface;
15337                 u32 tile_offset;
15338         } plane[I915_MAX_PIPES];
15339
15340         struct intel_transcoder_error_state {
15341                 bool power_domain_on;
15342                 enum transcoder cpu_transcoder;
15343
15344                 u32 conf;
15345
15346                 u32 htotal;
15347                 u32 hblank;
15348                 u32 hsync;
15349                 u32 vtotal;
15350                 u32 vblank;
15351                 u32 vsync;
15352         } transcoder[4];
15353 };
15354
15355 struct intel_display_error_state *
15356 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15357 {
15358         struct intel_display_error_state *error;
15359         int transcoders[] = {
15360                 TRANSCODER_A,
15361                 TRANSCODER_B,
15362                 TRANSCODER_C,
15363                 TRANSCODER_EDP,
15364         };
15365         int i;
15366
15367         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15368                 return NULL;
15369
15370         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15371         if (error == NULL)
15372                 return NULL;
15373
15374         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15375                 error->power_well_driver =
15376                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15377
15378         for_each_pipe(dev_priv, i) {
15379                 error->pipe[i].power_domain_on =
15380                         __intel_display_power_is_enabled(dev_priv,
15381                                                          POWER_DOMAIN_PIPE(i));
15382                 if (!error->pipe[i].power_domain_on)
15383                         continue;
15384
15385                 error->cursor[i].control = I915_READ(CURCNTR(i));
15386                 error->cursor[i].position = I915_READ(CURPOS(i));
15387                 error->cursor[i].base = I915_READ(CURBASE(i));
15388
15389                 error->plane[i].control = I915_READ(DSPCNTR(i));
15390                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15391                 if (INTEL_GEN(dev_priv) <= 3) {
15392                         error->plane[i].size = I915_READ(DSPSIZE(i));
15393                         error->plane[i].pos = I915_READ(DSPPOS(i));
15394                 }
15395                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15396                         error->plane[i].addr = I915_READ(DSPADDR(i));
15397                 if (INTEL_GEN(dev_priv) >= 4) {
15398                         error->plane[i].surface = I915_READ(DSPSURF(i));
15399                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15400                 }
15401
15402                 error->pipe[i].source = I915_READ(PIPESRC(i));
15403
15404                 if (HAS_GMCH_DISPLAY(dev_priv))
15405                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15406         }
15407
15408         /* Note: this does not include DSI transcoders. */
15409         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15410         if (HAS_DDI(dev_priv))
15411                 error->num_transcoders++; /* Account for eDP. */
15412
15413         for (i = 0; i < error->num_transcoders; i++) {
15414                 enum transcoder cpu_transcoder = transcoders[i];
15415
15416                 error->transcoder[i].power_domain_on =
15417                         __intel_display_power_is_enabled(dev_priv,
15418                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15419                 if (!error->transcoder[i].power_domain_on)
15420                         continue;
15421
15422                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15423
15424                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15425                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15426                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15427                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15428                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15429                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15430                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15431         }
15432
15433         return error;
15434 }
15435
15436 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15437
15438 void
15439 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15440                                 struct intel_display_error_state *error)
15441 {
15442         struct drm_i915_private *dev_priv = m->i915;
15443         int i;
15444
15445         if (!error)
15446                 return;
15447
15448         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15449         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15450                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15451                            error->power_well_driver);
15452         for_each_pipe(dev_priv, i) {
15453                 err_printf(m, "Pipe [%d]:\n", i);
15454                 err_printf(m, "  Power: %s\n",
15455                            onoff(error->pipe[i].power_domain_on));
15456                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15457                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15458
15459                 err_printf(m, "Plane [%d]:\n", i);
15460                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15461                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15462                 if (INTEL_GEN(dev_priv) <= 3) {
15463                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15464                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15465                 }
15466                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15467                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15468                 if (INTEL_GEN(dev_priv) >= 4) {
15469                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15470                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15471                 }
15472
15473                 err_printf(m, "Cursor [%d]:\n", i);
15474                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15475                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15476                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15477         }
15478
15479         for (i = 0; i < error->num_transcoders; i++) {
15480                 err_printf(m, "CPU transcoder: %s\n",
15481                            transcoder_name(error->transcoder[i].cpu_transcoder));
15482                 err_printf(m, "  Power: %s\n",
15483                            onoff(error->transcoder[i].power_domain_on));
15484                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15485                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15486                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15487                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15488                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15489                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15490                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15491         }
15492 }
15493
15494 #endif