drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else
 223                 return dev_priv->fdi_pll_freq;
 224 }
 225
 226 static const struct intel_limit intel_limits_i8xx_dac = {
 227         .dot = { .min = 25000, .max = 350000 },
 228         .vco = { .min = 908000, .max = 1512000 },
 229         .n = { .min = 2, .max = 16 },
 230         .m = { .min = 96, .max = 140 },
 231         .m1 = { .min = 18, .max = 26 },
 232         .m2 = { .min = 6, .max = 16 },
 233         .p = { .min = 4, .max = 128 },
 234         .p1 = { .min = 2, .max = 33 },
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 4, .p2_fast = 2 },
 237 };
 238
 239 static const struct intel_limit intel_limits_i8xx_dvo = {
 240         .dot = { .min = 25000, .max = 350000 },
 241         .vco = { .min = 908000, .max = 1512000 },
 242         .n = { .min = 2, .max = 16 },
 243         .m = { .min = 96, .max = 140 },
 244         .m1 = { .min = 18, .max = 26 },
 245         .m2 = { .min = 6, .max = 16 },
 246         .p = { .min = 4, .max = 128 },
 247         .p1 = { .min = 2, .max = 33 },
 248         .p2 = { .dot_limit = 165000,
 249                 .p2_slow = 4, .p2_fast = 4 },
 250 };
 251
 252 static const struct intel_limit intel_limits_i8xx_lvds = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 908000, .max = 1512000 },
 255         .n = { .min = 2, .max = 16 },
 256         .m = { .min = 96, .max = 140 },
 257         .m1 = { .min = 18, .max = 26 },
 258         .m2 = { .min = 6, .max = 16 },
 259         .p = { .min = 4, .max = 128 },
 260         .p1 = { .min = 1, .max = 6 },
 261         .p2 = { .dot_limit = 165000,
 262                 .p2_slow = 14, .p2_fast = 7 },
 263 };
 264
 265 static const struct intel_limit intel_limits_i9xx_sdvo = {
 266         .dot = { .min = 20000, .max = 400000 },
 267         .vco = { .min = 1400000, .max = 2800000 },
 268         .n = { .min = 1, .max = 6 },
 269         .m = { .min = 70, .max = 120 },
 270         .m1 = { .min = 8, .max = 18 },
 271         .m2 = { .min = 3, .max = 7 },
 272         .p = { .min = 5, .max = 80 },
 273         .p1 = { .min = 1, .max = 8 },
 274         .p2 = { .dot_limit = 200000,
 275                 .p2_slow = 10, .p2_fast = 5 },
 276 };
 277
 278 static const struct intel_limit intel_limits_i9xx_lvds = {
 279         .dot = { .min = 20000, .max = 400000 },
 280         .vco = { .min = 1400000, .max = 2800000 },
 281         .n = { .min = 1, .max = 6 },
 282         .m = { .min = 70, .max = 120 },
 283         .m1 = { .min = 8, .max = 18 },
 284         .m2 = { .min = 3, .max = 7 },
 285         .p = { .min = 7, .max = 98 },
 286         .p1 = { .min = 1, .max = 8 },
 287         .p2 = { .dot_limit = 112000,
 288                 .p2_slow = 14, .p2_fast = 7 },
 289 };
 290
 291
 292 static const struct intel_limit intel_limits_g4x_sdvo = {
 293         .dot = { .min = 25000, .max = 270000 },
 294         .vco = { .min = 1750000, .max = 3500000},
 295         .n = { .min = 1, .max = 4 },
 296         .m = { .min = 104, .max = 138 },
 297         .m1 = { .min = 17, .max = 23 },
 298         .m2 = { .min = 5, .max = 11 },
 299         .p = { .min = 10, .max = 30 },
 300         .p1 = { .min = 1, .max = 3},
 301         .p2 = { .dot_limit = 270000,
 302                 .p2_slow = 10,
 303                 .p2_fast = 10
 304         },
 305 };
 306
 307 static const struct intel_limit intel_limits_g4x_hdmi = {
 308         .dot = { .min = 22000, .max = 400000 },
 309         .vco = { .min = 1750000, .max = 3500000},
 310         .n = { .min = 1, .max = 4 },
 311         .m = { .min = 104, .max = 138 },
 312         .m1 = { .min = 16, .max = 23 },
 313         .m2 = { .min = 5, .max = 11 },
 314         .p = { .min = 5, .max = 80 },
 315         .p1 = { .min = 1, .max = 8},
 316         .p2 = { .dot_limit = 165000,
 317                 .p2_slow = 10, .p2_fast = 5 },
 318 };
 319
 320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 321         .dot = { .min = 20000, .max = 115000 },
 322         .vco = { .min = 1750000, .max = 3500000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 104, .max = 138 },
 325         .m1 = { .min = 17, .max = 23 },
 326         .m2 = { .min = 5, .max = 11 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 0,
 330                 .p2_slow = 14, .p2_fast = 14
 331         },
 332 };
 333
 334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 335         .dot = { .min = 80000, .max = 224000 },
 336         .vco = { .min = 1750000, .max = 3500000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 104, .max = 138 },
 339         .m1 = { .min = 17, .max = 23 },
 340         .m2 = { .min = 5, .max = 11 },
 341         .p = { .min = 14, .max = 42 },
 342         .p1 = { .min = 2, .max = 6 },
 343         .p2 = { .dot_limit = 0,
 344                 .p2_slow = 7, .p2_fast = 7
 345         },
 346 };
 347
 348 static const struct intel_limit intel_limits_pineview_sdvo = {
 349         .dot = { .min = 20000, .max = 400000},
 350         .vco = { .min = 1700000, .max = 3500000 },
 351         /* Pineview's Ncounter is a ring counter */
 352         .n = { .min = 3, .max = 6 },
 353         .m = { .min = 2, .max = 256 },
 354         /* Pineview only has one combined m divider, which we treat as m2. */
 355         .m1 = { .min = 0, .max = 0 },
 356         .m2 = { .min = 0, .max = 254 },
 357         .p = { .min = 5, .max = 80 },
 358         .p1 = { .min = 1, .max = 8 },
 359         .p2 = { .dot_limit = 200000,
 360                 .p2_slow = 10, .p2_fast = 5 },
 361 };
 362
 363 static const struct intel_limit intel_limits_pineview_lvds = {
 364         .dot = { .min = 20000, .max = 400000 },
 365         .vco = { .min = 1700000, .max = 3500000 },
 366         .n = { .min = 3, .max = 6 },
 367         .m = { .min = 2, .max = 256 },
 368         .m1 = { .min = 0, .max = 0 },
 369         .m2 = { .min = 0, .max = 254 },
 370         .p = { .min = 7, .max = 112 },
 371         .p1 = { .min = 1, .max = 8 },
 372         .p2 = { .dot_limit = 112000,
 373                 .p2_slow = 14, .p2_fast = 14 },
 374 };
 375
 376 /* Ironlake / Sandybridge
 377  *
 378  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 379  * the range value for them is (actual_value - 2).
 380  */
 381 static const struct intel_limit intel_limits_ironlake_dac = {
 382         .dot = { .min = 25000, .max = 350000 },
 383         .vco = { .min = 1760000, .max = 3510000 },
 384         .n = { .min = 1, .max = 5 },
 385         .m = { .min = 79, .max = 127 },
 386         .m1 = { .min = 12, .max = 22 },
 387         .m2 = { .min = 5, .max = 9 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 225000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 395         .dot = { .min = 25000, .max = 350000 },
 396         .vco = { .min = 1760000, .max = 3510000 },
 397         .n = { .min = 1, .max = 3 },
 398         .m = { .min = 79, .max = 118 },
 399         .m1 = { .min = 12, .max = 22 },
 400         .m2 = { .min = 5, .max = 9 },
 401         .p = { .min = 28, .max = 112 },
 402         .p1 = { .min = 2, .max = 8 },
 403         .p2 = { .dot_limit = 225000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 408         .dot = { .min = 25000, .max = 350000 },
 409         .vco = { .min = 1760000, .max = 3510000 },
 410         .n = { .min = 1, .max = 3 },
 411         .m = { .min = 79, .max = 127 },
 412         .m1 = { .min = 12, .max = 22 },
 413         .m2 = { .min = 5, .max = 9 },
 414         .p = { .min = 14, .max = 56 },
 415         .p1 = { .min = 2, .max = 8 },
 416         .p2 = { .dot_limit = 225000,
 417                 .p2_slow = 7, .p2_fast = 7 },
 418 };
 419
 420 /* LVDS 100mhz refclk limits. */
 421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 422         .dot = { .min = 25000, .max = 350000 },
 423         .vco = { .min = 1760000, .max = 3510000 },
 424         .n = { .min = 1, .max = 2 },
 425         .m = { .min = 79, .max = 126 },
 426         .m1 = { .min = 12, .max = 22 },
 427         .m2 = { .min = 5, .max = 9 },
 428         .p = { .min = 28, .max = 112 },
 429         .p1 = { .min = 2, .max = 8 },
 430         .p2 = { .dot_limit = 225000,
 431                 .p2_slow = 14, .p2_fast = 14 },
 432 };
 433
 434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 435         .dot = { .min = 25000, .max = 350000 },
 436         .vco = { .min = 1760000, .max = 3510000 },
 437         .n = { .min = 1, .max = 3 },
 438         .m = { .min = 79, .max = 126 },
 439         .m1 = { .min = 12, .max = 22 },
 440         .m2 = { .min = 5, .max = 9 },
 441         .p = { .min = 14, .max = 42 },
 442         .p1 = { .min = 2, .max = 6 },
 443         .p2 = { .dot_limit = 225000,
 444                 .p2_slow = 7, .p2_fast = 7 },
 445 };
 446
 447 static const struct intel_limit intel_limits_vlv = {
 448          /*
 449           * These are the data rate limits (measured in fast clocks)
 450           * since those are the strictest limits we have. The fast
 451           * clock and actual rate limits are more relaxed, so checking
 452           * them would make no difference.
 453           */
 454         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 455         .vco = { .min = 4000000, .max = 6000000 },
 456         .n = { .min = 1, .max = 7 },
 457         .m1 = { .min = 2, .max = 3 },
 458         .m2 = { .min = 11, .max = 156 },
 459         .p1 = { .min = 2, .max = 3 },
 460         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 461 };
 462
 463 static const struct intel_limit intel_limits_chv = {
 464         /*
 465          * These are the data rate limits (measured in fast clocks)
 466          * since those are the strictest limits we have.  The fast
 467          * clock and actual rate limits are more relaxed, so checking
 468          * them would make no difference.
 469          */
 470         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 471         .vco = { .min = 4800000, .max = 6480000 },
 472         .n = { .min = 1, .max = 1 },
 473         .m1 = { .min = 2, .max = 2 },
 474         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 475         .p1 = { .min = 2, .max = 4 },
 476         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 477 };
 478
 479 static const struct intel_limit intel_limits_bxt = {
 480         /* FIXME: find real dot limits */
 481         .dot = { .min = 0, .max = INT_MAX },
 482         .vco = { .min = 4800000, .max = 6700000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         /* FIXME: find real m2 limits */
 486         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 487         .p1 = { .min = 2, .max = 4 },
 488         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 489 };
 490
 491 static void
 492 skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
 493 {
 494         if (IS_SKYLAKE(dev_priv))
 495                 return;
 496
 497         if (enable)
 498                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 499                            DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 500         else
 501                 I915_WRITE(CLKGATE_DIS_PSL(pipe),
 502                            I915_READ(CLKGATE_DIS_PSL(pipe)) &
 503                            ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 504 }
 505
 506 static bool
 507 needs_modeset(const struct drm_crtc_state *state)
 508 {
 509         return drm_atomic_crtc_needs_modeset(state);
 510 }
 511
 512 /*
 513  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 514  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 515  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 516  * The helpers' return value is the rate of the clock that is fed to the
 517  * display engine's pipe which can be the above fast dot clock rate or a
 518  * divided-down version of it.
 519  */
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return 0;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529
 530         return clock->dot;
 531 }
 532
 533 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 534 {
 535         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 536 }
 537
 538 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 539 {
 540         clock->m = i9xx_dpll_compute_m(clock);
 541         clock->p = clock->p1 * clock->p2;
 542         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 543                 return 0;
 544         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 545         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 546
 547         return clock->dot;
 548 }
 549
 550 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 551 {
 552         clock->m = clock->m1 * clock->m2;
 553         clock->p = clock->p1 * clock->p2;
 554         if (WARN_ON(clock->n == 0 || clock->p == 0))
 555                 return 0;
 556         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558
 559         return clock->dot / 5;
 560 }
 561
 562 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 563 {
 564         clock->m = clock->m1 * clock->m2;
 565         clock->p = clock->p1 * clock->p2;
 566         if (WARN_ON(clock->n == 0 || clock->p == 0))
 567                 return 0;
 568         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 569                         clock->n << 22);
 570         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 571
 572         return clock->dot / 5;
 573 }
 574
 575 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 576
 577 /*
 578  * Returns whether the given set of divisors are valid for a given refclk with
 579  * the given connectors.
 580  */
 581 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 582                                const struct intel_limit *limit,
 583                                const struct dpll *clock)
 584 {
 585         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 586                 INTELPllInvalid("n out of range\n");
 587         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 588                 INTELPllInvalid("p1 out of range\n");
 589         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 590                 INTELPllInvalid("m2 out of range\n");
 591         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 592                 INTELPllInvalid("m1 out of range\n");
 593
 594         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 595             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 596                 if (clock->m1 <= clock->m2)
 597                         INTELPllInvalid("m1 <= m2\n");
 598
 599         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 600             !IS_GEN9_LP(dev_priv)) {
 601                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 602                         INTELPllInvalid("p out of range\n");
 603                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 604                         INTELPllInvalid("m out of range\n");
 605         }
 606
 607         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 608                 INTELPllInvalid("vco out of range\n");
 609         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 610          * connector, etc., rather than just a single range.
 611          */
 612         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 613                 INTELPllInvalid("dot out of range\n");
 614
 615         return true;
 616 }
 617
 618 static int
 619 i9xx_select_p2_div(const struct intel_limit *limit,
 620                    const struct intel_crtc_state *crtc_state,
 621                    int target)
 622 {
 623         struct drm_device *dev = crtc_state->base.crtc->dev;
 624
 625         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 626                 /*
 627                  * For LVDS just rely on its current settings for dual-channel.
 628                  * We haven't figured out how to reliably set up different
 629                  * single/dual channel state, if we even can.
 630                  */
 631                 if (intel_is_dual_link_lvds(dev))
 632                         return limit->p2.p2_fast;
 633                 else
 634                         return limit->p2.p2_slow;
 635         } else {
 636                 if (target < limit->p2.dot_limit)
 637                         return limit->p2.p2_slow;
 638                 else
 639                         return limit->p2.p2_fast;
 640         }
 641 }
 642
 643 /*
 644  * Returns a set of divisors for the desired target clock with the given
 645  * refclk, or FALSE.  The returned values represent the clock equation:
 646  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 647  *
 648  * Target and reference clocks are specified in kHz.
 649  *
 650  * If match_clock is provided, then best_clock P divider must match the P
 651  * divider from @match_clock used for LVDS downclocking.
 652  */
 653 static bool
 654 i9xx_find_best_dpll(const struct intel_limit *limit,
 655                     struct intel_crtc_state *crtc_state,
 656                     int target, int refclk, struct dpll *match_clock,
 657                     struct dpll *best_clock)
 658 {
 659         struct drm_device *dev = crtc_state->base.crtc->dev;
 660         struct dpll clock;
 661         int err = target;
 662
 663         memset(best_clock, 0, sizeof(*best_clock));
 664
 665         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         if (clock.m2 >= clock.m1)
 672                                 break;
 673                         for (clock.n = limit->n.min;
 674                              clock.n <= limit->n.max; clock.n++) {
 675                                 for (clock.p1 = limit->p1.min;
 676                                         clock.p1 <= limit->p1.max; clock.p1++) {
 677                                         int this_err;
 678
 679                                         i9xx_calc_dpll_params(refclk, &clock);
 680                                         if (!intel_PLL_is_valid(to_i915(dev),
 681                                                                 limit,
 682                                                                 &clock))
 683                                                 continue;
 684                                         if (match_clock &&
 685                                             clock.p != match_clock->p)
 686                                                 continue;
 687
 688                                         this_err = abs(clock.dot - target);
 689                                         if (this_err < err) {
 690                                                 *best_clock = clock;
 691                                                 err = this_err;
 692                                         }
 693                                 }
 694                         }
 695                 }
 696         }
 697
 698         return (err != target);
 699 }
 700
 701 /*
 702  * Returns a set of divisors for the desired target clock with the given
 703  * refclk, or FALSE.  The returned values represent the clock equation:
 704  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 705  *
 706  * Target and reference clocks are specified in kHz.
 707  *
 708  * If match_clock is provided, then best_clock P divider must match the P
 709  * divider from @match_clock used for LVDS downclocking.
 710  */
 711 static bool
 712 pnv_find_best_dpll(const struct intel_limit *limit,
 713                    struct intel_crtc_state *crtc_state,
 714                    int target, int refclk, struct dpll *match_clock,
 715                    struct dpll *best_clock)
 716 {
 717         struct drm_device *dev = crtc_state->base.crtc->dev;
 718         struct dpll clock;
 719         int err = target;
 720
 721         memset(best_clock, 0, sizeof(*best_clock));
 722
 723         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 724
 725         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 726              clock.m1++) {
 727                 for (clock.m2 = limit->m2.min;
 728                      clock.m2 <= limit->m2.max; clock.m2++) {
 729                         for (clock.n = limit->n.min;
 730                              clock.n <= limit->n.max; clock.n++) {
 731                                 for (clock.p1 = limit->p1.min;
 732                                         clock.p1 <= limit->p1.max; clock.p1++) {
 733                                         int this_err;
 734
 735                                         pnv_calc_dpll_params(refclk, &clock);
 736                                         if (!intel_PLL_is_valid(to_i915(dev),
 737                                                                 limit,
 738                                                                 &clock))
 739                                                 continue;
 740                                         if (match_clock &&
 741                                             clock.p != match_clock->p)
 742                                                 continue;
 743
 744                                         this_err = abs(clock.dot - target);
 745                                         if (this_err < err) {
 746                                                 *best_clock = clock;
 747                                                 err = this_err;
 748                                         }
 749                                 }
 750                         }
 751                 }
 752         }
 753
 754         return (err != target);
 755 }
 756
 757 /*
 758  * Returns a set of divisors for the desired target clock with the given
 759  * refclk, or FALSE.  The returned values represent the clock equation:
 760  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 761  *
 762  * Target and reference clocks are specified in kHz.
 763  *
 764  * If match_clock is provided, then best_clock P divider must match the P
 765  * divider from @match_clock used for LVDS downclocking.
 766  */
 767 static bool
 768 g4x_find_best_dpll(const struct intel_limit *limit,
 769                    struct intel_crtc_state *crtc_state,
 770                    int target, int refclk, struct dpll *match_clock,
 771                    struct dpll *best_clock)
 772 {
 773         struct drm_device *dev = crtc_state->base.crtc->dev;
 774         struct dpll clock;
 775         int max_n;
 776         bool found = false;
 777         /* approximately equals target * 0.00585 */
 778         int err_most = (target >> 8) + (target >> 9);
 779
 780         memset(best_clock, 0, sizeof(*best_clock));
 781
 782         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 783
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         i9xx_calc_dpll_params(refclk, &clock);
 797                                         if (!intel_PLL_is_valid(to_i915(dev),
 798                                                                 limit,
 799                                                                 &clock))
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err_most) {
 804                                                 *best_clock = clock;
 805                                                 err_most = this_err;
 806                                                 max_n = clock.n;
 807                                                 found = true;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813         return found;
 814 }
 815
 816 /*
 817  * Check if the calculated PLL configuration is more optimal compared to the
 818  * best configuration and error found so far. Return the calculated error.
 819  */
 820 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 821                                const struct dpll *calculated_clock,
 822                                const struct dpll *best_clock,
 823                                unsigned int best_error_ppm,
 824                                unsigned int *error_ppm)
 825 {
 826         /*
 827          * For CHV ignore the error and consider only the P value.
 828          * Prefer a bigger P value based on HW requirements.
 829          */
 830         if (IS_CHERRYVIEW(to_i915(dev))) {
 831                 *error_ppm = 0;
 832
 833                 return calculated_clock->p > best_clock->p;
 834         }
 835
 836         if (WARN_ON_ONCE(!target_freq))
 837                 return false;
 838
 839         *error_ppm = div_u64(1000000ULL *
 840                                 abs(target_freq - calculated_clock->dot),
 841                              target_freq);
 842         /*
 843          * Prefer a better P value over a better (smaller) error if the error
 844          * is small. Ensure this preference for future configurations too by
 845          * setting the error to 0.
 846          */
 847         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 848                 *error_ppm = 0;
 849
 850                 return true;
 851         }
 852
 853         return *error_ppm + 10 < best_error_ppm;
 854 }
 855
 856 /*
 857  * Returns a set of divisors for the desired target clock with the given
 858  * refclk, or FALSE.  The returned values represent the clock equation:
 859  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 860  */
 861 static bool
 862 vlv_find_best_dpll(const struct intel_limit *limit,
 863                    struct intel_crtc_state *crtc_state,
 864                    int target, int refclk, struct dpll *match_clock,
 865                    struct dpll *best_clock)
 866 {
 867         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 868         struct drm_device *dev = crtc->base.dev;
 869         struct dpll clock;
 870         unsigned int bestppm = 1000000;
 871         /* min update 19.2 MHz */
 872         int max_n = min(limit->n.max, refclk / 19200);
 873         bool found = false;
 874
 875         target *= 5; /* fast clock */
 876
 877         memset(best_clock, 0, sizeof(*best_clock));
 878
 879         /* based on hardware requirement, prefer smaller n to precision */
 880         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 881                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 882                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 883                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 884                                 clock.p = clock.p1 * clock.p2;
 885                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 886                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 887                                         unsigned int ppm;
 888
 889                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 890                                                                      refclk * clock.m1);
 891
 892                                         vlv_calc_dpll_params(refclk, &clock);
 893
 894                                         if (!intel_PLL_is_valid(to_i915(dev),
 895                                                                 limit,
 896                                                                 &clock))
 897                                                 continue;
 898
 899                                         if (!vlv_PLL_is_optimal(dev, target,
 900                                                                 &clock,
 901                                                                 best_clock,
 902                                                                 bestppm, &ppm))
 903                                                 continue;
 904
 905                                         *best_clock = clock;
 906                                         bestppm = ppm;
 907                                         found = true;
 908                                 }
 909                         }
 910                 }
 911         }
 912
 913         return found;
 914 }
 915
 916 /*
 917  * Returns a set of divisors for the desired target clock with the given
 918  * refclk, or FALSE.  The returned values represent the clock equation:
 919  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 920  */
 921 static bool
 922 chv_find_best_dpll(const struct intel_limit *limit,
 923                    struct intel_crtc_state *crtc_state,
 924                    int target, int refclk, struct dpll *match_clock,
 925                    struct dpll *best_clock)
 926 {
 927         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 928         struct drm_device *dev = crtc->base.dev;
 929         unsigned int best_error_ppm;
 930         struct dpll clock;
 931         uint64_t m2;
 932         int found = false;
 933
 934         memset(best_clock, 0, sizeof(*best_clock));
 935         best_error_ppm = 1000000;
 936
 937         /*
 938          * Based on hardware doc, the n always set to 1, and m1 always
 939          * set to 2.  If requires to support 200Mhz refclk, we need to
 940          * revisit this because n may not 1 anymore.
 941          */
 942         clock.n = 1, clock.m1 = 2;
 943         target *= 5;    /* fast clock */
 944
 945         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 946                 for (clock.p2 = limit->p2.p2_fast;
 947                                 clock.p2 >= limit->p2.p2_slow;
 948                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 949                         unsigned int error_ppm;
 950
 951                         clock.p = clock.p1 * clock.p2;
 952
 953                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 954                                         clock.n) << 22, refclk * clock.m1);
 955
 956                         if (m2 > INT_MAX/clock.m1)
 957                                 continue;
 958
 959                         clock.m2 = m2;
 960
 961                         chv_calc_dpll_params(refclk, &clock);
 962
 963                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 964                                 continue;
 965
 966                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 967                                                 best_error_ppm, &error_ppm))
 968                                 continue;
 969
 970                         *best_clock = clock;
 971                         best_error_ppm = error_ppm;
 972                         found = true;
 973                 }
 974         }
 975
 976         return found;
 977 }
 978
 979 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 980                         struct dpll *best_clock)
 981 {
 982         int refclk = 100000;
 983         const struct intel_limit *limit = &intel_limits_bxt;
 984
 985         return chv_find_best_dpll(limit, crtc_state,
 986                                   target_clock, refclk, NULL, best_clock);
 987 }
 988
 989 bool intel_crtc_active(struct intel_crtc *crtc)
 990 {
 991         /* Be paranoid as we can arrive here with only partial
 992          * state retrieved from the hardware during setup.
 993          *
 994          * We can ditch the adjusted_mode.crtc_clock check as soon
 995          * as Haswell has gained clock readout/fastboot support.
 996          *
 997          * We can ditch the crtc->primary->fb check as soon as we can
 998          * properly reconstruct framebuffers.
 999          *
1000          * FIXME: The intel_crtc->active here should be switched to
1001          * crtc->state->active once we have proper CRTC states wired up
1002          * for atomic.
1003          */
1004         return crtc->active && crtc->base.primary->state->fb &&
1005                 crtc->config->base.adjusted_mode.crtc_clock;
1006 }
1007
1008 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1009                                              enum pipe pipe)
1010 {
1011         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1012
1013         return crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1017                                     enum pipe pipe)
1018 {
1019         i915_reg_t reg = PIPEDSL(pipe);
1020         u32 line1, line2;
1021         u32 line_mask;
1022
1023         if (IS_GEN2(dev_priv))
1024                 line_mask = DSL_LINEMASK_GEN2;
1025         else
1026                 line_mask = DSL_LINEMASK_GEN3;
1027
1028         line1 = I915_READ(reg) & line_mask;
1029         msleep(5);
1030         line2 = I915_READ(reg) & line_mask;
1031
1032         return line1 != line2;
1033 }
1034
1035 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1038         enum pipe pipe = crtc->pipe;
1039
1040         /* Wait for the display line to settle/start moving */
1041         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1042                 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1043                           pipe_name(pipe), onoff(state));
1044 }
1045
1046 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1047 {
1048         wait_for_pipe_scanline_moving(crtc, false);
1049 }
1050
1051 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1052 {
1053         wait_for_pipe_scanline_moving(crtc, true);
1054 }
1055
1056 static void
1057 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1058 {
1059         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1060         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1061
1062         if (INTEL_GEN(dev_priv) >= 4) {
1063                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1064                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1065
1066                 /* Wait for the Pipe State to go off */
1067                 if (intel_wait_for_register(dev_priv,
1068                                             reg, I965_PIPECONF_ACTIVE, 0,
1069                                             100))
1070                         WARN(1, "pipe_off wait timed out\n");
1071         } else {
1072                 intel_wait_for_pipe_scanline_stopped(crtc);
1073         }
1074 }
1075
1076 /* Only for pre-ILK configs */
1077 void assert_pll(struct drm_i915_private *dev_priv,
1078                 enum pipe pipe, bool state)
1079 {
1080         u32 val;
1081         bool cur_state;
1082
1083         val = I915_READ(DPLL(pipe));
1084         cur_state = !!(val & DPLL_VCO_ENABLE);
1085         I915_STATE_WARN(cur_state != state,
1086              "PLL state assertion failure (expected %s, current %s)\n",
1087                         onoff(state), onoff(cur_state));
1088 }
1089
1090 /* XXX: the dsi pll is shared between MIPI DSI ports */
1091 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1092 {
1093         u32 val;
1094         bool cur_state;
1095
1096         mutex_lock(&dev_priv->sb_lock);
1097         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1098         mutex_unlock(&dev_priv->sb_lock);
1099
1100         cur_state = val & DSI_PLL_VCO_EN;
1101         I915_STATE_WARN(cur_state != state,
1102              "DSI PLL state assertion failure (expected %s, current %s)\n",
1103                         onoff(state), onoff(cur_state));
1104 }
1105
1106 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1107                           enum pipe pipe, bool state)
1108 {
1109         bool cur_state;
1110         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1111                                                                       pipe);
1112
1113         if (HAS_DDI(dev_priv)) {
1114                 /* DDI does not have a specific FDI_TX register */
1115                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1116                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1117         } else {
1118                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1119                 cur_state = !!(val & FDI_TX_ENABLE);
1120         }
1121         I915_STATE_WARN(cur_state != state,
1122              "FDI TX state assertion failure (expected %s, current %s)\n",
1123                         onoff(state), onoff(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         u32 val;
1132         bool cur_state;
1133
1134         val = I915_READ(FDI_RX_CTL(pipe));
1135         cur_state = !!(val & FDI_RX_ENABLE);
1136         I915_STATE_WARN(cur_state != state,
1137              "FDI RX state assertion failure (expected %s, current %s)\n",
1138                         onoff(state), onoff(cur_state));
1139 }
1140 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1141 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1142
1143 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1144                                       enum pipe pipe)
1145 {
1146         u32 val;
1147
1148         /* ILK FDI PLL is always enabled */
1149         if (IS_GEN5(dev_priv))
1150                 return;
1151
1152         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1153         if (HAS_DDI(dev_priv))
1154                 return;
1155
1156         val = I915_READ(FDI_TX_CTL(pipe));
1157         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1158 }
1159
1160 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1161                        enum pipe pipe, bool state)
1162 {
1163         u32 val;
1164         bool cur_state;
1165
1166         val = I915_READ(FDI_RX_CTL(pipe));
1167         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1168         I915_STATE_WARN(cur_state != state,
1169              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1170                         onoff(state), onoff(cur_state));
1171 }
1172
1173 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1174 {
1175         i915_reg_t pp_reg;
1176         u32 val;
1177         enum pipe panel_pipe = PIPE_A;
1178         bool locked = true;
1179
1180         if (WARN_ON(HAS_DDI(dev_priv)))
1181                 return;
1182
1183         if (HAS_PCH_SPLIT(dev_priv)) {
1184                 u32 port_sel;
1185
1186                 pp_reg = PP_CONTROL(0);
1187                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1188
1189                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1190                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1191                         panel_pipe = PIPE_B;
1192                 /* XXX: else fix for eDP */
1193         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1194                 /* presumably write lock depends on pipe, not port select */
1195                 pp_reg = PP_CONTROL(pipe);
1196                 panel_pipe = pipe;
1197         } else {
1198                 pp_reg = PP_CONTROL(0);
1199                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1200                         panel_pipe = PIPE_B;
1201         }
1202
1203         val = I915_READ(pp_reg);
1204         if (!(val & PANEL_POWER_ON) ||
1205             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1206                 locked = false;
1207
1208         I915_STATE_WARN(panel_pipe == pipe && locked,
1209              "panel assertion failure, pipe %c regs locked\n",
1210              pipe_name(pipe));
1211 }
1212
1213 void assert_pipe(struct drm_i915_private *dev_priv,
1214                  enum pipe pipe, bool state)
1215 {
1216         bool cur_state;
1217         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218                                                                       pipe);
1219         enum intel_display_power_domain power_domain;
1220
1221         /* we keep both pipes enabled on 830 */
1222         if (IS_I830(dev_priv))
1223                 state = true;
1224
1225         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1226         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1227                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1228                 cur_state = !!(val & PIPECONF_ENABLE);
1229
1230                 intel_display_power_put(dev_priv, power_domain);
1231         } else {
1232                 cur_state = false;
1233         }
1234
1235         I915_STATE_WARN(cur_state != state,
1236              "pipe %c assertion failure (expected %s, current %s)\n",
1237                         pipe_name(pipe), onoff(state), onoff(cur_state));
1238 }
1239
1240 static void assert_plane(struct intel_plane *plane, bool state)
1241 {
1242         bool cur_state = plane->get_hw_state(plane);
1243
1244         I915_STATE_WARN(cur_state != state,
1245                         "%s assertion failure (expected %s, current %s)\n",
1246                         plane->base.name, onoff(state), onoff(cur_state));
1247 }
1248
1249 #define assert_plane_enabled(p) assert_plane(p, true)
1250 #define assert_plane_disabled(p) assert_plane(p, false)
1251
1252 static void assert_planes_disabled(struct intel_crtc *crtc)
1253 {
1254         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1255         struct intel_plane *plane;
1256
1257         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1258                 assert_plane_disabled(plane);
1259 }
1260
1261 static void assert_vblank_disabled(struct drm_crtc *crtc)
1262 {
1263         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1264                 drm_crtc_vblank_put(crtc);
1265 }
1266
1267 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1268                                     enum pipe pipe)
1269 {
1270         u32 val;
1271         bool enabled;
1272
1273         val = I915_READ(PCH_TRANSCONF(pipe));
1274         enabled = !!(val & TRANS_ENABLE);
1275         I915_STATE_WARN(enabled,
1276              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1277              pipe_name(pipe));
1278 }
1279
1280 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1281                             enum pipe pipe, u32 port_sel, u32 val)
1282 {
1283         if ((val & DP_PORT_EN) == 0)
1284                 return false;
1285
1286         if (HAS_PCH_CPT(dev_priv)) {
1287                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1288                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1289                         return false;
1290         } else if (IS_CHERRYVIEW(dev_priv)) {
1291                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1292                         return false;
1293         } else {
1294                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1295                         return false;
1296         }
1297         return true;
1298 }
1299
1300 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1301                               enum pipe pipe, u32 val)
1302 {
1303         if ((val & SDVO_ENABLE) == 0)
1304                 return false;
1305
1306         if (HAS_PCH_CPT(dev_priv)) {
1307                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1308                         return false;
1309         } else if (IS_CHERRYVIEW(dev_priv)) {
1310                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1311                         return false;
1312         } else {
1313                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1314                         return false;
1315         }
1316         return true;
1317 }
1318
1319 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1320                               enum pipe pipe, u32 val)
1321 {
1322         if ((val & LVDS_PORT_EN) == 0)
1323                 return false;
1324
1325         if (HAS_PCH_CPT(dev_priv)) {
1326                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1327                         return false;
1328         } else {
1329                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1330                         return false;
1331         }
1332         return true;
1333 }
1334
1335 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1336                               enum pipe pipe, u32 val)
1337 {
1338         if ((val & ADPA_DAC_ENABLE) == 0)
1339                 return false;
1340         if (HAS_PCH_CPT(dev_priv)) {
1341                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1351                                    enum pipe pipe, i915_reg_t reg,
1352                                    u32 port_sel)
1353 {
1354         u32 val = I915_READ(reg);
1355         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1356              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1357              i915_mmio_reg_offset(reg), pipe_name(pipe));
1358
1359         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1360              && (val & DP_PIPEB_SELECT),
1361              "IBX PCH dp port still using transcoder B\n");
1362 }
1363
1364 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1365                                      enum pipe pipe, i915_reg_t reg)
1366 {
1367         u32 val = I915_READ(reg);
1368         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1369              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1370              i915_mmio_reg_offset(reg), pipe_name(pipe));
1371
1372         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1373              && (val & SDVO_PIPE_B_SELECT),
1374              "IBX PCH hdmi port still using transcoder B\n");
1375 }
1376
1377 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1378                                       enum pipe pipe)
1379 {
1380         u32 val;
1381
1382         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1383         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1384         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1385
1386         val = I915_READ(PCH_ADPA);
1387         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1388              "PCH VGA enabled on transcoder %c, should be disabled\n",
1389              pipe_name(pipe));
1390
1391         val = I915_READ(PCH_LVDS);
1392         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1393              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1394              pipe_name(pipe));
1395
1396         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1397         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1398         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1399 }
1400
1401 static void _vlv_enable_pll(struct intel_crtc *crtc,
1402                             const struct intel_crtc_state *pipe_config)
1403 {
1404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1405         enum pipe pipe = crtc->pipe;
1406
1407         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1408         POSTING_READ(DPLL(pipe));
1409         udelay(150);
1410
1411         if (intel_wait_for_register(dev_priv,
1412                                     DPLL(pipe),
1413                                     DPLL_LOCK_VLV,
1414                                     DPLL_LOCK_VLV,
1415                                     1))
1416                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1417 }
1418
1419 static void vlv_enable_pll(struct intel_crtc *crtc,
1420                            const struct intel_crtc_state *pipe_config)
1421 {
1422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1423         enum pipe pipe = crtc->pipe;
1424
1425         assert_pipe_disabled(dev_priv, pipe);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         assert_panel_unlocked(dev_priv, pipe);
1429
1430         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1431                 _vlv_enable_pll(crtc, pipe_config);
1432
1433         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1434         POSTING_READ(DPLL_MD(pipe));
1435 }
1436
1437
1438 static void _chv_enable_pll(struct intel_crtc *crtc,
1439                             const struct intel_crtc_state *pipe_config)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1442         enum pipe pipe = crtc->pipe;
1443         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1444         u32 tmp;
1445
1446         mutex_lock(&dev_priv->sb_lock);
1447
1448         /* Enable back the 10bit clock to display controller */
1449         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1450         tmp |= DPIO_DCLKP_EN;
1451         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1452
1453         mutex_unlock(&dev_priv->sb_lock);
1454
1455         /*
1456          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1457          */
1458         udelay(1);
1459
1460         /* Enable PLL */
1461         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1462
1463         /* Check PLL is locked */
1464         if (intel_wait_for_register(dev_priv,
1465                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1466                                     1))
1467                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void chv_enable_pll(struct intel_crtc *crtc,
1471                            const struct intel_crtc_state *pipe_config)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474         enum pipe pipe = crtc->pipe;
1475
1476         assert_pipe_disabled(dev_priv, pipe);
1477
1478         /* PLL is protected by panel, make sure we can write it */
1479         assert_panel_unlocked(dev_priv, pipe);
1480
1481         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482                 _chv_enable_pll(crtc, pipe_config);
1483
1484         if (pipe != PIPE_A) {
1485                 /*
1486                  * WaPixelRepeatModeFixForC0:chv
1487                  *
1488                  * DPLLCMD is AWOL. Use chicken bits to propagate
1489                  * the value from DPLLBMD to either pipe B or C.
1490                  */
1491                 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1492                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1493                 I915_WRITE(CBR4_VLV, 0);
1494                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1495
1496                 /*
1497                  * DPLLB VGA mode also seems to cause problems.
1498                  * We should always have it disabled.
1499                  */
1500                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1501         } else {
1502                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1503                 POSTING_READ(DPLL_MD(pipe));
1504         }
1505 }
1506
1507 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1508 {
1509         struct intel_crtc *crtc;
1510         int count = 0;
1511
1512         for_each_intel_crtc(&dev_priv->drm, crtc) {
1513                 count += crtc->base.state->active &&
1514                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1515         }
1516
1517         return count;
1518 }
1519
1520 static void i9xx_enable_pll(struct intel_crtc *crtc,
1521                             const struct intel_crtc_state *crtc_state)
1522 {
1523         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1524         i915_reg_t reg = DPLL(crtc->pipe);
1525         u32 dpll = crtc_state->dpll_hw_state.dpll;
1526         int i;
1527
1528         assert_pipe_disabled(dev_priv, crtc->pipe);
1529
1530         /* PLL is protected by panel, make sure we can write it */
1531         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1532                 assert_panel_unlocked(dev_priv, crtc->pipe);
1533
1534         /* Enable DVO 2x clock on both PLLs if necessary */
1535         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1536                 /*
1537                  * It appears to be important that we don't enable this
1538                  * for the current pipe before otherwise configuring the
1539                  * PLL. No idea how this should be handled if multiple
1540                  * DVO outputs are enabled simultaneosly.
1541                  */
1542                 dpll |= DPLL_DVO_2X_MODE;
1543                 I915_WRITE(DPLL(!crtc->pipe),
1544                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1545         }
1546
1547         /*
1548          * Apparently we need to have VGA mode enabled prior to changing
1549          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1550          * dividers, even though the register value does change.
1551          */
1552         I915_WRITE(reg, 0);
1553
1554         I915_WRITE(reg, dpll);
1555
1556         /* Wait for the clocks to stabilize. */
1557         POSTING_READ(reg);
1558         udelay(150);
1559
1560         if (INTEL_GEN(dev_priv) >= 4) {
1561                 I915_WRITE(DPLL_MD(crtc->pipe),
1562                            crtc_state->dpll_hw_state.dpll_md);
1563         } else {
1564                 /* The pixel multiplier can only be updated once the
1565                  * DPLL is enabled and the clocks are stable.
1566                  *
1567                  * So write it again.
1568                  */
1569                 I915_WRITE(reg, dpll);
1570         }
1571
1572         /* We do this three times for luck */
1573         for (i = 0; i < 3; i++) {
1574                 I915_WRITE(reg, dpll);
1575                 POSTING_READ(reg);
1576                 udelay(150); /* wait for warmup */
1577         }
1578 }
1579
1580 static void i9xx_disable_pll(struct intel_crtc *crtc)
1581 {
1582         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1583         enum pipe pipe = crtc->pipe;
1584
1585         /* Disable DVO 2x clock on both PLLs if necessary */
1586         if (IS_I830(dev_priv) &&
1587             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1588             !intel_num_dvo_pipes(dev_priv)) {
1589                 I915_WRITE(DPLL(PIPE_B),
1590                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1591                 I915_WRITE(DPLL(PIPE_A),
1592                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1593         }
1594
1595         /* Don't disable pipe or pipe PLLs if needed */
1596         if (IS_I830(dev_priv))
1597                 return;
1598
1599         /* Make sure the pipe isn't still relying on us */
1600         assert_pipe_disabled(dev_priv, pipe);
1601
1602         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1603         POSTING_READ(DPLL(pipe));
1604 }
1605
1606 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1607 {
1608         u32 val;
1609
1610         /* Make sure the pipe isn't still relying on us */
1611         assert_pipe_disabled(dev_priv, pipe);
1612
1613         val = DPLL_INTEGRATED_REF_CLK_VLV |
1614                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1615         if (pipe != PIPE_A)
1616                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1617
1618         I915_WRITE(DPLL(pipe), val);
1619         POSTING_READ(DPLL(pipe));
1620 }
1621
1622 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1623 {
1624         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1625         u32 val;
1626
1627         /* Make sure the pipe isn't still relying on us */
1628         assert_pipe_disabled(dev_priv, pipe);
1629
1630         val = DPLL_SSC_REF_CLK_CHV |
1631                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1632         if (pipe != PIPE_A)
1633                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1634
1635         I915_WRITE(DPLL(pipe), val);
1636         POSTING_READ(DPLL(pipe));
1637
1638         mutex_lock(&dev_priv->sb_lock);
1639
1640         /* Disable 10bit clock to display controller */
1641         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1642         val &= ~DPIO_DCLKP_EN;
1643         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1644
1645         mutex_unlock(&dev_priv->sb_lock);
1646 }
1647
1648 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1649                          struct intel_digital_port *dport,
1650                          unsigned int expected_mask)
1651 {
1652         u32 port_mask;
1653         i915_reg_t dpll_reg;
1654
1655         switch (dport->base.port) {
1656         case PORT_B:
1657                 port_mask = DPLL_PORTB_READY_MASK;
1658                 dpll_reg = DPLL(0);
1659                 break;
1660         case PORT_C:
1661                 port_mask = DPLL_PORTC_READY_MASK;
1662                 dpll_reg = DPLL(0);
1663                 expected_mask <<= 4;
1664                 break;
1665         case PORT_D:
1666                 port_mask = DPLL_PORTD_READY_MASK;
1667                 dpll_reg = DPIO_PHY_STATUS;
1668                 break;
1669         default:
1670                 BUG();
1671         }
1672
1673         if (intel_wait_for_register(dev_priv,
1674                                     dpll_reg, port_mask, expected_mask,
1675                                     1000))
1676                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1677                      port_name(dport->base.port),
1678                      I915_READ(dpll_reg) & port_mask, expected_mask);
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682                                            enum pipe pipe)
1683 {
1684         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1685                                                                 pipe);
1686         i915_reg_t reg;
1687         uint32_t val, pipeconf_val;
1688
1689         /* Make sure PCH DPLL is enabled */
1690         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1691
1692         /* FDI must be feeding us bits for PCH ports */
1693         assert_fdi_tx_enabled(dev_priv, pipe);
1694         assert_fdi_rx_enabled(dev_priv, pipe);
1695
1696         if (HAS_PCH_CPT(dev_priv)) {
1697                 /* Workaround: Set the timing override bit before enabling the
1698                  * pch transcoder. */
1699                 reg = TRANS_CHICKEN2(pipe);
1700                 val = I915_READ(reg);
1701                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1702                 I915_WRITE(reg, val);
1703         }
1704
1705         reg = PCH_TRANSCONF(pipe);
1706         val = I915_READ(reg);
1707         pipeconf_val = I915_READ(PIPECONF(pipe));
1708
1709         if (HAS_PCH_IBX(dev_priv)) {
1710                 /*
1711                  * Make the BPC in transcoder be consistent with
1712                  * that in pipeconf reg. For HDMI we must use 8bpc
1713                  * here for both 8bpc and 12bpc.
1714                  */
1715                 val &= ~PIPECONF_BPC_MASK;
1716                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1717                         val |= PIPECONF_8BPC;
1718                 else
1719                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1720         }
1721
1722         val &= ~TRANS_INTERLACE_MASK;
1723         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724                 if (HAS_PCH_IBX(dev_priv) &&
1725                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1726                         val |= TRANS_LEGACY_INTERLACED_ILK;
1727                 else
1728                         val |= TRANS_INTERLACED;
1729         else
1730                 val |= TRANS_PROGRESSIVE;
1731
1732         I915_WRITE(reg, val | TRANS_ENABLE);
1733         if (intel_wait_for_register(dev_priv,
1734                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1735                                     100))
1736                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1737 }
1738
1739 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740                                       enum transcoder cpu_transcoder)
1741 {
1742         u32 val, pipeconf_val;
1743
1744         /* FDI must be feeding us bits for PCH ports */
1745         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1746         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1747
1748         /* Workaround: set timing override bit. */
1749         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1750         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1751         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1752
1753         val = TRANS_ENABLE;
1754         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1755
1756         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1757             PIPECONF_INTERLACED_ILK)
1758                 val |= TRANS_INTERLACED;
1759         else
1760                 val |= TRANS_PROGRESSIVE;
1761
1762         I915_WRITE(LPT_TRANSCONF, val);
1763         if (intel_wait_for_register(dev_priv,
1764                                     LPT_TRANSCONF,
1765                                     TRANS_STATE_ENABLE,
1766                                     TRANS_STATE_ENABLE,
1767                                     100))
1768                 DRM_ERROR("Failed to enable PCH transcoder\n");
1769 }
1770
1771 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1772                                             enum pipe pipe)
1773 {
1774         i915_reg_t reg;
1775         uint32_t val;
1776
1777         /* FDI relies on the transcoder */
1778         assert_fdi_tx_disabled(dev_priv, pipe);
1779         assert_fdi_rx_disabled(dev_priv, pipe);
1780
1781         /* Ports must be off as well */
1782         assert_pch_ports_disabled(dev_priv, pipe);
1783
1784         reg = PCH_TRANSCONF(pipe);
1785         val = I915_READ(reg);
1786         val &= ~TRANS_ENABLE;
1787         I915_WRITE(reg, val);
1788         /* wait for PCH transcoder off, transcoder state */
1789         if (intel_wait_for_register(dev_priv,
1790                                     reg, TRANS_STATE_ENABLE, 0,
1791                                     50))
1792                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1793
1794         if (HAS_PCH_CPT(dev_priv)) {
1795                 /* Workaround: Clear the timing override chicken bit again. */
1796                 reg = TRANS_CHICKEN2(pipe);
1797                 val = I915_READ(reg);
1798                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1799                 I915_WRITE(reg, val);
1800         }
1801 }
1802
1803 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1804 {
1805         u32 val;
1806
1807         val = I915_READ(LPT_TRANSCONF);
1808         val &= ~TRANS_ENABLE;
1809         I915_WRITE(LPT_TRANSCONF, val);
1810         /* wait for PCH transcoder off, transcoder state */
1811         if (intel_wait_for_register(dev_priv,
1812                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1813                                     50))
1814                 DRM_ERROR("Failed to disable PCH transcoder\n");
1815
1816         /* Workaround: clear timing override bit. */
1817         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1818         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1819         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1820 }
1821
1822 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1823 {
1824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1825
1826         if (HAS_PCH_LPT(dev_priv))
1827                 return PIPE_A;
1828         else
1829                 return crtc->pipe;
1830 }
1831
1832 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1833 {
1834         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1836         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1837         enum pipe pipe = crtc->pipe;
1838         i915_reg_t reg;
1839         u32 val;
1840
1841         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1842
1843         assert_planes_disabled(crtc);
1844
1845         /*
1846          * A pipe without a PLL won't actually be able to drive bits from
1847          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1848          * need the check.
1849          */
1850         if (HAS_GMCH_DISPLAY(dev_priv)) {
1851                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1852                         assert_dsi_pll_enabled(dev_priv);
1853                 else
1854                         assert_pll_enabled(dev_priv, pipe);
1855         } else {
1856                 if (new_crtc_state->has_pch_encoder) {
1857                         /* if driving the PCH, we need FDI enabled */
1858                         assert_fdi_rx_pll_enabled(dev_priv,
1859                                                   intel_crtc_pch_transcoder(crtc));
1860                         assert_fdi_tx_pll_enabled(dev_priv,
1861                                                   (enum pipe) cpu_transcoder);
1862                 }
1863                 /* FIXME: assert CPU port conditions for SNB+ */
1864         }
1865
1866         reg = PIPECONF(cpu_transcoder);
1867         val = I915_READ(reg);
1868         if (val & PIPECONF_ENABLE) {
1869                 /* we keep both pipes enabled on 830 */
1870                 WARN_ON(!IS_I830(dev_priv));
1871                 return;
1872         }
1873
1874         I915_WRITE(reg, val | PIPECONF_ENABLE);
1875         POSTING_READ(reg);
1876
1877         /*
1878          * Until the pipe starts PIPEDSL reads will return a stale value,
1879          * which causes an apparent vblank timestamp jump when PIPEDSL
1880          * resets to its proper value. That also messes up the frame count
1881          * when it's derived from the timestamps. So let's wait for the
1882          * pipe to start properly before we call drm_crtc_vblank_on()
1883          */
1884         if (dev_priv->drm.max_vblank_count == 0)
1885                 intel_wait_for_pipe_scanline_moving(crtc);
1886 }
1887
1888 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1889 {
1890         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1891         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1892         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1893         enum pipe pipe = crtc->pipe;
1894         i915_reg_t reg;
1895         u32 val;
1896
1897         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1898
1899         /*
1900          * Make sure planes won't keep trying to pump pixels to us,
1901          * or we might hang the display.
1902          */
1903         assert_planes_disabled(crtc);
1904
1905         reg = PIPECONF(cpu_transcoder);
1906         val = I915_READ(reg);
1907         if ((val & PIPECONF_ENABLE) == 0)
1908                 return;
1909
1910         /*
1911          * Double wide has implications for planes
1912          * so best keep it disabled when not needed.
1913          */
1914         if (old_crtc_state->double_wide)
1915                 val &= ~PIPECONF_DOUBLE_WIDE;
1916
1917         /* Don't disable pipe or pipe PLLs if needed */
1918         if (!IS_I830(dev_priv))
1919                 val &= ~PIPECONF_ENABLE;
1920
1921         I915_WRITE(reg, val);
1922         if ((val & PIPECONF_ENABLE) == 0)
1923                 intel_wait_for_pipe_off(old_crtc_state);
1924 }
1925
1926 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1927 {
1928         return IS_GEN2(dev_priv) ? 2048 : 4096;
1929 }
1930
1931 static unsigned int
1932 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1933 {
1934         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1935         unsigned int cpp = fb->format->cpp[plane];
1936
1937         switch (fb->modifier) {
1938         case DRM_FORMAT_MOD_LINEAR:
1939                 return cpp;
1940         case I915_FORMAT_MOD_X_TILED:
1941                 if (IS_GEN2(dev_priv))
1942                         return 128;
1943                 else
1944                         return 512;
1945         case I915_FORMAT_MOD_Y_TILED_CCS:
1946                 if (plane == 1)
1947                         return 128;
1948                 /* fall through */
1949         case I915_FORMAT_MOD_Y_TILED:
1950                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
1951                         return 128;
1952                 else
1953                         return 512;
1954         case I915_FORMAT_MOD_Yf_TILED_CCS:
1955                 if (plane == 1)
1956                         return 128;
1957                 /* fall through */
1958         case I915_FORMAT_MOD_Yf_TILED:
1959                 switch (cpp) {
1960                 case 1:
1961                         return 64;
1962                 case 2:
1963                 case 4:
1964                         return 128;
1965                 case 8:
1966                 case 16:
1967                         return 256;
1968                 default:
1969                         MISSING_CASE(cpp);
1970                         return cpp;
1971                 }
1972                 break;
1973         default:
1974                 MISSING_CASE(fb->modifier);
1975                 return cpp;
1976         }
1977 }
1978
1979 static unsigned int
1980 intel_tile_height(const struct drm_framebuffer *fb, int plane)
1981 {
1982         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1983                 return 1;
1984         else
1985                 return intel_tile_size(to_i915(fb->dev)) /
1986                         intel_tile_width_bytes(fb, plane);
1987 }
1988
1989 /* Return the tile dimensions in pixel units */
1990 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
1991                             unsigned int *tile_width,
1992                             unsigned int *tile_height)
1993 {
1994         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
1995         unsigned int cpp = fb->format->cpp[plane];
1996
1997         *tile_width = tile_width_bytes / cpp;
1998         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1999 }
2000
2001 unsigned int
2002 intel_fb_align_height(const struct drm_framebuffer *fb,
2003                       int plane, unsigned int height)
2004 {
2005         unsigned int tile_height = intel_tile_height(fb, plane);
2006
2007         return ALIGN(height, tile_height);
2008 }
2009
2010 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2011 {
2012         unsigned int size = 0;
2013         int i;
2014
2015         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2016                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2017
2018         return size;
2019 }
2020
2021 static void
2022 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2023                         const struct drm_framebuffer *fb,
2024                         unsigned int rotation)
2025 {
2026         view->type = I915_GGTT_VIEW_NORMAL;
2027         if (drm_rotation_90_or_270(rotation)) {
2028                 view->type = I915_GGTT_VIEW_ROTATED;
2029                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2030         }
2031 }
2032
2033 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2034 {
2035         if (IS_I830(dev_priv))
2036                 return 16 * 1024;
2037         else if (IS_I85X(dev_priv))
2038                 return 256;
2039         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2040                 return 32;
2041         else
2042                 return 4 * 1024;
2043 }
2044
2045 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2046 {
2047         if (INTEL_GEN(dev_priv) >= 9)
2048                 return 256 * 1024;
2049         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2050                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2051                 return 128 * 1024;
2052         else if (INTEL_GEN(dev_priv) >= 4)
2053                 return 4 * 1024;
2054         else
2055                 return 0;
2056 }
2057
2058 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2059                                          int plane)
2060 {
2061         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2062
2063         /* AUX_DIST needs only 4K alignment */
2064         if (plane == 1)
2065                 return 4096;
2066
2067         switch (fb->modifier) {
2068         case DRM_FORMAT_MOD_LINEAR:
2069                 return intel_linear_alignment(dev_priv);
2070         case I915_FORMAT_MOD_X_TILED:
2071                 if (INTEL_GEN(dev_priv) >= 9)
2072                         return 256 * 1024;
2073                 return 0;
2074         case I915_FORMAT_MOD_Y_TILED_CCS:
2075         case I915_FORMAT_MOD_Yf_TILED_CCS:
2076         case I915_FORMAT_MOD_Y_TILED:
2077         case I915_FORMAT_MOD_Yf_TILED:
2078                 return 1 * 1024 * 1024;
2079         default:
2080                 MISSING_CASE(fb->modifier);
2081                 return 0;
2082         }
2083 }
2084
2085 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2086 {
2087         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2088         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2089
2090         return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
2091 }
2092
2093 struct i915_vma *
2094 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2095                            unsigned int rotation,
2096                            bool uses_fence,
2097                            unsigned long *out_flags)
2098 {
2099         struct drm_device *dev = fb->dev;
2100         struct drm_i915_private *dev_priv = to_i915(dev);
2101         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2102         struct i915_ggtt_view view;
2103         struct i915_vma *vma;
2104         unsigned int pinctl;
2105         u32 alignment;
2106
2107         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2108
2109         alignment = intel_surf_alignment(fb, 0);
2110
2111         intel_fill_fb_ggtt_view(&view, fb, rotation);
2112
2113         /* Note that the w/a also requires 64 PTE of padding following the
2114          * bo. We currently fill all unused PTE with the shadow page and so
2115          * we should always have valid PTE following the scanout preventing
2116          * the VT-d warning.
2117          */
2118         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2119                 alignment = 256 * 1024;
2120
2121         /*
2122          * Global gtt pte registers are special registers which actually forward
2123          * writes to a chunk of system memory. Which means that there is no risk
2124          * that the register values disappear as soon as we call
2125          * intel_runtime_pm_put(), so it is correct to wrap only the
2126          * pin/unpin/fence and not more.
2127          */
2128         intel_runtime_pm_get(dev_priv);
2129
2130         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2131
2132         pinctl = 0;
2133
2134         /* Valleyview is definitely limited to scanning out the first
2135          * 512MiB. Lets presume this behaviour was inherited from the
2136          * g4x display engine and that all earlier gen are similarly
2137          * limited. Testing suggests that it is a little more
2138          * complicated than this. For example, Cherryview appears quite
2139          * happy to scanout from anywhere within its global aperture.
2140          */
2141         if (HAS_GMCH_DISPLAY(dev_priv))
2142                 pinctl |= PIN_MAPPABLE;
2143
2144         vma = i915_gem_object_pin_to_display_plane(obj,
2145                                                    alignment, &view, pinctl);
2146         if (IS_ERR(vma))
2147                 goto err;
2148
2149         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2150                 int ret;
2151
2152                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2153                  * fence, whereas 965+ only requires a fence if using
2154                  * framebuffer compression.  For simplicity, we always, when
2155                  * possible, install a fence as the cost is not that onerous.
2156                  *
2157                  * If we fail to fence the tiled scanout, then either the
2158                  * modeset will reject the change (which is highly unlikely as
2159                  * the affected systems, all but one, do not have unmappable
2160                  * space) or we will not be able to enable full powersaving
2161                  * techniques (also likely not to apply due to various limits
2162                  * FBC and the like impose on the size of the buffer, which
2163                  * presumably we violated anyway with this unmappable buffer).
2164                  * Anyway, it is presumably better to stumble onwards with
2165                  * something and try to run the system in a "less than optimal"
2166                  * mode that matches the user configuration.
2167                  */
2168                 ret = i915_vma_pin_fence(vma);
2169                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2170                         i915_gem_object_unpin_from_display_plane(vma);
2171                         vma = ERR_PTR(ret);
2172                         goto err;
2173                 }
2174
2175                 if (ret == 0 && vma->fence)
2176                         *out_flags |= PLANE_HAS_FENCE;
2177         }
2178
2179         i915_vma_get(vma);
2180 err:
2181         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2182
2183         intel_runtime_pm_put(dev_priv);
2184         return vma;
2185 }
2186
2187 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2188 {
2189         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2190
2191         if (flags & PLANE_HAS_FENCE)
2192                 i915_vma_unpin_fence(vma);
2193         i915_gem_object_unpin_from_display_plane(vma);
2194         i915_vma_put(vma);
2195 }
2196
2197 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2198                           unsigned int rotation)
2199 {
2200         if (drm_rotation_90_or_270(rotation))
2201                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2202         else
2203                 return fb->pitches[plane];
2204 }
2205
2206 /*
2207  * Convert the x/y offsets into a linear offset.
2208  * Only valid with 0/180 degree rotation, which is fine since linear
2209  * offset is only used with linear buffers on pre-hsw and tiled buffers
2210  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2211  */
2212 u32 intel_fb_xy_to_linear(int x, int y,
2213                           const struct intel_plane_state *state,
2214                           int plane)
2215 {
2216         const struct drm_framebuffer *fb = state->base.fb;
2217         unsigned int cpp = fb->format->cpp[plane];
2218         unsigned int pitch = fb->pitches[plane];
2219
2220         return y * pitch + x * cpp;
2221 }
2222
2223 /*
2224  * Add the x/y offsets derived from fb->offsets[] to the user
2225  * specified plane src x/y offsets. The resulting x/y offsets
2226  * specify the start of scanout from the beginning of the gtt mapping.
2227  */
2228 void intel_add_fb_offsets(int *x, int *y,
2229                           const struct intel_plane_state *state,
2230                           int plane)
2231
2232 {
2233         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2234         unsigned int rotation = state->base.rotation;
2235
2236         if (drm_rotation_90_or_270(rotation)) {
2237                 *x += intel_fb->rotated[plane].x;
2238                 *y += intel_fb->rotated[plane].y;
2239         } else {
2240                 *x += intel_fb->normal[plane].x;
2241                 *y += intel_fb->normal[plane].y;
2242         }
2243 }
2244
2245 static u32 __intel_adjust_tile_offset(int *x, int *y,
2246                                       unsigned int tile_width,
2247                                       unsigned int tile_height,
2248                                       unsigned int tile_size,
2249                                       unsigned int pitch_tiles,
2250                                       u32 old_offset,
2251                                       u32 new_offset)
2252 {
2253         unsigned int pitch_pixels = pitch_tiles * tile_width;
2254         unsigned int tiles;
2255
2256         WARN_ON(old_offset & (tile_size - 1));
2257         WARN_ON(new_offset & (tile_size - 1));
2258         WARN_ON(new_offset > old_offset);
2259
2260         tiles = (old_offset - new_offset) / tile_size;
2261
2262         *y += tiles / pitch_tiles * tile_height;
2263         *x += tiles % pitch_tiles * tile_width;
2264
2265         /* minimize x in case it got needlessly big */
2266         *y += *x / pitch_pixels * tile_height;
2267         *x %= pitch_pixels;
2268
2269         return new_offset;
2270 }
2271
2272 static u32 _intel_adjust_tile_offset(int *x, int *y,
2273                                      const struct drm_framebuffer *fb, int plane,
2274                                      unsigned int rotation,
2275                                      u32 old_offset, u32 new_offset)
2276 {
2277         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2278         unsigned int cpp = fb->format->cpp[plane];
2279         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2280
2281         WARN_ON(new_offset > old_offset);
2282
2283         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2284                 unsigned int tile_size, tile_width, tile_height;
2285                 unsigned int pitch_tiles;
2286
2287                 tile_size = intel_tile_size(dev_priv);
2288                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2289
2290                 if (drm_rotation_90_or_270(rotation)) {
2291                         pitch_tiles = pitch / tile_height;
2292                         swap(tile_width, tile_height);
2293                 } else {
2294                         pitch_tiles = pitch / (tile_width * cpp);
2295                 }
2296
2297                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2298                                            tile_size, pitch_tiles,
2299                                            old_offset, new_offset);
2300         } else {
2301                 old_offset += *y * pitch + *x * cpp;
2302
2303                 *y = (old_offset - new_offset) / pitch;
2304                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2305         }
2306
2307         return new_offset;
2308 }
2309
2310 /*
2311  * Adjust the tile offset by moving the difference into
2312  * the x/y offsets.
2313  */
2314 static u32 intel_adjust_tile_offset(int *x, int *y,
2315                                     const struct intel_plane_state *state, int plane,
2316                                     u32 old_offset, u32 new_offset)
2317 {
2318         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2319                                          state->base.rotation,
2320                                          old_offset, new_offset);
2321 }
2322
2323 /*
2324  * Computes the linear offset to the base tile and adjusts
2325  * x, y. bytes per pixel is assumed to be a power-of-two.
2326  *
2327  * In the 90/270 rotated case, x and y are assumed
2328  * to be already rotated to match the rotated GTT view, and
2329  * pitch is the tile_height aligned framebuffer height.
2330  *
2331  * This function is used when computing the derived information
2332  * under intel_framebuffer, so using any of that information
2333  * here is not allowed. Anything under drm_framebuffer can be
2334  * used. This is why the user has to pass in the pitch since it
2335  * is specified in the rotated orientation.
2336  */
2337 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2338                                       int *x, int *y,
2339                                       const struct drm_framebuffer *fb, int plane,
2340                                       unsigned int pitch,
2341                                       unsigned int rotation,
2342                                       u32 alignment)
2343 {
2344         uint64_t fb_modifier = fb->modifier;
2345         unsigned int cpp = fb->format->cpp[plane];
2346         u32 offset, offset_aligned;
2347
2348         if (alignment)
2349                 alignment--;
2350
2351         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2352                 unsigned int tile_size, tile_width, tile_height;
2353                 unsigned int tile_rows, tiles, pitch_tiles;
2354
2355                 tile_size = intel_tile_size(dev_priv);
2356                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2357
2358                 if (drm_rotation_90_or_270(rotation)) {
2359                         pitch_tiles = pitch / tile_height;
2360                         swap(tile_width, tile_height);
2361                 } else {
2362                         pitch_tiles = pitch / (tile_width * cpp);
2363                 }
2364
2365                 tile_rows = *y / tile_height;
2366                 *y %= tile_height;
2367
2368                 tiles = *x / tile_width;
2369                 *x %= tile_width;
2370
2371                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2372                 offset_aligned = offset & ~alignment;
2373
2374                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2375                                            tile_size, pitch_tiles,
2376                                            offset, offset_aligned);
2377         } else {
2378                 offset = *y * pitch + *x * cpp;
2379                 offset_aligned = offset & ~alignment;
2380
2381                 *y = (offset & alignment) / pitch;
2382                 *x = ((offset & alignment) - *y * pitch) / cpp;
2383         }
2384
2385         return offset_aligned;
2386 }
2387
2388 u32 intel_compute_tile_offset(int *x, int *y,
2389                               const struct intel_plane_state *state,
2390                               int plane)
2391 {
2392         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2393         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2394         const struct drm_framebuffer *fb = state->base.fb;
2395         unsigned int rotation = state->base.rotation;
2396         int pitch = intel_fb_pitch(fb, plane, rotation);
2397         u32 alignment;
2398
2399         if (intel_plane->id == PLANE_CURSOR)
2400                 alignment = intel_cursor_alignment(dev_priv);
2401         else
2402                 alignment = intel_surf_alignment(fb, plane);
2403
2404         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2405                                           rotation, alignment);
2406 }
2407
2408 /* Convert the fb->offset[] into x/y offsets */
2409 static int intel_fb_offset_to_xy(int *x, int *y,
2410                                  const struct drm_framebuffer *fb, int plane)
2411 {
2412         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2413
2414         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2415             fb->offsets[plane] % intel_tile_size(dev_priv))
2416                 return -EINVAL;
2417
2418         *x = 0;
2419         *y = 0;
2420
2421         _intel_adjust_tile_offset(x, y,
2422                                   fb, plane, DRM_MODE_ROTATE_0,
2423                                   fb->offsets[plane], 0);
2424
2425         return 0;
2426 }
2427
2428 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2429 {
2430         switch (fb_modifier) {
2431         case I915_FORMAT_MOD_X_TILED:
2432                 return I915_TILING_X;
2433         case I915_FORMAT_MOD_Y_TILED:
2434         case I915_FORMAT_MOD_Y_TILED_CCS:
2435                 return I915_TILING_Y;
2436         default:
2437                 return I915_TILING_NONE;
2438         }
2439 }
2440
2441 /*
2442  * From the Sky Lake PRM:
2443  * "The Color Control Surface (CCS) contains the compression status of
2444  *  the cache-line pairs. The compression state of the cache-line pair
2445  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2446  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2447  *  cache-line-pairs. CCS is always Y tiled."
2448  *
2449  * Since cache line pairs refers to horizontally adjacent cache lines,
2450  * each cache line in the CCS corresponds to an area of 32x16 cache
2451  * lines on the main surface. Since each pixel is 4 bytes, this gives
2452  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2453  * main surface.
2454  */
2455 static const struct drm_format_info ccs_formats[] = {
2456         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2457         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2458         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2459         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2460 };
2461
2462 static const struct drm_format_info *
2463 lookup_format_info(const struct drm_format_info formats[],
2464                    int num_formats, u32 format)
2465 {
2466         int i;
2467
2468         for (i = 0; i < num_formats; i++) {
2469                 if (formats[i].format == format)
2470                         return &formats[i];
2471         }
2472
2473         return NULL;
2474 }
2475
2476 static const struct drm_format_info *
2477 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2478 {
2479         switch (cmd->modifier[0]) {
2480         case I915_FORMAT_MOD_Y_TILED_CCS:
2481         case I915_FORMAT_MOD_Yf_TILED_CCS:
2482                 return lookup_format_info(ccs_formats,
2483                                           ARRAY_SIZE(ccs_formats),
2484                                           cmd->pixel_format);
2485         default:
2486                 return NULL;
2487         }
2488 }
2489
2490 static int
2491 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2492                    struct drm_framebuffer *fb)
2493 {
2494         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2495         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2496         u32 gtt_offset_rotated = 0;
2497         unsigned int max_size = 0;
2498         int i, num_planes = fb->format->num_planes;
2499         unsigned int tile_size = intel_tile_size(dev_priv);
2500
2501         for (i = 0; i < num_planes; i++) {
2502                 unsigned int width, height;
2503                 unsigned int cpp, size;
2504                 u32 offset;
2505                 int x, y;
2506                 int ret;
2507
2508                 cpp = fb->format->cpp[i];
2509                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2510                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2511
2512                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2513                 if (ret) {
2514                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2515                                       i, fb->offsets[i]);
2516                         return ret;
2517                 }
2518
2519                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2520                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2521                         int hsub = fb->format->hsub;
2522                         int vsub = fb->format->vsub;
2523                         int tile_width, tile_height;
2524                         int main_x, main_y;
2525                         int ccs_x, ccs_y;
2526
2527                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2528                         tile_width *= hsub;
2529                         tile_height *= vsub;
2530
2531                         ccs_x = (x * hsub) % tile_width;
2532                         ccs_y = (y * vsub) % tile_height;
2533                         main_x = intel_fb->normal[0].x % tile_width;
2534                         main_y = intel_fb->normal[0].y % tile_height;
2535
2536                         /*
2537                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2538                          * x/y offsets must match between CCS and the main surface.
2539                          */
2540                         if (main_x != ccs_x || main_y != ccs_y) {
2541                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2542                                               main_x, main_y,
2543                                               ccs_x, ccs_y,
2544                                               intel_fb->normal[0].x,
2545                                               intel_fb->normal[0].y,
2546                                               x, y);
2547                                 return -EINVAL;
2548                         }
2549                 }
2550
2551                 /*
2552                  * The fence (if used) is aligned to the start of the object
2553                  * so having the framebuffer wrap around across the edge of the
2554                  * fenced region doesn't really work. We have no API to configure
2555                  * the fence start offset within the object (nor could we probably
2556                  * on gen2/3). So it's just easier if we just require that the
2557                  * fb layout agrees with the fence layout. We already check that the
2558                  * fb stride matches the fence stride elsewhere.
2559                  */
2560                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2561                     (x + width) * cpp > fb->pitches[i]) {
2562                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2563                                       i, fb->offsets[i]);
2564                         return -EINVAL;
2565                 }
2566
2567                 /*
2568                  * First pixel of the framebuffer from
2569                  * the start of the normal gtt mapping.
2570                  */
2571                 intel_fb->normal[i].x = x;
2572                 intel_fb->normal[i].y = y;
2573
2574                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2575                                                     fb, i, fb->pitches[i],
2576                                                     DRM_MODE_ROTATE_0, tile_size);
2577                 offset /= tile_size;
2578
2579                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2580                         unsigned int tile_width, tile_height;
2581                         unsigned int pitch_tiles;
2582                         struct drm_rect r;
2583
2584                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2585
2586                         rot_info->plane[i].offset = offset;
2587                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2588                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2589                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2590
2591                         intel_fb->rotated[i].pitch =
2592                                 rot_info->plane[i].height * tile_height;
2593
2594                         /* how many tiles does this plane need */
2595                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2596                         /*
2597                          * If the plane isn't horizontally tile aligned,
2598                          * we need one more tile.
2599                          */
2600                         if (x != 0)
2601                                 size++;
2602
2603                         /* rotate the x/y offsets to match the GTT view */
2604                         r.x1 = x;
2605                         r.y1 = y;
2606                         r.x2 = x + width;
2607                         r.y2 = y + height;
2608                         drm_rect_rotate(&r,
2609                                         rot_info->plane[i].width * tile_width,
2610                                         rot_info->plane[i].height * tile_height,
2611                                         DRM_MODE_ROTATE_270);
2612                         x = r.x1;
2613                         y = r.y1;
2614
2615                         /* rotate the tile dimensions to match the GTT view */
2616                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2617                         swap(tile_width, tile_height);
2618
2619                         /*
2620                          * We only keep the x/y offsets, so push all of the
2621                          * gtt offset into the x/y offsets.
2622                          */
2623                         __intel_adjust_tile_offset(&x, &y,
2624                                                    tile_width, tile_height,
2625                                                    tile_size, pitch_tiles,
2626                                                    gtt_offset_rotated * tile_size, 0);
2627
2628                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2629
2630                         /*
2631                          * First pixel of the framebuffer from
2632                          * the start of the rotated gtt mapping.
2633                          */
2634                         intel_fb->rotated[i].x = x;
2635                         intel_fb->rotated[i].y = y;
2636                 } else {
2637                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2638                                             x * cpp, tile_size);
2639                 }
2640
2641                 /* how many tiles in total needed in the bo */
2642                 max_size = max(max_size, offset + size);
2643         }
2644
2645         if (max_size * tile_size > intel_fb->obj->base.size) {
2646                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2647                               max_size * tile_size, intel_fb->obj->base.size);
2648                 return -EINVAL;
2649         }
2650
2651         return 0;
2652 }
2653
2654 static int i9xx_format_to_fourcc(int format)
2655 {
2656         switch (format) {
2657         case DISPPLANE_8BPP:
2658                 return DRM_FORMAT_C8;
2659         case DISPPLANE_BGRX555:
2660                 return DRM_FORMAT_XRGB1555;
2661         case DISPPLANE_BGRX565:
2662                 return DRM_FORMAT_RGB565;
2663         default:
2664         case DISPPLANE_BGRX888:
2665                 return DRM_FORMAT_XRGB8888;
2666         case DISPPLANE_RGBX888:
2667                 return DRM_FORMAT_XBGR8888;
2668         case DISPPLANE_BGRX101010:
2669                 return DRM_FORMAT_XRGB2101010;
2670         case DISPPLANE_RGBX101010:
2671                 return DRM_FORMAT_XBGR2101010;
2672         }
2673 }
2674
2675 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2676 {
2677         switch (format) {
2678         case PLANE_CTL_FORMAT_RGB_565:
2679                 return DRM_FORMAT_RGB565;
2680         case PLANE_CTL_FORMAT_NV12:
2681                 return DRM_FORMAT_NV12;
2682         default:
2683         case PLANE_CTL_FORMAT_XRGB_8888:
2684                 if (rgb_order) {
2685                         if (alpha)
2686                                 return DRM_FORMAT_ABGR8888;
2687                         else
2688                                 return DRM_FORMAT_XBGR8888;
2689                 } else {
2690                         if (alpha)
2691                                 return DRM_FORMAT_ARGB8888;
2692                         else
2693                                 return DRM_FORMAT_XRGB8888;
2694                 }
2695         case PLANE_CTL_FORMAT_XRGB_2101010:
2696                 if (rgb_order)
2697                         return DRM_FORMAT_XBGR2101010;
2698                 else
2699                         return DRM_FORMAT_XRGB2101010;
2700         }
2701 }
2702
2703 static bool
2704 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2705                               struct intel_initial_plane_config *plane_config)
2706 {
2707         struct drm_device *dev = crtc->base.dev;
2708         struct drm_i915_private *dev_priv = to_i915(dev);
2709         struct drm_i915_gem_object *obj = NULL;
2710         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2711         struct drm_framebuffer *fb = &plane_config->fb->base;
2712         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2713         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2714                                     PAGE_SIZE);
2715
2716         size_aligned -= base_aligned;
2717
2718         if (plane_config->size == 0)
2719                 return false;
2720
2721         /* If the FB is too big, just don't use it since fbdev is not very
2722          * important and we should probably use that space with FBC or other
2723          * features. */
2724         if (size_aligned * 2 > dev_priv->stolen_usable_size)
2725                 return false;
2726
2727         mutex_lock(&dev->struct_mutex);
2728         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2729                                                              base_aligned,
2730                                                              base_aligned,
2731                                                              size_aligned);
2732         mutex_unlock(&dev->struct_mutex);
2733         if (!obj)
2734                 return false;
2735
2736         if (plane_config->tiling == I915_TILING_X)
2737                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2738
2739         mode_cmd.pixel_format = fb->format->format;
2740         mode_cmd.width = fb->width;
2741         mode_cmd.height = fb->height;
2742         mode_cmd.pitches[0] = fb->pitches[0];
2743         mode_cmd.modifier[0] = fb->modifier;
2744         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2745
2746         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2747                 DRM_DEBUG_KMS("intel fb init failed\n");
2748                 goto out_unref_obj;
2749         }
2750
2751
2752         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2753         return true;
2754
2755 out_unref_obj:
2756         i915_gem_object_put(obj);
2757         return false;
2758 }
2759
2760 static void
2761 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2762                         struct intel_plane_state *plane_state,
2763                         bool visible)
2764 {
2765         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2766
2767         plane_state->base.visible = visible;
2768
2769         /* FIXME pre-g4x don't work like this */
2770         if (visible) {
2771                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2772                 crtc_state->active_planes |= BIT(plane->id);
2773         } else {
2774                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2775                 crtc_state->active_planes &= ~BIT(plane->id);
2776         }
2777
2778         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2779                       crtc_state->base.crtc->name,
2780                       crtc_state->active_planes);
2781 }
2782
2783 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
2784                                          struct intel_plane *plane)
2785 {
2786         struct intel_crtc_state *crtc_state =
2787                 to_intel_crtc_state(crtc->base.state);
2788         struct intel_plane_state *plane_state =
2789                 to_intel_plane_state(plane->base.state);
2790
2791         intel_set_plane_visible(crtc_state, plane_state, false);
2792
2793         if (plane->id == PLANE_PRIMARY)
2794                 intel_pre_disable_primary_noatomic(&crtc->base);
2795
2796         trace_intel_disable_plane(&plane->base, crtc);
2797         plane->disable_plane(plane, crtc);
2798 }
2799
2800 static void
2801 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2802                              struct intel_initial_plane_config *plane_config)
2803 {
2804         struct drm_device *dev = intel_crtc->base.dev;
2805         struct drm_i915_private *dev_priv = to_i915(dev);
2806         struct drm_crtc *c;
2807         struct drm_i915_gem_object *obj;
2808         struct drm_plane *primary = intel_crtc->base.primary;
2809         struct drm_plane_state *plane_state = primary->state;
2810         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2811         struct intel_plane *intel_plane = to_intel_plane(primary);
2812         struct intel_plane_state *intel_state =
2813                 to_intel_plane_state(plane_state);
2814         struct drm_framebuffer *fb;
2815
2816         if (!plane_config->fb)
2817                 return;
2818
2819         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2820                 fb = &plane_config->fb->base;
2821                 goto valid_fb;
2822         }
2823
2824         kfree(plane_config->fb);
2825
2826         /*
2827          * Failed to alloc the obj, check to see if we should share
2828          * an fb with another CRTC instead
2829          */
2830         for_each_crtc(dev, c) {
2831                 struct intel_plane_state *state;
2832
2833                 if (c == &intel_crtc->base)
2834                         continue;
2835
2836                 if (!to_intel_crtc(c)->active)
2837                         continue;
2838
2839                 state = to_intel_plane_state(c->primary->state);
2840                 if (!state->vma)
2841                         continue;
2842
2843                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2844                         fb = state->base.fb;
2845                         drm_framebuffer_get(fb);
2846                         goto valid_fb;
2847                 }
2848         }
2849
2850         /*
2851          * We've failed to reconstruct the BIOS FB.  Current display state
2852          * indicates that the primary plane is visible, but has a NULL FB,
2853          * which will lead to problems later if we don't fix it up.  The
2854          * simplest solution is to just disable the primary plane now and
2855          * pretend the BIOS never had it enabled.
2856          */
2857         intel_plane_disable_noatomic(intel_crtc, intel_plane);
2858
2859         return;
2860
2861 valid_fb:
2862         mutex_lock(&dev->struct_mutex);
2863         intel_state->vma =
2864                 intel_pin_and_fence_fb_obj(fb,
2865                                            primary->state->rotation,
2866                                            intel_plane_uses_fence(intel_state),
2867                                            &intel_state->flags);
2868         mutex_unlock(&dev->struct_mutex);
2869         if (IS_ERR(intel_state->vma)) {
2870                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2871                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2872
2873                 intel_state->vma = NULL;
2874                 drm_framebuffer_put(fb);
2875                 return;
2876         }
2877
2878         obj = intel_fb_obj(fb);
2879         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
2880
2881         plane_state->src_x = 0;
2882         plane_state->src_y = 0;
2883         plane_state->src_w = fb->width << 16;
2884         plane_state->src_h = fb->height << 16;
2885
2886         plane_state->crtc_x = 0;
2887         plane_state->crtc_y = 0;
2888         plane_state->crtc_w = fb->width;
2889         plane_state->crtc_h = fb->height;
2890
2891         intel_state->base.src = drm_plane_state_src(plane_state);
2892         intel_state->base.dst = drm_plane_state_dest(plane_state);
2893
2894         if (i915_gem_object_is_tiled(obj))
2895                 dev_priv->preserve_bios_swizzle = true;
2896
2897         drm_framebuffer_get(fb);
2898         primary->fb = primary->state->fb = fb;
2899         primary->crtc = primary->state->crtc = &intel_crtc->base;
2900
2901         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2902                                 to_intel_plane_state(plane_state),
2903                                 true);
2904
2905         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2906                   &obj->frontbuffer_bits);
2907 }
2908
2909 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2910                                unsigned int rotation)
2911 {
2912         int cpp = fb->format->cpp[plane];
2913
2914         switch (fb->modifier) {
2915         case DRM_FORMAT_MOD_LINEAR:
2916         case I915_FORMAT_MOD_X_TILED:
2917                 switch (cpp) {
2918                 case 8:
2919                         return 4096;
2920                 case 4:
2921                 case 2:
2922                 case 1:
2923                         return 8192;
2924                 default:
2925                         MISSING_CASE(cpp);
2926                         break;
2927                 }
2928                 break;
2929         case I915_FORMAT_MOD_Y_TILED_CCS:
2930         case I915_FORMAT_MOD_Yf_TILED_CCS:
2931                 /* FIXME AUX plane? */
2932         case I915_FORMAT_MOD_Y_TILED:
2933         case I915_FORMAT_MOD_Yf_TILED:
2934                 switch (cpp) {
2935                 case 8:
2936                         return 2048;
2937                 case 4:
2938                         return 4096;
2939                 case 2:
2940                 case 1:
2941                         return 8192;
2942                 default:
2943                         MISSING_CASE(cpp);
2944                         break;
2945                 }
2946                 break;
2947         default:
2948                 MISSING_CASE(fb->modifier);
2949         }
2950
2951         return 2048;
2952 }
2953
2954 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2955                                            int main_x, int main_y, u32 main_offset)
2956 {
2957         const struct drm_framebuffer *fb = plane_state->base.fb;
2958         int hsub = fb->format->hsub;
2959         int vsub = fb->format->vsub;
2960         int aux_x = plane_state->aux.x;
2961         int aux_y = plane_state->aux.y;
2962         u32 aux_offset = plane_state->aux.offset;
2963         u32 alignment = intel_surf_alignment(fb, 1);
2964
2965         while (aux_offset >= main_offset && aux_y <= main_y) {
2966                 int x, y;
2967
2968                 if (aux_x == main_x && aux_y == main_y)
2969                         break;
2970
2971                 if (aux_offset == 0)
2972                         break;
2973
2974                 x = aux_x / hsub;
2975                 y = aux_y / vsub;
2976                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2977                                                       aux_offset, aux_offset - alignment);
2978                 aux_x = x * hsub + aux_x % hsub;
2979                 aux_y = y * vsub + aux_y % vsub;
2980         }
2981
2982         if (aux_x != main_x || aux_y != main_y)
2983                 return false;
2984
2985         plane_state->aux.offset = aux_offset;
2986         plane_state->aux.x = aux_x;
2987         plane_state->aux.y = aux_y;
2988
2989         return true;
2990 }
2991
2992 static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
2993                                   struct intel_plane_state *plane_state)
2994 {
2995         struct drm_i915_private *dev_priv =
2996                 to_i915(plane_state->base.plane->dev);
2997         const struct drm_framebuffer *fb = plane_state->base.fb;
2998         unsigned int rotation = plane_state->base.rotation;
2999         int x = plane_state->base.src.x1 >> 16;
3000         int y = plane_state->base.src.y1 >> 16;
3001         int w = drm_rect_width(&plane_state->base.src) >> 16;
3002         int h = drm_rect_height(&plane_state->base.src) >> 16;
3003         int dst_x = plane_state->base.dst.x1;
3004         int pipe_src_w = crtc_state->pipe_src_w;
3005         int max_width = skl_max_plane_width(fb, 0, rotation);
3006         int max_height = 4096;
3007         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3008
3009         if (w > max_width || h > max_height) {
3010                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3011                               w, h, max_width, max_height);
3012                 return -EINVAL;
3013         }
3014
3015         /*
3016          * Display WA #1175: cnl,glk
3017          * Planes other than the cursor may cause FIFO underflow and display
3018          * corruption if starting less than 4 pixels from the right edge of
3019          * the screen.
3020          * Besides the above WA fix the similar problem, where planes other
3021          * than the cursor ending less than 4 pixels from the left edge of the
3022          * screen may cause FIFO underflow and display corruption.
3023          */
3024         if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
3025             (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
3026                 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
3027                               dst_x + w < 4 ? "end" : "start",
3028                               dst_x + w < 4 ? dst_x + w : dst_x,
3029                               4, pipe_src_w - 4);
3030                 return -ERANGE;
3031         }
3032
3033         intel_add_fb_offsets(&x, &y, plane_state, 0);
3034         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3035         alignment = intel_surf_alignment(fb, 0);
3036
3037         /*
3038          * AUX surface offset is specified as the distance from the
3039          * main surface offset, and it must be non-negative. Make
3040          * sure that is what we will get.
3041          */
3042         if (offset > aux_offset)
3043                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3044                                                   offset, aux_offset & ~(alignment - 1));
3045
3046         /*
3047          * When using an X-tiled surface, the plane blows up
3048          * if the x offset + width exceed the stride.
3049          *
3050          * TODO: linear and Y-tiled seem fine, Yf untested,
3051          */
3052         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3053                 int cpp = fb->format->cpp[0];
3054
3055                 while ((x + w) * cpp > fb->pitches[0]) {
3056                         if (offset == 0) {
3057                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3058                                 return -EINVAL;
3059                         }
3060
3061                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3062                                                           offset, offset - alignment);
3063                 }
3064         }
3065
3066         /*
3067          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3068          * they match with the main surface x/y offsets.
3069          */
3070         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3071             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3072                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3073                         if (offset == 0)
3074                                 break;
3075
3076                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3077                                                           offset, offset - alignment);
3078                 }
3079
3080                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3081                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3082                         return -EINVAL;
3083                 }
3084         }
3085
3086         plane_state->main.offset = offset;
3087         plane_state->main.x = x;
3088         plane_state->main.y = y;
3089
3090         return 0;
3091 }
3092
3093 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3094 {
3095         const struct drm_framebuffer *fb = plane_state->base.fb;
3096         unsigned int rotation = plane_state->base.rotation;
3097         int max_width = skl_max_plane_width(fb, 1, rotation);
3098         int max_height = 4096;
3099         int x = plane_state->base.src.x1 >> 17;
3100         int y = plane_state->base.src.y1 >> 17;
3101         int w = drm_rect_width(&plane_state->base.src) >> 17;
3102         int h = drm_rect_height(&plane_state->base.src) >> 17;
3103         u32 offset;
3104
3105         intel_add_fb_offsets(&x, &y, plane_state, 1);
3106         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3107
3108         /* FIXME not quite sure how/if these apply to the chroma plane */
3109         if (w > max_width || h > max_height) {
3110                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3111                               w, h, max_width, max_height);
3112                 return -EINVAL;
3113         }
3114
3115         plane_state->aux.offset = offset;
3116         plane_state->aux.x = x;
3117         plane_state->aux.y = y;
3118
3119         return 0;
3120 }
3121
3122 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3123 {
3124         const struct drm_framebuffer *fb = plane_state->base.fb;
3125         int src_x = plane_state->base.src.x1 >> 16;
3126         int src_y = plane_state->base.src.y1 >> 16;
3127         int hsub = fb->format->hsub;
3128         int vsub = fb->format->vsub;
3129         int x = src_x / hsub;
3130         int y = src_y / vsub;
3131         u32 offset;
3132
3133         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3134                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3135                               plane_state->base.rotation);
3136                 return -EINVAL;
3137         }
3138
3139         intel_add_fb_offsets(&x, &y, plane_state, 1);
3140         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3141
3142         plane_state->aux.offset = offset;
3143         plane_state->aux.x = x * hsub + src_x % hsub;
3144         plane_state->aux.y = y * vsub + src_y % vsub;
3145
3146         return 0;
3147 }
3148
3149 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
3150                             struct intel_plane_state *plane_state)
3151 {
3152         const struct drm_framebuffer *fb = plane_state->base.fb;
3153         unsigned int rotation = plane_state->base.rotation;
3154         int ret;
3155
3156         if (rotation & DRM_MODE_REFLECT_X &&
3157             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
3158                 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
3159                 return -EINVAL;
3160         }
3161
3162         if (!plane_state->base.visible)
3163                 return 0;
3164
3165         /* Rotate src coordinates to match rotated GTT view */
3166         if (drm_rotation_90_or_270(rotation))
3167                 drm_rect_rotate(&plane_state->base.src,
3168                                 fb->width << 16, fb->height << 16,
3169                                 DRM_MODE_ROTATE_270);
3170
3171         /*
3172          * Handle the AUX surface first since
3173          * the main surface setup depends on it.
3174          */
3175         if (fb->format->format == DRM_FORMAT_NV12) {
3176                 ret = skl_check_nv12_aux_surface(plane_state);
3177                 if (ret)
3178                         return ret;
3179         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3180                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3181                 ret = skl_check_ccs_aux_surface(plane_state);
3182                 if (ret)
3183                         return ret;
3184         } else {
3185                 plane_state->aux.offset = ~0xfff;
3186                 plane_state->aux.x = 0;
3187                 plane_state->aux.y = 0;
3188         }
3189
3190         ret = skl_check_main_surface(crtc_state, plane_state);
3191         if (ret)
3192                 return ret;
3193
3194         return 0;
3195 }
3196
3197 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3198                           const struct intel_plane_state *plane_state)
3199 {
3200         struct drm_i915_private *dev_priv =
3201                 to_i915(plane_state->base.plane->dev);
3202         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203         const struct drm_framebuffer *fb = plane_state->base.fb;
3204         unsigned int rotation = plane_state->base.rotation;
3205         u32 dspcntr;
3206
3207         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3208
3209         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3210             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3211                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3212
3213         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3214                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3215
3216         if (INTEL_GEN(dev_priv) < 5)
3217                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3218
3219         switch (fb->format->format) {
3220         case DRM_FORMAT_C8:
3221                 dspcntr |= DISPPLANE_8BPP;
3222                 break;
3223         case DRM_FORMAT_XRGB1555:
3224                 dspcntr |= DISPPLANE_BGRX555;
3225                 break;
3226         case DRM_FORMAT_RGB565:
3227                 dspcntr |= DISPPLANE_BGRX565;
3228                 break;
3229         case DRM_FORMAT_XRGB8888:
3230                 dspcntr |= DISPPLANE_BGRX888;
3231                 break;
3232         case DRM_FORMAT_XBGR8888:
3233                 dspcntr |= DISPPLANE_RGBX888;
3234                 break;
3235         case DRM_FORMAT_XRGB2101010:
3236                 dspcntr |= DISPPLANE_BGRX101010;
3237                 break;
3238         case DRM_FORMAT_XBGR2101010:
3239                 dspcntr |= DISPPLANE_RGBX101010;
3240                 break;
3241         default:
3242                 MISSING_CASE(fb->format->format);
3243                 return 0;
3244         }
3245
3246         if (INTEL_GEN(dev_priv) >= 4 &&
3247             fb->modifier == I915_FORMAT_MOD_X_TILED)
3248                 dspcntr |= DISPPLANE_TILED;
3249
3250         if (rotation & DRM_MODE_ROTATE_180)
3251                 dspcntr |= DISPPLANE_ROTATE_180;
3252
3253         if (rotation & DRM_MODE_REFLECT_X)
3254                 dspcntr |= DISPPLANE_MIRROR;
3255
3256         return dspcntr;
3257 }
3258
3259 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3260 {
3261         struct drm_i915_private *dev_priv =
3262                 to_i915(plane_state->base.plane->dev);
3263         int src_x = plane_state->base.src.x1 >> 16;
3264         int src_y = plane_state->base.src.y1 >> 16;
3265         u32 offset;
3266
3267         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3268
3269         if (INTEL_GEN(dev_priv) >= 4)
3270                 offset = intel_compute_tile_offset(&src_x, &src_y,
3271                                                    plane_state, 0);
3272         else
3273                 offset = 0;
3274
3275         /* HSW/BDW do this automagically in hardware */
3276         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3277                 unsigned int rotation = plane_state->base.rotation;
3278                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3279                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3280
3281                 if (rotation & DRM_MODE_ROTATE_180) {
3282                         src_x += src_w - 1;
3283                         src_y += src_h - 1;
3284                 } else if (rotation & DRM_MODE_REFLECT_X) {
3285                         src_x += src_w - 1;
3286                 }
3287         }
3288
3289         plane_state->main.offset = offset;
3290         plane_state->main.x = src_x;
3291         plane_state->main.y = src_y;
3292
3293         return 0;
3294 }
3295
3296 static void i9xx_update_plane(struct intel_plane *plane,
3297                               const struct intel_crtc_state *crtc_state,
3298                               const struct intel_plane_state *plane_state)
3299 {
3300         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3301         const struct drm_framebuffer *fb = plane_state->base.fb;
3302         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3303         u32 linear_offset;
3304         u32 dspcntr = plane_state->ctl;
3305         i915_reg_t reg = DSPCNTR(i9xx_plane);
3306         int x = plane_state->main.x;
3307         int y = plane_state->main.y;
3308         unsigned long irqflags;
3309         u32 dspaddr_offset;
3310
3311         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3312
3313         if (INTEL_GEN(dev_priv) >= 4)
3314                 dspaddr_offset = plane_state->main.offset;
3315         else
3316                 dspaddr_offset = linear_offset;
3317
3318         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3319
3320         if (INTEL_GEN(dev_priv) < 4) {
3321                 /* pipesrc and dspsize control the size that is scaled from,
3322                  * which should always be the user's requested size.
3323                  */
3324                 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3325                               ((crtc_state->pipe_src_h - 1) << 16) |
3326                               (crtc_state->pipe_src_w - 1));
3327                 I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
3328         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3329                 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3330                               ((crtc_state->pipe_src_h - 1) << 16) |
3331                               (crtc_state->pipe_src_w - 1));
3332                 I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
3333                 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3334         }
3335
3336         I915_WRITE_FW(reg, dspcntr);
3337
3338         I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
3339         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3340                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3341                               intel_plane_ggtt_offset(plane_state) +
3342                               dspaddr_offset);
3343                 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3344         } else if (INTEL_GEN(dev_priv) >= 4) {
3345                 I915_WRITE_FW(DSPSURF(i9xx_plane),
3346                               intel_plane_ggtt_offset(plane_state) +
3347                               dspaddr_offset);
3348                 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3349                 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3350         } else {
3351                 I915_WRITE_FW(DSPADDR(i9xx_plane),
3352                               intel_plane_ggtt_offset(plane_state) +
3353                               dspaddr_offset);
3354         }
3355         POSTING_READ_FW(reg);
3356
3357         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3358 }
3359
3360 static void i9xx_disable_plane(struct intel_plane *plane,
3361                                struct intel_crtc *crtc)
3362 {
3363         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3364         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3365         unsigned long irqflags;
3366
3367         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3368
3369         I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
3370         if (INTEL_GEN(dev_priv) >= 4)
3371                 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3372         else
3373                 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3374         POSTING_READ_FW(DSPCNTR(i9xx_plane));
3375
3376         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3377 }
3378
3379 static bool i9xx_plane_get_hw_state(struct intel_plane *plane)
3380 {
3381         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3382         enum intel_display_power_domain power_domain;
3383         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3384         enum pipe pipe = plane->pipe;
3385         bool ret;
3386
3387         /*
3388          * Not 100% correct for planes that can move between pipes,
3389          * but that's only the case for gen2-4 which don't have any
3390          * display power wells.
3391          */
3392         power_domain = POWER_DOMAIN_PIPE(pipe);
3393         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3394                 return false;
3395
3396         ret = I915_READ(DSPCNTR(i9xx_plane)) & DISPLAY_PLANE_ENABLE;
3397
3398         intel_display_power_put(dev_priv, power_domain);
3399
3400         return ret;
3401 }
3402
3403 static u32
3404 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3405 {
3406         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3407                 return 64;
3408         else
3409                 return intel_tile_width_bytes(fb, plane);
3410 }
3411
3412 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3413 {
3414         struct drm_device *dev = intel_crtc->base.dev;
3415         struct drm_i915_private *dev_priv = to_i915(dev);
3416
3417         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3418         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3419         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3420 }
3421
3422 /*
3423  * This function detaches (aka. unbinds) unused scalers in hardware
3424  */
3425 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3426 {
3427         struct intel_crtc_scaler_state *scaler_state;
3428         int i;
3429
3430         scaler_state = &intel_crtc->config->scaler_state;
3431
3432         /* loop through and disable scalers that aren't in use */
3433         for (i = 0; i < intel_crtc->num_scalers; i++) {
3434                 if (!scaler_state->scalers[i].in_use)
3435                         skl_detach_scaler(intel_crtc, i);
3436         }
3437 }
3438
3439 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3440                      unsigned int rotation)
3441 {
3442         u32 stride;
3443
3444         if (plane >= fb->format->num_planes)
3445                 return 0;
3446
3447         stride = intel_fb_pitch(fb, plane, rotation);
3448
3449         /*
3450          * The stride is either expressed as a multiple of 64 bytes chunks for
3451          * linear buffers or in number of tiles for tiled buffers.
3452          */
3453         if (drm_rotation_90_or_270(rotation))
3454                 stride /= intel_tile_height(fb, plane);
3455         else
3456                 stride /= intel_fb_stride_alignment(fb, plane);
3457
3458         return stride;
3459 }
3460
3461 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3462 {
3463         switch (pixel_format) {
3464         case DRM_FORMAT_C8:
3465                 return PLANE_CTL_FORMAT_INDEXED;
3466         case DRM_FORMAT_RGB565:
3467                 return PLANE_CTL_FORMAT_RGB_565;
3468         case DRM_FORMAT_XBGR8888:
3469         case DRM_FORMAT_ABGR8888:
3470                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3471         case DRM_FORMAT_XRGB8888:
3472         case DRM_FORMAT_ARGB8888:
3473                 return PLANE_CTL_FORMAT_XRGB_8888;
3474         case DRM_FORMAT_XRGB2101010:
3475                 return PLANE_CTL_FORMAT_XRGB_2101010;
3476         case DRM_FORMAT_XBGR2101010:
3477                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3478         case DRM_FORMAT_YUYV:
3479                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3480         case DRM_FORMAT_YVYU:
3481                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3482         case DRM_FORMAT_UYVY:
3483                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3484         case DRM_FORMAT_VYUY:
3485                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3486         case DRM_FORMAT_NV12:
3487                 return PLANE_CTL_FORMAT_NV12;
3488         default:
3489                 MISSING_CASE(pixel_format);
3490         }
3491
3492         return 0;
3493 }
3494
3495 /*
3496  * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3497  * to be already pre-multiplied. We need to add a knob (or a different
3498  * DRM_FORMAT) for user-space to configure that.
3499  */
3500 static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
3501 {
3502         switch (pixel_format) {
3503         case DRM_FORMAT_ABGR8888:
3504         case DRM_FORMAT_ARGB8888:
3505                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3506         default:
3507                 return PLANE_CTL_ALPHA_DISABLE;
3508         }
3509 }
3510
3511 static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
3512 {
3513         switch (pixel_format) {
3514         case DRM_FORMAT_ABGR8888:
3515         case DRM_FORMAT_ARGB8888:
3516                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
3517         default:
3518                 return PLANE_COLOR_ALPHA_DISABLE;
3519         }
3520 }
3521
3522 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3523 {
3524         switch (fb_modifier) {
3525         case DRM_FORMAT_MOD_LINEAR:
3526                 break;
3527         case I915_FORMAT_MOD_X_TILED:
3528                 return PLANE_CTL_TILED_X;
3529         case I915_FORMAT_MOD_Y_TILED:
3530                 return PLANE_CTL_TILED_Y;
3531         case I915_FORMAT_MOD_Y_TILED_CCS:
3532                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3533         case I915_FORMAT_MOD_Yf_TILED:
3534                 return PLANE_CTL_TILED_YF;
3535         case I915_FORMAT_MOD_Yf_TILED_CCS:
3536                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3537         default:
3538                 MISSING_CASE(fb_modifier);
3539         }
3540
3541         return 0;
3542 }
3543
3544 static u32 skl_plane_ctl_rotate(unsigned int rotate)
3545 {
3546         switch (rotate) {
3547         case DRM_MODE_ROTATE_0:
3548                 break;
3549         /*
3550          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3551          * while i915 HW rotation is clockwise, thats why this swapping.
3552          */
3553         case DRM_MODE_ROTATE_90:
3554                 return PLANE_CTL_ROTATE_270;
3555         case DRM_MODE_ROTATE_180:
3556                 return PLANE_CTL_ROTATE_180;
3557         case DRM_MODE_ROTATE_270:
3558                 return PLANE_CTL_ROTATE_90;
3559         default:
3560                 MISSING_CASE(rotate);
3561         }
3562
3563         return 0;
3564 }
3565
3566 static u32 cnl_plane_ctl_flip(unsigned int reflect)
3567 {
3568         switch (reflect) {
3569         case 0:
3570                 break;
3571         case DRM_MODE_REFLECT_X:
3572                 return PLANE_CTL_FLIP_HORIZONTAL;
3573         case DRM_MODE_REFLECT_Y:
3574         default:
3575                 MISSING_CASE(reflect);
3576         }
3577
3578         return 0;
3579 }
3580
3581 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3582                   const struct intel_plane_state *plane_state)
3583 {
3584         struct drm_i915_private *dev_priv =
3585                 to_i915(plane_state->base.plane->dev);
3586         const struct drm_framebuffer *fb = plane_state->base.fb;
3587         unsigned int rotation = plane_state->base.rotation;
3588         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3589         u32 plane_ctl;
3590
3591         plane_ctl = PLANE_CTL_ENABLE;
3592
3593         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
3594                 plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
3595                 plane_ctl |=
3596                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3597                         PLANE_CTL_PIPE_CSC_ENABLE |
3598                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3599
3600                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3601                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
3602
3603                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3604                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
3605         }
3606
3607         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3608         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3609         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
3610
3611         if (INTEL_GEN(dev_priv) >= 10)
3612                 plane_ctl |= cnl_plane_ctl_flip(rotation &
3613                                                 DRM_MODE_REFLECT_MASK);
3614
3615         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3616                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3617         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3618                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3619
3620         return plane_ctl;
3621 }
3622
3623 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
3624                         const struct intel_plane_state *plane_state)
3625 {
3626         struct drm_i915_private *dev_priv =
3627                 to_i915(plane_state->base.plane->dev);
3628         const struct drm_framebuffer *fb = plane_state->base.fb;
3629         u32 plane_color_ctl = 0;
3630
3631         if (INTEL_GEN(dev_priv) < 11) {
3632                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
3633                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
3634         }
3635         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
3636         plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
3637
3638         if (intel_format_is_yuv(fb->format->format)) {
3639                 if (fb->format->format == DRM_FORMAT_NV12) {
3640                         plane_color_ctl |=
3641                                 PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3642                         goto out;
3643                 }
3644                 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
3645                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
3646                 else
3647                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
3648
3649                 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
3650                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
3651         }
3652 out:
3653         return plane_color_ctl;
3654 }
3655
3656 static int
3657 __intel_display_resume(struct drm_device *dev,
3658                        struct drm_atomic_state *state,
3659                        struct drm_modeset_acquire_ctx *ctx)
3660 {
3661         struct drm_crtc_state *crtc_state;
3662         struct drm_crtc *crtc;
3663         int i, ret;
3664
3665         intel_modeset_setup_hw_state(dev, ctx);
3666         i915_redisable_vga(to_i915(dev));
3667
3668         if (!state)
3669                 return 0;
3670
3671         /*
3672          * We've duplicated the state, pointers to the old state are invalid.
3673          *
3674          * Don't attempt to use the old state until we commit the duplicated state.
3675          */
3676         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3677                 /*
3678                  * Force recalculation even if we restore
3679                  * current state. With fast modeset this may not result
3680                  * in a modeset when the state is compatible.
3681                  */
3682                 crtc_state->mode_changed = true;
3683         }
3684
3685         /* ignore any reset values/BIOS leftovers in the WM registers */
3686         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3687                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3688
3689         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3690
3691         WARN_ON(ret == -EDEADLK);
3692         return ret;
3693 }
3694
3695 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3696 {
3697         return intel_has_gpu_reset(dev_priv) &&
3698                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3699 }
3700
3701 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3702 {
3703         struct drm_device *dev = &dev_priv->drm;
3704         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3705         struct drm_atomic_state *state;
3706         int ret;
3707
3708         /* reset doesn't touch the display */
3709         if (!i915_modparams.force_reset_modeset_test &&
3710             !gpu_reset_clobbers_display(dev_priv))
3711                 return;
3712
3713         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3714         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3715         wake_up_all(&dev_priv->gpu_error.wait_queue);
3716
3717         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3718                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3719                 i915_gem_set_wedged(dev_priv);
3720         }
3721
3722         /*
3723          * Need mode_config.mutex so that we don't
3724          * trample ongoing ->detect() and whatnot.
3725          */
3726         mutex_lock(&dev->mode_config.mutex);
3727         drm_modeset_acquire_init(ctx, 0);
3728         while (1) {
3729                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3730                 if (ret != -EDEADLK)
3731                         break;
3732
3733                 drm_modeset_backoff(ctx);
3734         }
3735         /*
3736          * Disabling the crtcs gracefully seems nicer. Also the
3737          * g33 docs say we should at least disable all the planes.
3738          */
3739         state = drm_atomic_helper_duplicate_state(dev, ctx);
3740         if (IS_ERR(state)) {
3741                 ret = PTR_ERR(state);
3742                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3743                 return;
3744         }
3745
3746         ret = drm_atomic_helper_disable_all(dev, ctx);
3747         if (ret) {
3748                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3749                 drm_atomic_state_put(state);
3750                 return;
3751         }
3752
3753         dev_priv->modeset_restore_state = state;
3754         state->acquire_ctx = ctx;
3755 }
3756
3757 void intel_finish_reset(struct drm_i915_private *dev_priv)
3758 {
3759         struct drm_device *dev = &dev_priv->drm;
3760         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3761         struct drm_atomic_state *state;
3762         int ret;
3763
3764         /* reset doesn't touch the display */
3765         if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
3766                 return;
3767
3768         state = fetch_and_zero(&dev_priv->modeset_restore_state);
3769         if (!state)
3770                 goto unlock;
3771
3772         /* reset doesn't touch the display */
3773         if (!gpu_reset_clobbers_display(dev_priv)) {
3774                 /* for testing only restore the display */
3775                 ret = __intel_display_resume(dev, state, ctx);
3776                 if (ret)
3777                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3778         } else {
3779                 /*
3780                  * The display has been reset as well,
3781                  * so need a full re-initialization.
3782                  */
3783                 intel_runtime_pm_disable_interrupts(dev_priv);
3784                 intel_runtime_pm_enable_interrupts(dev_priv);
3785
3786                 intel_pps_unlock_regs_wa(dev_priv);
3787                 intel_modeset_init_hw(dev);
3788                 intel_init_clock_gating(dev_priv);
3789
3790                 spin_lock_irq(&dev_priv->irq_lock);
3791                 if (dev_priv->display.hpd_irq_setup)
3792                         dev_priv->display.hpd_irq_setup(dev_priv);
3793                 spin_unlock_irq(&dev_priv->irq_lock);
3794
3795                 ret = __intel_display_resume(dev, state, ctx);
3796                 if (ret)
3797                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3798
3799                 intel_hpd_init(dev_priv);
3800         }
3801
3802         drm_atomic_state_put(state);
3803 unlock:
3804         drm_modeset_drop_locks(ctx);
3805         drm_modeset_acquire_fini(ctx);
3806         mutex_unlock(&dev->mode_config.mutex);
3807
3808         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3809 }
3810
3811 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3812                                      const struct intel_crtc_state *new_crtc_state)
3813 {
3814         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3815         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3816
3817         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3818         crtc->base.mode = new_crtc_state->base.mode;
3819
3820         /*
3821          * Update pipe size and adjust fitter if needed: the reason for this is
3822          * that in compute_mode_changes we check the native mode (not the pfit
3823          * mode) to see if we can flip rather than do a full mode set. In the
3824          * fastboot case, we'll flip, but if we don't update the pipesrc and
3825          * pfit state, we'll end up with a big fb scanned out into the wrong
3826          * sized surface.
3827          */
3828
3829         I915_WRITE(PIPESRC(crtc->pipe),
3830                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3831                    (new_crtc_state->pipe_src_h - 1));
3832
3833         /* on skylake this is done by detaching scalers */
3834         if (INTEL_GEN(dev_priv) >= 9) {
3835                 skl_detach_scalers(crtc);
3836
3837                 if (new_crtc_state->pch_pfit.enabled)
3838                         skylake_pfit_enable(crtc);
3839         } else if (HAS_PCH_SPLIT(dev_priv)) {
3840                 if (new_crtc_state->pch_pfit.enabled)
3841                         ironlake_pfit_enable(crtc);
3842                 else if (old_crtc_state->pch_pfit.enabled)
3843                         ironlake_pfit_disable(crtc, true);
3844         }
3845 }
3846
3847 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3848 {
3849         struct drm_device *dev = crtc->base.dev;
3850         struct drm_i915_private *dev_priv = to_i915(dev);
3851         int pipe = crtc->pipe;
3852         i915_reg_t reg;
3853         u32 temp;
3854
3855         /* enable normal train */
3856         reg = FDI_TX_CTL(pipe);
3857         temp = I915_READ(reg);
3858         if (IS_IVYBRIDGE(dev_priv)) {
3859                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3860                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3861         } else {
3862                 temp &= ~FDI_LINK_TRAIN_NONE;
3863                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3864         }
3865         I915_WRITE(reg, temp);
3866
3867         reg = FDI_RX_CTL(pipe);
3868         temp = I915_READ(reg);
3869         if (HAS_PCH_CPT(dev_priv)) {
3870                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3871                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3872         } else {
3873                 temp &= ~FDI_LINK_TRAIN_NONE;
3874                 temp |= FDI_LINK_TRAIN_NONE;
3875         }
3876         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3877
3878         /* wait one idle pattern time */
3879         POSTING_READ(reg);
3880         udelay(1000);
3881
3882         /* IVB wants error correction enabled */
3883         if (IS_IVYBRIDGE(dev_priv))
3884                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3885                            FDI_FE_ERRC_ENABLE);
3886 }
3887
3888 /* The FDI link training functions for ILK/Ibexpeak. */
3889 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3890                                     const struct intel_crtc_state *crtc_state)
3891 {
3892         struct drm_device *dev = crtc->base.dev;
3893         struct drm_i915_private *dev_priv = to_i915(dev);
3894         int pipe = crtc->pipe;
3895         i915_reg_t reg;
3896         u32 temp, tries;
3897
3898         /* FDI needs bits from pipe first */
3899         assert_pipe_enabled(dev_priv, pipe);
3900
3901         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3902            for train result */
3903         reg = FDI_RX_IMR(pipe);
3904         temp = I915_READ(reg);
3905         temp &= ~FDI_RX_SYMBOL_LOCK;
3906         temp &= ~FDI_RX_BIT_LOCK;
3907         I915_WRITE(reg, temp);
3908         I915_READ(reg);
3909         udelay(150);
3910
3911         /* enable CPU FDI TX and PCH FDI RX */
3912         reg = FDI_TX_CTL(pipe);
3913         temp = I915_READ(reg);
3914         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3915         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3916         temp &= ~FDI_LINK_TRAIN_NONE;
3917         temp |= FDI_LINK_TRAIN_PATTERN_1;
3918         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3919
3920         reg = FDI_RX_CTL(pipe);
3921         temp = I915_READ(reg);
3922         temp &= ~FDI_LINK_TRAIN_NONE;
3923         temp |= FDI_LINK_TRAIN_PATTERN_1;
3924         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3925
3926         POSTING_READ(reg);
3927         udelay(150);
3928
3929         /* Ironlake workaround, enable clock pointer after FDI enable*/
3930         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3931         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3932                    FDI_RX_PHASE_SYNC_POINTER_EN);
3933
3934         reg = FDI_RX_IIR(pipe);
3935         for (tries = 0; tries < 5; tries++) {
3936                 temp = I915_READ(reg);
3937                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3938
3939                 if ((temp & FDI_RX_BIT_LOCK)) {
3940                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3941                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3942                         break;
3943                 }
3944         }
3945         if (tries == 5)
3946                 DRM_ERROR("FDI train 1 fail!\n");
3947
3948         /* Train 2 */
3949         reg = FDI_TX_CTL(pipe);
3950         temp = I915_READ(reg);
3951         temp &= ~FDI_LINK_TRAIN_NONE;
3952         temp |= FDI_LINK_TRAIN_PATTERN_2;
3953         I915_WRITE(reg, temp);
3954
3955         reg = FDI_RX_CTL(pipe);
3956         temp = I915_READ(reg);
3957         temp &= ~FDI_LINK_TRAIN_NONE;
3958         temp |= FDI_LINK_TRAIN_PATTERN_2;
3959         I915_WRITE(reg, temp);
3960
3961         POSTING_READ(reg);
3962         udelay(150);
3963
3964         reg = FDI_RX_IIR(pipe);
3965         for (tries = 0; tries < 5; tries++) {
3966                 temp = I915_READ(reg);
3967                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3968
3969                 if (temp & FDI_RX_SYMBOL_LOCK) {
3970                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3971                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3972                         break;
3973                 }
3974         }
3975         if (tries == 5)
3976                 DRM_ERROR("FDI train 2 fail!\n");
3977
3978         DRM_DEBUG_KMS("FDI train done\n");
3979
3980 }
3981
3982 static const int snb_b_fdi_train_param[] = {
3983         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3984         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3985         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3986         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3987 };
3988
3989 /* The FDI link training functions for SNB/Cougarpoint. */
3990 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3991                                 const struct intel_crtc_state *crtc_state)
3992 {
3993         struct drm_device *dev = crtc->base.dev;
3994         struct drm_i915_private *dev_priv = to_i915(dev);
3995         int pipe = crtc->pipe;
3996         i915_reg_t reg;
3997         u32 temp, i, retry;
3998
3999         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4000            for train result */
4001         reg = FDI_RX_IMR(pipe);
4002         temp = I915_READ(reg);
4003         temp &= ~FDI_RX_SYMBOL_LOCK;
4004         temp &= ~FDI_RX_BIT_LOCK;
4005         I915_WRITE(reg, temp);
4006
4007         POSTING_READ(reg);
4008         udelay(150);
4009
4010         /* enable CPU FDI TX and PCH FDI RX */
4011         reg = FDI_TX_CTL(pipe);
4012         temp = I915_READ(reg);
4013         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4014         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4015         temp &= ~FDI_LINK_TRAIN_NONE;
4016         temp |= FDI_LINK_TRAIN_PATTERN_1;
4017         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4018         /* SNB-B */
4019         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4020         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4021
4022         I915_WRITE(FDI_RX_MISC(pipe),
4023                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4024
4025         reg = FDI_RX_CTL(pipe);
4026         temp = I915_READ(reg);
4027         if (HAS_PCH_CPT(dev_priv)) {
4028                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4029                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4030         } else {
4031                 temp &= ~FDI_LINK_TRAIN_NONE;
4032                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4033         }
4034         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4035
4036         POSTING_READ(reg);
4037         udelay(150);
4038
4039         for (i = 0; i < 4; i++) {
4040                 reg = FDI_TX_CTL(pipe);
4041                 temp = I915_READ(reg);
4042                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4043                 temp |= snb_b_fdi_train_param[i];
4044                 I915_WRITE(reg, temp);
4045
4046                 POSTING_READ(reg);
4047                 udelay(500);
4048
4049                 for (retry = 0; retry < 5; retry++) {
4050                         reg = FDI_RX_IIR(pipe);
4051                         temp = I915_READ(reg);
4052                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4053                         if (temp & FDI_RX_BIT_LOCK) {
4054                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4055                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4056                                 break;
4057                         }
4058                         udelay(50);
4059                 }
4060                 if (retry < 5)
4061                         break;
4062         }
4063         if (i == 4)
4064                 DRM_ERROR("FDI train 1 fail!\n");
4065
4066         /* Train 2 */
4067         reg = FDI_TX_CTL(pipe);
4068         temp = I915_READ(reg);
4069         temp &= ~FDI_LINK_TRAIN_NONE;
4070         temp |= FDI_LINK_TRAIN_PATTERN_2;
4071         if (IS_GEN6(dev_priv)) {
4072                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4073                 /* SNB-B */
4074                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4075         }
4076         I915_WRITE(reg, temp);
4077
4078         reg = FDI_RX_CTL(pipe);
4079         temp = I915_READ(reg);
4080         if (HAS_PCH_CPT(dev_priv)) {
4081                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4082                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4083         } else {
4084                 temp &= ~FDI_LINK_TRAIN_NONE;
4085                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4086         }
4087         I915_WRITE(reg, temp);
4088
4089         POSTING_READ(reg);
4090         udelay(150);
4091
4092         for (i = 0; i < 4; i++) {
4093                 reg = FDI_TX_CTL(pipe);
4094                 temp = I915_READ(reg);
4095                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4096                 temp |= snb_b_fdi_train_param[i];
4097                 I915_WRITE(reg, temp);
4098
4099                 POSTING_READ(reg);
4100                 udelay(500);
4101
4102                 for (retry = 0; retry < 5; retry++) {
4103                         reg = FDI_RX_IIR(pipe);
4104                         temp = I915_READ(reg);
4105                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4106                         if (temp & FDI_RX_SYMBOL_LOCK) {
4107                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4108                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4109                                 break;
4110                         }
4111                         udelay(50);
4112                 }
4113                 if (retry < 5)
4114                         break;
4115         }
4116         if (i == 4)
4117                 DRM_ERROR("FDI train 2 fail!\n");
4118
4119         DRM_DEBUG_KMS("FDI train done.\n");
4120 }
4121
4122 /* Manual link training for Ivy Bridge A0 parts */
4123 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4124                                       const struct intel_crtc_state *crtc_state)
4125 {
4126         struct drm_device *dev = crtc->base.dev;
4127         struct drm_i915_private *dev_priv = to_i915(dev);
4128         int pipe = crtc->pipe;
4129         i915_reg_t reg;
4130         u32 temp, i, j;
4131
4132         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4133            for train result */
4134         reg = FDI_RX_IMR(pipe);
4135         temp = I915_READ(reg);
4136         temp &= ~FDI_RX_SYMBOL_LOCK;
4137         temp &= ~FDI_RX_BIT_LOCK;
4138         I915_WRITE(reg, temp);
4139
4140         POSTING_READ(reg);
4141         udelay(150);
4142
4143         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4144                       I915_READ(FDI_RX_IIR(pipe)));
4145
4146         /* Try each vswing and preemphasis setting twice before moving on */
4147         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4148                 /* disable first in case we need to retry */
4149                 reg = FDI_TX_CTL(pipe);
4150                 temp = I915_READ(reg);
4151                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4152                 temp &= ~FDI_TX_ENABLE;
4153                 I915_WRITE(reg, temp);
4154
4155                 reg = FDI_RX_CTL(pipe);
4156                 temp = I915_READ(reg);
4157                 temp &= ~FDI_LINK_TRAIN_AUTO;
4158                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4159                 temp &= ~FDI_RX_ENABLE;
4160                 I915_WRITE(reg, temp);
4161
4162                 /* enable CPU FDI TX and PCH FDI RX */
4163                 reg = FDI_TX_CTL(pipe);
4164                 temp = I915_READ(reg);
4165                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4166                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4167                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4168                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4169                 temp |= snb_b_fdi_train_param[j/2];
4170                 temp |= FDI_COMPOSITE_SYNC;
4171                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4172
4173                 I915_WRITE(FDI_RX_MISC(pipe),
4174                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4175
4176                 reg = FDI_RX_CTL(pipe);
4177                 temp = I915_READ(reg);
4178                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4179                 temp |= FDI_COMPOSITE_SYNC;
4180                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4181
4182                 POSTING_READ(reg);
4183                 udelay(1); /* should be 0.5us */
4184
4185                 for (i = 0; i < 4; i++) {
4186                         reg = FDI_RX_IIR(pipe);
4187                         temp = I915_READ(reg);
4188                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4189
4190                         if (temp & FDI_RX_BIT_LOCK ||
4191                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4192                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4193                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4194                                               i);
4195                                 break;
4196                         }
4197                         udelay(1); /* should be 0.5us */
4198                 }
4199                 if (i == 4) {
4200                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4201                         continue;
4202                 }
4203
4204                 /* Train 2 */
4205                 reg = FDI_TX_CTL(pipe);
4206                 temp = I915_READ(reg);
4207                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4208                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4209                 I915_WRITE(reg, temp);
4210
4211                 reg = FDI_RX_CTL(pipe);
4212                 temp = I915_READ(reg);
4213                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4214                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4215                 I915_WRITE(reg, temp);
4216
4217                 POSTING_READ(reg);
4218                 udelay(2); /* should be 1.5us */
4219
4220                 for (i = 0; i < 4; i++) {
4221                         reg = FDI_RX_IIR(pipe);
4222                         temp = I915_READ(reg);
4223                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4224
4225                         if (temp & FDI_RX_SYMBOL_LOCK ||
4226                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4227                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4228                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4229                                               i);
4230                                 goto train_done;
4231                         }
4232                         udelay(2); /* should be 1.5us */
4233                 }
4234                 if (i == 4)
4235                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4236         }
4237
4238 train_done:
4239         DRM_DEBUG_KMS("FDI train done.\n");
4240 }
4241
4242 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4243 {
4244         struct drm_device *dev = intel_crtc->base.dev;
4245         struct drm_i915_private *dev_priv = to_i915(dev);
4246         int pipe = intel_crtc->pipe;
4247         i915_reg_t reg;
4248         u32 temp;
4249
4250         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4251         reg = FDI_RX_CTL(pipe);
4252         temp = I915_READ(reg);
4253         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4254         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4255         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4256         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4257
4258         POSTING_READ(reg);
4259         udelay(200);
4260
4261         /* Switch from Rawclk to PCDclk */
4262         temp = I915_READ(reg);
4263         I915_WRITE(reg, temp | FDI_PCDCLK);
4264
4265         POSTING_READ(reg);
4266         udelay(200);
4267
4268         /* Enable CPU FDI TX PLL, always on for Ironlake */
4269         reg = FDI_TX_CTL(pipe);
4270         temp = I915_READ(reg);
4271         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4272                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4273
4274                 POSTING_READ(reg);
4275                 udelay(100);
4276         }
4277 }
4278
4279 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4280 {
4281         struct drm_device *dev = intel_crtc->base.dev;
4282         struct drm_i915_private *dev_priv = to_i915(dev);
4283         int pipe = intel_crtc->pipe;
4284         i915_reg_t reg;
4285         u32 temp;
4286
4287         /* Switch from PCDclk to Rawclk */
4288         reg = FDI_RX_CTL(pipe);
4289         temp = I915_READ(reg);
4290         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4291
4292         /* Disable CPU FDI TX PLL */
4293         reg = FDI_TX_CTL(pipe);
4294         temp = I915_READ(reg);
4295         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4296
4297         POSTING_READ(reg);
4298         udelay(100);
4299
4300         reg = FDI_RX_CTL(pipe);
4301         temp = I915_READ(reg);
4302         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4303
4304         /* Wait for the clocks to turn off. */
4305         POSTING_READ(reg);
4306         udelay(100);
4307 }
4308
4309 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4310 {
4311         struct drm_device *dev = crtc->dev;
4312         struct drm_i915_private *dev_priv = to_i915(dev);
4313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314         int pipe = intel_crtc->pipe;
4315         i915_reg_t reg;
4316         u32 temp;
4317
4318         /* disable CPU FDI tx and PCH FDI rx */
4319         reg = FDI_TX_CTL(pipe);
4320         temp = I915_READ(reg);
4321         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4322         POSTING_READ(reg);
4323
4324         reg = FDI_RX_CTL(pipe);
4325         temp = I915_READ(reg);
4326         temp &= ~(0x7 << 16);
4327         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4328         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4329
4330         POSTING_READ(reg);
4331         udelay(100);
4332
4333         /* Ironlake workaround, disable clock pointer after downing FDI */
4334         if (HAS_PCH_IBX(dev_priv))
4335                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4336
4337         /* still set train pattern 1 */
4338         reg = FDI_TX_CTL(pipe);
4339         temp = I915_READ(reg);
4340         temp &= ~FDI_LINK_TRAIN_NONE;
4341         temp |= FDI_LINK_TRAIN_PATTERN_1;
4342         I915_WRITE(reg, temp);
4343
4344         reg = FDI_RX_CTL(pipe);
4345         temp = I915_READ(reg);
4346         if (HAS_PCH_CPT(dev_priv)) {
4347                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4348                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4349         } else {
4350                 temp &= ~FDI_LINK_TRAIN_NONE;
4351                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4352         }
4353         /* BPC in FDI rx is consistent with that in PIPECONF */
4354         temp &= ~(0x07 << 16);
4355         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4356         I915_WRITE(reg, temp);
4357
4358         POSTING_READ(reg);
4359         udelay(100);
4360 }
4361
4362 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4363 {
4364         struct drm_crtc *crtc;
4365         bool cleanup_done;
4366
4367         drm_for_each_crtc(crtc, &dev_priv->drm) {
4368                 struct drm_crtc_commit *commit;
4369                 spin_lock(&crtc->commit_lock);
4370                 commit = list_first_entry_or_null(&crtc->commit_list,
4371                                                   struct drm_crtc_commit, commit_entry);
4372                 cleanup_done = commit ?
4373                         try_wait_for_completion(&commit->cleanup_done) : true;
4374                 spin_unlock(&crtc->commit_lock);
4375
4376                 if (cleanup_done)
4377                         continue;
4378
4379                 drm_crtc_wait_one_vblank(crtc);
4380
4381                 return true;
4382         }
4383
4384         return false;
4385 }
4386
4387 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4388 {
4389         u32 temp;
4390
4391         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4392
4393         mutex_lock(&dev_priv->sb_lock);
4394
4395         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4396         temp |= SBI_SSCCTL_DISABLE;
4397         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4398
4399         mutex_unlock(&dev_priv->sb_lock);
4400 }
4401
4402 /* Program iCLKIP clock to the desired frequency */
4403 static void lpt_program_iclkip(struct intel_crtc *crtc)
4404 {
4405         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4406         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4407         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4408         u32 temp;
4409
4410         lpt_disable_iclkip(dev_priv);
4411
4412         /* The iCLK virtual clock root frequency is in MHz,
4413          * but the adjusted_mode->crtc_clock in in KHz. To get the
4414          * divisors, it is necessary to divide one by another, so we
4415          * convert the virtual clock precision to KHz here for higher
4416          * precision.
4417          */
4418         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4419                 u32 iclk_virtual_root_freq = 172800 * 1000;
4420                 u32 iclk_pi_range = 64;
4421                 u32 desired_divisor;
4422
4423                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4424                                                     clock << auxdiv);
4425                 divsel = (desired_divisor / iclk_pi_range) - 2;
4426                 phaseinc = desired_divisor % iclk_pi_range;
4427
4428                 /*
4429                  * Near 20MHz is a corner case which is
4430                  * out of range for the 7-bit divisor
4431                  */
4432                 if (divsel <= 0x7f)
4433                         break;
4434         }
4435
4436         /* This should not happen with any sane values */
4437         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4438                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4439         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4440                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4441
4442         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4443                         clock,
4444                         auxdiv,
4445                         divsel,
4446                         phasedir,
4447                         phaseinc);
4448
4449         mutex_lock(&dev_priv->sb_lock);
4450
4451         /* Program SSCDIVINTPHASE6 */
4452         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4453         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4454         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4455         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4456         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4457         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4458         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4459         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4460
4461         /* Program SSCAUXDIV */
4462         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4463         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4464         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4465         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4466
4467         /* Enable modulator and associated divider */
4468         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4469         temp &= ~SBI_SSCCTL_DISABLE;
4470         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4471
4472         mutex_unlock(&dev_priv->sb_lock);
4473
4474         /* Wait for initialization time */
4475         udelay(24);
4476
4477         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4478 }
4479
4480 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4481 {
4482         u32 divsel, phaseinc, auxdiv;
4483         u32 iclk_virtual_root_freq = 172800 * 1000;
4484         u32 iclk_pi_range = 64;
4485         u32 desired_divisor;
4486         u32 temp;
4487
4488         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4489                 return 0;
4490
4491         mutex_lock(&dev_priv->sb_lock);
4492
4493         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4494         if (temp & SBI_SSCCTL_DISABLE) {
4495                 mutex_unlock(&dev_priv->sb_lock);
4496                 return 0;
4497         }
4498
4499         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4500         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4501                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4502         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4503                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4504
4505         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4506         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4507                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4508
4509         mutex_unlock(&dev_priv->sb_lock);
4510
4511         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4512
4513         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4514                                  desired_divisor << auxdiv);
4515 }
4516
4517 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4518                                                 enum pipe pch_transcoder)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = to_i915(dev);
4522         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4523
4524         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4525                    I915_READ(HTOTAL(cpu_transcoder)));
4526         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4527                    I915_READ(HBLANK(cpu_transcoder)));
4528         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4529                    I915_READ(HSYNC(cpu_transcoder)));
4530
4531         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4532                    I915_READ(VTOTAL(cpu_transcoder)));
4533         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4534                    I915_READ(VBLANK(cpu_transcoder)));
4535         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4536                    I915_READ(VSYNC(cpu_transcoder)));
4537         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4538                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4539 }
4540
4541 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4542 {
4543         struct drm_i915_private *dev_priv = to_i915(dev);
4544         uint32_t temp;
4545
4546         temp = I915_READ(SOUTH_CHICKEN1);
4547         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4548                 return;
4549
4550         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4551         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4552
4553         temp &= ~FDI_BC_BIFURCATION_SELECT;
4554         if (enable)
4555                 temp |= FDI_BC_BIFURCATION_SELECT;
4556
4557         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4558         I915_WRITE(SOUTH_CHICKEN1, temp);
4559         POSTING_READ(SOUTH_CHICKEN1);
4560 }
4561
4562 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4563 {
4564         struct drm_device *dev = intel_crtc->base.dev;
4565
4566         switch (intel_crtc->pipe) {
4567         case PIPE_A:
4568                 break;
4569         case PIPE_B:
4570                 if (intel_crtc->config->fdi_lanes > 2)
4571                         cpt_set_fdi_bc_bifurcation(dev, false);
4572                 else
4573                         cpt_set_fdi_bc_bifurcation(dev, true);
4574
4575                 break;
4576         case PIPE_C:
4577                 cpt_set_fdi_bc_bifurcation(dev, true);
4578
4579                 break;
4580         default:
4581                 BUG();
4582         }
4583 }
4584
4585 /* Return which DP Port should be selected for Transcoder DP control */
4586 static enum port
4587 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4588 {
4589         struct drm_device *dev = crtc->base.dev;
4590         struct intel_encoder *encoder;
4591
4592         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4593                 if (encoder->type == INTEL_OUTPUT_DP ||
4594                     encoder->type == INTEL_OUTPUT_EDP)
4595                         return encoder->port;
4596         }
4597
4598         return -1;
4599 }
4600
4601 /*
4602  * Enable PCH resources required for PCH ports:
4603  *   - PCH PLLs
4604  *   - FDI training & RX/TX
4605  *   - update transcoder timings
4606  *   - DP transcoding bits
4607  *   - transcoder
4608  */
4609 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4610 {
4611         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4612         struct drm_device *dev = crtc->base.dev;
4613         struct drm_i915_private *dev_priv = to_i915(dev);
4614         int pipe = crtc->pipe;
4615         u32 temp;
4616
4617         assert_pch_transcoder_disabled(dev_priv, pipe);
4618
4619         if (IS_IVYBRIDGE(dev_priv))
4620                 ivybridge_update_fdi_bc_bifurcation(crtc);
4621
4622         /* Write the TU size bits before fdi link training, so that error
4623          * detection works. */
4624         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4625                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4626
4627         /* For PCH output, training FDI link */
4628         dev_priv->display.fdi_link_train(crtc, crtc_state);
4629
4630         /* We need to program the right clock selection before writing the pixel
4631          * mutliplier into the DPLL. */
4632         if (HAS_PCH_CPT(dev_priv)) {
4633                 u32 sel;
4634
4635                 temp = I915_READ(PCH_DPLL_SEL);
4636                 temp |= TRANS_DPLL_ENABLE(pipe);
4637                 sel = TRANS_DPLLB_SEL(pipe);
4638                 if (crtc_state->shared_dpll ==
4639                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4640                         temp |= sel;
4641                 else
4642                         temp &= ~sel;
4643                 I915_WRITE(PCH_DPLL_SEL, temp);
4644         }
4645
4646         /* XXX: pch pll's can be enabled any time before we enable the PCH
4647          * transcoder, and we actually should do this to not upset any PCH
4648          * transcoder that already use the clock when we share it.
4649          *
4650          * Note that enable_shared_dpll tries to do the right thing, but
4651          * get_shared_dpll unconditionally resets the pll - we need that to have
4652          * the right LVDS enable sequence. */
4653         intel_enable_shared_dpll(crtc);
4654
4655         /* set transcoder timing, panel must allow it */
4656         assert_panel_unlocked(dev_priv, pipe);
4657         ironlake_pch_transcoder_set_timings(crtc, pipe);
4658
4659         intel_fdi_normal_train(crtc);
4660
4661         /* For PCH DP, enable TRANS_DP_CTL */
4662         if (HAS_PCH_CPT(dev_priv) &&
4663             intel_crtc_has_dp_encoder(crtc_state)) {
4664                 const struct drm_display_mode *adjusted_mode =
4665                         &crtc_state->base.adjusted_mode;
4666                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4667                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4668                 temp = I915_READ(reg);
4669                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4670                           TRANS_DP_SYNC_MASK |
4671                           TRANS_DP_BPC_MASK);
4672                 temp |= TRANS_DP_OUTPUT_ENABLE;
4673                 temp |= bpc << 9; /* same format but at 11:9 */
4674
4675                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4676                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4677                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4678                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4679
4680                 switch (intel_trans_dp_port_sel(crtc)) {
4681                 case PORT_B:
4682                         temp |= TRANS_DP_PORT_SEL_B;
4683                         break;
4684                 case PORT_C:
4685                         temp |= TRANS_DP_PORT_SEL_C;
4686                         break;
4687                 case PORT_D:
4688                         temp |= TRANS_DP_PORT_SEL_D;
4689                         break;
4690                 default:
4691                         BUG();
4692                 }
4693
4694                 I915_WRITE(reg, temp);
4695         }
4696
4697         ironlake_enable_pch_transcoder(dev_priv, pipe);
4698 }
4699
4700 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4701 {
4702         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4704         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4705
4706         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4707
4708         lpt_program_iclkip(crtc);
4709
4710         /* Set transcoder timing. */
4711         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4712
4713         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4714 }
4715
4716 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4717 {
4718         struct drm_i915_private *dev_priv = to_i915(dev);
4719         i915_reg_t dslreg = PIPEDSL(pipe);
4720         u32 temp;
4721
4722         temp = I915_READ(dslreg);
4723         udelay(500);
4724         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4725                 if (wait_for(I915_READ(dslreg) != temp, 5))
4726                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4727         }
4728 }
4729
4730 static int
4731 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4732                   unsigned int scaler_user, int *scaler_id,
4733                   int src_w, int src_h, int dst_w, int dst_h,
4734                   bool plane_scaler_check,
4735                   uint32_t pixel_format)
4736 {
4737         struct intel_crtc_scaler_state *scaler_state =
4738                 &crtc_state->scaler_state;
4739         struct intel_crtc *intel_crtc =
4740                 to_intel_crtc(crtc_state->base.crtc);
4741         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4742         const struct drm_display_mode *adjusted_mode =
4743                 &crtc_state->base.adjusted_mode;
4744         int need_scaling;
4745
4746         /*
4747          * Src coordinates are already rotated by 270 degrees for
4748          * the 90/270 degree plane rotation cases (to match the
4749          * GTT mapping), hence no need to account for rotation here.
4750          */
4751         need_scaling = src_w != dst_w || src_h != dst_h;
4752
4753         if (plane_scaler_check)
4754                 if (pixel_format == DRM_FORMAT_NV12)
4755                         need_scaling = true;
4756
4757         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4758                 need_scaling = true;
4759
4760         /*
4761          * Scaling/fitting not supported in IF-ID mode in GEN9+
4762          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4763          * Once NV12 is enabled, handle it here while allocating scaler
4764          * for NV12.
4765          */
4766         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4767             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4768                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4769                 return -EINVAL;
4770         }
4771
4772         /*
4773          * if plane is being disabled or scaler is no more required or force detach
4774          *  - free scaler binded to this plane/crtc
4775          *  - in order to do this, update crtc->scaler_usage
4776          *
4777          * Here scaler state in crtc_state is set free so that
4778          * scaler can be assigned to other user. Actual register
4779          * update to free the scaler is done in plane/panel-fit programming.
4780          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4781          */
4782         if (force_detach || !need_scaling) {
4783                 if (*scaler_id >= 0) {
4784                         scaler_state->scaler_users &= ~(1 << scaler_user);
4785                         scaler_state->scalers[*scaler_id].in_use = 0;
4786
4787                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4788                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4789                                 intel_crtc->pipe, scaler_user, *scaler_id,
4790                                 scaler_state->scaler_users);
4791                         *scaler_id = -1;
4792                 }
4793                 return 0;
4794         }
4795
4796         if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
4797             (src_h < SKL_MIN_YUV_420_SRC_H || (src_w % 4) != 0 ||
4798              (src_h % 4) != 0)) {
4799                 DRM_DEBUG_KMS("NV12: src dimensions not met\n");
4800                 return -EINVAL;
4801         }
4802
4803         /* range checks */
4804         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4805             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4806             (IS_GEN11(dev_priv) &&
4807              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
4808               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
4809             (!IS_GEN11(dev_priv) &&
4810              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4811               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
4812                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4813                         "size is out of scaler range\n",
4814                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4815                 return -EINVAL;
4816         }
4817
4818         /* mark this plane as a scaler user in crtc_state */
4819         scaler_state->scaler_users |= (1 << scaler_user);
4820         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4821                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4822                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4823                 scaler_state->scaler_users);
4824
4825         return 0;
4826 }
4827
4828 /**
4829  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4830  *
4831  * @state: crtc's scaler state
4832  *
4833  * Return
4834  *     0 - scaler_usage updated successfully
4835  *    error - requested scaling cannot be supported or other error condition
4836  */
4837 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4838 {
4839         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4840
4841         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4842                                  &state->scaler_state.scaler_id,
4843                                  state->pipe_src_w, state->pipe_src_h,
4844                                  adjusted_mode->crtc_hdisplay,
4845                                  adjusted_mode->crtc_vdisplay, false, 0);
4846 }
4847
4848 /**
4849  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4850  * @crtc_state: crtc's scaler state
4851  * @plane_state: atomic plane state to update
4852  *
4853  * Return
4854  *     0 - scaler_usage updated successfully
4855  *    error - requested scaling cannot be supported or other error condition
4856  */
4857 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4858                                    struct intel_plane_state *plane_state)
4859 {
4860
4861         struct intel_plane *intel_plane =
4862                 to_intel_plane(plane_state->base.plane);
4863         struct drm_framebuffer *fb = plane_state->base.fb;
4864         int ret;
4865
4866         bool force_detach = !fb || !plane_state->base.visible;
4867
4868         ret = skl_update_scaler(crtc_state, force_detach,
4869                                 drm_plane_index(&intel_plane->base),
4870                                 &plane_state->scaler_id,
4871                                 drm_rect_width(&plane_state->base.src) >> 16,
4872                                 drm_rect_height(&plane_state->base.src) >> 16,
4873                                 drm_rect_width(&plane_state->base.dst),
4874                                 drm_rect_height(&plane_state->base.dst),
4875                                 fb ? true : false, fb ? fb->format->format : 0);
4876
4877         if (ret || plane_state->scaler_id < 0)
4878                 return ret;
4879
4880         /* check colorkey */
4881         if (plane_state->ckey.flags) {
4882                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4883                               intel_plane->base.base.id,
4884                               intel_plane->base.name);
4885                 return -EINVAL;
4886         }
4887
4888         /* Check src format */
4889         switch (fb->format->format) {
4890         case DRM_FORMAT_RGB565:
4891         case DRM_FORMAT_XBGR8888:
4892         case DRM_FORMAT_XRGB8888:
4893         case DRM_FORMAT_ABGR8888:
4894         case DRM_FORMAT_ARGB8888:
4895         case DRM_FORMAT_XRGB2101010:
4896         case DRM_FORMAT_XBGR2101010:
4897         case DRM_FORMAT_YUYV:
4898         case DRM_FORMAT_YVYU:
4899         case DRM_FORMAT_UYVY:
4900         case DRM_FORMAT_VYUY:
4901         case DRM_FORMAT_NV12:
4902                 break;
4903         default:
4904                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4905                               intel_plane->base.base.id, intel_plane->base.name,
4906                               fb->base.id, fb->format->format);
4907                 return -EINVAL;
4908         }
4909
4910         return 0;
4911 }
4912
4913 static void skylake_scaler_disable(struct intel_crtc *crtc)
4914 {
4915         int i;
4916
4917         for (i = 0; i < crtc->num_scalers; i++)
4918                 skl_detach_scaler(crtc, i);
4919 }
4920
4921 static void skylake_pfit_enable(struct intel_crtc *crtc)
4922 {
4923         struct drm_device *dev = crtc->base.dev;
4924         struct drm_i915_private *dev_priv = to_i915(dev);
4925         int pipe = crtc->pipe;
4926         struct intel_crtc_scaler_state *scaler_state =
4927                 &crtc->config->scaler_state;
4928
4929         if (crtc->config->pch_pfit.enabled) {
4930                 int id;
4931
4932                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4933                         return;
4934
4935                 id = scaler_state->scaler_id;
4936                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4937                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4938                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4939                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4940         }
4941 }
4942
4943 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4944 {
4945         struct drm_device *dev = crtc->base.dev;
4946         struct drm_i915_private *dev_priv = to_i915(dev);
4947         int pipe = crtc->pipe;
4948
4949         if (crtc->config->pch_pfit.enabled) {
4950                 /* Force use of hard-coded filter coefficients
4951                  * as some pre-programmed values are broken,
4952                  * e.g. x201.
4953                  */
4954                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4955                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4956                                                  PF_PIPE_SEL_IVB(pipe));
4957                 else
4958                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4959                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4960                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4961         }
4962 }
4963
4964 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
4965 {
4966         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4967         struct drm_device *dev = crtc->base.dev;
4968         struct drm_i915_private *dev_priv = to_i915(dev);
4969
4970         if (!crtc_state->ips_enabled)
4971                 return;
4972
4973         /*
4974          * We can only enable IPS after we enable a plane and wait for a vblank
4975          * This function is called from post_plane_update, which is run after
4976          * a vblank wait.
4977          */
4978         WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
4979
4980         if (IS_BROADWELL(dev_priv)) {
4981                 mutex_lock(&dev_priv->pcu_lock);
4982                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4983                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4984                 mutex_unlock(&dev_priv->pcu_lock);
4985                 /* Quoting Art Runyan: "its not safe to expect any particular
4986                  * value in IPS_CTL bit 31 after enabling IPS through the
4987                  * mailbox." Moreover, the mailbox may return a bogus state,
4988                  * so we need to just enable it and continue on.
4989                  */
4990         } else {
4991                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4992                 /* The bit only becomes 1 in the next vblank, so this wait here
4993                  * is essentially intel_wait_for_vblank. If we don't have this
4994                  * and don't wait for vblanks until the end of crtc_enable, then
4995                  * the HW state readout code will complain that the expected
4996                  * IPS_CTL value is not the one we read. */
4997                 if (intel_wait_for_register(dev_priv,
4998                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4999                                             50))
5000                         DRM_ERROR("Timed out waiting for IPS enable\n");
5001         }
5002 }
5003
5004 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5005 {
5006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5007         struct drm_device *dev = crtc->base.dev;
5008         struct drm_i915_private *dev_priv = to_i915(dev);
5009
5010         if (!crtc_state->ips_enabled)
5011                 return;
5012
5013         if (IS_BROADWELL(dev_priv)) {
5014                 mutex_lock(&dev_priv->pcu_lock);
5015                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5016                 mutex_unlock(&dev_priv->pcu_lock);
5017                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
5018                 if (intel_wait_for_register(dev_priv,
5019                                             IPS_CTL, IPS_ENABLE, 0,
5020                                             42))
5021                         DRM_ERROR("Timed out waiting for IPS disable\n");
5022         } else {
5023                 I915_WRITE(IPS_CTL, 0);
5024                 POSTING_READ(IPS_CTL);
5025         }
5026
5027         /* We need to wait for a vblank before we can disable the plane. */
5028         intel_wait_for_vblank(dev_priv, crtc->pipe);
5029 }
5030
5031 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5032 {
5033         if (intel_crtc->overlay) {
5034                 struct drm_device *dev = intel_crtc->base.dev;
5035
5036                 mutex_lock(&dev->struct_mutex);
5037                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5038                 mutex_unlock(&dev->struct_mutex);
5039         }
5040
5041         /* Let userspace switch the overlay on again. In most cases userspace
5042          * has to recompute where to put it anyway.
5043          */
5044 }
5045
5046 /**
5047  * intel_post_enable_primary - Perform operations after enabling primary plane
5048  * @crtc: the CRTC whose primary plane was just enabled
5049  * @new_crtc_state: the enabling state
5050  *
5051  * Performs potentially sleeping operations that must be done after the primary
5052  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5053  * called due to an explicit primary plane update, or due to an implicit
5054  * re-enable that is caused when a sprite plane is updated to no longer
5055  * completely hide the primary plane.
5056  */
5057 static void
5058 intel_post_enable_primary(struct drm_crtc *crtc,
5059                           const struct intel_crtc_state *new_crtc_state)
5060 {
5061         struct drm_device *dev = crtc->dev;
5062         struct drm_i915_private *dev_priv = to_i915(dev);
5063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5064         int pipe = intel_crtc->pipe;
5065
5066         /*
5067          * Gen2 reports pipe underruns whenever all planes are disabled.
5068          * So don't enable underrun reporting before at least some planes
5069          * are enabled.
5070          * FIXME: Need to fix the logic to work when we turn off all planes
5071          * but leave the pipe running.
5072          */
5073         if (IS_GEN2(dev_priv))
5074                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5075
5076         /* Underruns don't always raise interrupts, so check manually. */
5077         intel_check_cpu_fifo_underruns(dev_priv);
5078         intel_check_pch_fifo_underruns(dev_priv);
5079 }
5080
5081 /* FIXME get rid of this and use pre_plane_update */
5082 static void
5083 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5084 {
5085         struct drm_device *dev = crtc->dev;
5086         struct drm_i915_private *dev_priv = to_i915(dev);
5087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088         int pipe = intel_crtc->pipe;
5089
5090         /*
5091          * Gen2 reports pipe underruns whenever all planes are disabled.
5092          * So disable underrun reporting before all the planes get disabled.
5093          */
5094         if (IS_GEN2(dev_priv))
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5096
5097         hsw_disable_ips(to_intel_crtc_state(crtc->state));
5098
5099         /*
5100          * Vblank time updates from the shadow to live plane control register
5101          * are blocked if the memory self-refresh mode is active at that
5102          * moment. So to make sure the plane gets truly disabled, disable
5103          * first the self-refresh mode. The self-refresh enable bit in turn
5104          * will be checked/applied by the HW only at the next frame start
5105          * event which is after the vblank start event, so we need to have a
5106          * wait-for-vblank between disabling the plane and the pipe.
5107          */
5108         if (HAS_GMCH_DISPLAY(dev_priv) &&
5109             intel_set_memory_cxsr(dev_priv, false))
5110                 intel_wait_for_vblank(dev_priv, pipe);
5111 }
5112
5113 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5114                                        const struct intel_crtc_state *new_crtc_state)
5115 {
5116         if (!old_crtc_state->ips_enabled)
5117                 return false;
5118
5119         if (needs_modeset(&new_crtc_state->base))
5120                 return true;
5121
5122         return !new_crtc_state->ips_enabled;
5123 }
5124
5125 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5126                                        const struct intel_crtc_state *new_crtc_state)
5127 {
5128         if (!new_crtc_state->ips_enabled)
5129                 return false;
5130
5131         if (needs_modeset(&new_crtc_state->base))
5132                 return true;
5133
5134         /*
5135          * We can't read out IPS on broadwell, assume the worst and
5136          * forcibly enable IPS on the first fastset.
5137          */
5138         if (new_crtc_state->update_pipe &&
5139             old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5140                 return true;
5141
5142         return !old_crtc_state->ips_enabled;
5143 }
5144
5145 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5146 {
5147         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5148         struct drm_device *dev = crtc->base.dev;
5149         struct drm_i915_private *dev_priv = to_i915(dev);
5150         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5151         struct intel_crtc_state *pipe_config =
5152                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5153                                                 crtc);
5154         struct drm_plane *primary = crtc->base.primary;
5155         struct drm_plane_state *old_primary_state =
5156                 drm_atomic_get_old_plane_state(old_state, primary);
5157
5158         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5159
5160         if (pipe_config->update_wm_post && pipe_config->base.active)
5161                 intel_update_watermarks(crtc);
5162
5163         if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5164                 hsw_enable_ips(pipe_config);
5165
5166         if (old_primary_state) {
5167                 struct drm_plane_state *new_primary_state =
5168                         drm_atomic_get_new_plane_state(old_state, primary);
5169                 struct drm_framebuffer *fb = new_primary_state->fb;
5170
5171                 intel_fbc_post_update(crtc);
5172
5173                 if (new_primary_state->visible &&
5174                     (needs_modeset(&pipe_config->base) ||
5175                      !old_primary_state->visible))
5176                         intel_post_enable_primary(&crtc->base, pipe_config);
5177
5178                 /* Display WA 827 */
5179                 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5180                     IS_CANNONLAKE(dev_priv)) {
5181                         if (fb && fb->format->format == DRM_FORMAT_NV12)
5182                                 skl_wa_clkgate(dev_priv, crtc->pipe, false);
5183                 }
5184
5185         }
5186 }
5187
5188 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5189                                    struct intel_crtc_state *pipe_config)
5190 {
5191         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5192         struct drm_device *dev = crtc->base.dev;
5193         struct drm_i915_private *dev_priv = to_i915(dev);
5194         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5195         struct drm_plane *primary = crtc->base.primary;
5196         struct drm_plane_state *old_primary_state =
5197                 drm_atomic_get_old_plane_state(old_state, primary);
5198         bool modeset = needs_modeset(&pipe_config->base);
5199         struct intel_atomic_state *old_intel_state =
5200                 to_intel_atomic_state(old_state);
5201
5202         if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5203                 hsw_disable_ips(old_crtc_state);
5204
5205         if (old_primary_state) {
5206                 struct intel_plane_state *new_primary_state =
5207                         intel_atomic_get_new_plane_state(old_intel_state,
5208                                                          to_intel_plane(primary));
5209                 struct drm_framebuffer *fb = new_primary_state->base.fb;
5210
5211                 /* Display WA 827 */
5212                 if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
5213                     IS_CANNONLAKE(dev_priv)) {
5214                         if (fb && fb->format->format == DRM_FORMAT_NV12)
5215                                 skl_wa_clkgate(dev_priv, crtc->pipe, true);
5216                 }
5217
5218                 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5219                 /*
5220                  * Gen2 reports pipe underruns whenever all planes are disabled.
5221                  * So disable underrun reporting before all the planes get disabled.
5222                  */
5223                 if (IS_GEN2(dev_priv) && old_primary_state->visible &&
5224                     (modeset || !new_primary_state->base.visible))
5225                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5226         }
5227
5228         /*
5229          * Vblank time updates from the shadow to live plane control register
5230          * are blocked if the memory self-refresh mode is active at that
5231          * moment. So to make sure the plane gets truly disabled, disable
5232          * first the self-refresh mode. The self-refresh enable bit in turn
5233          * will be checked/applied by the HW only at the next frame start
5234          * event which is after the vblank start event, so we need to have a
5235          * wait-for-vblank between disabling the plane and the pipe.
5236          */
5237         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5238             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5239                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5240
5241         /*
5242          * IVB workaround: must disable low power watermarks for at least
5243          * one frame before enabling scaling.  LP watermarks can be re-enabled
5244          * when scaling is disabled.
5245          *
5246          * WaCxSRDisabledForSpriteScaling:ivb
5247          */
5248         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5249                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5250
5251         /*
5252          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5253          * watermark programming here.
5254          */
5255         if (needs_modeset(&pipe_config->base))
5256                 return;
5257
5258         /*
5259          * For platforms that support atomic watermarks, program the
5260          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5261          * will be the intermediate values that are safe for both pre- and
5262          * post- vblank; when vblank happens, the 'active' values will be set
5263          * to the final 'target' values and we'll do this again to get the
5264          * optimal watermarks.  For gen9+ platforms, the values we program here
5265          * will be the final target values which will get automatically latched
5266          * at vblank time; no further programming will be necessary.
5267          *
5268          * If a platform hasn't been transitioned to atomic watermarks yet,
5269          * we'll continue to update watermarks the old way, if flags tell
5270          * us to.
5271          */
5272         if (dev_priv->display.initial_watermarks != NULL)
5273                 dev_priv->display.initial_watermarks(old_intel_state,
5274                                                      pipe_config);
5275         else if (pipe_config->update_wm_pre)
5276                 intel_update_watermarks(crtc);
5277 }
5278
5279 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5280 {
5281         struct drm_device *dev = crtc->dev;
5282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5283         struct drm_plane *p;
5284         int pipe = intel_crtc->pipe;
5285
5286         intel_crtc_dpms_overlay_disable(intel_crtc);
5287
5288         drm_for_each_plane_mask(p, dev, plane_mask)
5289                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5290
5291         /*
5292          * FIXME: Once we grow proper nuclear flip support out of this we need
5293          * to compute the mask of flip planes precisely. For the time being
5294          * consider this a flip to a NULL plane.
5295          */
5296         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5297 }
5298
5299 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5300                                           struct intel_crtc_state *crtc_state,
5301                                           struct drm_atomic_state *old_state)
5302 {
5303         struct drm_connector_state *conn_state;
5304         struct drm_connector *conn;
5305         int i;
5306
5307         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5308                 struct intel_encoder *encoder =
5309                         to_intel_encoder(conn_state->best_encoder);
5310
5311                 if (conn_state->crtc != crtc)
5312                         continue;
5313
5314                 if (encoder->pre_pll_enable)
5315                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5316         }
5317 }
5318
5319 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5320                                       struct intel_crtc_state *crtc_state,
5321                                       struct drm_atomic_state *old_state)
5322 {
5323         struct drm_connector_state *conn_state;
5324         struct drm_connector *conn;
5325         int i;
5326
5327         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5328                 struct intel_encoder *encoder =
5329                         to_intel_encoder(conn_state->best_encoder);
5330
5331                 if (conn_state->crtc != crtc)
5332                         continue;
5333
5334                 if (encoder->pre_enable)
5335                         encoder->pre_enable(encoder, crtc_state, conn_state);
5336         }
5337 }
5338
5339 static void intel_encoders_enable(struct drm_crtc *crtc,
5340                                   struct intel_crtc_state *crtc_state,
5341                                   struct drm_atomic_state *old_state)
5342 {
5343         struct drm_connector_state *conn_state;
5344         struct drm_connector *conn;
5345         int i;
5346
5347         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5348                 struct intel_encoder *encoder =
5349                         to_intel_encoder(conn_state->best_encoder);
5350
5351                 if (conn_state->crtc != crtc)
5352                         continue;
5353
5354                 encoder->enable(encoder, crtc_state, conn_state);
5355                 intel_opregion_notify_encoder(encoder, true);
5356         }
5357 }
5358
5359 static void intel_encoders_disable(struct drm_crtc *crtc,
5360                                    struct intel_crtc_state *old_crtc_state,
5361                                    struct drm_atomic_state *old_state)
5362 {
5363         struct drm_connector_state *old_conn_state;
5364         struct drm_connector *conn;
5365         int i;
5366
5367         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5368                 struct intel_encoder *encoder =
5369                         to_intel_encoder(old_conn_state->best_encoder);
5370
5371                 if (old_conn_state->crtc != crtc)
5372                         continue;
5373
5374                 intel_opregion_notify_encoder(encoder, false);
5375                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5376         }
5377 }
5378
5379 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5380                                         struct intel_crtc_state *old_crtc_state,
5381                                         struct drm_atomic_state *old_state)
5382 {
5383         struct drm_connector_state *old_conn_state;
5384         struct drm_connector *conn;
5385         int i;
5386
5387         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5388                 struct intel_encoder *encoder =
5389                         to_intel_encoder(old_conn_state->best_encoder);
5390
5391                 if (old_conn_state->crtc != crtc)
5392                         continue;
5393
5394                 if (encoder->post_disable)
5395                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5396         }
5397 }
5398
5399 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5400                                             struct intel_crtc_state *old_crtc_state,
5401                                             struct drm_atomic_state *old_state)
5402 {
5403         struct drm_connector_state *old_conn_state;
5404         struct drm_connector *conn;
5405         int i;
5406
5407         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5408                 struct intel_encoder *encoder =
5409                         to_intel_encoder(old_conn_state->best_encoder);
5410
5411                 if (old_conn_state->crtc != crtc)
5412                         continue;
5413
5414                 if (encoder->post_pll_disable)
5415                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5416         }
5417 }
5418
5419 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5420                                  struct drm_atomic_state *old_state)
5421 {
5422         struct drm_crtc *crtc = pipe_config->base.crtc;
5423         struct drm_device *dev = crtc->dev;
5424         struct drm_i915_private *dev_priv = to_i915(dev);
5425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5426         int pipe = intel_crtc->pipe;
5427         struct intel_atomic_state *old_intel_state =
5428                 to_intel_atomic_state(old_state);
5429
5430         if (WARN_ON(intel_crtc->active))
5431                 return;
5432
5433         /*
5434          * Sometimes spurious CPU pipe underruns happen during FDI
5435          * training, at least with VGA+HDMI cloning. Suppress them.
5436          *
5437          * On ILK we get an occasional spurious CPU pipe underruns
5438          * between eDP port A enable and vdd enable. Also PCH port
5439          * enable seems to result in the occasional CPU pipe underrun.
5440          *
5441          * Spurious PCH underruns also occur during PCH enabling.
5442          */
5443         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5444                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5445         if (intel_crtc->config->has_pch_encoder)
5446                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5447
5448         if (intel_crtc->config->has_pch_encoder)
5449                 intel_prepare_shared_dpll(intel_crtc);
5450
5451         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5452                 intel_dp_set_m_n(intel_crtc, M1_N1);
5453
5454         intel_set_pipe_timings(intel_crtc);
5455         intel_set_pipe_src_size(intel_crtc);
5456
5457         if (intel_crtc->config->has_pch_encoder) {
5458                 intel_cpu_transcoder_set_m_n(intel_crtc,
5459                                      &intel_crtc->config->fdi_m_n, NULL);
5460         }
5461
5462         ironlake_set_pipeconf(crtc);
5463
5464         intel_crtc->active = true;
5465
5466         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5467
5468         if (intel_crtc->config->has_pch_encoder) {
5469                 /* Note: FDI PLL enabling _must_ be done before we enable the
5470                  * cpu pipes, hence this is separate from all the other fdi/pch
5471                  * enabling. */
5472                 ironlake_fdi_pll_enable(intel_crtc);
5473         } else {
5474                 assert_fdi_tx_disabled(dev_priv, pipe);
5475                 assert_fdi_rx_disabled(dev_priv, pipe);
5476         }
5477
5478         ironlake_pfit_enable(intel_crtc);
5479
5480         /*
5481          * On ILK+ LUT must be loaded before the pipe is running but with
5482          * clocks enabled
5483          */
5484         intel_color_load_luts(&pipe_config->base);
5485
5486         if (dev_priv->display.initial_watermarks != NULL)
5487                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5488         intel_enable_pipe(pipe_config);
5489
5490         if (intel_crtc->config->has_pch_encoder)
5491                 ironlake_pch_enable(pipe_config);
5492
5493         assert_vblank_disabled(crtc);
5494         drm_crtc_vblank_on(crtc);
5495
5496         intel_encoders_enable(crtc, pipe_config, old_state);
5497
5498         if (HAS_PCH_CPT(dev_priv))
5499                 cpt_verify_modeset(dev, intel_crtc->pipe);
5500
5501         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5502         if (intel_crtc->config->has_pch_encoder)
5503                 intel_wait_for_vblank(dev_priv, pipe);
5504         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5505         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5506 }
5507
5508 /* IPS only exists on ULT machines and is tied to pipe A. */
5509 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5510 {
5511         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5512 }
5513
5514 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
5515                                             enum pipe pipe, bool apply)
5516 {
5517         u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
5518         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
5519
5520         if (apply)
5521                 val |= mask;
5522         else
5523                 val &= ~mask;
5524
5525         I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
5526 }
5527
5528 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
5529 {
5530         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5531         enum pipe pipe = crtc->pipe;
5532         uint32_t val;
5533
5534         val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
5535
5536         /* Program B credit equally to all pipes */
5537         val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
5538
5539         I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
5540 }
5541
5542 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5543                                 struct drm_atomic_state *old_state)
5544 {
5545         struct drm_crtc *crtc = pipe_config->base.crtc;
5546         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5548         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5549         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5550         struct intel_atomic_state *old_intel_state =
5551                 to_intel_atomic_state(old_state);
5552         bool psl_clkgate_wa;
5553
5554         if (WARN_ON(intel_crtc->active))
5555                 return;
5556
5557         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5558
5559         if (intel_crtc->config->shared_dpll)
5560                 intel_enable_shared_dpll(intel_crtc);
5561
5562         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5563                 intel_dp_set_m_n(intel_crtc, M1_N1);
5564
5565         if (!transcoder_is_dsi(cpu_transcoder))
5566                 intel_set_pipe_timings(intel_crtc);
5567
5568         intel_set_pipe_src_size(intel_crtc);
5569
5570         if (cpu_transcoder != TRANSCODER_EDP &&
5571             !transcoder_is_dsi(cpu_transcoder)) {
5572                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5573                            intel_crtc->config->pixel_multiplier - 1);
5574         }
5575
5576         if (intel_crtc->config->has_pch_encoder) {
5577                 intel_cpu_transcoder_set_m_n(intel_crtc,
5578                                      &intel_crtc->config->fdi_m_n, NULL);
5579         }
5580
5581         if (!transcoder_is_dsi(cpu_transcoder))
5582                 haswell_set_pipeconf(crtc);
5583
5584         haswell_set_pipemisc(crtc);
5585
5586         intel_color_set_csc(&pipe_config->base);
5587
5588         intel_crtc->active = true;
5589
5590         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5591
5592         if (!transcoder_is_dsi(cpu_transcoder))
5593                 intel_ddi_enable_pipe_clock(pipe_config);
5594
5595         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
5596         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
5597                          intel_crtc->config->pch_pfit.enabled;
5598         if (psl_clkgate_wa)
5599                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
5600
5601         if (INTEL_GEN(dev_priv) >= 9)
5602                 skylake_pfit_enable(intel_crtc);
5603         else
5604                 ironlake_pfit_enable(intel_crtc);
5605
5606         /*
5607          * On ILK+ LUT must be loaded before the pipe is running but with
5608          * clocks enabled
5609          */
5610         intel_color_load_luts(&pipe_config->base);
5611
5612         intel_ddi_set_pipe_settings(pipe_config);
5613         if (!transcoder_is_dsi(cpu_transcoder))
5614                 intel_ddi_enable_transcoder_func(pipe_config);
5615
5616         if (dev_priv->display.initial_watermarks != NULL)
5617                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5618
5619         if (INTEL_GEN(dev_priv) >= 11)
5620                 icl_pipe_mbus_enable(intel_crtc);
5621
5622         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5623         if (!transcoder_is_dsi(cpu_transcoder))
5624                 intel_enable_pipe(pipe_config);
5625
5626         if (intel_crtc->config->has_pch_encoder)
5627                 lpt_pch_enable(pipe_config);
5628
5629         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5630                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5631
5632         assert_vblank_disabled(crtc);
5633         drm_crtc_vblank_on(crtc);
5634
5635         intel_encoders_enable(crtc, pipe_config, old_state);
5636
5637         if (psl_clkgate_wa) {
5638                 intel_wait_for_vblank(dev_priv, pipe);
5639                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
5640         }
5641
5642         /* If we change the relative order between pipe/planes enabling, we need
5643          * to change the workaround. */
5644         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5645         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5646                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5647                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5648         }
5649 }
5650
5651 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5652 {
5653         struct drm_device *dev = crtc->base.dev;
5654         struct drm_i915_private *dev_priv = to_i915(dev);
5655         int pipe = crtc->pipe;
5656
5657         /* To avoid upsetting the power well on haswell only disable the pfit if
5658          * it's in use. The hw state code will make sure we get this right. */
5659         if (force || crtc->config->pch_pfit.enabled) {
5660                 I915_WRITE(PF_CTL(pipe), 0);
5661                 I915_WRITE(PF_WIN_POS(pipe), 0);
5662                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5663         }
5664 }
5665
5666 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5667                                   struct drm_atomic_state *old_state)
5668 {
5669         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5670         struct drm_device *dev = crtc->dev;
5671         struct drm_i915_private *dev_priv = to_i915(dev);
5672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5673         int pipe = intel_crtc->pipe;
5674
5675         /*
5676          * Sometimes spurious CPU pipe underruns happen when the
5677          * pipe is already disabled, but FDI RX/TX is still enabled.
5678          * Happens at least with VGA+HDMI cloning. Suppress them.
5679          */
5680         if (intel_crtc->config->has_pch_encoder) {
5681                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5682                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5683         }
5684
5685         intel_encoders_disable(crtc, old_crtc_state, old_state);
5686
5687         drm_crtc_vblank_off(crtc);
5688         assert_vblank_disabled(crtc);
5689
5690         intel_disable_pipe(old_crtc_state);
5691
5692         ironlake_pfit_disable(intel_crtc, false);
5693
5694         if (intel_crtc->config->has_pch_encoder)
5695                 ironlake_fdi_disable(crtc);
5696
5697         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5698
5699         if (intel_crtc->config->has_pch_encoder) {
5700                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5701
5702                 if (HAS_PCH_CPT(dev_priv)) {
5703                         i915_reg_t reg;
5704                         u32 temp;
5705
5706                         /* disable TRANS_DP_CTL */
5707                         reg = TRANS_DP_CTL(pipe);
5708                         temp = I915_READ(reg);
5709                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5710                                   TRANS_DP_PORT_SEL_MASK);
5711                         temp |= TRANS_DP_PORT_SEL_NONE;
5712                         I915_WRITE(reg, temp);
5713
5714                         /* disable DPLL_SEL */
5715                         temp = I915_READ(PCH_DPLL_SEL);
5716                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5717                         I915_WRITE(PCH_DPLL_SEL, temp);
5718                 }
5719
5720                 ironlake_fdi_pll_disable(intel_crtc);
5721         }
5722
5723         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5724         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5725 }
5726
5727 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5728                                  struct drm_atomic_state *old_state)
5729 {
5730         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5731         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5733         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5734
5735         intel_encoders_disable(crtc, old_crtc_state, old_state);
5736
5737         drm_crtc_vblank_off(crtc);
5738         assert_vblank_disabled(crtc);
5739
5740         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5741         if (!transcoder_is_dsi(cpu_transcoder))
5742                 intel_disable_pipe(old_crtc_state);
5743
5744         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5745                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5746
5747         if (!transcoder_is_dsi(cpu_transcoder))
5748                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5749
5750         if (INTEL_GEN(dev_priv) >= 9)
5751                 skylake_scaler_disable(intel_crtc);
5752         else
5753                 ironlake_pfit_disable(intel_crtc, false);
5754
5755         if (!transcoder_is_dsi(cpu_transcoder))
5756                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5757
5758         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5759 }
5760
5761 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5762 {
5763         struct drm_device *dev = crtc->base.dev;
5764         struct drm_i915_private *dev_priv = to_i915(dev);
5765         struct intel_crtc_state *pipe_config = crtc->config;
5766
5767         if (!pipe_config->gmch_pfit.control)
5768                 return;
5769
5770         /*
5771          * The panel fitter should only be adjusted whilst the pipe is disabled,
5772          * according to register description and PRM.
5773          */
5774         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5775         assert_pipe_disabled(dev_priv, crtc->pipe);
5776
5777         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5778         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5779
5780         /* Border color in case we don't scale up to the full screen. Black by
5781          * default, change to something else for debugging. */
5782         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5783 }
5784
5785 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5786 {
5787         switch (port) {
5788         case PORT_A:
5789                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5790         case PORT_B:
5791                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5792         case PORT_C:
5793                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5794         case PORT_D:
5795                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5796         case PORT_E:
5797                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5798         case PORT_F:
5799                 return POWER_DOMAIN_PORT_DDI_F_LANES;
5800         default:
5801                 MISSING_CASE(port);
5802                 return POWER_DOMAIN_PORT_OTHER;
5803         }
5804 }
5805
5806 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5807                                   struct intel_crtc_state *crtc_state)
5808 {
5809         struct drm_device *dev = crtc->dev;
5810         struct drm_i915_private *dev_priv = to_i915(dev);
5811         struct drm_encoder *encoder;
5812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813         enum pipe pipe = intel_crtc->pipe;
5814         u64 mask;
5815         enum transcoder transcoder = crtc_state->cpu_transcoder;
5816
5817         if (!crtc_state->base.active)
5818                 return 0;
5819
5820         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
5821         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
5822         if (crtc_state->pch_pfit.enabled ||
5823             crtc_state->pch_pfit.force_thru)
5824                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5825
5826         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5827                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5828
5829                 mask |= BIT_ULL(intel_encoder->power_domain);
5830         }
5831
5832         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5833                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
5834
5835         if (crtc_state->shared_dpll)
5836                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5837
5838         return mask;
5839 }
5840
5841 static u64
5842 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5843                                struct intel_crtc_state *crtc_state)
5844 {
5845         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847         enum intel_display_power_domain domain;
5848         u64 domains, new_domains, old_domains;
5849
5850         old_domains = intel_crtc->enabled_power_domains;
5851         intel_crtc->enabled_power_domains = new_domains =
5852                 get_crtc_power_domains(crtc, crtc_state);
5853
5854         domains = new_domains & ~old_domains;
5855
5856         for_each_power_domain(domain, domains)
5857                 intel_display_power_get(dev_priv, domain);
5858
5859         return old_domains & ~new_domains;
5860 }
5861
5862 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5863                                       u64 domains)
5864 {
5865         enum intel_display_power_domain domain;
5866
5867         for_each_power_domain(domain, domains)
5868                 intel_display_power_put(dev_priv, domain);
5869 }
5870
5871 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5872                                    struct drm_atomic_state *old_state)
5873 {
5874         struct intel_atomic_state *old_intel_state =
5875                 to_intel_atomic_state(old_state);
5876         struct drm_crtc *crtc = pipe_config->base.crtc;
5877         struct drm_device *dev = crtc->dev;
5878         struct drm_i915_private *dev_priv = to_i915(dev);
5879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5880         int pipe = intel_crtc->pipe;
5881
5882         if (WARN_ON(intel_crtc->active))
5883                 return;
5884
5885         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5886                 intel_dp_set_m_n(intel_crtc, M1_N1);
5887
5888         intel_set_pipe_timings(intel_crtc);
5889         intel_set_pipe_src_size(intel_crtc);
5890
5891         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5892                 struct drm_i915_private *dev_priv = to_i915(dev);
5893
5894                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5895                 I915_WRITE(CHV_CANVAS(pipe), 0);
5896         }
5897
5898         i9xx_set_pipeconf(intel_crtc);
5899
5900         intel_crtc->active = true;
5901
5902         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5903
5904         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5905
5906         if (IS_CHERRYVIEW(dev_priv)) {
5907                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5908                 chv_enable_pll(intel_crtc, intel_crtc->config);
5909         } else {
5910                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5911                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5912         }
5913
5914         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5915
5916         i9xx_pfit_enable(intel_crtc);
5917
5918         intel_color_load_luts(&pipe_config->base);
5919
5920         dev_priv->display.initial_watermarks(old_intel_state,
5921                                              pipe_config);
5922         intel_enable_pipe(pipe_config);
5923
5924         assert_vblank_disabled(crtc);
5925         drm_crtc_vblank_on(crtc);
5926
5927         intel_encoders_enable(crtc, pipe_config, old_state);
5928 }
5929
5930 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5931 {
5932         struct drm_device *dev = crtc->base.dev;
5933         struct drm_i915_private *dev_priv = to_i915(dev);
5934
5935         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5936         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5937 }
5938
5939 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5940                              struct drm_atomic_state *old_state)
5941 {
5942         struct intel_atomic_state *old_intel_state =
5943                 to_intel_atomic_state(old_state);
5944         struct drm_crtc *crtc = pipe_config->base.crtc;
5945         struct drm_device *dev = crtc->dev;
5946         struct drm_i915_private *dev_priv = to_i915(dev);
5947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5948         enum pipe pipe = intel_crtc->pipe;
5949
5950         if (WARN_ON(intel_crtc->active))
5951                 return;
5952
5953         i9xx_set_pll_dividers(intel_crtc);
5954
5955         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5956                 intel_dp_set_m_n(intel_crtc, M1_N1);
5957
5958         intel_set_pipe_timings(intel_crtc);
5959         intel_set_pipe_src_size(intel_crtc);
5960
5961         i9xx_set_pipeconf(intel_crtc);
5962
5963         intel_crtc->active = true;
5964
5965         if (!IS_GEN2(dev_priv))
5966                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5967
5968         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5969
5970         i9xx_enable_pll(intel_crtc, pipe_config);
5971
5972         i9xx_pfit_enable(intel_crtc);
5973
5974         intel_color_load_luts(&pipe_config->base);
5975
5976         if (dev_priv->display.initial_watermarks != NULL)
5977                 dev_priv->display.initial_watermarks(old_intel_state,
5978                                                      intel_crtc->config);
5979         else
5980                 intel_update_watermarks(intel_crtc);
5981         intel_enable_pipe(pipe_config);
5982
5983         assert_vblank_disabled(crtc);
5984         drm_crtc_vblank_on(crtc);
5985
5986         intel_encoders_enable(crtc, pipe_config, old_state);
5987 }
5988
5989 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5990 {
5991         struct drm_device *dev = crtc->base.dev;
5992         struct drm_i915_private *dev_priv = to_i915(dev);
5993
5994         if (!crtc->config->gmch_pfit.control)
5995                 return;
5996
5997         assert_pipe_disabled(dev_priv, crtc->pipe);
5998
5999         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6000                          I915_READ(PFIT_CONTROL));
6001         I915_WRITE(PFIT_CONTROL, 0);
6002 }
6003
6004 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6005                               struct drm_atomic_state *old_state)
6006 {
6007         struct drm_crtc *crtc = old_crtc_state->base.crtc;
6008         struct drm_device *dev = crtc->dev;
6009         struct drm_i915_private *dev_priv = to_i915(dev);
6010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6011         int pipe = intel_crtc->pipe;
6012
6013         /*
6014          * On gen2 planes are double buffered but the pipe isn't, so we must
6015          * wait for planes to fully turn off before disabling the pipe.
6016          */
6017         if (IS_GEN2(dev_priv))
6018                 intel_wait_for_vblank(dev_priv, pipe);
6019
6020         intel_encoders_disable(crtc, old_crtc_state, old_state);
6021
6022         drm_crtc_vblank_off(crtc);
6023         assert_vblank_disabled(crtc);
6024
6025         intel_disable_pipe(old_crtc_state);
6026
6027         i9xx_pfit_disable(intel_crtc);
6028
6029         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6030
6031         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6032                 if (IS_CHERRYVIEW(dev_priv))
6033                         chv_disable_pll(dev_priv, pipe);
6034                 else if (IS_VALLEYVIEW(dev_priv))
6035                         vlv_disable_pll(dev_priv, pipe);
6036                 else
6037                         i9xx_disable_pll(intel_crtc);
6038         }
6039
6040         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6041
6042         if (!IS_GEN2(dev_priv))
6043                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6044
6045         if (!dev_priv->display.initial_watermarks)
6046                 intel_update_watermarks(intel_crtc);
6047
6048         /* clock the pipe down to 640x480@60 to potentially save power */
6049         if (IS_I830(dev_priv))
6050                 i830_enable_pipe(dev_priv, pipe);
6051 }
6052
6053 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
6054                                         struct drm_modeset_acquire_ctx *ctx)
6055 {
6056         struct intel_encoder *encoder;
6057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6058         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6059         enum intel_display_power_domain domain;
6060         struct intel_plane *plane;
6061         u64 domains;
6062         struct drm_atomic_state *state;
6063         struct intel_crtc_state *crtc_state;
6064         int ret;
6065
6066         if (!intel_crtc->active)
6067                 return;
6068
6069         for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
6070                 const struct intel_plane_state *plane_state =
6071                         to_intel_plane_state(plane->base.state);
6072
6073                 if (plane_state->base.visible)
6074                         intel_plane_disable_noatomic(intel_crtc, plane);
6075         }
6076
6077         state = drm_atomic_state_alloc(crtc->dev);
6078         if (!state) {
6079                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6080                               crtc->base.id, crtc->name);
6081                 return;
6082         }
6083
6084         state->acquire_ctx = ctx;
6085
6086         /* Everything's already locked, -EDEADLK can't happen. */
6087         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6088         ret = drm_atomic_add_affected_connectors(state, crtc);
6089
6090         WARN_ON(IS_ERR(crtc_state) || ret);
6091
6092         dev_priv->display.crtc_disable(crtc_state, state);
6093
6094         drm_atomic_state_put(state);
6095
6096         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6097                       crtc->base.id, crtc->name);
6098
6099         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6100         crtc->state->active = false;
6101         intel_crtc->active = false;
6102         crtc->enabled = false;
6103         crtc->state->connector_mask = 0;
6104         crtc->state->encoder_mask = 0;
6105
6106         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6107                 encoder->base.crtc = NULL;
6108
6109         intel_fbc_disable(intel_crtc);
6110         intel_update_watermarks(intel_crtc);
6111         intel_disable_shared_dpll(intel_crtc);
6112
6113         domains = intel_crtc->enabled_power_domains;
6114         for_each_power_domain(domain, domains)
6115                 intel_display_power_put(dev_priv, domain);
6116         intel_crtc->enabled_power_domains = 0;
6117
6118         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6119         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6120         dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
6121 }
6122
6123 /*
6124  * turn all crtc's off, but do not adjust state
6125  * This has to be paired with a call to intel_modeset_setup_hw_state.
6126  */
6127 int intel_display_suspend(struct drm_device *dev)
6128 {
6129         struct drm_i915_private *dev_priv = to_i915(dev);
6130         struct drm_atomic_state *state;
6131         int ret;
6132
6133         state = drm_atomic_helper_suspend(dev);
6134         ret = PTR_ERR_OR_ZERO(state);
6135         if (ret)
6136                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6137         else
6138                 dev_priv->modeset_restore_state = state;
6139         return ret;
6140 }
6141
6142 void intel_encoder_destroy(struct drm_encoder *encoder)
6143 {
6144         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6145
6146         drm_encoder_cleanup(encoder);
6147         kfree(intel_encoder);
6148 }
6149
6150 /* Cross check the actual hw state with our own modeset state tracking (and it's
6151  * internal consistency). */
6152 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6153                                          struct drm_connector_state *conn_state)
6154 {
6155         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6156
6157         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6158                       connector->base.base.id,
6159                       connector->base.name);
6160
6161         if (connector->get_hw_state(connector)) {
6162                 struct intel_encoder *encoder = connector->encoder;
6163
6164                 I915_STATE_WARN(!crtc_state,
6165                          "connector enabled without attached crtc\n");
6166
6167                 if (!crtc_state)
6168                         return;
6169
6170                 I915_STATE_WARN(!crtc_state->active,
6171                       "connector is active, but attached crtc isn't\n");
6172
6173                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6174                         return;
6175
6176                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6177                         "atomic encoder doesn't match attached encoder\n");
6178
6179                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6180                         "attached encoder crtc differs from connector crtc\n");
6181         } else {
6182                 I915_STATE_WARN(crtc_state && crtc_state->active,
6183                         "attached crtc is active, but connector isn't\n");
6184                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6185                         "best encoder set without crtc!\n");
6186         }
6187 }
6188
6189 int intel_connector_init(struct intel_connector *connector)
6190 {
6191         struct intel_digital_connector_state *conn_state;
6192
6193         /*
6194          * Allocate enough memory to hold intel_digital_connector_state,
6195          * This might be a few bytes too many, but for connectors that don't
6196          * need it we'll free the state and allocate a smaller one on the first
6197          * succesful commit anyway.
6198          */
6199         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6200         if (!conn_state)
6201                 return -ENOMEM;
6202
6203         __drm_atomic_helper_connector_reset(&connector->base,
6204                                             &conn_state->base);
6205
6206         return 0;
6207 }
6208
6209 struct intel_connector *intel_connector_alloc(void)
6210 {
6211         struct intel_connector *connector;
6212
6213         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6214         if (!connector)
6215                 return NULL;
6216
6217         if (intel_connector_init(connector) < 0) {
6218                 kfree(connector);
6219                 return NULL;
6220         }
6221
6222         return connector;
6223 }
6224
6225 /*
6226  * Free the bits allocated by intel_connector_alloc.
6227  * This should only be used after intel_connector_alloc has returned
6228  * successfully, and before drm_connector_init returns successfully.
6229  * Otherwise the destroy callbacks for the connector and the state should
6230  * take care of proper cleanup/free
6231  */
6232 void intel_connector_free(struct intel_connector *connector)
6233 {
6234         kfree(to_intel_digital_connector_state(connector->base.state));
6235         kfree(connector);
6236 }
6237
6238 /* Simple connector->get_hw_state implementation for encoders that support only
6239  * one connector and no cloning and hence the encoder state determines the state
6240  * of the connector. */
6241 bool intel_connector_get_hw_state(struct intel_connector *connector)
6242 {
6243         enum pipe pipe = 0;
6244         struct intel_encoder *encoder = connector->encoder;
6245
6246         return encoder->get_hw_state(encoder, &pipe);
6247 }
6248
6249 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6250 {
6251         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6252                 return crtc_state->fdi_lanes;
6253
6254         return 0;
6255 }
6256
6257 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6258                                      struct intel_crtc_state *pipe_config)
6259 {
6260         struct drm_i915_private *dev_priv = to_i915(dev);
6261         struct drm_atomic_state *state = pipe_config->base.state;
6262         struct intel_crtc *other_crtc;
6263         struct intel_crtc_state *other_crtc_state;
6264
6265         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6266                       pipe_name(pipe), pipe_config->fdi_lanes);
6267         if (pipe_config->fdi_lanes > 4) {
6268                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6269                               pipe_name(pipe), pipe_config->fdi_lanes);
6270                 return -EINVAL;
6271         }
6272
6273         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6274                 if (pipe_config->fdi_lanes > 2) {
6275                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6276                                       pipe_config->fdi_lanes);
6277                         return -EINVAL;
6278                 } else {
6279                         return 0;
6280                 }
6281         }
6282
6283         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6284                 return 0;
6285
6286         /* Ivybridge 3 pipe is really complicated */
6287         switch (pipe) {
6288         case PIPE_A:
6289                 return 0;
6290         case PIPE_B:
6291                 if (pipe_config->fdi_lanes <= 2)
6292                         return 0;
6293
6294                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6295                 other_crtc_state =
6296                         intel_atomic_get_crtc_state(state, other_crtc);
6297                 if (IS_ERR(other_crtc_state))
6298                         return PTR_ERR(other_crtc_state);
6299
6300                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6301                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6302                                       pipe_name(pipe), pipe_config->fdi_lanes);
6303                         return -EINVAL;
6304                 }
6305                 return 0;
6306         case PIPE_C:
6307                 if (pipe_config->fdi_lanes > 2) {
6308                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6309                                       pipe_name(pipe), pipe_config->fdi_lanes);
6310                         return -EINVAL;
6311                 }
6312
6313                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6314                 other_crtc_state =
6315                         intel_atomic_get_crtc_state(state, other_crtc);
6316                 if (IS_ERR(other_crtc_state))
6317                         return PTR_ERR(other_crtc_state);
6318
6319                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6320                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6321                         return -EINVAL;
6322                 }
6323                 return 0;
6324         default:
6325                 BUG();
6326         }
6327 }
6328
6329 #define RETRY 1
6330 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6331                                        struct intel_crtc_state *pipe_config)
6332 {
6333         struct drm_device *dev = intel_crtc->base.dev;
6334         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6335         int lane, link_bw, fdi_dotclock, ret;
6336         bool needs_recompute = false;
6337
6338 retry:
6339         /* FDI is a binary signal running at ~2.7GHz, encoding
6340          * each output octet as 10 bits. The actual frequency
6341          * is stored as a divider into a 100MHz clock, and the
6342          * mode pixel clock is stored in units of 1KHz.
6343          * Hence the bw of each lane in terms of the mode signal
6344          * is:
6345          */
6346         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6347
6348         fdi_dotclock = adjusted_mode->crtc_clock;
6349
6350         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6351                                            pipe_config->pipe_bpp);
6352
6353         pipe_config->fdi_lanes = lane;
6354
6355         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6356                                link_bw, &pipe_config->fdi_m_n, false);
6357
6358         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6359         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6360                 pipe_config->pipe_bpp -= 2*3;
6361                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6362                               pipe_config->pipe_bpp);
6363                 needs_recompute = true;
6364                 pipe_config->bw_constrained = true;
6365
6366                 goto retry;
6367         }
6368
6369         if (needs_recompute)
6370                 return RETRY;
6371
6372         return ret;
6373 }
6374
6375 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
6376 {
6377         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6378         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6379
6380         /* IPS only exists on ULT machines and is tied to pipe A. */
6381         if (!hsw_crtc_supports_ips(crtc))
6382                 return false;
6383
6384         if (!i915_modparams.enable_ips)
6385                 return false;
6386
6387         if (crtc_state->pipe_bpp > 24)
6388                 return false;
6389
6390         /*
6391          * We compare against max which means we must take
6392          * the increased cdclk requirement into account when
6393          * calculating the new cdclk.
6394          *
6395          * Should measure whether using a lower cdclk w/o IPS
6396          */
6397         if (IS_BROADWELL(dev_priv) &&
6398             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
6399                 return false;
6400
6401         return true;
6402 }
6403
6404 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
6405 {
6406         struct drm_i915_private *dev_priv =
6407                 to_i915(crtc_state->base.crtc->dev);
6408         struct intel_atomic_state *intel_state =
6409                 to_intel_atomic_state(crtc_state->base.state);
6410
6411         if (!hsw_crtc_state_ips_capable(crtc_state))
6412                 return false;
6413
6414         if (crtc_state->ips_force_disable)
6415                 return false;
6416
6417         /* IPS should be fine as long as at least one plane is enabled. */
6418         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
6419                 return false;
6420
6421         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
6422         if (IS_BROADWELL(dev_priv) &&
6423             crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
6424                 return false;
6425
6426         return true;
6427 }
6428
6429 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6430 {
6431         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6432
6433         /* GDG double wide on either pipe, otherwise pipe A only */
6434         return INTEL_GEN(dev_priv) < 4 &&
6435                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6436 }
6437
6438 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6439 {
6440         uint32_t pixel_rate;
6441
6442         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6443
6444         /*
6445          * We only use IF-ID interlacing. If we ever use
6446          * PF-ID we'll need to adjust the pixel_rate here.
6447          */
6448
6449         if (pipe_config->pch_pfit.enabled) {
6450                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6451                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6452
6453                 pipe_w = pipe_config->pipe_src_w;
6454                 pipe_h = pipe_config->pipe_src_h;
6455
6456                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6457                 pfit_h = pfit_size & 0xFFFF;
6458                 if (pipe_w < pfit_w)
6459                         pipe_w = pfit_w;
6460                 if (pipe_h < pfit_h)
6461                         pipe_h = pfit_h;
6462
6463                 if (WARN_ON(!pfit_w || !pfit_h))
6464                         return pixel_rate;
6465
6466                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6467                                      pfit_w * pfit_h);
6468         }
6469
6470         return pixel_rate;
6471 }
6472
6473 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6474 {
6475         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6476
6477         if (HAS_GMCH_DISPLAY(dev_priv))
6478                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6479                 crtc_state->pixel_rate =
6480                         crtc_state->base.adjusted_mode.crtc_clock;
6481         else
6482                 crtc_state->pixel_rate =
6483                         ilk_pipe_pixel_rate(crtc_state);
6484 }
6485
6486 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6487                                      struct intel_crtc_state *pipe_config)
6488 {
6489         struct drm_device *dev = crtc->base.dev;
6490         struct drm_i915_private *dev_priv = to_i915(dev);
6491         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6492         int clock_limit = dev_priv->max_dotclk_freq;
6493
6494         if (INTEL_GEN(dev_priv) < 4) {
6495                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6496
6497                 /*
6498                  * Enable double wide mode when the dot clock
6499                  * is > 90% of the (display) core speed.
6500                  */
6501                 if (intel_crtc_supports_double_wide(crtc) &&
6502                     adjusted_mode->crtc_clock > clock_limit) {
6503                         clock_limit = dev_priv->max_dotclk_freq;
6504                         pipe_config->double_wide = true;
6505                 }
6506         }
6507
6508         if (adjusted_mode->crtc_clock > clock_limit) {
6509                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6510                               adjusted_mode->crtc_clock, clock_limit,
6511                               yesno(pipe_config->double_wide));
6512                 return -EINVAL;
6513         }
6514
6515         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6516                 /*
6517                  * There is only one pipe CSC unit per pipe, and we need that
6518                  * for output conversion from RGB->YCBCR. So if CTM is already
6519                  * applied we can't support YCBCR420 output.
6520                  */
6521                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6522                 return -EINVAL;
6523         }
6524
6525         /*
6526          * Pipe horizontal size must be even in:
6527          * - DVO ganged mode
6528          * - LVDS dual channel mode
6529          * - Double wide pipe
6530          */
6531         if (pipe_config->pipe_src_w & 1) {
6532                 if (pipe_config->double_wide) {
6533                         DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
6534                         return -EINVAL;
6535                 }
6536
6537                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6538                     intel_is_dual_link_lvds(dev)) {
6539                         DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
6540                         return -EINVAL;
6541                 }
6542         }
6543
6544         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6545          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6546          */
6547         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6548                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6549                 return -EINVAL;
6550
6551         intel_crtc_compute_pixel_rate(pipe_config);
6552
6553         if (pipe_config->has_pch_encoder)
6554                 return ironlake_fdi_compute_config(crtc, pipe_config);
6555
6556         return 0;
6557 }
6558
6559 static void
6560 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6561 {
6562         while (*num > DATA_LINK_M_N_MASK ||
6563                *den > DATA_LINK_M_N_MASK) {
6564                 *num >>= 1;
6565                 *den >>= 1;
6566         }
6567 }
6568
6569 static void compute_m_n(unsigned int m, unsigned int n,
6570                         uint32_t *ret_m, uint32_t *ret_n,
6571                         bool reduce_m_n)
6572 {
6573         /*
6574          * Reduce M/N as much as possible without loss in precision. Several DP
6575          * dongles in particular seem to be fussy about too large *link* M/N
6576          * values. The passed in values are more likely to have the least
6577          * significant bits zero than M after rounding below, so do this first.
6578          */
6579         if (reduce_m_n) {
6580                 while ((m & 1) == 0 && (n & 1) == 0) {
6581                         m >>= 1;
6582                         n >>= 1;
6583                 }
6584         }
6585
6586         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6587         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6588         intel_reduce_m_n_ratio(ret_m, ret_n);
6589 }
6590
6591 void
6592 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6593                        int pixel_clock, int link_clock,
6594                        struct intel_link_m_n *m_n,
6595                        bool reduce_m_n)
6596 {
6597         m_n->tu = 64;
6598
6599         compute_m_n(bits_per_pixel * pixel_clock,
6600                     link_clock * nlanes * 8,
6601                     &m_n->gmch_m, &m_n->gmch_n,
6602                     reduce_m_n);
6603
6604         compute_m_n(pixel_clock, link_clock,
6605                     &m_n->link_m, &m_n->link_n,
6606                     reduce_m_n);
6607 }
6608
6609 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6610 {
6611         if (i915_modparams.panel_use_ssc >= 0)
6612                 return i915_modparams.panel_use_ssc != 0;
6613         return dev_priv->vbt.lvds_use_ssc
6614                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6615 }
6616
6617 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6618 {
6619         return (1 << dpll->n) << 16 | dpll->m2;
6620 }
6621
6622 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6623 {
6624         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6625 }
6626
6627 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6628                                      struct intel_crtc_state *crtc_state,
6629                                      struct dpll *reduced_clock)
6630 {
6631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6632         u32 fp, fp2 = 0;
6633
6634         if (IS_PINEVIEW(dev_priv)) {
6635                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6636                 if (reduced_clock)
6637                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6638         } else {
6639                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6640                 if (reduced_clock)
6641                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6642         }
6643
6644         crtc_state->dpll_hw_state.fp0 = fp;
6645
6646         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6647             reduced_clock) {
6648                 crtc_state->dpll_hw_state.fp1 = fp2;
6649         } else {
6650                 crtc_state->dpll_hw_state.fp1 = fp;
6651         }
6652 }
6653
6654 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6655                 pipe)
6656 {
6657         u32 reg_val;
6658
6659         /*
6660          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6661          * and set it to a reasonable value instead.
6662          */
6663         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6664         reg_val &= 0xffffff00;
6665         reg_val |= 0x00000030;
6666         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6667
6668         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6669         reg_val &= 0x00ffffff;
6670         reg_val |= 0x8c000000;
6671         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6672
6673         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6674         reg_val &= 0xffffff00;
6675         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6676
6677         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6678         reg_val &= 0x00ffffff;
6679         reg_val |= 0xb0000000;
6680         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6681 }
6682
6683 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6684                                          struct intel_link_m_n *m_n)
6685 {
6686         struct drm_device *dev = crtc->base.dev;
6687         struct drm_i915_private *dev_priv = to_i915(dev);
6688         int pipe = crtc->pipe;
6689
6690         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6691         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6692         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6693         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6694 }
6695
6696 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6697                                          struct intel_link_m_n *m_n,
6698                                          struct intel_link_m_n *m2_n2)
6699 {
6700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6701         int pipe = crtc->pipe;
6702         enum transcoder transcoder = crtc->config->cpu_transcoder;
6703
6704         if (INTEL_GEN(dev_priv) >= 5) {
6705                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6706                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6707                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6708                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6709                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6710                  * for gen < 8) and if DRRS is supported (to make sure the
6711                  * registers are not unnecessarily accessed).
6712                  */
6713                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6714                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6715                         I915_WRITE(PIPE_DATA_M2(transcoder),
6716                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6717                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6718                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6719                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6720                 }
6721         } else {
6722                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6723                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6724                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6725                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6726         }
6727 }
6728
6729 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6730 {
6731         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6732
6733         if (m_n == M1_N1) {
6734                 dp_m_n = &crtc->config->dp_m_n;
6735                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6736         } else if (m_n == M2_N2) {
6737
6738                 /*
6739                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6740                  * needs to be programmed into M1_N1.
6741                  */
6742                 dp_m_n = &crtc->config->dp_m2_n2;
6743         } else {
6744                 DRM_ERROR("Unsupported divider value\n");
6745                 return;
6746         }
6747
6748         if (crtc->config->has_pch_encoder)
6749                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6750         else
6751                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6752 }
6753
6754 static void vlv_compute_dpll(struct intel_crtc *crtc,
6755                              struct intel_crtc_state *pipe_config)
6756 {
6757         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6758                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6759         if (crtc->pipe != PIPE_A)
6760                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6761
6762         /* DPLL not used with DSI, but still need the rest set up */
6763         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6764                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6765                         DPLL_EXT_BUFFER_ENABLE_VLV;
6766
6767         pipe_config->dpll_hw_state.dpll_md =
6768                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6769 }
6770
6771 static void chv_compute_dpll(struct intel_crtc *crtc,
6772                              struct intel_crtc_state *pipe_config)
6773 {
6774         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6775                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6776         if (crtc->pipe != PIPE_A)
6777                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6778
6779         /* DPLL not used with DSI, but still need the rest set up */
6780         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6781                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6782
6783         pipe_config->dpll_hw_state.dpll_md =
6784                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6785 }
6786
6787 static void vlv_prepare_pll(struct intel_crtc *crtc,
6788                             const struct intel_crtc_state *pipe_config)
6789 {
6790         struct drm_device *dev = crtc->base.dev;
6791         struct drm_i915_private *dev_priv = to_i915(dev);
6792         enum pipe pipe = crtc->pipe;
6793         u32 mdiv;
6794         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6795         u32 coreclk, reg_val;
6796
6797         /* Enable Refclk */
6798         I915_WRITE(DPLL(pipe),
6799                    pipe_config->dpll_hw_state.dpll &
6800                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6801
6802         /* No need to actually set up the DPLL with DSI */
6803         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6804                 return;
6805
6806         mutex_lock(&dev_priv->sb_lock);
6807
6808         bestn = pipe_config->dpll.n;
6809         bestm1 = pipe_config->dpll.m1;
6810         bestm2 = pipe_config->dpll.m2;
6811         bestp1 = pipe_config->dpll.p1;
6812         bestp2 = pipe_config->dpll.p2;
6813
6814         /* See eDP HDMI DPIO driver vbios notes doc */
6815
6816         /* PLL B needs special handling */
6817         if (pipe == PIPE_B)
6818                 vlv_pllb_recal_opamp(dev_priv, pipe);
6819
6820         /* Set up Tx target for periodic Rcomp update */
6821         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6822
6823         /* Disable target IRef on PLL */
6824         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6825         reg_val &= 0x00ffffff;
6826         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6827
6828         /* Disable fast lock */
6829         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6830
6831         /* Set idtafcrecal before PLL is enabled */
6832         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6833         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6834         mdiv |= ((bestn << DPIO_N_SHIFT));
6835         mdiv |= (1 << DPIO_K_SHIFT);
6836
6837         /*
6838          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6839          * but we don't support that).
6840          * Note: don't use the DAC post divider as it seems unstable.
6841          */
6842         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6843         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6844
6845         mdiv |= DPIO_ENABLE_CALIBRATION;
6846         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6847
6848         /* Set HBR and RBR LPF coefficients */
6849         if (pipe_config->port_clock == 162000 ||
6850             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6851             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6852                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6853                                  0x009f0003);
6854         else
6855                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6856                                  0x00d0000f);
6857
6858         if (intel_crtc_has_dp_encoder(pipe_config)) {
6859                 /* Use SSC source */
6860                 if (pipe == PIPE_A)
6861                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6862                                          0x0df40000);
6863                 else
6864                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6865                                          0x0df70000);
6866         } else { /* HDMI or VGA */
6867                 /* Use bend source */
6868                 if (pipe == PIPE_A)
6869                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6870                                          0x0df70000);
6871                 else
6872                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6873                                          0x0df40000);
6874         }
6875
6876         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6877         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6878         if (intel_crtc_has_dp_encoder(crtc->config))
6879                 coreclk |= 0x01000000;
6880         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6881
6882         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6883         mutex_unlock(&dev_priv->sb_lock);
6884 }
6885
6886 static void chv_prepare_pll(struct intel_crtc *crtc,
6887                             const struct intel_crtc_state *pipe_config)
6888 {
6889         struct drm_device *dev = crtc->base.dev;
6890         struct drm_i915_private *dev_priv = to_i915(dev);
6891         enum pipe pipe = crtc->pipe;
6892         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6893         u32 loopfilter, tribuf_calcntr;
6894         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6895         u32 dpio_val;
6896         int vco;
6897
6898         /* Enable Refclk and SSC */
6899         I915_WRITE(DPLL(pipe),
6900                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6901
6902         /* No need to actually set up the DPLL with DSI */
6903         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6904                 return;
6905
6906         bestn = pipe_config->dpll.n;
6907         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6908         bestm1 = pipe_config->dpll.m1;
6909         bestm2 = pipe_config->dpll.m2 >> 22;
6910         bestp1 = pipe_config->dpll.p1;
6911         bestp2 = pipe_config->dpll.p2;
6912         vco = pipe_config->dpll.vco;
6913         dpio_val = 0;
6914         loopfilter = 0;
6915
6916         mutex_lock(&dev_priv->sb_lock);
6917
6918         /* p1 and p2 divider */
6919         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6920                         5 << DPIO_CHV_S1_DIV_SHIFT |
6921                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6922                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6923                         1 << DPIO_CHV_K_DIV_SHIFT);
6924
6925         /* Feedback post-divider - m2 */
6926         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6927
6928         /* Feedback refclk divider - n and m1 */
6929         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6930                         DPIO_CHV_M1_DIV_BY_2 |
6931                         1 << DPIO_CHV_N_DIV_SHIFT);
6932
6933         /* M2 fraction division */
6934         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6935
6936         /* M2 fraction division enable */
6937         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6938         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6939         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6940         if (bestm2_frac)
6941                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6942         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6943
6944         /* Program digital lock detect threshold */
6945         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6946         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6947                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6948         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6949         if (!bestm2_frac)
6950                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6951         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6952
6953         /* Loop filter */
6954         if (vco == 5400000) {
6955                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6956                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6957                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6958                 tribuf_calcntr = 0x9;
6959         } else if (vco <= 6200000) {
6960                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6961                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6962                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6963                 tribuf_calcntr = 0x9;
6964         } else if (vco <= 6480000) {
6965                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6966                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6967                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6968                 tribuf_calcntr = 0x8;
6969         } else {
6970                 /* Not supported. Apply the same limits as in the max case */
6971                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6972                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6973                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6974                 tribuf_calcntr = 0;
6975         }
6976         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6977
6978         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6979         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6980         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6981         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6982
6983         /* AFC Recal */
6984         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6985                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6986                         DPIO_AFC_RECAL);
6987
6988         mutex_unlock(&dev_priv->sb_lock);
6989 }
6990
6991 /**
6992  * vlv_force_pll_on - forcibly enable just the PLL
6993  * @dev_priv: i915 private structure
6994  * @pipe: pipe PLL to enable
6995  * @dpll: PLL configuration
6996  *
6997  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6998  * in cases where we need the PLL enabled even when @pipe is not going to
6999  * be enabled.
7000  */
7001 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7002                      const struct dpll *dpll)
7003 {
7004         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7005         struct intel_crtc_state *pipe_config;
7006
7007         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7008         if (!pipe_config)
7009                 return -ENOMEM;
7010
7011         pipe_config->base.crtc = &crtc->base;
7012         pipe_config->pixel_multiplier = 1;
7013         pipe_config->dpll = *dpll;
7014
7015         if (IS_CHERRYVIEW(dev_priv)) {
7016                 chv_compute_dpll(crtc, pipe_config);
7017                 chv_prepare_pll(crtc, pipe_config);
7018                 chv_enable_pll(crtc, pipe_config);
7019         } else {
7020                 vlv_compute_dpll(crtc, pipe_config);
7021                 vlv_prepare_pll(crtc, pipe_config);
7022                 vlv_enable_pll(crtc, pipe_config);
7023         }
7024
7025         kfree(pipe_config);
7026
7027         return 0;
7028 }
7029
7030 /**
7031  * vlv_force_pll_off - forcibly disable just the PLL
7032  * @dev_priv: i915 private structure
7033  * @pipe: pipe PLL to disable
7034  *
7035  * Disable the PLL for @pipe. To be used in cases where we need
7036  * the PLL enabled even when @pipe is not going to be enabled.
7037  */
7038 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7039 {
7040         if (IS_CHERRYVIEW(dev_priv))
7041                 chv_disable_pll(dev_priv, pipe);
7042         else
7043                 vlv_disable_pll(dev_priv, pipe);
7044 }
7045
7046 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7047                               struct intel_crtc_state *crtc_state,
7048                               struct dpll *reduced_clock)
7049 {
7050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7051         u32 dpll;
7052         struct dpll *clock = &crtc_state->dpll;
7053
7054         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7055
7056         dpll = DPLL_VGA_MODE_DIS;
7057
7058         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7059                 dpll |= DPLLB_MODE_LVDS;
7060         else
7061                 dpll |= DPLLB_MODE_DAC_SERIAL;
7062
7063         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7064             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7065                 dpll |= (crtc_state->pixel_multiplier - 1)
7066                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7067         }
7068
7069         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7070             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
7071                 dpll |= DPLL_SDVO_HIGH_SPEED;
7072
7073         if (intel_crtc_has_dp_encoder(crtc_state))
7074                 dpll |= DPLL_SDVO_HIGH_SPEED;
7075
7076         /* compute bitmask from p1 value */
7077         if (IS_PINEVIEW(dev_priv))
7078                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7079         else {
7080                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7081                 if (IS_G4X(dev_priv) && reduced_clock)
7082                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7083         }
7084         switch (clock->p2) {
7085         case 5:
7086                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7087                 break;
7088         case 7:
7089                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7090                 break;
7091         case 10:
7092                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7093                 break;
7094         case 14:
7095                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7096                 break;
7097         }
7098         if (INTEL_GEN(dev_priv) >= 4)
7099                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7100
7101         if (crtc_state->sdvo_tv_clock)
7102                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7103         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7104                  intel_panel_use_ssc(dev_priv))
7105                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7106         else
7107                 dpll |= PLL_REF_INPUT_DREFCLK;
7108
7109         dpll |= DPLL_VCO_ENABLE;
7110         crtc_state->dpll_hw_state.dpll = dpll;
7111
7112         if (INTEL_GEN(dev_priv) >= 4) {
7113                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7114                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7115                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7116         }
7117 }
7118
7119 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7120                               struct intel_crtc_state *crtc_state,
7121                               struct dpll *reduced_clock)
7122 {
7123         struct drm_device *dev = crtc->base.dev;
7124         struct drm_i915_private *dev_priv = to_i915(dev);
7125         u32 dpll;
7126         struct dpll *clock = &crtc_state->dpll;
7127
7128         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7129
7130         dpll = DPLL_VGA_MODE_DIS;
7131
7132         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7133                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7134         } else {
7135                 if (clock->p1 == 2)
7136                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7137                 else
7138                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7139                 if (clock->p2 == 4)
7140                         dpll |= PLL_P2_DIVIDE_BY_4;
7141         }
7142
7143         if (!IS_I830(dev_priv) &&
7144             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7145                 dpll |= DPLL_DVO_2X_MODE;
7146
7147         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7148             intel_panel_use_ssc(dev_priv))
7149                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7150         else
7151                 dpll |= PLL_REF_INPUT_DREFCLK;
7152
7153         dpll |= DPLL_VCO_ENABLE;
7154         crtc_state->dpll_hw_state.dpll = dpll;
7155 }
7156
7157 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7158 {
7159         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7160         enum pipe pipe = intel_crtc->pipe;
7161         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7162         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7163         uint32_t crtc_vtotal, crtc_vblank_end;
7164         int vsyncshift = 0;
7165
7166         /* We need to be careful not to changed the adjusted mode, for otherwise
7167          * the hw state checker will get angry at the mismatch. */
7168         crtc_vtotal = adjusted_mode->crtc_vtotal;
7169         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7170
7171         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7172                 /* the chip adds 2 halflines automatically */
7173                 crtc_vtotal -= 1;
7174                 crtc_vblank_end -= 1;
7175
7176                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7177                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7178                 else
7179                         vsyncshift = adjusted_mode->crtc_hsync_start -
7180                                 adjusted_mode->crtc_htotal / 2;
7181                 if (vsyncshift < 0)
7182                         vsyncshift += adjusted_mode->crtc_htotal;
7183         }
7184
7185         if (INTEL_GEN(dev_priv) > 3)
7186                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7187
7188         I915_WRITE(HTOTAL(cpu_transcoder),
7189                    (adjusted_mode->crtc_hdisplay - 1) |
7190                    ((adjusted_mode->crtc_htotal - 1) << 16));
7191         I915_WRITE(HBLANK(cpu_transcoder),
7192                    (adjusted_mode->crtc_hblank_start - 1) |
7193                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7194         I915_WRITE(HSYNC(cpu_transcoder),
7195                    (adjusted_mode->crtc_hsync_start - 1) |
7196                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7197
7198         I915_WRITE(VTOTAL(cpu_transcoder),
7199                    (adjusted_mode->crtc_vdisplay - 1) |
7200                    ((crtc_vtotal - 1) << 16));
7201         I915_WRITE(VBLANK(cpu_transcoder),
7202                    (adjusted_mode->crtc_vblank_start - 1) |
7203                    ((crtc_vblank_end - 1) << 16));
7204         I915_WRITE(VSYNC(cpu_transcoder),
7205                    (adjusted_mode->crtc_vsync_start - 1) |
7206                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7207
7208         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7209          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7210          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7211          * bits. */
7212         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7213             (pipe == PIPE_B || pipe == PIPE_C))
7214                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7215
7216 }
7217
7218 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7219 {
7220         struct drm_device *dev = intel_crtc->base.dev;
7221         struct drm_i915_private *dev_priv = to_i915(dev);
7222         enum pipe pipe = intel_crtc->pipe;
7223
7224         /* pipesrc controls the size that is scaled from, which should
7225          * always be the user's requested size.
7226          */
7227         I915_WRITE(PIPESRC(pipe),
7228                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7229                    (intel_crtc->config->pipe_src_h - 1));
7230 }
7231
7232 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7233                                    struct intel_crtc_state *pipe_config)
7234 {
7235         struct drm_device *dev = crtc->base.dev;
7236         struct drm_i915_private *dev_priv = to_i915(dev);
7237         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7238         uint32_t tmp;
7239
7240         tmp = I915_READ(HTOTAL(cpu_transcoder));
7241         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7242         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7243         tmp = I915_READ(HBLANK(cpu_transcoder));
7244         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7245         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7246         tmp = I915_READ(HSYNC(cpu_transcoder));
7247         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7248         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7249
7250         tmp = I915_READ(VTOTAL(cpu_transcoder));
7251         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7252         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7253         tmp = I915_READ(VBLANK(cpu_transcoder));
7254         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7255         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7256         tmp = I915_READ(VSYNC(cpu_transcoder));
7257         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7258         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7259
7260         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7261                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7262                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7263                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7264         }
7265 }
7266
7267 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7268                                     struct intel_crtc_state *pipe_config)
7269 {
7270         struct drm_device *dev = crtc->base.dev;
7271         struct drm_i915_private *dev_priv = to_i915(dev);
7272         u32 tmp;
7273
7274         tmp = I915_READ(PIPESRC(crtc->pipe));
7275         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7276         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7277
7278         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7279         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7280 }
7281
7282 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7283                                  struct intel_crtc_state *pipe_config)
7284 {
7285         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7286         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7287         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7288         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7289
7290         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7291         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7292         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7293         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7294
7295         mode->flags = pipe_config->base.adjusted_mode.flags;
7296         mode->type = DRM_MODE_TYPE_DRIVER;
7297
7298         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7299
7300         mode->hsync = drm_mode_hsync(mode);
7301         mode->vrefresh = drm_mode_vrefresh(mode);
7302         drm_mode_set_name(mode);
7303 }
7304
7305 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7306 {
7307         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7308         uint32_t pipeconf;
7309
7310         pipeconf = 0;
7311
7312         /* we keep both pipes enabled on 830 */
7313         if (IS_I830(dev_priv))
7314                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7315
7316         if (intel_crtc->config->double_wide)
7317                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7318
7319         /* only g4x and later have fancy bpc/dither controls */
7320         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7321             IS_CHERRYVIEW(dev_priv)) {
7322                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7323                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7324                         pipeconf |= PIPECONF_DITHER_EN |
7325                                     PIPECONF_DITHER_TYPE_SP;
7326
7327                 switch (intel_crtc->config->pipe_bpp) {
7328                 case 18:
7329                         pipeconf |= PIPECONF_6BPC;
7330                         break;
7331                 case 24:
7332                         pipeconf |= PIPECONF_8BPC;
7333                         break;
7334                 case 30:
7335                         pipeconf |= PIPECONF_10BPC;
7336                         break;
7337                 default:
7338                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7339                         BUG();
7340                 }
7341         }
7342
7343         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7344                 if (INTEL_GEN(dev_priv) < 4 ||
7345                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7346                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7347                 else
7348                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7349         } else
7350                 pipeconf |= PIPECONF_PROGRESSIVE;
7351
7352         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7353              intel_crtc->config->limited_color_range)
7354                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7355
7356         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7357         POSTING_READ(PIPECONF(intel_crtc->pipe));
7358 }
7359
7360 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7361                                    struct intel_crtc_state *crtc_state)
7362 {
7363         struct drm_device *dev = crtc->base.dev;
7364         struct drm_i915_private *dev_priv = to_i915(dev);
7365         const struct intel_limit *limit;
7366         int refclk = 48000;
7367
7368         memset(&crtc_state->dpll_hw_state, 0,
7369                sizeof(crtc_state->dpll_hw_state));
7370
7371         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7372                 if (intel_panel_use_ssc(dev_priv)) {
7373                         refclk = dev_priv->vbt.lvds_ssc_freq;
7374                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7375                 }
7376
7377                 limit = &intel_limits_i8xx_lvds;
7378         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7379                 limit = &intel_limits_i8xx_dvo;
7380         } else {
7381                 limit = &intel_limits_i8xx_dac;
7382         }
7383
7384         if (!crtc_state->clock_set &&
7385             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7386                                  refclk, NULL, &crtc_state->dpll)) {
7387                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7388                 return -EINVAL;
7389         }
7390
7391         i8xx_compute_dpll(crtc, crtc_state, NULL);
7392
7393         return 0;
7394 }
7395
7396 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7397                                   struct intel_crtc_state *crtc_state)
7398 {
7399         struct drm_device *dev = crtc->base.dev;
7400         struct drm_i915_private *dev_priv = to_i915(dev);
7401         const struct intel_limit *limit;
7402         int refclk = 96000;
7403
7404         memset(&crtc_state->dpll_hw_state, 0,
7405                sizeof(crtc_state->dpll_hw_state));
7406
7407         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7408                 if (intel_panel_use_ssc(dev_priv)) {
7409                         refclk = dev_priv->vbt.lvds_ssc_freq;
7410                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7411                 }
7412
7413                 if (intel_is_dual_link_lvds(dev))
7414                         limit = &intel_limits_g4x_dual_channel_lvds;
7415                 else
7416                         limit = &intel_limits_g4x_single_channel_lvds;
7417         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7418                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7419                 limit = &intel_limits_g4x_hdmi;
7420         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7421                 limit = &intel_limits_g4x_sdvo;
7422         } else {
7423                 /* The option is for other outputs */
7424                 limit = &intel_limits_i9xx_sdvo;
7425         }
7426
7427         if (!crtc_state->clock_set &&
7428             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7429                                 refclk, NULL, &crtc_state->dpll)) {
7430                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7431                 return -EINVAL;
7432         }
7433
7434         i9xx_compute_dpll(crtc, crtc_state, NULL);
7435
7436         return 0;
7437 }
7438
7439 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7440                                   struct intel_crtc_state *crtc_state)
7441 {
7442         struct drm_device *dev = crtc->base.dev;
7443         struct drm_i915_private *dev_priv = to_i915(dev);
7444         const struct intel_limit *limit;
7445         int refclk = 96000;
7446
7447         memset(&crtc_state->dpll_hw_state, 0,
7448                sizeof(crtc_state->dpll_hw_state));
7449
7450         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7451                 if (intel_panel_use_ssc(dev_priv)) {
7452                         refclk = dev_priv->vbt.lvds_ssc_freq;
7453                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7454                 }
7455
7456                 limit = &intel_limits_pineview_lvds;
7457         } else {
7458                 limit = &intel_limits_pineview_sdvo;
7459         }
7460
7461         if (!crtc_state->clock_set &&
7462             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7463                                 refclk, NULL, &crtc_state->dpll)) {
7464                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7465                 return -EINVAL;
7466         }
7467
7468         i9xx_compute_dpll(crtc, crtc_state, NULL);
7469
7470         return 0;
7471 }
7472
7473 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7474                                    struct intel_crtc_state *crtc_state)
7475 {
7476         struct drm_device *dev = crtc->base.dev;
7477         struct drm_i915_private *dev_priv = to_i915(dev);
7478         const struct intel_limit *limit;
7479         int refclk = 96000;
7480
7481         memset(&crtc_state->dpll_hw_state, 0,
7482                sizeof(crtc_state->dpll_hw_state));
7483
7484         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7485                 if (intel_panel_use_ssc(dev_priv)) {
7486                         refclk = dev_priv->vbt.lvds_ssc_freq;
7487                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7488                 }
7489
7490                 limit = &intel_limits_i9xx_lvds;
7491         } else {
7492                 limit = &intel_limits_i9xx_sdvo;
7493         }
7494
7495         if (!crtc_state->clock_set &&
7496             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7497                                  refclk, NULL, &crtc_state->dpll)) {
7498                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7499                 return -EINVAL;
7500         }
7501
7502         i9xx_compute_dpll(crtc, crtc_state, NULL);
7503
7504         return 0;
7505 }
7506
7507 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7508                                   struct intel_crtc_state *crtc_state)
7509 {
7510         int refclk = 100000;
7511         const struct intel_limit *limit = &intel_limits_chv;
7512
7513         memset(&crtc_state->dpll_hw_state, 0,
7514                sizeof(crtc_state->dpll_hw_state));
7515
7516         if (!crtc_state->clock_set &&
7517             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7518                                 refclk, NULL, &crtc_state->dpll)) {
7519                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7520                 return -EINVAL;
7521         }
7522
7523         chv_compute_dpll(crtc, crtc_state);
7524
7525         return 0;
7526 }
7527
7528 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7529                                   struct intel_crtc_state *crtc_state)
7530 {
7531         int refclk = 100000;
7532         const struct intel_limit *limit = &intel_limits_vlv;
7533
7534         memset(&crtc_state->dpll_hw_state, 0,
7535                sizeof(crtc_state->dpll_hw_state));
7536
7537         if (!crtc_state->clock_set &&
7538             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7539                                 refclk, NULL, &crtc_state->dpll)) {
7540                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7541                 return -EINVAL;
7542         }
7543
7544         vlv_compute_dpll(crtc, crtc_state);
7545
7546         return 0;
7547 }
7548
7549 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7550                                  struct intel_crtc_state *pipe_config)
7551 {
7552         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7553         uint32_t tmp;
7554
7555         if (INTEL_GEN(dev_priv) <= 3 &&
7556             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7557                 return;
7558
7559         tmp = I915_READ(PFIT_CONTROL);
7560         if (!(tmp & PFIT_ENABLE))
7561                 return;
7562
7563         /* Check whether the pfit is attached to our pipe. */
7564         if (INTEL_GEN(dev_priv) < 4) {
7565                 if (crtc->pipe != PIPE_B)
7566                         return;
7567         } else {
7568                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7569                         return;
7570         }
7571
7572         pipe_config->gmch_pfit.control = tmp;
7573         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7574 }
7575
7576 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7577                                struct intel_crtc_state *pipe_config)
7578 {
7579         struct drm_device *dev = crtc->base.dev;
7580         struct drm_i915_private *dev_priv = to_i915(dev);
7581         int pipe = pipe_config->cpu_transcoder;
7582         struct dpll clock;
7583         u32 mdiv;
7584         int refclk = 100000;
7585
7586         /* In case of DSI, DPLL will not be used */
7587         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7588                 return;
7589
7590         mutex_lock(&dev_priv->sb_lock);
7591         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7592         mutex_unlock(&dev_priv->sb_lock);
7593
7594         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7595         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7596         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7597         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7598         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7599
7600         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7601 }
7602
7603 static void
7604 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7605                               struct intel_initial_plane_config *plane_config)
7606 {
7607         struct drm_device *dev = crtc->base.dev;
7608         struct drm_i915_private *dev_priv = to_i915(dev);
7609         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
7610         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
7611         enum pipe pipe = crtc->pipe;
7612         u32 val, base, offset;
7613         int fourcc, pixel_format;
7614         unsigned int aligned_height;
7615         struct drm_framebuffer *fb;
7616         struct intel_framebuffer *intel_fb;
7617
7618         if (!plane->get_hw_state(plane))
7619                 return;
7620
7621         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7622         if (!intel_fb) {
7623                 DRM_DEBUG_KMS("failed to alloc fb\n");
7624                 return;
7625         }
7626
7627         fb = &intel_fb->base;
7628
7629         fb->dev = dev;
7630
7631         val = I915_READ(DSPCNTR(i9xx_plane));
7632
7633         if (INTEL_GEN(dev_priv) >= 4) {
7634                 if (val & DISPPLANE_TILED) {
7635                         plane_config->tiling = I915_TILING_X;
7636                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7637                 }
7638         }
7639
7640         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7641         fourcc = i9xx_format_to_fourcc(pixel_format);
7642         fb->format = drm_format_info(fourcc);
7643
7644         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7645                 offset = I915_READ(DSPOFFSET(i9xx_plane));
7646                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7647         } else if (INTEL_GEN(dev_priv) >= 4) {
7648                 if (plane_config->tiling)
7649                         offset = I915_READ(DSPTILEOFF(i9xx_plane));
7650                 else
7651                         offset = I915_READ(DSPLINOFF(i9xx_plane));
7652                 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
7653         } else {
7654                 base = I915_READ(DSPADDR(i9xx_plane));
7655         }
7656         plane_config->base = base;
7657
7658         val = I915_READ(PIPESRC(pipe));
7659         fb->width = ((val >> 16) & 0xfff) + 1;
7660         fb->height = ((val >> 0) & 0xfff) + 1;
7661
7662         val = I915_READ(DSPSTRIDE(i9xx_plane));
7663         fb->pitches[0] = val & 0xffffffc0;
7664
7665         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7666
7667         plane_config->size = fb->pitches[0] * aligned_height;
7668
7669         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670                       crtc->base.name, plane->base.name, fb->width, fb->height,
7671                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7672                       plane_config->size);
7673
7674         plane_config->fb = intel_fb;
7675 }
7676
7677 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7678                                struct intel_crtc_state *pipe_config)
7679 {
7680         struct drm_device *dev = crtc->base.dev;
7681         struct drm_i915_private *dev_priv = to_i915(dev);
7682         int pipe = pipe_config->cpu_transcoder;
7683         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7684         struct dpll clock;
7685         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7686         int refclk = 100000;
7687
7688         /* In case of DSI, DPLL will not be used */
7689         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7690                 return;
7691
7692         mutex_lock(&dev_priv->sb_lock);
7693         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7694         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7695         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7696         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7697         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7698         mutex_unlock(&dev_priv->sb_lock);
7699
7700         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7701         clock.m2 = (pll_dw0 & 0xff) << 22;
7702         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7703                 clock.m2 |= pll_dw2 & 0x3fffff;
7704         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7705         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7706         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7707
7708         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7709 }
7710
7711 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7712                                  struct intel_crtc_state *pipe_config)
7713 {
7714         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7715         enum intel_display_power_domain power_domain;
7716         uint32_t tmp;
7717         bool ret;
7718
7719         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7720         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7721                 return false;
7722
7723         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7724         pipe_config->shared_dpll = NULL;
7725
7726         ret = false;
7727
7728         tmp = I915_READ(PIPECONF(crtc->pipe));
7729         if (!(tmp & PIPECONF_ENABLE))
7730                 goto out;
7731
7732         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7733             IS_CHERRYVIEW(dev_priv)) {
7734                 switch (tmp & PIPECONF_BPC_MASK) {
7735                 case PIPECONF_6BPC:
7736                         pipe_config->pipe_bpp = 18;
7737                         break;
7738                 case PIPECONF_8BPC:
7739                         pipe_config->pipe_bpp = 24;
7740                         break;
7741                 case PIPECONF_10BPC:
7742                         pipe_config->pipe_bpp = 30;
7743                         break;
7744                 default:
7745                         break;
7746                 }
7747         }
7748
7749         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7750             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7751                 pipe_config->limited_color_range = true;
7752
7753         if (INTEL_GEN(dev_priv) < 4)
7754                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7755
7756         intel_get_pipe_timings(crtc, pipe_config);
7757         intel_get_pipe_src_size(crtc, pipe_config);
7758
7759         i9xx_get_pfit_config(crtc, pipe_config);
7760
7761         if (INTEL_GEN(dev_priv) >= 4) {
7762                 /* No way to read it out on pipes B and C */
7763                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7764                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7765                 else
7766                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7767                 pipe_config->pixel_multiplier =
7768                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7769                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7770                 pipe_config->dpll_hw_state.dpll_md = tmp;
7771         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7772                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7773                 tmp = I915_READ(DPLL(crtc->pipe));
7774                 pipe_config->pixel_multiplier =
7775                         ((tmp & SDVO_MULTIPLIER_MASK)
7776                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7777         } else {
7778                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7779                  * port and will be fixed up in the encoder->get_config
7780                  * function. */
7781                 pipe_config->pixel_multiplier = 1;
7782         }
7783         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7784         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7785                 /*
7786                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7787                  * on 830. Filter it out here so that we don't
7788                  * report errors due to that.
7789                  */
7790                 if (IS_I830(dev_priv))
7791                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7792
7793                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7794                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7795         } else {
7796                 /* Mask out read-only status bits. */
7797                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7798                                                      DPLL_PORTC_READY_MASK |
7799                                                      DPLL_PORTB_READY_MASK);
7800         }
7801
7802         if (IS_CHERRYVIEW(dev_priv))
7803                 chv_crtc_clock_get(crtc, pipe_config);
7804         else if (IS_VALLEYVIEW(dev_priv))
7805                 vlv_crtc_clock_get(crtc, pipe_config);
7806         else
7807                 i9xx_crtc_clock_get(crtc, pipe_config);
7808
7809         /*
7810          * Normally the dotclock is filled in by the encoder .get_config()
7811          * but in case the pipe is enabled w/o any ports we need a sane
7812          * default.
7813          */
7814         pipe_config->base.adjusted_mode.crtc_clock =
7815                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7816
7817         ret = true;
7818
7819 out:
7820         intel_display_power_put(dev_priv, power_domain);
7821
7822         return ret;
7823 }
7824
7825 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7826 {
7827         struct intel_encoder *encoder;
7828         int i;
7829         u32 val, final;
7830         bool has_lvds = false;
7831         bool has_cpu_edp = false;
7832         bool has_panel = false;
7833         bool has_ck505 = false;
7834         bool can_ssc = false;
7835         bool using_ssc_source = false;
7836
7837         /* We need to take the global config into account */
7838         for_each_intel_encoder(&dev_priv->drm, encoder) {
7839                 switch (encoder->type) {
7840                 case INTEL_OUTPUT_LVDS:
7841                         has_panel = true;
7842                         has_lvds = true;
7843                         break;
7844                 case INTEL_OUTPUT_EDP:
7845                         has_panel = true;
7846                         if (encoder->port == PORT_A)
7847                                 has_cpu_edp = true;
7848                         break;
7849                 default:
7850                         break;
7851                 }
7852         }
7853
7854         if (HAS_PCH_IBX(dev_priv)) {
7855                 has_ck505 = dev_priv->vbt.display_clock_mode;
7856                 can_ssc = has_ck505;
7857         } else {
7858                 has_ck505 = false;
7859                 can_ssc = true;
7860         }
7861
7862         /* Check if any DPLLs are using the SSC source */
7863         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7864                 u32 temp = I915_READ(PCH_DPLL(i));
7865
7866                 if (!(temp & DPLL_VCO_ENABLE))
7867                         continue;
7868
7869                 if ((temp & PLL_REF_INPUT_MASK) ==
7870                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7871                         using_ssc_source = true;
7872                         break;
7873                 }
7874         }
7875
7876         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7877                       has_panel, has_lvds, has_ck505, using_ssc_source);
7878
7879         /* Ironlake: try to setup display ref clock before DPLL
7880          * enabling. This is only under driver's control after
7881          * PCH B stepping, previous chipset stepping should be
7882          * ignoring this setting.
7883          */
7884         val = I915_READ(PCH_DREF_CONTROL);
7885
7886         /* As we must carefully and slowly disable/enable each source in turn,
7887          * compute the final state we want first and check if we need to
7888          * make any changes at all.
7889          */
7890         final = val;
7891         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7892         if (has_ck505)
7893                 final |= DREF_NONSPREAD_CK505_ENABLE;
7894         else
7895                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7896
7897         final &= ~DREF_SSC_SOURCE_MASK;
7898         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7899         final &= ~DREF_SSC1_ENABLE;
7900
7901         if (has_panel) {
7902                 final |= DREF_SSC_SOURCE_ENABLE;
7903
7904                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7905                         final |= DREF_SSC1_ENABLE;
7906
7907                 if (has_cpu_edp) {
7908                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7909                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7910                         else
7911                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7912                 } else
7913                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7914         } else if (using_ssc_source) {
7915                 final |= DREF_SSC_SOURCE_ENABLE;
7916                 final |= DREF_SSC1_ENABLE;
7917         }
7918
7919         if (final == val)
7920                 return;
7921
7922         /* Always enable nonspread source */
7923         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7924
7925         if (has_ck505)
7926                 val |= DREF_NONSPREAD_CK505_ENABLE;
7927         else
7928                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7929
7930         if (has_panel) {
7931                 val &= ~DREF_SSC_SOURCE_MASK;
7932                 val |= DREF_SSC_SOURCE_ENABLE;
7933
7934                 /* SSC must be turned on before enabling the CPU output  */
7935                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7936                         DRM_DEBUG_KMS("Using SSC on panel\n");
7937                         val |= DREF_SSC1_ENABLE;
7938                 } else
7939                         val &= ~DREF_SSC1_ENABLE;
7940
7941                 /* Get SSC going before enabling the outputs */
7942                 I915_WRITE(PCH_DREF_CONTROL, val);
7943                 POSTING_READ(PCH_DREF_CONTROL);
7944                 udelay(200);
7945
7946                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7947
7948                 /* Enable CPU source on CPU attached eDP */
7949                 if (has_cpu_edp) {
7950                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7951                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7952                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7953                         } else
7954                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7955                 } else
7956                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7957
7958                 I915_WRITE(PCH_DREF_CONTROL, val);
7959                 POSTING_READ(PCH_DREF_CONTROL);
7960                 udelay(200);
7961         } else {
7962                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7963
7964                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7965
7966                 /* Turn off CPU output */
7967                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7968
7969                 I915_WRITE(PCH_DREF_CONTROL, val);
7970                 POSTING_READ(PCH_DREF_CONTROL);
7971                 udelay(200);
7972
7973                 if (!using_ssc_source) {
7974                         DRM_DEBUG_KMS("Disabling SSC source\n");
7975
7976                         /* Turn off the SSC source */
7977                         val &= ~DREF_SSC_SOURCE_MASK;
7978                         val |= DREF_SSC_SOURCE_DISABLE;
7979
7980                         /* Turn off SSC1 */
7981                         val &= ~DREF_SSC1_ENABLE;
7982
7983                         I915_WRITE(PCH_DREF_CONTROL, val);
7984                         POSTING_READ(PCH_DREF_CONTROL);
7985                         udelay(200);
7986                 }
7987         }
7988
7989         BUG_ON(val != final);
7990 }
7991
7992 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7993 {
7994         uint32_t tmp;
7995
7996         tmp = I915_READ(SOUTH_CHICKEN2);
7997         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7998         I915_WRITE(SOUTH_CHICKEN2, tmp);
7999
8000         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8001                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8002                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8003
8004         tmp = I915_READ(SOUTH_CHICKEN2);
8005         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8006         I915_WRITE(SOUTH_CHICKEN2, tmp);
8007
8008         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8009                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8010                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8011 }
8012
8013 /* WaMPhyProgramming:hsw */
8014 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8015 {
8016         uint32_t tmp;
8017
8018         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8019         tmp &= ~(0xFF << 24);
8020         tmp |= (0x12 << 24);
8021         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8022
8023         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8024         tmp |= (1 << 11);
8025         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8026
8027         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8028         tmp |= (1 << 11);
8029         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8030
8031         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8032         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8033         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8034
8035         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8036         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8037         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8038
8039         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8040         tmp &= ~(7 << 13);
8041         tmp |= (5 << 13);
8042         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8043
8044         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8045         tmp &= ~(7 << 13);
8046         tmp |= (5 << 13);
8047         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8048
8049         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8050         tmp &= ~0xFF;
8051         tmp |= 0x1C;
8052         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8053
8054         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8055         tmp &= ~0xFF;
8056         tmp |= 0x1C;
8057         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8058
8059         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8060         tmp &= ~(0xFF << 16);
8061         tmp |= (0x1C << 16);
8062         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8063
8064         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8065         tmp &= ~(0xFF << 16);
8066         tmp |= (0x1C << 16);
8067         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8068
8069         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8070         tmp |= (1 << 27);
8071         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8072
8073         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8074         tmp |= (1 << 27);
8075         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8076
8077         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8078         tmp &= ~(0xF << 28);
8079         tmp |= (4 << 28);
8080         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8081
8082         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8083         tmp &= ~(0xF << 28);
8084         tmp |= (4 << 28);
8085         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8086 }
8087
8088 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8089  * Programming" based on the parameters passed:
8090  * - Sequence to enable CLKOUT_DP
8091  * - Sequence to enable CLKOUT_DP without spread
8092  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8093  */
8094 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
8095                                  bool with_spread, bool with_fdi)
8096 {
8097         uint32_t reg, tmp;
8098
8099         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8100                 with_spread = true;
8101         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
8102             with_fdi, "LP PCH doesn't have FDI\n"))
8103                 with_fdi = false;
8104
8105         mutex_lock(&dev_priv->sb_lock);
8106
8107         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8108         tmp &= ~SBI_SSCCTL_DISABLE;
8109         tmp |= SBI_SSCCTL_PATHALT;
8110         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8111
8112         udelay(24);
8113
8114         if (with_spread) {
8115                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8116                 tmp &= ~SBI_SSCCTL_PATHALT;
8117                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8118
8119                 if (with_fdi) {
8120                         lpt_reset_fdi_mphy(dev_priv);
8121                         lpt_program_fdi_mphy(dev_priv);
8122                 }
8123         }
8124
8125         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8126         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8127         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8128         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8129
8130         mutex_unlock(&dev_priv->sb_lock);
8131 }
8132
8133 /* Sequence to disable CLKOUT_DP */
8134 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8135 {
8136         uint32_t reg, tmp;
8137
8138         mutex_lock(&dev_priv->sb_lock);
8139
8140         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8141         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8142         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8143         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8144
8145         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8146         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8147                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8148                         tmp |= SBI_SSCCTL_PATHALT;
8149                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8150                         udelay(32);
8151                 }
8152                 tmp |= SBI_SSCCTL_DISABLE;
8153                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8154         }
8155
8156         mutex_unlock(&dev_priv->sb_lock);
8157 }
8158
8159 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8160
8161 static const uint16_t sscdivintphase[] = {
8162         [BEND_IDX( 50)] = 0x3B23,
8163         [BEND_IDX( 45)] = 0x3B23,
8164         [BEND_IDX( 40)] = 0x3C23,
8165         [BEND_IDX( 35)] = 0x3C23,
8166         [BEND_IDX( 30)] = 0x3D23,
8167         [BEND_IDX( 25)] = 0x3D23,
8168         [BEND_IDX( 20)] = 0x3E23,
8169         [BEND_IDX( 15)] = 0x3E23,
8170         [BEND_IDX( 10)] = 0x3F23,
8171         [BEND_IDX(  5)] = 0x3F23,
8172         [BEND_IDX(  0)] = 0x0025,
8173         [BEND_IDX( -5)] = 0x0025,
8174         [BEND_IDX(-10)] = 0x0125,
8175         [BEND_IDX(-15)] = 0x0125,
8176         [BEND_IDX(-20)] = 0x0225,
8177         [BEND_IDX(-25)] = 0x0225,
8178         [BEND_IDX(-30)] = 0x0325,
8179         [BEND_IDX(-35)] = 0x0325,
8180         [BEND_IDX(-40)] = 0x0425,
8181         [BEND_IDX(-45)] = 0x0425,
8182         [BEND_IDX(-50)] = 0x0525,
8183 };
8184
8185 /*
8186  * Bend CLKOUT_DP
8187  * steps -50 to 50 inclusive, in steps of 5
8188  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8189  * change in clock period = -(steps / 10) * 5.787 ps
8190  */
8191 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8192 {
8193         uint32_t tmp;
8194         int idx = BEND_IDX(steps);
8195
8196         if (WARN_ON(steps % 5 != 0))
8197                 return;
8198
8199         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8200                 return;
8201
8202         mutex_lock(&dev_priv->sb_lock);
8203
8204         if (steps % 10 != 0)
8205                 tmp = 0xAAAAAAAB;
8206         else
8207                 tmp = 0x00000000;
8208         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8209
8210         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8211         tmp &= 0xffff0000;
8212         tmp |= sscdivintphase[idx];
8213         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8214
8215         mutex_unlock(&dev_priv->sb_lock);
8216 }
8217
8218 #undef BEND_IDX
8219
8220 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8221 {
8222         struct intel_encoder *encoder;
8223         bool has_vga = false;
8224
8225         for_each_intel_encoder(&dev_priv->drm, encoder) {
8226                 switch (encoder->type) {
8227                 case INTEL_OUTPUT_ANALOG:
8228                         has_vga = true;
8229                         break;
8230                 default:
8231                         break;
8232                 }
8233         }
8234
8235         if (has_vga) {
8236                 lpt_bend_clkout_dp(dev_priv, 0);
8237                 lpt_enable_clkout_dp(dev_priv, true, true);
8238         } else {
8239                 lpt_disable_clkout_dp(dev_priv);
8240         }
8241 }
8242
8243 /*
8244  * Initialize reference clocks when the driver loads
8245  */
8246 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8247 {
8248         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8249                 ironlake_init_pch_refclk(dev_priv);
8250         else if (HAS_PCH_LPT(dev_priv))
8251                 lpt_init_pch_refclk(dev_priv);
8252 }
8253
8254 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8255 {
8256         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8258         int pipe = intel_crtc->pipe;
8259         uint32_t val;
8260
8261         val = 0;
8262
8263         switch (intel_crtc->config->pipe_bpp) {
8264         case 18:
8265                 val |= PIPECONF_6BPC;
8266                 break;
8267         case 24:
8268                 val |= PIPECONF_8BPC;
8269                 break;
8270         case 30:
8271                 val |= PIPECONF_10BPC;
8272                 break;
8273         case 36:
8274                 val |= PIPECONF_12BPC;
8275                 break;
8276         default:
8277                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8278                 BUG();
8279         }
8280
8281         if (intel_crtc->config->dither)
8282                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8283
8284         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8285                 val |= PIPECONF_INTERLACED_ILK;
8286         else
8287                 val |= PIPECONF_PROGRESSIVE;
8288
8289         if (intel_crtc->config->limited_color_range)
8290                 val |= PIPECONF_COLOR_RANGE_SELECT;
8291
8292         I915_WRITE(PIPECONF(pipe), val);
8293         POSTING_READ(PIPECONF(pipe));
8294 }
8295
8296 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8297 {
8298         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8300         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8301         u32 val = 0;
8302
8303         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8304                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8305
8306         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8307                 val |= PIPECONF_INTERLACED_ILK;
8308         else
8309                 val |= PIPECONF_PROGRESSIVE;
8310
8311         I915_WRITE(PIPECONF(cpu_transcoder), val);
8312         POSTING_READ(PIPECONF(cpu_transcoder));
8313 }
8314
8315 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8316 {
8317         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8319         struct intel_crtc_state *config = intel_crtc->config;
8320
8321         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8322                 u32 val = 0;
8323
8324                 switch (intel_crtc->config->pipe_bpp) {
8325                 case 18:
8326                         val |= PIPEMISC_DITHER_6_BPC;
8327                         break;
8328                 case 24:
8329                         val |= PIPEMISC_DITHER_8_BPC;
8330                         break;
8331                 case 30:
8332                         val |= PIPEMISC_DITHER_10_BPC;
8333                         break;
8334                 case 36:
8335                         val |= PIPEMISC_DITHER_12_BPC;
8336                         break;
8337                 default:
8338                         /* Case prevented by pipe_config_set_bpp. */
8339                         BUG();
8340                 }
8341
8342                 if (intel_crtc->config->dither)
8343                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8344
8345                 if (config->ycbcr420) {
8346                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8347                                 PIPEMISC_YUV420_ENABLE |
8348                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8349                 }
8350
8351                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8352         }
8353 }
8354
8355 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8356 {
8357         /*
8358          * Account for spread spectrum to avoid
8359          * oversubscribing the link. Max center spread
8360          * is 2.5%; use 5% for safety's sake.
8361          */
8362         u32 bps = target_clock * bpp * 21 / 20;
8363         return DIV_ROUND_UP(bps, link_bw * 8);
8364 }
8365
8366 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8367 {
8368         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8369 }
8370
8371 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8372                                   struct intel_crtc_state *crtc_state,
8373                                   struct dpll *reduced_clock)
8374 {
8375         struct drm_crtc *crtc = &intel_crtc->base;
8376         struct drm_device *dev = crtc->dev;
8377         struct drm_i915_private *dev_priv = to_i915(dev);
8378         u32 dpll, fp, fp2;
8379         int factor;
8380
8381         /* Enable autotuning of the PLL clock (if permissible) */
8382         factor = 21;
8383         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8384                 if ((intel_panel_use_ssc(dev_priv) &&
8385                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8386                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8387                         factor = 25;
8388         } else if (crtc_state->sdvo_tv_clock)
8389                 factor = 20;
8390
8391         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8392
8393         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8394                 fp |= FP_CB_TUNE;
8395
8396         if (reduced_clock) {
8397                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8398
8399                 if (reduced_clock->m < factor * reduced_clock->n)
8400                         fp2 |= FP_CB_TUNE;
8401         } else {
8402                 fp2 = fp;
8403         }
8404
8405         dpll = 0;
8406
8407         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8408                 dpll |= DPLLB_MODE_LVDS;
8409         else
8410                 dpll |= DPLLB_MODE_DAC_SERIAL;
8411
8412         dpll |= (crtc_state->pixel_multiplier - 1)
8413                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8414
8415         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8416             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8417                 dpll |= DPLL_SDVO_HIGH_SPEED;
8418
8419         if (intel_crtc_has_dp_encoder(crtc_state))
8420                 dpll |= DPLL_SDVO_HIGH_SPEED;
8421
8422         /*
8423          * The high speed IO clock is only really required for
8424          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8425          * possible to share the DPLL between CRT and HDMI. Enabling
8426          * the clock needlessly does no real harm, except use up a
8427          * bit of power potentially.
8428          *
8429          * We'll limit this to IVB with 3 pipes, since it has only two
8430          * DPLLs and so DPLL sharing is the only way to get three pipes
8431          * driving PCH ports at the same time. On SNB we could do this,
8432          * and potentially avoid enabling the second DPLL, but it's not
8433          * clear if it''s a win or loss power wise. No point in doing
8434          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8435          */
8436         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8437             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8438                 dpll |= DPLL_SDVO_HIGH_SPEED;
8439
8440         /* compute bitmask from p1 value */
8441         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8442         /* also FPA1 */
8443         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8444
8445         switch (crtc_state->dpll.p2) {
8446         case 5:
8447                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8448                 break;
8449         case 7:
8450                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8451                 break;
8452         case 10:
8453                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8454                 break;
8455         case 14:
8456                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8457                 break;
8458         }
8459
8460         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8461             intel_panel_use_ssc(dev_priv))
8462                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8463         else
8464                 dpll |= PLL_REF_INPUT_DREFCLK;
8465
8466         dpll |= DPLL_VCO_ENABLE;
8467
8468         crtc_state->dpll_hw_state.dpll = dpll;
8469         crtc_state->dpll_hw_state.fp0 = fp;
8470         crtc_state->dpll_hw_state.fp1 = fp2;
8471 }
8472
8473 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8474                                        struct intel_crtc_state *crtc_state)
8475 {
8476         struct drm_device *dev = crtc->base.dev;
8477         struct drm_i915_private *dev_priv = to_i915(dev);
8478         const struct intel_limit *limit;
8479         int refclk = 120000;
8480
8481         memset(&crtc_state->dpll_hw_state, 0,
8482                sizeof(crtc_state->dpll_hw_state));
8483
8484         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8485         if (!crtc_state->has_pch_encoder)
8486                 return 0;
8487
8488         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8489                 if (intel_panel_use_ssc(dev_priv)) {
8490                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8491                                       dev_priv->vbt.lvds_ssc_freq);
8492                         refclk = dev_priv->vbt.lvds_ssc_freq;
8493                 }
8494
8495                 if (intel_is_dual_link_lvds(dev)) {
8496                         if (refclk == 100000)
8497                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8498                         else
8499                                 limit = &intel_limits_ironlake_dual_lvds;
8500                 } else {
8501                         if (refclk == 100000)
8502                                 limit = &intel_limits_ironlake_single_lvds_100m;
8503                         else
8504                                 limit = &intel_limits_ironlake_single_lvds;
8505                 }
8506         } else {
8507                 limit = &intel_limits_ironlake_dac;
8508         }
8509
8510         if (!crtc_state->clock_set &&
8511             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8512                                 refclk, NULL, &crtc_state->dpll)) {
8513                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8514                 return -EINVAL;
8515         }
8516
8517         ironlake_compute_dpll(crtc, crtc_state, NULL);
8518
8519         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8520                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8521                                  pipe_name(crtc->pipe));
8522                 return -EINVAL;
8523         }
8524
8525         return 0;
8526 }
8527
8528 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8529                                          struct intel_link_m_n *m_n)
8530 {
8531         struct drm_device *dev = crtc->base.dev;
8532         struct drm_i915_private *dev_priv = to_i915(dev);
8533         enum pipe pipe = crtc->pipe;
8534
8535         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8536         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8537         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8538                 & ~TU_SIZE_MASK;
8539         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8540         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8541                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8542 }
8543
8544 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8545                                          enum transcoder transcoder,
8546                                          struct intel_link_m_n *m_n,
8547                                          struct intel_link_m_n *m2_n2)
8548 {
8549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8550         enum pipe pipe = crtc->pipe;
8551
8552         if (INTEL_GEN(dev_priv) >= 5) {
8553                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8554                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8555                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8556                         & ~TU_SIZE_MASK;
8557                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8558                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8559                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8560                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8561                  * gen < 8) and if DRRS is supported (to make sure the
8562                  * registers are not unnecessarily read).
8563                  */
8564                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8565                         crtc->config->has_drrs) {
8566                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8567                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8568                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8569                                         & ~TU_SIZE_MASK;
8570                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8571                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8572                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8573                 }
8574         } else {
8575                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8576                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8577                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8578                         & ~TU_SIZE_MASK;
8579                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8580                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8581                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8582         }
8583 }
8584
8585 void intel_dp_get_m_n(struct intel_crtc *crtc,
8586                       struct intel_crtc_state *pipe_config)
8587 {
8588         if (pipe_config->has_pch_encoder)
8589                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8590         else
8591                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8592                                              &pipe_config->dp_m_n,
8593                                              &pipe_config->dp_m2_n2);
8594 }
8595
8596 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8597                                         struct intel_crtc_state *pipe_config)
8598 {
8599         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8600                                      &pipe_config->fdi_m_n, NULL);
8601 }
8602
8603 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8604                                     struct intel_crtc_state *pipe_config)
8605 {
8606         struct drm_device *dev = crtc->base.dev;
8607         struct drm_i915_private *dev_priv = to_i915(dev);
8608         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8609         uint32_t ps_ctrl = 0;
8610         int id = -1;
8611         int i;
8612
8613         /* find scaler attached to this pipe */
8614         for (i = 0; i < crtc->num_scalers; i++) {
8615                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8616                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8617                         id = i;
8618                         pipe_config->pch_pfit.enabled = true;
8619                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8620                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8621                         break;
8622                 }
8623         }
8624
8625         scaler_state->scaler_id = id;
8626         if (id >= 0) {
8627                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8628         } else {
8629                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8630         }
8631 }
8632
8633 static void
8634 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8635                                  struct intel_initial_plane_config *plane_config)
8636 {
8637         struct drm_device *dev = crtc->base.dev;
8638         struct drm_i915_private *dev_priv = to_i915(dev);
8639         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8640         enum plane_id plane_id = plane->id;
8641         enum pipe pipe = crtc->pipe;
8642         u32 val, base, offset, stride_mult, tiling, alpha;
8643         int fourcc, pixel_format;
8644         unsigned int aligned_height;
8645         struct drm_framebuffer *fb;
8646         struct intel_framebuffer *intel_fb;
8647
8648         if (!plane->get_hw_state(plane))
8649                 return;
8650
8651         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8652         if (!intel_fb) {
8653                 DRM_DEBUG_KMS("failed to alloc fb\n");
8654                 return;
8655         }
8656
8657         fb = &intel_fb->base;
8658
8659         fb->dev = dev;
8660
8661         val = I915_READ(PLANE_CTL(pipe, plane_id));
8662
8663         if (INTEL_GEN(dev_priv) >= 11)
8664                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
8665         else
8666                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8667
8668         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
8669                 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
8670                 alpha &= PLANE_COLOR_ALPHA_MASK;
8671         } else {
8672                 alpha = val & PLANE_CTL_ALPHA_MASK;
8673         }
8674
8675         fourcc = skl_format_to_fourcc(pixel_format,
8676                                       val & PLANE_CTL_ORDER_RGBX, alpha);
8677         fb->format = drm_format_info(fourcc);
8678
8679         tiling = val & PLANE_CTL_TILED_MASK;
8680         switch (tiling) {
8681         case PLANE_CTL_TILED_LINEAR:
8682                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8683                 break;
8684         case PLANE_CTL_TILED_X:
8685                 plane_config->tiling = I915_TILING_X;
8686                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8687                 break;
8688         case PLANE_CTL_TILED_Y:
8689                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8690                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8691                 else
8692                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8693                 break;
8694         case PLANE_CTL_TILED_YF:
8695                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8696                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8697                 else
8698                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8699                 break;
8700         default:
8701                 MISSING_CASE(tiling);
8702                 goto error;
8703         }
8704
8705         base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8706         plane_config->base = base;
8707
8708         offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
8709
8710         val = I915_READ(PLANE_SIZE(pipe, plane_id));
8711         fb->height = ((val >> 16) & 0xfff) + 1;
8712         fb->width = ((val >> 0) & 0x1fff) + 1;
8713
8714         val = I915_READ(PLANE_STRIDE(pipe, plane_id));
8715         stride_mult = intel_fb_stride_alignment(fb, 0);
8716         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8717
8718         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8719
8720         plane_config->size = fb->pitches[0] * aligned_height;
8721
8722         DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8723                       crtc->base.name, plane->base.name, fb->width, fb->height,
8724                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8725                       plane_config->size);
8726
8727         plane_config->fb = intel_fb;
8728         return;
8729
8730 error:
8731         kfree(intel_fb);
8732 }
8733
8734 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8735                                      struct intel_crtc_state *pipe_config)
8736 {
8737         struct drm_device *dev = crtc->base.dev;
8738         struct drm_i915_private *dev_priv = to_i915(dev);
8739         uint32_t tmp;
8740
8741         tmp = I915_READ(PF_CTL(crtc->pipe));
8742
8743         if (tmp & PF_ENABLE) {
8744                 pipe_config->pch_pfit.enabled = true;
8745                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8746                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8747
8748                 /* We currently do not free assignements of panel fitters on
8749                  * ivb/hsw (since we don't use the higher upscaling modes which
8750                  * differentiates them) so just WARN about this case for now. */
8751                 if (IS_GEN7(dev_priv)) {
8752                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8753                                 PF_PIPE_SEL_IVB(crtc->pipe));
8754                 }
8755         }
8756 }
8757
8758 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8759                                      struct intel_crtc_state *pipe_config)
8760 {
8761         struct drm_device *dev = crtc->base.dev;
8762         struct drm_i915_private *dev_priv = to_i915(dev);
8763         enum intel_display_power_domain power_domain;
8764         uint32_t tmp;
8765         bool ret;
8766
8767         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8768         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8769                 return false;
8770
8771         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8772         pipe_config->shared_dpll = NULL;
8773
8774         ret = false;
8775         tmp = I915_READ(PIPECONF(crtc->pipe));
8776         if (!(tmp & PIPECONF_ENABLE))
8777                 goto out;
8778
8779         switch (tmp & PIPECONF_BPC_MASK) {
8780         case PIPECONF_6BPC:
8781                 pipe_config->pipe_bpp = 18;
8782                 break;
8783         case PIPECONF_8BPC:
8784                 pipe_config->pipe_bpp = 24;
8785                 break;
8786         case PIPECONF_10BPC:
8787                 pipe_config->pipe_bpp = 30;
8788                 break;
8789         case PIPECONF_12BPC:
8790                 pipe_config->pipe_bpp = 36;
8791                 break;
8792         default:
8793                 break;
8794         }
8795
8796         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8797                 pipe_config->limited_color_range = true;
8798
8799         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8800                 struct intel_shared_dpll *pll;
8801                 enum intel_dpll_id pll_id;
8802
8803                 pipe_config->has_pch_encoder = true;
8804
8805                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8806                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8807                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8808
8809                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8810
8811                 if (HAS_PCH_IBX(dev_priv)) {
8812                         /*
8813                          * The pipe->pch transcoder and pch transcoder->pll
8814                          * mapping is fixed.
8815                          */
8816                         pll_id = (enum intel_dpll_id) crtc->pipe;
8817                 } else {
8818                         tmp = I915_READ(PCH_DPLL_SEL);
8819                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8820                                 pll_id = DPLL_ID_PCH_PLL_B;
8821                         else
8822                                 pll_id= DPLL_ID_PCH_PLL_A;
8823                 }
8824
8825                 pipe_config->shared_dpll =
8826                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8827                 pll = pipe_config->shared_dpll;
8828
8829                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
8830                                                 &pipe_config->dpll_hw_state));
8831
8832                 tmp = pipe_config->dpll_hw_state.dpll;
8833                 pipe_config->pixel_multiplier =
8834                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8835                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8836
8837                 ironlake_pch_clock_get(crtc, pipe_config);
8838         } else {
8839                 pipe_config->pixel_multiplier = 1;
8840         }
8841
8842         intel_get_pipe_timings(crtc, pipe_config);
8843         intel_get_pipe_src_size(crtc, pipe_config);
8844
8845         ironlake_get_pfit_config(crtc, pipe_config);
8846
8847         ret = true;
8848
8849 out:
8850         intel_display_power_put(dev_priv, power_domain);
8851
8852         return ret;
8853 }
8854
8855 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8856 {
8857         struct drm_device *dev = &dev_priv->drm;
8858         struct intel_crtc *crtc;
8859
8860         for_each_intel_crtc(dev, crtc)
8861                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8862                      pipe_name(crtc->pipe));
8863
8864         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8865                         "Display power well on\n");
8866         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8867         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8868         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8869         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8870         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8871              "CPU PWM1 enabled\n");
8872         if (IS_HASWELL(dev_priv))
8873                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8874                      "CPU PWM2 enabled\n");
8875         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8876              "PCH PWM1 enabled\n");
8877         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8878              "Utility pin enabled\n");
8879         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8880
8881         /*
8882          * In theory we can still leave IRQs enabled, as long as only the HPD
8883          * interrupts remain enabled. We used to check for that, but since it's
8884          * gen-specific and since we only disable LCPLL after we fully disable
8885          * the interrupts, the check below should be enough.
8886          */
8887         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8888 }
8889
8890 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8891 {
8892         if (IS_HASWELL(dev_priv))
8893                 return I915_READ(D_COMP_HSW);
8894         else
8895                 return I915_READ(D_COMP_BDW);
8896 }
8897
8898 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8899 {
8900         if (IS_HASWELL(dev_priv)) {
8901                 mutex_lock(&dev_priv->pcu_lock);
8902                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8903                                             val))
8904                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8905                 mutex_unlock(&dev_priv->pcu_lock);
8906         } else {
8907                 I915_WRITE(D_COMP_BDW, val);
8908                 POSTING_READ(D_COMP_BDW);
8909         }
8910 }
8911
8912 /*
8913  * This function implements pieces of two sequences from BSpec:
8914  * - Sequence for display software to disable LCPLL
8915  * - Sequence for display software to allow package C8+
8916  * The steps implemented here are just the steps that actually touch the LCPLL
8917  * register. Callers should take care of disabling all the display engine
8918  * functions, doing the mode unset, fixing interrupts, etc.
8919  */
8920 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8921                               bool switch_to_fclk, bool allow_power_down)
8922 {
8923         uint32_t val;
8924
8925         assert_can_disable_lcpll(dev_priv);
8926
8927         val = I915_READ(LCPLL_CTL);
8928
8929         if (switch_to_fclk) {
8930                 val |= LCPLL_CD_SOURCE_FCLK;
8931                 I915_WRITE(LCPLL_CTL, val);
8932
8933                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8934                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8935                         DRM_ERROR("Switching to FCLK failed\n");
8936
8937                 val = I915_READ(LCPLL_CTL);
8938         }
8939
8940         val |= LCPLL_PLL_DISABLE;
8941         I915_WRITE(LCPLL_CTL, val);
8942         POSTING_READ(LCPLL_CTL);
8943
8944         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8945                 DRM_ERROR("LCPLL still locked\n");
8946
8947         val = hsw_read_dcomp(dev_priv);
8948         val |= D_COMP_COMP_DISABLE;
8949         hsw_write_dcomp(dev_priv, val);
8950         ndelay(100);
8951
8952         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8953                      1))
8954                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8955
8956         if (allow_power_down) {
8957                 val = I915_READ(LCPLL_CTL);
8958                 val |= LCPLL_POWER_DOWN_ALLOW;
8959                 I915_WRITE(LCPLL_CTL, val);
8960                 POSTING_READ(LCPLL_CTL);
8961         }
8962 }
8963
8964 /*
8965  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8966  * source.
8967  */
8968 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8969 {
8970         uint32_t val;
8971
8972         val = I915_READ(LCPLL_CTL);
8973
8974         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8975                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8976                 return;
8977
8978         /*
8979          * Make sure we're not on PC8 state before disabling PC8, otherwise
8980          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8981          */
8982         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8983
8984         if (val & LCPLL_POWER_DOWN_ALLOW) {
8985                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8986                 I915_WRITE(LCPLL_CTL, val);
8987                 POSTING_READ(LCPLL_CTL);
8988         }
8989
8990         val = hsw_read_dcomp(dev_priv);
8991         val |= D_COMP_COMP_FORCE;
8992         val &= ~D_COMP_COMP_DISABLE;
8993         hsw_write_dcomp(dev_priv, val);
8994
8995         val = I915_READ(LCPLL_CTL);
8996         val &= ~LCPLL_PLL_DISABLE;
8997         I915_WRITE(LCPLL_CTL, val);
8998
8999         if (intel_wait_for_register(dev_priv,
9000                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
9001                                     5))
9002                 DRM_ERROR("LCPLL not locked yet\n");
9003
9004         if (val & LCPLL_CD_SOURCE_FCLK) {
9005                 val = I915_READ(LCPLL_CTL);
9006                 val &= ~LCPLL_CD_SOURCE_FCLK;
9007                 I915_WRITE(LCPLL_CTL, val);
9008
9009                 if (wait_for_us((I915_READ(LCPLL_CTL) &
9010                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9011                         DRM_ERROR("Switching back to LCPLL failed\n");
9012         }
9013
9014         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9015
9016         intel_update_cdclk(dev_priv);
9017         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
9018 }
9019
9020 /*
9021  * Package states C8 and deeper are really deep PC states that can only be
9022  * reached when all the devices on the system allow it, so even if the graphics
9023  * device allows PC8+, it doesn't mean the system will actually get to these
9024  * states. Our driver only allows PC8+ when going into runtime PM.
9025  *
9026  * The requirements for PC8+ are that all the outputs are disabled, the power
9027  * well is disabled and most interrupts are disabled, and these are also
9028  * requirements for runtime PM. When these conditions are met, we manually do
9029  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9030  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9031  * hang the machine.
9032  *
9033  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9034  * the state of some registers, so when we come back from PC8+ we need to
9035  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9036  * need to take care of the registers kept by RC6. Notice that this happens even
9037  * if we don't put the device in PCI D3 state (which is what currently happens
9038  * because of the runtime PM support).
9039  *
9040  * For more, read "Display Sequences for Package C8" on the hardware
9041  * documentation.
9042  */
9043 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9044 {
9045         uint32_t val;
9046
9047         DRM_DEBUG_KMS("Enabling package C8+\n");
9048
9049         if (HAS_PCH_LPT_LP(dev_priv)) {
9050                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9051                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9052                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9053         }
9054
9055         lpt_disable_clkout_dp(dev_priv);
9056         hsw_disable_lcpll(dev_priv, true, true);
9057 }
9058
9059 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9060 {
9061         uint32_t val;
9062
9063         DRM_DEBUG_KMS("Disabling package C8+\n");
9064
9065         hsw_restore_lcpll(dev_priv);
9066         lpt_init_pch_refclk(dev_priv);
9067
9068         if (HAS_PCH_LPT_LP(dev_priv)) {
9069                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9070                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9071                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9072         }
9073 }
9074
9075 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9076                                       struct intel_crtc_state *crtc_state)
9077 {
9078         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9079                 struct intel_encoder *encoder =
9080                         intel_ddi_get_crtc_new_encoder(crtc_state);
9081
9082                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9083                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9084                                          pipe_name(crtc->pipe));
9085                         return -EINVAL;
9086                 }
9087         }
9088
9089         return 0;
9090 }
9091
9092 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9093                                    enum port port,
9094                                    struct intel_crtc_state *pipe_config)
9095 {
9096         enum intel_dpll_id id;
9097         u32 temp;
9098
9099         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9100         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9101
9102         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9103                 return;
9104
9105         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9106 }
9107
9108 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9109                                 enum port port,
9110                                 struct intel_crtc_state *pipe_config)
9111 {
9112         enum intel_dpll_id id;
9113
9114         switch (port) {
9115         case PORT_A:
9116                 id = DPLL_ID_SKL_DPLL0;
9117                 break;
9118         case PORT_B:
9119                 id = DPLL_ID_SKL_DPLL1;
9120                 break;
9121         case PORT_C:
9122                 id = DPLL_ID_SKL_DPLL2;
9123                 break;
9124         default:
9125                 DRM_ERROR("Incorrect port type\n");
9126                 return;
9127         }
9128
9129         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9130 }
9131
9132 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9133                                 enum port port,
9134                                 struct intel_crtc_state *pipe_config)
9135 {
9136         enum intel_dpll_id id;
9137         u32 temp;
9138
9139         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9140         id = temp >> (port * 3 + 1);
9141
9142         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9143                 return;
9144
9145         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9146 }
9147
9148 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9149                                 enum port port,
9150                                 struct intel_crtc_state *pipe_config)
9151 {
9152         enum intel_dpll_id id;
9153         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9154
9155         switch (ddi_pll_sel) {
9156         case PORT_CLK_SEL_WRPLL1:
9157                 id = DPLL_ID_WRPLL1;
9158                 break;
9159         case PORT_CLK_SEL_WRPLL2:
9160                 id = DPLL_ID_WRPLL2;
9161                 break;
9162         case PORT_CLK_SEL_SPLL:
9163                 id = DPLL_ID_SPLL;
9164                 break;
9165         case PORT_CLK_SEL_LCPLL_810:
9166                 id = DPLL_ID_LCPLL_810;
9167                 break;
9168         case PORT_CLK_SEL_LCPLL_1350:
9169                 id = DPLL_ID_LCPLL_1350;
9170                 break;
9171         case PORT_CLK_SEL_LCPLL_2700:
9172                 id = DPLL_ID_LCPLL_2700;
9173                 break;
9174         default:
9175                 MISSING_CASE(ddi_pll_sel);
9176                 /* fall through */
9177         case PORT_CLK_SEL_NONE:
9178                 return;
9179         }
9180
9181         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9182 }
9183
9184 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9185                                      struct intel_crtc_state *pipe_config,
9186                                      u64 *power_domain_mask)
9187 {
9188         struct drm_device *dev = crtc->base.dev;
9189         struct drm_i915_private *dev_priv = to_i915(dev);
9190         enum intel_display_power_domain power_domain;
9191         u32 tmp;
9192
9193         /*
9194          * The pipe->transcoder mapping is fixed with the exception of the eDP
9195          * transcoder handled below.
9196          */
9197         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9198
9199         /*
9200          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9201          * consistency and less surprising code; it's in always on power).
9202          */
9203         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9204         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9205                 enum pipe trans_edp_pipe;
9206                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9207                 default:
9208                         WARN(1, "unknown pipe linked to edp transcoder\n");
9209                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9210                 case TRANS_DDI_EDP_INPUT_A_ON:
9211                         trans_edp_pipe = PIPE_A;
9212                         break;
9213                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9214                         trans_edp_pipe = PIPE_B;
9215                         break;
9216                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9217                         trans_edp_pipe = PIPE_C;
9218                         break;
9219                 }
9220
9221                 if (trans_edp_pipe == crtc->pipe)
9222                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9223         }
9224
9225         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9226         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9227                 return false;
9228         *power_domain_mask |= BIT_ULL(power_domain);
9229
9230         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9231
9232         return tmp & PIPECONF_ENABLE;
9233 }
9234
9235 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9236                                          struct intel_crtc_state *pipe_config,
9237                                          u64 *power_domain_mask)
9238 {
9239         struct drm_device *dev = crtc->base.dev;
9240         struct drm_i915_private *dev_priv = to_i915(dev);
9241         enum intel_display_power_domain power_domain;
9242         enum port port;
9243         enum transcoder cpu_transcoder;
9244         u32 tmp;
9245
9246         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9247                 if (port == PORT_A)
9248                         cpu_transcoder = TRANSCODER_DSI_A;
9249                 else
9250                         cpu_transcoder = TRANSCODER_DSI_C;
9251
9252                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9253                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9254                         continue;
9255                 *power_domain_mask |= BIT_ULL(power_domain);
9256
9257                 /*
9258                  * The PLL needs to be enabled with a valid divider
9259                  * configuration, otherwise accessing DSI registers will hang
9260                  * the machine. See BSpec North Display Engine
9261                  * registers/MIPI[BXT]. We can break out here early, since we
9262                  * need the same DSI PLL to be enabled for both DSI ports.
9263                  */
9264                 if (!intel_dsi_pll_is_enabled(dev_priv))
9265                         break;
9266
9267                 /* XXX: this works for video mode only */
9268                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9269                 if (!(tmp & DPI_ENABLE))
9270                         continue;
9271
9272                 tmp = I915_READ(MIPI_CTRL(port));
9273                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9274                         continue;
9275
9276                 pipe_config->cpu_transcoder = cpu_transcoder;
9277                 break;
9278         }
9279
9280         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9281 }
9282
9283 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9284                                        struct intel_crtc_state *pipe_config)
9285 {
9286         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9287         struct intel_shared_dpll *pll;
9288         enum port port;
9289         uint32_t tmp;
9290
9291         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9292
9293         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9294
9295         if (IS_CANNONLAKE(dev_priv))
9296                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9297         else if (IS_GEN9_BC(dev_priv))
9298                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9299         else if (IS_GEN9_LP(dev_priv))
9300                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9301         else
9302                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9303
9304         pll = pipe_config->shared_dpll;
9305         if (pll) {
9306                 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
9307                                                 &pipe_config->dpll_hw_state));
9308         }
9309
9310         /*
9311          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9312          * DDI E. So just check whether this pipe is wired to DDI E and whether
9313          * the PCH transcoder is on.
9314          */
9315         if (INTEL_GEN(dev_priv) < 9 &&
9316             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9317                 pipe_config->has_pch_encoder = true;
9318
9319                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9320                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9321                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9322
9323                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9324         }
9325 }
9326
9327 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9328                                     struct intel_crtc_state *pipe_config)
9329 {
9330         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9331         enum intel_display_power_domain power_domain;
9332         u64 power_domain_mask;
9333         bool active;
9334
9335         intel_crtc_init_scalers(crtc, pipe_config);
9336
9337         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9338         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9339                 return false;
9340         power_domain_mask = BIT_ULL(power_domain);
9341
9342         pipe_config->shared_dpll = NULL;
9343
9344         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9345
9346         if (IS_GEN9_LP(dev_priv) &&
9347             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9348                 WARN_ON(active);
9349                 active = true;
9350         }
9351
9352         if (!active)
9353                 goto out;
9354
9355         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9356                 haswell_get_ddi_port_state(crtc, pipe_config);
9357                 intel_get_pipe_timings(crtc, pipe_config);
9358         }
9359
9360         intel_get_pipe_src_size(crtc, pipe_config);
9361
9362         pipe_config->gamma_mode =
9363                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9364
9365         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
9366                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9367                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9368
9369                 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
9370                         bool blend_mode_420 = tmp &
9371                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9372
9373                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9374                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9375                             pipe_config->ycbcr420 != blend_mode_420)
9376                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9377                 } else if (clrspace_yuv) {
9378                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9379                 }
9380         }
9381
9382         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9383         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9384                 power_domain_mask |= BIT_ULL(power_domain);
9385                 if (INTEL_GEN(dev_priv) >= 9)
9386                         skylake_get_pfit_config(crtc, pipe_config);
9387                 else
9388                         ironlake_get_pfit_config(crtc, pipe_config);
9389         }
9390
9391         if (hsw_crtc_supports_ips(crtc)) {
9392                 if (IS_HASWELL(dev_priv))
9393                         pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
9394                 else {
9395                         /*
9396                          * We cannot readout IPS state on broadwell, set to
9397                          * true so we can set it to a defined state on first
9398                          * commit.
9399                          */
9400                         pipe_config->ips_enabled = true;
9401                 }
9402         }
9403
9404         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9405             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9406                 pipe_config->pixel_multiplier =
9407                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9408         } else {
9409                 pipe_config->pixel_multiplier = 1;
9410         }
9411
9412 out:
9413         for_each_power_domain(power_domain, power_domain_mask)
9414                 intel_display_power_put(dev_priv, power_domain);
9415
9416         return active;
9417 }
9418
9419 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9420 {
9421         struct drm_i915_private *dev_priv =
9422                 to_i915(plane_state->base.plane->dev);
9423         const struct drm_framebuffer *fb = plane_state->base.fb;
9424         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9425         u32 base;
9426
9427         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9428                 base = obj->phys_handle->busaddr;
9429         else
9430                 base = intel_plane_ggtt_offset(plane_state);
9431
9432         base += plane_state->main.offset;
9433
9434         /* ILK+ do this automagically */
9435         if (HAS_GMCH_DISPLAY(dev_priv) &&
9436             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9437                 base += (plane_state->base.crtc_h *
9438                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9439
9440         return base;
9441 }
9442
9443 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9444 {
9445         int x = plane_state->base.crtc_x;
9446         int y = plane_state->base.crtc_y;
9447         u32 pos = 0;
9448
9449         if (x < 0) {
9450                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9451                 x = -x;
9452         }
9453         pos |= x << CURSOR_X_SHIFT;
9454
9455         if (y < 0) {
9456                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9457                 y = -y;
9458         }
9459         pos |= y << CURSOR_Y_SHIFT;
9460
9461         return pos;
9462 }
9463
9464 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9465 {
9466         const struct drm_mode_config *config =
9467                 &plane_state->base.plane->dev->mode_config;
9468         int width = plane_state->base.crtc_w;
9469         int height = plane_state->base.crtc_h;
9470
9471         return width > 0 && width <= config->cursor_width &&
9472                 height > 0 && height <= config->cursor_height;
9473 }
9474
9475 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9476                               struct intel_plane_state *plane_state)
9477 {
9478         const struct drm_framebuffer *fb = plane_state->base.fb;
9479         int src_x, src_y;
9480         u32 offset;
9481         int ret;
9482
9483         ret = drm_atomic_helper_check_plane_state(&plane_state->base,
9484                                                   &crtc_state->base,
9485                                                   DRM_PLANE_HELPER_NO_SCALING,
9486                                                   DRM_PLANE_HELPER_NO_SCALING,
9487                                                   true, true);
9488         if (ret)
9489                 return ret;
9490
9491         if (!fb)
9492                 return 0;
9493
9494         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9495                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9496                 return -EINVAL;
9497         }
9498
9499         src_x = plane_state->base.src_x >> 16;
9500         src_y = plane_state->base.src_y >> 16;
9501
9502         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9503         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9504
9505         if (src_x != 0 || src_y != 0) {
9506                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9507                 return -EINVAL;
9508         }
9509
9510         plane_state->main.offset = offset;
9511
9512         return 0;
9513 }
9514
9515 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9516                            const struct intel_plane_state *plane_state)
9517 {
9518         const struct drm_framebuffer *fb = plane_state->base.fb;
9519
9520         return CURSOR_ENABLE |
9521                 CURSOR_GAMMA_ENABLE |
9522                 CURSOR_FORMAT_ARGB |
9523                 CURSOR_STRIDE(fb->pitches[0]);
9524 }
9525
9526 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9527 {
9528         int width = plane_state->base.crtc_w;
9529
9530         /*
9531          * 845g/865g are only limited by the width of their cursors,
9532          * the height is arbitrary up to the precision of the register.
9533          */
9534         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9535 }
9536
9537 static int i845_check_cursor(struct intel_plane *plane,
9538                              struct intel_crtc_state *crtc_state,
9539                              struct intel_plane_state *plane_state)
9540 {
9541         const struct drm_framebuffer *fb = plane_state->base.fb;
9542         int ret;
9543
9544         ret = intel_check_cursor(crtc_state, plane_state);
9545         if (ret)
9546                 return ret;
9547
9548         /* if we want to turn off the cursor ignore width and height */
9549         if (!fb)
9550                 return 0;
9551
9552         /* Check for which cursor types we support */
9553         if (!i845_cursor_size_ok(plane_state)) {
9554                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9555                           plane_state->base.crtc_w,
9556                           plane_state->base.crtc_h);
9557                 return -EINVAL;
9558         }
9559
9560         switch (fb->pitches[0]) {
9561         case 256:
9562         case 512:
9563         case 1024:
9564         case 2048:
9565                 break;
9566         default:
9567                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9568                               fb->pitches[0]);
9569                 return -EINVAL;
9570         }
9571
9572         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9573
9574         return 0;
9575 }
9576
9577 static void i845_update_cursor(struct intel_plane *plane,
9578                                const struct intel_crtc_state *crtc_state,
9579                                const struct intel_plane_state *plane_state)
9580 {
9581         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9582         u32 cntl = 0, base = 0, pos = 0, size = 0;
9583         unsigned long irqflags;
9584
9585         if (plane_state && plane_state->base.visible) {
9586                 unsigned int width = plane_state->base.crtc_w;
9587                 unsigned int height = plane_state->base.crtc_h;
9588
9589                 cntl = plane_state->ctl;
9590                 size = (height << 12) | width;
9591
9592                 base = intel_cursor_base(plane_state);
9593                 pos = intel_cursor_position(plane_state);
9594         }
9595
9596         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9597
9598         /* On these chipsets we can only modify the base/size/stride
9599          * whilst the cursor is disabled.
9600          */
9601         if (plane->cursor.base != base ||
9602             plane->cursor.size != size ||
9603             plane->cursor.cntl != cntl) {
9604                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9605                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9606                 I915_WRITE_FW(CURSIZE, size);
9607                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9608                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9609
9610                 plane->cursor.base = base;
9611                 plane->cursor.size = size;
9612                 plane->cursor.cntl = cntl;
9613         } else {
9614                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9615         }
9616
9617         POSTING_READ_FW(CURCNTR(PIPE_A));
9618
9619         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9620 }
9621
9622 static void i845_disable_cursor(struct intel_plane *plane,
9623                                 struct intel_crtc *crtc)
9624 {
9625         i845_update_cursor(plane, NULL, NULL);
9626 }
9627
9628 static bool i845_cursor_get_hw_state(struct intel_plane *plane)
9629 {
9630         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9631         enum intel_display_power_domain power_domain;
9632         bool ret;
9633
9634         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
9635         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9636                 return false;
9637
9638         ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
9639
9640         intel_display_power_put(dev_priv, power_domain);
9641
9642         return ret;
9643 }
9644
9645 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9646                            const struct intel_plane_state *plane_state)
9647 {
9648         struct drm_i915_private *dev_priv =
9649                 to_i915(plane_state->base.plane->dev);
9650         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9651         u32 cntl;
9652
9653         cntl = MCURSOR_GAMMA_ENABLE;
9654
9655         if (HAS_DDI(dev_priv))
9656                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9657
9658         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
9659                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9660
9661         switch (plane_state->base.crtc_w) {
9662         case 64:
9663                 cntl |= CURSOR_MODE_64_ARGB_AX;
9664                 break;
9665         case 128:
9666                 cntl |= CURSOR_MODE_128_ARGB_AX;
9667                 break;
9668         case 256:
9669                 cntl |= CURSOR_MODE_256_ARGB_AX;
9670                 break;
9671         default:
9672                 MISSING_CASE(plane_state->base.crtc_w);
9673                 return 0;
9674         }
9675
9676         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9677                 cntl |= CURSOR_ROTATE_180;
9678
9679         return cntl;
9680 }
9681
9682 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9683 {
9684         struct drm_i915_private *dev_priv =
9685                 to_i915(plane_state->base.plane->dev);
9686         int width = plane_state->base.crtc_w;
9687         int height = plane_state->base.crtc_h;
9688
9689         if (!intel_cursor_size_ok(plane_state))
9690                 return false;
9691
9692         /* Cursor width is limited to a few power-of-two sizes */
9693         switch (width) {
9694         case 256:
9695         case 128:
9696         case 64:
9697                 break;
9698         default:
9699                 return false;
9700         }
9701
9702         /*
9703          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9704          * height from 8 lines up to the cursor width, when the
9705          * cursor is not rotated. Everything else requires square
9706          * cursors.
9707          */
9708         if (HAS_CUR_FBC(dev_priv) &&
9709             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9710                 if (height < 8 || height > width)
9711                         return false;
9712         } else {
9713                 if (height != width)
9714                         return false;
9715         }
9716
9717         return true;
9718 }
9719
9720 static int i9xx_check_cursor(struct intel_plane *plane,
9721                              struct intel_crtc_state *crtc_state,
9722                              struct intel_plane_state *plane_state)
9723 {
9724         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9725         const struct drm_framebuffer *fb = plane_state->base.fb;
9726         enum pipe pipe = plane->pipe;
9727         int ret;
9728
9729         ret = intel_check_cursor(crtc_state, plane_state);
9730         if (ret)
9731                 return ret;
9732
9733         /* if we want to turn off the cursor ignore width and height */
9734         if (!fb)
9735                 return 0;
9736
9737         /* Check for which cursor types we support */
9738         if (!i9xx_cursor_size_ok(plane_state)) {
9739                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9740                           plane_state->base.crtc_w,
9741                           plane_state->base.crtc_h);
9742                 return -EINVAL;
9743         }
9744
9745         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9746                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9747                               fb->pitches[0], plane_state->base.crtc_w);
9748                 return -EINVAL;
9749         }
9750
9751         /*
9752          * There's something wrong with the cursor on CHV pipe C.
9753          * If it straddles the left edge of the screen then
9754          * moving it away from the edge or disabling it often
9755          * results in a pipe underrun, and often that can lead to
9756          * dead pipe (constant underrun reported, and it scans
9757          * out just a solid color). To recover from that, the
9758          * display power well must be turned off and on again.
9759          * Refuse the put the cursor into that compromised position.
9760          */
9761         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9762             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9763                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9764                 return -EINVAL;
9765         }
9766
9767         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9768
9769         return 0;
9770 }
9771
9772 static void i9xx_update_cursor(struct intel_plane *plane,
9773                                const struct intel_crtc_state *crtc_state,
9774                                const struct intel_plane_state *plane_state)
9775 {
9776         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9777         enum pipe pipe = plane->pipe;
9778         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9779         unsigned long irqflags;
9780
9781         if (plane_state && plane_state->base.visible) {
9782                 cntl = plane_state->ctl;
9783
9784                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9785                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9786
9787                 base = intel_cursor_base(plane_state);
9788                 pos = intel_cursor_position(plane_state);
9789         }
9790
9791         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9792
9793         /*
9794          * On some platforms writing CURCNTR first will also
9795          * cause CURPOS to be armed by the CURBASE write.
9796          * Without the CURCNTR write the CURPOS write would
9797          * arm itself. Thus we always start the full update
9798          * with a CURCNTR write.
9799          *
9800          * On other platforms CURPOS always requires the
9801          * CURBASE write to arm the update. Additonally
9802          * a write to any of the cursor register will cancel
9803          * an already armed cursor update. Thus leaving out
9804          * the CURBASE write after CURPOS could lead to a
9805          * cursor that doesn't appear to move, or even change
9806          * shape. Thus we always write CURBASE.
9807          *
9808          * CURCNTR and CUR_FBC_CTL are always
9809          * armed by the CURBASE write only.
9810          */
9811         if (plane->cursor.base != base ||
9812             plane->cursor.size != fbc_ctl ||
9813             plane->cursor.cntl != cntl) {
9814                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9815                 if (HAS_CUR_FBC(dev_priv))
9816                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9817                 I915_WRITE_FW(CURPOS(pipe), pos);
9818                 I915_WRITE_FW(CURBASE(pipe), base);
9819
9820                 plane->cursor.base = base;
9821                 plane->cursor.size = fbc_ctl;
9822                 plane->cursor.cntl = cntl;
9823         } else {
9824                 I915_WRITE_FW(CURPOS(pipe), pos);
9825                 I915_WRITE_FW(CURBASE(pipe), base);
9826         }
9827
9828         POSTING_READ_FW(CURBASE(pipe));
9829
9830         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9831 }
9832
9833 static void i9xx_disable_cursor(struct intel_plane *plane,
9834                                 struct intel_crtc *crtc)
9835 {
9836         i9xx_update_cursor(plane, NULL, NULL);
9837 }
9838
9839 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
9840 {
9841         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9842         enum intel_display_power_domain power_domain;
9843         enum pipe pipe = plane->pipe;
9844         bool ret;
9845
9846         /*
9847          * Not 100% correct for planes that can move between pipes,
9848          * but that's only the case for gen2-3 which don't have any
9849          * display power wells.
9850          */
9851         power_domain = POWER_DOMAIN_PIPE(pipe);
9852         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9853                 return false;
9854
9855         ret = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
9856
9857         intel_display_power_put(dev_priv, power_domain);
9858
9859         return ret;
9860 }
9861
9862 /* VESA 640x480x72Hz mode to set on the pipe */
9863 static const struct drm_display_mode load_detect_mode = {
9864         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9865                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9866 };
9867
9868 struct drm_framebuffer *
9869 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9870                          struct drm_mode_fb_cmd2 *mode_cmd)
9871 {
9872         struct intel_framebuffer *intel_fb;
9873         int ret;
9874
9875         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9876         if (!intel_fb)
9877                 return ERR_PTR(-ENOMEM);
9878
9879         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9880         if (ret)
9881                 goto err;
9882
9883         return &intel_fb->base;
9884
9885 err:
9886         kfree(intel_fb);
9887         return ERR_PTR(ret);
9888 }
9889
9890 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
9891                                         struct drm_crtc *crtc)
9892 {
9893         struct drm_plane *plane;
9894         struct drm_plane_state *plane_state;
9895         int ret, i;
9896
9897         ret = drm_atomic_add_affected_planes(state, crtc);
9898         if (ret)
9899                 return ret;
9900
9901         for_each_new_plane_in_state(state, plane, plane_state, i) {
9902                 if (plane_state->crtc != crtc)
9903                         continue;
9904
9905                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
9906                 if (ret)
9907                         return ret;
9908
9909                 drm_atomic_set_fb_for_plane(plane_state, NULL);
9910         }
9911
9912         return 0;
9913 }
9914
9915 int intel_get_load_detect_pipe(struct drm_connector *connector,
9916                                const struct drm_display_mode *mode,
9917                                struct intel_load_detect_pipe *old,
9918                                struct drm_modeset_acquire_ctx *ctx)
9919 {
9920         struct intel_crtc *intel_crtc;
9921         struct intel_encoder *intel_encoder =
9922                 intel_attached_encoder(connector);
9923         struct drm_crtc *possible_crtc;
9924         struct drm_encoder *encoder = &intel_encoder->base;
9925         struct drm_crtc *crtc = NULL;
9926         struct drm_device *dev = encoder->dev;
9927         struct drm_i915_private *dev_priv = to_i915(dev);
9928         struct drm_mode_config *config = &dev->mode_config;
9929         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9930         struct drm_connector_state *connector_state;
9931         struct intel_crtc_state *crtc_state;
9932         int ret, i = -1;
9933
9934         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9935                       connector->base.id, connector->name,
9936                       encoder->base.id, encoder->name);
9937
9938         old->restore_state = NULL;
9939
9940         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9941
9942         /*
9943          * Algorithm gets a little messy:
9944          *
9945          *   - if the connector already has an assigned crtc, use it (but make
9946          *     sure it's on first)
9947          *
9948          *   - try to find the first unused crtc that can drive this connector,
9949          *     and use that if we find one
9950          */
9951
9952         /* See if we already have a CRTC for this connector */
9953         if (connector->state->crtc) {
9954                 crtc = connector->state->crtc;
9955
9956                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9957                 if (ret)
9958                         goto fail;
9959
9960                 /* Make sure the crtc and connector are running */
9961                 goto found;
9962         }
9963
9964         /* Find an unused one (if possible) */
9965         for_each_crtc(dev, possible_crtc) {
9966                 i++;
9967                 if (!(encoder->possible_crtcs & (1 << i)))
9968                         continue;
9969
9970                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9971                 if (ret)
9972                         goto fail;
9973
9974                 if (possible_crtc->state->enable) {
9975                         drm_modeset_unlock(&possible_crtc->mutex);
9976                         continue;
9977                 }
9978
9979                 crtc = possible_crtc;
9980                 break;
9981         }
9982
9983         /*
9984          * If we didn't find an unused CRTC, don't use any.
9985          */
9986         if (!crtc) {
9987                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9988                 ret = -ENODEV;
9989                 goto fail;
9990         }
9991
9992 found:
9993         intel_crtc = to_intel_crtc(crtc);
9994
9995         state = drm_atomic_state_alloc(dev);
9996         restore_state = drm_atomic_state_alloc(dev);
9997         if (!state || !restore_state) {
9998                 ret = -ENOMEM;
9999                 goto fail;
10000         }
10001
10002         state->acquire_ctx = ctx;
10003         restore_state->acquire_ctx = ctx;
10004
10005         connector_state = drm_atomic_get_connector_state(state, connector);
10006         if (IS_ERR(connector_state)) {
10007                 ret = PTR_ERR(connector_state);
10008                 goto fail;
10009         }
10010
10011         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10012         if (ret)
10013                 goto fail;
10014
10015         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10016         if (IS_ERR(crtc_state)) {
10017                 ret = PTR_ERR(crtc_state);
10018                 goto fail;
10019         }
10020
10021         crtc_state->base.active = crtc_state->base.enable = true;
10022
10023         if (!mode)
10024                 mode = &load_detect_mode;
10025
10026         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10027         if (ret)
10028                 goto fail;
10029
10030         ret = intel_modeset_disable_planes(state, crtc);
10031         if (ret)
10032                 goto fail;
10033
10034         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10035         if (!ret)
10036                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10037         if (!ret)
10038                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
10039         if (ret) {
10040                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10041                 goto fail;
10042         }
10043
10044         ret = drm_atomic_commit(state);
10045         if (ret) {
10046                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10047                 goto fail;
10048         }
10049
10050         old->restore_state = restore_state;
10051         drm_atomic_state_put(state);
10052
10053         /* let the connector get through one full cycle before testing */
10054         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10055         return true;
10056
10057 fail:
10058         if (state) {
10059                 drm_atomic_state_put(state);
10060                 state = NULL;
10061         }
10062         if (restore_state) {
10063                 drm_atomic_state_put(restore_state);
10064                 restore_state = NULL;
10065         }
10066
10067         if (ret == -EDEADLK)
10068                 return ret;
10069
10070         return false;
10071 }
10072
10073 void intel_release_load_detect_pipe(struct drm_connector *connector,
10074                                     struct intel_load_detect_pipe *old,
10075                                     struct drm_modeset_acquire_ctx *ctx)
10076 {
10077         struct intel_encoder *intel_encoder =
10078                 intel_attached_encoder(connector);
10079         struct drm_encoder *encoder = &intel_encoder->base;
10080         struct drm_atomic_state *state = old->restore_state;
10081         int ret;
10082
10083         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10084                       connector->base.id, connector->name,
10085                       encoder->base.id, encoder->name);
10086
10087         if (!state)
10088                 return;
10089
10090         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10091         if (ret)
10092                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10093         drm_atomic_state_put(state);
10094 }
10095
10096 static int i9xx_pll_refclk(struct drm_device *dev,
10097                            const struct intel_crtc_state *pipe_config)
10098 {
10099         struct drm_i915_private *dev_priv = to_i915(dev);
10100         u32 dpll = pipe_config->dpll_hw_state.dpll;
10101
10102         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10103                 return dev_priv->vbt.lvds_ssc_freq;
10104         else if (HAS_PCH_SPLIT(dev_priv))
10105                 return 120000;
10106         else if (!IS_GEN2(dev_priv))
10107                 return 96000;
10108         else
10109                 return 48000;
10110 }
10111
10112 /* Returns the clock of the currently programmed mode of the given pipe. */
10113 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10114                                 struct intel_crtc_state *pipe_config)
10115 {
10116         struct drm_device *dev = crtc->base.dev;
10117         struct drm_i915_private *dev_priv = to_i915(dev);
10118         int pipe = pipe_config->cpu_transcoder;
10119         u32 dpll = pipe_config->dpll_hw_state.dpll;
10120         u32 fp;
10121         struct dpll clock;
10122         int port_clock;
10123         int refclk = i9xx_pll_refclk(dev, pipe_config);
10124
10125         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10126                 fp = pipe_config->dpll_hw_state.fp0;
10127         else
10128                 fp = pipe_config->dpll_hw_state.fp1;
10129
10130         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10131         if (IS_PINEVIEW(dev_priv)) {
10132                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10133                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10134         } else {
10135                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10136                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10137         }
10138
10139         if (!IS_GEN2(dev_priv)) {
10140                 if (IS_PINEVIEW(dev_priv))
10141                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10142                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10143                 else
10144                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10145                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10146
10147                 switch (dpll & DPLL_MODE_MASK) {
10148                 case DPLLB_MODE_DAC_SERIAL:
10149                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10150                                 5 : 10;
10151                         break;
10152                 case DPLLB_MODE_LVDS:
10153                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10154                                 7 : 14;
10155                         break;
10156                 default:
10157                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10158                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10159                         return;
10160                 }
10161
10162                 if (IS_PINEVIEW(dev_priv))
10163                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10164                 else
10165                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10166         } else {
10167                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10168                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10169
10170                 if (is_lvds) {
10171                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10172                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10173
10174                         if (lvds & LVDS_CLKB_POWER_UP)
10175                                 clock.p2 = 7;
10176                         else
10177                                 clock.p2 = 14;
10178                 } else {
10179                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10180                                 clock.p1 = 2;
10181                         else {
10182                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10183                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10184                         }
10185                         if (dpll & PLL_P2_DIVIDE_BY_4)
10186                                 clock.p2 = 4;
10187                         else
10188                                 clock.p2 = 2;
10189                 }
10190
10191                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10192         }
10193
10194         /*
10195          * This value includes pixel_multiplier. We will use
10196          * port_clock to compute adjusted_mode.crtc_clock in the
10197          * encoder's get_config() function.
10198          */
10199         pipe_config->port_clock = port_clock;
10200 }
10201
10202 int intel_dotclock_calculate(int link_freq,
10203                              const struct intel_link_m_n *m_n)
10204 {
10205         /*
10206          * The calculation for the data clock is:
10207          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10208          * But we want to avoid losing precison if possible, so:
10209          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10210          *
10211          * and the link clock is simpler:
10212          * link_clock = (m * link_clock) / n
10213          */
10214
10215         if (!m_n->link_n)
10216                 return 0;
10217
10218         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
10219 }
10220
10221 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10222                                    struct intel_crtc_state *pipe_config)
10223 {
10224         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10225
10226         /* read out port_clock from the DPLL */
10227         i9xx_crtc_clock_get(crtc, pipe_config);
10228
10229         /*
10230          * In case there is an active pipe without active ports,
10231          * we may need some idea for the dotclock anyway.
10232          * Calculate one based on the FDI configuration.
10233          */
10234         pipe_config->base.adjusted_mode.crtc_clock =
10235                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10236                                          &pipe_config->fdi_m_n);
10237 }
10238
10239 /* Returns the currently programmed mode of the given encoder. */
10240 struct drm_display_mode *
10241 intel_encoder_current_mode(struct intel_encoder *encoder)
10242 {
10243         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
10244         struct intel_crtc_state *crtc_state;
10245         struct drm_display_mode *mode;
10246         struct intel_crtc *crtc;
10247         enum pipe pipe;
10248
10249         if (!encoder->get_hw_state(encoder, &pipe))
10250                 return NULL;
10251
10252         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10253
10254         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10255         if (!mode)
10256                 return NULL;
10257
10258         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
10259         if (!crtc_state) {
10260                 kfree(mode);
10261                 return NULL;
10262         }
10263
10264         crtc_state->base.crtc = &crtc->base;
10265
10266         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
10267                 kfree(crtc_state);
10268                 kfree(mode);
10269                 return NULL;
10270         }
10271
10272         encoder->get_config(encoder, crtc_state);
10273
10274         intel_mode_from_pipe_config(mode, crtc_state);
10275
10276         kfree(crtc_state);
10277
10278         return mode;
10279 }
10280
10281 static void intel_crtc_destroy(struct drm_crtc *crtc)
10282 {
10283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10284
10285         drm_crtc_cleanup(crtc);
10286         kfree(intel_crtc);
10287 }
10288
10289 /**
10290  * intel_wm_need_update - Check whether watermarks need updating
10291  * @plane: drm plane
10292  * @state: new plane state
10293  *
10294  * Check current plane state versus the new one to determine whether
10295  * watermarks need to be recalculated.
10296  *
10297  * Returns true or false.
10298  */
10299 static bool intel_wm_need_update(struct drm_plane *plane,
10300                                  struct drm_plane_state *state)
10301 {
10302         struct intel_plane_state *new = to_intel_plane_state(state);
10303         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10304
10305         /* Update watermarks on tiling or size changes. */
10306         if (new->base.visible != cur->base.visible)
10307                 return true;
10308
10309         if (!cur->base.fb || !new->base.fb)
10310                 return false;
10311
10312         if (cur->base.fb->modifier != new->base.fb->modifier ||
10313             cur->base.rotation != new->base.rotation ||
10314             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10315             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10316             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10317             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10318                 return true;
10319
10320         return false;
10321 }
10322
10323 static bool needs_scaling(const struct intel_plane_state *state)
10324 {
10325         int src_w = drm_rect_width(&state->base.src) >> 16;
10326         int src_h = drm_rect_height(&state->base.src) >> 16;
10327         int dst_w = drm_rect_width(&state->base.dst);
10328         int dst_h = drm_rect_height(&state->base.dst);
10329
10330         return (src_w != dst_w || src_h != dst_h);
10331 }
10332
10333 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10334                                     struct drm_crtc_state *crtc_state,
10335                                     const struct intel_plane_state *old_plane_state,
10336                                     struct drm_plane_state *plane_state)
10337 {
10338         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10339         struct drm_crtc *crtc = crtc_state->crtc;
10340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10341         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10342         struct drm_device *dev = crtc->dev;
10343         struct drm_i915_private *dev_priv = to_i915(dev);
10344         bool mode_changed = needs_modeset(crtc_state);
10345         bool was_crtc_enabled = old_crtc_state->base.active;
10346         bool is_crtc_enabled = crtc_state->active;
10347         bool turn_off, turn_on, visible, was_visible;
10348         struct drm_framebuffer *fb = plane_state->fb;
10349         int ret;
10350
10351         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10352                 ret = skl_update_scaler_plane(
10353                         to_intel_crtc_state(crtc_state),
10354                         to_intel_plane_state(plane_state));
10355                 if (ret)
10356                         return ret;
10357         }
10358
10359         was_visible = old_plane_state->base.visible;
10360         visible = plane_state->visible;
10361
10362         if (!was_crtc_enabled && WARN_ON(was_visible))
10363                 was_visible = false;
10364
10365         /*
10366          * Visibility is calculated as if the crtc was on, but
10367          * after scaler setup everything depends on it being off
10368          * when the crtc isn't active.
10369          *
10370          * FIXME this is wrong for watermarks. Watermarks should also
10371          * be computed as if the pipe would be active. Perhaps move
10372          * per-plane wm computation to the .check_plane() hook, and
10373          * only combine the results from all planes in the current place?
10374          */
10375         if (!is_crtc_enabled) {
10376                 plane_state->visible = visible = false;
10377                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10378         }
10379
10380         if (!was_visible && !visible)
10381                 return 0;
10382
10383         if (fb != old_plane_state->base.fb)
10384                 pipe_config->fb_changed = true;
10385
10386         turn_off = was_visible && (!visible || mode_changed);
10387         turn_on = visible && (!was_visible || mode_changed);
10388
10389         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10390                          intel_crtc->base.base.id, intel_crtc->base.name,
10391                          plane->base.base.id, plane->base.name,
10392                          fb ? fb->base.id : -1);
10393
10394         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10395                          plane->base.base.id, plane->base.name,
10396                          was_visible, visible,
10397                          turn_off, turn_on, mode_changed);
10398
10399         if (turn_on) {
10400                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10401                         pipe_config->update_wm_pre = true;
10402
10403                 /* must disable cxsr around plane enable/disable */
10404                 if (plane->id != PLANE_CURSOR)
10405                         pipe_config->disable_cxsr = true;
10406         } else if (turn_off) {
10407                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10408                         pipe_config->update_wm_post = true;
10409
10410                 /* must disable cxsr around plane enable/disable */
10411                 if (plane->id != PLANE_CURSOR)
10412                         pipe_config->disable_cxsr = true;
10413         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10414                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10415                         /* FIXME bollocks */
10416                         pipe_config->update_wm_pre = true;
10417                         pipe_config->update_wm_post = true;
10418                 }
10419         }
10420
10421         if (visible || was_visible)
10422                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10423
10424         /*
10425          * WaCxSRDisabledForSpriteScaling:ivb
10426          *
10427          * cstate->update_wm was already set above, so this flag will
10428          * take effect when we commit and program watermarks.
10429          */
10430         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10431             needs_scaling(to_intel_plane_state(plane_state)) &&
10432             !needs_scaling(old_plane_state))
10433                 pipe_config->disable_lp_wm = true;
10434
10435         return 0;
10436 }
10437
10438 static bool encoders_cloneable(const struct intel_encoder *a,
10439                                const struct intel_encoder *b)
10440 {
10441         /* masks could be asymmetric, so check both ways */
10442         return a == b || (a->cloneable & (1 << b->type) &&
10443                           b->cloneable & (1 << a->type));
10444 }
10445
10446 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10447                                          struct intel_crtc *crtc,
10448                                          struct intel_encoder *encoder)
10449 {
10450         struct intel_encoder *source_encoder;
10451         struct drm_connector *connector;
10452         struct drm_connector_state *connector_state;
10453         int i;
10454
10455         for_each_new_connector_in_state(state, connector, connector_state, i) {
10456                 if (connector_state->crtc != &crtc->base)
10457                         continue;
10458
10459                 source_encoder =
10460                         to_intel_encoder(connector_state->best_encoder);
10461                 if (!encoders_cloneable(encoder, source_encoder))
10462                         return false;
10463         }
10464
10465         return true;
10466 }
10467
10468 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10469                                    struct drm_crtc_state *crtc_state)
10470 {
10471         struct drm_device *dev = crtc->dev;
10472         struct drm_i915_private *dev_priv = to_i915(dev);
10473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10474         struct intel_crtc_state *pipe_config =
10475                 to_intel_crtc_state(crtc_state);
10476         struct drm_atomic_state *state = crtc_state->state;
10477         int ret;
10478         bool mode_changed = needs_modeset(crtc_state);
10479
10480         if (mode_changed && !crtc_state->active)
10481                 pipe_config->update_wm_post = true;
10482
10483         if (mode_changed && crtc_state->enable &&
10484             dev_priv->display.crtc_compute_clock &&
10485             !WARN_ON(pipe_config->shared_dpll)) {
10486                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10487                                                            pipe_config);
10488                 if (ret)
10489                         return ret;
10490         }
10491
10492         if (crtc_state->color_mgmt_changed) {
10493                 ret = intel_color_check(crtc, crtc_state);
10494                 if (ret)
10495                         return ret;
10496
10497                 /*
10498                  * Changing color management on Intel hardware is
10499                  * handled as part of planes update.
10500                  */
10501                 crtc_state->planes_changed = true;
10502         }
10503
10504         ret = 0;
10505         if (dev_priv->display.compute_pipe_wm) {
10506                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10507                 if (ret) {
10508                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10509                         return ret;
10510                 }
10511         }
10512
10513         if (dev_priv->display.compute_intermediate_wm &&
10514             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10515                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10516                         return 0;
10517
10518                 /*
10519                  * Calculate 'intermediate' watermarks that satisfy both the
10520                  * old state and the new state.  We can program these
10521                  * immediately.
10522                  */
10523                 ret = dev_priv->display.compute_intermediate_wm(dev,
10524                                                                 intel_crtc,
10525                                                                 pipe_config);
10526                 if (ret) {
10527                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10528                         return ret;
10529                 }
10530         } else if (dev_priv->display.compute_intermediate_wm) {
10531                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10532                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10533         }
10534
10535         if (INTEL_GEN(dev_priv) >= 9) {
10536                 if (mode_changed)
10537                         ret = skl_update_scaler_crtc(pipe_config);
10538
10539                 if (!ret)
10540                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10541                                                             pipe_config);
10542                 if (!ret)
10543                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10544                                                          pipe_config);
10545         }
10546
10547         if (HAS_IPS(dev_priv))
10548                 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
10549
10550         return ret;
10551 }
10552
10553 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10554         .atomic_begin = intel_begin_crtc_commit,
10555         .atomic_flush = intel_finish_crtc_commit,
10556         .atomic_check = intel_crtc_atomic_check,
10557 };
10558
10559 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10560 {
10561         struct intel_connector *connector;
10562         struct drm_connector_list_iter conn_iter;
10563
10564         drm_connector_list_iter_begin(dev, &conn_iter);
10565         for_each_intel_connector_iter(connector, &conn_iter) {
10566                 if (connector->base.state->crtc)
10567                         drm_connector_unreference(&connector->base);
10568
10569                 if (connector->base.encoder) {
10570                         connector->base.state->best_encoder =
10571                                 connector->base.encoder;
10572                         connector->base.state->crtc =
10573                                 connector->base.encoder->crtc;
10574
10575                         drm_connector_reference(&connector->base);
10576                 } else {
10577                         connector->base.state->best_encoder = NULL;
10578                         connector->base.state->crtc = NULL;
10579                 }
10580         }
10581         drm_connector_list_iter_end(&conn_iter);
10582 }
10583
10584 static void
10585 connected_sink_compute_bpp(struct intel_connector *connector,
10586                            struct intel_crtc_state *pipe_config)
10587 {
10588         const struct drm_display_info *info = &connector->base.display_info;
10589         int bpp = pipe_config->pipe_bpp;
10590
10591         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10592                       connector->base.base.id,
10593                       connector->base.name);
10594
10595         /* Don't use an invalid EDID bpc value */
10596         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10597                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10598                               bpp, info->bpc * 3);
10599                 pipe_config->pipe_bpp = info->bpc * 3;
10600         }
10601
10602         /* Clamp bpp to 8 on screens without EDID 1.4 */
10603         if (info->bpc == 0 && bpp > 24) {
10604                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10605                               bpp);
10606                 pipe_config->pipe_bpp = 24;
10607         }
10608 }
10609
10610 static int
10611 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10612                           struct intel_crtc_state *pipe_config)
10613 {
10614         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10615         struct drm_atomic_state *state;
10616         struct drm_connector *connector;
10617         struct drm_connector_state *connector_state;
10618         int bpp, i;
10619
10620         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10621             IS_CHERRYVIEW(dev_priv)))
10622                 bpp = 10*3;
10623         else if (INTEL_GEN(dev_priv) >= 5)
10624                 bpp = 12*3;
10625         else
10626                 bpp = 8*3;
10627
10628
10629         pipe_config->pipe_bpp = bpp;
10630
10631         state = pipe_config->base.state;
10632
10633         /* Clamp display bpp to EDID value */
10634         for_each_new_connector_in_state(state, connector, connector_state, i) {
10635                 if (connector_state->crtc != &crtc->base)
10636                         continue;
10637
10638                 connected_sink_compute_bpp(to_intel_connector(connector),
10639                                            pipe_config);
10640         }
10641
10642         return bpp;
10643 }
10644
10645 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10646 {
10647         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10648                         "type: 0x%x flags: 0x%x\n",
10649                 mode->crtc_clock,
10650                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10651                 mode->crtc_hsync_end, mode->crtc_htotal,
10652                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10653                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10654 }
10655
10656 static inline void
10657 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10658                       unsigned int lane_count, struct intel_link_m_n *m_n)
10659 {
10660         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10661                       id, lane_count,
10662                       m_n->gmch_m, m_n->gmch_n,
10663                       m_n->link_m, m_n->link_n, m_n->tu);
10664 }
10665
10666 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
10667
10668 static const char * const output_type_str[] = {
10669         OUTPUT_TYPE(UNUSED),
10670         OUTPUT_TYPE(ANALOG),
10671         OUTPUT_TYPE(DVO),
10672         OUTPUT_TYPE(SDVO),
10673         OUTPUT_TYPE(LVDS),
10674         OUTPUT_TYPE(TVOUT),
10675         OUTPUT_TYPE(HDMI),
10676         OUTPUT_TYPE(DP),
10677         OUTPUT_TYPE(EDP),
10678         OUTPUT_TYPE(DSI),
10679         OUTPUT_TYPE(DDI),
10680         OUTPUT_TYPE(DP_MST),
10681 };
10682
10683 #undef OUTPUT_TYPE
10684
10685 static void snprintf_output_types(char *buf, size_t len,
10686                                   unsigned int output_types)
10687 {
10688         char *str = buf;
10689         int i;
10690
10691         str[0] = '\0';
10692
10693         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
10694                 int r;
10695
10696                 if ((output_types & BIT(i)) == 0)
10697                         continue;
10698
10699                 r = snprintf(str, len, "%s%s",
10700                              str != buf ? "," : "", output_type_str[i]);
10701                 if (r >= len)
10702                         break;
10703                 str += r;
10704                 len -= r;
10705
10706                 output_types &= ~BIT(i);
10707         }
10708
10709         WARN_ON_ONCE(output_types != 0);
10710 }
10711
10712 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10713                                    struct intel_crtc_state *pipe_config,
10714                                    const char *context)
10715 {
10716         struct drm_device *dev = crtc->base.dev;
10717         struct drm_i915_private *dev_priv = to_i915(dev);
10718         struct drm_plane *plane;
10719         struct intel_plane *intel_plane;
10720         struct intel_plane_state *state;
10721         struct drm_framebuffer *fb;
10722         char buf[64];
10723
10724         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10725                       crtc->base.base.id, crtc->base.name, context);
10726
10727         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
10728         DRM_DEBUG_KMS("output_types: %s (0x%x)\n",
10729                       buf, pipe_config->output_types);
10730
10731         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10732                       transcoder_name(pipe_config->cpu_transcoder),
10733                       pipe_config->pipe_bpp, pipe_config->dither);
10734
10735         if (pipe_config->has_pch_encoder)
10736                 intel_dump_m_n_config(pipe_config, "fdi",
10737                                       pipe_config->fdi_lanes,
10738                                       &pipe_config->fdi_m_n);
10739
10740         if (pipe_config->ycbcr420)
10741                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10742
10743         if (intel_crtc_has_dp_encoder(pipe_config)) {
10744                 intel_dump_m_n_config(pipe_config, "dp m_n",
10745                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10746                 if (pipe_config->has_drrs)
10747                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10748                                               pipe_config->lane_count,
10749                                               &pipe_config->dp_m2_n2);
10750         }
10751
10752         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10753                       pipe_config->has_audio, pipe_config->has_infoframe);
10754
10755         DRM_DEBUG_KMS("requested mode:\n");
10756         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10757         DRM_DEBUG_KMS("adjusted mode:\n");
10758         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10759         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10760         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10761                       pipe_config->port_clock,
10762                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10763                       pipe_config->pixel_rate);
10764
10765         if (INTEL_GEN(dev_priv) >= 9)
10766                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10767                               crtc->num_scalers,
10768                               pipe_config->scaler_state.scaler_users,
10769                               pipe_config->scaler_state.scaler_id);
10770
10771         if (HAS_GMCH_DISPLAY(dev_priv))
10772                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10773                               pipe_config->gmch_pfit.control,
10774                               pipe_config->gmch_pfit.pgm_ratios,
10775                               pipe_config->gmch_pfit.lvds_border_bits);
10776         else
10777                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10778                               pipe_config->pch_pfit.pos,
10779                               pipe_config->pch_pfit.size,
10780                               enableddisabled(pipe_config->pch_pfit.enabled));
10781
10782         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10783                       pipe_config->ips_enabled, pipe_config->double_wide);
10784
10785         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10786
10787         DRM_DEBUG_KMS("planes on this crtc\n");
10788         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10789                 struct drm_format_name_buf format_name;
10790                 intel_plane = to_intel_plane(plane);
10791                 if (intel_plane->pipe != crtc->pipe)
10792                         continue;
10793
10794                 state = to_intel_plane_state(plane->state);
10795                 fb = state->base.fb;
10796                 if (!fb) {
10797                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10798                                       plane->base.id, plane->name, state->scaler_id);
10799                         continue;
10800                 }
10801
10802                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10803                               plane->base.id, plane->name,
10804                               fb->base.id, fb->width, fb->height,
10805                               drm_get_format_name(fb->format->format, &format_name));
10806                 if (INTEL_GEN(dev_priv) >= 9)
10807                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10808                                       state->scaler_id,
10809                                       state->base.src.x1 >> 16,
10810                                       state->base.src.y1 >> 16,
10811                                       drm_rect_width(&state->base.src) >> 16,
10812                                       drm_rect_height(&state->base.src) >> 16,
10813                                       state->base.dst.x1, state->base.dst.y1,
10814                                       drm_rect_width(&state->base.dst),
10815                                       drm_rect_height(&state->base.dst));
10816         }
10817 }
10818
10819 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10820 {
10821         struct drm_device *dev = state->dev;
10822         struct drm_connector *connector;
10823         struct drm_connector_list_iter conn_iter;
10824         unsigned int used_ports = 0;
10825         unsigned int used_mst_ports = 0;
10826         bool ret = true;
10827
10828         /*
10829          * Walk the connector list instead of the encoder
10830          * list to detect the problem on ddi platforms
10831          * where there's just one encoder per digital port.
10832          */
10833         drm_connector_list_iter_begin(dev, &conn_iter);
10834         drm_for_each_connector_iter(connector, &conn_iter) {
10835                 struct drm_connector_state *connector_state;
10836                 struct intel_encoder *encoder;
10837
10838                 connector_state = drm_atomic_get_new_connector_state(state, connector);
10839                 if (!connector_state)
10840                         connector_state = connector->state;
10841
10842                 if (!connector_state->best_encoder)
10843                         continue;
10844
10845                 encoder = to_intel_encoder(connector_state->best_encoder);
10846
10847                 WARN_ON(!connector_state->crtc);
10848
10849                 switch (encoder->type) {
10850                         unsigned int port_mask;
10851                 case INTEL_OUTPUT_DDI:
10852                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10853                                 break;
10854                 case INTEL_OUTPUT_DP:
10855                 case INTEL_OUTPUT_HDMI:
10856                 case INTEL_OUTPUT_EDP:
10857                         port_mask = 1 << encoder->port;
10858
10859                         /* the same port mustn't appear more than once */
10860                         if (used_ports & port_mask)
10861                                 ret = false;
10862
10863                         used_ports |= port_mask;
10864                         break;
10865                 case INTEL_OUTPUT_DP_MST:
10866                         used_mst_ports |=
10867                                 1 << encoder->port;
10868                         break;
10869                 default:
10870                         break;
10871                 }
10872         }
10873         drm_connector_list_iter_end(&conn_iter);
10874
10875         /* can't mix MST and SST/HDMI on the same port */
10876         if (used_ports & used_mst_ports)
10877                 return false;
10878
10879         return ret;
10880 }
10881
10882 static void
10883 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10884 {
10885         struct drm_i915_private *dev_priv =
10886                 to_i915(crtc_state->base.crtc->dev);
10887         struct intel_crtc_scaler_state scaler_state;
10888         struct intel_dpll_hw_state dpll_hw_state;
10889         struct intel_shared_dpll *shared_dpll;
10890         struct intel_crtc_wm_state wm_state;
10891         bool force_thru, ips_force_disable;
10892
10893         /* FIXME: before the switch to atomic started, a new pipe_config was
10894          * kzalloc'd. Code that depends on any field being zero should be
10895          * fixed, so that the crtc_state can be safely duplicated. For now,
10896          * only fields that are know to not cause problems are preserved. */
10897
10898         scaler_state = crtc_state->scaler_state;
10899         shared_dpll = crtc_state->shared_dpll;
10900         dpll_hw_state = crtc_state->dpll_hw_state;
10901         force_thru = crtc_state->pch_pfit.force_thru;
10902         ips_force_disable = crtc_state->ips_force_disable;
10903         if (IS_G4X(dev_priv) ||
10904             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10905                 wm_state = crtc_state->wm;
10906
10907         /* Keep base drm_crtc_state intact, only clear our extended struct */
10908         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10909         memset(&crtc_state->base + 1, 0,
10910                sizeof(*crtc_state) - sizeof(crtc_state->base));
10911
10912         crtc_state->scaler_state = scaler_state;
10913         crtc_state->shared_dpll = shared_dpll;
10914         crtc_state->dpll_hw_state = dpll_hw_state;
10915         crtc_state->pch_pfit.force_thru = force_thru;
10916         crtc_state->ips_force_disable = ips_force_disable;
10917         if (IS_G4X(dev_priv) ||
10918             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10919                 crtc_state->wm = wm_state;
10920 }
10921
10922 static int
10923 intel_modeset_pipe_config(struct drm_crtc *crtc,
10924                           struct intel_crtc_state *pipe_config)
10925 {
10926         struct drm_atomic_state *state = pipe_config->base.state;
10927         struct intel_encoder *encoder;
10928         struct drm_connector *connector;
10929         struct drm_connector_state *connector_state;
10930         int base_bpp, ret = -EINVAL;
10931         int i;
10932         bool retry = true;
10933
10934         clear_intel_crtc_state(pipe_config);
10935
10936         pipe_config->cpu_transcoder =
10937                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10938
10939         /*
10940          * Sanitize sync polarity flags based on requested ones. If neither
10941          * positive or negative polarity is requested, treat this as meaning
10942          * negative polarity.
10943          */
10944         if (!(pipe_config->base.adjusted_mode.flags &
10945               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10946                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10947
10948         if (!(pipe_config->base.adjusted_mode.flags &
10949               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10950                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10951
10952         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10953                                              pipe_config);
10954         if (base_bpp < 0)
10955                 goto fail;
10956
10957         /*
10958          * Determine the real pipe dimensions. Note that stereo modes can
10959          * increase the actual pipe size due to the frame doubling and
10960          * insertion of additional space for blanks between the frame. This
10961          * is stored in the crtc timings. We use the requested mode to do this
10962          * computation to clearly distinguish it from the adjusted mode, which
10963          * can be changed by the connectors in the below retry loop.
10964          */
10965         drm_mode_get_hv_timing(&pipe_config->base.mode,
10966                                &pipe_config->pipe_src_w,
10967                                &pipe_config->pipe_src_h);
10968
10969         for_each_new_connector_in_state(state, connector, connector_state, i) {
10970                 if (connector_state->crtc != crtc)
10971                         continue;
10972
10973                 encoder = to_intel_encoder(connector_state->best_encoder);
10974
10975                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10976                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10977                         goto fail;
10978                 }
10979
10980                 /*
10981                  * Determine output_types before calling the .compute_config()
10982                  * hooks so that the hooks can use this information safely.
10983                  */
10984                 if (encoder->compute_output_type)
10985                         pipe_config->output_types |=
10986                                 BIT(encoder->compute_output_type(encoder, pipe_config,
10987                                                                  connector_state));
10988                 else
10989                         pipe_config->output_types |= BIT(encoder->type);
10990         }
10991
10992 encoder_retry:
10993         /* Ensure the port clock defaults are reset when retrying. */
10994         pipe_config->port_clock = 0;
10995         pipe_config->pixel_multiplier = 1;
10996
10997         /* Fill in default crtc timings, allow encoders to overwrite them. */
10998         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10999                               CRTC_STEREO_DOUBLE);
11000
11001         /* Pass our mode to the connectors and the CRTC to give them a chance to
11002          * adjust it according to limitations or connector properties, and also
11003          * a chance to reject the mode entirely.
11004          */
11005         for_each_new_connector_in_state(state, connector, connector_state, i) {
11006                 if (connector_state->crtc != crtc)
11007                         continue;
11008
11009                 encoder = to_intel_encoder(connector_state->best_encoder);
11010
11011                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11012                         DRM_DEBUG_KMS("Encoder config failure\n");
11013                         goto fail;
11014                 }
11015         }
11016
11017         /* Set default port clock if not overwritten by the encoder. Needs to be
11018          * done afterwards in case the encoder adjusts the mode. */
11019         if (!pipe_config->port_clock)
11020                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11021                         * pipe_config->pixel_multiplier;
11022
11023         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11024         if (ret < 0) {
11025                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11026                 goto fail;
11027         }
11028
11029         if (ret == RETRY) {
11030                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11031                         ret = -EINVAL;
11032                         goto fail;
11033                 }
11034
11035                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11036                 retry = false;
11037                 goto encoder_retry;
11038         }
11039
11040         /* Dithering seems to not pass-through bits correctly when it should, so
11041          * only enable it on 6bpc panels and when its not a compliance
11042          * test requesting 6bpc video pattern.
11043          */
11044         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11045                 !pipe_config->dither_force_disable;
11046         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11047                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11048
11049 fail:
11050         return ret;
11051 }
11052
11053 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11054 {
11055         int diff;
11056
11057         if (clock1 == clock2)
11058                 return true;
11059
11060         if (!clock1 || !clock2)
11061                 return false;
11062
11063         diff = abs(clock1 - clock2);
11064
11065         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11066                 return true;
11067
11068         return false;
11069 }
11070
11071 static bool
11072 intel_compare_m_n(unsigned int m, unsigned int n,
11073                   unsigned int m2, unsigned int n2,
11074                   bool exact)
11075 {
11076         if (m == m2 && n == n2)
11077                 return true;
11078
11079         if (exact || !m || !n || !m2 || !n2)
11080                 return false;
11081
11082         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11083
11084         if (n > n2) {
11085                 while (n > n2) {
11086                         m2 <<= 1;
11087                         n2 <<= 1;
11088                 }
11089         } else if (n < n2) {
11090                 while (n < n2) {
11091                         m <<= 1;
11092                         n <<= 1;
11093                 }
11094         }
11095
11096         if (n != n2)
11097                 return false;
11098
11099         return intel_fuzzy_clock_check(m, m2);
11100 }
11101
11102 static bool
11103 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11104                        struct intel_link_m_n *m2_n2,
11105                        bool adjust)
11106 {
11107         if (m_n->tu == m2_n2->tu &&
11108             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11109                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11110             intel_compare_m_n(m_n->link_m, m_n->link_n,
11111                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11112                 if (adjust)
11113                         *m2_n2 = *m_n;
11114
11115                 return true;
11116         }
11117
11118         return false;
11119 }
11120
11121 static void __printf(3, 4)
11122 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11123 {
11124         struct va_format vaf;
11125         va_list args;
11126
11127         va_start(args, format);
11128         vaf.fmt = format;
11129         vaf.va = &args;
11130
11131         if (adjust)
11132                 drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
11133         else
11134                 drm_err("mismatch in %s %pV", name, &vaf);
11135
11136         va_end(args);
11137 }
11138
11139 static bool
11140 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11141                           struct intel_crtc_state *current_config,
11142                           struct intel_crtc_state *pipe_config,
11143                           bool adjust)
11144 {
11145         bool ret = true;
11146         bool fixup_inherited = adjust &&
11147                 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
11148                 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
11149
11150 #define PIPE_CONF_CHECK_X(name) do { \
11151         if (current_config->name != pipe_config->name) { \
11152                 pipe_config_err(adjust, __stringify(name), \
11153                           "(expected 0x%08x, found 0x%08x)\n", \
11154                           current_config->name, \
11155                           pipe_config->name); \
11156                 ret = false; \
11157         } \
11158 } while (0)
11159
11160 #define PIPE_CONF_CHECK_I(name) do { \
11161         if (current_config->name != pipe_config->name) { \
11162                 pipe_config_err(adjust, __stringify(name), \
11163                           "(expected %i, found %i)\n", \
11164                           current_config->name, \
11165                           pipe_config->name); \
11166                 ret = false; \
11167         } \
11168 } while (0)
11169
11170 #define PIPE_CONF_CHECK_BOOL(name) do { \
11171         if (current_config->name != pipe_config->name) { \
11172                 pipe_config_err(adjust, __stringify(name), \
11173                           "(expected %s, found %s)\n", \
11174                           yesno(current_config->name), \
11175                           yesno(pipe_config->name)); \
11176                 ret = false; \
11177         } \
11178 } while (0)
11179
11180 /*
11181  * Checks state where we only read out the enabling, but not the entire
11182  * state itself (like full infoframes or ELD for audio). These states
11183  * require a full modeset on bootup to fix up.
11184  */
11185 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
11186         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
11187                 PIPE_CONF_CHECK_BOOL(name); \
11188         } else { \
11189                 pipe_config_err(adjust, __stringify(name), \
11190                           "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
11191                           yesno(current_config->name), \
11192                           yesno(pipe_config->name)); \
11193                 ret = false; \
11194         } \
11195 } while (0)
11196
11197 #define PIPE_CONF_CHECK_P(name) do { \
11198         if (current_config->name != pipe_config->name) { \
11199                 pipe_config_err(adjust, __stringify(name), \
11200                           "(expected %p, found %p)\n", \
11201                           current_config->name, \
11202                           pipe_config->name); \
11203                 ret = false; \
11204         } \
11205 } while (0)
11206
11207 #define PIPE_CONF_CHECK_M_N(name) do { \
11208         if (!intel_compare_link_m_n(&current_config->name, \
11209                                     &pipe_config->name,\
11210                                     adjust)) { \
11211                 pipe_config_err(adjust, __stringify(name), \
11212                           "(expected tu %i gmch %i/%i link %i/%i, " \
11213                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11214                           current_config->name.tu, \
11215                           current_config->name.gmch_m, \
11216                           current_config->name.gmch_n, \
11217                           current_config->name.link_m, \
11218                           current_config->name.link_n, \
11219                           pipe_config->name.tu, \
11220                           pipe_config->name.gmch_m, \
11221                           pipe_config->name.gmch_n, \
11222                           pipe_config->name.link_m, \
11223                           pipe_config->name.link_n); \
11224                 ret = false; \
11225         } \
11226 } while (0)
11227
11228 /* This is required for BDW+ where there is only one set of registers for
11229  * switching between high and low RR.
11230  * This macro can be used whenever a comparison has to be made between one
11231  * hw state and multiple sw state variables.
11232  */
11233 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
11234         if (!intel_compare_link_m_n(&current_config->name, \
11235                                     &pipe_config->name, adjust) && \
11236             !intel_compare_link_m_n(&current_config->alt_name, \
11237                                     &pipe_config->name, adjust)) { \
11238                 pipe_config_err(adjust, __stringify(name), \
11239                           "(expected tu %i gmch %i/%i link %i/%i, " \
11240                           "or tu %i gmch %i/%i link %i/%i, " \
11241                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11242                           current_config->name.tu, \
11243                           current_config->name.gmch_m, \
11244                           current_config->name.gmch_n, \
11245                           current_config->name.link_m, \
11246                           current_config->name.link_n, \
11247                           current_config->alt_name.tu, \
11248                           current_config->alt_name.gmch_m, \
11249                           current_config->alt_name.gmch_n, \
11250                           current_config->alt_name.link_m, \
11251                           current_config->alt_name.link_n, \
11252                           pipe_config->name.tu, \
11253                           pipe_config->name.gmch_m, \
11254                           pipe_config->name.gmch_n, \
11255                           pipe_config->name.link_m, \
11256                           pipe_config->name.link_n); \
11257                 ret = false; \
11258         } \
11259 } while (0)
11260
11261 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
11262         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11263                 pipe_config_err(adjust, __stringify(name), \
11264                           "(%x) (expected %i, found %i)\n", \
11265                           (mask), \
11266                           current_config->name & (mask), \
11267                           pipe_config->name & (mask)); \
11268                 ret = false; \
11269         } \
11270 } while (0)
11271
11272 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
11273         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11274                 pipe_config_err(adjust, __stringify(name), \
11275                           "(expected %i, found %i)\n", \
11276                           current_config->name, \
11277                           pipe_config->name); \
11278                 ret = false; \
11279         } \
11280 } while (0)
11281
11282 #define PIPE_CONF_QUIRK(quirk)  \
11283         ((current_config->quirks | pipe_config->quirks) & (quirk))
11284
11285         PIPE_CONF_CHECK_I(cpu_transcoder);
11286
11287         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
11288         PIPE_CONF_CHECK_I(fdi_lanes);
11289         PIPE_CONF_CHECK_M_N(fdi_m_n);
11290
11291         PIPE_CONF_CHECK_I(lane_count);
11292         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11293
11294         if (INTEL_GEN(dev_priv) < 8) {
11295                 PIPE_CONF_CHECK_M_N(dp_m_n);
11296
11297                 if (current_config->has_drrs)
11298                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11299         } else
11300                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11301
11302         PIPE_CONF_CHECK_X(output_types);
11303
11304         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11305         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11306         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11307         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11308         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11309         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11310
11311         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11312         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11313         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11314         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11315         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11316         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11317
11318         PIPE_CONF_CHECK_I(pixel_multiplier);
11319         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
11320         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11321             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11322                 PIPE_CONF_CHECK_BOOL(limited_color_range);
11323
11324         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
11325         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
11326         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_infoframe);
11327         PIPE_CONF_CHECK_BOOL(ycbcr420);
11328
11329         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
11330
11331         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11332                               DRM_MODE_FLAG_INTERLACE);
11333
11334         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11335                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11336                                       DRM_MODE_FLAG_PHSYNC);
11337                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11338                                       DRM_MODE_FLAG_NHSYNC);
11339                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11340                                       DRM_MODE_FLAG_PVSYNC);
11341                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11342                                       DRM_MODE_FLAG_NVSYNC);
11343         }
11344
11345         PIPE_CONF_CHECK_X(gmch_pfit.control);
11346         /* pfit ratios are autocomputed by the hw on gen4+ */
11347         if (INTEL_GEN(dev_priv) < 4)
11348                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11349         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11350
11351         if (!adjust) {
11352                 PIPE_CONF_CHECK_I(pipe_src_w);
11353                 PIPE_CONF_CHECK_I(pipe_src_h);
11354
11355                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
11356                 if (current_config->pch_pfit.enabled) {
11357                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11358                         PIPE_CONF_CHECK_X(pch_pfit.size);
11359                 }
11360
11361                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11362                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11363         }
11364
11365         PIPE_CONF_CHECK_BOOL(double_wide);
11366
11367         PIPE_CONF_CHECK_P(shared_dpll);
11368         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11369         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11370         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11371         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11372         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11373         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11374         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11375         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11376         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11377         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
11378         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
11379         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
11380         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
11381         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
11382         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
11383         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
11384         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
11385         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
11386         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
11387         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
11388         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
11389
11390         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11391         PIPE_CONF_CHECK_X(dsi_pll.div);
11392
11393         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11394                 PIPE_CONF_CHECK_I(pipe_bpp);
11395
11396         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11397         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11398
11399         PIPE_CONF_CHECK_I(min_voltage_level);
11400
11401 #undef PIPE_CONF_CHECK_X
11402 #undef PIPE_CONF_CHECK_I
11403 #undef PIPE_CONF_CHECK_BOOL
11404 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
11405 #undef PIPE_CONF_CHECK_P
11406 #undef PIPE_CONF_CHECK_FLAGS
11407 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11408 #undef PIPE_CONF_QUIRK
11409
11410         return ret;
11411 }
11412
11413 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11414                                            const struct intel_crtc_state *pipe_config)
11415 {
11416         if (pipe_config->has_pch_encoder) {
11417                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11418                                                             &pipe_config->fdi_m_n);
11419                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11420
11421                 /*
11422                  * FDI already provided one idea for the dotclock.
11423                  * Yell if the encoder disagrees.
11424                  */
11425                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11426                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11427                      fdi_dotclock, dotclock);
11428         }
11429 }
11430
11431 static void verify_wm_state(struct drm_crtc *crtc,
11432                             struct drm_crtc_state *new_state)
11433 {
11434         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11435         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11436         struct skl_pipe_wm hw_wm, *sw_wm;
11437         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11438         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11440         const enum pipe pipe = intel_crtc->pipe;
11441         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11442
11443         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11444                 return;
11445
11446         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11447         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11448
11449         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11450         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11451
11452         if (INTEL_GEN(dev_priv) >= 11)
11453                 if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
11454                         DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
11455                                   sw_ddb->enabled_slices,
11456                                   hw_ddb.enabled_slices);
11457         /* planes */
11458         for_each_universal_plane(dev_priv, pipe, plane) {
11459                 hw_plane_wm = &hw_wm.planes[plane];
11460                 sw_plane_wm = &sw_wm->planes[plane];
11461
11462                 /* Watermarks */
11463                 for (level = 0; level <= max_level; level++) {
11464                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11465                                                 &sw_plane_wm->wm[level]))
11466                                 continue;
11467
11468                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11469                                   pipe_name(pipe), plane + 1, level,
11470                                   sw_plane_wm->wm[level].plane_en,
11471                                   sw_plane_wm->wm[level].plane_res_b,
11472                                   sw_plane_wm->wm[level].plane_res_l,
11473                                   hw_plane_wm->wm[level].plane_en,
11474                                   hw_plane_wm->wm[level].plane_res_b,
11475                                   hw_plane_wm->wm[level].plane_res_l);
11476                 }
11477
11478                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11479                                          &sw_plane_wm->trans_wm)) {
11480                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11481                                   pipe_name(pipe), plane + 1,
11482                                   sw_plane_wm->trans_wm.plane_en,
11483                                   sw_plane_wm->trans_wm.plane_res_b,
11484                                   sw_plane_wm->trans_wm.plane_res_l,
11485                                   hw_plane_wm->trans_wm.plane_en,
11486                                   hw_plane_wm->trans_wm.plane_res_b,
11487                                   hw_plane_wm->trans_wm.plane_res_l);
11488                 }
11489
11490                 /* DDB */
11491                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11492                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11493
11494                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11495                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11496                                   pipe_name(pipe), plane + 1,
11497                                   sw_ddb_entry->start, sw_ddb_entry->end,
11498                                   hw_ddb_entry->start, hw_ddb_entry->end);
11499                 }
11500         }
11501
11502         /*
11503          * cursor
11504          * If the cursor plane isn't active, we may not have updated it's ddb
11505          * allocation. In that case since the ddb allocation will be updated
11506          * once the plane becomes visible, we can skip this check
11507          */
11508         if (1) {
11509                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11510                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11511
11512                 /* Watermarks */
11513                 for (level = 0; level <= max_level; level++) {
11514                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11515                                                 &sw_plane_wm->wm[level]))
11516                                 continue;
11517
11518                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11519                                   pipe_name(pipe), level,
11520                                   sw_plane_wm->wm[level].plane_en,
11521                                   sw_plane_wm->wm[level].plane_res_b,
11522                                   sw_plane_wm->wm[level].plane_res_l,
11523                                   hw_plane_wm->wm[level].plane_en,
11524                                   hw_plane_wm->wm[level].plane_res_b,
11525                                   hw_plane_wm->wm[level].plane_res_l);
11526                 }
11527
11528                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11529                                          &sw_plane_wm->trans_wm)) {
11530                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11531                                   pipe_name(pipe),
11532                                   sw_plane_wm->trans_wm.plane_en,
11533                                   sw_plane_wm->trans_wm.plane_res_b,
11534                                   sw_plane_wm->trans_wm.plane_res_l,
11535                                   hw_plane_wm->trans_wm.plane_en,
11536                                   hw_plane_wm->trans_wm.plane_res_b,
11537                                   hw_plane_wm->trans_wm.plane_res_l);
11538                 }
11539
11540                 /* DDB */
11541                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11542                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11543
11544                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11545                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11546                                   pipe_name(pipe),
11547                                   sw_ddb_entry->start, sw_ddb_entry->end,
11548                                   hw_ddb_entry->start, hw_ddb_entry->end);
11549                 }
11550         }
11551 }
11552
11553 static void
11554 verify_connector_state(struct drm_device *dev,
11555                        struct drm_atomic_state *state,
11556                        struct drm_crtc *crtc)
11557 {
11558         struct drm_connector *connector;
11559         struct drm_connector_state *new_conn_state;
11560         int i;
11561
11562         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11563                 struct drm_encoder *encoder = connector->encoder;
11564                 struct drm_crtc_state *crtc_state = NULL;
11565
11566                 if (new_conn_state->crtc != crtc)
11567                         continue;
11568
11569                 if (crtc)
11570                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11571
11572                 intel_connector_verify_state(crtc_state, new_conn_state);
11573
11574                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11575                      "connector's atomic encoder doesn't match legacy encoder\n");
11576         }
11577 }
11578
11579 static void
11580 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11581 {
11582         struct intel_encoder *encoder;
11583         struct drm_connector *connector;
11584         struct drm_connector_state *old_conn_state, *new_conn_state;
11585         int i;
11586
11587         for_each_intel_encoder(dev, encoder) {
11588                 bool enabled = false, found = false;
11589                 enum pipe pipe;
11590
11591                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11592                               encoder->base.base.id,
11593                               encoder->base.name);
11594
11595                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11596                                                    new_conn_state, i) {
11597                         if (old_conn_state->best_encoder == &encoder->base)
11598                                 found = true;
11599
11600                         if (new_conn_state->best_encoder != &encoder->base)
11601                                 continue;
11602                         found = enabled = true;
11603
11604                         I915_STATE_WARN(new_conn_state->crtc !=
11605                                         encoder->base.crtc,
11606                              "connector's crtc doesn't match encoder crtc\n");
11607                 }
11608
11609                 if (!found)
11610                         continue;
11611
11612                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11613                      "encoder's enabled state mismatch "
11614                      "(expected %i, found %i)\n",
11615                      !!encoder->base.crtc, enabled);
11616
11617                 if (!encoder->base.crtc) {
11618                         bool active;
11619
11620                         active = encoder->get_hw_state(encoder, &pipe);
11621                         I915_STATE_WARN(active,
11622                              "encoder detached but still enabled on pipe %c.\n",
11623                              pipe_name(pipe));
11624                 }
11625         }
11626 }
11627
11628 static void
11629 verify_crtc_state(struct drm_crtc *crtc,
11630                   struct drm_crtc_state *old_crtc_state,
11631                   struct drm_crtc_state *new_crtc_state)
11632 {
11633         struct drm_device *dev = crtc->dev;
11634         struct drm_i915_private *dev_priv = to_i915(dev);
11635         struct intel_encoder *encoder;
11636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11637         struct intel_crtc_state *pipe_config, *sw_config;
11638         struct drm_atomic_state *old_state;
11639         bool active;
11640
11641         old_state = old_crtc_state->state;
11642         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11643         pipe_config = to_intel_crtc_state(old_crtc_state);
11644         memset(pipe_config, 0, sizeof(*pipe_config));
11645         pipe_config->base.crtc = crtc;
11646         pipe_config->base.state = old_state;
11647
11648         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11649
11650         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11651
11652         /* we keep both pipes enabled on 830 */
11653         if (IS_I830(dev_priv))
11654                 active = new_crtc_state->active;
11655
11656         I915_STATE_WARN(new_crtc_state->active != active,
11657              "crtc active state doesn't match with hw state "
11658              "(expected %i, found %i)\n", new_crtc_state->active, active);
11659
11660         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11661              "transitional active state does not match atomic hw state "
11662              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11663
11664         for_each_encoder_on_crtc(dev, crtc, encoder) {
11665                 enum pipe pipe;
11666
11667                 active = encoder->get_hw_state(encoder, &pipe);
11668                 I915_STATE_WARN(active != new_crtc_state->active,
11669                         "[ENCODER:%i] active %i with crtc active %i\n",
11670                         encoder->base.base.id, active, new_crtc_state->active);
11671
11672                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11673                                 "Encoder connected to wrong pipe %c\n",
11674                                 pipe_name(pipe));
11675
11676                 if (active)
11677                         encoder->get_config(encoder, pipe_config);
11678         }
11679
11680         intel_crtc_compute_pixel_rate(pipe_config);
11681
11682         if (!new_crtc_state->active)
11683                 return;
11684
11685         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11686
11687         sw_config = to_intel_crtc_state(new_crtc_state);
11688         if (!intel_pipe_config_compare(dev_priv, sw_config,
11689                                        pipe_config, false)) {
11690                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11691                 intel_dump_pipe_config(intel_crtc, pipe_config,
11692                                        "[hw state]");
11693                 intel_dump_pipe_config(intel_crtc, sw_config,
11694                                        "[sw state]");
11695         }
11696 }
11697
11698 static void
11699 intel_verify_planes(struct intel_atomic_state *state)
11700 {
11701         struct intel_plane *plane;
11702         const struct intel_plane_state *plane_state;
11703         int i;
11704
11705         for_each_new_intel_plane_in_state(state, plane,
11706                                           plane_state, i)
11707                 assert_plane(plane, plane_state->base.visible);
11708 }
11709
11710 static void
11711 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11712                          struct intel_shared_dpll *pll,
11713                          struct drm_crtc *crtc,
11714                          struct drm_crtc_state *new_state)
11715 {
11716         struct intel_dpll_hw_state dpll_hw_state;
11717         unsigned crtc_mask;
11718         bool active;
11719
11720         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11721
11722         DRM_DEBUG_KMS("%s\n", pll->info->name);
11723
11724         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
11725
11726         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
11727                 I915_STATE_WARN(!pll->on && pll->active_mask,
11728                      "pll in active use but not on in sw tracking\n");
11729                 I915_STATE_WARN(pll->on && !pll->active_mask,
11730                      "pll is on but not used by any active crtc\n");
11731                 I915_STATE_WARN(pll->on != active,
11732                      "pll on state mismatch (expected %i, found %i)\n",
11733                      pll->on, active);
11734         }
11735
11736         if (!crtc) {
11737                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11738                                 "more active pll users than references: %x vs %x\n",
11739                                 pll->active_mask, pll->state.crtc_mask);
11740
11741                 return;
11742         }
11743
11744         crtc_mask = 1 << drm_crtc_index(crtc);
11745
11746         if (new_state->active)
11747                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11748                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11749                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11750         else
11751                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11752                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11753                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11754
11755         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11756                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11757                         crtc_mask, pll->state.crtc_mask);
11758
11759         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11760                                           &dpll_hw_state,
11761                                           sizeof(dpll_hw_state)),
11762                         "pll hw state mismatch\n");
11763 }
11764
11765 static void
11766 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11767                          struct drm_crtc_state *old_crtc_state,
11768                          struct drm_crtc_state *new_crtc_state)
11769 {
11770         struct drm_i915_private *dev_priv = to_i915(dev);
11771         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11772         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11773
11774         if (new_state->shared_dpll)
11775                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11776
11777         if (old_state->shared_dpll &&
11778             old_state->shared_dpll != new_state->shared_dpll) {
11779                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11780                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11781
11782                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11783                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11784                                 pipe_name(drm_crtc_index(crtc)));
11785                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11786                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11787                                 pipe_name(drm_crtc_index(crtc)));
11788         }
11789 }
11790
11791 static void
11792 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11793                           struct drm_atomic_state *state,
11794                           struct drm_crtc_state *old_state,
11795                           struct drm_crtc_state *new_state)
11796 {
11797         if (!needs_modeset(new_state) &&
11798             !to_intel_crtc_state(new_state)->update_pipe)
11799                 return;
11800
11801         verify_wm_state(crtc, new_state);
11802         verify_connector_state(crtc->dev, state, crtc);
11803         verify_crtc_state(crtc, old_state, new_state);
11804         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11805 }
11806
11807 static void
11808 verify_disabled_dpll_state(struct drm_device *dev)
11809 {
11810         struct drm_i915_private *dev_priv = to_i915(dev);
11811         int i;
11812
11813         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11814                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11815 }
11816
11817 static void
11818 intel_modeset_verify_disabled(struct drm_device *dev,
11819                               struct drm_atomic_state *state)
11820 {
11821         verify_encoder_state(dev, state);
11822         verify_connector_state(dev, state, NULL);
11823         verify_disabled_dpll_state(dev);
11824 }
11825
11826 static void update_scanline_offset(struct intel_crtc *crtc)
11827 {
11828         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11829
11830         /*
11831          * The scanline counter increments at the leading edge of hsync.
11832          *
11833          * On most platforms it starts counting from vtotal-1 on the
11834          * first active line. That means the scanline counter value is
11835          * always one less than what we would expect. Ie. just after
11836          * start of vblank, which also occurs at start of hsync (on the
11837          * last active line), the scanline counter will read vblank_start-1.
11838          *
11839          * On gen2 the scanline counter starts counting from 1 instead
11840          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11841          * to keep the value positive), instead of adding one.
11842          *
11843          * On HSW+ the behaviour of the scanline counter depends on the output
11844          * type. For DP ports it behaves like most other platforms, but on HDMI
11845          * there's an extra 1 line difference. So we need to add two instead of
11846          * one to the value.
11847          *
11848          * On VLV/CHV DSI the scanline counter would appear to increment
11849          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11850          * that means we can't tell whether we're in vblank or not while
11851          * we're on that particular line. We must still set scanline_offset
11852          * to 1 so that the vblank timestamps come out correct when we query
11853          * the scanline counter from within the vblank interrupt handler.
11854          * However if queried just before the start of vblank we'll get an
11855          * answer that's slightly in the future.
11856          */
11857         if (IS_GEN2(dev_priv)) {
11858                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11859                 int vtotal;
11860
11861                 vtotal = adjusted_mode->crtc_vtotal;
11862                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11863                         vtotal /= 2;
11864
11865                 crtc->scanline_offset = vtotal - 1;
11866         } else if (HAS_DDI(dev_priv) &&
11867                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11868                 crtc->scanline_offset = 2;
11869         } else
11870                 crtc->scanline_offset = 1;
11871 }
11872
11873 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11874 {
11875         struct drm_device *dev = state->dev;
11876         struct drm_i915_private *dev_priv = to_i915(dev);
11877         struct drm_crtc *crtc;
11878         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11879         int i;
11880
11881         if (!dev_priv->display.crtc_compute_clock)
11882                 return;
11883
11884         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11885                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11886                 struct intel_shared_dpll *old_dpll =
11887                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11888
11889                 if (!needs_modeset(new_crtc_state))
11890                         continue;
11891
11892                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11893
11894                 if (!old_dpll)
11895                         continue;
11896
11897                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11898         }
11899 }
11900
11901 /*
11902  * This implements the workaround described in the "notes" section of the mode
11903  * set sequence documentation. When going from no pipes or single pipe to
11904  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11905  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11906  */
11907 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11908 {
11909         struct drm_crtc_state *crtc_state;
11910         struct intel_crtc *intel_crtc;
11911         struct drm_crtc *crtc;
11912         struct intel_crtc_state *first_crtc_state = NULL;
11913         struct intel_crtc_state *other_crtc_state = NULL;
11914         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11915         int i;
11916
11917         /* look at all crtc's that are going to be enabled in during modeset */
11918         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11919                 intel_crtc = to_intel_crtc(crtc);
11920
11921                 if (!crtc_state->active || !needs_modeset(crtc_state))
11922                         continue;
11923
11924                 if (first_crtc_state) {
11925                         other_crtc_state = to_intel_crtc_state(crtc_state);
11926                         break;
11927                 } else {
11928                         first_crtc_state = to_intel_crtc_state(crtc_state);
11929                         first_pipe = intel_crtc->pipe;
11930                 }
11931         }
11932
11933         /* No workaround needed? */
11934         if (!first_crtc_state)
11935                 return 0;
11936
11937         /* w/a possibly needed, check how many crtc's are already enabled. */
11938         for_each_intel_crtc(state->dev, intel_crtc) {
11939                 struct intel_crtc_state *pipe_config;
11940
11941                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11942                 if (IS_ERR(pipe_config))
11943                         return PTR_ERR(pipe_config);
11944
11945                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11946
11947                 if (!pipe_config->base.active ||
11948                     needs_modeset(&pipe_config->base))
11949                         continue;
11950
11951                 /* 2 or more enabled crtcs means no need for w/a */
11952                 if (enabled_pipe != INVALID_PIPE)
11953                         return 0;
11954
11955                 enabled_pipe = intel_crtc->pipe;
11956         }
11957
11958         if (enabled_pipe != INVALID_PIPE)
11959                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11960         else if (other_crtc_state)
11961                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11962
11963         return 0;
11964 }
11965
11966 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11967 {
11968         struct drm_crtc *crtc;
11969
11970         /* Add all pipes to the state */
11971         for_each_crtc(state->dev, crtc) {
11972                 struct drm_crtc_state *crtc_state;
11973
11974                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11975                 if (IS_ERR(crtc_state))
11976                         return PTR_ERR(crtc_state);
11977         }
11978
11979         return 0;
11980 }
11981
11982 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11983 {
11984         struct drm_crtc *crtc;
11985
11986         /*
11987          * Add all pipes to the state, and force
11988          * a modeset on all the active ones.
11989          */
11990         for_each_crtc(state->dev, crtc) {
11991                 struct drm_crtc_state *crtc_state;
11992                 int ret;
11993
11994                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11995                 if (IS_ERR(crtc_state))
11996                         return PTR_ERR(crtc_state);
11997
11998                 if (!crtc_state->active || needs_modeset(crtc_state))
11999                         continue;
12000
12001                 crtc_state->mode_changed = true;
12002
12003                 ret = drm_atomic_add_affected_connectors(state, crtc);
12004                 if (ret)
12005                         return ret;
12006
12007                 ret = drm_atomic_add_affected_planes(state, crtc);
12008                 if (ret)
12009                         return ret;
12010         }
12011
12012         return 0;
12013 }
12014
12015 static int intel_modeset_checks(struct drm_atomic_state *state)
12016 {
12017         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12018         struct drm_i915_private *dev_priv = to_i915(state->dev);
12019         struct drm_crtc *crtc;
12020         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12021         int ret = 0, i;
12022
12023         if (!check_digital_port_conflicts(state)) {
12024                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12025                 return -EINVAL;
12026         }
12027
12028         intel_state->modeset = true;
12029         intel_state->active_crtcs = dev_priv->active_crtcs;
12030         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12031         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12032
12033         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12034                 if (new_crtc_state->active)
12035                         intel_state->active_crtcs |= 1 << i;
12036                 else
12037                         intel_state->active_crtcs &= ~(1 << i);
12038
12039                 if (old_crtc_state->active != new_crtc_state->active)
12040                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12041         }
12042
12043         /*
12044          * See if the config requires any additional preparation, e.g.
12045          * to adjust global state with pipes off.  We need to do this
12046          * here so we can get the modeset_pipe updated config for the new
12047          * mode set on this crtc.  For other crtcs we need to use the
12048          * adjusted_mode bits in the crtc directly.
12049          */
12050         if (dev_priv->display.modeset_calc_cdclk) {
12051                 ret = dev_priv->display.modeset_calc_cdclk(state);
12052                 if (ret < 0)
12053                         return ret;
12054
12055                 /*
12056                  * Writes to dev_priv->cdclk.logical must protected by
12057                  * holding all the crtc locks, even if we don't end up
12058                  * touching the hardware
12059                  */
12060                 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
12061                                         &intel_state->cdclk.logical)) {
12062                         ret = intel_lock_all_pipes(state);
12063                         if (ret < 0)
12064                                 return ret;
12065                 }
12066
12067                 /* All pipes must be switched off while we change the cdclk. */
12068                 if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
12069                                               &intel_state->cdclk.actual)) {
12070                         ret = intel_modeset_all_pipes(state);
12071                         if (ret < 0)
12072                                 return ret;
12073                 }
12074
12075                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12076                               intel_state->cdclk.logical.cdclk,
12077                               intel_state->cdclk.actual.cdclk);
12078                 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
12079                               intel_state->cdclk.logical.voltage_level,
12080                               intel_state->cdclk.actual.voltage_level);
12081         } else {
12082                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12083         }
12084
12085         intel_modeset_clear_plls(state);
12086
12087         if (IS_HASWELL(dev_priv))
12088                 return haswell_mode_set_planes_workaround(state);
12089
12090         return 0;
12091 }
12092
12093 /*
12094  * Handle calculation of various watermark data at the end of the atomic check
12095  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12096  * handlers to ensure that all derived state has been updated.
12097  */
12098 static int calc_watermark_data(struct drm_atomic_state *state)
12099 {
12100         struct drm_device *dev = state->dev;
12101         struct drm_i915_private *dev_priv = to_i915(dev);
12102
12103         /* Is there platform-specific watermark information to calculate? */
12104         if (dev_priv->display.compute_global_watermarks)
12105                 return dev_priv->display.compute_global_watermarks(state);
12106
12107         return 0;
12108 }
12109
12110 /**
12111  * intel_atomic_check - validate state object
12112  * @dev: drm device
12113  * @state: state to validate
12114  */
12115 static int intel_atomic_check(struct drm_device *dev,
12116                               struct drm_atomic_state *state)
12117 {
12118         struct drm_i915_private *dev_priv = to_i915(dev);
12119         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12120         struct drm_crtc *crtc;
12121         struct drm_crtc_state *old_crtc_state, *crtc_state;
12122         int ret, i;
12123         bool any_ms = false;
12124
12125         /* Catch I915_MODE_FLAG_INHERITED */
12126         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
12127                                       crtc_state, i) {
12128                 if (crtc_state->mode.private_flags !=
12129                     old_crtc_state->mode.private_flags)
12130                         crtc_state->mode_changed = true;
12131         }
12132
12133         ret = drm_atomic_helper_check_modeset(dev, state);
12134         if (ret)
12135                 return ret;
12136
12137         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12138                 struct intel_crtc_state *pipe_config =
12139                         to_intel_crtc_state(crtc_state);
12140
12141                 if (!needs_modeset(crtc_state))
12142                         continue;
12143
12144                 if (!crtc_state->enable) {
12145                         any_ms = true;
12146                         continue;
12147                 }
12148
12149                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12150                 if (ret) {
12151                         intel_dump_pipe_config(to_intel_crtc(crtc),
12152                                                pipe_config, "[failed]");
12153                         return ret;
12154                 }
12155
12156                 if (i915_modparams.fastboot &&
12157                     intel_pipe_config_compare(dev_priv,
12158                                         to_intel_crtc_state(old_crtc_state),
12159                                         pipe_config, true)) {
12160                         crtc_state->mode_changed = false;
12161                         pipe_config->update_pipe = true;
12162                 }
12163
12164                 if (needs_modeset(crtc_state))
12165                         any_ms = true;
12166
12167                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12168                                        needs_modeset(crtc_state) ?
12169                                        "[modeset]" : "[fastset]");
12170         }
12171
12172         if (any_ms) {
12173                 ret = intel_modeset_checks(state);
12174
12175                 if (ret)
12176                         return ret;
12177         } else {
12178                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12179         }
12180
12181         ret = drm_atomic_helper_check_planes(dev, state);
12182         if (ret)
12183                 return ret;
12184
12185         intel_fbc_choose_crtc(dev_priv, intel_state);
12186         return calc_watermark_data(state);
12187 }
12188
12189 static int intel_atomic_prepare_commit(struct drm_device *dev,
12190                                        struct drm_atomic_state *state)
12191 {
12192         return drm_atomic_helper_prepare_planes(dev, state);
12193 }
12194
12195 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12196 {
12197         struct drm_device *dev = crtc->base.dev;
12198
12199         if (!dev->max_vblank_count)
12200                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
12201
12202         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12203 }
12204
12205 static void intel_update_crtc(struct drm_crtc *crtc,
12206                               struct drm_atomic_state *state,
12207                               struct drm_crtc_state *old_crtc_state,
12208                               struct drm_crtc_state *new_crtc_state)
12209 {
12210         struct drm_device *dev = crtc->dev;
12211         struct drm_i915_private *dev_priv = to_i915(dev);
12212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12213         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12214         bool modeset = needs_modeset(new_crtc_state);
12215         struct intel_plane_state *new_plane_state =
12216                 intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
12217                                                  to_intel_plane(crtc->primary));
12218
12219         if (modeset) {
12220                 update_scanline_offset(intel_crtc);
12221                 dev_priv->display.crtc_enable(pipe_config, state);
12222
12223                 /* vblanks work again, re-enable pipe CRC. */
12224                 intel_crtc_enable_pipe_crc(intel_crtc);
12225         } else {
12226                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12227                                        pipe_config);
12228         }
12229
12230         if (new_plane_state)
12231                 intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
12232
12233         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12234 }
12235
12236 static void intel_update_crtcs(struct drm_atomic_state *state)
12237 {
12238         struct drm_crtc *crtc;
12239         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12240         int i;
12241
12242         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12243                 if (!new_crtc_state->active)
12244                         continue;
12245
12246                 intel_update_crtc(crtc, state, old_crtc_state,
12247                                   new_crtc_state);
12248         }
12249 }
12250
12251 static void skl_update_crtcs(struct drm_atomic_state *state)
12252 {
12253         struct drm_i915_private *dev_priv = to_i915(state->dev);
12254         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12255         struct drm_crtc *crtc;
12256         struct intel_crtc *intel_crtc;
12257         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12258         struct intel_crtc_state *cstate;
12259         unsigned int updated = 0;
12260         bool progress;
12261         enum pipe pipe;
12262         int i;
12263         u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
12264         u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
12265
12266         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12267
12268         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12269                 /* ignore allocations for crtc's that have been turned off. */
12270                 if (new_crtc_state->active)
12271                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12272
12273         /* If 2nd DBuf slice required, enable it here */
12274         if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
12275                 icl_dbuf_slices_update(dev_priv, required_slices);
12276
12277         /*
12278          * Whenever the number of active pipes changes, we need to make sure we
12279          * update the pipes in the right order so that their ddb allocations
12280          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12281          * cause pipe underruns and other bad stuff.
12282          */
12283         do {
12284                 progress = false;
12285
12286                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12287                         bool vbl_wait = false;
12288                         unsigned int cmask = drm_crtc_mask(crtc);
12289
12290                         intel_crtc = to_intel_crtc(crtc);
12291                         cstate = to_intel_crtc_state(new_crtc_state);
12292                         pipe = intel_crtc->pipe;
12293
12294                         if (updated & cmask || !cstate->base.active)
12295                                 continue;
12296
12297                         if (skl_ddb_allocation_overlaps(dev_priv,
12298                                                         entries,
12299                                                         &cstate->wm.skl.ddb,
12300                                                         i))
12301                                 continue;
12302
12303                         updated |= cmask;
12304                         entries[i] = &cstate->wm.skl.ddb;
12305
12306                         /*
12307                          * If this is an already active pipe, it's DDB changed,
12308                          * and this isn't the last pipe that needs updating
12309                          * then we need to wait for a vblank to pass for the
12310                          * new ddb allocation to take effect.
12311                          */
12312                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12313                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12314                             !new_crtc_state->active_changed &&
12315                             intel_state->wm_results.dirty_pipes != updated)
12316                                 vbl_wait = true;
12317
12318                         intel_update_crtc(crtc, state, old_crtc_state,
12319                                           new_crtc_state);
12320
12321                         if (vbl_wait)
12322                                 intel_wait_for_vblank(dev_priv, pipe);
12323
12324                         progress = true;
12325                 }
12326         } while (progress);
12327
12328         /* If 2nd DBuf slice is no more required disable it */
12329         if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
12330                 icl_dbuf_slices_update(dev_priv, required_slices);
12331 }
12332
12333 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12334 {
12335         struct intel_atomic_state *state, *next;
12336         struct llist_node *freed;
12337
12338         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12339         llist_for_each_entry_safe(state, next, freed, freed)
12340                 drm_atomic_state_put(&state->base);
12341 }
12342
12343 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12344 {
12345         struct drm_i915_private *dev_priv =
12346                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12347
12348         intel_atomic_helper_free_state(dev_priv);
12349 }
12350
12351 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12352 {
12353         struct wait_queue_entry wait_fence, wait_reset;
12354         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12355
12356         init_wait_entry(&wait_fence, 0);
12357         init_wait_entry(&wait_reset, 0);
12358         for (;;) {
12359                 prepare_to_wait(&intel_state->commit_ready.wait,
12360                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12361                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12362                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12363
12364
12365                 if (i915_sw_fence_done(&intel_state->commit_ready)
12366                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12367                         break;
12368
12369                 schedule();
12370         }
12371         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12372         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12373 }
12374
12375 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12376 {
12377         struct drm_device *dev = state->dev;
12378         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12379         struct drm_i915_private *dev_priv = to_i915(dev);
12380         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12381         struct drm_crtc *crtc;
12382         struct intel_crtc_state *intel_cstate;
12383         u64 put_domains[I915_MAX_PIPES] = {};
12384         int i;
12385
12386         intel_atomic_commit_fence_wait(intel_state);
12387
12388         drm_atomic_helper_wait_for_dependencies(state);
12389
12390         if (intel_state->modeset)
12391                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12392
12393         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12394                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12395
12396                 if (needs_modeset(new_crtc_state) ||
12397                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12398
12399                         put_domains[to_intel_crtc(crtc)->pipe] =
12400                                 modeset_get_crtc_power_domains(crtc,
12401                                         to_intel_crtc_state(new_crtc_state));
12402                 }
12403
12404                 if (!needs_modeset(new_crtc_state))
12405                         continue;
12406
12407                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12408                                        to_intel_crtc_state(new_crtc_state));
12409
12410                 if (old_crtc_state->active) {
12411                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12412
12413                         /*
12414                          * We need to disable pipe CRC before disabling the pipe,
12415                          * or we race against vblank off.
12416                          */
12417                         intel_crtc_disable_pipe_crc(intel_crtc);
12418
12419                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12420                         intel_crtc->active = false;
12421                         intel_fbc_disable(intel_crtc);
12422                         intel_disable_shared_dpll(intel_crtc);
12423
12424                         /*
12425                          * Underruns don't always raise
12426                          * interrupts, so check manually.
12427                          */
12428                         intel_check_cpu_fifo_underruns(dev_priv);
12429                         intel_check_pch_fifo_underruns(dev_priv);
12430
12431                         if (!new_crtc_state->active) {
12432                                 /*
12433                                  * Make sure we don't call initial_watermarks
12434                                  * for ILK-style watermark updates.
12435                                  *
12436                                  * No clue what this is supposed to achieve.
12437                                  */
12438                                 if (INTEL_GEN(dev_priv) >= 9)
12439                                         dev_priv->display.initial_watermarks(intel_state,
12440                                                                              to_intel_crtc_state(new_crtc_state));
12441                         }
12442                 }
12443         }
12444
12445         /* FIXME: Eventually get rid of our intel_crtc->config pointer */
12446         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
12447                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
12448
12449         if (intel_state->modeset) {
12450                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12451
12452                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12453
12454                 /*
12455                  * SKL workaround: bspec recommends we disable the SAGV when we
12456                  * have more then one pipe enabled
12457                  */
12458                 if (!intel_can_enable_sagv(state))
12459                         intel_disable_sagv(dev_priv);
12460
12461                 intel_modeset_verify_disabled(dev, state);
12462         }
12463
12464         /* Complete the events for pipes that have now been disabled */
12465         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12466                 bool modeset = needs_modeset(new_crtc_state);
12467
12468                 /* Complete events for now disable pipes here. */
12469                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12470                         spin_lock_irq(&dev->event_lock);
12471                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12472                         spin_unlock_irq(&dev->event_lock);
12473
12474                         new_crtc_state->event = NULL;
12475                 }
12476         }
12477
12478         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12479         dev_priv->display.update_crtcs(state);
12480
12481         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12482          * already, but still need the state for the delayed optimization. To
12483          * fix this:
12484          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12485          * - schedule that vblank worker _before_ calling hw_done
12486          * - at the start of commit_tail, cancel it _synchrously
12487          * - switch over to the vblank wait helper in the core after that since
12488          *   we don't need out special handling any more.
12489          */
12490         drm_atomic_helper_wait_for_flip_done(dev, state);
12491
12492         /*
12493          * Now that the vblank has passed, we can go ahead and program the
12494          * optimal watermarks on platforms that need two-step watermark
12495          * programming.
12496          *
12497          * TODO: Move this (and other cleanup) to an async worker eventually.
12498          */
12499         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12500                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12501
12502                 if (dev_priv->display.optimize_watermarks)
12503                         dev_priv->display.optimize_watermarks(intel_state,
12504                                                               intel_cstate);
12505         }
12506
12507         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12508                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12509
12510                 if (put_domains[i])
12511                         modeset_put_power_domains(dev_priv, put_domains[i]);
12512
12513                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12514         }
12515
12516         if (intel_state->modeset)
12517                 intel_verify_planes(intel_state);
12518
12519         if (intel_state->modeset && intel_can_enable_sagv(state))
12520                 intel_enable_sagv(dev_priv);
12521
12522         drm_atomic_helper_commit_hw_done(state);
12523
12524         if (intel_state->modeset) {
12525                 /* As one of the primary mmio accessors, KMS has a high
12526                  * likelihood of triggering bugs in unclaimed access. After we
12527                  * finish modesetting, see if an error has been flagged, and if
12528                  * so enable debugging for the next modeset - and hope we catch
12529                  * the culprit.
12530                  */
12531                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12532                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12533         }
12534
12535         drm_atomic_helper_cleanup_planes(dev, state);
12536
12537         drm_atomic_helper_commit_cleanup_done(state);
12538
12539         drm_atomic_state_put(state);
12540
12541         intel_atomic_helper_free_state(dev_priv);
12542 }
12543
12544 static void intel_atomic_commit_work(struct work_struct *work)
12545 {
12546         struct drm_atomic_state *state =
12547                 container_of(work, struct drm_atomic_state, commit_work);
12548
12549         intel_atomic_commit_tail(state);
12550 }
12551
12552 static int __i915_sw_fence_call
12553 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12554                           enum i915_sw_fence_notify notify)
12555 {
12556         struct intel_atomic_state *state =
12557                 container_of(fence, struct intel_atomic_state, commit_ready);
12558
12559         switch (notify) {
12560         case FENCE_COMPLETE:
12561                 /* we do blocking waits in the worker, nothing to do here */
12562                 break;
12563         case FENCE_FREE:
12564                 {
12565                         struct intel_atomic_helper *helper =
12566                                 &to_i915(state->base.dev)->atomic_helper;
12567
12568                         if (llist_add(&state->freed, &helper->free_list))
12569                                 schedule_work(&helper->free_work);
12570                         break;
12571                 }
12572         }
12573
12574         return NOTIFY_DONE;
12575 }
12576
12577 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12578 {
12579         struct drm_plane_state *old_plane_state, *new_plane_state;
12580         struct drm_plane *plane;
12581         int i;
12582
12583         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12584                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12585                                   intel_fb_obj(new_plane_state->fb),
12586                                   to_intel_plane(plane)->frontbuffer_bit);
12587 }
12588
12589 /**
12590  * intel_atomic_commit - commit validated state object
12591  * @dev: DRM device
12592  * @state: the top-level driver state object
12593  * @nonblock: nonblocking commit
12594  *
12595  * This function commits a top-level state object that has been validated
12596  * with drm_atomic_helper_check().
12597  *
12598  * RETURNS
12599  * Zero for success or -errno.
12600  */
12601 static int intel_atomic_commit(struct drm_device *dev,
12602                                struct drm_atomic_state *state,
12603                                bool nonblock)
12604 {
12605         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12606         struct drm_i915_private *dev_priv = to_i915(dev);
12607         int ret = 0;
12608
12609         drm_atomic_state_get(state);
12610         i915_sw_fence_init(&intel_state->commit_ready,
12611                            intel_atomic_commit_ready);
12612
12613         /*
12614          * The intel_legacy_cursor_update() fast path takes care
12615          * of avoiding the vblank waits for simple cursor
12616          * movement and flips. For cursor on/off and size changes,
12617          * we want to perform the vblank waits so that watermark
12618          * updates happen during the correct frames. Gen9+ have
12619          * double buffered watermarks and so shouldn't need this.
12620          *
12621          * Unset state->legacy_cursor_update before the call to
12622          * drm_atomic_helper_setup_commit() because otherwise
12623          * drm_atomic_helper_wait_for_flip_done() is a noop and
12624          * we get FIFO underruns because we didn't wait
12625          * for vblank.
12626          *
12627          * FIXME doing watermarks and fb cleanup from a vblank worker
12628          * (assuming we had any) would solve these problems.
12629          */
12630         if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
12631                 struct intel_crtc_state *new_crtc_state;
12632                 struct intel_crtc *crtc;
12633                 int i;
12634
12635                 for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
12636                         if (new_crtc_state->wm.need_postvbl_update ||
12637                             new_crtc_state->update_wm_post)
12638                                 state->legacy_cursor_update = false;
12639         }
12640
12641         ret = intel_atomic_prepare_commit(dev, state);
12642         if (ret) {
12643                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12644                 i915_sw_fence_commit(&intel_state->commit_ready);
12645                 return ret;
12646         }
12647
12648         ret = drm_atomic_helper_setup_commit(state, nonblock);
12649         if (!ret)
12650                 ret = drm_atomic_helper_swap_state(state, true);
12651
12652         if (ret) {
12653                 i915_sw_fence_commit(&intel_state->commit_ready);
12654
12655                 drm_atomic_helper_cleanup_planes(dev, state);
12656                 return ret;
12657         }
12658         dev_priv->wm.distrust_bios_wm = false;
12659         intel_shared_dpll_swap_state(state);
12660         intel_atomic_track_fbs(state);
12661
12662         if (intel_state->modeset) {
12663                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12664                        sizeof(intel_state->min_cdclk));
12665                 memcpy(dev_priv->min_voltage_level,
12666                        intel_state->min_voltage_level,
12667                        sizeof(intel_state->min_voltage_level));
12668                 dev_priv->active_crtcs = intel_state->active_crtcs;
12669                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12670                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12671         }
12672
12673         drm_atomic_state_get(state);
12674         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12675
12676         i915_sw_fence_commit(&intel_state->commit_ready);
12677         if (nonblock && intel_state->modeset) {
12678                 queue_work(dev_priv->modeset_wq, &state->commit_work);
12679         } else if (nonblock) {
12680                 queue_work(system_unbound_wq, &state->commit_work);
12681         } else {
12682                 if (intel_state->modeset)
12683                         flush_workqueue(dev_priv->modeset_wq);
12684                 intel_atomic_commit_tail(state);
12685         }
12686
12687         return 0;
12688 }
12689
12690 static const struct drm_crtc_funcs intel_crtc_funcs = {
12691         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12692         .set_config = drm_atomic_helper_set_config,
12693         .destroy = intel_crtc_destroy,
12694         .page_flip = drm_atomic_helper_page_flip,
12695         .atomic_duplicate_state = intel_crtc_duplicate_state,
12696         .atomic_destroy_state = intel_crtc_destroy_state,
12697         .set_crc_source = intel_crtc_set_crc_source,
12698 };
12699
12700 struct wait_rps_boost {
12701         struct wait_queue_entry wait;
12702
12703         struct drm_crtc *crtc;
12704         struct i915_request *request;
12705 };
12706
12707 static int do_rps_boost(struct wait_queue_entry *_wait,
12708                         unsigned mode, int sync, void *key)
12709 {
12710         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12711         struct i915_request *rq = wait->request;
12712
12713         /*
12714          * If we missed the vblank, but the request is already running it
12715          * is reasonable to assume that it will complete before the next
12716          * vblank without our intervention, so leave RPS alone.
12717          */
12718         if (!i915_request_started(rq))
12719                 gen6_rps_boost(rq, NULL);
12720         i915_request_put(rq);
12721
12722         drm_crtc_vblank_put(wait->crtc);
12723
12724         list_del(&wait->wait.entry);
12725         kfree(wait);
12726         return 1;
12727 }
12728
12729 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12730                                        struct dma_fence *fence)
12731 {
12732         struct wait_rps_boost *wait;
12733
12734         if (!dma_fence_is_i915(fence))
12735                 return;
12736
12737         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12738                 return;
12739
12740         if (drm_crtc_vblank_get(crtc))
12741                 return;
12742
12743         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12744         if (!wait) {
12745                 drm_crtc_vblank_put(crtc);
12746                 return;
12747         }
12748
12749         wait->request = to_request(dma_fence_get(fence));
12750         wait->crtc = crtc;
12751
12752         wait->wait.func = do_rps_boost;
12753         wait->wait.flags = 0;
12754
12755         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12756 }
12757
12758 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
12759 {
12760         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12761         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12762         struct drm_framebuffer *fb = plane_state->base.fb;
12763         struct i915_vma *vma;
12764
12765         if (plane->id == PLANE_CURSOR &&
12766             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12767                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12768                 const int align = intel_cursor_alignment(dev_priv);
12769
12770                 return i915_gem_object_attach_phys(obj, align);
12771         }
12772
12773         vma = intel_pin_and_fence_fb_obj(fb,
12774                                          plane_state->base.rotation,
12775                                          intel_plane_uses_fence(plane_state),
12776                                          &plane_state->flags);
12777         if (IS_ERR(vma))
12778                 return PTR_ERR(vma);
12779
12780         plane_state->vma = vma;
12781
12782         return 0;
12783 }
12784
12785 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
12786 {
12787         struct i915_vma *vma;
12788
12789         vma = fetch_and_zero(&old_plane_state->vma);
12790         if (vma)
12791                 intel_unpin_fb_vma(vma, old_plane_state->flags);
12792 }
12793
12794 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
12795 {
12796         struct i915_sched_attr attr = {
12797                 .priority = I915_PRIORITY_DISPLAY,
12798         };
12799
12800         i915_gem_object_wait_priority(obj, 0, &attr);
12801 }
12802
12803 /**
12804  * intel_prepare_plane_fb - Prepare fb for usage on plane
12805  * @plane: drm plane to prepare for
12806  * @new_state: the plane state being prepared
12807  *
12808  * Prepares a framebuffer for usage on a display plane.  Generally this
12809  * involves pinning the underlying object and updating the frontbuffer tracking
12810  * bits.  Some older platforms need special physical address handling for
12811  * cursor planes.
12812  *
12813  * Must be called with struct_mutex held.
12814  *
12815  * Returns 0 on success, negative error code on failure.
12816  */
12817 int
12818 intel_prepare_plane_fb(struct drm_plane *plane,
12819                        struct drm_plane_state *new_state)
12820 {
12821         struct intel_atomic_state *intel_state =
12822                 to_intel_atomic_state(new_state->state);
12823         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12824         struct drm_framebuffer *fb = new_state->fb;
12825         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12826         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12827         int ret;
12828
12829         if (old_obj) {
12830                 struct drm_crtc_state *crtc_state =
12831                         drm_atomic_get_new_crtc_state(new_state->state,
12832                                                       plane->state->crtc);
12833
12834                 /* Big Hammer, we also need to ensure that any pending
12835                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12836                  * current scanout is retired before unpinning the old
12837                  * framebuffer. Note that we rely on userspace rendering
12838                  * into the buffer attached to the pipe they are waiting
12839                  * on. If not, userspace generates a GPU hang with IPEHR
12840                  * point to the MI_WAIT_FOR_EVENT.
12841                  *
12842                  * This should only fail upon a hung GPU, in which case we
12843                  * can safely continue.
12844                  */
12845                 if (needs_modeset(crtc_state)) {
12846                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12847                                                               old_obj->resv, NULL,
12848                                                               false, 0,
12849                                                               GFP_KERNEL);
12850                         if (ret < 0)
12851                                 return ret;
12852                 }
12853         }
12854
12855         if (new_state->fence) { /* explicit fencing */
12856                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12857                                                     new_state->fence,
12858                                                     I915_FENCE_TIMEOUT,
12859                                                     GFP_KERNEL);
12860                 if (ret < 0)
12861                         return ret;
12862         }
12863
12864         if (!obj)
12865                 return 0;
12866
12867         ret = i915_gem_object_pin_pages(obj);
12868         if (ret)
12869                 return ret;
12870
12871         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12872         if (ret) {
12873                 i915_gem_object_unpin_pages(obj);
12874                 return ret;
12875         }
12876
12877         ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
12878
12879         fb_obj_bump_render_priority(obj);
12880
12881         mutex_unlock(&dev_priv->drm.struct_mutex);
12882         i915_gem_object_unpin_pages(obj);
12883         if (ret)
12884                 return ret;
12885
12886         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
12887
12888         if (!new_state->fence) { /* implicit fencing */
12889                 struct dma_fence *fence;
12890
12891                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12892                                                       obj->resv, NULL,
12893                                                       false, I915_FENCE_TIMEOUT,
12894                                                       GFP_KERNEL);
12895                 if (ret < 0)
12896                         return ret;
12897
12898                 fence = reservation_object_get_excl_rcu(obj->resv);
12899                 if (fence) {
12900                         add_rps_boost_after_vblank(new_state->crtc, fence);
12901                         dma_fence_put(fence);
12902                 }
12903         } else {
12904                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12905         }
12906
12907         return 0;
12908 }
12909
12910 /**
12911  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12912  * @plane: drm plane to clean up for
12913  * @old_state: the state from the previous modeset
12914  *
12915  * Cleans up a framebuffer that has just been removed from a plane.
12916  *
12917  * Must be called with struct_mutex held.
12918  */
12919 void
12920 intel_cleanup_plane_fb(struct drm_plane *plane,
12921                        struct drm_plane_state *old_state)
12922 {
12923         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12924
12925         /* Should only be called after a successful intel_prepare_plane_fb()! */
12926         mutex_lock(&dev_priv->drm.struct_mutex);
12927         intel_plane_unpin_fb(to_intel_plane_state(old_state));
12928         mutex_unlock(&dev_priv->drm.struct_mutex);
12929 }
12930
12931 int
12932 skl_max_scale(struct intel_crtc *intel_crtc,
12933               struct intel_crtc_state *crtc_state,
12934               uint32_t pixel_format)
12935 {
12936         struct drm_i915_private *dev_priv;
12937         int max_scale, mult;
12938         int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
12939
12940         if (!intel_crtc || !crtc_state->base.enable)
12941                 return DRM_PLANE_HELPER_NO_SCALING;
12942
12943         dev_priv = to_i915(intel_crtc->base.dev);
12944
12945         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12946         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12947
12948         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
12949                 max_dotclk *= 2;
12950
12951         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12952                 return DRM_PLANE_HELPER_NO_SCALING;
12953
12954         /*
12955          * skl max scale is lower of:
12956          *    close to 3 but not 3, -1 is for that purpose
12957          *            or
12958          *    cdclk/crtc_clock
12959          */
12960         mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
12961         tmpclk1 = (1 << 16) * mult - 1;
12962         tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
12963         max_scale = min(tmpclk1, tmpclk2);
12964
12965         return max_scale;
12966 }
12967
12968 static int
12969 intel_check_primary_plane(struct intel_plane *plane,
12970                           struct intel_crtc_state *crtc_state,
12971                           struct intel_plane_state *state)
12972 {
12973         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12974         struct drm_crtc *crtc = state->base.crtc;
12975         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12976         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12977         bool can_position = false;
12978         int ret;
12979         uint32_t pixel_format = 0;
12980
12981         if (INTEL_GEN(dev_priv) >= 9) {
12982                 /* use scaler when colorkey is not required */
12983                 if (!state->ckey.flags) {
12984                         min_scale = 1;
12985                         if (state->base.fb)
12986                                 pixel_format = state->base.fb->format->format;
12987                         max_scale = skl_max_scale(to_intel_crtc(crtc),
12988                                                   crtc_state, pixel_format);
12989                 }
12990                 can_position = true;
12991         }
12992
12993         ret = drm_atomic_helper_check_plane_state(&state->base,
12994                                                   &crtc_state->base,
12995                                                   min_scale, max_scale,
12996                                                   can_position, true);
12997         if (ret)
12998                 return ret;
12999
13000         if (!state->base.fb)
13001                 return 0;
13002
13003         if (INTEL_GEN(dev_priv) >= 9) {
13004                 ret = skl_check_plane_surface(crtc_state, state);
13005                 if (ret)
13006                         return ret;
13007
13008                 state->ctl = skl_plane_ctl(crtc_state, state);
13009         } else {
13010                 ret = i9xx_check_plane_surface(state);
13011                 if (ret)
13012                         return ret;
13013
13014                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13015         }
13016
13017         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
13018                 state->color_ctl = glk_plane_color_ctl(crtc_state, state);
13019
13020         return 0;
13021 }
13022
13023 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13024                                     struct drm_crtc_state *old_crtc_state)
13025 {
13026         struct drm_device *dev = crtc->dev;
13027         struct drm_i915_private *dev_priv = to_i915(dev);
13028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13029         struct intel_crtc_state *old_intel_cstate =
13030                 to_intel_crtc_state(old_crtc_state);
13031         struct intel_atomic_state *old_intel_state =
13032                 to_intel_atomic_state(old_crtc_state->state);
13033         struct intel_crtc_state *intel_cstate =
13034                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13035         bool modeset = needs_modeset(&intel_cstate->base);
13036
13037         if (!modeset &&
13038             (intel_cstate->base.color_mgmt_changed ||
13039              intel_cstate->update_pipe)) {
13040                 intel_color_set_csc(&intel_cstate->base);
13041                 intel_color_load_luts(&intel_cstate->base);
13042         }
13043
13044         /* Perform vblank evasion around commit operation */
13045         intel_pipe_update_start(intel_cstate);
13046
13047         if (modeset)
13048                 goto out;
13049
13050         if (intel_cstate->update_pipe)
13051                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
13052         else if (INTEL_GEN(dev_priv) >= 9)
13053                 skl_detach_scalers(intel_crtc);
13054
13055 out:
13056         if (dev_priv->display.atomic_update_watermarks)
13057                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13058                                                            intel_cstate);
13059 }
13060
13061 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
13062                                   struct intel_crtc_state *crtc_state)
13063 {
13064         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13065
13066         if (!IS_GEN2(dev_priv))
13067                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
13068
13069         if (crtc_state->has_pch_encoder) {
13070                 enum pipe pch_transcoder =
13071                         intel_crtc_pch_transcoder(crtc);
13072
13073                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
13074         }
13075 }
13076
13077 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13078                                      struct drm_crtc_state *old_crtc_state)
13079 {
13080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13081         struct intel_atomic_state *old_intel_state =
13082                 to_intel_atomic_state(old_crtc_state->state);
13083         struct intel_crtc_state *new_crtc_state =
13084                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
13085
13086         intel_pipe_update_end(new_crtc_state);
13087
13088         if (new_crtc_state->update_pipe &&
13089             !needs_modeset(&new_crtc_state->base) &&
13090             old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED)
13091                 intel_crtc_arm_fifo_underrun(intel_crtc, new_crtc_state);
13092 }
13093
13094 /**
13095  * intel_plane_destroy - destroy a plane
13096  * @plane: plane to destroy
13097  *
13098  * Common destruction function for all types of planes (primary, cursor,
13099  * sprite).
13100  */
13101 void intel_plane_destroy(struct drm_plane *plane)
13102 {
13103         drm_plane_cleanup(plane);
13104         kfree(to_intel_plane(plane));
13105 }
13106
13107 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
13108 {
13109         switch (format) {
13110         case DRM_FORMAT_C8:
13111         case DRM_FORMAT_RGB565:
13112         case DRM_FORMAT_XRGB1555:
13113         case DRM_FORMAT_XRGB8888:
13114                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13115                         modifier == I915_FORMAT_MOD_X_TILED;
13116         default:
13117                 return false;
13118         }
13119 }
13120
13121 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13122 {
13123         switch (format) {
13124         case DRM_FORMAT_C8:
13125         case DRM_FORMAT_RGB565:
13126         case DRM_FORMAT_XRGB8888:
13127         case DRM_FORMAT_XBGR8888:
13128         case DRM_FORMAT_XRGB2101010:
13129         case DRM_FORMAT_XBGR2101010:
13130                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13131                         modifier == I915_FORMAT_MOD_X_TILED;
13132         default:
13133                 return false;
13134         }
13135 }
13136
13137 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13138 {
13139         switch (format) {
13140         case DRM_FORMAT_XRGB8888:
13141         case DRM_FORMAT_XBGR8888:
13142         case DRM_FORMAT_ARGB8888:
13143         case DRM_FORMAT_ABGR8888:
13144                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13145                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13146                         return true;
13147                 /* fall through */
13148         case DRM_FORMAT_RGB565:
13149         case DRM_FORMAT_XRGB2101010:
13150         case DRM_FORMAT_XBGR2101010:
13151         case DRM_FORMAT_YUYV:
13152         case DRM_FORMAT_YVYU:
13153         case DRM_FORMAT_UYVY:
13154         case DRM_FORMAT_VYUY:
13155                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13156                         return true;
13157                 /* fall through */
13158         case DRM_FORMAT_C8:
13159                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13160                     modifier == I915_FORMAT_MOD_X_TILED ||
13161                     modifier == I915_FORMAT_MOD_Y_TILED)
13162                         return true;
13163                 /* fall through */
13164         default:
13165                 return false;
13166         }
13167 }
13168
13169 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13170                                                      uint32_t format,
13171                                                      uint64_t modifier)
13172 {
13173         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13174
13175         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13176                 return false;
13177
13178         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13179             modifier != DRM_FORMAT_MOD_LINEAR)
13180                 return false;
13181
13182         if (INTEL_GEN(dev_priv) >= 9)
13183                 return skl_mod_supported(format, modifier);
13184         else if (INTEL_GEN(dev_priv) >= 4)
13185                 return i965_mod_supported(format, modifier);
13186         else
13187                 return i8xx_mod_supported(format, modifier);
13188 }
13189
13190 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13191                                                     uint32_t format,
13192                                                     uint64_t modifier)
13193 {
13194         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13195                 return false;
13196
13197         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13198 }
13199
13200 static struct drm_plane_funcs intel_plane_funcs = {
13201         .update_plane = drm_atomic_helper_update_plane,
13202         .disable_plane = drm_atomic_helper_disable_plane,
13203         .destroy = intel_plane_destroy,
13204         .atomic_get_property = intel_plane_atomic_get_property,
13205         .atomic_set_property = intel_plane_atomic_set_property,
13206         .atomic_duplicate_state = intel_plane_duplicate_state,
13207         .atomic_destroy_state = intel_plane_destroy_state,
13208         .format_mod_supported = intel_primary_plane_format_mod_supported,
13209 };
13210
13211 static int
13212 intel_legacy_cursor_update(struct drm_plane *plane,
13213                            struct drm_crtc *crtc,
13214                            struct drm_framebuffer *fb,
13215                            int crtc_x, int crtc_y,
13216                            unsigned int crtc_w, unsigned int crtc_h,
13217                            uint32_t src_x, uint32_t src_y,
13218                            uint32_t src_w, uint32_t src_h,
13219                            struct drm_modeset_acquire_ctx *ctx)
13220 {
13221         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13222         int ret;
13223         struct drm_plane_state *old_plane_state, *new_plane_state;
13224         struct intel_plane *intel_plane = to_intel_plane(plane);
13225         struct drm_framebuffer *old_fb;
13226         struct drm_crtc_state *crtc_state = crtc->state;
13227
13228         /*
13229          * When crtc is inactive or there is a modeset pending,
13230          * wait for it to complete in the slowpath
13231          */
13232         if (!crtc_state->active || needs_modeset(crtc_state) ||
13233             to_intel_crtc_state(crtc_state)->update_pipe)
13234                 goto slow;
13235
13236         old_plane_state = plane->state;
13237         /*
13238          * Don't do an async update if there is an outstanding commit modifying
13239          * the plane.  This prevents our async update's changes from getting
13240          * overridden by a previous synchronous update's state.
13241          */
13242         if (old_plane_state->commit &&
13243             !try_wait_for_completion(&old_plane_state->commit->hw_done))
13244                 goto slow;
13245
13246         /*
13247          * If any parameters change that may affect watermarks,
13248          * take the slowpath. Only changing fb or position should be
13249          * in the fastpath.
13250          */
13251         if (old_plane_state->crtc != crtc ||
13252             old_plane_state->src_w != src_w ||
13253             old_plane_state->src_h != src_h ||
13254             old_plane_state->crtc_w != crtc_w ||
13255             old_plane_state->crtc_h != crtc_h ||
13256             !old_plane_state->fb != !fb)
13257                 goto slow;
13258
13259         new_plane_state = intel_plane_duplicate_state(plane);
13260         if (!new_plane_state)
13261                 return -ENOMEM;
13262
13263         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13264
13265         new_plane_state->src_x = src_x;
13266         new_plane_state->src_y = src_y;
13267         new_plane_state->src_w = src_w;
13268         new_plane_state->src_h = src_h;
13269         new_plane_state->crtc_x = crtc_x;
13270         new_plane_state->crtc_y = crtc_y;
13271         new_plane_state->crtc_w = crtc_w;
13272         new_plane_state->crtc_h = crtc_h;
13273
13274         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13275                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13276                                                   to_intel_plane_state(plane->state),
13277                                                   to_intel_plane_state(new_plane_state));
13278         if (ret)
13279                 goto out_free;
13280
13281         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13282         if (ret)
13283                 goto out_free;
13284
13285         ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
13286         if (ret)
13287                 goto out_unlock;
13288
13289         intel_fb_obj_flush(intel_fb_obj(fb), ORIGIN_FLIP);
13290
13291         old_fb = old_plane_state->fb;
13292         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13293                           intel_plane->frontbuffer_bit);
13294
13295         /* Swap plane state */
13296         plane->state = new_plane_state;
13297
13298         if (plane->state->visible) {
13299                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13300                 intel_plane->update_plane(intel_plane,
13301                                           to_intel_crtc_state(crtc->state),
13302                                           to_intel_plane_state(plane->state));
13303         } else {
13304                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13305                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13306         }
13307
13308         intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
13309
13310 out_unlock:
13311         mutex_unlock(&dev_priv->drm.struct_mutex);
13312 out_free:
13313         if (ret)
13314                 intel_plane_destroy_state(plane, new_plane_state);
13315         else
13316                 intel_plane_destroy_state(plane, old_plane_state);
13317         return ret;
13318
13319 slow:
13320         return drm_atomic_helper_update_plane(plane, crtc, fb,
13321                                               crtc_x, crtc_y, crtc_w, crtc_h,
13322                                               src_x, src_y, src_w, src_h, ctx);
13323 }
13324
13325 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13326         .update_plane = intel_legacy_cursor_update,
13327         .disable_plane = drm_atomic_helper_disable_plane,
13328         .destroy = intel_plane_destroy,
13329         .atomic_get_property = intel_plane_atomic_get_property,
13330         .atomic_set_property = intel_plane_atomic_set_property,
13331         .atomic_duplicate_state = intel_plane_duplicate_state,
13332         .atomic_destroy_state = intel_plane_destroy_state,
13333         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13334 };
13335
13336 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13337                                enum i9xx_plane_id i9xx_plane)
13338 {
13339         if (!HAS_FBC(dev_priv))
13340                 return false;
13341
13342         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13343                 return i9xx_plane == PLANE_A; /* tied to pipe A */
13344         else if (IS_IVYBRIDGE(dev_priv))
13345                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13346                         i9xx_plane == PLANE_C;
13347         else if (INTEL_GEN(dev_priv) >= 4)
13348                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13349         else
13350                 return i9xx_plane == PLANE_A;
13351 }
13352
13353 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13354                               enum pipe pipe, enum plane_id plane_id)
13355 {
13356         if (!HAS_FBC(dev_priv))
13357                 return false;
13358
13359         return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13360 }
13361
13362 static struct intel_plane *
13363 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13364 {
13365         struct intel_plane *primary = NULL;
13366         struct intel_plane_state *state = NULL;
13367         const uint32_t *intel_primary_formats;
13368         unsigned int supported_rotations;
13369         unsigned int num_formats;
13370         const uint64_t *modifiers;
13371         int ret;
13372
13373         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13374         if (!primary) {
13375                 ret = -ENOMEM;
13376                 goto fail;
13377         }
13378
13379         state = intel_create_plane_state(&primary->base);
13380         if (!state) {
13381                 ret = -ENOMEM;
13382                 goto fail;
13383         }
13384
13385         primary->base.state = &state->base;
13386
13387         primary->can_scale = false;
13388         primary->max_downscale = 1;
13389         if (INTEL_GEN(dev_priv) >= 9) {
13390                 primary->can_scale = true;
13391                 state->scaler_id = -1;
13392         }
13393         primary->pipe = pipe;
13394         /*
13395          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13396          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13397          */
13398         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13399                 primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
13400         else
13401                 primary->i9xx_plane = (enum i9xx_plane_id) pipe;
13402         primary->id = PLANE_PRIMARY;
13403         primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13404
13405         if (INTEL_GEN(dev_priv) >= 9)
13406                 primary->has_fbc = skl_plane_has_fbc(dev_priv,
13407                                                      primary->pipe,
13408                                                      primary->id);
13409         else
13410                 primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13411                                                       primary->i9xx_plane);
13412
13413         if (primary->has_fbc) {
13414                 struct intel_fbc *fbc = &dev_priv->fbc;
13415
13416                 fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13417         }
13418
13419         primary->check_plane = intel_check_primary_plane;
13420
13421         if (INTEL_GEN(dev_priv) >= 9) {
13422                 intel_primary_formats = skl_primary_formats;
13423                 num_formats = ARRAY_SIZE(skl_primary_formats);
13424
13425                 if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
13426                         modifiers = skl_format_modifiers_ccs;
13427                 else
13428                         modifiers = skl_format_modifiers_noccs;
13429
13430                 primary->update_plane = skl_update_plane;
13431                 primary->disable_plane = skl_disable_plane;
13432                 primary->get_hw_state = skl_plane_get_hw_state;
13433         } else if (INTEL_GEN(dev_priv) >= 4) {
13434                 intel_primary_formats = i965_primary_formats;
13435                 num_formats = ARRAY_SIZE(i965_primary_formats);
13436                 modifiers = i9xx_format_modifiers;
13437
13438                 primary->update_plane = i9xx_update_plane;
13439                 primary->disable_plane = i9xx_disable_plane;
13440                 primary->get_hw_state = i9xx_plane_get_hw_state;
13441         } else {
13442                 intel_primary_formats = i8xx_primary_formats;
13443                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13444                 modifiers = i9xx_format_modifiers;
13445
13446                 primary->update_plane = i9xx_update_plane;
13447                 primary->disable_plane = i9xx_disable_plane;
13448                 primary->get_hw_state = i9xx_plane_get_hw_state;
13449         }
13450
13451         if (INTEL_GEN(dev_priv) >= 9)
13452                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13453                                                0, &intel_plane_funcs,
13454                                                intel_primary_formats, num_formats,
13455                                                modifiers,
13456                                                DRM_PLANE_TYPE_PRIMARY,
13457                                                "plane 1%c", pipe_name(pipe));
13458         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13459                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13460                                                0, &intel_plane_funcs,
13461                                                intel_primary_formats, num_formats,
13462                                                modifiers,
13463                                                DRM_PLANE_TYPE_PRIMARY,
13464                                                "primary %c", pipe_name(pipe));
13465         else
13466                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13467                                                0, &intel_plane_funcs,
13468                                                intel_primary_formats, num_formats,
13469                                                modifiers,
13470                                                DRM_PLANE_TYPE_PRIMARY,
13471                                                "plane %c",
13472                                                plane_name(primary->i9xx_plane));
13473         if (ret)
13474                 goto fail;
13475
13476         if (INTEL_GEN(dev_priv) >= 10) {
13477                 supported_rotations =
13478                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13479                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
13480                         DRM_MODE_REFLECT_X;
13481         } else if (INTEL_GEN(dev_priv) >= 9) {
13482                 supported_rotations =
13483                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13484                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13485         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13486                 supported_rotations =
13487                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13488                         DRM_MODE_REFLECT_X;
13489         } else if (INTEL_GEN(dev_priv) >= 4) {
13490                 supported_rotations =
13491                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13492         } else {
13493                 supported_rotations = DRM_MODE_ROTATE_0;
13494         }
13495
13496         if (INTEL_GEN(dev_priv) >= 4)
13497                 drm_plane_create_rotation_property(&primary->base,
13498                                                    DRM_MODE_ROTATE_0,
13499                                                    supported_rotations);
13500
13501         if (INTEL_GEN(dev_priv) >= 9)
13502                 drm_plane_create_color_properties(&primary->base,
13503                                                   BIT(DRM_COLOR_YCBCR_BT601) |
13504                                                   BIT(DRM_COLOR_YCBCR_BT709),
13505                                                   BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
13506                                                   BIT(DRM_COLOR_YCBCR_FULL_RANGE),
13507                                                   DRM_COLOR_YCBCR_BT709,
13508                                                   DRM_COLOR_YCBCR_LIMITED_RANGE);
13509
13510         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13511
13512         return primary;
13513
13514 fail:
13515         kfree(state);
13516         kfree(primary);
13517
13518         return ERR_PTR(ret);
13519 }
13520
13521 static struct intel_plane *
13522 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13523                           enum pipe pipe)
13524 {
13525         struct intel_plane *cursor = NULL;
13526         struct intel_plane_state *state = NULL;
13527         int ret;
13528
13529         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13530         if (!cursor) {
13531                 ret = -ENOMEM;
13532                 goto fail;
13533         }
13534
13535         state = intel_create_plane_state(&cursor->base);
13536         if (!state) {
13537                 ret = -ENOMEM;
13538                 goto fail;
13539         }
13540
13541         cursor->base.state = &state->base;
13542
13543         cursor->can_scale = false;
13544         cursor->max_downscale = 1;
13545         cursor->pipe = pipe;
13546         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
13547         cursor->id = PLANE_CURSOR;
13548         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
13549
13550         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13551                 cursor->update_plane = i845_update_cursor;
13552                 cursor->disable_plane = i845_disable_cursor;
13553                 cursor->get_hw_state = i845_cursor_get_hw_state;
13554                 cursor->check_plane = i845_check_cursor;
13555         } else {
13556                 cursor->update_plane = i9xx_update_cursor;
13557                 cursor->disable_plane = i9xx_disable_cursor;
13558                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
13559                 cursor->check_plane = i9xx_check_cursor;
13560         }
13561
13562         cursor->cursor.base = ~0;
13563         cursor->cursor.cntl = ~0;
13564
13565         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13566                 cursor->cursor.size = ~0;
13567
13568         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13569                                        0, &intel_cursor_plane_funcs,
13570                                        intel_cursor_formats,
13571                                        ARRAY_SIZE(intel_cursor_formats),
13572                                        cursor_format_modifiers,
13573                                        DRM_PLANE_TYPE_CURSOR,
13574                                        "cursor %c", pipe_name(pipe));
13575         if (ret)
13576                 goto fail;
13577
13578         if (INTEL_GEN(dev_priv) >= 4)
13579                 drm_plane_create_rotation_property(&cursor->base,
13580                                                    DRM_MODE_ROTATE_0,
13581                                                    DRM_MODE_ROTATE_0 |
13582                                                    DRM_MODE_ROTATE_180);
13583
13584         if (INTEL_GEN(dev_priv) >= 9)
13585                 state->scaler_id = -1;
13586
13587         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13588
13589         return cursor;
13590
13591 fail:
13592         kfree(state);
13593         kfree(cursor);
13594
13595         return ERR_PTR(ret);
13596 }
13597
13598 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13599                                     struct intel_crtc_state *crtc_state)
13600 {
13601         struct intel_crtc_scaler_state *scaler_state =
13602                 &crtc_state->scaler_state;
13603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13604         int i;
13605
13606         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13607         if (!crtc->num_scalers)
13608                 return;
13609
13610         for (i = 0; i < crtc->num_scalers; i++) {
13611                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13612
13613                 scaler->in_use = 0;
13614                 scaler->mode = PS_SCALER_MODE_DYN;
13615         }
13616
13617         scaler_state->scaler_id = -1;
13618 }
13619
13620 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13621 {
13622         struct intel_crtc *intel_crtc;
13623         struct intel_crtc_state *crtc_state = NULL;
13624         struct intel_plane *primary = NULL;
13625         struct intel_plane *cursor = NULL;
13626         int sprite, ret;
13627
13628         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13629         if (!intel_crtc)
13630                 return -ENOMEM;
13631
13632         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13633         if (!crtc_state) {
13634                 ret = -ENOMEM;
13635                 goto fail;
13636         }
13637         intel_crtc->config = crtc_state;
13638         intel_crtc->base.state = &crtc_state->base;
13639         crtc_state->base.crtc = &intel_crtc->base;
13640
13641         primary = intel_primary_plane_create(dev_priv, pipe);
13642         if (IS_ERR(primary)) {
13643                 ret = PTR_ERR(primary);
13644                 goto fail;
13645         }
13646         intel_crtc->plane_ids_mask |= BIT(primary->id);
13647
13648         for_each_sprite(dev_priv, pipe, sprite) {
13649                 struct intel_plane *plane;
13650
13651                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13652                 if (IS_ERR(plane)) {
13653                         ret = PTR_ERR(plane);
13654                         goto fail;
13655                 }
13656                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13657         }
13658
13659         cursor = intel_cursor_plane_create(dev_priv, pipe);
13660         if (IS_ERR(cursor)) {
13661                 ret = PTR_ERR(cursor);
13662                 goto fail;
13663         }
13664         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13665
13666         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13667                                         &primary->base, &cursor->base,
13668                                         &intel_crtc_funcs,
13669                                         "pipe %c", pipe_name(pipe));
13670         if (ret)
13671                 goto fail;
13672
13673         intel_crtc->pipe = pipe;
13674
13675         /* initialize shared scalers */
13676         intel_crtc_init_scalers(intel_crtc, crtc_state);
13677
13678         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
13679                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
13680         dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
13681
13682         if (INTEL_GEN(dev_priv) < 9) {
13683                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
13684
13685                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13686                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
13687                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
13688         }
13689
13690         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13691
13692         intel_color_init(&intel_crtc->base);
13693
13694         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13695
13696         return 0;
13697
13698 fail:
13699         /*
13700          * drm_mode_config_cleanup() will free up any
13701          * crtcs/planes already initialized.
13702          */
13703         kfree(crtc_state);
13704         kfree(intel_crtc);
13705
13706         return ret;
13707 }
13708
13709 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13710 {
13711         struct drm_device *dev = connector->base.dev;
13712
13713         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13714
13715         if (!connector->base.state->crtc)
13716                 return INVALID_PIPE;
13717
13718         return to_intel_crtc(connector->base.state->crtc)->pipe;
13719 }
13720
13721 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
13722                                       struct drm_file *file)
13723 {
13724         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13725         struct drm_crtc *drmmode_crtc;
13726         struct intel_crtc *crtc;
13727
13728         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
13729         if (!drmmode_crtc)
13730                 return -ENOENT;
13731
13732         crtc = to_intel_crtc(drmmode_crtc);
13733         pipe_from_crtc_id->pipe = crtc->pipe;
13734
13735         return 0;
13736 }
13737
13738 static int intel_encoder_clones(struct intel_encoder *encoder)
13739 {
13740         struct drm_device *dev = encoder->base.dev;
13741         struct intel_encoder *source_encoder;
13742         int index_mask = 0;
13743         int entry = 0;
13744
13745         for_each_intel_encoder(dev, source_encoder) {
13746                 if (encoders_cloneable(encoder, source_encoder))
13747                         index_mask |= (1 << entry);
13748
13749                 entry++;
13750         }
13751
13752         return index_mask;
13753 }
13754
13755 static bool has_edp_a(struct drm_i915_private *dev_priv)
13756 {
13757         if (!IS_MOBILE(dev_priv))
13758                 return false;
13759
13760         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13761                 return false;
13762
13763         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13764                 return false;
13765
13766         return true;
13767 }
13768
13769 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13770 {
13771         if (INTEL_GEN(dev_priv) >= 9)
13772                 return false;
13773
13774         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13775                 return false;
13776
13777         if (IS_CHERRYVIEW(dev_priv))
13778                 return false;
13779
13780         if (HAS_PCH_LPT_H(dev_priv) &&
13781             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13782                 return false;
13783
13784         /* DDI E can't be used if DDI A requires 4 lanes */
13785         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13786                 return false;
13787
13788         if (!dev_priv->vbt.int_crt_support)
13789                 return false;
13790
13791         return true;
13792 }
13793
13794 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13795 {
13796         int pps_num;
13797         int pps_idx;
13798
13799         if (HAS_DDI(dev_priv))
13800                 return;
13801         /*
13802          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13803          * everywhere where registers can be write protected.
13804          */
13805         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13806                 pps_num = 2;
13807         else
13808                 pps_num = 1;
13809
13810         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13811                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13812
13813                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13814                 I915_WRITE(PP_CONTROL(pps_idx), val);
13815         }
13816 }
13817
13818 static void intel_pps_init(struct drm_i915_private *dev_priv)
13819 {
13820         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13821                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13822         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13823                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13824         else
13825                 dev_priv->pps_mmio_base = PPS_BASE;
13826
13827         intel_pps_unlock_regs_wa(dev_priv);
13828 }
13829
13830 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13831 {
13832         struct intel_encoder *encoder;
13833         bool dpd_is_edp = false;
13834
13835         intel_pps_init(dev_priv);
13836
13837         /*
13838          * intel_edp_init_connector() depends on this completing first, to
13839          * prevent the registeration of both eDP and LVDS and the incorrect
13840          * sharing of the PPS.
13841          */
13842         intel_lvds_init(dev_priv);
13843
13844         if (intel_crt_present(dev_priv))
13845                 intel_crt_init(dev_priv);
13846
13847         if (IS_GEN9_LP(dev_priv)) {
13848                 /*
13849                  * FIXME: Broxton doesn't support port detection via the
13850                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13851                  * detect the ports.
13852                  */
13853                 intel_ddi_init(dev_priv, PORT_A);
13854                 intel_ddi_init(dev_priv, PORT_B);
13855                 intel_ddi_init(dev_priv, PORT_C);
13856
13857                 intel_dsi_init(dev_priv);
13858         } else if (HAS_DDI(dev_priv)) {
13859                 int found;
13860
13861                 /*
13862                  * Haswell uses DDI functions to detect digital outputs.
13863                  * On SKL pre-D0 the strap isn't connected, so we assume
13864                  * it's there.
13865                  */
13866                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13867                 /* WaIgnoreDDIAStrap: skl */
13868                 if (found || IS_GEN9_BC(dev_priv))
13869                         intel_ddi_init(dev_priv, PORT_A);
13870
13871                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
13872                  * register */
13873                 found = I915_READ(SFUSE_STRAP);
13874
13875                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13876                         intel_ddi_init(dev_priv, PORT_B);
13877                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13878                         intel_ddi_init(dev_priv, PORT_C);
13879                 if (found & SFUSE_STRAP_DDID_DETECTED)
13880                         intel_ddi_init(dev_priv, PORT_D);
13881                 if (found & SFUSE_STRAP_DDIF_DETECTED)
13882                         intel_ddi_init(dev_priv, PORT_F);
13883                 /*
13884                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13885                  */
13886                 if (IS_GEN9_BC(dev_priv) &&
13887                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13888                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13889                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13890                         intel_ddi_init(dev_priv, PORT_E);
13891
13892         } else if (HAS_PCH_SPLIT(dev_priv)) {
13893                 int found;
13894                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13895
13896                 if (has_edp_a(dev_priv))
13897                         intel_dp_init(dev_priv, DP_A, PORT_A);
13898
13899                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13900                         /* PCH SDVOB multiplex with HDMIB */
13901                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13902                         if (!found)
13903                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13904                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13905                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13906                 }
13907
13908                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13909                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13910
13911                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13912                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13913
13914                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13915                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13916
13917                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13918                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13919         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13920                 bool has_edp, has_port;
13921
13922                 /*
13923                  * The DP_DETECTED bit is the latched state of the DDC
13924                  * SDA pin at boot. However since eDP doesn't require DDC
13925                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13926                  * eDP ports may have been muxed to an alternate function.
13927                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13928                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13929                  * detect eDP ports.
13930                  *
13931                  * Sadly the straps seem to be missing sometimes even for HDMI
13932                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13933                  * and VBT for the presence of the port. Additionally we can't
13934                  * trust the port type the VBT declares as we've seen at least
13935                  * HDMI ports that the VBT claim are DP or eDP.
13936                  */
13937                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13938                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13939                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13940                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13941                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13942                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13943
13944                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13945                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13946                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13947                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13948                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13949                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13950
13951                 if (IS_CHERRYVIEW(dev_priv)) {
13952                         /*
13953                          * eDP not supported on port D,
13954                          * so no need to worry about it
13955                          */
13956                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13957                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13958                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13959                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13960                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13961                 }
13962
13963                 intel_dsi_init(dev_priv);
13964         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13965                 bool found = false;
13966
13967                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13968                         DRM_DEBUG_KMS("probing SDVOB\n");
13969                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13970                         if (!found && IS_G4X(dev_priv)) {
13971                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13972                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13973                         }
13974
13975                         if (!found && IS_G4X(dev_priv))
13976                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13977                 }
13978
13979                 /* Before G4X SDVOC doesn't have its own detect register */
13980
13981                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13982                         DRM_DEBUG_KMS("probing SDVOC\n");
13983                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13984                 }
13985
13986                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13987
13988                         if (IS_G4X(dev_priv)) {
13989                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13990                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13991                         }
13992                         if (IS_G4X(dev_priv))
13993                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13994                 }
13995
13996                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13997                         intel_dp_init(dev_priv, DP_D, PORT_D);
13998         } else if (IS_GEN2(dev_priv))
13999                 intel_dvo_init(dev_priv);
14000
14001         if (SUPPORTS_TV(dev_priv))
14002                 intel_tv_init(dev_priv);
14003
14004         intel_psr_init(dev_priv);
14005
14006         for_each_intel_encoder(&dev_priv->drm, encoder) {
14007                 encoder->base.possible_crtcs = encoder->crtc_mask;
14008                 encoder->base.possible_clones =
14009                         intel_encoder_clones(encoder);
14010         }
14011
14012         intel_init_pch_refclk(dev_priv);
14013
14014         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14015 }
14016
14017 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14018 {
14019         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14020
14021         drm_framebuffer_cleanup(fb);
14022
14023         i915_gem_object_lock(intel_fb->obj);
14024         WARN_ON(!intel_fb->obj->framebuffer_references--);
14025         i915_gem_object_unlock(intel_fb->obj);
14026
14027         i915_gem_object_put(intel_fb->obj);
14028
14029         kfree(intel_fb);
14030 }
14031
14032 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14033                                                 struct drm_file *file,
14034                                                 unsigned int *handle)
14035 {
14036         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14037         struct drm_i915_gem_object *obj = intel_fb->obj;
14038
14039         if (obj->userptr.mm) {
14040                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14041                 return -EINVAL;
14042         }
14043
14044         return drm_gem_handle_create(file, &obj->base, handle);
14045 }
14046
14047 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14048                                         struct drm_file *file,
14049                                         unsigned flags, unsigned color,
14050                                         struct drm_clip_rect *clips,
14051                                         unsigned num_clips)
14052 {
14053         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14054
14055         i915_gem_object_flush_if_display(obj);
14056         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14057
14058         return 0;
14059 }
14060
14061 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14062         .destroy = intel_user_framebuffer_destroy,
14063         .create_handle = intel_user_framebuffer_create_handle,
14064         .dirty = intel_user_framebuffer_dirty,
14065 };
14066
14067 static
14068 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14069                          uint64_t fb_modifier, uint32_t pixel_format)
14070 {
14071         u32 gen = INTEL_GEN(dev_priv);
14072
14073         if (gen >= 9) {
14074                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14075
14076                 /* "The stride in bytes must not exceed the of the size of 8K
14077                  *  pixels and 32K bytes."
14078                  */
14079                 return min(8192 * cpp, 32768);
14080         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14081                 return 32*1024;
14082         } else if (gen >= 4) {
14083                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14084                         return 16*1024;
14085                 else
14086                         return 32*1024;
14087         } else if (gen >= 3) {
14088                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14089                         return 8*1024;
14090                 else
14091                         return 16*1024;
14092         } else {
14093                 /* XXX DSPC is limited to 4k tiled */
14094                 return 8*1024;
14095         }
14096 }
14097
14098 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14099                                   struct drm_i915_gem_object *obj,
14100                                   struct drm_mode_fb_cmd2 *mode_cmd)
14101 {
14102         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14103         struct drm_framebuffer *fb = &intel_fb->base;
14104         struct drm_format_name_buf format_name;
14105         u32 pitch_limit;
14106         unsigned int tiling, stride;
14107         int ret = -EINVAL;
14108         int i;
14109
14110         i915_gem_object_lock(obj);
14111         obj->framebuffer_references++;
14112         tiling = i915_gem_object_get_tiling(obj);
14113         stride = i915_gem_object_get_stride(obj);
14114         i915_gem_object_unlock(obj);
14115
14116         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14117                 /*
14118                  * If there's a fence, enforce that
14119                  * the fb modifier and tiling mode match.
14120                  */
14121                 if (tiling != I915_TILING_NONE &&
14122                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14123                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14124                         goto err;
14125                 }
14126         } else {
14127                 if (tiling == I915_TILING_X) {
14128                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14129                 } else if (tiling == I915_TILING_Y) {
14130                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14131                         goto err;
14132                 }
14133         }
14134
14135         /* Passed in modifier sanity checking. */
14136         switch (mode_cmd->modifier[0]) {
14137         case I915_FORMAT_MOD_Y_TILED_CCS:
14138         case I915_FORMAT_MOD_Yf_TILED_CCS:
14139                 switch (mode_cmd->pixel_format) {
14140                 case DRM_FORMAT_XBGR8888:
14141                 case DRM_FORMAT_ABGR8888:
14142                 case DRM_FORMAT_XRGB8888:
14143                 case DRM_FORMAT_ARGB8888:
14144                         break;
14145                 default:
14146                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
14147                         goto err;
14148                 }
14149                 /* fall through */
14150         case I915_FORMAT_MOD_Y_TILED:
14151         case I915_FORMAT_MOD_Yf_TILED:
14152                 if (INTEL_GEN(dev_priv) < 9) {
14153                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14154                                       mode_cmd->modifier[0]);
14155                         goto err;
14156                 }
14157         case DRM_FORMAT_MOD_LINEAR:
14158         case I915_FORMAT_MOD_X_TILED:
14159                 break;
14160         default:
14161                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14162                               mode_cmd->modifier[0]);
14163                 goto err;
14164         }
14165
14166         /*
14167          * gen2/3 display engine uses the fence if present,
14168          * so the tiling mode must match the fb modifier exactly.
14169          */
14170         if (INTEL_GEN(dev_priv) < 4 &&
14171             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14172                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14173                 goto err;
14174         }
14175
14176         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14177                                            mode_cmd->pixel_format);
14178         if (mode_cmd->pitches[0] > pitch_limit) {
14179                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14180                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14181                               "tiled" : "linear",
14182                               mode_cmd->pitches[0], pitch_limit);
14183                 goto err;
14184         }
14185
14186         /*
14187          * If there's a fence, enforce that
14188          * the fb pitch and fence stride match.
14189          */
14190         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14191                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14192                               mode_cmd->pitches[0], stride);
14193                 goto err;
14194         }
14195
14196         /* Reject formats not supported by any plane early. */
14197         switch (mode_cmd->pixel_format) {
14198         case DRM_FORMAT_C8:
14199         case DRM_FORMAT_RGB565:
14200         case DRM_FORMAT_XRGB8888:
14201         case DRM_FORMAT_ARGB8888:
14202                 break;
14203         case DRM_FORMAT_XRGB1555:
14204                 if (INTEL_GEN(dev_priv) > 3) {
14205                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14206                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14207                         goto err;
14208                 }
14209                 break;
14210         case DRM_FORMAT_ABGR8888:
14211                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14212                     INTEL_GEN(dev_priv) < 9) {
14213                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14214                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14215                         goto err;
14216                 }
14217                 break;
14218         case DRM_FORMAT_XBGR8888:
14219         case DRM_FORMAT_XRGB2101010:
14220         case DRM_FORMAT_XBGR2101010:
14221                 if (INTEL_GEN(dev_priv) < 4) {
14222                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14223                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14224                         goto err;
14225                 }
14226                 break;
14227         case DRM_FORMAT_ABGR2101010:
14228                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14229                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14230                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14231                         goto err;
14232                 }
14233                 break;
14234         case DRM_FORMAT_YUYV:
14235         case DRM_FORMAT_UYVY:
14236         case DRM_FORMAT_YVYU:
14237         case DRM_FORMAT_VYUY:
14238                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14239                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14240                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14241                         goto err;
14242                 }
14243                 break;
14244         default:
14245                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14246                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14247                 goto err;
14248         }
14249
14250         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14251         if (mode_cmd->offsets[0] != 0)
14252                 goto err;
14253
14254         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14255
14256         for (i = 0; i < fb->format->num_planes; i++) {
14257                 u32 stride_alignment;
14258
14259                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14260                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14261                         goto err;
14262                 }
14263
14264                 stride_alignment = intel_fb_stride_alignment(fb, i);
14265
14266                 /*
14267                  * Display WA #0531: skl,bxt,kbl,glk
14268                  *
14269                  * Render decompression and plane width > 3840
14270                  * combined with horizontal panning requires the
14271                  * plane stride to be a multiple of 4. We'll just
14272                  * require the entire fb to accommodate that to avoid
14273                  * potential runtime errors at plane configuration time.
14274                  */
14275                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14276                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14277                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14278                         stride_alignment *= 4;
14279
14280                 if (fb->pitches[i] & (stride_alignment - 1)) {
14281                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14282                                       i, fb->pitches[i], stride_alignment);
14283                         goto err;
14284                 }
14285         }
14286
14287         intel_fb->obj = obj;
14288
14289         ret = intel_fill_fb_info(dev_priv, fb);
14290         if (ret)
14291                 goto err;
14292
14293         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14294         if (ret) {
14295                 DRM_ERROR("framebuffer init failed %d\n", ret);
14296                 goto err;
14297         }
14298
14299         return 0;
14300
14301 err:
14302         i915_gem_object_lock(obj);
14303         obj->framebuffer_references--;
14304         i915_gem_object_unlock(obj);
14305         return ret;
14306 }
14307
14308 static struct drm_framebuffer *
14309 intel_user_framebuffer_create(struct drm_device *dev,
14310                               struct drm_file *filp,
14311                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14312 {
14313         struct drm_framebuffer *fb;
14314         struct drm_i915_gem_object *obj;
14315         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14316
14317         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14318         if (!obj)
14319                 return ERR_PTR(-ENOENT);
14320
14321         fb = intel_framebuffer_create(obj, &mode_cmd);
14322         if (IS_ERR(fb))
14323                 i915_gem_object_put(obj);
14324
14325         return fb;
14326 }
14327
14328 static void intel_atomic_state_free(struct drm_atomic_state *state)
14329 {
14330         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14331
14332         drm_atomic_state_default_release(state);
14333
14334         i915_sw_fence_fini(&intel_state->commit_ready);
14335
14336         kfree(state);
14337 }
14338
14339 static enum drm_mode_status
14340 intel_mode_valid(struct drm_device *dev,
14341                  const struct drm_display_mode *mode)
14342 {
14343         if (mode->vscan > 1)
14344                 return MODE_NO_VSCAN;
14345
14346         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
14347                 return MODE_NO_DBLESCAN;
14348
14349         if (mode->flags & DRM_MODE_FLAG_HSKEW)
14350                 return MODE_H_ILLEGAL;
14351
14352         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
14353                            DRM_MODE_FLAG_NCSYNC |
14354                            DRM_MODE_FLAG_PCSYNC))
14355                 return MODE_HSYNC;
14356
14357         if (mode->flags & (DRM_MODE_FLAG_BCAST |
14358                            DRM_MODE_FLAG_PIXMUX |
14359                            DRM_MODE_FLAG_CLKDIV2))
14360                 return MODE_BAD;
14361
14362         return MODE_OK;
14363 }
14364
14365 static const struct drm_mode_config_funcs intel_mode_funcs = {
14366         .fb_create = intel_user_framebuffer_create,
14367         .get_format_info = intel_get_format_info,
14368         .output_poll_changed = intel_fbdev_output_poll_changed,
14369         .mode_valid = intel_mode_valid,
14370         .atomic_check = intel_atomic_check,
14371         .atomic_commit = intel_atomic_commit,
14372         .atomic_state_alloc = intel_atomic_state_alloc,
14373         .atomic_state_clear = intel_atomic_state_clear,
14374         .atomic_state_free = intel_atomic_state_free,
14375 };
14376
14377 /**
14378  * intel_init_display_hooks - initialize the display modesetting hooks
14379  * @dev_priv: device private
14380  */
14381 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14382 {
14383         intel_init_cdclk_hooks(dev_priv);
14384
14385         if (INTEL_GEN(dev_priv) >= 9) {
14386                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14387                 dev_priv->display.get_initial_plane_config =
14388                         skylake_get_initial_plane_config;
14389                 dev_priv->display.crtc_compute_clock =
14390                         haswell_crtc_compute_clock;
14391                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14392                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14393         } else if (HAS_DDI(dev_priv)) {
14394                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14395                 dev_priv->display.get_initial_plane_config =
14396                         i9xx_get_initial_plane_config;
14397                 dev_priv->display.crtc_compute_clock =
14398                         haswell_crtc_compute_clock;
14399                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14400                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14401         } else if (HAS_PCH_SPLIT(dev_priv)) {
14402                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14403                 dev_priv->display.get_initial_plane_config =
14404                         i9xx_get_initial_plane_config;
14405                 dev_priv->display.crtc_compute_clock =
14406                         ironlake_crtc_compute_clock;
14407                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14408                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14409         } else if (IS_CHERRYVIEW(dev_priv)) {
14410                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14411                 dev_priv->display.get_initial_plane_config =
14412                         i9xx_get_initial_plane_config;
14413                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14414                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14415                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14416         } else if (IS_VALLEYVIEW(dev_priv)) {
14417                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14418                 dev_priv->display.get_initial_plane_config =
14419                         i9xx_get_initial_plane_config;
14420                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14421                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14422                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14423         } else if (IS_G4X(dev_priv)) {
14424                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14425                 dev_priv->display.get_initial_plane_config =
14426                         i9xx_get_initial_plane_config;
14427                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14428                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14429                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14430         } else if (IS_PINEVIEW(dev_priv)) {
14431                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14432                 dev_priv->display.get_initial_plane_config =
14433                         i9xx_get_initial_plane_config;
14434                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14435                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14436                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14437         } else if (!IS_GEN2(dev_priv)) {
14438                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14439                 dev_priv->display.get_initial_plane_config =
14440                         i9xx_get_initial_plane_config;
14441                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14442                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14443                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14444         } else {
14445                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14446                 dev_priv->display.get_initial_plane_config =
14447                         i9xx_get_initial_plane_config;
14448                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14449                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14450                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14451         }
14452
14453         if (IS_GEN5(dev_priv)) {
14454                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14455         } else if (IS_GEN6(dev_priv)) {
14456                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14457         } else if (IS_IVYBRIDGE(dev_priv)) {
14458                 /* FIXME: detect B0+ stepping and use auto training */
14459                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14460         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14461                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14462         }
14463
14464         if (INTEL_GEN(dev_priv) >= 9)
14465                 dev_priv->display.update_crtcs = skl_update_crtcs;
14466         else
14467                 dev_priv->display.update_crtcs = intel_update_crtcs;
14468 }
14469
14470 /*
14471  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14472  */
14473 static void quirk_ssc_force_disable(struct drm_device *dev)
14474 {
14475         struct drm_i915_private *dev_priv = to_i915(dev);
14476         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14477         DRM_INFO("applying lvds SSC disable quirk\n");
14478 }
14479
14480 /*
14481  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14482  * brightness value
14483  */
14484 static void quirk_invert_brightness(struct drm_device *dev)
14485 {
14486         struct drm_i915_private *dev_priv = to_i915(dev);
14487         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14488         DRM_INFO("applying inverted panel brightness quirk\n");
14489 }
14490
14491 /* Some VBT's incorrectly indicate no backlight is present */
14492 static void quirk_backlight_present(struct drm_device *dev)
14493 {
14494         struct drm_i915_private *dev_priv = to_i915(dev);
14495         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14496         DRM_INFO("applying backlight present quirk\n");
14497 }
14498
14499 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14500  * which is 300 ms greater than eDP spec T12 min.
14501  */
14502 static void quirk_increase_t12_delay(struct drm_device *dev)
14503 {
14504         struct drm_i915_private *dev_priv = to_i915(dev);
14505
14506         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14507         DRM_INFO("Applying T12 delay quirk\n");
14508 }
14509
14510 struct intel_quirk {
14511         int device;
14512         int subsystem_vendor;
14513         int subsystem_device;
14514         void (*hook)(struct drm_device *dev);
14515 };
14516
14517 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14518 struct intel_dmi_quirk {
14519         void (*hook)(struct drm_device *dev);
14520         const struct dmi_system_id (*dmi_id_list)[];
14521 };
14522
14523 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14524 {
14525         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14526         return 1;
14527 }
14528
14529 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14530         {
14531                 .dmi_id_list = &(const struct dmi_system_id[]) {
14532                         {
14533                                 .callback = intel_dmi_reverse_brightness,
14534                                 .ident = "NCR Corporation",
14535                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14536                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14537                                 },
14538                         },
14539                         { }  /* terminating entry */
14540                 },
14541                 .hook = quirk_invert_brightness,
14542         },
14543 };
14544
14545 static struct intel_quirk intel_quirks[] = {
14546         /* Lenovo U160 cannot use SSC on LVDS */
14547         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14548
14549         /* Sony Vaio Y cannot use SSC on LVDS */
14550         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14551
14552         /* Acer Aspire 5734Z must invert backlight brightness */
14553         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14554
14555         /* Acer/eMachines G725 */
14556         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14557
14558         /* Acer/eMachines e725 */
14559         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14560
14561         /* Acer/Packard Bell NCL20 */
14562         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14563
14564         /* Acer Aspire 4736Z */
14565         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14566
14567         /* Acer Aspire 5336 */
14568         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14569
14570         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14571         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14572
14573         /* Acer C720 Chromebook (Core i3 4005U) */
14574         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14575
14576         /* Apple Macbook 2,1 (Core 2 T7400) */
14577         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14578
14579         /* Apple Macbook 4,1 */
14580         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14581
14582         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14583         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14584
14585         /* HP Chromebook 14 (Celeron 2955U) */
14586         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14587
14588         /* Dell Chromebook 11 */
14589         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14590
14591         /* Dell Chromebook 11 (2015 version) */
14592         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14593
14594         /* Toshiba Satellite P50-C-18C */
14595         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14596 };
14597
14598 static void intel_init_quirks(struct drm_device *dev)
14599 {
14600         struct pci_dev *d = dev->pdev;
14601         int i;
14602
14603         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14604                 struct intel_quirk *q = &intel_quirks[i];
14605
14606                 if (d->device == q->device &&
14607                     (d->subsystem_vendor == q->subsystem_vendor ||
14608                      q->subsystem_vendor == PCI_ANY_ID) &&
14609                     (d->subsystem_device == q->subsystem_device ||
14610                      q->subsystem_device == PCI_ANY_ID))
14611                         q->hook(dev);
14612         }
14613         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14614                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14615                         intel_dmi_quirks[i].hook(dev);
14616         }
14617 }
14618
14619 /* Disable the VGA plane that we never use */
14620 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14621 {
14622         struct pci_dev *pdev = dev_priv->drm.pdev;
14623         u8 sr1;
14624         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14625
14626         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14627         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14628         outb(SR01, VGA_SR_INDEX);
14629         sr1 = inb(VGA_SR_DATA);
14630         outb(sr1 | 1<<5, VGA_SR_DATA);
14631         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14632         udelay(300);
14633
14634         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14635         POSTING_READ(vga_reg);
14636 }
14637
14638 void intel_modeset_init_hw(struct drm_device *dev)
14639 {
14640         struct drm_i915_private *dev_priv = to_i915(dev);
14641
14642         intel_update_cdclk(dev_priv);
14643         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
14644         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14645 }
14646
14647 /*
14648  * Calculate what we think the watermarks should be for the state we've read
14649  * out of the hardware and then immediately program those watermarks so that
14650  * we ensure the hardware settings match our internal state.
14651  *
14652  * We can calculate what we think WM's should be by creating a duplicate of the
14653  * current state (which was constructed during hardware readout) and running it
14654  * through the atomic check code to calculate new watermark values in the
14655  * state object.
14656  */
14657 static void sanitize_watermarks(struct drm_device *dev)
14658 {
14659         struct drm_i915_private *dev_priv = to_i915(dev);
14660         struct drm_atomic_state *state;
14661         struct intel_atomic_state *intel_state;
14662         struct drm_crtc *crtc;
14663         struct drm_crtc_state *cstate;
14664         struct drm_modeset_acquire_ctx ctx;
14665         int ret;
14666         int i;
14667
14668         /* Only supported on platforms that use atomic watermark design */
14669         if (!dev_priv->display.optimize_watermarks)
14670                 return;
14671
14672         /*
14673          * We need to hold connection_mutex before calling duplicate_state so
14674          * that the connector loop is protected.
14675          */
14676         drm_modeset_acquire_init(&ctx, 0);
14677 retry:
14678         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14679         if (ret == -EDEADLK) {
14680                 drm_modeset_backoff(&ctx);
14681                 goto retry;
14682         } else if (WARN_ON(ret)) {
14683                 goto fail;
14684         }
14685
14686         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14687         if (WARN_ON(IS_ERR(state)))
14688                 goto fail;
14689
14690         intel_state = to_intel_atomic_state(state);
14691
14692         /*
14693          * Hardware readout is the only time we don't want to calculate
14694          * intermediate watermarks (since we don't trust the current
14695          * watermarks).
14696          */
14697         if (!HAS_GMCH_DISPLAY(dev_priv))
14698                 intel_state->skip_intermediate_wm = true;
14699
14700         ret = intel_atomic_check(dev, state);
14701         if (ret) {
14702                 /*
14703                  * If we fail here, it means that the hardware appears to be
14704                  * programmed in a way that shouldn't be possible, given our
14705                  * understanding of watermark requirements.  This might mean a
14706                  * mistake in the hardware readout code or a mistake in the
14707                  * watermark calculations for a given platform.  Raise a WARN
14708                  * so that this is noticeable.
14709                  *
14710                  * If this actually happens, we'll have to just leave the
14711                  * BIOS-programmed watermarks untouched and hope for the best.
14712                  */
14713                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14714                 goto put_state;
14715         }
14716
14717         /* Write calculated watermark values back */
14718         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14719                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14720
14721                 cs->wm.need_postvbl_update = true;
14722                 dev_priv->display.optimize_watermarks(intel_state, cs);
14723
14724                 to_intel_crtc_state(crtc->state)->wm = cs->wm;
14725         }
14726
14727 put_state:
14728         drm_atomic_state_put(state);
14729 fail:
14730         drm_modeset_drop_locks(&ctx);
14731         drm_modeset_acquire_fini(&ctx);
14732 }
14733
14734 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
14735 {
14736         if (IS_GEN5(dev_priv)) {
14737                 u32 fdi_pll_clk =
14738                         I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
14739
14740                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
14741         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
14742                 dev_priv->fdi_pll_freq = 270000;
14743         } else {
14744                 return;
14745         }
14746
14747         DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
14748 }
14749
14750 int intel_modeset_init(struct drm_device *dev)
14751 {
14752         struct drm_i915_private *dev_priv = to_i915(dev);
14753         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14754         enum pipe pipe;
14755         struct intel_crtc *crtc;
14756
14757         dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14758
14759         drm_mode_config_init(dev);
14760
14761         dev->mode_config.min_width = 0;
14762         dev->mode_config.min_height = 0;
14763
14764         dev->mode_config.preferred_depth = 24;
14765         dev->mode_config.prefer_shadow = 1;
14766
14767         dev->mode_config.allow_fb_modifiers = true;
14768
14769         dev->mode_config.funcs = &intel_mode_funcs;
14770
14771         init_llist_head(&dev_priv->atomic_helper.free_list);
14772         INIT_WORK(&dev_priv->atomic_helper.free_work,
14773                   intel_atomic_helper_free_state_worker);
14774
14775         intel_init_quirks(dev);
14776
14777         intel_init_pm(dev_priv);
14778
14779         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14780                 return 0;
14781
14782         /*
14783          * There may be no VBT; and if the BIOS enabled SSC we can
14784          * just keep using it to avoid unnecessary flicker.  Whereas if the
14785          * BIOS isn't using it, don't assume it will work even if the VBT
14786          * indicates as much.
14787          */
14788         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14789                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14790                                             DREF_SSC1_ENABLE);
14791
14792                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14793                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14794                                      bios_lvds_use_ssc ? "en" : "dis",
14795                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14796                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14797                 }
14798         }
14799
14800         if (IS_GEN2(dev_priv)) {
14801                 dev->mode_config.max_width = 2048;
14802                 dev->mode_config.max_height = 2048;
14803         } else if (IS_GEN3(dev_priv)) {
14804                 dev->mode_config.max_width = 4096;
14805                 dev->mode_config.max_height = 4096;
14806         } else {
14807                 dev->mode_config.max_width = 8192;
14808                 dev->mode_config.max_height = 8192;
14809         }
14810
14811         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14812                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14813                 dev->mode_config.cursor_height = 1023;
14814         } else if (IS_GEN2(dev_priv)) {
14815                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14816                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14817         } else {
14818                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14819                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14820         }
14821
14822         dev->mode_config.fb_base = ggtt->gmadr.start;
14823
14824         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14825                       INTEL_INFO(dev_priv)->num_pipes,
14826                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14827
14828         for_each_pipe(dev_priv, pipe) {
14829                 int ret;
14830
14831                 ret = intel_crtc_init(dev_priv, pipe);
14832                 if (ret) {
14833                         drm_mode_config_cleanup(dev);
14834                         return ret;
14835                 }
14836         }
14837
14838         intel_shared_dpll_init(dev);
14839         intel_update_fdi_pll_freq(dev_priv);
14840
14841         intel_update_czclk(dev_priv);
14842         intel_modeset_init_hw(dev);
14843
14844         if (dev_priv->max_cdclk_freq == 0)
14845                 intel_update_max_cdclk(dev_priv);
14846
14847         /* Just disable it once at startup */
14848         i915_disable_vga(dev_priv);
14849         intel_setup_outputs(dev_priv);
14850
14851         drm_modeset_lock_all(dev);
14852         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14853         drm_modeset_unlock_all(dev);
14854
14855         for_each_intel_crtc(dev, crtc) {
14856                 struct intel_initial_plane_config plane_config = {};
14857
14858                 if (!crtc->active)
14859                         continue;
14860
14861                 /*
14862                  * Note that reserving the BIOS fb up front prevents us
14863                  * from stuffing other stolen allocations like the ring
14864                  * on top.  This prevents some ugliness at boot time, and
14865                  * can even allow for smooth boot transitions if the BIOS
14866                  * fb is large enough for the active pipe configuration.
14867                  */
14868                 dev_priv->display.get_initial_plane_config(crtc,
14869                                                            &plane_config);
14870
14871                 /*
14872                  * If the fb is shared between multiple heads, we'll
14873                  * just get the first one.
14874                  */
14875                 intel_find_initial_plane_obj(crtc, &plane_config);
14876         }
14877
14878         /*
14879          * Make sure hardware watermarks really match the state we read out.
14880          * Note that we need to do this after reconstructing the BIOS fb's
14881          * since the watermark calculation done here will use pstate->fb.
14882          */
14883         if (!HAS_GMCH_DISPLAY(dev_priv))
14884                 sanitize_watermarks(dev);
14885
14886         return 0;
14887 }
14888
14889 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14890 {
14891         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14892         /* 640x480@60Hz, ~25175 kHz */
14893         struct dpll clock = {
14894                 .m1 = 18,
14895                 .m2 = 7,
14896                 .p1 = 13,
14897                 .p2 = 4,
14898                 .n = 2,
14899         };
14900         u32 dpll, fp;
14901         int i;
14902
14903         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14904
14905         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14906                       pipe_name(pipe), clock.vco, clock.dot);
14907
14908         fp = i9xx_dpll_compute_fp(&clock);
14909         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14910                 DPLL_VGA_MODE_DIS |
14911                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14912                 PLL_P2_DIVIDE_BY_4 |
14913                 PLL_REF_INPUT_DREFCLK |
14914                 DPLL_VCO_ENABLE;
14915
14916         I915_WRITE(FP0(pipe), fp);
14917         I915_WRITE(FP1(pipe), fp);
14918
14919         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14920         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14921         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14922         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14923         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14924         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14925         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14926
14927         /*
14928          * Apparently we need to have VGA mode enabled prior to changing
14929          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14930          * dividers, even though the register value does change.
14931          */
14932         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14933         I915_WRITE(DPLL(pipe), dpll);
14934
14935         /* Wait for the clocks to stabilize. */
14936         POSTING_READ(DPLL(pipe));
14937         udelay(150);
14938
14939         /* The pixel multiplier can only be updated once the
14940          * DPLL is enabled and the clocks are stable.
14941          *
14942          * So write it again.
14943          */
14944         I915_WRITE(DPLL(pipe), dpll);
14945
14946         /* We do this three times for luck */
14947         for (i = 0; i < 3 ; i++) {
14948                 I915_WRITE(DPLL(pipe), dpll);
14949                 POSTING_READ(DPLL(pipe));
14950                 udelay(150); /* wait for warmup */
14951         }
14952
14953         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14954         POSTING_READ(PIPECONF(pipe));
14955
14956         intel_wait_for_pipe_scanline_moving(crtc);
14957 }
14958
14959 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14960 {
14961         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
14962
14963         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14964                       pipe_name(pipe));
14965
14966         WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
14967         WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
14968         WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
14969         WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
14970         WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
14971
14972         I915_WRITE(PIPECONF(pipe), 0);
14973         POSTING_READ(PIPECONF(pipe));
14974
14975         intel_wait_for_pipe_scanline_stopped(crtc);
14976
14977         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14978         POSTING_READ(DPLL(pipe));
14979 }
14980
14981 static bool intel_plane_mapping_ok(struct intel_crtc *crtc,
14982                                    struct intel_plane *plane)
14983 {
14984         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14985         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
14986         u32 val = I915_READ(DSPCNTR(i9xx_plane));
14987
14988         return (val & DISPLAY_PLANE_ENABLE) == 0 ||
14989                 (val & DISPPLANE_SEL_PIPE_MASK) == DISPPLANE_SEL_PIPE(crtc->pipe);
14990 }
14991
14992 static void
14993 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
14994 {
14995         struct intel_crtc *crtc;
14996
14997         if (INTEL_GEN(dev_priv) >= 4)
14998                 return;
14999
15000         for_each_intel_crtc(&dev_priv->drm, crtc) {
15001                 struct intel_plane *plane =
15002                         to_intel_plane(crtc->base.primary);
15003
15004                 if (intel_plane_mapping_ok(crtc, plane))
15005                         continue;
15006
15007                 DRM_DEBUG_KMS("%s attached to the wrong pipe, disabling plane\n",
15008                               plane->base.name);
15009                 intel_plane_disable_noatomic(crtc, plane);
15010         }
15011 }
15012
15013 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15014 {
15015         struct drm_device *dev = crtc->base.dev;
15016         struct intel_encoder *encoder;
15017
15018         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15019                 return true;
15020
15021         return false;
15022 }
15023
15024 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15025 {
15026         struct drm_device *dev = encoder->base.dev;
15027         struct intel_connector *connector;
15028
15029         for_each_connector_on_encoder(dev, &encoder->base, connector)
15030                 return connector;
15031
15032         return NULL;
15033 }
15034
15035 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15036                               enum pipe pch_transcoder)
15037 {
15038         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15039                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
15040 }
15041
15042 static void intel_sanitize_crtc(struct intel_crtc *crtc,
15043                                 struct drm_modeset_acquire_ctx *ctx)
15044 {
15045         struct drm_device *dev = crtc->base.dev;
15046         struct drm_i915_private *dev_priv = to_i915(dev);
15047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15048
15049         /* Clear any frame start delays used for debugging left by the BIOS */
15050         if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
15051                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15052
15053                 I915_WRITE(reg,
15054                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15055         }
15056
15057         /* restore vblank interrupts to correct state */
15058         drm_crtc_vblank_reset(&crtc->base);
15059         if (crtc->active) {
15060                 struct intel_plane *plane;
15061
15062                 drm_crtc_vblank_on(&crtc->base);
15063
15064                 /* Disable everything but the primary plane */
15065                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15066                         const struct intel_plane_state *plane_state =
15067                                 to_intel_plane_state(plane->base.state);
15068
15069                         if (plane_state->base.visible &&
15070                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
15071                                 intel_plane_disable_noatomic(crtc, plane);
15072                 }
15073         }
15074
15075         /* Adjust the state of the output pipe according to whether we
15076          * have active connectors/encoders. */
15077         if (crtc->active && !intel_crtc_has_encoders(crtc))
15078                 intel_crtc_disable_noatomic(&crtc->base, ctx);
15079
15080         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15081                 /*
15082                  * We start out with underrun reporting disabled to avoid races.
15083                  * For correct bookkeeping mark this on active crtcs.
15084                  *
15085                  * Also on gmch platforms we dont have any hardware bits to
15086                  * disable the underrun reporting. Which means we need to start
15087                  * out with underrun reporting disabled also on inactive pipes,
15088                  * since otherwise we'll complain about the garbage we read when
15089                  * e.g. coming up after runtime pm.
15090                  *
15091                  * No protection against concurrent access is required - at
15092                  * worst a fifo underrun happens which also sets this to false.
15093                  */
15094                 crtc->cpu_fifo_underrun_disabled = true;
15095                 /*
15096                  * We track the PCH trancoder underrun reporting state
15097                  * within the crtc. With crtc for pipe A housing the underrun
15098                  * reporting state for PCH transcoder A, crtc for pipe B housing
15099                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15100                  * and marking underrun reporting as disabled for the non-existing
15101                  * PCH transcoders B and C would prevent enabling the south
15102                  * error interrupt (see cpt_can_enable_serr_int()).
15103                  */
15104                 if (has_pch_trancoder(dev_priv, crtc->pipe))
15105                         crtc->pch_fifo_underrun_disabled = true;
15106         }
15107 }
15108
15109 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15110 {
15111         struct intel_connector *connector;
15112
15113         /* We need to check both for a crtc link (meaning that the
15114          * encoder is active and trying to read from a pipe) and the
15115          * pipe itself being active. */
15116         bool has_active_crtc = encoder->base.crtc &&
15117                 to_intel_crtc(encoder->base.crtc)->active;
15118
15119         connector = intel_encoder_find_connector(encoder);
15120         if (connector && !has_active_crtc) {
15121                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15122                               encoder->base.base.id,
15123                               encoder->base.name);
15124
15125                 /* Connector is active, but has no active pipe. This is
15126                  * fallout from our resume register restoring. Disable
15127                  * the encoder manually again. */
15128                 if (encoder->base.crtc) {
15129                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15130
15131                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15132                                       encoder->base.base.id,
15133                                       encoder->base.name);
15134                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15135                         if (encoder->post_disable)
15136                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15137                 }
15138                 encoder->base.crtc = NULL;
15139
15140                 /* Inconsistent output/port/pipe state happens presumably due to
15141                  * a bug in one of the get_hw_state functions. Or someplace else
15142                  * in our code, like the register restore mess on resume. Clamp
15143                  * things to off as a safer default. */
15144
15145                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15146                 connector->base.encoder = NULL;
15147         }
15148 }
15149
15150 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15151 {
15152         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15153
15154         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15155                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15156                 i915_disable_vga(dev_priv);
15157         }
15158 }
15159
15160 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15161 {
15162         /* This function can be called both from intel_modeset_setup_hw_state or
15163          * at a very early point in our resume sequence, where the power well
15164          * structures are not yet restored. Since this function is at a very
15165          * paranoid "someone might have enabled VGA while we were not looking"
15166          * level, just check if the power well is enabled instead of trying to
15167          * follow the "don't touch the power well if we don't need it" policy
15168          * the rest of the driver uses. */
15169         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15170                 return;
15171
15172         i915_redisable_vga_power_on(dev_priv);
15173
15174         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15175 }
15176
15177 /* FIXME read out full plane state for all planes */
15178 static void readout_plane_state(struct intel_crtc *crtc)
15179 {
15180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15181         struct intel_crtc_state *crtc_state =
15182                 to_intel_crtc_state(crtc->base.state);
15183         struct intel_plane *plane;
15184
15185         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
15186                 struct intel_plane_state *plane_state =
15187                         to_intel_plane_state(plane->base.state);
15188                 bool visible = plane->get_hw_state(plane);
15189
15190                 intel_set_plane_visible(crtc_state, plane_state, visible);
15191         }
15192 }
15193
15194 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15195 {
15196         struct drm_i915_private *dev_priv = to_i915(dev);
15197         enum pipe pipe;
15198         struct intel_crtc *crtc;
15199         struct intel_encoder *encoder;
15200         struct intel_connector *connector;
15201         struct drm_connector_list_iter conn_iter;
15202         int i;
15203
15204         dev_priv->active_crtcs = 0;
15205
15206         for_each_intel_crtc(dev, crtc) {
15207                 struct intel_crtc_state *crtc_state =
15208                         to_intel_crtc_state(crtc->base.state);
15209
15210                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15211                 memset(crtc_state, 0, sizeof(*crtc_state));
15212                 crtc_state->base.crtc = &crtc->base;
15213
15214                 crtc_state->base.active = crtc_state->base.enable =
15215                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15216
15217                 crtc->base.enabled = crtc_state->base.enable;
15218                 crtc->active = crtc_state->base.active;
15219
15220                 if (crtc_state->base.active)
15221                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15222
15223                 readout_plane_state(crtc);
15224
15225                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15226                               crtc->base.base.id, crtc->base.name,
15227                               enableddisabled(crtc_state->base.active));
15228         }
15229
15230         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15231                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15232
15233                 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
15234                                                         &pll->state.hw_state);
15235                 pll->state.crtc_mask = 0;
15236                 for_each_intel_crtc(dev, crtc) {
15237                         struct intel_crtc_state *crtc_state =
15238                                 to_intel_crtc_state(crtc->base.state);
15239
15240                         if (crtc_state->base.active &&
15241                             crtc_state->shared_dpll == pll)
15242                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15243                 }
15244                 pll->active_mask = pll->state.crtc_mask;
15245
15246                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15247                               pll->info->name, pll->state.crtc_mask, pll->on);
15248         }
15249
15250         for_each_intel_encoder(dev, encoder) {
15251                 pipe = 0;
15252
15253                 if (encoder->get_hw_state(encoder, &pipe)) {
15254                         struct intel_crtc_state *crtc_state;
15255
15256                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15257                         crtc_state = to_intel_crtc_state(crtc->base.state);
15258
15259                         encoder->base.crtc = &crtc->base;
15260                         encoder->get_config(encoder, crtc_state);
15261                 } else {
15262                         encoder->base.crtc = NULL;
15263                 }
15264
15265                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15266                               encoder->base.base.id, encoder->base.name,
15267                               enableddisabled(encoder->base.crtc),
15268                               pipe_name(pipe));
15269         }
15270
15271         drm_connector_list_iter_begin(dev, &conn_iter);
15272         for_each_intel_connector_iter(connector, &conn_iter) {
15273                 if (connector->get_hw_state(connector)) {
15274                         connector->base.dpms = DRM_MODE_DPMS_ON;
15275
15276                         encoder = connector->encoder;
15277                         connector->base.encoder = &encoder->base;
15278
15279                         if (encoder->base.crtc &&
15280                             encoder->base.crtc->state->active) {
15281                                 /*
15282                                  * This has to be done during hardware readout
15283                                  * because anything calling .crtc_disable may
15284                                  * rely on the connector_mask being accurate.
15285                                  */
15286                                 encoder->base.crtc->state->connector_mask |=
15287                                         1 << drm_connector_index(&connector->base);
15288                                 encoder->base.crtc->state->encoder_mask |=
15289                                         1 << drm_encoder_index(&encoder->base);
15290                         }
15291
15292                 } else {
15293                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15294                         connector->base.encoder = NULL;
15295                 }
15296                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15297                               connector->base.base.id, connector->base.name,
15298                               enableddisabled(connector->base.encoder));
15299         }
15300         drm_connector_list_iter_end(&conn_iter);
15301
15302         for_each_intel_crtc(dev, crtc) {
15303                 struct intel_crtc_state *crtc_state =
15304                         to_intel_crtc_state(crtc->base.state);
15305                 int min_cdclk = 0;
15306
15307                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15308                 if (crtc_state->base.active) {
15309                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15310                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15311                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15312
15313                         /*
15314                          * The initial mode needs to be set in order to keep
15315                          * the atomic core happy. It wants a valid mode if the
15316                          * crtc's enabled, so we do the above call.
15317                          *
15318                          * But we don't set all the derived state fully, hence
15319                          * set a flag to indicate that a full recalculation is
15320                          * needed on the next commit.
15321                          */
15322                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15323
15324                         intel_crtc_compute_pixel_rate(crtc_state);
15325
15326                         if (dev_priv->display.modeset_calc_cdclk) {
15327                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15328                                 if (WARN_ON(min_cdclk < 0))
15329                                         min_cdclk = 0;
15330                         }
15331
15332                         drm_calc_timestamping_constants(&crtc->base,
15333                                                         &crtc_state->base.adjusted_mode);
15334                         update_scanline_offset(crtc);
15335                 }
15336
15337                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15338                 dev_priv->min_voltage_level[crtc->pipe] =
15339                         crtc_state->min_voltage_level;
15340
15341                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15342         }
15343 }
15344
15345 static void
15346 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15347 {
15348         struct intel_encoder *encoder;
15349
15350         for_each_intel_encoder(&dev_priv->drm, encoder) {
15351                 u64 get_domains;
15352                 enum intel_display_power_domain domain;
15353
15354                 if (!encoder->get_power_domains)
15355                         continue;
15356
15357                 get_domains = encoder->get_power_domains(encoder);
15358                 for_each_power_domain(domain, get_domains)
15359                         intel_display_power_get(dev_priv, domain);
15360         }
15361 }
15362
15363 static void intel_early_display_was(struct drm_i915_private *dev_priv)
15364 {
15365         /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
15366         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
15367                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
15368                            DARBF_GATING_DIS);
15369
15370         if (IS_HASWELL(dev_priv)) {
15371                 /*
15372                  * WaRsPkgCStateDisplayPMReq:hsw
15373                  * System hang if this isn't done before disabling all planes!
15374                  */
15375                 I915_WRITE(CHICKEN_PAR1_1,
15376                            I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
15377         }
15378 }
15379
15380 /* Scan out the current hw modeset state,
15381  * and sanitizes it to the current state
15382  */
15383 static void
15384 intel_modeset_setup_hw_state(struct drm_device *dev,
15385                              struct drm_modeset_acquire_ctx *ctx)
15386 {
15387         struct drm_i915_private *dev_priv = to_i915(dev);
15388         enum pipe pipe;
15389         struct intel_crtc *crtc;
15390         struct intel_encoder *encoder;
15391         int i;
15392
15393         intel_early_display_was(dev_priv);
15394         intel_modeset_readout_hw_state(dev);
15395
15396         /* HW state is read out, now we need to sanitize this mess. */
15397         get_encoder_power_domains(dev_priv);
15398
15399         intel_sanitize_plane_mapping(dev_priv);
15400
15401         for_each_intel_encoder(dev, encoder) {
15402                 intel_sanitize_encoder(encoder);
15403         }
15404
15405         for_each_pipe(dev_priv, pipe) {
15406                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15407
15408                 intel_sanitize_crtc(crtc, ctx);
15409                 intel_dump_pipe_config(crtc, crtc->config,
15410                                        "[setup_hw_state]");
15411         }
15412
15413         intel_modeset_update_connector_atomic_state(dev);
15414
15415         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15416                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15417
15418                 if (!pll->on || pll->active_mask)
15419                         continue;
15420
15421                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
15422                               pll->info->name);
15423
15424                 pll->info->funcs->disable(dev_priv, pll);
15425                 pll->on = false;
15426         }
15427
15428         if (IS_G4X(dev_priv)) {
15429                 g4x_wm_get_hw_state(dev);
15430                 g4x_wm_sanitize(dev_priv);
15431         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15432                 vlv_wm_get_hw_state(dev);
15433                 vlv_wm_sanitize(dev_priv);
15434         } else if (INTEL_GEN(dev_priv) >= 9) {
15435                 skl_wm_get_hw_state(dev);
15436         } else if (HAS_PCH_SPLIT(dev_priv)) {
15437                 ilk_wm_get_hw_state(dev);
15438         }
15439
15440         for_each_intel_crtc(dev, crtc) {
15441                 u64 put_domains;
15442
15443                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15444                 if (WARN_ON(put_domains))
15445                         modeset_put_power_domains(dev_priv, put_domains);
15446         }
15447         intel_display_set_init_power(dev_priv, false);
15448
15449         intel_power_domains_verify_state(dev_priv);
15450
15451         intel_fbc_init_pipe_state(dev_priv);
15452 }
15453
15454 void intel_display_resume(struct drm_device *dev)
15455 {
15456         struct drm_i915_private *dev_priv = to_i915(dev);
15457         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15458         struct drm_modeset_acquire_ctx ctx;
15459         int ret;
15460
15461         dev_priv->modeset_restore_state = NULL;
15462         if (state)
15463                 state->acquire_ctx = &ctx;
15464
15465         drm_modeset_acquire_init(&ctx, 0);
15466
15467         while (1) {
15468                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15469                 if (ret != -EDEADLK)
15470                         break;
15471
15472                 drm_modeset_backoff(&ctx);
15473         }
15474
15475         if (!ret)
15476                 ret = __intel_display_resume(dev, state, &ctx);
15477
15478         intel_enable_ipc(dev_priv);
15479         drm_modeset_drop_locks(&ctx);
15480         drm_modeset_acquire_fini(&ctx);
15481
15482         if (ret)
15483                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15484         if (state)
15485                 drm_atomic_state_put(state);
15486 }
15487
15488 int intel_connector_register(struct drm_connector *connector)
15489 {
15490         struct intel_connector *intel_connector = to_intel_connector(connector);
15491         int ret;
15492
15493         ret = intel_backlight_device_register(intel_connector);
15494         if (ret)
15495                 goto err;
15496
15497         return 0;
15498
15499 err:
15500         return ret;
15501 }
15502
15503 void intel_connector_unregister(struct drm_connector *connector)
15504 {
15505         struct intel_connector *intel_connector = to_intel_connector(connector);
15506
15507         intel_backlight_device_unregister(intel_connector);
15508         intel_panel_destroy_backlight(connector);
15509 }
15510
15511 static void intel_hpd_poll_fini(struct drm_device *dev)
15512 {
15513         struct intel_connector *connector;
15514         struct drm_connector_list_iter conn_iter;
15515
15516         /* Kill all the work that may have been queued by hpd. */
15517         drm_connector_list_iter_begin(dev, &conn_iter);
15518         for_each_intel_connector_iter(connector, &conn_iter) {
15519                 if (connector->modeset_retry_work.func)
15520                         cancel_work_sync(&connector->modeset_retry_work);
15521                 if (connector->hdcp_shim) {
15522                         cancel_delayed_work_sync(&connector->hdcp_check_work);
15523                         cancel_work_sync(&connector->hdcp_prop_work);
15524                 }
15525         }
15526         drm_connector_list_iter_end(&conn_iter);
15527 }
15528
15529 void intel_modeset_cleanup(struct drm_device *dev)
15530 {
15531         struct drm_i915_private *dev_priv = to_i915(dev);
15532
15533         flush_work(&dev_priv->atomic_helper.free_work);
15534         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15535
15536         intel_disable_gt_powersave(dev_priv);
15537
15538         /*
15539          * Interrupts and polling as the first thing to avoid creating havoc.
15540          * Too much stuff here (turning of connectors, ...) would
15541          * experience fancy races otherwise.
15542          */
15543         intel_irq_uninstall(dev_priv);
15544
15545         /*
15546          * Due to the hpd irq storm handling the hotplug work can re-arm the
15547          * poll handlers. Hence disable polling after hpd handling is shut down.
15548          */
15549         intel_hpd_poll_fini(dev);
15550
15551         /* poll work can call into fbdev, hence clean that up afterwards */
15552         intel_fbdev_fini(dev_priv);
15553
15554         intel_unregister_dsm_handler();
15555
15556         intel_fbc_global_disable(dev_priv);
15557
15558         /* flush any delayed tasks or pending work */
15559         flush_scheduled_work();
15560
15561         drm_mode_config_cleanup(dev);
15562
15563         intel_cleanup_overlay(dev_priv);
15564
15565         intel_cleanup_gt_powersave(dev_priv);
15566
15567         intel_teardown_gmbus(dev_priv);
15568
15569         destroy_workqueue(dev_priv->modeset_wq);
15570 }
15571
15572 void intel_connector_attach_encoder(struct intel_connector *connector,
15573                                     struct intel_encoder *encoder)
15574 {
15575         connector->encoder = encoder;
15576         drm_mode_connector_attach_encoder(&connector->base,
15577                                           &encoder->base);
15578 }
15579
15580 /*
15581  * set vga decode state - true == enable VGA decode
15582  */
15583 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15584 {
15585         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15586         u16 gmch_ctrl;
15587
15588         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15589                 DRM_ERROR("failed to read control word\n");
15590                 return -EIO;
15591         }
15592
15593         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15594                 return 0;
15595
15596         if (state)
15597                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15598         else
15599                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15600
15601         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15602                 DRM_ERROR("failed to write control word\n");
15603                 return -EIO;
15604         }
15605
15606         return 0;
15607 }
15608
15609 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15610
15611 struct intel_display_error_state {
15612
15613         u32 power_well_driver;
15614
15615         int num_transcoders;
15616
15617         struct intel_cursor_error_state {
15618                 u32 control;
15619                 u32 position;
15620                 u32 base;
15621                 u32 size;
15622         } cursor[I915_MAX_PIPES];
15623
15624         struct intel_pipe_error_state {
15625                 bool power_domain_on;
15626                 u32 source;
15627                 u32 stat;
15628         } pipe[I915_MAX_PIPES];
15629
15630         struct intel_plane_error_state {
15631                 u32 control;
15632                 u32 stride;
15633                 u32 size;
15634                 u32 pos;
15635                 u32 addr;
15636                 u32 surface;
15637                 u32 tile_offset;
15638         } plane[I915_MAX_PIPES];
15639
15640         struct intel_transcoder_error_state {
15641                 bool power_domain_on;
15642                 enum transcoder cpu_transcoder;
15643
15644                 u32 conf;
15645
15646                 u32 htotal;
15647                 u32 hblank;
15648                 u32 hsync;
15649                 u32 vtotal;
15650                 u32 vblank;
15651                 u32 vsync;
15652         } transcoder[4];
15653 };
15654
15655 struct intel_display_error_state *
15656 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15657 {
15658         struct intel_display_error_state *error;
15659         int transcoders[] = {
15660                 TRANSCODER_A,
15661                 TRANSCODER_B,
15662                 TRANSCODER_C,
15663                 TRANSCODER_EDP,
15664         };
15665         int i;
15666
15667         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15668                 return NULL;
15669
15670         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15671         if (error == NULL)
15672                 return NULL;
15673
15674         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15675                 error->power_well_driver =
15676                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15677
15678         for_each_pipe(dev_priv, i) {
15679                 error->pipe[i].power_domain_on =
15680                         __intel_display_power_is_enabled(dev_priv,
15681                                                          POWER_DOMAIN_PIPE(i));
15682                 if (!error->pipe[i].power_domain_on)
15683                         continue;
15684
15685                 error->cursor[i].control = I915_READ(CURCNTR(i));
15686                 error->cursor[i].position = I915_READ(CURPOS(i));
15687                 error->cursor[i].base = I915_READ(CURBASE(i));
15688
15689                 error->plane[i].control = I915_READ(DSPCNTR(i));
15690                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15691                 if (INTEL_GEN(dev_priv) <= 3) {
15692                         error->plane[i].size = I915_READ(DSPSIZE(i));
15693                         error->plane[i].pos = I915_READ(DSPPOS(i));
15694                 }
15695                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15696                         error->plane[i].addr = I915_READ(DSPADDR(i));
15697                 if (INTEL_GEN(dev_priv) >= 4) {
15698                         error->plane[i].surface = I915_READ(DSPSURF(i));
15699                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15700                 }
15701
15702                 error->pipe[i].source = I915_READ(PIPESRC(i));
15703
15704                 if (HAS_GMCH_DISPLAY(dev_priv))
15705                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15706         }
15707
15708         /* Note: this does not include DSI transcoders. */
15709         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15710         if (HAS_DDI(dev_priv))
15711                 error->num_transcoders++; /* Account for eDP. */
15712
15713         for (i = 0; i < error->num_transcoders; i++) {
15714                 enum transcoder cpu_transcoder = transcoders[i];
15715
15716                 error->transcoder[i].power_domain_on =
15717                         __intel_display_power_is_enabled(dev_priv,
15718                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15719                 if (!error->transcoder[i].power_domain_on)
15720                         continue;
15721
15722                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15723
15724                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15725                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15726                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15727                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15728                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15729                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15730                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15731         }
15732
15733         return error;
15734 }
15735
15736 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15737
15738 void
15739 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15740                                 struct intel_display_error_state *error)
15741 {
15742         struct drm_i915_private *dev_priv = m->i915;
15743         int i;
15744
15745         if (!error)
15746                 return;
15747
15748         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15749         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15750                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15751                            error->power_well_driver);
15752         for_each_pipe(dev_priv, i) {
15753                 err_printf(m, "Pipe [%d]:\n", i);
15754                 err_printf(m, "  Power: %s\n",
15755                            onoff(error->pipe[i].power_domain_on));
15756                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15757                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15758
15759                 err_printf(m, "Plane [%d]:\n", i);
15760                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15761                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15762                 if (INTEL_GEN(dev_priv) <= 3) {
15763                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15764                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15765                 }
15766                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15767                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15768                 if (INTEL_GEN(dev_priv) >= 4) {
15769                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15770                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15771                 }
15772
15773                 err_printf(m, "Cursor [%d]:\n", i);
15774                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15775                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15776                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15777         }
15778
15779         for (i = 0; i < error->num_transcoders; i++) {
15780                 err_printf(m, "CPU transcoder: %s\n",
15781                            transcoder_name(error->transcoder[i].cpu_transcoder));
15782                 err_printf(m, "  Power: %s\n",
15783                            onoff(error->transcoder[i].power_domain_on));
15784                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15785                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15786                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15787                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15788                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15789                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15790                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15791         }
15792 }
15793
15794 #endif