2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "intel_display.h"
33 struct drm_i915_private;
35 /* Keep in gen based order, and chronological order within a gen */
37 INTEL_PLATFORM_UNINITIALIZED = 0,
80 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
81 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
82 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
83 INTEL_PPGTT_FULL_4LVL,
86 #define DEV_INFO_FOR_EACH_FLAG(func) \
89 func(is_alpha_support); \
90 /* Keep has_* in alphabetical order */ \
91 func(has_64bit_reloc); \
92 func(gpu_reset_clobbers_display); \
93 func(has_reset_engine); \
99 func(has_logical_ring_contexts); \
100 func(has_logical_ring_elsq); \
101 func(has_logical_ring_preemption); \
102 func(has_pooled_eu); \
105 func(has_runtime_pm); \
107 func(has_coherent_ggtt); \
108 func(unfenced_needs_alignment); \
109 func(hws_needs_physical);
111 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
112 /* Keep in alphabetical order */ \
113 func(cursor_needs_physical); \
123 func(overlay_needs_physical); \
126 #define GEN_MAX_SLICES (6) /* CNL upper bound */
127 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
129 struct sseu_dev_info {
131 u8 subslice_mask[GEN_MAX_SLICES];
135 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
138 u8 has_subslice_pg:1;
141 /* Topology fields */
144 u8 max_eus_per_subslice;
146 /* We don't have more than 8 eus per subslice at the moment and as we
147 * store eus enabled using bits, no need to multiply by eus per
150 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
153 typedef u8 intel_ring_mask_t;
155 struct intel_device_info {
159 u8 gt; /* GT number, 0 if undefined */
160 intel_ring_mask_t ring_mask; /* Rings supported by the HW */
162 enum intel_platform platform;
165 enum intel_ppgtt ppgtt;
166 unsigned int page_sizes; /* page sizes supported by the HW */
168 u32 display_mmio_offset;
172 #define DEFINE_FLAG(name) u8 name:1
173 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
177 #define DEFINE_FLAG(name) u8 name:1
178 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
182 u16 ddb_size; /* in blocks */
184 /* Register offsets for the various display pipes and transcoders */
185 int pipe_offsets[I915_MAX_TRANSCODERS];
186 int trans_offsets[I915_MAX_TRANSCODERS];
187 int cursor_offsets[I915_MAX_PIPES];
190 u16 degamma_lut_size;
192 u32 degamma_lut_tests;
197 struct intel_runtime_info {
200 u8 num_sprites[I915_MAX_PIPES];
201 u8 num_scalers[I915_MAX_PIPES];
205 /* Slice/subslice/EU info */
206 struct sseu_dev_info sseu;
208 u32 cs_timestamp_frequency_khz;
210 /* Enabled (not fused off) media engine bitmasks. */
214 /* Media engine access to SFC per instance */
218 struct intel_driver_caps {
219 unsigned int scheduler;
220 bool has_logical_contexts:1;
223 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
225 unsigned int i, total = 0;
227 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
228 total += hweight8(sseu->subslice_mask[i]);
233 static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
234 int slice, int subslice)
236 int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
238 int slice_stride = sseu->max_subslices * subslice_stride;
240 return slice * slice_stride + subslice * subslice_stride;
243 static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
244 int slice, int subslice)
246 int i, offset = sseu_eu_idx(sseu, slice, subslice);
250 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
251 eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
258 static inline void sseu_set_eus(struct sseu_dev_info *sseu,
259 int slice, int subslice, u16 eu_mask)
261 int i, offset = sseu_eu_idx(sseu, slice, subslice);
264 i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
265 sseu->eu_mask[offset + i] =
266 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
270 const char *intel_platform_name(enum intel_platform platform);
272 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
273 void intel_device_info_dump_flags(const struct intel_device_info *info,
274 struct drm_printer *p);
275 void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
276 struct drm_printer *p);
277 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
278 struct drm_printer *p);
280 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
282 void intel_driver_caps_print(const struct intel_driver_caps *caps,
283 struct drm_printer *p);