2 * Copyright © 2014-2017 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "intel_step.h"
32 #include "gt/intel_engine_types.h"
33 #include "gt/intel_context_types.h"
34 #include "gt/intel_sseu.h"
36 #include "gem/i915_gem_object_types.h"
39 struct drm_i915_private;
40 struct intel_gt_definition;
42 /* Keep in gen based order, and chronological order within a gen */
44 INTEL_PLATFORM_UNINITIALIZED = 0,
98 * Subplatform bits share the same namespace per parent platform. In other words
99 * it is fine for the same bit to be used on multiple parent platforms.
102 #define INTEL_SUBPLATFORM_BITS (3)
103 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
105 /* HSW/BDW/SKL/KBL/CFL */
106 #define INTEL_SUBPLATFORM_ULT (0)
107 #define INTEL_SUBPLATFORM_ULX (1)
110 #define INTEL_SUBPLATFORM_PORTF (0)
113 #define INTEL_SUBPLATFORM_UY (0)
116 #define INTEL_SUBPLATFORM_G10 0
117 #define INTEL_SUBPLATFORM_G11 1
118 #define INTEL_SUBPLATFORM_G12 2
121 #define INTEL_SUBPLATFORM_RPL 0
125 * As #define INTEL_SUBPLATFORM_RPL 0 will apply
126 * here too, SUBPLATFORM_N will have different
129 #define INTEL_SUBPLATFORM_N 1
130 #define INTEL_SUBPLATFORM_RPLU 2
132 enum intel_ppgtt_type {
133 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
134 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
135 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
138 #define DEV_INFO_FOR_EACH_FLAG(func) \
141 func(require_force_probe); \
143 /* Keep has_* in alphabetical order */ \
144 func(has_64bit_reloc); \
145 func(has_64k_pages); \
146 func(gpu_reset_clobbers_display); \
147 func(has_reset_engine); \
148 func(has_3d_pipeline); \
149 func(has_flat_ccs); \
150 func(has_global_mocs); \
153 func(has_heci_pxp); \
154 func(has_heci_gscfi); \
155 func(has_guc_deprivilege); \
156 func(has_guc_tlb_invalidation); \
157 func(has_l3_ccs_read); \
160 func(has_logical_ring_contexts); \
161 func(has_logical_ring_elsq); \
162 func(has_media_ratio_mode); \
163 func(has_mslice_steering); \
164 func(has_oa_bpc_reporting); \
165 func(has_oa_slice_contrib_limits); \
167 func(has_one_eu_per_fuse_bit); \
172 func(has_runtime_pm); \
174 func(has_coherent_ggtt); \
175 func(tuning_thread_rr_after_dep); \
176 func(unfenced_needs_alignment); \
177 func(hws_needs_physical);
179 struct intel_ip_version {
185 struct intel_runtime_info {
187 * Single "graphics" IP version that represents
188 * render, compute and copy behavior.
191 struct intel_ip_version ip;
194 struct intel_ip_version ip;
198 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
199 * single runtime conditionals, and also to provide groundwork for
200 * future per platform, or per SKU build optimizations.
202 * Array can be extended when necessary if the corresponding
203 * BUILD_BUG_ON is hit.
205 u32 platform_mask[2];
211 struct intel_step_info step;
213 unsigned int page_sizes; /* page sizes supported by the HW */
215 enum intel_ppgtt_type ppgtt_type;
216 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
221 struct intel_device_info {
222 enum intel_platform platform;
224 unsigned int dma_mask_size; /* available DMA address bits */
226 const struct intel_gt_definition *extra_gt_list;
228 u8 gt; /* GT number, 0 if undefined */
230 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
231 u32 memory_regions; /* regions supported by the HW */
233 #define DEFINE_FLAG(name) u8 name:1
234 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
238 * Initial runtime info. Do not access outside of i915_driver_create().
240 const struct intel_runtime_info __runtime;
242 u32 cachelevel_to_pat[I915_MAX_CACHE_LEVEL];
246 struct intel_driver_caps {
247 unsigned int scheduler;
248 bool has_logical_contexts:1;
251 const char *intel_platform_name(enum intel_platform platform);
253 void intel_device_info_driver_create(struct drm_i915_private *i915, u16 device_id,
254 const struct intel_device_info *match_info);
255 void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv);
256 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
258 void intel_device_info_print(const struct intel_device_info *info,
259 const struct intel_runtime_info *runtime,
260 struct drm_printer *p);
262 void intel_driver_caps_print(const struct intel_driver_caps *caps,
263 struct drm_printer *p);