2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <drm/drm_print.h>
26 #include <drm/i915_pciids.h>
28 #include "display/intel_cdclk.h"
29 #include "display/intel_de.h"
30 #include "intel_device_info.h"
33 #define PLATFORM_NAME(x) [INTEL_##x] = #x
34 static const char * const platform_names[] = {
40 PLATFORM_NAME(I915GM),
42 PLATFORM_NAME(I945GM),
44 PLATFORM_NAME(PINEVIEW),
46 PLATFORM_NAME(I965GM),
49 PLATFORM_NAME(IRONLAKE),
50 PLATFORM_NAME(SANDYBRIDGE),
51 PLATFORM_NAME(IVYBRIDGE),
52 PLATFORM_NAME(VALLEYVIEW),
53 PLATFORM_NAME(HASWELL),
54 PLATFORM_NAME(BROADWELL),
55 PLATFORM_NAME(CHERRYVIEW),
56 PLATFORM_NAME(SKYLAKE),
57 PLATFORM_NAME(BROXTON),
58 PLATFORM_NAME(KABYLAKE),
59 PLATFORM_NAME(GEMINILAKE),
60 PLATFORM_NAME(COFFEELAKE),
61 PLATFORM_NAME(COMETLAKE),
62 PLATFORM_NAME(CANNONLAKE),
63 PLATFORM_NAME(ICELAKE),
64 PLATFORM_NAME(ELKHARTLAKE),
65 PLATFORM_NAME(JASPERLAKE),
66 PLATFORM_NAME(TIGERLAKE),
67 PLATFORM_NAME(ROCKETLAKE),
72 const char *intel_platform_name(enum intel_platform platform)
74 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
76 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
77 platform_names[platform] == NULL))
80 return platform_names[platform];
83 static const char *iommu_name(void)
85 const char *msg = "n/a";
87 #ifdef CONFIG_INTEL_IOMMU
88 msg = enableddisabled(intel_iommu_gfx_mapped);
94 void intel_device_info_print_static(const struct intel_device_info *info,
95 struct drm_printer *p)
97 drm_printf(p, "gen: %d\n", info->gen);
98 drm_printf(p, "gt: %d\n", info->gt);
99 drm_printf(p, "iommu: %s\n", iommu_name());
100 drm_printf(p, "memory-regions: %x\n", info->memory_regions);
101 drm_printf(p, "page-sizes: %x\n", info->page_sizes);
102 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
103 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
104 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
105 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
107 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
108 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
111 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
112 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
116 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
117 struct drm_printer *p)
119 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
122 #undef INTEL_VGA_DEVICE
123 #define INTEL_VGA_DEVICE(id, info) (id)
125 static const u16 subplatform_ult_ids[] = {
126 INTEL_HSW_ULT_GT1_IDS(0),
127 INTEL_HSW_ULT_GT2_IDS(0),
128 INTEL_HSW_ULT_GT3_IDS(0),
129 INTEL_BDW_ULT_GT1_IDS(0),
130 INTEL_BDW_ULT_GT2_IDS(0),
131 INTEL_BDW_ULT_GT3_IDS(0),
132 INTEL_BDW_ULT_RSVD_IDS(0),
133 INTEL_SKL_ULT_GT1_IDS(0),
134 INTEL_SKL_ULT_GT2_IDS(0),
135 INTEL_SKL_ULT_GT3_IDS(0),
136 INTEL_KBL_ULT_GT1_IDS(0),
137 INTEL_KBL_ULT_GT2_IDS(0),
138 INTEL_KBL_ULT_GT3_IDS(0),
139 INTEL_CFL_U_GT2_IDS(0),
140 INTEL_CFL_U_GT3_IDS(0),
141 INTEL_WHL_U_GT1_IDS(0),
142 INTEL_WHL_U_GT2_IDS(0),
143 INTEL_WHL_U_GT3_IDS(0),
144 INTEL_CML_U_GT1_IDS(0),
145 INTEL_CML_U_GT2_IDS(0),
148 static const u16 subplatform_ulx_ids[] = {
149 INTEL_HSW_ULX_GT1_IDS(0),
150 INTEL_HSW_ULX_GT2_IDS(0),
151 INTEL_BDW_ULX_GT1_IDS(0),
152 INTEL_BDW_ULX_GT2_IDS(0),
153 INTEL_BDW_ULX_GT3_IDS(0),
154 INTEL_BDW_ULX_RSVD_IDS(0),
155 INTEL_SKL_ULX_GT1_IDS(0),
156 INTEL_SKL_ULX_GT2_IDS(0),
157 INTEL_KBL_ULX_GT1_IDS(0),
158 INTEL_KBL_ULX_GT2_IDS(0),
159 INTEL_AML_KBL_GT2_IDS(0),
160 INTEL_AML_CFL_GT2_IDS(0),
163 static const u16 subplatform_portf_ids[] = {
164 INTEL_CNL_PORT_F_IDS(0),
165 INTEL_ICL_PORT_F_IDS(0),
168 static bool find_devid(u16 id, const u16 *p, unsigned int num)
170 for (; num; num--, p++) {
178 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
180 const struct intel_device_info *info = INTEL_INFO(i915);
181 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
182 const unsigned int pi = __platform_mask_index(rinfo, info->platform);
183 const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
184 u16 devid = INTEL_DEVID(i915);
187 /* Make sure IS_<platform> checks are working. */
188 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
190 /* Find and mark subplatform bits based on the PCI device id. */
191 if (find_devid(devid, subplatform_ult_ids,
192 ARRAY_SIZE(subplatform_ult_ids))) {
193 mask = BIT(INTEL_SUBPLATFORM_ULT);
194 } else if (find_devid(devid, subplatform_ulx_ids,
195 ARRAY_SIZE(subplatform_ulx_ids))) {
196 mask = BIT(INTEL_SUBPLATFORM_ULX);
197 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
198 /* ULX machines are also considered ULT. */
199 mask |= BIT(INTEL_SUBPLATFORM_ULT);
201 } else if (find_devid(devid, subplatform_portf_ids,
202 ARRAY_SIZE(subplatform_portf_ids))) {
203 mask = BIT(INTEL_SUBPLATFORM_PORTF);
206 if (IS_TIGERLAKE(i915)) {
207 struct pci_dev *root, *pdev = i915->drm.pdev;
209 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
211 drm_WARN_ON(&i915->drm, mask);
212 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
215 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
216 case TGL_ROOT_DEVICE_SKU_ULX:
217 mask = BIT(INTEL_SUBPLATFORM_ULX);
219 case TGL_ROOT_DEVICE_SKU_ULT:
220 mask = BIT(INTEL_SUBPLATFORM_ULT);
225 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
227 RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
231 * intel_device_info_runtime_init - initialize runtime info
232 * @dev_priv: the i915 device
234 * Determine various intel_device_info fields at runtime.
236 * Use it when either:
237 * - it's judged too laborious to fill n static structures with the limit
238 * when a simple if statement does the job,
239 * - run-time checks (eg read fuse/strap registers) are needed.
241 * This function needs to be called:
242 * - after the MMIO has been setup as we are reading registers,
243 * - after the PCH has been detected,
244 * - before the first usage of the fields it can tweak.
246 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
248 struct intel_device_info *info = mkwrite_device_info(dev_priv);
249 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
252 if (INTEL_GEN(dev_priv) >= 10) {
253 for_each_pipe(dev_priv, pipe)
254 runtime->num_scalers[pipe] = 2;
255 } else if (IS_GEN(dev_priv, 9)) {
256 runtime->num_scalers[PIPE_A] = 2;
257 runtime->num_scalers[PIPE_B] = 2;
258 runtime->num_scalers[PIPE_C] = 1;
261 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
263 if (IS_ROCKETLAKE(dev_priv))
264 for_each_pipe(dev_priv, pipe)
265 runtime->num_sprites[pipe] = 4;
266 else if (INTEL_GEN(dev_priv) >= 11)
267 for_each_pipe(dev_priv, pipe)
268 runtime->num_sprites[pipe] = 6;
269 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
270 for_each_pipe(dev_priv, pipe)
271 runtime->num_sprites[pipe] = 3;
272 else if (IS_BROXTON(dev_priv)) {
274 * Skylake and Broxton currently don't expose the topmost plane as its
275 * use is exclusive with the legacy cursor and we only want to expose
276 * one of those, not both. Until we can safely expose the topmost plane
277 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
278 * we don't expose the topmost plane at all to prevent ABI breakage
282 runtime->num_sprites[PIPE_A] = 2;
283 runtime->num_sprites[PIPE_B] = 2;
284 runtime->num_sprites[PIPE_C] = 1;
285 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
286 for_each_pipe(dev_priv, pipe)
287 runtime->num_sprites[pipe] = 2;
288 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
289 for_each_pipe(dev_priv, pipe)
290 runtime->num_sprites[pipe] = 1;
293 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
294 HAS_PCH_SPLIT(dev_priv)) {
295 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
296 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
299 * SFUSE_STRAP is supposed to have a bit signalling the display
300 * is fused off. Unfortunately it seems that, at least in
301 * certain cases, fused off display means that PCH display
302 * reads don't land anywhere. In that case, we read 0s.
304 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
305 * should be set when taking over after the firmware.
307 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
308 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
309 (HAS_PCH_CPT(dev_priv) &&
310 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
311 drm_info(&dev_priv->drm,
312 "Display fused off, disabling\n");
314 info->cpu_transcoder_mask = 0;
315 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
316 drm_info(&dev_priv->drm, "PipeC fused off\n");
317 info->pipe_mask &= ~BIT(PIPE_C);
318 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
320 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
321 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
323 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
324 info->pipe_mask &= ~BIT(PIPE_A);
325 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
327 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
328 info->pipe_mask &= ~BIT(PIPE_B);
329 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
331 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
332 info->pipe_mask &= ~BIT(PIPE_C);
333 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
335 if (INTEL_GEN(dev_priv) >= 12 &&
336 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
337 info->pipe_mask &= ~BIT(PIPE_D);
338 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
341 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
342 info->display.has_hdcp = 0;
344 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
345 info->display.has_fbc = 0;
347 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
348 info->display.has_csr = 0;
350 if (INTEL_GEN(dev_priv) >= 10 &&
351 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
352 info->display.has_dsc = 0;
355 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
356 drm_info(&dev_priv->drm,
357 "Disabling ppGTT for VT-d support\n");
358 info->ppgtt_type = INTEL_PPGTT_NONE;
361 runtime->rawclk_freq = intel_read_rawclk(dev_priv);
362 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
364 if (!HAS_DISPLAY(dev_priv)) {
365 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
367 memset(&info->display, 0, sizeof(info->display));
368 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
369 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
373 void intel_driver_caps_print(const struct intel_driver_caps *caps,
374 struct drm_printer *p)
376 drm_printf(p, "Has logical contexts? %s\n",
377 yesno(caps->has_logical_contexts));
378 drm_printf(p, "scheduler: %x\n", caps->scheduler);