drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26
  27 #include "i915_drv.h"
  28
  29 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  30 static const char * const platform_names[] = {
  31         PLATFORM_NAME(I830),
  32         PLATFORM_NAME(I845G),
  33         PLATFORM_NAME(I85X),
  34         PLATFORM_NAME(I865G),
  35         PLATFORM_NAME(I915G),
  36         PLATFORM_NAME(I915GM),
  37         PLATFORM_NAME(I945G),
  38         PLATFORM_NAME(I945GM),
  39         PLATFORM_NAME(G33),
  40         PLATFORM_NAME(PINEVIEW),
  41         PLATFORM_NAME(I965G),
  42         PLATFORM_NAME(I965GM),
  43         PLATFORM_NAME(G45),
  44         PLATFORM_NAME(GM45),
  45         PLATFORM_NAME(IRONLAKE),
  46         PLATFORM_NAME(SANDYBRIDGE),
  47         PLATFORM_NAME(IVYBRIDGE),
  48         PLATFORM_NAME(VALLEYVIEW),
  49         PLATFORM_NAME(HASWELL),
  50         PLATFORM_NAME(BROADWELL),
  51         PLATFORM_NAME(CHERRYVIEW),
  52         PLATFORM_NAME(SKYLAKE),
  53         PLATFORM_NAME(BROXTON),
  54         PLATFORM_NAME(KABYLAKE),
  55         PLATFORM_NAME(GEMINILAKE),
  56         PLATFORM_NAME(COFFEELAKE),
  57         PLATFORM_NAME(CANNONLAKE),
  58 };
  59 #undef PLATFORM_NAME
  60
  61 const char *intel_platform_name(enum intel_platform platform)
  62 {
  63         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  64
  65         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  66                          platform_names[platform] == NULL))
  67                 return "<unknown>";
  68
  69         return platform_names[platform];
  70 }
  71
  72 void intel_device_info_dump_flags(const struct intel_device_info *info,
  73                                   struct drm_printer *p)
  74 {
  75 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
  76         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  77 #undef PRINT_FLAG
  78 }
  79
  80 void intel_device_info_dump(struct drm_i915_private *dev_priv)
  81 {
  82         const struct intel_device_info *info = &dev_priv->info;
  83
  84         DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
  85                          intel_platform_name(info->platform),
  86                          info->gen,
  87                          dev_priv->drm.pdev->device,
  88                          dev_priv->drm.pdev->revision);
  89
  90         if (drm_debug & DRM_UT_DRIVER) {
  91                 struct drm_printer p = drm_debug_printer("i915 device info: ");
  92
  93                 intel_device_info_dump_flags(info, &p);
  94         }
  95 }
  96
  97 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
  98 {
  99         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 100         const u32 fuse2 = I915_READ(GEN8_FUSE2);
 101
 102         sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
 103                             GEN10_F2_S_ENA_SHIFT;
 104         sseu->subslice_mask = (1 << 4) - 1;
 105         sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
 106                                  GEN10_F2_SS_DIS_SHIFT);
 107
 108         sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
 109         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
 110         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
 111         sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
 112                                      GEN10_EU_DIS_SS_MASK));
 113
 114         /*
 115          * CNL is expected to always have a uniform distribution
 116          * of EU across subslices with the exception that any one
 117          * EU in any one subslice may be fused off for die
 118          * recovery.
 119          */
 120         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 121                                 DIV_ROUND_UP(sseu->eu_total,
 122                                              sseu_subslice_total(sseu)) : 0;
 123
 124         /* No restrictions on Power Gating */
 125         sseu->has_slice_pg = 1;
 126         sseu->has_subslice_pg = 1;
 127         sseu->has_eu_pg = 1;
 128 }
 129
 130 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 131 {
 132         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 133         u32 fuse, eu_dis;
 134
 135         fuse = I915_READ(CHV_FUSE_GT);
 136
 137         sseu->slice_mask = BIT(0);
 138
 139         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 140                 sseu->subslice_mask |= BIT(0);
 141                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 142                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 143                 sseu->eu_total += 8 - hweight32(eu_dis);
 144         }
 145
 146         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 147                 sseu->subslice_mask |= BIT(1);
 148                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 149                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 150                 sseu->eu_total += 8 - hweight32(eu_dis);
 151         }
 152
 153         /*
 154          * CHV expected to always have a uniform distribution of EU
 155          * across subslices.
 156         */
 157         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 158                                 sseu->eu_total / sseu_subslice_total(sseu) :
 159                                 0;
 160         /*
 161          * CHV supports subslice power gating on devices with more than
 162          * one subslice, and supports EU power gating on devices with
 163          * more than one EU pair per subslice.
 164         */
 165         sseu->has_slice_pg = 0;
 166         sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
 167         sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
 168 }
 169
 170 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 171 {
 172         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 173         struct sseu_dev_info *sseu = &info->sseu;
 174         int s_max = 3, ss_max = 4, eu_max = 8;
 175         int s, ss;
 176         u32 fuse2, eu_disable;
 177         u8 eu_mask = 0xff;
 178
 179         fuse2 = I915_READ(GEN8_FUSE2);
 180         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 181
 182         /*
 183          * The subslice disable field is global, i.e. it applies
 184          * to each of the enabled slices.
 185         */
 186         sseu->subslice_mask = (1 << ss_max) - 1;
 187         sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
 188                                  GEN9_F2_SS_DIS_SHIFT);
 189
 190         /*
 191          * Iterate through enabled slices and subslices to
 192          * count the total enabled EU.
 193         */
 194         for (s = 0; s < s_max; s++) {
 195                 if (!(sseu->slice_mask & BIT(s)))
 196                         /* skip disabled slice */
 197                         continue;
 198
 199                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 200                 for (ss = 0; ss < ss_max; ss++) {
 201                         int eu_per_ss;
 202
 203                         if (!(sseu->subslice_mask & BIT(ss)))
 204                                 /* skip disabled subslice */
 205                                 continue;
 206
 207                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 208                                                       eu_mask);
 209
 210                         /*
 211                          * Record which subslice(s) has(have) 7 EUs. we
 212                          * can tune the hash used to spread work among
 213                          * subslices if they are unbalanced.
 214                          */
 215                         if (eu_per_ss == 7)
 216                                 sseu->subslice_7eu[s] |= BIT(ss);
 217
 218                         sseu->eu_total += eu_per_ss;
 219                 }
 220         }
 221
 222         /*
 223          * SKL is expected to always have a uniform distribution
 224          * of EU across subslices with the exception that any one
 225          * EU in any one subslice may be fused off for die
 226          * recovery. BXT is expected to be perfectly uniform in EU
 227          * distribution.
 228         */
 229         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 230                                 DIV_ROUND_UP(sseu->eu_total,
 231                                              sseu_subslice_total(sseu)) : 0;
 232         /*
 233          * SKL+ supports slice power gating on devices with more than
 234          * one slice, and supports EU power gating on devices with
 235          * more than one EU pair per subslice. BXT+ supports subslice
 236          * power gating on devices with more than one subslice, and
 237          * supports EU power gating on devices with more than one EU
 238          * pair per subslice.
 239         */
 240         sseu->has_slice_pg =
 241                 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
 242         sseu->has_subslice_pg =
 243                 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 244         sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 245
 246         if (IS_GEN9_LP(dev_priv)) {
 247 #define IS_SS_DISABLED(ss)      (!(sseu->subslice_mask & BIT(ss)))
 248                 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
 249
 250                 sseu->min_eu_in_pool = 0;
 251                 if (info->has_pooled_eu) {
 252                         if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
 253                                 sseu->min_eu_in_pool = 3;
 254                         else if (IS_SS_DISABLED(1))
 255                                 sseu->min_eu_in_pool = 6;
 256                         else
 257                                 sseu->min_eu_in_pool = 9;
 258                 }
 259 #undef IS_SS_DISABLED
 260         }
 261 }
 262
 263 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 264 {
 265         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 266         const int s_max = 3, ss_max = 3, eu_max = 8;
 267         int s, ss;
 268         u32 fuse2, eu_disable[3]; /* s_max */
 269
 270         fuse2 = I915_READ(GEN8_FUSE2);
 271         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 272         /*
 273          * The subslice disable field is global, i.e. it applies
 274          * to each of the enabled slices.
 275          */
 276         sseu->subslice_mask = GENMASK(ss_max - 1, 0);
 277         sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
 278                                  GEN8_F2_SS_DIS_SHIFT);
 279
 280         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 281         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 282                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 283                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 284         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 285                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 286                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 287
 288         /*
 289          * Iterate through enabled slices and subslices to
 290          * count the total enabled EU.
 291          */
 292         for (s = 0; s < s_max; s++) {
 293                 if (!(sseu->slice_mask & BIT(s)))
 294                         /* skip disabled slice */
 295                         continue;
 296
 297                 for (ss = 0; ss < ss_max; ss++) {
 298                         u32 n_disabled;
 299
 300                         if (!(sseu->subslice_mask & BIT(ss)))
 301                                 /* skip disabled subslice */
 302                                 continue;
 303
 304                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 305
 306                         /*
 307                          * Record which subslices have 7 EUs.
 308                          */
 309                         if (eu_max - n_disabled == 7)
 310                                 sseu->subslice_7eu[s] |= 1 << ss;
 311
 312                         sseu->eu_total += eu_max - n_disabled;
 313                 }
 314         }
 315
 316         /*
 317          * BDW is expected to always have a uniform distribution of EU across
 318          * subslices with the exception that any one EU in any one subslice may
 319          * be fused off for die recovery.
 320          */
 321         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 322                                 DIV_ROUND_UP(sseu->eu_total,
 323                                              sseu_subslice_total(sseu)) : 0;
 324
 325         /*
 326          * BDW supports slice power gating on devices with more than
 327          * one slice.
 328          */
 329         sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
 330         sseu->has_subslice_pg = 0;
 331         sseu->has_eu_pg = 0;
 332 }
 333
 334 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 335 {
 336         u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
 337         u32 base_freq, frac_freq;
 338
 339         base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
 340                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
 341         base_freq *= 1000;
 342
 343         frac_freq = ((ts_override &
 344                       GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
 345                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
 346         frac_freq = 1000 / (frac_freq + 1);
 347
 348         return base_freq + frac_freq;
 349 }
 350
 351 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 352 {
 353         u32 f12_5_mhz = 12500;
 354         u32 f19_2_mhz = 19200;
 355         u32 f24_mhz = 24000;
 356
 357         if (INTEL_GEN(dev_priv) <= 4) {
 358                 /* PRMs say:
 359                  *
 360                  *     "The value in this register increments once every 16
 361                  *      hclks." (through the “Clocking Configuration”
 362                  *      (“CLKCFG”) MCHBAR register)
 363                  */
 364                 return dev_priv->rawclk_freq / 16;
 365         } else if (INTEL_GEN(dev_priv) <= 8) {
 366                 /* PRMs say:
 367                  *
 368                  *     "The PCU TSC counts 10ns increments; this timestamp
 369                  *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
 370                  *      rolling over every 1.5 hours).
 371                  */
 372                 return f12_5_mhz;
 373         } else if (INTEL_GEN(dev_priv) <= 9) {
 374                 u32 ctc_reg = I915_READ(CTC_MODE);
 375                 u32 freq = 0;
 376
 377                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 378                         freq = read_reference_ts_freq(dev_priv);
 379                 } else {
 380                         freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
 381
 382                         /* Now figure out how the command stream's timestamp
 383                          * register increments from this frequency (it might
 384                          * increment only every few clock cycle).
 385                          */
 386                         freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
 387                                       CTC_SHIFT_PARAMETER_SHIFT);
 388                 }
 389
 390                 return freq;
 391         } else if (INTEL_GEN(dev_priv) <= 10) {
 392                 u32 ctc_reg = I915_READ(CTC_MODE);
 393                 u32 freq = 0;
 394                 u32 rpm_config_reg = 0;
 395
 396                 /* First figure out the reference frequency. There are 2 ways
 397                  * we can compute the frequency, either through the
 398                  * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
 399                  * tells us which one we should use.
 400                  */
 401                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 402                         freq = read_reference_ts_freq(dev_priv);
 403                 } else {
 404                         u32 crystal_clock;
 405
 406                         rpm_config_reg = I915_READ(RPM_CONFIG0);
 407                         crystal_clock = (rpm_config_reg &
 408                                          GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 409                                 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
 410                         switch (crystal_clock) {
 411                         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
 412                                 freq = f19_2_mhz;
 413                                 break;
 414                         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
 415                                 freq = f24_mhz;
 416                                 break;
 417                         }
 418
 419                         /* Now figure out how the command stream's timestamp
 420                          * register increments from this frequency (it might
 421                          * increment only every few clock cycle).
 422                          */
 423                         freq >>= 3 - ((rpm_config_reg &
 424                                        GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
 425                                       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
 426                 }
 427
 428                 return freq;
 429         }
 430
 431         MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
 432         return 0;
 433 }
 434
 435 /*
 436  * Determine various intel_device_info fields at runtime.
 437  *
 438  * Use it when either:
 439  *   - it's judged too laborious to fill n static structures with the limit
 440  *     when a simple if statement does the job,
 441  *   - run-time checks (eg read fuse/strap registers) are needed.
 442  *
 443  * This function needs to be called:
 444  *   - after the MMIO has been setup as we are reading registers,
 445  *   - after the PCH has been detected,
 446  *   - before the first usage of the fields it can tweak.
 447  */
 448 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 449 {
 450         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 451         enum pipe pipe;
 452
 453         if (INTEL_GEN(dev_priv) >= 10) {
 454                 for_each_pipe(dev_priv, pipe)
 455                         info->num_scalers[pipe] = 2;
 456         } else if (INTEL_GEN(dev_priv) == 9) {
 457                 info->num_scalers[PIPE_A] = 2;
 458                 info->num_scalers[PIPE_B] = 2;
 459                 info->num_scalers[PIPE_C] = 1;
 460         }
 461
 462         /*
 463          * Skylake and Broxton currently don't expose the topmost plane as its
 464          * use is exclusive with the legacy cursor and we only want to expose
 465          * one of those, not both. Until we can safely expose the topmost plane
 466          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 467          * we don't expose the topmost plane at all to prevent ABI breakage
 468          * down the line.
 469          */
 470         if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
 471                 for_each_pipe(dev_priv, pipe)
 472                         info->num_sprites[pipe] = 3;
 473         else if (IS_BROXTON(dev_priv)) {
 474                 info->num_sprites[PIPE_A] = 2;
 475                 info->num_sprites[PIPE_B] = 2;
 476                 info->num_sprites[PIPE_C] = 1;
 477         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 478                 for_each_pipe(dev_priv, pipe)
 479                         info->num_sprites[pipe] = 2;
 480         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 481                 for_each_pipe(dev_priv, pipe)
 482                         info->num_sprites[pipe] = 1;
 483         }
 484
 485         if (i915_modparams.disable_display) {
 486                 DRM_INFO("Display disabled (module parameter)\n");
 487                 info->num_pipes = 0;
 488         } else if (info->num_pipes > 0 &&
 489                    (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
 490                    HAS_PCH_SPLIT(dev_priv)) {
 491                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 492                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 493
 494                 /*
 495                  * SFUSE_STRAP is supposed to have a bit signalling the display
 496                  * is fused off. Unfortunately it seems that, at least in
 497                  * certain cases, fused off display means that PCH display
 498                  * reads don't land anywhere. In that case, we read 0s.
 499                  *
 500                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 501                  * should be set when taking over after the firmware.
 502                  */
 503                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 504                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 505                     (HAS_PCH_CPT(dev_priv) &&
 506                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 507                         DRM_INFO("Display fused off, disabling\n");
 508                         info->num_pipes = 0;
 509                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 510                         DRM_INFO("PipeC fused off\n");
 511                         info->num_pipes -= 1;
 512                 }
 513         } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
 514                 u32 dfsm = I915_READ(SKL_DFSM);
 515                 u8 disabled_mask = 0;
 516                 bool invalid;
 517                 int num_bits;
 518
 519                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
 520                         disabled_mask |= BIT(PIPE_A);
 521                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
 522                         disabled_mask |= BIT(PIPE_B);
 523                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 524                         disabled_mask |= BIT(PIPE_C);
 525
 526                 num_bits = hweight8(disabled_mask);
 527
 528                 switch (disabled_mask) {
 529                 case BIT(PIPE_A):
 530                 case BIT(PIPE_B):
 531                 case BIT(PIPE_A) | BIT(PIPE_B):
 532                 case BIT(PIPE_A) | BIT(PIPE_C):
 533                         invalid = true;
 534                         break;
 535                 default:
 536                         invalid = false;
 537                 }
 538
 539                 if (num_bits > info->num_pipes || invalid)
 540                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
 541                                   disabled_mask);
 542                 else
 543                         info->num_pipes -= num_bits;
 544         }
 545
 546         /* Initialize slice/subslice/EU info */
 547         if (IS_CHERRYVIEW(dev_priv))
 548                 cherryview_sseu_info_init(dev_priv);
 549         else if (IS_BROADWELL(dev_priv))
 550                 broadwell_sseu_info_init(dev_priv);
 551         else if (INTEL_GEN(dev_priv) == 9)
 552                 gen9_sseu_info_init(dev_priv);
 553         else if (INTEL_GEN(dev_priv) >= 10)
 554                 gen10_sseu_info_init(dev_priv);
 555
 556         /* Initialize command stream timestamp frequency */
 557         info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 558
 559         DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 560         DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
 561         DRM_DEBUG_DRIVER("subslice total: %u\n",
 562                          sseu_subslice_total(&info->sseu));
 563         DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
 564         DRM_DEBUG_DRIVER("subslice per slice: %u\n",
 565                          hweight8(info->sseu.subslice_mask));
 566         DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
 567         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
 568         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 569                          info->sseu.has_slice_pg ? "y" : "n");
 570         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 571                          info->sseu.has_subslice_pg ? "y" : "n");
 572         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 573                          info->sseu.has_eu_pg ? "y" : "n");
 574         DRM_DEBUG_DRIVER("CS timestamp frequency: %u kHz\n",
 575                          info->cs_timestamp_frequency_khz);
 576 }