2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <drm/drm_print.h>
27 #include "intel_device_info.h"
30 #define PLATFORM_NAME(x) [INTEL_##x] = #x
31 static const char * const platform_names[] = {
37 PLATFORM_NAME(I915GM),
39 PLATFORM_NAME(I945GM),
41 PLATFORM_NAME(PINEVIEW),
43 PLATFORM_NAME(I965GM),
46 PLATFORM_NAME(IRONLAKE),
47 PLATFORM_NAME(SANDYBRIDGE),
48 PLATFORM_NAME(IVYBRIDGE),
49 PLATFORM_NAME(VALLEYVIEW),
50 PLATFORM_NAME(HASWELL),
51 PLATFORM_NAME(BROADWELL),
52 PLATFORM_NAME(CHERRYVIEW),
53 PLATFORM_NAME(SKYLAKE),
54 PLATFORM_NAME(BROXTON),
55 PLATFORM_NAME(KABYLAKE),
56 PLATFORM_NAME(GEMINILAKE),
57 PLATFORM_NAME(COFFEELAKE),
58 PLATFORM_NAME(CANNONLAKE),
59 PLATFORM_NAME(ICELAKE),
63 const char *intel_platform_name(enum intel_platform platform)
65 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
67 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
68 platform_names[platform] == NULL))
71 return platform_names[platform];
74 void intel_device_info_dump_flags(const struct intel_device_info *info,
75 struct drm_printer *p)
77 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
78 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
81 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
82 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
86 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
90 drm_printf(p, "slice total: %u, mask=%04x\n",
91 hweight8(sseu->slice_mask), sseu->slice_mask);
92 drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
93 for (s = 0; s < sseu->max_slices; s++) {
94 drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
95 s, hweight8(sseu->subslice_mask[s]),
96 sseu->subslice_mask[s]);
98 drm_printf(p, "EU total: %u\n", sseu->eu_total);
99 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
100 drm_printf(p, "has slice power gating: %s\n",
101 yesno(sseu->has_slice_pg));
102 drm_printf(p, "has subslice power gating: %s\n",
103 yesno(sseu->has_subslice_pg));
104 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
107 void intel_device_info_dump_runtime(const struct intel_device_info *info,
108 struct drm_printer *p)
110 sseu_dump(&info->sseu, p);
112 drm_printf(p, "CS timestamp frequency: %u kHz\n",
113 info->cs_timestamp_frequency_khz);
116 void intel_device_info_dump(const struct intel_device_info *info,
117 struct drm_printer *p)
119 struct drm_i915_private *dev_priv =
120 container_of(info, struct drm_i915_private, info);
122 drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
123 INTEL_DEVID(dev_priv),
124 INTEL_REVID(dev_priv),
125 intel_platform_name(info->platform),
128 intel_device_info_dump_flags(info, p);
131 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
132 struct drm_printer *p)
136 if (sseu->max_slices == 0) {
137 drm_printf(p, "Unavailable\n");
141 for (s = 0; s < sseu->max_slices; s++) {
142 drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
143 s, hweight8(sseu->subslice_mask[s]),
144 sseu->subslice_mask[s]);
146 for (ss = 0; ss < sseu->max_subslices; ss++) {
147 u16 enabled_eus = sseu_get_eus(sseu, s, ss);
149 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n",
150 ss, hweight16(enabled_eus), enabled_eus);
155 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
159 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
160 total += hweight8(sseu->eu_mask[i]);
165 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
167 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
169 u32 ss_en, ss_en_mask;
173 sseu->max_slices = 1;
174 sseu->max_subslices = 8;
175 sseu->max_eus_per_subslice = 8;
177 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
178 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
179 ss_en_mask = BIT(sseu->max_subslices) - 1;
180 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
182 for (s = 0; s < sseu->max_slices; s++) {
184 int ss_idx = sseu->max_subslices * s;
187 sseu->slice_mask |= BIT(s);
188 sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
189 for (ss = 0; ss < sseu->max_subslices; ss++) {
190 if (sseu->subslice_mask[s] & BIT(ss))
191 sseu_set_eus(sseu, s, ss, eu_en);
195 sseu->eu_per_subslice = hweight8(eu_en);
196 sseu->eu_total = compute_eu_total(sseu);
198 /* ICL has no power gating restrictions. */
199 sseu->has_slice_pg = 1;
200 sseu->has_subslice_pg = 1;
204 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
206 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
207 const u32 fuse2 = I915_READ(GEN8_FUSE2);
209 const int eu_mask = 0xff;
210 u32 subslice_mask, eu_en;
212 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
213 GEN10_F2_S_ENA_SHIFT;
214 sseu->max_slices = 6;
215 sseu->max_subslices = 4;
216 sseu->max_eus_per_subslice = 8;
218 subslice_mask = (1 << 4) - 1;
219 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
220 GEN10_F2_SS_DIS_SHIFT);
223 * Slice0 can have up to 3 subslices, but there are only 2 in
226 sseu->subslice_mask[0] = subslice_mask;
227 for (s = 1; s < sseu->max_slices; s++)
228 sseu->subslice_mask[s] = subslice_mask & 0x3;
231 eu_en = ~I915_READ(GEN8_EU_DISABLE0);
232 for (ss = 0; ss < sseu->max_subslices; ss++)
233 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
235 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
236 eu_en = ~I915_READ(GEN8_EU_DISABLE1);
237 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
239 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
240 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
242 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
243 eu_en = ~I915_READ(GEN8_EU_DISABLE2);
244 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
246 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
247 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
249 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
250 eu_en = ~I915_READ(GEN10_EU_DISABLE3);
251 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
253 /* Do a second pass where we mark the subslices disabled if all their
256 for (s = 0; s < sseu->max_slices; s++) {
257 for (ss = 0; ss < sseu->max_subslices; ss++) {
258 if (sseu_get_eus(sseu, s, ss) == 0)
259 sseu->subslice_mask[s] &= ~BIT(ss);
263 sseu->eu_total = compute_eu_total(sseu);
266 * CNL is expected to always have a uniform distribution
267 * of EU across subslices with the exception that any one
268 * EU in any one subslice may be fused off for die
271 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
272 DIV_ROUND_UP(sseu->eu_total,
273 sseu_subslice_total(sseu)) : 0;
275 /* No restrictions on Power Gating */
276 sseu->has_slice_pg = 1;
277 sseu->has_subslice_pg = 1;
281 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
283 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
286 fuse = I915_READ(CHV_FUSE_GT);
288 sseu->slice_mask = BIT(0);
289 sseu->max_slices = 1;
290 sseu->max_subslices = 2;
291 sseu->max_eus_per_subslice = 8;
293 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
295 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
296 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
297 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
298 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
300 sseu->subslice_mask[0] |= BIT(0);
301 sseu_set_eus(sseu, 0, 0, ~disabled_mask);
304 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
306 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
307 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
308 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
309 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
311 sseu->subslice_mask[0] |= BIT(1);
312 sseu_set_eus(sseu, 0, 1, ~disabled_mask);
315 sseu->eu_total = compute_eu_total(sseu);
318 * CHV expected to always have a uniform distribution of EU
321 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
322 sseu->eu_total / sseu_subslice_total(sseu) :
325 * CHV supports subslice power gating on devices with more than
326 * one subslice, and supports EU power gating on devices with
327 * more than one EU pair per subslice.
329 sseu->has_slice_pg = 0;
330 sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
331 sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
334 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
336 struct intel_device_info *info = mkwrite_device_info(dev_priv);
337 struct sseu_dev_info *sseu = &info->sseu;
339 u32 fuse2, eu_disable, subslice_mask;
340 const u8 eu_mask = 0xff;
342 fuse2 = I915_READ(GEN8_FUSE2);
343 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
345 /* BXT has a single slice and at most 3 subslices. */
346 sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
347 sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
348 sseu->max_eus_per_subslice = 8;
351 * The subslice disable field is global, i.e. it applies
352 * to each of the enabled slices.
354 subslice_mask = (1 << sseu->max_subslices) - 1;
355 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
356 GEN9_F2_SS_DIS_SHIFT);
359 * Iterate through enabled slices and subslices to
360 * count the total enabled EU.
362 for (s = 0; s < sseu->max_slices; s++) {
363 if (!(sseu->slice_mask & BIT(s)))
364 /* skip disabled slice */
367 sseu->subslice_mask[s] = subslice_mask;
369 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
370 for (ss = 0; ss < sseu->max_subslices; ss++) {
374 if (!(sseu->subslice_mask[s] & BIT(ss)))
375 /* skip disabled subslice */
378 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
380 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
382 eu_per_ss = sseu->max_eus_per_subslice -
383 hweight8(eu_disabled_mask);
386 * Record which subslice(s) has(have) 7 EUs. we
387 * can tune the hash used to spread work among
388 * subslices if they are unbalanced.
391 sseu->subslice_7eu[s] |= BIT(ss);
395 sseu->eu_total = compute_eu_total(sseu);
398 * SKL is expected to always have a uniform distribution
399 * of EU across subslices with the exception that any one
400 * EU in any one subslice may be fused off for die
401 * recovery. BXT is expected to be perfectly uniform in EU
404 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
405 DIV_ROUND_UP(sseu->eu_total,
406 sseu_subslice_total(sseu)) : 0;
408 * SKL+ supports slice power gating on devices with more than
409 * one slice, and supports EU power gating on devices with
410 * more than one EU pair per subslice. BXT+ supports subslice
411 * power gating on devices with more than one subslice, and
412 * supports EU power gating on devices with more than one EU
416 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
417 sseu->has_subslice_pg =
418 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
419 sseu->has_eu_pg = sseu->eu_per_subslice > 2;
421 if (IS_GEN9_LP(dev_priv)) {
422 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
423 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
425 sseu->min_eu_in_pool = 0;
426 if (info->has_pooled_eu) {
427 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
428 sseu->min_eu_in_pool = 3;
429 else if (IS_SS_DISABLED(1))
430 sseu->min_eu_in_pool = 6;
432 sseu->min_eu_in_pool = 9;
434 #undef IS_SS_DISABLED
438 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
440 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
442 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
444 fuse2 = I915_READ(GEN8_FUSE2);
445 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
446 sseu->max_slices = 3;
447 sseu->max_subslices = 3;
448 sseu->max_eus_per_subslice = 8;
451 * The subslice disable field is global, i.e. it applies
452 * to each of the enabled slices.
454 subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
455 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
456 GEN8_F2_SS_DIS_SHIFT);
458 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
459 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
460 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
461 (32 - GEN8_EU_DIS0_S1_SHIFT));
462 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
463 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
464 (32 - GEN8_EU_DIS1_S2_SHIFT));
467 * Iterate through enabled slices and subslices to
468 * count the total enabled EU.
470 for (s = 0; s < sseu->max_slices; s++) {
471 if (!(sseu->slice_mask & BIT(s)))
472 /* skip disabled slice */
475 sseu->subslice_mask[s] = subslice_mask;
477 for (ss = 0; ss < sseu->max_subslices; ss++) {
481 if (!(sseu->subslice_mask[s] & BIT(ss)))
482 /* skip disabled subslice */
486 eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
488 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
490 n_disabled = hweight8(eu_disabled_mask);
493 * Record which subslices have 7 EUs.
495 if (sseu->max_eus_per_subslice - n_disabled == 7)
496 sseu->subslice_7eu[s] |= 1 << ss;
500 sseu->eu_total = compute_eu_total(sseu);
503 * BDW is expected to always have a uniform distribution of EU across
504 * subslices with the exception that any one EU in any one subslice may
505 * be fused off for die recovery.
507 sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
508 DIV_ROUND_UP(sseu->eu_total,
509 sseu_subslice_total(sseu)) : 0;
512 * BDW supports slice power gating on devices with more than
515 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
516 sseu->has_subslice_pg = 0;
520 static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
522 struct intel_device_info *info = mkwrite_device_info(dev_priv);
523 struct sseu_dev_info *sseu = &info->sseu;
528 * There isn't a register to tell us how many slices/subslices. We
529 * work off the PCI-ids here.
533 MISSING_CASE(info->gt);
536 sseu->slice_mask = BIT(0);
537 sseu->subslice_mask[0] = BIT(0);
540 sseu->slice_mask = BIT(0);
541 sseu->subslice_mask[0] = BIT(0) | BIT(1);
544 sseu->slice_mask = BIT(0) | BIT(1);
545 sseu->subslice_mask[0] = BIT(0) | BIT(1);
546 sseu->subslice_mask[1] = BIT(0) | BIT(1);
550 sseu->max_slices = hweight8(sseu->slice_mask);
551 sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
553 fuse1 = I915_READ(HSW_PAVP_FUSE1);
554 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
556 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
557 HSW_F1_EU_DIS_SHIFT);
559 case HSW_F1_EU_DIS_10EUS:
560 sseu->eu_per_subslice = 10;
562 case HSW_F1_EU_DIS_8EUS:
563 sseu->eu_per_subslice = 8;
565 case HSW_F1_EU_DIS_6EUS:
566 sseu->eu_per_subslice = 6;
569 sseu->max_eus_per_subslice = sseu->eu_per_subslice;
571 for (s = 0; s < sseu->max_slices; s++) {
572 for (ss = 0; ss < sseu->max_subslices; ss++) {
573 sseu_set_eus(sseu, s, ss,
574 (1UL << sseu->eu_per_subslice) - 1);
578 sseu->eu_total = compute_eu_total(sseu);
580 /* No powergating for you. */
581 sseu->has_slice_pg = 0;
582 sseu->has_subslice_pg = 0;
586 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
588 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
589 u32 base_freq, frac_freq;
591 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
592 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
595 frac_freq = ((ts_override &
596 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
597 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
598 frac_freq = 1000 / (frac_freq + 1);
600 return base_freq + frac_freq;
603 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
606 u32 f19_2_mhz = 19200;
608 u32 crystal_clock = (rpm_config_reg &
609 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
610 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
612 switch (crystal_clock) {
613 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
615 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
618 MISSING_CASE(crystal_clock);
623 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
626 u32 f19_2_mhz = 19200;
629 u32 f38_4_mhz = 38400;
630 u32 crystal_clock = (rpm_config_reg &
631 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
632 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
634 switch (crystal_clock) {
635 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
637 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
639 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
641 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
644 MISSING_CASE(crystal_clock);
649 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
651 u32 f12_5_mhz = 12500;
652 u32 f19_2_mhz = 19200;
655 if (INTEL_GEN(dev_priv) <= 4) {
658 * "The value in this register increments once every 16
659 * hclks." (through the “Clocking Configuration”
660 * (“CLKCFG”) MCHBAR register)
662 return dev_priv->rawclk_freq / 16;
663 } else if (INTEL_GEN(dev_priv) <= 8) {
666 * "The PCU TSC counts 10ns increments; this timestamp
667 * reflects bits 38:3 of the TSC (i.e. 80ns granularity,
668 * rolling over every 1.5 hours).
671 } else if (INTEL_GEN(dev_priv) <= 9) {
672 u32 ctc_reg = I915_READ(CTC_MODE);
675 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
676 freq = read_reference_ts_freq(dev_priv);
678 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
680 /* Now figure out how the command stream's timestamp
681 * register increments from this frequency (it might
682 * increment only every few clock cycle).
684 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
685 CTC_SHIFT_PARAMETER_SHIFT);
689 } else if (INTEL_GEN(dev_priv) <= 11) {
690 u32 ctc_reg = I915_READ(CTC_MODE);
693 /* First figure out the reference frequency. There are 2 ways
694 * we can compute the frequency, either through the
695 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
696 * tells us which one we should use.
698 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
699 freq = read_reference_ts_freq(dev_priv);
701 u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
703 if (INTEL_GEN(dev_priv) <= 10)
704 freq = gen10_get_crystal_clock_freq(dev_priv,
707 freq = gen11_get_crystal_clock_freq(dev_priv,
710 /* Now figure out how the command stream's timestamp
711 * register increments from this frequency (it might
712 * increment only every few clock cycle).
714 freq >>= 3 - ((rpm_config_reg &
715 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
716 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
722 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
727 * intel_device_info_runtime_init - initialize runtime info
728 * @info: intel device info struct
730 * Determine various intel_device_info fields at runtime.
732 * Use it when either:
733 * - it's judged too laborious to fill n static structures with the limit
734 * when a simple if statement does the job,
735 * - run-time checks (eg read fuse/strap registers) are needed.
737 * This function needs to be called:
738 * - after the MMIO has been setup as we are reading registers,
739 * - after the PCH has been detected,
740 * - before the first usage of the fields it can tweak.
742 void intel_device_info_runtime_init(struct intel_device_info *info)
744 struct drm_i915_private *dev_priv =
745 container_of(info, struct drm_i915_private, info);
748 if (INTEL_GEN(dev_priv) >= 10) {
749 for_each_pipe(dev_priv, pipe)
750 info->num_scalers[pipe] = 2;
751 } else if (IS_GEN9(dev_priv)) {
752 info->num_scalers[PIPE_A] = 2;
753 info->num_scalers[PIPE_B] = 2;
754 info->num_scalers[PIPE_C] = 1;
757 BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
759 if (IS_GEN11(dev_priv))
760 for_each_pipe(dev_priv, pipe)
761 info->num_sprites[pipe] = 6;
762 else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
763 for_each_pipe(dev_priv, pipe)
764 info->num_sprites[pipe] = 3;
765 else if (IS_BROXTON(dev_priv)) {
767 * Skylake and Broxton currently don't expose the topmost plane as its
768 * use is exclusive with the legacy cursor and we only want to expose
769 * one of those, not both. Until we can safely expose the topmost plane
770 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
771 * we don't expose the topmost plane at all to prevent ABI breakage
775 info->num_sprites[PIPE_A] = 2;
776 info->num_sprites[PIPE_B] = 2;
777 info->num_sprites[PIPE_C] = 1;
778 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
779 for_each_pipe(dev_priv, pipe)
780 info->num_sprites[pipe] = 2;
781 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
782 for_each_pipe(dev_priv, pipe)
783 info->num_sprites[pipe] = 1;
786 if (i915_modparams.disable_display) {
787 DRM_INFO("Display disabled (module parameter)\n");
789 } else if (HAS_DISPLAY(dev_priv) &&
790 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
791 HAS_PCH_SPLIT(dev_priv)) {
792 u32 fuse_strap = I915_READ(FUSE_STRAP);
793 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
796 * SFUSE_STRAP is supposed to have a bit signalling the display
797 * is fused off. Unfortunately it seems that, at least in
798 * certain cases, fused off display means that PCH display
799 * reads don't land anywhere. In that case, we read 0s.
801 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
802 * should be set when taking over after the firmware.
804 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
805 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
806 (HAS_PCH_CPT(dev_priv) &&
807 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
808 DRM_INFO("Display fused off, disabling\n");
810 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
811 DRM_INFO("PipeC fused off\n");
812 info->num_pipes -= 1;
814 } else if (HAS_DISPLAY(dev_priv) && IS_GEN9(dev_priv)) {
815 u32 dfsm = I915_READ(SKL_DFSM);
816 u8 disabled_mask = 0;
820 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
821 disabled_mask |= BIT(PIPE_A);
822 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
823 disabled_mask |= BIT(PIPE_B);
824 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
825 disabled_mask |= BIT(PIPE_C);
827 num_bits = hweight8(disabled_mask);
829 switch (disabled_mask) {
832 case BIT(PIPE_A) | BIT(PIPE_B):
833 case BIT(PIPE_A) | BIT(PIPE_C):
840 if (num_bits > info->num_pipes || invalid)
841 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
844 info->num_pipes -= num_bits;
847 /* Initialize slice/subslice/EU info */
848 if (IS_HASWELL(dev_priv))
849 haswell_sseu_info_init(dev_priv);
850 else if (IS_CHERRYVIEW(dev_priv))
851 cherryview_sseu_info_init(dev_priv);
852 else if (IS_BROADWELL(dev_priv))
853 broadwell_sseu_info_init(dev_priv);
854 else if (IS_GEN9(dev_priv))
855 gen9_sseu_info_init(dev_priv);
856 else if (IS_GEN10(dev_priv))
857 gen10_sseu_info_init(dev_priv);
858 else if (INTEL_GEN(dev_priv) >= 11)
859 gen11_sseu_info_init(dev_priv);
861 if (IS_GEN6(dev_priv) && intel_vtd_active()) {
862 DRM_INFO("Disabling ppGTT for VT-d support\n");
863 info->ppgtt = INTEL_PPGTT_NONE;
866 /* Initialize command stream timestamp frequency */
867 info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
870 void intel_driver_caps_print(const struct intel_driver_caps *caps,
871 struct drm_printer *p)
873 drm_printf(p, "Has logical contexts? %s\n",
874 yesno(caps->has_logical_contexts));
875 drm_printf(p, "scheduler: %x\n", caps->scheduler);
879 * Determine which engines are fused off in our particular hardware. Since the
880 * fuse register is in the blitter powerwell, we need forcewake to be ready at
881 * this point (but later we need to prune the forcewake domains for engines that
882 * are indeed fused off).
884 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
886 struct intel_device_info *info = mkwrite_device_info(dev_priv);
890 if (INTEL_GEN(dev_priv) < 11)
893 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
895 info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
896 info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
897 GEN11_GT_VEBOX_DISABLE_SHIFT;
899 DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable);
900 for (i = 0; i < I915_MAX_VCS; i++) {
901 if (!HAS_ENGINE(dev_priv, _VCS(i)))
904 if (!(BIT(i) & info->vdbox_enable)) {
905 info->ring_mask &= ~ENGINE_MASK(_VCS(i));
906 DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
910 DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable);
911 for (i = 0; i < I915_MAX_VECS; i++) {
912 if (!HAS_ENGINE(dev_priv, _VECS(i)))
915 if (!(BIT(i) & info->vebox_enable)) {
916 info->ring_mask &= ~ENGINE_MASK(_VECS(i));
917 DRM_DEBUG_DRIVER("vecs%u fused off\n", i);