drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26 #include <drm/i915_pciids.h>
  27
  28 #include "display/intel_cdclk.h"
  29 #include "display/intel_de.h"
  30 #include "intel_device_info.h"
  31 #include "i915_drv.h"
  32
  33 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  34 static const char * const platform_names[] = {
  35         PLATFORM_NAME(I830),
  36         PLATFORM_NAME(I845G),
  37         PLATFORM_NAME(I85X),
  38         PLATFORM_NAME(I865G),
  39         PLATFORM_NAME(I915G),
  40         PLATFORM_NAME(I915GM),
  41         PLATFORM_NAME(I945G),
  42         PLATFORM_NAME(I945GM),
  43         PLATFORM_NAME(G33),
  44         PLATFORM_NAME(PINEVIEW),
  45         PLATFORM_NAME(I965G),
  46         PLATFORM_NAME(I965GM),
  47         PLATFORM_NAME(G45),
  48         PLATFORM_NAME(GM45),
  49         PLATFORM_NAME(IRONLAKE),
  50         PLATFORM_NAME(SANDYBRIDGE),
  51         PLATFORM_NAME(IVYBRIDGE),
  52         PLATFORM_NAME(VALLEYVIEW),
  53         PLATFORM_NAME(HASWELL),
  54         PLATFORM_NAME(BROADWELL),
  55         PLATFORM_NAME(CHERRYVIEW),
  56         PLATFORM_NAME(SKYLAKE),
  57         PLATFORM_NAME(BROXTON),
  58         PLATFORM_NAME(KABYLAKE),
  59         PLATFORM_NAME(GEMINILAKE),
  60         PLATFORM_NAME(COFFEELAKE),
  61         PLATFORM_NAME(COMETLAKE),
  62         PLATFORM_NAME(CANNONLAKE),
  63         PLATFORM_NAME(ICELAKE),
  64         PLATFORM_NAME(ELKHARTLAKE),
  65         PLATFORM_NAME(JASPERLAKE),
  66         PLATFORM_NAME(TIGERLAKE),
  67         PLATFORM_NAME(ROCKETLAKE),
  68         PLATFORM_NAME(DG1),
  69         PLATFORM_NAME(ALDERLAKE_S),
  70         PLATFORM_NAME(ALDERLAKE_P),
  71         PLATFORM_NAME(XEHPSDV),
  72         PLATFORM_NAME(DG2),
  73 };
  74 #undef PLATFORM_NAME
  75
  76 const char *intel_platform_name(enum intel_platform platform)
  77 {
  78         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  79
  80         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  81                          platform_names[platform] == NULL))
  82                 return "<unknown>";
  83
  84         return platform_names[platform];
  85 }
  86
  87 static const char *iommu_name(void)
  88 {
  89         const char *msg = "n/a";
  90
  91 #ifdef CONFIG_INTEL_IOMMU
  92         msg = enableddisabled(intel_iommu_gfx_mapped);
  93 #endif
  94
  95         return msg;
  96 }
  97
  98 void intel_device_info_print_static(const struct intel_device_info *info,
  99                                     struct drm_printer *p)
 100 {
 101         if (info->graphics_rel)
 102                 drm_printf(p, "graphics version: %u.%02u\n", info->graphics_ver, info->graphics_rel);
 103         else
 104                 drm_printf(p, "graphics version: %u\n", info->graphics_ver);
 105
 106         if (info->media_rel)
 107                 drm_printf(p, "media version: %u.%02u\n", info->media_ver, info->media_rel);
 108         else
 109                 drm_printf(p, "media version: %u\n", info->media_ver);
 110
 111         drm_printf(p, "display version: %u\n", info->display.ver);
 112         drm_printf(p, "gt: %d\n", info->gt);
 113         drm_printf(p, "iommu: %s\n", iommu_name());
 114         drm_printf(p, "memory-regions: %x\n", info->memory_regions);
 115         drm_printf(p, "page-sizes: %x\n", info->page_sizes);
 116         drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
 117         drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
 118         drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
 119         drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
 120
 121 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
 122         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 123 #undef PRINT_FLAG
 124
 125 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
 126         DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 127 #undef PRINT_FLAG
 128 }
 129
 130 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 131                                      struct drm_printer *p)
 132 {
 133         drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
 134 }
 135
 136 #undef INTEL_VGA_DEVICE
 137 #define INTEL_VGA_DEVICE(id, info) (id)
 138
 139 static const u16 subplatform_ult_ids[] = {
 140         INTEL_HSW_ULT_GT1_IDS(0),
 141         INTEL_HSW_ULT_GT2_IDS(0),
 142         INTEL_HSW_ULT_GT3_IDS(0),
 143         INTEL_BDW_ULT_GT1_IDS(0),
 144         INTEL_BDW_ULT_GT2_IDS(0),
 145         INTEL_BDW_ULT_GT3_IDS(0),
 146         INTEL_BDW_ULT_RSVD_IDS(0),
 147         INTEL_SKL_ULT_GT1_IDS(0),
 148         INTEL_SKL_ULT_GT2_IDS(0),
 149         INTEL_SKL_ULT_GT3_IDS(0),
 150         INTEL_KBL_ULT_GT1_IDS(0),
 151         INTEL_KBL_ULT_GT2_IDS(0),
 152         INTEL_KBL_ULT_GT3_IDS(0),
 153         INTEL_CFL_U_GT2_IDS(0),
 154         INTEL_CFL_U_GT3_IDS(0),
 155         INTEL_WHL_U_GT1_IDS(0),
 156         INTEL_WHL_U_GT2_IDS(0),
 157         INTEL_WHL_U_GT3_IDS(0),
 158         INTEL_CML_U_GT1_IDS(0),
 159         INTEL_CML_U_GT2_IDS(0),
 160 };
 161
 162 static const u16 subplatform_ulx_ids[] = {
 163         INTEL_HSW_ULX_GT1_IDS(0),
 164         INTEL_HSW_ULX_GT2_IDS(0),
 165         INTEL_BDW_ULX_GT1_IDS(0),
 166         INTEL_BDW_ULX_GT2_IDS(0),
 167         INTEL_BDW_ULX_GT3_IDS(0),
 168         INTEL_BDW_ULX_RSVD_IDS(0),
 169         INTEL_SKL_ULX_GT1_IDS(0),
 170         INTEL_SKL_ULX_GT2_IDS(0),
 171         INTEL_KBL_ULX_GT1_IDS(0),
 172         INTEL_KBL_ULX_GT2_IDS(0),
 173         INTEL_AML_KBL_GT2_IDS(0),
 174         INTEL_AML_CFL_GT2_IDS(0),
 175 };
 176
 177 static const u16 subplatform_portf_ids[] = {
 178         INTEL_CNL_PORT_F_IDS(0),
 179         INTEL_ICL_PORT_F_IDS(0),
 180 };
 181
 182 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 183 {
 184         for (; num; num--, p++) {
 185                 if (*p == id)
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 193 {
 194         const struct intel_device_info *info = INTEL_INFO(i915);
 195         const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
 196         const unsigned int pi = __platform_mask_index(rinfo, info->platform);
 197         const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
 198         u16 devid = INTEL_DEVID(i915);
 199         u32 mask = 0;
 200
 201         /* Make sure IS_<platform> checks are working. */
 202         RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
 203
 204         /* Find and mark subplatform bits based on the PCI device id. */
 205         if (find_devid(devid, subplatform_ult_ids,
 206                        ARRAY_SIZE(subplatform_ult_ids))) {
 207                 mask = BIT(INTEL_SUBPLATFORM_ULT);
 208         } else if (find_devid(devid, subplatform_ulx_ids,
 209                               ARRAY_SIZE(subplatform_ulx_ids))) {
 210                 mask = BIT(INTEL_SUBPLATFORM_ULX);
 211                 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 212                         /* ULX machines are also considered ULT. */
 213                         mask |= BIT(INTEL_SUBPLATFORM_ULT);
 214                 }
 215         } else if (find_devid(devid, subplatform_portf_ids,
 216                               ARRAY_SIZE(subplatform_portf_ids))) {
 217                 mask = BIT(INTEL_SUBPLATFORM_PORTF);
 218         }
 219
 220         if (IS_TIGERLAKE(i915)) {
 221                 struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev);
 222
 223                 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
 224
 225                 drm_WARN_ON(&i915->drm, mask);
 226                 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
 227                             TGL_ROOT_DEVICE_ID);
 228
 229                 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
 230                 case TGL_ROOT_DEVICE_SKU_ULX:
 231                         mask = BIT(INTEL_SUBPLATFORM_ULX);
 232                         break;
 233                 case TGL_ROOT_DEVICE_SKU_ULT:
 234                         mask = BIT(INTEL_SUBPLATFORM_ULT);
 235                         break;
 236                 }
 237         }
 238
 239         GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
 240
 241         RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 242 }
 243
 244 /**
 245  * intel_device_info_runtime_init - initialize runtime info
 246  * @dev_priv: the i915 device
 247  *
 248  * Determine various intel_device_info fields at runtime.
 249  *
 250  * Use it when either:
 251  *   - it's judged too laborious to fill n static structures with the limit
 252  *     when a simple if statement does the job,
 253  *   - run-time checks (eg read fuse/strap registers) are needed.
 254  *
 255  * This function needs to be called:
 256  *   - after the MMIO has been setup as we are reading registers,
 257  *   - after the PCH has been detected,
 258  *   - before the first usage of the fields it can tweak.
 259  */
 260 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 261 {
 262         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 263         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 264         enum pipe pipe;
 265
 266         /* Wa_14011765242: adl-s A0,A1 */
 267         if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 268                 for_each_pipe(dev_priv, pipe)
 269                         runtime->num_scalers[pipe] = 0;
 270         else if (DISPLAY_VER(dev_priv) >= 11) {
 271                 for_each_pipe(dev_priv, pipe)
 272                         runtime->num_scalers[pipe] = 2;
 273         } else if (DISPLAY_VER(dev_priv) >= 9) {
 274                 runtime->num_scalers[PIPE_A] = 2;
 275                 runtime->num_scalers[PIPE_B] = 2;
 276                 runtime->num_scalers[PIPE_C] = 1;
 277         }
 278
 279         BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 280
 281         if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 282                 for_each_pipe(dev_priv, pipe)
 283                         runtime->num_sprites[pipe] = 4;
 284         else if (DISPLAY_VER(dev_priv) >= 11)
 285                 for_each_pipe(dev_priv, pipe)
 286                         runtime->num_sprites[pipe] = 6;
 287         else if (DISPLAY_VER(dev_priv) == 10)
 288                 for_each_pipe(dev_priv, pipe)
 289                         runtime->num_sprites[pipe] = 3;
 290         else if (IS_BROXTON(dev_priv)) {
 291                 /*
 292                  * Skylake and Broxton currently don't expose the topmost plane as its
 293                  * use is exclusive with the legacy cursor and we only want to expose
 294                  * one of those, not both. Until we can safely expose the topmost plane
 295                  * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 296                  * we don't expose the topmost plane at all to prevent ABI breakage
 297                  * down the line.
 298                  */
 299
 300                 runtime->num_sprites[PIPE_A] = 2;
 301                 runtime->num_sprites[PIPE_B] = 2;
 302                 runtime->num_sprites[PIPE_C] = 1;
 303         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 304                 for_each_pipe(dev_priv, pipe)
 305                         runtime->num_sprites[pipe] = 2;
 306         } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 307                 for_each_pipe(dev_priv, pipe)
 308                         runtime->num_sprites[pipe] = 1;
 309         }
 310
 311         if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
 312             HAS_PCH_SPLIT(dev_priv)) {
 313                 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
 314                 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
 315
 316                 /*
 317                  * SFUSE_STRAP is supposed to have a bit signalling the display
 318                  * is fused off. Unfortunately it seems that, at least in
 319                  * certain cases, fused off display means that PCH display
 320                  * reads don't land anywhere. In that case, we read 0s.
 321                  *
 322                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 323                  * should be set when taking over after the firmware.
 324                  */
 325                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 326                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 327                     (HAS_PCH_CPT(dev_priv) &&
 328                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 329                         drm_info(&dev_priv->drm,
 330                                  "Display fused off, disabling\n");
 331                         info->pipe_mask = 0;
 332                         info->cpu_transcoder_mask = 0;
 333                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 334                         drm_info(&dev_priv->drm, "PipeC fused off\n");
 335                         info->pipe_mask &= ~BIT(PIPE_C);
 336                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 337                 }
 338         } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 339                 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 340
 341                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
 342                         info->pipe_mask &= ~BIT(PIPE_A);
 343                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
 344                 }
 345                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 346                         info->pipe_mask &= ~BIT(PIPE_B);
 347                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 348                 }
 349                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 350                         info->pipe_mask &= ~BIT(PIPE_C);
 351                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 352                 }
 353
 354                 if (DISPLAY_VER(dev_priv) >= 12 &&
 355                     (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 356                         info->pipe_mask &= ~BIT(PIPE_D);
 357                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 358                 }
 359
 360                 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 361                         info->display.has_hdcp = 0;
 362
 363                 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 364                         info->display.has_fbc = 0;
 365
 366                 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 367                         info->display.has_dmc = 0;
 368
 369                 if (DISPLAY_VER(dev_priv) >= 10 &&
 370                     (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
 371                         info->display.has_dsc = 0;
 372         }
 373
 374         if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
 375                 drm_info(&dev_priv->drm,
 376                          "Disabling ppGTT for VT-d support\n");
 377                 info->ppgtt_type = INTEL_PPGTT_NONE;
 378         }
 379
 380         runtime->rawclk_freq = intel_read_rawclk(dev_priv);
 381         drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 382
 383         if (!HAS_DISPLAY(dev_priv)) {
 384                 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 385                                                    DRIVER_ATOMIC);
 386                 memset(&info->display, 0, sizeof(info->display));
 387                 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
 388                 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
 389         }
 390 }
 391
 392 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 393                              struct drm_printer *p)
 394 {
 395         drm_printf(p, "Has logical contexts? %s\n",
 396                    yesno(caps->has_logical_contexts));
 397         drm_printf(p, "scheduler: %x\n", caps->scheduler);
 398 }