2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <drm/drm_scdc_helper.h>
30 #include "intel_drv.h"
32 struct ddi_buf_trans {
33 u32 trans1; /* balance leg enable, de-emph level */
34 u32 trans2; /* vref sel, vswing */
35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
38 static const u8 index_to_dp_signal_levels[] = {
39 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
40 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
41 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
42 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
43 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
44 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
45 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
46 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
47 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
48 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
51 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
52 * them for both DP and FDI transports, allowing those ports to
53 * automatically adapt to HDMI connections as well
55 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
56 { 0x00FFFFFF, 0x0006000E, 0x0 },
57 { 0x00D75FFF, 0x0005000A, 0x0 },
58 { 0x00C30FFF, 0x00040006, 0x0 },
59 { 0x80AAAFFF, 0x000B0000, 0x0 },
60 { 0x00FFFFFF, 0x0005000A, 0x0 },
61 { 0x00D75FFF, 0x000C0004, 0x0 },
62 { 0x80C30FFF, 0x000B0000, 0x0 },
63 { 0x00FFFFFF, 0x00040006, 0x0 },
64 { 0x80D75FFF, 0x000B0000, 0x0 },
67 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
68 { 0x00FFFFFF, 0x0007000E, 0x0 },
69 { 0x00D75FFF, 0x000F000A, 0x0 },
70 { 0x00C30FFF, 0x00060006, 0x0 },
71 { 0x00AAAFFF, 0x001E0000, 0x0 },
72 { 0x00FFFFFF, 0x000F000A, 0x0 },
73 { 0x00D75FFF, 0x00160004, 0x0 },
74 { 0x00C30FFF, 0x001E0000, 0x0 },
75 { 0x00FFFFFF, 0x00060006, 0x0 },
76 { 0x00D75FFF, 0x001E0000, 0x0 },
79 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
80 /* Idx NT mV d T mV d db */
81 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
82 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
83 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
84 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
85 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
86 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
87 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
88 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
89 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
90 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
91 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
92 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
95 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
96 { 0x00FFFFFF, 0x00000012, 0x0 },
97 { 0x00EBAFFF, 0x00020011, 0x0 },
98 { 0x00C71FFF, 0x0006000F, 0x0 },
99 { 0x00AAAFFF, 0x000E000A, 0x0 },
100 { 0x00FFFFFF, 0x00020011, 0x0 },
101 { 0x00DB6FFF, 0x0005000F, 0x0 },
102 { 0x00BEEFFF, 0x000A000C, 0x0 },
103 { 0x00FFFFFF, 0x0005000F, 0x0 },
104 { 0x00DB6FFF, 0x000A000C, 0x0 },
107 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
108 { 0x00FFFFFF, 0x0007000E, 0x0 },
109 { 0x00D75FFF, 0x000E000A, 0x0 },
110 { 0x00BEFFFF, 0x00140006, 0x0 },
111 { 0x80B2CFFF, 0x001B0002, 0x0 },
112 { 0x00FFFFFF, 0x000E000A, 0x0 },
113 { 0x00DB6FFF, 0x00160005, 0x0 },
114 { 0x80C71FFF, 0x001A0002, 0x0 },
115 { 0x00F7DFFF, 0x00180004, 0x0 },
116 { 0x80D75FFF, 0x001B0002, 0x0 },
119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
120 { 0x00FFFFFF, 0x0001000E, 0x0 },
121 { 0x00D75FFF, 0x0004000A, 0x0 },
122 { 0x00C30FFF, 0x00070006, 0x0 },
123 { 0x00AAAFFF, 0x000C0000, 0x0 },
124 { 0x00FFFFFF, 0x0004000A, 0x0 },
125 { 0x00D75FFF, 0x00090004, 0x0 },
126 { 0x00C30FFF, 0x000C0000, 0x0 },
127 { 0x00FFFFFF, 0x00070006, 0x0 },
128 { 0x00D75FFF, 0x000C0000, 0x0 },
131 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
132 /* Idx NT mV d T mV df db */
133 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
134 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
135 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
136 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
137 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
138 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
139 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
140 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
141 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
142 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
145 /* Skylake H and S */
146 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
147 { 0x00002016, 0x000000A0, 0x0 },
148 { 0x00005012, 0x0000009B, 0x0 },
149 { 0x00007011, 0x00000088, 0x0 },
150 { 0x80009010, 0x000000C0, 0x1 },
151 { 0x00002016, 0x0000009B, 0x0 },
152 { 0x00005012, 0x00000088, 0x0 },
153 { 0x80007011, 0x000000C0, 0x1 },
154 { 0x00002016, 0x000000DF, 0x0 },
155 { 0x80005012, 0x000000C0, 0x1 },
159 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
160 { 0x0000201B, 0x000000A2, 0x0 },
161 { 0x00005012, 0x00000088, 0x0 },
162 { 0x80007011, 0x000000CD, 0x1 },
163 { 0x80009010, 0x000000C0, 0x1 },
164 { 0x0000201B, 0x0000009D, 0x0 },
165 { 0x80005012, 0x000000C0, 0x1 },
166 { 0x80007011, 0x000000C0, 0x1 },
167 { 0x00002016, 0x00000088, 0x0 },
168 { 0x80005012, 0x000000C0, 0x1 },
172 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
173 { 0x00000018, 0x000000A2, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
175 { 0x80007011, 0x000000CD, 0x3 },
176 { 0x80009010, 0x000000C0, 0x3 },
177 { 0x00000018, 0x0000009D, 0x0 },
178 { 0x80005012, 0x000000C0, 0x3 },
179 { 0x80007011, 0x000000C0, 0x3 },
180 { 0x00000018, 0x00000088, 0x0 },
181 { 0x80005012, 0x000000C0, 0x3 },
184 /* Kabylake H and S */
185 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
186 { 0x00002016, 0x000000A0, 0x0 },
187 { 0x00005012, 0x0000009B, 0x0 },
188 { 0x00007011, 0x00000088, 0x0 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x00002016, 0x0000009B, 0x0 },
191 { 0x00005012, 0x00000088, 0x0 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000097, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
198 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
199 { 0x0000201B, 0x000000A1, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x0000201B, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00002016, 0x0000004F, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
211 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
212 { 0x00001017, 0x000000A1, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000CD, 0x3 },
215 { 0x8000800F, 0x000000C0, 0x3 },
216 { 0x00001017, 0x0000009D, 0x0 },
217 { 0x80005012, 0x000000C0, 0x3 },
218 { 0x80007011, 0x000000C0, 0x3 },
219 { 0x00001017, 0x0000004C, 0x0 },
220 { 0x80005012, 0x000000C0, 0x3 },
224 * Skylake/Kabylake H and S
225 * eDP 1.4 low vswing translation parameters
227 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
228 { 0x00000018, 0x000000A8, 0x0 },
229 { 0x00004013, 0x000000A9, 0x0 },
230 { 0x00007011, 0x000000A2, 0x0 },
231 { 0x00009010, 0x0000009C, 0x0 },
232 { 0x00000018, 0x000000A9, 0x0 },
233 { 0x00006013, 0x000000A2, 0x0 },
234 { 0x00007011, 0x000000A6, 0x0 },
235 { 0x00000018, 0x000000AB, 0x0 },
236 { 0x00007013, 0x0000009F, 0x0 },
237 { 0x00000018, 0x000000DF, 0x0 },
242 * eDP 1.4 low vswing translation parameters
244 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
245 { 0x00000018, 0x000000A8, 0x0 },
246 { 0x00004013, 0x000000A9, 0x0 },
247 { 0x00007011, 0x000000A2, 0x0 },
248 { 0x00009010, 0x0000009C, 0x0 },
249 { 0x00000018, 0x000000A9, 0x0 },
250 { 0x00006013, 0x000000A2, 0x0 },
251 { 0x00007011, 0x000000A6, 0x0 },
252 { 0x00002016, 0x000000AB, 0x0 },
253 { 0x00005013, 0x0000009F, 0x0 },
254 { 0x00000018, 0x000000DF, 0x0 },
259 * eDP 1.4 low vswing translation parameters
261 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
262 { 0x00000018, 0x000000A8, 0x0 },
263 { 0x00004013, 0x000000AB, 0x0 },
264 { 0x00007011, 0x000000A4, 0x0 },
265 { 0x00009010, 0x000000DF, 0x0 },
266 { 0x00000018, 0x000000AA, 0x0 },
267 { 0x00006013, 0x000000A4, 0x0 },
268 { 0x00007011, 0x0000009D, 0x0 },
269 { 0x00000018, 0x000000A0, 0x0 },
270 { 0x00006012, 0x000000DF, 0x0 },
271 { 0x00000018, 0x0000008A, 0x0 },
274 /* Skylake/Kabylake U, H and S */
275 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
276 { 0x00000018, 0x000000AC, 0x0 },
277 { 0x00005012, 0x0000009D, 0x0 },
278 { 0x00007011, 0x00000088, 0x0 },
279 { 0x00000018, 0x000000A1, 0x0 },
280 { 0x00000018, 0x00000098, 0x0 },
281 { 0x00004013, 0x00000088, 0x0 },
282 { 0x80006012, 0x000000CD, 0x1 },
283 { 0x00000018, 0x000000DF, 0x0 },
284 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
285 { 0x80003015, 0x000000C0, 0x1 },
286 { 0x80000018, 0x000000C0, 0x1 },
289 /* Skylake/Kabylake Y */
290 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
291 { 0x00000018, 0x000000A1, 0x0 },
292 { 0x00005012, 0x000000DF, 0x0 },
293 { 0x80007011, 0x000000CB, 0x3 },
294 { 0x00000018, 0x000000A4, 0x0 },
295 { 0x00000018, 0x0000009D, 0x0 },
296 { 0x00004013, 0x00000080, 0x0 },
297 { 0x80006013, 0x000000C0, 0x3 },
298 { 0x00000018, 0x0000008A, 0x0 },
299 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
300 { 0x80003015, 0x000000C0, 0x3 },
301 { 0x80000018, 0x000000C0, 0x3 },
304 struct bxt_ddi_buf_trans {
305 u8 margin; /* swing value */
306 u8 scale; /* scale value */
307 u8 enable; /* scale enable */
311 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
312 /* Idx NT mV diff db */
313 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
314 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
315 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
316 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
317 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
318 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
319 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
320 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
321 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
322 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
325 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
326 /* Idx NT mV diff db */
327 { 26, 0, 0, 128, }, /* 0: 200 0 */
328 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
329 { 48, 0, 0, 96, }, /* 2: 200 4 */
330 { 54, 0, 0, 69, }, /* 3: 200 6 */
331 { 32, 0, 0, 128, }, /* 4: 250 0 */
332 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
333 { 54, 0, 0, 85, }, /* 6: 250 4 */
334 { 43, 0, 0, 128, }, /* 7: 300 0 */
335 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
336 { 48, 0, 0, 128, }, /* 9: 300 0 */
339 /* BSpec has 2 recommended values - entries 0 and 8.
340 * Using the entry with higher vswing.
342 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
343 /* Idx NT mV diff db */
344 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
345 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
346 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
347 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
348 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
349 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
350 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
351 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
352 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
353 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
356 struct cnl_ddi_buf_trans {
360 u8 dw4_post_cursor_2;
361 u8 dw4_post_cursor_1;
364 /* Voltage Swing Programming for VccIO 0.85V for DP */
365 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
366 /* NT mV Trans mV db */
367 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
368 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
369 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
370 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
371 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
372 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
373 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
374 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
375 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
376 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
379 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
380 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
381 /* NT mV Trans mV db */
382 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
383 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
384 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
385 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
386 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
387 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
388 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
391 /* Voltage Swing Programming for VccIO 0.85V for eDP */
392 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
393 /* NT mV Trans mV db */
394 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
395 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
396 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
397 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
398 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
399 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
400 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
401 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
402 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
405 /* Voltage Swing Programming for VccIO 0.95V for DP */
406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
409 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
410 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
411 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
412 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
413 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
414 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
415 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
416 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
417 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
420 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
421 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
422 /* NT mV Trans mV db */
423 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
425 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
426 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
427 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
428 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
429 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
430 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
431 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
432 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
433 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
436 /* Voltage Swing Programming for VccIO 0.95V for eDP */
437 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
438 /* NT mV Trans mV db */
439 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
440 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
441 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
442 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
443 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
444 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
445 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
446 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
447 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
448 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
451 /* Voltage Swing Programming for VccIO 1.05V for DP */
452 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
453 /* NT mV Trans mV db */
454 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
455 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
456 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
457 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
458 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
459 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
460 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
461 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
462 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
463 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
466 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
467 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
468 /* NT mV Trans mV db */
469 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
471 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
472 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
473 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
474 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
475 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
476 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
477 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
478 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
479 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
482 /* Voltage Swing Programming for VccIO 1.05V for eDP */
483 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
484 /* NT mV Trans mV db */
485 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
486 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
487 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
488 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
489 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
490 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
491 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
492 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
493 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
496 struct icl_combo_phy_ddi_buf_trans {
497 u32 dw2_swing_select;
498 u32 dw2_swing_scalar;
502 /* Voltage Swing Programming for VccIO 0.85V for DP */
503 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
505 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
506 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
507 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
508 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
509 { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
510 { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
511 { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
512 { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
513 { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
514 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
517 /* FIXME - After table is updated in Bspec */
518 /* Voltage Swing Programming for VccIO 0.85V for eDP */
519 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
521 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
522 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
523 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
524 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
525 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
526 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
527 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
528 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
529 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
530 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
533 /* Voltage Swing Programming for VccIO 0.95V for DP */
534 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
536 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
537 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
538 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
539 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
540 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
541 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
542 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
543 { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
544 { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
545 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
548 /* FIXME - After table is updated in Bspec */
549 /* Voltage Swing Programming for VccIO 0.95V for eDP */
550 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
552 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
553 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
554 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
555 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
556 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
557 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
558 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
559 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
560 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
561 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
564 /* Voltage Swing Programming for VccIO 1.05V for DP */
565 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
567 { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
568 { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
569 { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
570 { 0x2, 0x98, 0x900F }, /* 400 9.5 */
571 { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
572 { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
573 { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
574 { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
575 { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
576 { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
579 /* FIXME - After table is updated in Bspec */
580 /* Voltage Swing Programming for VccIO 1.05V for eDP */
581 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
583 { 0x0, 0x00, 0x00 }, /* 200 0.0 */
584 { 0x0, 0x00, 0x00 }, /* 200 1.5 */
585 { 0x0, 0x00, 0x00 }, /* 200 4.0 */
586 { 0x0, 0x00, 0x00 }, /* 200 6.0 */
587 { 0x0, 0x00, 0x00 }, /* 250 0.0 */
588 { 0x0, 0x00, 0x00 }, /* 250 1.5 */
589 { 0x0, 0x00, 0x00 }, /* 250 4.0 */
590 { 0x0, 0x00, 0x00 }, /* 300 0.0 */
591 { 0x0, 0x00, 0x00 }, /* 300 1.5 */
592 { 0x0, 0x00, 0x00 }, /* 350 0.0 */
595 struct icl_mg_phy_ddi_buf_trans {
596 u32 cri_txdeemph_override_5_0;
597 u32 cri_txdeemph_override_11_6;
598 u32 cri_txdeemph_override_17_12;
601 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
602 /* Voltage swing pre-emphasis */
603 { 0x0, 0x1B, 0x00 }, /* 0 0 */
604 { 0x0, 0x23, 0x08 }, /* 0 1 */
605 { 0x0, 0x2D, 0x12 }, /* 0 2 */
606 { 0x0, 0x00, 0x00 }, /* 0 3 */
607 { 0x0, 0x23, 0x00 }, /* 1 0 */
608 { 0x0, 0x2B, 0x09 }, /* 1 1 */
609 { 0x0, 0x2E, 0x11 }, /* 1 2 */
610 { 0x0, 0x2F, 0x00 }, /* 2 0 */
611 { 0x0, 0x33, 0x0C }, /* 2 1 */
612 { 0x0, 0x00, 0x00 }, /* 3 0 */
615 static const struct ddi_buf_trans *
616 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
618 if (dev_priv->vbt.edp.low_vswing) {
619 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
620 return bdw_ddi_translations_edp;
622 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
623 return bdw_ddi_translations_dp;
627 static const struct ddi_buf_trans *
628 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
630 if (IS_SKL_ULX(dev_priv)) {
631 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
632 return skl_y_ddi_translations_dp;
633 } else if (IS_SKL_ULT(dev_priv)) {
634 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
635 return skl_u_ddi_translations_dp;
637 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
638 return skl_ddi_translations_dp;
642 static const struct ddi_buf_trans *
643 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
645 if (IS_KBL_ULX(dev_priv)) {
646 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
647 return kbl_y_ddi_translations_dp;
648 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
649 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
650 return kbl_u_ddi_translations_dp;
652 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
653 return kbl_ddi_translations_dp;
657 static const struct ddi_buf_trans *
658 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
660 if (dev_priv->vbt.edp.low_vswing) {
661 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
662 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
663 return skl_y_ddi_translations_edp;
664 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
665 IS_CFL_ULT(dev_priv)) {
666 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
667 return skl_u_ddi_translations_edp;
669 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
670 return skl_ddi_translations_edp;
674 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
675 return kbl_get_buf_trans_dp(dev_priv, n_entries);
677 return skl_get_buf_trans_dp(dev_priv, n_entries);
680 static const struct ddi_buf_trans *
681 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
683 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
684 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
685 return skl_y_ddi_translations_hdmi;
687 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
688 return skl_ddi_translations_hdmi;
692 static int skl_buf_trans_num_entries(enum port port, int n_entries)
694 /* Only DDIA and DDIE can select the 10th register with DP */
695 if (port == PORT_A || port == PORT_E)
696 return min(n_entries, 10);
698 return min(n_entries, 9);
701 static const struct ddi_buf_trans *
702 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
703 enum port port, int *n_entries)
705 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
706 const struct ddi_buf_trans *ddi_translations =
707 kbl_get_buf_trans_dp(dev_priv, n_entries);
708 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
709 return ddi_translations;
710 } else if (IS_SKYLAKE(dev_priv)) {
711 const struct ddi_buf_trans *ddi_translations =
712 skl_get_buf_trans_dp(dev_priv, n_entries);
713 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
714 return ddi_translations;
715 } else if (IS_BROADWELL(dev_priv)) {
716 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
717 return bdw_ddi_translations_dp;
718 } else if (IS_HASWELL(dev_priv)) {
719 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
720 return hsw_ddi_translations_dp;
727 static const struct ddi_buf_trans *
728 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
729 enum port port, int *n_entries)
731 if (IS_GEN9_BC(dev_priv)) {
732 const struct ddi_buf_trans *ddi_translations =
733 skl_get_buf_trans_edp(dev_priv, n_entries);
734 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
735 return ddi_translations;
736 } else if (IS_BROADWELL(dev_priv)) {
737 return bdw_get_buf_trans_edp(dev_priv, n_entries);
738 } else if (IS_HASWELL(dev_priv)) {
739 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
740 return hsw_ddi_translations_dp;
747 static const struct ddi_buf_trans *
748 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
751 if (IS_BROADWELL(dev_priv)) {
752 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
753 return bdw_ddi_translations_fdi;
754 } else if (IS_HASWELL(dev_priv)) {
755 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
756 return hsw_ddi_translations_fdi;
763 static const struct ddi_buf_trans *
764 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
767 if (IS_GEN9_BC(dev_priv)) {
768 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
769 } else if (IS_BROADWELL(dev_priv)) {
770 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
771 return bdw_ddi_translations_hdmi;
772 } else if (IS_HASWELL(dev_priv)) {
773 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
774 return hsw_ddi_translations_hdmi;
781 static const struct bxt_ddi_buf_trans *
782 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
784 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
785 return bxt_ddi_translations_dp;
788 static const struct bxt_ddi_buf_trans *
789 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
791 if (dev_priv->vbt.edp.low_vswing) {
792 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
793 return bxt_ddi_translations_edp;
796 return bxt_get_buf_trans_dp(dev_priv, n_entries);
799 static const struct bxt_ddi_buf_trans *
800 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
802 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
803 return bxt_ddi_translations_hdmi;
806 static const struct cnl_ddi_buf_trans *
807 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
809 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
811 if (voltage == VOLTAGE_INFO_0_85V) {
812 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
813 return cnl_ddi_translations_hdmi_0_85V;
814 } else if (voltage == VOLTAGE_INFO_0_95V) {
815 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
816 return cnl_ddi_translations_hdmi_0_95V;
817 } else if (voltage == VOLTAGE_INFO_1_05V) {
818 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
819 return cnl_ddi_translations_hdmi_1_05V;
821 *n_entries = 1; /* shut up gcc */
822 MISSING_CASE(voltage);
827 static const struct cnl_ddi_buf_trans *
828 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
830 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
832 if (voltage == VOLTAGE_INFO_0_85V) {
833 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
834 return cnl_ddi_translations_dp_0_85V;
835 } else if (voltage == VOLTAGE_INFO_0_95V) {
836 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
837 return cnl_ddi_translations_dp_0_95V;
838 } else if (voltage == VOLTAGE_INFO_1_05V) {
839 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
840 return cnl_ddi_translations_dp_1_05V;
842 *n_entries = 1; /* shut up gcc */
843 MISSING_CASE(voltage);
848 static const struct cnl_ddi_buf_trans *
849 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
851 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
853 if (dev_priv->vbt.edp.low_vswing) {
854 if (voltage == VOLTAGE_INFO_0_85V) {
855 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
856 return cnl_ddi_translations_edp_0_85V;
857 } else if (voltage == VOLTAGE_INFO_0_95V) {
858 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
859 return cnl_ddi_translations_edp_0_95V;
860 } else if (voltage == VOLTAGE_INFO_1_05V) {
861 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
862 return cnl_ddi_translations_edp_1_05V;
864 *n_entries = 1; /* shut up gcc */
865 MISSING_CASE(voltage);
869 return cnl_get_buf_trans_dp(dev_priv, n_entries);
873 static const struct icl_combo_phy_ddi_buf_trans *
874 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
875 int type, int *n_entries)
877 u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
879 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
881 case VOLTAGE_INFO_0_85V:
882 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
883 return icl_combo_phy_ddi_translations_edp_0_85V;
884 case VOLTAGE_INFO_0_95V:
885 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
886 return icl_combo_phy_ddi_translations_edp_0_95V;
887 case VOLTAGE_INFO_1_05V:
888 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
889 return icl_combo_phy_ddi_translations_edp_1_05V;
891 MISSING_CASE(voltage);
896 case VOLTAGE_INFO_0_85V:
897 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
898 return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
899 case VOLTAGE_INFO_0_95V:
900 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
901 return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
902 case VOLTAGE_INFO_1_05V:
903 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
904 return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
906 MISSING_CASE(voltage);
912 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
914 int n_entries, level, default_entry;
916 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
918 if (IS_ICELAKE(dev_priv)) {
919 if (port == PORT_A || port == PORT_B)
920 icl_get_combo_buf_trans(dev_priv, port,
921 INTEL_OUTPUT_HDMI, &n_entries);
923 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
924 default_entry = n_entries - 1;
925 } else if (IS_CANNONLAKE(dev_priv)) {
926 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
927 default_entry = n_entries - 1;
928 } else if (IS_GEN9_LP(dev_priv)) {
929 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
930 default_entry = n_entries - 1;
931 } else if (IS_GEN9_BC(dev_priv)) {
932 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
934 } else if (IS_BROADWELL(dev_priv)) {
935 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
937 } else if (IS_HASWELL(dev_priv)) {
938 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
941 WARN(1, "ddi translation table missing\n");
945 /* Choose a good default if VBT is badly populated */
946 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
947 level = default_entry;
949 if (WARN_ON_ONCE(n_entries == 0))
951 if (WARN_ON_ONCE(level >= n_entries))
952 level = n_entries - 1;
958 * Starting with Haswell, DDI port buffers must be programmed with correct
959 * values in advance. This function programs the correct values for
960 * DP/eDP/FDI use cases.
962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
963 const struct intel_crtc_state *crtc_state)
965 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
968 enum port port = encoder->port;
969 const struct ddi_buf_trans *ddi_translations;
971 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
972 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
974 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
975 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
978 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
981 /* If we're boosting the current, set bit 31 of trans1 */
982 if (IS_GEN9_BC(dev_priv) &&
983 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
984 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
986 for (i = 0; i < n_entries; i++) {
987 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
988 ddi_translations[i].trans1 | iboost_bit);
989 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
990 ddi_translations[i].trans2);
995 * Starting with Haswell, DDI port buffers must be programmed with correct
996 * values in advance. This function programs the correct values for
997 * HDMI/DVI use cases.
999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005 enum port port = encoder->port;
1006 const struct ddi_buf_trans *ddi_translations;
1008 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1010 if (WARN_ON_ONCE(!ddi_translations))
1012 if (WARN_ON_ONCE(level >= n_entries))
1013 level = n_entries - 1;
1015 /* If we're boosting the current, set bit 31 of trans1 */
1016 if (IS_GEN9_BC(dev_priv) &&
1017 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1020 /* Entry 9 is for HDMI: */
1021 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022 ddi_translations[level].trans1 | iboost_bit);
1023 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024 ddi_translations[level].trans2);
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1030 i915_reg_t reg = DDI_BUF_CTL(port);
1033 for (i = 0; i < 16; i++) {
1035 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1038 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1041 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1043 switch (pll->info->id) {
1044 case DPLL_ID_WRPLL1:
1045 return PORT_CLK_SEL_WRPLL1;
1046 case DPLL_ID_WRPLL2:
1047 return PORT_CLK_SEL_WRPLL2;
1049 return PORT_CLK_SEL_SPLL;
1050 case DPLL_ID_LCPLL_810:
1051 return PORT_CLK_SEL_LCPLL_810;
1052 case DPLL_ID_LCPLL_1350:
1053 return PORT_CLK_SEL_LCPLL_1350;
1054 case DPLL_ID_LCPLL_2700:
1055 return PORT_CLK_SEL_LCPLL_2700;
1057 MISSING_CASE(pll->info->id);
1058 return PORT_CLK_SEL_NONE;
1062 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1063 const struct intel_shared_dpll *pll)
1065 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1066 int clock = crtc->config->port_clock;
1067 const enum intel_dpll_id id = pll->info->id;
1073 case DPLL_ID_ICL_DPLL0:
1074 case DPLL_ID_ICL_DPLL1:
1075 return DDI_CLK_SEL_NONE;
1076 case DPLL_ID_ICL_TBTPLL:
1079 return DDI_CLK_SEL_TBT_162;
1081 return DDI_CLK_SEL_TBT_270;
1083 return DDI_CLK_SEL_TBT_540;
1085 return DDI_CLK_SEL_TBT_810;
1087 MISSING_CASE(clock);
1090 case DPLL_ID_ICL_MGPLL1:
1091 case DPLL_ID_ICL_MGPLL2:
1092 case DPLL_ID_ICL_MGPLL3:
1093 case DPLL_ID_ICL_MGPLL4:
1094 return DDI_CLK_SEL_MG;
1098 /* Starting with Haswell, different DDI ports can work in FDI mode for
1099 * connection to the PCH-located connectors. For this, it is necessary to train
1100 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1102 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1103 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1104 * DDI A (which is used for eDP)
1107 void hsw_fdi_link_train(struct intel_crtc *crtc,
1108 const struct intel_crtc_state *crtc_state)
1110 struct drm_device *dev = crtc->base.dev;
1111 struct drm_i915_private *dev_priv = to_i915(dev);
1112 struct intel_encoder *encoder;
1113 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1115 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1116 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1117 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1120 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1121 * mode set "sequence for CRT port" document:
1122 * - TP1 to TP2 time with the default value
1123 * - FDI delay to 90h
1125 * WaFDIAutoLinkSetTimingOverrride:hsw
1127 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1128 FDI_RX_PWRDN_LANE0_VAL(2) |
1129 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1131 /* Enable the PCH Receiver FDI PLL */
1132 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1134 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1135 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1136 POSTING_READ(FDI_RX_CTL(PIPE_A));
1139 /* Switch from Rawclk to PCDclk */
1140 rx_ctl_val |= FDI_PCDCLK;
1141 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1143 /* Configure Port Clock Select */
1144 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1145 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1146 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1148 /* Start the training iterating through available voltages and emphasis,
1149 * testing each value twice. */
1150 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1151 /* Configure DP_TP_CTL with auto-training */
1152 I915_WRITE(DP_TP_CTL(PORT_E),
1153 DP_TP_CTL_FDI_AUTOTRAIN |
1154 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1155 DP_TP_CTL_LINK_TRAIN_PAT1 |
1158 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1159 * DDI E does not support port reversal, the functionality is
1160 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1161 * port reversal bit */
1162 I915_WRITE(DDI_BUF_CTL(PORT_E),
1163 DDI_BUF_CTL_ENABLE |
1164 ((crtc_state->fdi_lanes - 1) << 1) |
1165 DDI_BUF_TRANS_SELECT(i / 2));
1166 POSTING_READ(DDI_BUF_CTL(PORT_E));
1170 /* Program PCH FDI Receiver TU */
1171 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1173 /* Enable PCH FDI Receiver with auto-training */
1174 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1175 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176 POSTING_READ(FDI_RX_CTL(PIPE_A));
1178 /* Wait for FDI receiver lane calibration */
1181 /* Unset FDI_RX_MISC pwrdn lanes */
1182 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1183 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1184 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185 POSTING_READ(FDI_RX_MISC(PIPE_A));
1187 /* Wait for FDI auto training time */
1190 temp = I915_READ(DP_TP_STATUS(PORT_E));
1191 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1192 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1197 * Leave things enabled even if we failed to train FDI.
1198 * Results in less fireworks from the state checker.
1200 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1201 DRM_ERROR("FDI link training failed!\n");
1205 rx_ctl_val &= ~FDI_RX_ENABLE;
1206 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1207 POSTING_READ(FDI_RX_CTL(PIPE_A));
1209 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1210 temp &= ~DDI_BUF_CTL_ENABLE;
1211 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1212 POSTING_READ(DDI_BUF_CTL(PORT_E));
1214 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1215 temp = I915_READ(DP_TP_CTL(PORT_E));
1216 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1217 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1218 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1219 POSTING_READ(DP_TP_CTL(PORT_E));
1221 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1223 /* Reset FDI_RX_MISC pwrdn lanes */
1224 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1225 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1226 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1227 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1228 POSTING_READ(FDI_RX_MISC(PIPE_A));
1231 /* Enable normal pixel sending for FDI */
1232 I915_WRITE(DP_TP_CTL(PORT_E),
1233 DP_TP_CTL_FDI_AUTOTRAIN |
1234 DP_TP_CTL_LINK_TRAIN_NORMAL |
1235 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1239 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1241 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1242 struct intel_digital_port *intel_dig_port =
1243 enc_to_dig_port(&encoder->base);
1245 intel_dp->DP = intel_dig_port->saved_port_bits |
1246 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1247 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1250 static struct intel_encoder *
1251 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1253 struct drm_device *dev = crtc->base.dev;
1254 struct intel_encoder *encoder, *ret = NULL;
1255 int num_encoders = 0;
1257 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1262 if (num_encoders != 1)
1263 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1264 pipe_name(crtc->pipe));
1266 BUG_ON(ret == NULL);
1270 #define LC_FREQ 2700
1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1275 int refclk = LC_FREQ;
1279 wrpll = I915_READ(reg);
1280 switch (wrpll & WRPLL_PLL_REF_MASK) {
1282 case WRPLL_PLL_NON_SSC:
1284 * We could calculate spread here, but our checking
1285 * code only cares about 5% accuracy, and spread is a max of
1290 case WRPLL_PLL_LCPLL:
1294 WARN(1, "bad wrpll refclk\n");
1298 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1299 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1300 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1302 /* Convert to KHz, p & r have a fixed point portion */
1303 return (refclk * n * 100) / (p * r);
1306 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1307 enum intel_dpll_id pll_id)
1309 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1310 uint32_t cfgcr1_val, cfgcr2_val;
1311 uint32_t p0, p1, p2, dco_freq;
1313 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1314 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1316 cfgcr1_val = I915_READ(cfgcr1_reg);
1317 cfgcr2_val = I915_READ(cfgcr2_reg);
1319 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1320 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1322 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1323 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1329 case DPLL_CFGCR2_PDIV_1:
1332 case DPLL_CFGCR2_PDIV_2:
1335 case DPLL_CFGCR2_PDIV_3:
1338 case DPLL_CFGCR2_PDIV_7:
1344 case DPLL_CFGCR2_KDIV_5:
1347 case DPLL_CFGCR2_KDIV_2:
1350 case DPLL_CFGCR2_KDIV_3:
1353 case DPLL_CFGCR2_KDIV_1:
1358 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1360 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1363 return dco_freq / (p0 * p1 * p2 * 5);
1366 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1367 enum intel_dpll_id pll_id)
1369 uint32_t cfgcr0, cfgcr1;
1370 uint32_t p0, p1, p2, dco_freq, ref_clock;
1372 if (INTEL_GEN(dev_priv) >= 11) {
1373 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1374 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1376 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1377 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1380 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1383 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1391 case DPLL_CFGCR1_PDIV_2:
1394 case DPLL_CFGCR1_PDIV_3:
1397 case DPLL_CFGCR1_PDIV_5:
1400 case DPLL_CFGCR1_PDIV_7:
1406 case DPLL_CFGCR1_KDIV_1:
1409 case DPLL_CFGCR1_KDIV_2:
1412 case DPLL_CFGCR1_KDIV_4:
1417 ref_clock = dev_priv->cdclk.hw.ref;
1419 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1421 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1422 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1427 return dco_freq / (p0 * p1 * p2 * 5);
1430 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1433 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1436 case DDI_CLK_SEL_NONE:
1438 case DDI_CLK_SEL_TBT_162:
1440 case DDI_CLK_SEL_TBT_270:
1442 case DDI_CLK_SEL_TBT_540:
1444 case DDI_CLK_SEL_TBT_810:
1452 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1455 u32 mg_pll_div0, mg_clktop_hsclkctl;
1456 u32 m1, m2_int, m2_frac, div1, div2, refclk;
1459 refclk = dev_priv->cdclk.hw.ref;
1461 mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1462 mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1464 m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1465 m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1466 m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1467 (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1468 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1470 switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1471 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1474 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1477 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1480 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1484 MISSING_CASE(mg_clktop_hsclkctl);
1488 div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1489 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1490 /* div2 value of 0 is same as 1 means no div */
1495 * Adjust the original formula to delay the division by 2^22 in order to
1496 * minimize possible rounding errors.
1498 tmp = (u64)m1 * m2_int * refclk +
1499 (((u64)m1 * m2_frac * refclk) >> 22);
1500 tmp = div_u64(tmp, 5 * div1 * div2);
1505 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1509 if (pipe_config->has_pch_encoder)
1510 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1511 &pipe_config->fdi_m_n);
1512 else if (intel_crtc_has_dp_encoder(pipe_config))
1513 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1514 &pipe_config->dp_m_n);
1515 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1516 dotclock = pipe_config->port_clock * 2 / 3;
1518 dotclock = pipe_config->port_clock;
1520 if (pipe_config->ycbcr420)
1523 if (pipe_config->pixel_multiplier)
1524 dotclock /= pipe_config->pixel_multiplier;
1526 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1529 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1530 struct intel_crtc_state *pipe_config)
1532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533 enum port port = encoder->port;
1537 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1538 if (port == PORT_A || port == PORT_B) {
1539 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1540 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1542 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1545 if (pll_id == DPLL_ID_ICL_TBTPLL)
1546 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1548 link_clock = icl_calc_mg_pll_link(dev_priv, port);
1551 pipe_config->port_clock = link_clock;
1552 ddi_dotclock_get(pipe_config);
1555 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1556 struct intel_crtc_state *pipe_config)
1558 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1561 enum intel_dpll_id pll_id;
1563 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1565 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1567 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1570 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1572 switch (link_clock) {
1573 case DPLL_CFGCR0_LINK_RATE_810:
1576 case DPLL_CFGCR0_LINK_RATE_1080:
1577 link_clock = 108000;
1579 case DPLL_CFGCR0_LINK_RATE_1350:
1580 link_clock = 135000;
1582 case DPLL_CFGCR0_LINK_RATE_1620:
1583 link_clock = 162000;
1585 case DPLL_CFGCR0_LINK_RATE_2160:
1586 link_clock = 216000;
1588 case DPLL_CFGCR0_LINK_RATE_2700:
1589 link_clock = 270000;
1591 case DPLL_CFGCR0_LINK_RATE_3240:
1592 link_clock = 324000;
1594 case DPLL_CFGCR0_LINK_RATE_4050:
1595 link_clock = 405000;
1598 WARN(1, "Unsupported link rate\n");
1604 pipe_config->port_clock = link_clock;
1606 ddi_dotclock_get(pipe_config);
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610 struct intel_crtc_state *pipe_config)
1612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1615 enum intel_dpll_id pll_id;
1617 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1619 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1621 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1622 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1624 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1625 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1627 switch (link_clock) {
1628 case DPLL_CTRL1_LINK_RATE_810:
1631 case DPLL_CTRL1_LINK_RATE_1080:
1632 link_clock = 108000;
1634 case DPLL_CTRL1_LINK_RATE_1350:
1635 link_clock = 135000;
1637 case DPLL_CTRL1_LINK_RATE_1620:
1638 link_clock = 162000;
1640 case DPLL_CTRL1_LINK_RATE_2160:
1641 link_clock = 216000;
1643 case DPLL_CTRL1_LINK_RATE_2700:
1644 link_clock = 270000;
1647 WARN(1, "Unsupported link rate\n");
1653 pipe_config->port_clock = link_clock;
1655 ddi_dotclock_get(pipe_config);
1658 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1659 struct intel_crtc_state *pipe_config)
1661 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1665 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1666 switch (val & PORT_CLK_SEL_MASK) {
1667 case PORT_CLK_SEL_LCPLL_810:
1670 case PORT_CLK_SEL_LCPLL_1350:
1671 link_clock = 135000;
1673 case PORT_CLK_SEL_LCPLL_2700:
1674 link_clock = 270000;
1676 case PORT_CLK_SEL_WRPLL1:
1677 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1679 case PORT_CLK_SEL_WRPLL2:
1680 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1682 case PORT_CLK_SEL_SPLL:
1683 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1684 if (pll == SPLL_PLL_FREQ_810MHz)
1686 else if (pll == SPLL_PLL_FREQ_1350MHz)
1687 link_clock = 135000;
1688 else if (pll == SPLL_PLL_FREQ_2700MHz)
1689 link_clock = 270000;
1691 WARN(1, "bad spll freq\n");
1696 WARN(1, "bad port clock sel\n");
1700 pipe_config->port_clock = link_clock * 2;
1702 ddi_dotclock_get(pipe_config);
1705 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1707 struct intel_dpll_hw_state *state;
1710 /* For DDI ports we always use a shared PLL. */
1711 if (WARN_ON(!crtc_state->shared_dpll))
1714 state = &crtc_state->dpll_hw_state;
1717 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1718 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1719 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1720 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1721 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1722 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1724 return chv_calc_dpll_params(100000, &clock);
1727 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1728 struct intel_crtc_state *pipe_config)
1730 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1732 ddi_dotclock_get(pipe_config);
1735 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1736 struct intel_crtc_state *pipe_config)
1738 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1740 if (INTEL_GEN(dev_priv) <= 8)
1741 hsw_ddi_clock_get(encoder, pipe_config);
1742 else if (IS_GEN9_BC(dev_priv))
1743 skl_ddi_clock_get(encoder, pipe_config);
1744 else if (IS_GEN9_LP(dev_priv))
1745 bxt_ddi_clock_get(encoder, pipe_config);
1746 else if (IS_CANNONLAKE(dev_priv))
1747 cnl_ddi_clock_get(encoder, pipe_config);
1748 else if (IS_ICELAKE(dev_priv))
1749 icl_ddi_clock_get(encoder, pipe_config);
1752 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1755 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1756 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1759 if (!intel_crtc_has_dp_encoder(crtc_state))
1762 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1764 temp = TRANS_MSA_SYNC_CLK;
1766 if (crtc_state->limited_color_range)
1767 temp |= TRANS_MSA_CEA_RANGE;
1769 switch (crtc_state->pipe_bpp) {
1771 temp |= TRANS_MSA_6_BPC;
1774 temp |= TRANS_MSA_8_BPC;
1777 temp |= TRANS_MSA_10_BPC;
1780 temp |= TRANS_MSA_12_BPC;
1783 MISSING_CASE(crtc_state->pipe_bpp);
1787 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1790 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1795 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1798 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1800 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1802 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1803 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1806 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1808 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1809 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811 enum pipe pipe = crtc->pipe;
1812 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1813 enum port port = encoder->port;
1816 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1817 temp = TRANS_DDI_FUNC_ENABLE;
1818 temp |= TRANS_DDI_SELECT_PORT(port);
1820 switch (crtc_state->pipe_bpp) {
1822 temp |= TRANS_DDI_BPC_6;
1825 temp |= TRANS_DDI_BPC_8;
1828 temp |= TRANS_DDI_BPC_10;
1831 temp |= TRANS_DDI_BPC_12;
1837 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1838 temp |= TRANS_DDI_PVSYNC;
1839 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1840 temp |= TRANS_DDI_PHSYNC;
1842 if (cpu_transcoder == TRANSCODER_EDP) {
1845 /* On Haswell, can only use the always-on power well for
1846 * eDP when not using the panel fitter, and when not
1847 * using motion blur mitigation (which we don't
1849 if (IS_HASWELL(dev_priv) &&
1850 (crtc_state->pch_pfit.enabled ||
1851 crtc_state->pch_pfit.force_thru))
1852 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1854 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1857 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1860 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1868 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1869 if (crtc_state->has_hdmi_sink)
1870 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1872 temp |= TRANS_DDI_MODE_SELECT_DVI;
1874 if (crtc_state->hdmi_scrambling)
1875 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1876 if (crtc_state->hdmi_high_tmds_clock_ratio)
1877 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1878 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1879 temp |= TRANS_DDI_MODE_SELECT_FDI;
1880 temp |= (crtc_state->fdi_lanes - 1) << 1;
1881 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1882 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1883 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1885 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1886 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1889 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1892 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1894 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1896 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1897 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1898 uint32_t val = I915_READ(reg);
1900 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1901 val |= TRANS_DDI_PORT_NONE;
1902 I915_WRITE(reg, val);
1904 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1905 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1906 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1907 /* Quirk time at 100ms for reliable operation */
1912 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1915 struct drm_device *dev = intel_encoder->base.dev;
1916 struct drm_i915_private *dev_priv = to_i915(dev);
1921 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1922 intel_encoder->power_domain)))
1925 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1930 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1932 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1934 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1935 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1937 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1941 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1943 struct drm_device *dev = intel_connector->base.dev;
1944 struct drm_i915_private *dev_priv = to_i915(dev);
1945 struct intel_encoder *encoder = intel_connector->encoder;
1946 int type = intel_connector->base.connector_type;
1947 enum port port = encoder->port;
1949 enum transcoder cpu_transcoder;
1953 if (!intel_display_power_get_if_enabled(dev_priv,
1954 encoder->power_domain))
1957 if (!encoder->get_hw_state(encoder, &pipe)) {
1963 cpu_transcoder = TRANSCODER_EDP;
1965 cpu_transcoder = (enum transcoder) pipe;
1967 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1969 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1970 case TRANS_DDI_MODE_SELECT_HDMI:
1971 case TRANS_DDI_MODE_SELECT_DVI:
1972 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1975 case TRANS_DDI_MODE_SELECT_DP_SST:
1976 ret = type == DRM_MODE_CONNECTOR_eDP ||
1977 type == DRM_MODE_CONNECTOR_DisplayPort;
1980 case TRANS_DDI_MODE_SELECT_DP_MST:
1981 /* if the transcoder is in MST state then
1982 * connector isn't connected */
1986 case TRANS_DDI_MODE_SELECT_FDI:
1987 ret = type == DRM_MODE_CONNECTOR_VGA;
1996 intel_display_power_put(dev_priv, encoder->power_domain);
2001 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2004 struct drm_device *dev = encoder->base.dev;
2005 struct drm_i915_private *dev_priv = to_i915(dev);
2006 enum port port = encoder->port;
2011 if (!intel_display_power_get_if_enabled(dev_priv,
2012 encoder->power_domain))
2017 tmp = I915_READ(DDI_BUF_CTL(port));
2019 if (!(tmp & DDI_BUF_CTL_ENABLE))
2022 if (port == PORT_A) {
2023 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2025 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2026 case TRANS_DDI_EDP_INPUT_A_ON:
2027 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2030 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2033 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2043 for_each_pipe(dev_priv, p) {
2044 enum transcoder cpu_transcoder = (enum transcoder) p;
2046 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2048 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2049 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2050 TRANS_DDI_MODE_SELECT_DP_MST)
2060 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2063 if (ret && IS_GEN9_LP(dev_priv)) {
2064 tmp = I915_READ(BXT_PHY_CTL(port));
2065 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2066 BXT_PHY_LANE_POWERDOWN_ACK |
2067 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2068 DRM_ERROR("Port %c enabled but PHY powered down? "
2069 "(PHY_CTL %08x)\n", port_name(port), tmp);
2072 intel_display_power_put(dev_priv, encoder->power_domain);
2077 static inline enum intel_display_power_domain
2078 intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
2080 /* CNL HW requires corresponding AUX IOs to be powered up for PSR with
2081 * DC states enabled at the same time, while for driver initiated AUX
2082 * transfers we need the same AUX IOs to be powered but with DC states
2083 * disabled. Accordingly use the AUX power domain here which leaves DC
2085 * However, for non-A AUX ports the corresponding non-EDP transcoders
2086 * would have already enabled power well 2 and DC_OFF. This means we can
2087 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2088 * specific AUX_IO reference without powering up any extra wells.
2089 * Note that PSR is enabled only on Port A even though this function
2090 * returns the correct domain for other ports too.
2092 return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2093 intel_dp->aux_power_domain;
2096 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2097 struct intel_crtc_state *crtc_state)
2099 struct intel_digital_port *dig_port;
2103 * TODO: Add support for MST encoders. Atm, the following should never
2104 * happen since fake-MST encoders don't set their get_power_domains()
2107 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2110 dig_port = enc_to_dig_port(&encoder->base);
2111 domains = BIT_ULL(dig_port->ddi_io_power_domain);
2113 /* AUX power is only needed for (e)DP mode, not for HDMI. */
2114 if (intel_crtc_has_dp_encoder(crtc_state)) {
2115 struct intel_dp *intel_dp = &dig_port->dp;
2117 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
2123 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2125 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2126 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2127 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2128 enum port port = encoder->port;
2129 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2131 if (cpu_transcoder != TRANSCODER_EDP)
2132 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2133 TRANS_CLK_SEL_PORT(port));
2136 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2138 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2139 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2141 if (cpu_transcoder != TRANSCODER_EDP)
2142 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2143 TRANS_CLK_SEL_DISABLED);
2146 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2147 enum port port, uint8_t iboost)
2151 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2152 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2154 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2156 tmp |= BALANCE_LEG_DISABLE(port);
2157 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2160 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2161 int level, enum intel_output_type type)
2163 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2165 enum port port = encoder->port;
2168 if (type == INTEL_OUTPUT_HDMI)
2169 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2171 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2174 const struct ddi_buf_trans *ddi_translations;
2177 if (type == INTEL_OUTPUT_HDMI)
2178 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2179 else if (type == INTEL_OUTPUT_EDP)
2180 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2182 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2184 if (WARN_ON_ONCE(!ddi_translations))
2186 if (WARN_ON_ONCE(level >= n_entries))
2187 level = n_entries - 1;
2189 iboost = ddi_translations[level].i_boost;
2192 /* Make sure that the requested I_boost is valid */
2193 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2194 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2198 _skl_ddi_set_iboost(dev_priv, port, iboost);
2200 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2201 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2204 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2205 int level, enum intel_output_type type)
2207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2208 const struct bxt_ddi_buf_trans *ddi_translations;
2209 enum port port = encoder->port;
2212 if (type == INTEL_OUTPUT_HDMI)
2213 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2214 else if (type == INTEL_OUTPUT_EDP)
2215 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2217 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2219 if (WARN_ON_ONCE(!ddi_translations))
2221 if (WARN_ON_ONCE(level >= n_entries))
2222 level = n_entries - 1;
2224 bxt_ddi_phy_set_signal_level(dev_priv, port,
2225 ddi_translations[level].margin,
2226 ddi_translations[level].scale,
2227 ddi_translations[level].enable,
2228 ddi_translations[level].deemphasis);
2231 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2234 enum port port = encoder->port;
2237 if (IS_ICELAKE(dev_priv)) {
2238 if (port == PORT_A || port == PORT_B)
2239 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2242 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2243 } else if (IS_CANNONLAKE(dev_priv)) {
2244 if (encoder->type == INTEL_OUTPUT_EDP)
2245 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2247 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2248 } else if (IS_GEN9_LP(dev_priv)) {
2249 if (encoder->type == INTEL_OUTPUT_EDP)
2250 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2252 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2254 if (encoder->type == INTEL_OUTPUT_EDP)
2255 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2257 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2260 if (WARN_ON(n_entries < 1))
2262 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2263 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2265 return index_to_dp_signal_levels[n_entries - 1] &
2266 DP_TRAIN_VOLTAGE_SWING_MASK;
2270 * We assume that the full set of pre-emphasis values can be
2271 * used on all DDI platforms. Should that change we need to
2272 * rethink this code.
2274 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2276 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2278 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2280 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2282 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2285 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2289 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2290 int level, enum intel_output_type type)
2292 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2293 const struct cnl_ddi_buf_trans *ddi_translations;
2294 enum port port = encoder->port;
2298 if (type == INTEL_OUTPUT_HDMI)
2299 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2300 else if (type == INTEL_OUTPUT_EDP)
2301 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2303 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2305 if (WARN_ON_ONCE(!ddi_translations))
2307 if (WARN_ON_ONCE(level >= n_entries))
2308 level = n_entries - 1;
2310 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2311 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2312 val &= ~SCALING_MODE_SEL_MASK;
2313 val |= SCALING_MODE_SEL(2);
2314 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2316 /* Program PORT_TX_DW2 */
2317 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2318 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2320 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2321 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2322 /* Rcomp scalar is fixed as 0x98 for every table entry */
2323 val |= RCOMP_SCALAR(0x98);
2324 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2326 /* Program PORT_TX_DW4 */
2327 /* We cannot write to GRP. It would overrite individual loadgen */
2328 for (ln = 0; ln < 4; ln++) {
2329 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2330 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2332 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2333 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2334 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2335 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2338 /* Program PORT_TX_DW5 */
2339 /* All DW5 values are fixed for every table entry */
2340 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2341 val &= ~RTERM_SELECT_MASK;
2342 val |= RTERM_SELECT(6);
2343 val |= TAP3_DISABLE;
2344 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2346 /* Program PORT_TX_DW7 */
2347 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2348 val &= ~N_SCALAR_MASK;
2349 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2350 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2353 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2354 int level, enum intel_output_type type)
2356 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2357 enum port port = encoder->port;
2358 int width, rate, ln;
2361 if (type == INTEL_OUTPUT_HDMI) {
2363 rate = 0; /* Rate is always < than 6GHz for HDMI */
2365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2367 width = intel_dp->lane_count;
2368 rate = intel_dp->link_rate;
2372 * 1. If port type is eDP or DP,
2373 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2376 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2377 if (type != INTEL_OUTPUT_HDMI)
2378 val |= COMMON_KEEPER_EN;
2380 val &= ~COMMON_KEEPER_EN;
2381 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2383 /* 2. Program loadgen select */
2385 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2386 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2387 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2388 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2390 for (ln = 0; ln <= 3; ln++) {
2391 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2392 val &= ~LOADGEN_SELECT;
2394 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2395 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2396 val |= LOADGEN_SELECT;
2398 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2401 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2402 val = I915_READ(CNL_PORT_CL1CM_DW5);
2403 val |= SUS_CLOCK_CONFIG;
2404 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2406 /* 4. Clear training enable to change swing values */
2407 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2408 val &= ~TX_TRAINING_EN;
2409 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2411 /* 5. Program swing and de-emphasis */
2412 cnl_ddi_vswing_program(encoder, level, type);
2414 /* 6. Set training enable to trigger update */
2415 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2416 val |= TX_TRAINING_EN;
2417 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2420 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2421 u32 level, enum port port, int type)
2423 const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2427 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2429 if (!ddi_translations)
2432 if (level >= n_entries) {
2433 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2434 level = n_entries - 1;
2437 /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2438 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2439 val &= ~RTERM_SELECT_MASK;
2440 val |= RTERM_SELECT(0x6);
2441 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2443 /* Program PORT_TX_DW5 */
2444 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2445 /* Set DisableTap2 and DisableTap3 if MIPI DSI
2446 * Clear DisableTap2 and DisableTap3 for all other Ports
2448 if (type == INTEL_OUTPUT_DSI) {
2449 val |= TAP2_DISABLE;
2450 val |= TAP3_DISABLE;
2452 val &= ~TAP2_DISABLE;
2453 val &= ~TAP3_DISABLE;
2455 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2457 /* Program PORT_TX_DW2 */
2458 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2459 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2461 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2462 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2463 /* Program Rcomp scalar for every table entry */
2464 val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2465 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2467 /* Program PORT_TX_DW4 */
2468 /* We cannot write to GRP. It would overwrite individual loadgen. */
2469 for (ln = 0; ln <= 3; ln++) {
2470 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2471 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2473 val |= ddi_translations[level].dw4_scaling;
2474 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2478 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2480 enum intel_output_type type)
2482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2483 enum port port = encoder->port;
2489 if (type == INTEL_OUTPUT_HDMI) {
2491 /* Rate is always < than 6GHz for HDMI */
2493 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2495 width = intel_dp->lane_count;
2496 rate = intel_dp->link_rate;
2500 * 1. If port type is eDP or DP,
2501 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2504 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2505 if (type == INTEL_OUTPUT_HDMI)
2506 val &= ~COMMON_KEEPER_EN;
2508 val |= COMMON_KEEPER_EN;
2509 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2511 /* 2. Program loadgen select */
2513 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2514 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2515 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2516 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2518 for (ln = 0; ln <= 3; ln++) {
2519 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2520 val &= ~LOADGEN_SELECT;
2522 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2523 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2524 val |= LOADGEN_SELECT;
2526 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2529 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2530 val = I915_READ(ICL_PORT_CL_DW5(port));
2531 val |= SUS_CLOCK_CONFIG;
2532 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2534 /* 4. Clear training enable to change swing values */
2535 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2536 val &= ~TX_TRAINING_EN;
2537 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2539 /* 5. Program swing and de-emphasis */
2540 icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2542 /* 6. Set training enable to trigger update */
2543 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2544 val |= TX_TRAINING_EN;
2545 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2548 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2552 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2553 enum port port = encoder->port;
2554 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2558 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2559 ddi_translations = icl_mg_phy_ddi_translations;
2560 /* The table does not have values for level 3 and level 9. */
2561 if (level >= n_entries || level == 3 || level == 9) {
2562 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2563 level, n_entries - 2);
2564 level = n_entries - 2;
2567 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2568 for (ln = 0; ln < 2; ln++) {
2569 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2570 val &= ~CRI_USE_FS32;
2571 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2573 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2574 val &= ~CRI_USE_FS32;
2575 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2578 /* Program MG_TX_SWINGCTRL with values from vswing table */
2579 for (ln = 0; ln < 2; ln++) {
2580 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2581 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583 ddi_translations[level].cri_txdeemph_override_17_12);
2584 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2586 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2587 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2588 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2589 ddi_translations[level].cri_txdeemph_override_17_12);
2590 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2593 /* Program MG_TX_DRVCTRL with values from vswing table */
2594 for (ln = 0; ln < 2; ln++) {
2595 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2596 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2597 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2598 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2599 ddi_translations[level].cri_txdeemph_override_5_0) |
2600 CRI_TXDEEMPH_OVERRIDE_11_6(
2601 ddi_translations[level].cri_txdeemph_override_11_6) |
2602 CRI_TXDEEMPH_OVERRIDE_EN;
2603 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2605 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2606 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2607 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2608 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2609 ddi_translations[level].cri_txdeemph_override_5_0) |
2610 CRI_TXDEEMPH_OVERRIDE_11_6(
2611 ddi_translations[level].cri_txdeemph_override_11_6) |
2612 CRI_TXDEEMPH_OVERRIDE_EN;
2613 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2615 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2619 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2620 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2621 * values from table for which TX1 and TX2 enabled.
2623 for (ln = 0; ln < 2; ln++) {
2624 val = I915_READ(MG_CLKHUB(port, ln));
2625 if (link_clock < 300000)
2626 val |= CFG_LOW_RATE_LKREN_EN;
2628 val &= ~CFG_LOW_RATE_LKREN_EN;
2629 I915_WRITE(MG_CLKHUB(port, ln), val);
2632 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2633 for (ln = 0; ln < 2; ln++) {
2634 val = I915_READ(MG_TX1_DCC(port, ln));
2635 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2636 if (link_clock <= 500000) {
2637 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2639 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2640 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2642 I915_WRITE(MG_TX1_DCC(port, ln), val);
2644 val = I915_READ(MG_TX2_DCC(port, ln));
2645 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2646 if (link_clock <= 500000) {
2647 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2649 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2650 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2652 I915_WRITE(MG_TX2_DCC(port, ln), val);
2655 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2656 for (ln = 0; ln < 2; ln++) {
2657 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2658 val |= CRI_CALCINIT;
2659 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2661 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2662 val |= CRI_CALCINIT;
2663 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2667 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2670 enum intel_output_type type)
2672 enum port port = encoder->port;
2674 if (port == PORT_A || port == PORT_B)
2675 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2677 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2680 static uint32_t translate_signal_level(int signal_levels)
2684 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2685 if (index_to_dp_signal_levels[i] == signal_levels)
2689 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2695 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2697 uint8_t train_set = intel_dp->train_set[0];
2698 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2699 DP_TRAIN_PRE_EMPHASIS_MASK);
2701 return translate_signal_level(signal_levels);
2704 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2706 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2707 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2708 struct intel_encoder *encoder = &dport->base;
2709 int level = intel_ddi_dp_level(intel_dp);
2711 if (IS_ICELAKE(dev_priv))
2712 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2713 level, encoder->type);
2714 else if (IS_CANNONLAKE(dev_priv))
2715 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2717 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2722 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2724 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2725 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2726 struct intel_encoder *encoder = &dport->base;
2727 int level = intel_ddi_dp_level(intel_dp);
2729 if (IS_GEN9_BC(dev_priv))
2730 skl_ddi_set_iboost(encoder, level, encoder->type);
2732 return DDI_BUF_TRANS_SELECT(level);
2735 void icl_map_plls_to_ports(struct drm_crtc *crtc,
2736 struct intel_crtc_state *crtc_state,
2737 struct drm_atomic_state *old_state)
2739 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2740 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2741 struct drm_connector_state *conn_state;
2742 struct drm_connector *conn;
2745 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
2746 struct intel_encoder *encoder =
2747 to_intel_encoder(conn_state->best_encoder);
2751 if (conn_state->crtc != crtc)
2754 port = encoder->port;
2755 mutex_lock(&dev_priv->dpll_lock);
2757 val = I915_READ(DPCLKA_CFGCR0_ICL);
2758 WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
2760 if (port == PORT_A || port == PORT_B) {
2761 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2762 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2763 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2764 POSTING_READ(DPCLKA_CFGCR0_ICL);
2767 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2768 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2770 mutex_unlock(&dev_priv->dpll_lock);
2774 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
2775 struct intel_crtc_state *crtc_state,
2776 struct drm_atomic_state *old_state)
2778 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2779 struct drm_connector_state *old_conn_state;
2780 struct drm_connector *conn;
2783 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
2784 struct intel_encoder *encoder =
2785 to_intel_encoder(old_conn_state->best_encoder);
2788 if (old_conn_state->crtc != crtc)
2791 port = encoder->port;
2792 mutex_lock(&dev_priv->dpll_lock);
2793 I915_WRITE(DPCLKA_CFGCR0_ICL,
2794 I915_READ(DPCLKA_CFGCR0_ICL) |
2795 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2796 mutex_unlock(&dev_priv->dpll_lock);
2800 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2801 const struct intel_shared_dpll *pll)
2803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2804 enum port port = encoder->port;
2810 mutex_lock(&dev_priv->dpll_lock);
2812 if (IS_ICELAKE(dev_priv)) {
2814 I915_WRITE(DDI_CLK_SEL(port),
2815 icl_pll_to_ddi_pll_sel(encoder, pll));
2816 } else if (IS_CANNONLAKE(dev_priv)) {
2817 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2818 val = I915_READ(DPCLKA_CFGCR0);
2819 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2820 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2821 I915_WRITE(DPCLKA_CFGCR0, val);
2824 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2825 * This step and the step before must be done with separate
2828 val = I915_READ(DPCLKA_CFGCR0);
2829 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2830 I915_WRITE(DPCLKA_CFGCR0, val);
2831 } else if (IS_GEN9_BC(dev_priv)) {
2832 /* DDI -> PLL mapping */
2833 val = I915_READ(DPLL_CTRL2);
2835 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2836 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2837 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2838 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2840 I915_WRITE(DPLL_CTRL2, val);
2842 } else if (INTEL_GEN(dev_priv) < 9) {
2843 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2846 mutex_unlock(&dev_priv->dpll_lock);
2849 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2851 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2852 enum port port = encoder->port;
2854 if (IS_ICELAKE(dev_priv)) {
2856 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2857 } else if (IS_CANNONLAKE(dev_priv)) {
2858 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2859 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2860 } else if (IS_GEN9_BC(dev_priv)) {
2861 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2862 DPLL_CTRL2_DDI_CLK_OFF(port));
2863 } else if (INTEL_GEN(dev_priv) < 9) {
2864 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2868 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2869 const struct intel_crtc_state *crtc_state,
2870 const struct drm_connector_state *conn_state)
2872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2874 enum port port = encoder->port;
2875 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2876 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2877 int level = intel_ddi_dp_level(intel_dp);
2879 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2881 intel_display_power_get(dev_priv,
2882 intel_ddi_main_link_aux_domain(intel_dp));
2884 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2885 crtc_state->lane_count, is_mst);
2887 intel_edp_panel_on(intel_dp);
2889 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2891 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2893 icl_program_mg_dp_mode(intel_dp);
2894 icl_disable_phy_clock_gating(dig_port);
2896 if (IS_ICELAKE(dev_priv))
2897 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2898 level, encoder->type);
2899 else if (IS_CANNONLAKE(dev_priv))
2900 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2901 else if (IS_GEN9_LP(dev_priv))
2902 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2904 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2906 intel_ddi_init_dp_buf_reg(encoder);
2908 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2909 intel_dp_start_link_train(intel_dp);
2910 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2911 intel_dp_stop_link_train(intel_dp);
2913 icl_enable_phy_clock_gating(dig_port);
2915 intel_ddi_enable_pipe_clock(crtc_state);
2918 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2919 const struct intel_crtc_state *crtc_state,
2920 const struct drm_connector_state *conn_state)
2922 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2923 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2924 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2925 enum port port = encoder->port;
2926 int level = intel_ddi_hdmi_level(dev_priv, port);
2927 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2929 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2930 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2932 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2934 if (IS_ICELAKE(dev_priv))
2935 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
2936 level, INTEL_OUTPUT_HDMI);
2937 else if (IS_CANNONLAKE(dev_priv))
2938 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2939 else if (IS_GEN9_LP(dev_priv))
2940 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2942 intel_prepare_hdmi_ddi_buffers(encoder, level);
2944 if (IS_GEN9_BC(dev_priv))
2945 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2947 intel_ddi_enable_pipe_clock(crtc_state);
2949 intel_dig_port->set_infoframes(&encoder->base,
2950 crtc_state->has_infoframe,
2951 crtc_state, conn_state);
2954 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2955 const struct intel_crtc_state *crtc_state,
2956 const struct drm_connector_state *conn_state)
2958 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2959 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2960 enum pipe pipe = crtc->pipe;
2963 * When called from DP MST code:
2964 * - conn_state will be NULL
2965 * - encoder will be the main encoder (ie. mst->primary)
2966 * - the main connector associated with this port
2967 * won't be active or linked to a crtc
2968 * - crtc_state will be the state of the first stream to
2969 * be activated on this port, and it may not be the same
2970 * stream that will be deactivated last, but each stream
2971 * should have a state that is identical when it comes to
2972 * the DP link parameteres
2975 WARN_ON(crtc_state->has_pch_encoder);
2977 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2979 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2980 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2982 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2985 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2987 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2988 enum port port = encoder->port;
2992 val = I915_READ(DDI_BUF_CTL(port));
2993 if (val & DDI_BUF_CTL_ENABLE) {
2994 val &= ~DDI_BUF_CTL_ENABLE;
2995 I915_WRITE(DDI_BUF_CTL(port), val);
2999 val = I915_READ(DP_TP_CTL(port));
3000 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3001 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3002 I915_WRITE(DP_TP_CTL(port), val);
3005 intel_wait_ddi_buf_idle(dev_priv, port);
3008 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3009 const struct intel_crtc_state *old_crtc_state,
3010 const struct drm_connector_state *old_conn_state)
3012 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3013 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3014 struct intel_dp *intel_dp = &dig_port->dp;
3015 bool is_mst = intel_crtc_has_type(old_crtc_state,
3016 INTEL_OUTPUT_DP_MST);
3018 intel_ddi_disable_pipe_clock(old_crtc_state);
3021 * Power down sink before disabling the port, otherwise we end
3022 * up getting interrupts from the sink on detecting link loss.
3025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3027 intel_disable_ddi_buf(encoder);
3029 intel_edp_panel_vdd_on(intel_dp);
3030 intel_edp_panel_off(intel_dp);
3032 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3034 intel_ddi_clk_disable(encoder);
3036 intel_display_power_put(dev_priv,
3037 intel_ddi_main_link_aux_domain(intel_dp));
3040 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3041 const struct intel_crtc_state *old_crtc_state,
3042 const struct drm_connector_state *old_conn_state)
3044 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3045 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3046 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3048 dig_port->set_infoframes(&encoder->base, false,
3049 old_crtc_state, old_conn_state);
3051 intel_ddi_disable_pipe_clock(old_crtc_state);
3053 intel_disable_ddi_buf(encoder);
3055 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3057 intel_ddi_clk_disable(encoder);
3059 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3062 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3063 const struct intel_crtc_state *old_crtc_state,
3064 const struct drm_connector_state *old_conn_state)
3067 * When called from DP MST code:
3068 * - old_conn_state will be NULL
3069 * - encoder will be the main encoder (ie. mst->primary)
3070 * - the main connector associated with this port
3071 * won't be active or linked to a crtc
3072 * - old_crtc_state will be the state of the last stream to
3073 * be deactivated on this port, and it may not be the same
3074 * stream that was activated last, but each stream
3075 * should have a state that is identical when it comes to
3076 * the DP link parameteres
3079 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3080 intel_ddi_post_disable_hdmi(encoder,
3081 old_crtc_state, old_conn_state);
3083 intel_ddi_post_disable_dp(encoder,
3084 old_crtc_state, old_conn_state);
3087 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3088 const struct intel_crtc_state *old_crtc_state,
3089 const struct drm_connector_state *old_conn_state)
3091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3095 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3096 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3097 * step 13 is the correct place for it. Step 18 is where it was
3098 * originally before the BUN.
3100 val = I915_READ(FDI_RX_CTL(PIPE_A));
3101 val &= ~FDI_RX_ENABLE;
3102 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3104 intel_disable_ddi_buf(encoder);
3105 intel_ddi_clk_disable(encoder);
3107 val = I915_READ(FDI_RX_MISC(PIPE_A));
3108 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3109 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3110 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3112 val = I915_READ(FDI_RX_CTL(PIPE_A));
3114 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3116 val = I915_READ(FDI_RX_CTL(PIPE_A));
3117 val &= ~FDI_RX_PLL_ENABLE;
3118 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3121 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3122 const struct intel_crtc_state *crtc_state,
3123 const struct drm_connector_state *conn_state)
3125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3126 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3127 enum port port = encoder->port;
3129 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3130 intel_dp_stop_link_train(intel_dp);
3132 intel_edp_backlight_on(crtc_state, conn_state);
3133 intel_psr_enable(intel_dp, crtc_state);
3134 intel_edp_drrs_enable(intel_dp, crtc_state);
3136 if (crtc_state->has_audio)
3137 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3140 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3141 const struct intel_crtc_state *crtc_state,
3142 const struct drm_connector_state *conn_state)
3144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3145 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3146 struct drm_connector *connector = conn_state->connector;
3147 enum port port = encoder->port;
3149 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3150 crtc_state->hdmi_high_tmds_clock_ratio,
3151 crtc_state->hdmi_scrambling))
3152 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3153 connector->base.id, connector->name);
3155 /* Display WA #1143: skl,kbl,cfl */
3156 if (IS_GEN9_BC(dev_priv)) {
3158 * For some reason these chicken bits have been
3159 * stuffed into a transcoder register, event though
3160 * the bits affect a specific DDI port rather than
3161 * a specific transcoder.
3163 static const enum transcoder port_to_transcoder[] = {
3164 [PORT_A] = TRANSCODER_EDP,
3165 [PORT_B] = TRANSCODER_A,
3166 [PORT_C] = TRANSCODER_B,
3167 [PORT_D] = TRANSCODER_C,
3168 [PORT_E] = TRANSCODER_A,
3170 enum transcoder transcoder = port_to_transcoder[port];
3173 val = I915_READ(CHICKEN_TRANS(transcoder));
3176 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3177 DDIE_TRAINING_OVERRIDE_VALUE;
3179 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3180 DDI_TRAINING_OVERRIDE_VALUE;
3182 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3183 POSTING_READ(CHICKEN_TRANS(transcoder));
3188 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3189 DDIE_TRAINING_OVERRIDE_VALUE);
3191 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3192 DDI_TRAINING_OVERRIDE_VALUE);
3194 I915_WRITE(CHICKEN_TRANS(transcoder), val);
3197 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3198 * are ignored so nothing special needs to be done besides
3199 * enabling the port.
3201 I915_WRITE(DDI_BUF_CTL(port),
3202 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3204 if (crtc_state->has_audio)
3205 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3208 static void intel_enable_ddi(struct intel_encoder *encoder,
3209 const struct intel_crtc_state *crtc_state,
3210 const struct drm_connector_state *conn_state)
3212 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3213 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3215 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3217 /* Enable hdcp if it's desired */
3218 if (conn_state->content_protection ==
3219 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3220 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3223 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3224 const struct intel_crtc_state *old_crtc_state,
3225 const struct drm_connector_state *old_conn_state)
3227 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3229 intel_dp->link_trained = false;
3231 if (old_crtc_state->has_audio)
3232 intel_audio_codec_disable(encoder,
3233 old_crtc_state, old_conn_state);
3235 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3236 intel_psr_disable(intel_dp, old_crtc_state);
3237 intel_edp_backlight_off(old_conn_state);
3240 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3241 const struct intel_crtc_state *old_crtc_state,
3242 const struct drm_connector_state *old_conn_state)
3244 struct drm_connector *connector = old_conn_state->connector;
3246 if (old_crtc_state->has_audio)
3247 intel_audio_codec_disable(encoder,
3248 old_crtc_state, old_conn_state);
3250 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3252 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3253 connector->base.id, connector->name);
3256 static void intel_disable_ddi(struct intel_encoder *encoder,
3257 const struct intel_crtc_state *old_crtc_state,
3258 const struct drm_connector_state *old_conn_state)
3260 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3262 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3263 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3265 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3268 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
3269 const struct intel_crtc_state *pipe_config,
3270 const struct drm_connector_state *conn_state)
3272 uint8_t mask = pipe_config->lane_lat_optim_mask;
3274 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
3277 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3280 struct drm_i915_private *dev_priv =
3281 to_i915(intel_dig_port->base.base.dev);
3282 enum port port = intel_dig_port->base.port;
3286 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3287 val = I915_READ(DDI_BUF_CTL(port));
3288 if (val & DDI_BUF_CTL_ENABLE) {
3289 val &= ~DDI_BUF_CTL_ENABLE;
3290 I915_WRITE(DDI_BUF_CTL(port), val);
3294 val = I915_READ(DP_TP_CTL(port));
3295 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3296 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3297 I915_WRITE(DP_TP_CTL(port), val);
3298 POSTING_READ(DP_TP_CTL(port));
3301 intel_wait_ddi_buf_idle(dev_priv, port);
3304 val = DP_TP_CTL_ENABLE |
3305 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3306 if (intel_dp->link_mst)
3307 val |= DP_TP_CTL_MODE_MST;
3309 val |= DP_TP_CTL_MODE_SST;
3310 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3311 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3313 I915_WRITE(DP_TP_CTL(port), val);
3314 POSTING_READ(DP_TP_CTL(port));
3316 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3317 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3318 POSTING_READ(DDI_BUF_CTL(port));
3323 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3324 enum transcoder cpu_transcoder)
3326 if (cpu_transcoder == TRANSCODER_EDP)
3329 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3332 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3333 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3336 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3337 struct intel_crtc_state *crtc_state)
3339 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3340 crtc_state->min_voltage_level = 2;
3341 else if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3342 crtc_state->min_voltage_level = 1;
3345 void intel_ddi_get_config(struct intel_encoder *encoder,
3346 struct intel_crtc_state *pipe_config)
3348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3349 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3350 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3351 struct intel_digital_port *intel_dig_port;
3352 u32 temp, flags = 0;
3354 /* XXX: DSI transcoder paranoia */
3355 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3358 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3359 if (temp & TRANS_DDI_PHSYNC)
3360 flags |= DRM_MODE_FLAG_PHSYNC;
3362 flags |= DRM_MODE_FLAG_NHSYNC;
3363 if (temp & TRANS_DDI_PVSYNC)
3364 flags |= DRM_MODE_FLAG_PVSYNC;
3366 flags |= DRM_MODE_FLAG_NVSYNC;
3368 pipe_config->base.adjusted_mode.flags |= flags;
3370 switch (temp & TRANS_DDI_BPC_MASK) {
3371 case TRANS_DDI_BPC_6:
3372 pipe_config->pipe_bpp = 18;
3374 case TRANS_DDI_BPC_8:
3375 pipe_config->pipe_bpp = 24;
3377 case TRANS_DDI_BPC_10:
3378 pipe_config->pipe_bpp = 30;
3380 case TRANS_DDI_BPC_12:
3381 pipe_config->pipe_bpp = 36;
3387 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3388 case TRANS_DDI_MODE_SELECT_HDMI:
3389 pipe_config->has_hdmi_sink = true;
3390 intel_dig_port = enc_to_dig_port(&encoder->base);
3392 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
3393 pipe_config->has_infoframe = true;
3395 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3396 TRANS_DDI_HDMI_SCRAMBLING_MASK)
3397 pipe_config->hdmi_scrambling = true;
3398 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3399 pipe_config->hdmi_high_tmds_clock_ratio = true;
3401 case TRANS_DDI_MODE_SELECT_DVI:
3402 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3403 pipe_config->lane_count = 4;
3405 case TRANS_DDI_MODE_SELECT_FDI:
3406 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3408 case TRANS_DDI_MODE_SELECT_DP_SST:
3409 if (encoder->type == INTEL_OUTPUT_EDP)
3410 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3412 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3413 pipe_config->lane_count =
3414 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3415 intel_dp_get_m_n(intel_crtc, pipe_config);
3417 case TRANS_DDI_MODE_SELECT_DP_MST:
3418 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3419 pipe_config->lane_count =
3420 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3421 intel_dp_get_m_n(intel_crtc, pipe_config);
3427 pipe_config->has_audio =
3428 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3430 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3431 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3433 * This is a big fat ugly hack.
3435 * Some machines in UEFI boot mode provide us a VBT that has 18
3436 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3437 * unknown we fail to light up. Yet the same BIOS boots up with
3438 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3439 * max, not what it tells us to use.
3441 * Note: This will still be broken if the eDP panel is not lit
3442 * up by the BIOS, and thus we can't get the mode at module
3445 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3446 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3447 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3450 intel_ddi_clock_get(encoder, pipe_config);
3452 if (IS_GEN9_LP(dev_priv))
3453 pipe_config->lane_lat_optim_mask =
3454 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3456 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3459 static enum intel_output_type
3460 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3461 struct intel_crtc_state *crtc_state,
3462 struct drm_connector_state *conn_state)
3464 switch (conn_state->connector->connector_type) {
3465 case DRM_MODE_CONNECTOR_HDMIA:
3466 return INTEL_OUTPUT_HDMI;
3467 case DRM_MODE_CONNECTOR_eDP:
3468 return INTEL_OUTPUT_EDP;
3469 case DRM_MODE_CONNECTOR_DisplayPort:
3470 return INTEL_OUTPUT_DP;
3472 MISSING_CASE(conn_state->connector->connector_type);
3473 return INTEL_OUTPUT_UNUSED;
3477 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3478 struct intel_crtc_state *pipe_config,
3479 struct drm_connector_state *conn_state)
3481 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3482 enum port port = encoder->port;
3486 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3488 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3489 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3491 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3493 if (IS_GEN9_LP(dev_priv) && ret)
3494 pipe_config->lane_lat_optim_mask =
3495 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3497 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3503 static const struct drm_encoder_funcs intel_ddi_funcs = {
3504 .reset = intel_dp_encoder_reset,
3505 .destroy = intel_dp_encoder_destroy,
3508 static struct intel_connector *
3509 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3511 struct intel_connector *connector;
3512 enum port port = intel_dig_port->base.port;
3514 connector = intel_connector_alloc();
3518 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3519 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3527 static int modeset_pipe(struct drm_crtc *crtc,
3528 struct drm_modeset_acquire_ctx *ctx)
3530 struct drm_atomic_state *state;
3531 struct drm_crtc_state *crtc_state;
3534 state = drm_atomic_state_alloc(crtc->dev);
3538 state->acquire_ctx = ctx;
3540 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3541 if (IS_ERR(crtc_state)) {
3542 ret = PTR_ERR(crtc_state);
3546 crtc_state->mode_changed = true;
3548 ret = drm_atomic_add_affected_connectors(state, crtc);
3552 ret = drm_atomic_add_affected_planes(state, crtc);
3556 ret = drm_atomic_commit(state);
3563 drm_atomic_state_put(state);
3568 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3569 struct drm_modeset_acquire_ctx *ctx)
3571 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3572 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3573 struct intel_connector *connector = hdmi->attached_connector;
3574 struct i2c_adapter *adapter =
3575 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3576 struct drm_connector_state *conn_state;
3577 struct intel_crtc_state *crtc_state;
3578 struct intel_crtc *crtc;
3582 if (!connector || connector->base.status != connector_status_connected)
3585 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3590 conn_state = connector->base.state;
3592 crtc = to_intel_crtc(conn_state->crtc);
3596 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3600 crtc_state = to_intel_crtc_state(crtc->base.state);
3602 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3604 if (!crtc_state->base.active)
3607 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3608 !crtc_state->hdmi_scrambling)
3611 if (conn_state->commit &&
3612 !try_wait_for_completion(&conn_state->commit->hw_done))
3615 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3617 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3621 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3622 crtc_state->hdmi_high_tmds_clock_ratio &&
3623 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3624 crtc_state->hdmi_scrambling)
3628 * HDMI 2.0 says that one should not send scrambled data
3629 * prior to configuring the sink scrambling, and that
3630 * TMDS clock/data transmission should be suspended when
3631 * changing the TMDS clock rate in the sink. So let's
3632 * just do a full modeset here, even though some sinks
3633 * would be perfectly happy if were to just reconfigure
3634 * the SCDC settings on the fly.
3636 return modeset_pipe(&crtc->base, ctx);
3639 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3640 struct intel_connector *connector)
3642 struct drm_modeset_acquire_ctx ctx;
3646 changed = intel_encoder_hotplug(encoder, connector);
3648 drm_modeset_acquire_init(&ctx, 0);
3651 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3652 ret = intel_hdmi_reset_link(encoder, &ctx);
3654 ret = intel_dp_retrain_link(encoder, &ctx);
3656 if (ret == -EDEADLK) {
3657 drm_modeset_backoff(&ctx);
3664 drm_modeset_drop_locks(&ctx);
3665 drm_modeset_acquire_fini(&ctx);
3666 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
3671 static struct intel_connector *
3672 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3674 struct intel_connector *connector;
3675 enum port port = intel_dig_port->base.port;
3677 connector = intel_connector_alloc();
3681 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3682 intel_hdmi_init_connector(intel_dig_port, connector);
3687 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
3689 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
3691 if (dport->base.port != PORT_A)
3694 if (dport->saved_port_bits & DDI_A_4_LANES)
3697 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
3698 * supported configuration
3700 if (IS_GEN9_LP(dev_priv))
3703 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
3704 * one who does also have a full A/E split called
3705 * DDI_F what makes DDI_E useless. However for this
3706 * case let's trust VBT info.
3708 if (IS_CANNONLAKE(dev_priv) &&
3709 !intel_bios_is_port_present(dev_priv, PORT_E))
3716 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
3718 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
3719 enum port port = intel_dport->base.port;
3722 if (INTEL_GEN(dev_priv) >= 11)
3725 if (port == PORT_A || port == PORT_E) {
3726 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
3727 max_lanes = port == PORT_A ? 4 : 0;
3729 /* Both A and E share 2 lanes */
3734 * Some BIOS might fail to set this bit on port A if eDP
3735 * wasn't lit up at boot. Force this bit set when needed
3736 * so we use the proper lane count for our calculations.
3738 if (intel_ddi_a_force_4_lanes(intel_dport)) {
3739 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
3740 intel_dport->saved_port_bits |= DDI_A_4_LANES;
3747 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
3749 struct intel_digital_port *intel_dig_port;
3750 struct intel_encoder *intel_encoder;
3751 struct drm_encoder *encoder;
3752 bool init_hdmi, init_dp, init_lspcon = false;
3755 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3756 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3757 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3759 if (intel_bios_is_lspcon_present(dev_priv, port)) {
3761 * Lspcon device needs to be driven with DP connector
3762 * with special detection sequence. So make sure DP
3763 * is initialized before lspcon.
3768 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
3771 if (!init_dp && !init_hdmi) {
3772 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3777 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3778 if (!intel_dig_port)
3781 intel_encoder = &intel_dig_port->base;
3782 encoder = &intel_encoder->base;
3784 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
3785 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
3787 intel_encoder->hotplug = intel_ddi_hotplug;
3788 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
3789 intel_encoder->compute_config = intel_ddi_compute_config;
3790 intel_encoder->enable = intel_enable_ddi;
3791 if (IS_GEN9_LP(dev_priv))
3792 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
3793 intel_encoder->pre_enable = intel_ddi_pre_enable;
3794 intel_encoder->disable = intel_disable_ddi;
3795 intel_encoder->post_disable = intel_ddi_post_disable;
3796 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3797 intel_encoder->get_config = intel_ddi_get_config;
3798 intel_encoder->suspend = intel_dp_encoder_suspend;
3799 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
3800 intel_encoder->type = INTEL_OUTPUT_DDI;
3801 intel_encoder->power_domain = intel_port_to_power_domain(port);
3802 intel_encoder->port = port;
3803 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3804 intel_encoder->cloneable = 0;
3806 if (INTEL_GEN(dev_priv) >= 11)
3807 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3808 DDI_BUF_PORT_REVERSAL;
3810 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3811 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
3812 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3813 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
3817 intel_dig_port->ddi_io_power_domain =
3818 POWER_DOMAIN_PORT_DDI_A_IO;
3821 intel_dig_port->ddi_io_power_domain =
3822 POWER_DOMAIN_PORT_DDI_B_IO;
3825 intel_dig_port->ddi_io_power_domain =
3826 POWER_DOMAIN_PORT_DDI_C_IO;
3829 intel_dig_port->ddi_io_power_domain =
3830 POWER_DOMAIN_PORT_DDI_D_IO;
3833 intel_dig_port->ddi_io_power_domain =
3834 POWER_DOMAIN_PORT_DDI_E_IO;
3837 intel_dig_port->ddi_io_power_domain =
3838 POWER_DOMAIN_PORT_DDI_F_IO;
3844 intel_infoframe_init(intel_dig_port);
3847 if (!intel_ddi_init_dp_connector(intel_dig_port))
3850 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3853 /* In theory we don't need the encoder->type check, but leave it just in
3854 * case we have some really bad VBTs... */
3855 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3856 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3861 if (lspcon_init(intel_dig_port))
3862 /* TODO: handle hdmi info frame part */
3863 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3867 * LSPCON init faied, but DP init was success, so
3868 * lets try to drive as DP++ port.
3870 DRM_ERROR("LSPCON init failed on port %c\n",
3877 drm_encoder_cleanup(encoder);
3878 kfree(intel_dig_port);