2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 static const u8 index_to_dp_signal_levels[] = {
38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
51 * them for both DP and FDI transports, allowing those ports to
52 * automatically adapt to HDMI connections as well
54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 { 0x00FFFFFF, 0x0006000E, 0x0 },
56 { 0x00D75FFF, 0x0005000A, 0x0 },
57 { 0x00C30FFF, 0x00040006, 0x0 },
58 { 0x80AAAFFF, 0x000B0000, 0x0 },
59 { 0x00FFFFFF, 0x0005000A, 0x0 },
60 { 0x00D75FFF, 0x000C0004, 0x0 },
61 { 0x80C30FFF, 0x000B0000, 0x0 },
62 { 0x00FFFFFF, 0x00040006, 0x0 },
63 { 0x80D75FFF, 0x000B0000, 0x0 },
66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 { 0x00FFFFFF, 0x0007000E, 0x0 },
68 { 0x00D75FFF, 0x000F000A, 0x0 },
69 { 0x00C30FFF, 0x00060006, 0x0 },
70 { 0x00AAAFFF, 0x001E0000, 0x0 },
71 { 0x00FFFFFF, 0x000F000A, 0x0 },
72 { 0x00D75FFF, 0x00160004, 0x0 },
73 { 0x00C30FFF, 0x001E0000, 0x0 },
74 { 0x00FFFFFF, 0x00060006, 0x0 },
75 { 0x00D75FFF, 0x001E0000, 0x0 },
78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
79 /* Idx NT mV d T mV d db */
80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 { 0x00FFFFFF, 0x00000012, 0x0 },
96 { 0x00EBAFFF, 0x00020011, 0x0 },
97 { 0x00C71FFF, 0x0006000F, 0x0 },
98 { 0x00AAAFFF, 0x000E000A, 0x0 },
99 { 0x00FFFFFF, 0x00020011, 0x0 },
100 { 0x00DB6FFF, 0x0005000F, 0x0 },
101 { 0x00BEEFFF, 0x000A000C, 0x0 },
102 { 0x00FFFFFF, 0x0005000F, 0x0 },
103 { 0x00DB6FFF, 0x000A000C, 0x0 },
106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 { 0x00FFFFFF, 0x0007000E, 0x0 },
108 { 0x00D75FFF, 0x000E000A, 0x0 },
109 { 0x00BEFFFF, 0x00140006, 0x0 },
110 { 0x80B2CFFF, 0x001B0002, 0x0 },
111 { 0x00FFFFFF, 0x000E000A, 0x0 },
112 { 0x00DB6FFF, 0x00160005, 0x0 },
113 { 0x80C71FFF, 0x001A0002, 0x0 },
114 { 0x00F7DFFF, 0x00180004, 0x0 },
115 { 0x80D75FFF, 0x001B0002, 0x0 },
118 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 { 0x00FFFFFF, 0x0001000E, 0x0 },
120 { 0x00D75FFF, 0x0004000A, 0x0 },
121 { 0x00C30FFF, 0x00070006, 0x0 },
122 { 0x00AAAFFF, 0x000C0000, 0x0 },
123 { 0x00FFFFFF, 0x0004000A, 0x0 },
124 { 0x00D75FFF, 0x00090004, 0x0 },
125 { 0x00C30FFF, 0x000C0000, 0x0 },
126 { 0x00FFFFFF, 0x00070006, 0x0 },
127 { 0x00D75FFF, 0x000C0000, 0x0 },
130 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
131 /* Idx NT mV d T mV df db */
132 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
144 /* Skylake H and S */
145 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A0, 0x0 },
147 { 0x00005012, 0x0000009B, 0x0 },
148 { 0x00007011, 0x00000088, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x00002016, 0x0000009B, 0x0 },
151 { 0x00005012, 0x00000088, 0x0 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x000000DF, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
158 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159 { 0x0000201B, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x1 },
162 { 0x80009010, 0x000000C0, 0x1 },
163 { 0x0000201B, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x1 },
165 { 0x80007011, 0x000000C0, 0x1 },
166 { 0x00002016, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x1 },
171 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 { 0x00000018, 0x000000A2, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000CD, 0x3 },
175 { 0x80009010, 0x000000C0, 0x3 },
176 { 0x00000018, 0x0000009D, 0x0 },
177 { 0x80005012, 0x000000C0, 0x3 },
178 { 0x80007011, 0x000000C0, 0x3 },
179 { 0x00000018, 0x00000088, 0x0 },
180 { 0x80005012, 0x000000C0, 0x3 },
183 /* Kabylake H and S */
184 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
185 { 0x00002016, 0x000000A0, 0x0 },
186 { 0x00005012, 0x0000009B, 0x0 },
187 { 0x00007011, 0x00000088, 0x0 },
188 { 0x80009010, 0x000000C0, 0x1 },
189 { 0x00002016, 0x0000009B, 0x0 },
190 { 0x00005012, 0x00000088, 0x0 },
191 { 0x80007011, 0x000000C0, 0x1 },
192 { 0x00002016, 0x00000097, 0x0 },
193 { 0x80005012, 0x000000C0, 0x1 },
197 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
198 { 0x0000201B, 0x000000A1, 0x0 },
199 { 0x00005012, 0x00000088, 0x0 },
200 { 0x80007011, 0x000000CD, 0x3 },
201 { 0x80009010, 0x000000C0, 0x3 },
202 { 0x0000201B, 0x0000009D, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 { 0x80007011, 0x000000C0, 0x3 },
205 { 0x00002016, 0x0000004F, 0x0 },
206 { 0x80005012, 0x000000C0, 0x3 },
210 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
211 { 0x00001017, 0x000000A1, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000CD, 0x3 },
214 { 0x8000800F, 0x000000C0, 0x3 },
215 { 0x00001017, 0x0000009D, 0x0 },
216 { 0x80005012, 0x000000C0, 0x3 },
217 { 0x80007011, 0x000000C0, 0x3 },
218 { 0x00001017, 0x0000004C, 0x0 },
219 { 0x80005012, 0x000000C0, 0x3 },
223 * Skylake/Kabylake H and S
224 * eDP 1.4 low vswing translation parameters
226 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 { 0x00000018, 0x000000A8, 0x0 },
228 { 0x00004013, 0x000000A9, 0x0 },
229 { 0x00007011, 0x000000A2, 0x0 },
230 { 0x00009010, 0x0000009C, 0x0 },
231 { 0x00000018, 0x000000A9, 0x0 },
232 { 0x00006013, 0x000000A2, 0x0 },
233 { 0x00007011, 0x000000A6, 0x0 },
234 { 0x00000018, 0x000000AB, 0x0 },
235 { 0x00007013, 0x0000009F, 0x0 },
236 { 0x00000018, 0x000000DF, 0x0 },
241 * eDP 1.4 low vswing translation parameters
243 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244 { 0x00000018, 0x000000A8, 0x0 },
245 { 0x00004013, 0x000000A9, 0x0 },
246 { 0x00007011, 0x000000A2, 0x0 },
247 { 0x00009010, 0x0000009C, 0x0 },
248 { 0x00000018, 0x000000A9, 0x0 },
249 { 0x00006013, 0x000000A2, 0x0 },
250 { 0x00007011, 0x000000A6, 0x0 },
251 { 0x00002016, 0x000000AB, 0x0 },
252 { 0x00005013, 0x0000009F, 0x0 },
253 { 0x00000018, 0x000000DF, 0x0 },
258 * eDP 1.4 low vswing translation parameters
260 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 { 0x00000018, 0x000000A8, 0x0 },
262 { 0x00004013, 0x000000AB, 0x0 },
263 { 0x00007011, 0x000000A4, 0x0 },
264 { 0x00009010, 0x000000DF, 0x0 },
265 { 0x00000018, 0x000000AA, 0x0 },
266 { 0x00006013, 0x000000A4, 0x0 },
267 { 0x00007011, 0x0000009D, 0x0 },
268 { 0x00000018, 0x000000A0, 0x0 },
269 { 0x00006012, 0x000000DF, 0x0 },
270 { 0x00000018, 0x0000008A, 0x0 },
273 /* Skylake/Kabylake U, H and S */
274 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 { 0x00000018, 0x000000AC, 0x0 },
276 { 0x00005012, 0x0000009D, 0x0 },
277 { 0x00007011, 0x00000088, 0x0 },
278 { 0x00000018, 0x000000A1, 0x0 },
279 { 0x00000018, 0x00000098, 0x0 },
280 { 0x00004013, 0x00000088, 0x0 },
281 { 0x80006012, 0x000000CD, 0x1 },
282 { 0x00000018, 0x000000DF, 0x0 },
283 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284 { 0x80003015, 0x000000C0, 0x1 },
285 { 0x80000018, 0x000000C0, 0x1 },
288 /* Skylake/Kabylake Y */
289 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 { 0x00000018, 0x000000A1, 0x0 },
291 { 0x00005012, 0x000000DF, 0x0 },
292 { 0x80007011, 0x000000CB, 0x3 },
293 { 0x00000018, 0x000000A4, 0x0 },
294 { 0x00000018, 0x0000009D, 0x0 },
295 { 0x00004013, 0x00000080, 0x0 },
296 { 0x80006013, 0x000000C0, 0x3 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299 { 0x80003015, 0x000000C0, 0x3 },
300 { 0x80000018, 0x000000C0, 0x3 },
303 struct bxt_ddi_buf_trans {
304 u8 margin; /* swing value */
305 u8 scale; /* scale value */
306 u8 enable; /* scale enable */
310 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
311 /* Idx NT mV diff db */
312 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
313 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
314 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
315 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
316 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
317 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
318 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
319 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
320 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
321 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
324 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
325 /* Idx NT mV diff db */
326 { 26, 0, 0, 128, }, /* 0: 200 0 */
327 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
328 { 48, 0, 0, 96, }, /* 2: 200 4 */
329 { 54, 0, 0, 69, }, /* 3: 200 6 */
330 { 32, 0, 0, 128, }, /* 4: 250 0 */
331 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
332 { 54, 0, 0, 85, }, /* 6: 250 4 */
333 { 43, 0, 0, 128, }, /* 7: 300 0 */
334 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
335 { 48, 0, 0, 128, }, /* 9: 300 0 */
338 /* BSpec has 2 recommended values - entries 0 and 8.
339 * Using the entry with higher vswing.
341 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
342 /* Idx NT mV diff db */
343 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
344 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
345 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
346 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
347 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
348 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
349 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
350 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
351 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
352 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
355 struct cnl_ddi_buf_trans {
359 u8 dw4_post_cursor_2;
360 u8 dw4_post_cursor_1;
363 /* Voltage Swing Programming for VccIO 0.85V for DP */
364 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
365 /* NT mV Trans mV db */
366 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
367 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
368 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
369 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
370 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
371 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
372 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
373 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
374 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
375 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
378 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
379 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
380 /* NT mV Trans mV db */
381 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
382 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
383 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
384 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
385 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
386 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
387 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
390 /* Voltage Swing Programming for VccIO 0.85V for eDP */
391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
394 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
395 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
396 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
397 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
398 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
399 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
400 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
401 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
404 /* Voltage Swing Programming for VccIO 0.95V for DP */
405 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
406 /* NT mV Trans mV db */
407 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
408 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
409 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
410 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
411 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
412 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
413 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
414 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
415 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
416 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
419 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
420 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
421 /* NT mV Trans mV db */
422 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
424 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
425 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
426 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
427 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
428 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
429 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
430 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
431 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
432 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
435 /* Voltage Swing Programming for VccIO 0.95V for eDP */
436 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
437 /* NT mV Trans mV db */
438 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
439 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
440 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
441 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
442 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
443 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
444 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
445 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
446 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
447 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
450 /* Voltage Swing Programming for VccIO 1.05V for DP */
451 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
452 /* NT mV Trans mV db */
453 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
454 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
455 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
456 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
457 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
458 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
459 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
460 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
461 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
462 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
465 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
466 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
467 /* NT mV Trans mV db */
468 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
470 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
471 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
472 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
473 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
474 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
475 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
476 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
477 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
478 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
481 /* Voltage Swing Programming for VccIO 1.05V for eDP */
482 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
483 /* NT mV Trans mV db */
484 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
485 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
486 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
487 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
488 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
489 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
490 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
491 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
492 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
495 static const struct ddi_buf_trans *
496 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
498 if (dev_priv->vbt.edp.low_vswing) {
499 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
500 return bdw_ddi_translations_edp;
502 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
503 return bdw_ddi_translations_dp;
507 static const struct ddi_buf_trans *
508 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
510 if (IS_SKL_ULX(dev_priv)) {
511 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
512 return skl_y_ddi_translations_dp;
513 } else if (IS_SKL_ULT(dev_priv)) {
514 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
515 return skl_u_ddi_translations_dp;
517 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
518 return skl_ddi_translations_dp;
522 static const struct ddi_buf_trans *
523 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
525 if (IS_KBL_ULX(dev_priv)) {
526 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
527 return kbl_y_ddi_translations_dp;
528 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
529 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
530 return kbl_u_ddi_translations_dp;
532 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
533 return kbl_ddi_translations_dp;
537 static const struct ddi_buf_trans *
538 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
540 if (dev_priv->vbt.edp.low_vswing) {
541 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
542 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
543 return skl_y_ddi_translations_edp;
544 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
545 IS_CFL_ULT(dev_priv)) {
546 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
547 return skl_u_ddi_translations_edp;
549 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
550 return skl_ddi_translations_edp;
554 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
555 return kbl_get_buf_trans_dp(dev_priv, n_entries);
557 return skl_get_buf_trans_dp(dev_priv, n_entries);
560 static const struct ddi_buf_trans *
561 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
563 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
564 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
565 return skl_y_ddi_translations_hdmi;
567 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
568 return skl_ddi_translations_hdmi;
572 static int skl_buf_trans_num_entries(enum port port, int n_entries)
574 /* Only DDIA and DDIE can select the 10th register with DP */
575 if (port == PORT_A || port == PORT_E)
576 return min(n_entries, 10);
578 return min(n_entries, 9);
581 static const struct ddi_buf_trans *
582 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
583 enum port port, int *n_entries)
585 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
586 const struct ddi_buf_trans *ddi_translations =
587 kbl_get_buf_trans_dp(dev_priv, n_entries);
588 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
589 return ddi_translations;
590 } else if (IS_SKYLAKE(dev_priv)) {
591 const struct ddi_buf_trans *ddi_translations =
592 skl_get_buf_trans_dp(dev_priv, n_entries);
593 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
594 return ddi_translations;
595 } else if (IS_BROADWELL(dev_priv)) {
596 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
597 return bdw_ddi_translations_dp;
598 } else if (IS_HASWELL(dev_priv)) {
599 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
600 return hsw_ddi_translations_dp;
607 static const struct ddi_buf_trans *
608 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
609 enum port port, int *n_entries)
611 if (IS_GEN9_BC(dev_priv)) {
612 const struct ddi_buf_trans *ddi_translations =
613 skl_get_buf_trans_edp(dev_priv, n_entries);
614 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
615 return ddi_translations;
616 } else if (IS_BROADWELL(dev_priv)) {
617 return bdw_get_buf_trans_edp(dev_priv, n_entries);
618 } else if (IS_HASWELL(dev_priv)) {
619 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
620 return hsw_ddi_translations_dp;
627 static const struct ddi_buf_trans *
628 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
631 if (IS_BROADWELL(dev_priv)) {
632 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
633 return bdw_ddi_translations_fdi;
634 } else if (IS_HASWELL(dev_priv)) {
635 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
636 return hsw_ddi_translations_fdi;
643 static const struct ddi_buf_trans *
644 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
647 if (IS_GEN9_BC(dev_priv)) {
648 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
649 } else if (IS_BROADWELL(dev_priv)) {
650 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
651 return bdw_ddi_translations_hdmi;
652 } else if (IS_HASWELL(dev_priv)) {
653 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
654 return hsw_ddi_translations_hdmi;
661 static const struct bxt_ddi_buf_trans *
662 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
664 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
665 return bxt_ddi_translations_dp;
668 static const struct bxt_ddi_buf_trans *
669 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
671 if (dev_priv->vbt.edp.low_vswing) {
672 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
673 return bxt_ddi_translations_edp;
676 return bxt_get_buf_trans_dp(dev_priv, n_entries);
679 static const struct bxt_ddi_buf_trans *
680 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
682 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
683 return bxt_ddi_translations_hdmi;
686 static const struct cnl_ddi_buf_trans *
687 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
689 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
691 if (voltage == VOLTAGE_INFO_0_85V) {
692 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
693 return cnl_ddi_translations_hdmi_0_85V;
694 } else if (voltage == VOLTAGE_INFO_0_95V) {
695 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
696 return cnl_ddi_translations_hdmi_0_95V;
697 } else if (voltage == VOLTAGE_INFO_1_05V) {
698 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
699 return cnl_ddi_translations_hdmi_1_05V;
701 *n_entries = 1; /* shut up gcc */
702 MISSING_CASE(voltage);
707 static const struct cnl_ddi_buf_trans *
708 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
710 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
712 if (voltage == VOLTAGE_INFO_0_85V) {
713 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
714 return cnl_ddi_translations_dp_0_85V;
715 } else if (voltage == VOLTAGE_INFO_0_95V) {
716 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
717 return cnl_ddi_translations_dp_0_95V;
718 } else if (voltage == VOLTAGE_INFO_1_05V) {
719 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
720 return cnl_ddi_translations_dp_1_05V;
722 *n_entries = 1; /* shut up gcc */
723 MISSING_CASE(voltage);
728 static const struct cnl_ddi_buf_trans *
729 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
731 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
733 if (dev_priv->vbt.edp.low_vswing) {
734 if (voltage == VOLTAGE_INFO_0_85V) {
735 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
736 return cnl_ddi_translations_edp_0_85V;
737 } else if (voltage == VOLTAGE_INFO_0_95V) {
738 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
739 return cnl_ddi_translations_edp_0_95V;
740 } else if (voltage == VOLTAGE_INFO_1_05V) {
741 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
742 return cnl_ddi_translations_edp_1_05V;
744 *n_entries = 1; /* shut up gcc */
745 MISSING_CASE(voltage);
749 return cnl_get_buf_trans_dp(dev_priv, n_entries);
753 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
755 int n_entries, level, default_entry;
757 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
759 if (IS_CANNONLAKE(dev_priv)) {
760 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
761 default_entry = n_entries - 1;
762 } else if (IS_GEN9_LP(dev_priv)) {
763 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
764 default_entry = n_entries - 1;
765 } else if (IS_GEN9_BC(dev_priv)) {
766 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
768 } else if (IS_BROADWELL(dev_priv)) {
769 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
771 } else if (IS_HASWELL(dev_priv)) {
772 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
775 WARN(1, "ddi translation table missing\n");
779 /* Choose a good default if VBT is badly populated */
780 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
781 level = default_entry;
783 if (WARN_ON_ONCE(n_entries == 0))
785 if (WARN_ON_ONCE(level >= n_entries))
786 level = n_entries - 1;
792 * Starting with Haswell, DDI port buffers must be programmed with correct
793 * values in advance. This function programs the correct values for
794 * DP/eDP/FDI use cases.
796 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
797 const struct intel_crtc_state *crtc_state)
799 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
802 enum port port = encoder->port;
803 const struct ddi_buf_trans *ddi_translations;
805 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
806 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
808 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
809 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
812 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
815 /* If we're boosting the current, set bit 31 of trans1 */
816 if (IS_GEN9_BC(dev_priv) &&
817 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
818 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
820 for (i = 0; i < n_entries; i++) {
821 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
822 ddi_translations[i].trans1 | iboost_bit);
823 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
824 ddi_translations[i].trans2);
829 * Starting with Haswell, DDI port buffers must be programmed with correct
830 * values in advance. This function programs the correct values for
831 * HDMI/DVI use cases.
833 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
836 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
839 enum port port = encoder->port;
840 const struct ddi_buf_trans *ddi_translations;
842 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
844 if (WARN_ON_ONCE(!ddi_translations))
846 if (WARN_ON_ONCE(level >= n_entries))
847 level = n_entries - 1;
849 /* If we're boosting the current, set bit 31 of trans1 */
850 if (IS_GEN9_BC(dev_priv) &&
851 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
852 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
854 /* Entry 9 is for HDMI: */
855 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
856 ddi_translations[level].trans1 | iboost_bit);
857 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
858 ddi_translations[level].trans2);
861 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
864 i915_reg_t reg = DDI_BUF_CTL(port);
867 for (i = 0; i < 16; i++) {
869 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
872 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
875 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
879 return PORT_CLK_SEL_WRPLL1;
881 return PORT_CLK_SEL_WRPLL2;
883 return PORT_CLK_SEL_SPLL;
884 case DPLL_ID_LCPLL_810:
885 return PORT_CLK_SEL_LCPLL_810;
886 case DPLL_ID_LCPLL_1350:
887 return PORT_CLK_SEL_LCPLL_1350;
888 case DPLL_ID_LCPLL_2700:
889 return PORT_CLK_SEL_LCPLL_2700;
891 MISSING_CASE(pll->id);
892 return PORT_CLK_SEL_NONE;
896 /* Starting with Haswell, different DDI ports can work in FDI mode for
897 * connection to the PCH-located connectors. For this, it is necessary to train
898 * both the DDI port and PCH receiver for the desired DDI buffer settings.
900 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
901 * please note that when FDI mode is active on DDI E, it shares 2 lines with
902 * DDI A (which is used for eDP)
905 void hsw_fdi_link_train(struct intel_crtc *crtc,
906 const struct intel_crtc_state *crtc_state)
908 struct drm_device *dev = crtc->base.dev;
909 struct drm_i915_private *dev_priv = to_i915(dev);
910 struct intel_encoder *encoder;
911 u32 temp, i, rx_ctl_val, ddi_pll_sel;
913 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
914 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
915 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
918 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
919 * mode set "sequence for CRT port" document:
920 * - TP1 to TP2 time with the default value
923 * WaFDIAutoLinkSetTimingOverrride:hsw
925 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
926 FDI_RX_PWRDN_LANE0_VAL(2) |
927 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
929 /* Enable the PCH Receiver FDI PLL */
930 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
932 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
933 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
934 POSTING_READ(FDI_RX_CTL(PIPE_A));
937 /* Switch from Rawclk to PCDclk */
938 rx_ctl_val |= FDI_PCDCLK;
939 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
941 /* Configure Port Clock Select */
942 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
943 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
944 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
946 /* Start the training iterating through available voltages and emphasis,
947 * testing each value twice. */
948 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
949 /* Configure DP_TP_CTL with auto-training */
950 I915_WRITE(DP_TP_CTL(PORT_E),
951 DP_TP_CTL_FDI_AUTOTRAIN |
952 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
953 DP_TP_CTL_LINK_TRAIN_PAT1 |
956 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
957 * DDI E does not support port reversal, the functionality is
958 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
959 * port reversal bit */
960 I915_WRITE(DDI_BUF_CTL(PORT_E),
962 ((crtc_state->fdi_lanes - 1) << 1) |
963 DDI_BUF_TRANS_SELECT(i / 2));
964 POSTING_READ(DDI_BUF_CTL(PORT_E));
968 /* Program PCH FDI Receiver TU */
969 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
971 /* Enable PCH FDI Receiver with auto-training */
972 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
973 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
974 POSTING_READ(FDI_RX_CTL(PIPE_A));
976 /* Wait for FDI receiver lane calibration */
979 /* Unset FDI_RX_MISC pwrdn lanes */
980 temp = I915_READ(FDI_RX_MISC(PIPE_A));
981 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
982 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
983 POSTING_READ(FDI_RX_MISC(PIPE_A));
985 /* Wait for FDI auto training time */
988 temp = I915_READ(DP_TP_STATUS(PORT_E));
989 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
990 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
995 * Leave things enabled even if we failed to train FDI.
996 * Results in less fireworks from the state checker.
998 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
999 DRM_ERROR("FDI link training failed!\n");
1003 rx_ctl_val &= ~FDI_RX_ENABLE;
1004 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1005 POSTING_READ(FDI_RX_CTL(PIPE_A));
1007 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1008 temp &= ~DDI_BUF_CTL_ENABLE;
1009 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1010 POSTING_READ(DDI_BUF_CTL(PORT_E));
1012 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1013 temp = I915_READ(DP_TP_CTL(PORT_E));
1014 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1015 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1016 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1017 POSTING_READ(DP_TP_CTL(PORT_E));
1019 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1021 /* Reset FDI_RX_MISC pwrdn lanes */
1022 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1023 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1024 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1025 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1026 POSTING_READ(FDI_RX_MISC(PIPE_A));
1029 /* Enable normal pixel sending for FDI */
1030 I915_WRITE(DP_TP_CTL(PORT_E),
1031 DP_TP_CTL_FDI_AUTOTRAIN |
1032 DP_TP_CTL_LINK_TRAIN_NORMAL |
1033 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1037 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1039 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1040 struct intel_digital_port *intel_dig_port =
1041 enc_to_dig_port(&encoder->base);
1043 intel_dp->DP = intel_dig_port->saved_port_bits |
1044 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1045 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1048 static struct intel_encoder *
1049 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1051 struct drm_device *dev = crtc->base.dev;
1052 struct intel_encoder *encoder, *ret = NULL;
1053 int num_encoders = 0;
1055 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1060 if (num_encoders != 1)
1061 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1062 pipe_name(crtc->pipe));
1064 BUG_ON(ret == NULL);
1068 /* Finds the only possible encoder associated with the given CRTC. */
1069 struct intel_encoder *
1070 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
1072 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1073 struct intel_encoder *ret = NULL;
1074 struct drm_atomic_state *state;
1075 struct drm_connector *connector;
1076 struct drm_connector_state *connector_state;
1077 int num_encoders = 0;
1080 state = crtc_state->base.state;
1082 for_each_new_connector_in_state(state, connector, connector_state, i) {
1083 if (connector_state->crtc != crtc_state->base.crtc)
1086 ret = to_intel_encoder(connector_state->best_encoder);
1090 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
1091 pipe_name(crtc->pipe));
1093 BUG_ON(ret == NULL);
1097 #define LC_FREQ 2700
1099 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1102 int refclk = LC_FREQ;
1106 wrpll = I915_READ(reg);
1107 switch (wrpll & WRPLL_PLL_REF_MASK) {
1109 case WRPLL_PLL_NON_SSC:
1111 * We could calculate spread here, but our checking
1112 * code only cares about 5% accuracy, and spread is a max of
1117 case WRPLL_PLL_LCPLL:
1121 WARN(1, "bad wrpll refclk\n");
1125 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1126 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1127 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1129 /* Convert to KHz, p & r have a fixed point portion */
1130 return (refclk * n * 100) / (p * r);
1133 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1134 enum intel_dpll_id pll_id)
1136 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1137 uint32_t cfgcr1_val, cfgcr2_val;
1138 uint32_t p0, p1, p2, dco_freq;
1140 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1141 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1143 cfgcr1_val = I915_READ(cfgcr1_reg);
1144 cfgcr2_val = I915_READ(cfgcr2_reg);
1146 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1147 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1149 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1150 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1156 case DPLL_CFGCR2_PDIV_1:
1159 case DPLL_CFGCR2_PDIV_2:
1162 case DPLL_CFGCR2_PDIV_3:
1165 case DPLL_CFGCR2_PDIV_7:
1171 case DPLL_CFGCR2_KDIV_5:
1174 case DPLL_CFGCR2_KDIV_2:
1177 case DPLL_CFGCR2_KDIV_3:
1180 case DPLL_CFGCR2_KDIV_1:
1185 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1187 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1190 return dco_freq / (p0 * p1 * p2 * 5);
1193 static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1194 enum intel_dpll_id pll_id)
1196 uint32_t cfgcr0, cfgcr1;
1197 uint32_t p0, p1, p2, dco_freq, ref_clock;
1199 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1200 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1202 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1203 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1205 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1206 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1207 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1213 case DPLL_CFGCR1_PDIV_2:
1216 case DPLL_CFGCR1_PDIV_3:
1219 case DPLL_CFGCR1_PDIV_5:
1222 case DPLL_CFGCR1_PDIV_7:
1228 case DPLL_CFGCR1_KDIV_1:
1231 case DPLL_CFGCR1_KDIV_2:
1234 case DPLL_CFGCR1_KDIV_4:
1239 ref_clock = dev_priv->cdclk.hw.ref;
1241 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1243 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1244 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1246 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1249 return dco_freq / (p0 * p1 * p2 * 5);
1252 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1256 if (pipe_config->has_pch_encoder)
1257 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1258 &pipe_config->fdi_m_n);
1259 else if (intel_crtc_has_dp_encoder(pipe_config))
1260 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1261 &pipe_config->dp_m_n);
1262 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1263 dotclock = pipe_config->port_clock * 2 / 3;
1265 dotclock = pipe_config->port_clock;
1267 if (pipe_config->ycbcr420)
1270 if (pipe_config->pixel_multiplier)
1271 dotclock /= pipe_config->pixel_multiplier;
1273 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1276 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1277 struct intel_crtc_state *pipe_config)
1279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1282 enum intel_dpll_id pll_id;
1284 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1286 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1288 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1289 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1291 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1293 switch (link_clock) {
1294 case DPLL_CFGCR0_LINK_RATE_810:
1297 case DPLL_CFGCR0_LINK_RATE_1080:
1298 link_clock = 108000;
1300 case DPLL_CFGCR0_LINK_RATE_1350:
1301 link_clock = 135000;
1303 case DPLL_CFGCR0_LINK_RATE_1620:
1304 link_clock = 162000;
1306 case DPLL_CFGCR0_LINK_RATE_2160:
1307 link_clock = 216000;
1309 case DPLL_CFGCR0_LINK_RATE_2700:
1310 link_clock = 270000;
1312 case DPLL_CFGCR0_LINK_RATE_3240:
1313 link_clock = 324000;
1315 case DPLL_CFGCR0_LINK_RATE_4050:
1316 link_clock = 405000;
1319 WARN(1, "Unsupported link rate\n");
1325 pipe_config->port_clock = link_clock;
1327 ddi_dotclock_get(pipe_config);
1330 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1331 struct intel_crtc_state *pipe_config)
1333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1336 enum intel_dpll_id pll_id;
1338 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1340 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1342 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1343 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1345 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1346 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1348 switch (link_clock) {
1349 case DPLL_CTRL1_LINK_RATE_810:
1352 case DPLL_CTRL1_LINK_RATE_1080:
1353 link_clock = 108000;
1355 case DPLL_CTRL1_LINK_RATE_1350:
1356 link_clock = 135000;
1358 case DPLL_CTRL1_LINK_RATE_1620:
1359 link_clock = 162000;
1361 case DPLL_CTRL1_LINK_RATE_2160:
1362 link_clock = 216000;
1364 case DPLL_CTRL1_LINK_RATE_2700:
1365 link_clock = 270000;
1368 WARN(1, "Unsupported link rate\n");
1374 pipe_config->port_clock = link_clock;
1376 ddi_dotclock_get(pipe_config);
1379 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1380 struct intel_crtc_state *pipe_config)
1382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1386 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1387 switch (val & PORT_CLK_SEL_MASK) {
1388 case PORT_CLK_SEL_LCPLL_810:
1391 case PORT_CLK_SEL_LCPLL_1350:
1392 link_clock = 135000;
1394 case PORT_CLK_SEL_LCPLL_2700:
1395 link_clock = 270000;
1397 case PORT_CLK_SEL_WRPLL1:
1398 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1400 case PORT_CLK_SEL_WRPLL2:
1401 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1403 case PORT_CLK_SEL_SPLL:
1404 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1405 if (pll == SPLL_PLL_FREQ_810MHz)
1407 else if (pll == SPLL_PLL_FREQ_1350MHz)
1408 link_clock = 135000;
1409 else if (pll == SPLL_PLL_FREQ_2700MHz)
1410 link_clock = 270000;
1412 WARN(1, "bad spll freq\n");
1417 WARN(1, "bad port clock sel\n");
1421 pipe_config->port_clock = link_clock * 2;
1423 ddi_dotclock_get(pipe_config);
1426 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1428 struct intel_dpll_hw_state *state;
1431 /* For DDI ports we always use a shared PLL. */
1432 if (WARN_ON(!crtc_state->shared_dpll))
1435 state = &crtc_state->dpll_hw_state;
1438 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1439 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1440 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1441 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1442 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1443 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1445 return chv_calc_dpll_params(100000, &clock);
1448 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1449 struct intel_crtc_state *pipe_config)
1451 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1453 ddi_dotclock_get(pipe_config);
1456 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1457 struct intel_crtc_state *pipe_config)
1459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1461 if (INTEL_GEN(dev_priv) <= 8)
1462 hsw_ddi_clock_get(encoder, pipe_config);
1463 else if (IS_GEN9_BC(dev_priv))
1464 skl_ddi_clock_get(encoder, pipe_config);
1465 else if (IS_GEN9_LP(dev_priv))
1466 bxt_ddi_clock_get(encoder, pipe_config);
1467 else if (IS_CANNONLAKE(dev_priv))
1468 cnl_ddi_clock_get(encoder, pipe_config);
1471 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1474 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1475 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1478 if (!intel_crtc_has_dp_encoder(crtc_state))
1481 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1483 temp = TRANS_MSA_SYNC_CLK;
1484 switch (crtc_state->pipe_bpp) {
1486 temp |= TRANS_MSA_6_BPC;
1489 temp |= TRANS_MSA_8_BPC;
1492 temp |= TRANS_MSA_10_BPC;
1495 temp |= TRANS_MSA_12_BPC;
1498 MISSING_CASE(crtc_state->pipe_bpp);
1502 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1505 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1513 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1515 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1517 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1518 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1521 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1524 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1526 enum pipe pipe = crtc->pipe;
1527 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1528 enum port port = encoder->port;
1531 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1532 temp = TRANS_DDI_FUNC_ENABLE;
1533 temp |= TRANS_DDI_SELECT_PORT(port);
1535 switch (crtc_state->pipe_bpp) {
1537 temp |= TRANS_DDI_BPC_6;
1540 temp |= TRANS_DDI_BPC_8;
1543 temp |= TRANS_DDI_BPC_10;
1546 temp |= TRANS_DDI_BPC_12;
1552 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1553 temp |= TRANS_DDI_PVSYNC;
1554 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1555 temp |= TRANS_DDI_PHSYNC;
1557 if (cpu_transcoder == TRANSCODER_EDP) {
1560 /* On Haswell, can only use the always-on power well for
1561 * eDP when not using the panel fitter, and when not
1562 * using motion blur mitigation (which we don't
1564 if (IS_HASWELL(dev_priv) &&
1565 (crtc_state->pch_pfit.enabled ||
1566 crtc_state->pch_pfit.force_thru))
1567 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1569 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1572 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1575 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1583 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1584 if (crtc_state->has_hdmi_sink)
1585 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1587 temp |= TRANS_DDI_MODE_SELECT_DVI;
1589 if (crtc_state->hdmi_scrambling)
1590 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1591 if (crtc_state->hdmi_high_tmds_clock_ratio)
1592 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1593 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1594 temp |= TRANS_DDI_MODE_SELECT_FDI;
1595 temp |= (crtc_state->fdi_lanes - 1) << 1;
1596 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1597 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1598 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1600 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1601 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1604 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1607 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1608 enum transcoder cpu_transcoder)
1610 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1611 uint32_t val = I915_READ(reg);
1613 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1614 val |= TRANS_DDI_PORT_NONE;
1615 I915_WRITE(reg, val);
1618 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1621 struct drm_device *dev = intel_encoder->base.dev;
1622 struct drm_i915_private *dev_priv = to_i915(dev);
1627 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1628 intel_encoder->power_domain)))
1631 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1636 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1638 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1640 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1641 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1643 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1647 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1649 struct drm_device *dev = intel_connector->base.dev;
1650 struct drm_i915_private *dev_priv = to_i915(dev);
1651 struct intel_encoder *encoder = intel_connector->encoder;
1652 int type = intel_connector->base.connector_type;
1653 enum port port = encoder->port;
1655 enum transcoder cpu_transcoder;
1659 if (!intel_display_power_get_if_enabled(dev_priv,
1660 encoder->power_domain))
1663 if (!encoder->get_hw_state(encoder, &pipe)) {
1669 cpu_transcoder = TRANSCODER_EDP;
1671 cpu_transcoder = (enum transcoder) pipe;
1673 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1675 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1676 case TRANS_DDI_MODE_SELECT_HDMI:
1677 case TRANS_DDI_MODE_SELECT_DVI:
1678 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1681 case TRANS_DDI_MODE_SELECT_DP_SST:
1682 ret = type == DRM_MODE_CONNECTOR_eDP ||
1683 type == DRM_MODE_CONNECTOR_DisplayPort;
1686 case TRANS_DDI_MODE_SELECT_DP_MST:
1687 /* if the transcoder is in MST state then
1688 * connector isn't connected */
1692 case TRANS_DDI_MODE_SELECT_FDI:
1693 ret = type == DRM_MODE_CONNECTOR_VGA;
1702 intel_display_power_put(dev_priv, encoder->power_domain);
1707 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1710 struct drm_device *dev = encoder->base.dev;
1711 struct drm_i915_private *dev_priv = to_i915(dev);
1712 enum port port = encoder->port;
1717 if (!intel_display_power_get_if_enabled(dev_priv,
1718 encoder->power_domain))
1723 tmp = I915_READ(DDI_BUF_CTL(port));
1725 if (!(tmp & DDI_BUF_CTL_ENABLE))
1728 if (port == PORT_A) {
1729 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1731 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1732 case TRANS_DDI_EDP_INPUT_A_ON:
1733 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1736 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1739 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1749 for_each_pipe(dev_priv, p) {
1750 enum transcoder cpu_transcoder = (enum transcoder) p;
1752 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1754 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1755 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1756 TRANS_DDI_MODE_SELECT_DP_MST)
1766 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1769 if (ret && IS_GEN9_LP(dev_priv)) {
1770 tmp = I915_READ(BXT_PHY_CTL(port));
1771 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1772 BXT_PHY_LANE_POWERDOWN_ACK |
1773 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1774 DRM_ERROR("Port %c enabled but PHY powered down? "
1775 "(PHY_CTL %08x)\n", port_name(port), tmp);
1778 intel_display_power_put(dev_priv, encoder->power_domain);
1783 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
1785 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1788 if (intel_ddi_get_hw_state(encoder, &pipe))
1789 return BIT_ULL(dig_port->ddi_io_power_domain);
1794 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1796 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1797 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1798 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1799 enum port port = encoder->port;
1800 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1802 if (cpu_transcoder != TRANSCODER_EDP)
1803 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1804 TRANS_CLK_SEL_PORT(port));
1807 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1809 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1810 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1812 if (cpu_transcoder != TRANSCODER_EDP)
1813 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1814 TRANS_CLK_SEL_DISABLED);
1817 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1818 enum port port, uint8_t iboost)
1822 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
1823 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1825 tmp |= iboost << BALANCE_LEG_SHIFT(port);
1827 tmp |= BALANCE_LEG_DISABLE(port);
1828 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
1831 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1832 int level, enum intel_output_type type)
1834 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1836 enum port port = encoder->port;
1839 if (type == INTEL_OUTPUT_HDMI)
1840 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1842 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1845 const struct ddi_buf_trans *ddi_translations;
1848 if (type == INTEL_OUTPUT_HDMI)
1849 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1850 else if (type == INTEL_OUTPUT_EDP)
1851 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1853 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1855 if (WARN_ON_ONCE(!ddi_translations))
1857 if (WARN_ON_ONCE(level >= n_entries))
1858 level = n_entries - 1;
1860 iboost = ddi_translations[level].i_boost;
1863 /* Make sure that the requested I_boost is valid */
1864 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1865 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1869 _skl_ddi_set_iboost(dev_priv, port, iboost);
1871 if (port == PORT_A && intel_dig_port->max_lanes == 4)
1872 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1875 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1876 int level, enum intel_output_type type)
1878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1879 const struct bxt_ddi_buf_trans *ddi_translations;
1880 enum port port = encoder->port;
1883 if (type == INTEL_OUTPUT_HDMI)
1884 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1885 else if (type == INTEL_OUTPUT_EDP)
1886 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1888 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
1890 if (WARN_ON_ONCE(!ddi_translations))
1892 if (WARN_ON_ONCE(level >= n_entries))
1893 level = n_entries - 1;
1895 bxt_ddi_phy_set_signal_level(dev_priv, port,
1896 ddi_translations[level].margin,
1897 ddi_translations[level].scale,
1898 ddi_translations[level].enable,
1899 ddi_translations[level].deemphasis);
1902 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1904 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1905 enum port port = encoder->port;
1908 if (IS_CANNONLAKE(dev_priv)) {
1909 if (encoder->type == INTEL_OUTPUT_EDP)
1910 cnl_get_buf_trans_edp(dev_priv, &n_entries);
1912 cnl_get_buf_trans_dp(dev_priv, &n_entries);
1913 } else if (IS_GEN9_LP(dev_priv)) {
1914 if (encoder->type == INTEL_OUTPUT_EDP)
1915 bxt_get_buf_trans_edp(dev_priv, &n_entries);
1917 bxt_get_buf_trans_dp(dev_priv, &n_entries);
1919 if (encoder->type == INTEL_OUTPUT_EDP)
1920 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1922 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1925 if (WARN_ON(n_entries < 1))
1927 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1928 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1930 return index_to_dp_signal_levels[n_entries - 1] &
1931 DP_TRAIN_VOLTAGE_SWING_MASK;
1934 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1935 int level, enum intel_output_type type)
1937 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1938 const struct cnl_ddi_buf_trans *ddi_translations;
1939 enum port port = encoder->port;
1943 if (type == INTEL_OUTPUT_HDMI)
1944 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1945 else if (type == INTEL_OUTPUT_EDP)
1946 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1948 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1950 if (WARN_ON_ONCE(!ddi_translations))
1952 if (WARN_ON_ONCE(level >= n_entries))
1953 level = n_entries - 1;
1955 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1956 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1957 val &= ~SCALING_MODE_SEL_MASK;
1958 val |= SCALING_MODE_SEL(2);
1959 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1961 /* Program PORT_TX_DW2 */
1962 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1963 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1965 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1966 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1967 /* Rcomp scalar is fixed as 0x98 for every table entry */
1968 val |= RCOMP_SCALAR(0x98);
1969 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1971 /* Program PORT_TX_DW4 */
1972 /* We cannot write to GRP. It would overrite individual loadgen */
1973 for (ln = 0; ln < 4; ln++) {
1974 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1975 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1977 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1978 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1979 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1980 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1983 /* Program PORT_TX_DW5 */
1984 /* All DW5 values are fixed for every table entry */
1985 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1986 val &= ~RTERM_SELECT_MASK;
1987 val |= RTERM_SELECT(6);
1988 val |= TAP3_DISABLE;
1989 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1991 /* Program PORT_TX_DW7 */
1992 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1993 val &= ~N_SCALAR_MASK;
1994 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1995 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
1998 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
1999 int level, enum intel_output_type type)
2001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2002 enum port port = encoder->port;
2003 int width, rate, ln;
2006 if (type == INTEL_OUTPUT_HDMI) {
2008 rate = 0; /* Rate is always < than 6GHz for HDMI */
2010 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012 width = intel_dp->lane_count;
2013 rate = intel_dp->link_rate;
2017 * 1. If port type is eDP or DP,
2018 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2021 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2022 if (type != INTEL_OUTPUT_HDMI)
2023 val |= COMMON_KEEPER_EN;
2025 val &= ~COMMON_KEEPER_EN;
2026 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2028 /* 2. Program loadgen select */
2030 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2031 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2032 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2033 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2035 for (ln = 0; ln <= 3; ln++) {
2036 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2037 val &= ~LOADGEN_SELECT;
2039 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2040 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2041 val |= LOADGEN_SELECT;
2043 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2046 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2047 val = I915_READ(CNL_PORT_CL1CM_DW5);
2048 val |= SUS_CLOCK_CONFIG;
2049 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2051 /* 4. Clear training enable to change swing values */
2052 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2053 val &= ~TX_TRAINING_EN;
2054 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2056 /* 5. Program swing and de-emphasis */
2057 cnl_ddi_vswing_program(encoder, level, type);
2059 /* 6. Set training enable to trigger update */
2060 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2061 val |= TX_TRAINING_EN;
2062 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2065 static uint32_t translate_signal_level(int signal_levels)
2069 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2070 if (index_to_dp_signal_levels[i] == signal_levels)
2074 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2080 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2082 uint8_t train_set = intel_dp->train_set[0];
2083 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2084 DP_TRAIN_PRE_EMPHASIS_MASK);
2086 return translate_signal_level(signal_levels);
2089 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2091 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2092 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2093 struct intel_encoder *encoder = &dport->base;
2094 int level = intel_ddi_dp_level(intel_dp);
2096 if (IS_CANNONLAKE(dev_priv))
2097 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2099 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2104 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2106 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2107 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2108 struct intel_encoder *encoder = &dport->base;
2109 int level = intel_ddi_dp_level(intel_dp);
2111 if (IS_GEN9_BC(dev_priv))
2112 skl_ddi_set_iboost(encoder, level, encoder->type);
2114 return DDI_BUF_TRANS_SELECT(level);
2117 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2118 const struct intel_shared_dpll *pll)
2120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2121 enum port port = encoder->port;
2127 mutex_lock(&dev_priv->dpll_lock);
2129 if (IS_CANNONLAKE(dev_priv)) {
2130 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2131 val = I915_READ(DPCLKA_CFGCR0);
2132 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2133 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2134 I915_WRITE(DPCLKA_CFGCR0, val);
2137 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2138 * This step and the step before must be done with separate
2141 val = I915_READ(DPCLKA_CFGCR0);
2142 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2143 I915_WRITE(DPCLKA_CFGCR0, val);
2144 } else if (IS_GEN9_BC(dev_priv)) {
2145 /* DDI -> PLL mapping */
2146 val = I915_READ(DPLL_CTRL2);
2148 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2149 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2150 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2151 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2153 I915_WRITE(DPLL_CTRL2, val);
2155 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2156 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2159 mutex_unlock(&dev_priv->dpll_lock);
2162 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2164 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2165 enum port port = encoder->port;
2167 if (IS_CANNONLAKE(dev_priv))
2168 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2169 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2170 else if (IS_GEN9_BC(dev_priv))
2171 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2172 DPLL_CTRL2_DDI_CLK_OFF(port));
2173 else if (INTEL_GEN(dev_priv) < 9)
2174 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2177 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2178 const struct intel_crtc_state *crtc_state,
2179 const struct drm_connector_state *conn_state)
2181 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2183 enum port port = encoder->port;
2184 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2185 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2186 int level = intel_ddi_dp_level(intel_dp);
2188 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2190 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2191 crtc_state->lane_count, is_mst);
2193 intel_edp_panel_on(intel_dp);
2195 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2197 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2199 if (IS_CANNONLAKE(dev_priv))
2200 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2201 else if (IS_GEN9_LP(dev_priv))
2202 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2204 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
2206 intel_ddi_init_dp_buf_reg(encoder);
2208 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2209 intel_dp_start_link_train(intel_dp);
2210 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
2211 intel_dp_stop_link_train(intel_dp);
2214 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2215 const struct intel_crtc_state *crtc_state,
2216 const struct drm_connector_state *conn_state)
2218 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2219 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2221 enum port port = encoder->port;
2222 int level = intel_ddi_hdmi_level(dev_priv, port);
2223 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2225 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2226 intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2228 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2230 if (IS_CANNONLAKE(dev_priv))
2231 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2232 else if (IS_GEN9_LP(dev_priv))
2233 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2235 intel_prepare_hdmi_ddi_buffers(encoder, level);
2237 if (IS_GEN9_BC(dev_priv))
2238 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2240 intel_dig_port->set_infoframes(&encoder->base,
2241 crtc_state->has_infoframe,
2242 crtc_state, conn_state);
2245 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2246 const struct intel_crtc_state *crtc_state,
2247 const struct drm_connector_state *conn_state)
2249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2251 enum pipe pipe = crtc->pipe;
2254 * When called from DP MST code:
2255 * - conn_state will be NULL
2256 * - encoder will be the main encoder (ie. mst->primary)
2257 * - the main connector associated with this port
2258 * won't be active or linked to a crtc
2259 * - crtc_state will be the state of the first stream to
2260 * be activated on this port, and it may not be the same
2261 * stream that will be deactivated last, but each stream
2262 * should have a state that is identical when it comes to
2263 * the DP link parameteres
2266 WARN_ON(crtc_state->has_pch_encoder);
2268 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2270 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2271 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2273 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
2276 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
2278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2279 enum port port = encoder->port;
2283 val = I915_READ(DDI_BUF_CTL(port));
2284 if (val & DDI_BUF_CTL_ENABLE) {
2285 val &= ~DDI_BUF_CTL_ENABLE;
2286 I915_WRITE(DDI_BUF_CTL(port), val);
2290 val = I915_READ(DP_TP_CTL(port));
2291 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2292 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2293 I915_WRITE(DP_TP_CTL(port), val);
2296 intel_wait_ddi_buf_idle(dev_priv, port);
2299 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2300 const struct intel_crtc_state *old_crtc_state,
2301 const struct drm_connector_state *old_conn_state)
2303 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2304 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2305 struct intel_dp *intel_dp = &dig_port->dp;
2306 bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST);
2309 * Power down sink before disabling the port, otherwise we end
2310 * up getting interrupts from the sink on detecting link loss.
2313 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2315 intel_disable_ddi_buf(encoder);
2317 intel_edp_panel_vdd_on(intel_dp);
2318 intel_edp_panel_off(intel_dp);
2320 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2322 intel_ddi_clk_disable(encoder);
2325 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2326 const struct intel_crtc_state *old_crtc_state,
2327 const struct drm_connector_state *old_conn_state)
2329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2330 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2331 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2333 intel_disable_ddi_buf(encoder);
2335 dig_port->set_infoframes(&encoder->base, false,
2336 old_crtc_state, old_conn_state);
2338 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2340 intel_ddi_clk_disable(encoder);
2342 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2345 static void intel_ddi_post_disable(struct intel_encoder *encoder,
2346 const struct intel_crtc_state *old_crtc_state,
2347 const struct drm_connector_state *old_conn_state)
2350 * When called from DP MST code:
2351 * - old_conn_state will be NULL
2352 * - encoder will be the main encoder (ie. mst->primary)
2353 * - the main connector associated with this port
2354 * won't be active or linked to a crtc
2355 * - old_crtc_state will be the state of the last stream to
2356 * be deactivated on this port, and it may not be the same
2357 * stream that was activated last, but each stream
2358 * should have a state that is identical when it comes to
2359 * the DP link parameteres
2362 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2363 intel_ddi_post_disable_hdmi(encoder,
2364 old_crtc_state, old_conn_state);
2366 intel_ddi_post_disable_dp(encoder,
2367 old_crtc_state, old_conn_state);
2370 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2371 const struct intel_crtc_state *old_crtc_state,
2372 const struct drm_connector_state *old_conn_state)
2374 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2378 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2379 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2380 * step 13 is the correct place for it. Step 18 is where it was
2381 * originally before the BUN.
2383 val = I915_READ(FDI_RX_CTL(PIPE_A));
2384 val &= ~FDI_RX_ENABLE;
2385 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2387 intel_disable_ddi_buf(encoder);
2388 intel_ddi_clk_disable(encoder);
2390 val = I915_READ(FDI_RX_MISC(PIPE_A));
2391 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2392 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2393 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2395 val = I915_READ(FDI_RX_CTL(PIPE_A));
2397 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2399 val = I915_READ(FDI_RX_CTL(PIPE_A));
2400 val &= ~FDI_RX_PLL_ENABLE;
2401 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2404 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2405 const struct intel_crtc_state *crtc_state,
2406 const struct drm_connector_state *conn_state)
2408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2409 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2410 enum port port = encoder->port;
2412 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2413 intel_dp_stop_link_train(intel_dp);
2415 intel_edp_backlight_on(crtc_state, conn_state);
2416 intel_psr_enable(intel_dp, crtc_state);
2417 intel_edp_drrs_enable(intel_dp, crtc_state);
2419 if (crtc_state->has_audio)
2420 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2423 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2424 const struct intel_crtc_state *crtc_state,
2425 const struct drm_connector_state *conn_state)
2427 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2428 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2429 enum port port = encoder->port;
2431 intel_hdmi_handle_sink_scrambling(encoder,
2432 conn_state->connector,
2433 crtc_state->hdmi_high_tmds_clock_ratio,
2434 crtc_state->hdmi_scrambling);
2436 /* Display WA #1143: skl,kbl,cfl */
2437 if (IS_GEN9_BC(dev_priv)) {
2439 * For some reason these chicken bits have been
2440 * stuffed into a transcoder register, event though
2441 * the bits affect a specific DDI port rather than
2442 * a specific transcoder.
2444 static const enum transcoder port_to_transcoder[] = {
2445 [PORT_A] = TRANSCODER_EDP,
2446 [PORT_B] = TRANSCODER_A,
2447 [PORT_C] = TRANSCODER_B,
2448 [PORT_D] = TRANSCODER_C,
2449 [PORT_E] = TRANSCODER_A,
2451 enum transcoder transcoder = port_to_transcoder[port];
2454 val = I915_READ(CHICKEN_TRANS(transcoder));
2457 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2458 DDIE_TRAINING_OVERRIDE_VALUE;
2460 val |= DDI_TRAINING_OVERRIDE_ENABLE |
2461 DDI_TRAINING_OVERRIDE_VALUE;
2463 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2464 POSTING_READ(CHICKEN_TRANS(transcoder));
2469 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2470 DDIE_TRAINING_OVERRIDE_VALUE);
2472 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2473 DDI_TRAINING_OVERRIDE_VALUE);
2475 I915_WRITE(CHICKEN_TRANS(transcoder), val);
2478 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2479 * are ignored so nothing special needs to be done besides
2480 * enabling the port.
2482 I915_WRITE(DDI_BUF_CTL(port),
2483 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2485 if (crtc_state->has_audio)
2486 intel_audio_codec_enable(encoder, crtc_state, conn_state);
2489 static void intel_enable_ddi(struct intel_encoder *encoder,
2490 const struct intel_crtc_state *crtc_state,
2491 const struct drm_connector_state *conn_state)
2493 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2494 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2496 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2498 /* Enable hdcp if it's desired */
2499 if (conn_state->content_protection ==
2500 DRM_MODE_CONTENT_PROTECTION_DESIRED)
2501 intel_hdcp_enable(to_intel_connector(conn_state->connector));
2504 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2505 const struct intel_crtc_state *old_crtc_state,
2506 const struct drm_connector_state *old_conn_state)
2508 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2510 if (old_crtc_state->has_audio)
2511 intel_audio_codec_disable(encoder,
2512 old_crtc_state, old_conn_state);
2514 intel_edp_drrs_disable(intel_dp, old_crtc_state);
2515 intel_psr_disable(intel_dp, old_crtc_state);
2516 intel_edp_backlight_off(old_conn_state);
2519 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2520 const struct intel_crtc_state *old_crtc_state,
2521 const struct drm_connector_state *old_conn_state)
2523 if (old_crtc_state->has_audio)
2524 intel_audio_codec_disable(encoder,
2525 old_crtc_state, old_conn_state);
2527 intel_hdmi_handle_sink_scrambling(encoder,
2528 old_conn_state->connector,
2532 static void intel_disable_ddi(struct intel_encoder *encoder,
2533 const struct intel_crtc_state *old_crtc_state,
2534 const struct drm_connector_state *old_conn_state)
2536 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
2538 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2539 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2541 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
2544 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2545 const struct intel_crtc_state *pipe_config,
2546 const struct drm_connector_state *conn_state)
2548 uint8_t mask = pipe_config->lane_lat_optim_mask;
2550 bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2553 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2556 struct drm_i915_private *dev_priv =
2557 to_i915(intel_dig_port->base.base.dev);
2558 enum port port = intel_dig_port->base.port;
2562 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2563 val = I915_READ(DDI_BUF_CTL(port));
2564 if (val & DDI_BUF_CTL_ENABLE) {
2565 val &= ~DDI_BUF_CTL_ENABLE;
2566 I915_WRITE(DDI_BUF_CTL(port), val);
2570 val = I915_READ(DP_TP_CTL(port));
2571 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2572 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2573 I915_WRITE(DP_TP_CTL(port), val);
2574 POSTING_READ(DP_TP_CTL(port));
2577 intel_wait_ddi_buf_idle(dev_priv, port);
2580 val = DP_TP_CTL_ENABLE |
2581 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2582 if (intel_dp->link_mst)
2583 val |= DP_TP_CTL_MODE_MST;
2585 val |= DP_TP_CTL_MODE_SST;
2586 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2587 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2589 I915_WRITE(DP_TP_CTL(port), val);
2590 POSTING_READ(DP_TP_CTL(port));
2592 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2593 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2594 POSTING_READ(DDI_BUF_CTL(port));
2599 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2600 enum transcoder cpu_transcoder)
2602 if (cpu_transcoder == TRANSCODER_EDP)
2605 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
2608 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
2609 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
2612 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
2613 struct intel_crtc_state *crtc_state)
2615 if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
2616 crtc_state->min_voltage_level = 2;
2619 void intel_ddi_get_config(struct intel_encoder *encoder,
2620 struct intel_crtc_state *pipe_config)
2622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2623 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2624 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2625 struct intel_digital_port *intel_dig_port;
2626 u32 temp, flags = 0;
2628 /* XXX: DSI transcoder paranoia */
2629 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2632 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2633 if (temp & TRANS_DDI_PHSYNC)
2634 flags |= DRM_MODE_FLAG_PHSYNC;
2636 flags |= DRM_MODE_FLAG_NHSYNC;
2637 if (temp & TRANS_DDI_PVSYNC)
2638 flags |= DRM_MODE_FLAG_PVSYNC;
2640 flags |= DRM_MODE_FLAG_NVSYNC;
2642 pipe_config->base.adjusted_mode.flags |= flags;
2644 switch (temp & TRANS_DDI_BPC_MASK) {
2645 case TRANS_DDI_BPC_6:
2646 pipe_config->pipe_bpp = 18;
2648 case TRANS_DDI_BPC_8:
2649 pipe_config->pipe_bpp = 24;
2651 case TRANS_DDI_BPC_10:
2652 pipe_config->pipe_bpp = 30;
2654 case TRANS_DDI_BPC_12:
2655 pipe_config->pipe_bpp = 36;
2661 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2662 case TRANS_DDI_MODE_SELECT_HDMI:
2663 pipe_config->has_hdmi_sink = true;
2664 intel_dig_port = enc_to_dig_port(&encoder->base);
2666 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
2667 pipe_config->has_infoframe = true;
2669 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2670 TRANS_DDI_HDMI_SCRAMBLING_MASK)
2671 pipe_config->hdmi_scrambling = true;
2672 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2673 pipe_config->hdmi_high_tmds_clock_ratio = true;
2675 case TRANS_DDI_MODE_SELECT_DVI:
2676 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
2677 pipe_config->lane_count = 4;
2679 case TRANS_DDI_MODE_SELECT_FDI:
2680 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
2682 case TRANS_DDI_MODE_SELECT_DP_SST:
2683 if (encoder->type == INTEL_OUTPUT_EDP)
2684 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2686 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2687 pipe_config->lane_count =
2688 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2689 intel_dp_get_m_n(intel_crtc, pipe_config);
2691 case TRANS_DDI_MODE_SELECT_DP_MST:
2692 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
2693 pipe_config->lane_count =
2694 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2695 intel_dp_get_m_n(intel_crtc, pipe_config);
2701 pipe_config->has_audio =
2702 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
2704 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2705 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2707 * This is a big fat ugly hack.
2709 * Some machines in UEFI boot mode provide us a VBT that has 18
2710 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2711 * unknown we fail to light up. Yet the same BIOS boots up with
2712 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2713 * max, not what it tells us to use.
2715 * Note: This will still be broken if the eDP panel is not lit
2716 * up by the BIOS, and thus we can't get the mode at module
2719 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2720 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2721 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2724 intel_ddi_clock_get(encoder, pipe_config);
2726 if (IS_GEN9_LP(dev_priv))
2727 pipe_config->lane_lat_optim_mask =
2728 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2730 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2733 static enum intel_output_type
2734 intel_ddi_compute_output_type(struct intel_encoder *encoder,
2735 struct intel_crtc_state *crtc_state,
2736 struct drm_connector_state *conn_state)
2738 switch (conn_state->connector->connector_type) {
2739 case DRM_MODE_CONNECTOR_HDMIA:
2740 return INTEL_OUTPUT_HDMI;
2741 case DRM_MODE_CONNECTOR_eDP:
2742 return INTEL_OUTPUT_EDP;
2743 case DRM_MODE_CONNECTOR_DisplayPort:
2744 return INTEL_OUTPUT_DP;
2746 MISSING_CASE(conn_state->connector->connector_type);
2747 return INTEL_OUTPUT_UNUSED;
2751 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2752 struct intel_crtc_state *pipe_config,
2753 struct drm_connector_state *conn_state)
2755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2756 enum port port = encoder->port;
2760 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2762 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
2763 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
2765 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2767 if (IS_GEN9_LP(dev_priv) && ret)
2768 pipe_config->lane_lat_optim_mask =
2769 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
2771 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
2777 static const struct drm_encoder_funcs intel_ddi_funcs = {
2778 .reset = intel_dp_encoder_reset,
2779 .destroy = intel_dp_encoder_destroy,
2782 static struct intel_connector *
2783 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2785 struct intel_connector *connector;
2786 enum port port = intel_dig_port->base.port;
2788 connector = intel_connector_alloc();
2792 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2793 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2801 static struct intel_connector *
2802 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2804 struct intel_connector *connector;
2805 enum port port = intel_dig_port->base.port;
2807 connector = intel_connector_alloc();
2811 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2812 intel_hdmi_init_connector(intel_dig_port, connector);
2817 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
2819 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2821 if (dport->base.port != PORT_A)
2824 if (dport->saved_port_bits & DDI_A_4_LANES)
2827 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
2828 * supported configuration
2830 if (IS_GEN9_LP(dev_priv))
2833 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
2834 * one who does also have a full A/E split called
2835 * DDI_F what makes DDI_E useless. However for this
2836 * case let's trust VBT info.
2838 if (IS_CANNONLAKE(dev_priv) &&
2839 !intel_bios_is_port_present(dev_priv, PORT_E))
2845 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
2847 struct intel_digital_port *intel_dig_port;
2848 struct intel_encoder *intel_encoder;
2849 struct drm_encoder *encoder;
2850 bool init_hdmi, init_dp, init_lspcon = false;
2853 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2879 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2880 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2881 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2883 if (intel_bios_is_lspcon_present(dev_priv, port)) {
2885 * Lspcon device needs to be driven with DP connector
2886 * with special detection sequence. So make sure DP
2887 * is initialized before lspcon.
2892 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
2895 if (!init_dp && !init_hdmi) {
2896 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2901 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2902 if (!intel_dig_port)
2905 intel_encoder = &intel_dig_port->base;
2906 encoder = &intel_encoder->base;
2908 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2909 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
2911 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
2912 intel_encoder->compute_config = intel_ddi_compute_config;
2913 intel_encoder->enable = intel_enable_ddi;
2914 if (IS_GEN9_LP(dev_priv))
2915 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
2916 intel_encoder->pre_enable = intel_ddi_pre_enable;
2917 intel_encoder->disable = intel_disable_ddi;
2918 intel_encoder->post_disable = intel_ddi_post_disable;
2919 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2920 intel_encoder->get_config = intel_ddi_get_config;
2921 intel_encoder->suspend = intel_dp_encoder_suspend;
2922 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
2924 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2925 (DDI_BUF_PORT_REVERSAL |
2930 intel_dig_port->ddi_io_power_domain =
2931 POWER_DOMAIN_PORT_DDI_A_IO;
2934 intel_dig_port->ddi_io_power_domain =
2935 POWER_DOMAIN_PORT_DDI_B_IO;
2938 intel_dig_port->ddi_io_power_domain =
2939 POWER_DOMAIN_PORT_DDI_C_IO;
2942 intel_dig_port->ddi_io_power_domain =
2943 POWER_DOMAIN_PORT_DDI_D_IO;
2946 intel_dig_port->ddi_io_power_domain =
2947 POWER_DOMAIN_PORT_DDI_E_IO;
2950 intel_dig_port->ddi_io_power_domain =
2951 POWER_DOMAIN_PORT_DDI_F_IO;
2958 * Some BIOS might fail to set this bit on port A if eDP
2959 * wasn't lit up at boot. Force this bit set when needed
2960 * so we use the proper lane count for our calculations.
2962 if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
2963 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
2964 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2968 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2969 intel_dig_port->max_lanes = max_lanes;
2971 intel_encoder->type = INTEL_OUTPUT_DDI;
2972 intel_encoder->power_domain = intel_port_to_power_domain(port);
2973 intel_encoder->port = port;
2974 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2975 intel_encoder->cloneable = 0;
2977 intel_infoframe_init(intel_dig_port);
2980 if (!intel_ddi_init_dp_connector(intel_dig_port))
2983 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2984 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2987 /* In theory we don't need the encoder->type check, but leave it just in
2988 * case we have some really bad VBTs... */
2989 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2990 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2995 if (lspcon_init(intel_dig_port))
2996 /* TODO: handle hdmi info frame part */
2997 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
3001 * LSPCON init faied, but DP init was success, so
3002 * lets try to drive as DP++ port.
3004 DRM_ERROR("LSPCON init failed on port %c\n",
3011 drm_encoder_cleanup(encoder);
3012 kfree(intel_dig_port);