drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "intel_dsi.h"
  32
  33 struct ddi_buf_trans {
  34         u32 trans1;     /* balance leg enable, de-emph level */
  35         u32 trans2;     /* vref sel, vswing */
  36         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  37 };
  38
  39 static const u8 index_to_dp_signal_levels[] = {
  40         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  41         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  42         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  43         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  44         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  45         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  46         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  47         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  49         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  50 };
  51
  52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  53  * them for both DP and FDI transports, allowing those ports to
  54  * automatically adapt to HDMI connections as well
  55  */
  56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  57         { 0x00FFFFFF, 0x0006000E, 0x0 },
  58         { 0x00D75FFF, 0x0005000A, 0x0 },
  59         { 0x00C30FFF, 0x00040006, 0x0 },
  60         { 0x80AAAFFF, 0x000B0000, 0x0 },
  61         { 0x00FFFFFF, 0x0005000A, 0x0 },
  62         { 0x00D75FFF, 0x000C0004, 0x0 },
  63         { 0x80C30FFF, 0x000B0000, 0x0 },
  64         { 0x00FFFFFF, 0x00040006, 0x0 },
  65         { 0x80D75FFF, 0x000B0000, 0x0 },
  66 };
  67
  68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  69         { 0x00FFFFFF, 0x0007000E, 0x0 },
  70         { 0x00D75FFF, 0x000F000A, 0x0 },
  71         { 0x00C30FFF, 0x00060006, 0x0 },
  72         { 0x00AAAFFF, 0x001E0000, 0x0 },
  73         { 0x00FFFFFF, 0x000F000A, 0x0 },
  74         { 0x00D75FFF, 0x00160004, 0x0 },
  75         { 0x00C30FFF, 0x001E0000, 0x0 },
  76         { 0x00FFFFFF, 0x00060006, 0x0 },
  77         { 0x00D75FFF, 0x001E0000, 0x0 },
  78 };
  79
  80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  81                                         /* Idx  NT mV d T mV d  db      */
  82         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  83         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  84         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  85         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  86         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  87         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  88         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  89         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  90         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  91         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  92         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  93         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  94 };
  95
  96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  97         { 0x00FFFFFF, 0x00000012, 0x0 },
  98         { 0x00EBAFFF, 0x00020011, 0x0 },
  99         { 0x00C71FFF, 0x0006000F, 0x0 },
 100         { 0x00AAAFFF, 0x000E000A, 0x0 },
 101         { 0x00FFFFFF, 0x00020011, 0x0 },
 102         { 0x00DB6FFF, 0x0005000F, 0x0 },
 103         { 0x00BEEFFF, 0x000A000C, 0x0 },
 104         { 0x00FFFFFF, 0x0005000F, 0x0 },
 105         { 0x00DB6FFF, 0x000A000C, 0x0 },
 106 };
 107
 108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 109         { 0x00FFFFFF, 0x0007000E, 0x0 },
 110         { 0x00D75FFF, 0x000E000A, 0x0 },
 111         { 0x00BEFFFF, 0x00140006, 0x0 },
 112         { 0x80B2CFFF, 0x001B0002, 0x0 },
 113         { 0x00FFFFFF, 0x000E000A, 0x0 },
 114         { 0x00DB6FFF, 0x00160005, 0x0 },
 115         { 0x80C71FFF, 0x001A0002, 0x0 },
 116         { 0x00F7DFFF, 0x00180004, 0x0 },
 117         { 0x80D75FFF, 0x001B0002, 0x0 },
 118 };
 119
 120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 121         { 0x00FFFFFF, 0x0001000E, 0x0 },
 122         { 0x00D75FFF, 0x0004000A, 0x0 },
 123         { 0x00C30FFF, 0x00070006, 0x0 },
 124         { 0x00AAAFFF, 0x000C0000, 0x0 },
 125         { 0x00FFFFFF, 0x0004000A, 0x0 },
 126         { 0x00D75FFF, 0x00090004, 0x0 },
 127         { 0x00C30FFF, 0x000C0000, 0x0 },
 128         { 0x00FFFFFF, 0x00070006, 0x0 },
 129         { 0x00D75FFF, 0x000C0000, 0x0 },
 130 };
 131
 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 133                                         /* Idx  NT mV d T mV df db      */
 134         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 135         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 136         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 137         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 138         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 139         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 140         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 141         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 142         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 143         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 144 };
 145
 146 /* Skylake H and S */
 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 148         { 0x00002016, 0x000000A0, 0x0 },
 149         { 0x00005012, 0x0000009B, 0x0 },
 150         { 0x00007011, 0x00000088, 0x0 },
 151         { 0x80009010, 0x000000C0, 0x1 },
 152         { 0x00002016, 0x0000009B, 0x0 },
 153         { 0x00005012, 0x00000088, 0x0 },
 154         { 0x80007011, 0x000000C0, 0x1 },
 155         { 0x00002016, 0x000000DF, 0x0 },
 156         { 0x80005012, 0x000000C0, 0x1 },
 157 };
 158
 159 /* Skylake U */
 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 161         { 0x0000201B, 0x000000A2, 0x0 },
 162         { 0x00005012, 0x00000088, 0x0 },
 163         { 0x80007011, 0x000000CD, 0x1 },
 164         { 0x80009010, 0x000000C0, 0x1 },
 165         { 0x0000201B, 0x0000009D, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167         { 0x80007011, 0x000000C0, 0x1 },
 168         { 0x00002016, 0x00000088, 0x0 },
 169         { 0x80005012, 0x000000C0, 0x1 },
 170 };
 171
 172 /* Skylake Y */
 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 174         { 0x00000018, 0x000000A2, 0x0 },
 175         { 0x00005012, 0x00000088, 0x0 },
 176         { 0x80007011, 0x000000CD, 0x3 },
 177         { 0x80009010, 0x000000C0, 0x3 },
 178         { 0x00000018, 0x0000009D, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x3 },
 180         { 0x80007011, 0x000000C0, 0x3 },
 181         { 0x00000018, 0x00000088, 0x0 },
 182         { 0x80005012, 0x000000C0, 0x3 },
 183 };
 184
 185 /* Kabylake H and S */
 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 187         { 0x00002016, 0x000000A0, 0x0 },
 188         { 0x00005012, 0x0000009B, 0x0 },
 189         { 0x00007011, 0x00000088, 0x0 },
 190         { 0x80009010, 0x000000C0, 0x1 },
 191         { 0x00002016, 0x0000009B, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000C0, 0x1 },
 194         { 0x00002016, 0x00000097, 0x0 },
 195         { 0x80005012, 0x000000C0, 0x1 },
 196 };
 197
 198 /* Kabylake U */
 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 200         { 0x0000201B, 0x000000A1, 0x0 },
 201         { 0x00005012, 0x00000088, 0x0 },
 202         { 0x80007011, 0x000000CD, 0x3 },
 203         { 0x80009010, 0x000000C0, 0x3 },
 204         { 0x0000201B, 0x0000009D, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x3 },
 206         { 0x80007011, 0x000000C0, 0x3 },
 207         { 0x00002016, 0x0000004F, 0x0 },
 208         { 0x80005012, 0x000000C0, 0x3 },
 209 };
 210
 211 /* Kabylake Y */
 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 213         { 0x00001017, 0x000000A1, 0x0 },
 214         { 0x00005012, 0x00000088, 0x0 },
 215         { 0x80007011, 0x000000CD, 0x3 },
 216         { 0x8000800F, 0x000000C0, 0x3 },
 217         { 0x00001017, 0x0000009D, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219         { 0x80007011, 0x000000C0, 0x3 },
 220         { 0x00001017, 0x0000004C, 0x0 },
 221         { 0x80005012, 0x000000C0, 0x3 },
 222 };
 223
 224 /*
 225  * Skylake/Kabylake H and S
 226  * eDP 1.4 low vswing translation parameters
 227  */
 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 229         { 0x00000018, 0x000000A8, 0x0 },
 230         { 0x00004013, 0x000000A9, 0x0 },
 231         { 0x00007011, 0x000000A2, 0x0 },
 232         { 0x00009010, 0x0000009C, 0x0 },
 233         { 0x00000018, 0x000000A9, 0x0 },
 234         { 0x00006013, 0x000000A2, 0x0 },
 235         { 0x00007011, 0x000000A6, 0x0 },
 236         { 0x00000018, 0x000000AB, 0x0 },
 237         { 0x00007013, 0x0000009F, 0x0 },
 238         { 0x00000018, 0x000000DF, 0x0 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake U
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00002016, 0x000000AB, 0x0 },
 254         { 0x00005013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake Y
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000AB, 0x0 },
 265         { 0x00007011, 0x000000A4, 0x0 },
 266         { 0x00009010, 0x000000DF, 0x0 },
 267         { 0x00000018, 0x000000AA, 0x0 },
 268         { 0x00006013, 0x000000A4, 0x0 },
 269         { 0x00007011, 0x0000009D, 0x0 },
 270         { 0x00000018, 0x000000A0, 0x0 },
 271         { 0x00006012, 0x000000DF, 0x0 },
 272         { 0x00000018, 0x0000008A, 0x0 },
 273 };
 274
 275 /* Skylake/Kabylake U, H and S */
 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000AC, 0x0 },
 278         { 0x00005012, 0x0000009D, 0x0 },
 279         { 0x00007011, 0x00000088, 0x0 },
 280         { 0x00000018, 0x000000A1, 0x0 },
 281         { 0x00000018, 0x00000098, 0x0 },
 282         { 0x00004013, 0x00000088, 0x0 },
 283         { 0x80006012, 0x000000CD, 0x1 },
 284         { 0x00000018, 0x000000DF, 0x0 },
 285         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x1 },
 287         { 0x80000018, 0x000000C0, 0x1 },
 288 };
 289
 290 /* Skylake/Kabylake Y */
 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 292         { 0x00000018, 0x000000A1, 0x0 },
 293         { 0x00005012, 0x000000DF, 0x0 },
 294         { 0x80007011, 0x000000CB, 0x3 },
 295         { 0x00000018, 0x000000A4, 0x0 },
 296         { 0x00000018, 0x0000009D, 0x0 },
 297         { 0x00004013, 0x00000080, 0x0 },
 298         { 0x80006013, 0x000000C0, 0x3 },
 299         { 0x00000018, 0x0000008A, 0x0 },
 300         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 301         { 0x80003015, 0x000000C0, 0x3 },
 302         { 0x80000018, 0x000000C0, 0x3 },
 303 };
 304
 305 struct bxt_ddi_buf_trans {
 306         u8 margin;      /* swing value */
 307         u8 scale;       /* scale value */
 308         u8 enable;      /* scale enable */
 309         u8 deemphasis;
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 315         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 316         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 317         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 318         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 319         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 320         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 321         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 322         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 323         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 324 };
 325
 326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 327                                         /* Idx  NT mV diff      db  */
 328         { 26, 0, 0, 128, },     /* 0:   200             0   */
 329         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 330         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 331         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 332         { 32, 0, 0, 128, },     /* 4:   250             0   */
 333         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 334         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 335         { 43, 0, 0, 128, },     /* 7:   300             0   */
 336         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 337         { 48, 0, 0, 128, },     /* 9:   300             0   */
 338 };
 339
 340 /* BSpec has 2 recommended values - entries 0 and 8.
 341  * Using the entry with higher vswing.
 342  */
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 346         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 347         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 348         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 349         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 350         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 351         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 352         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 353         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 354         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 355 };
 356
 357 struct cnl_ddi_buf_trans {
 358         u8 dw2_swing_sel;
 359         u8 dw7_n_scalar;
 360         u8 dw4_cursor_coeff;
 361         u8 dw4_post_cursor_2;
 362         u8 dw4_post_cursor_1;
 363 };
 364
 365 /* Voltage Swing Programming for VccIO 0.85V for DP */
 366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 367                                                 /* NT mV Trans mV db    */
 368         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 369         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 370         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 371         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 372         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 373         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 374         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 375         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 376         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 377         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 378 };
 379
 380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 382                                                 /* NT mV Trans mV db    */
 383         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 384         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 385         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 386         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 387         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 388         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 389         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 390 };
 391
 392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 394                                                 /* NT mV Trans mV db    */
 395         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 396         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 397         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 398         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 399         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 400         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 401         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 402         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 403         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 404 };
 405
 406 /* Voltage Swing Programming for VccIO 0.95V for DP */
 407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 408                                                 /* NT mV Trans mV db    */
 409         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 410         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 411         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 412         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 413         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 414         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 415         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 416         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 417         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 418         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 419 };
 420
 421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 423                                                 /* NT mV Trans mV db    */
 424         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 426         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 427         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 428         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 429         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 430         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 431         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 432         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 433         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 434         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 435 };
 436
 437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 439                                                 /* NT mV Trans mV db    */
 440         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 441         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 442         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 443         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 444         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 445         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 446         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 447         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 448         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 449         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 450 };
 451
 452 /* Voltage Swing Programming for VccIO 1.05V for DP */
 453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 454                                                 /* NT mV Trans mV db    */
 455         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 456         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 457         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 458         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 459         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 460         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 461         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 462         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 463         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 464         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 465 };
 466
 467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 469                                                 /* NT mV Trans mV db    */
 470         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 472         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 473         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 474         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 475         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 476         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 477         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 478         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 479         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 480         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 481 };
 482
 483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 485                                                 /* NT mV Trans mV db    */
 486         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 487         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 488         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 489         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 490         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 491         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 492         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 493         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 494         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 495 };
 496
 497 /* icl_combo_phy_ddi_translations */
 498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 499                                                 /* NT mV Trans mV db    */
 500         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 501         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 502         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 503         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 504         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 505         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 506         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 507         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 508         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 509         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 510 };
 511
 512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 513                                                 /* NT mV Trans mV db    */
 514         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 515         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 516         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 517         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 518         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 519         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 520         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 521         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 522         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 523         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 524 };
 525
 526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 527                                                 /* NT mV Trans mV db    */
 528         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 529         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 530         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 531         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 532         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 533         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 534         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 535         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 536         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 537         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 538 };
 539
 540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 541                                                 /* NT mV Trans mV db    */
 542         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 543         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 544         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 545         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 546         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 547         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 548         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 549 };
 550
 551 struct icl_mg_phy_ddi_buf_trans {
 552         u32 cri_txdeemph_override_5_0;
 553         u32 cri_txdeemph_override_11_6;
 554         u32 cri_txdeemph_override_17_12;
 555 };
 556
 557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 558                                 /* Voltage swing  pre-emphasis */
 559         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 560         { 0x0, 0x23, 0x08 },    /* 0              1   */
 561         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 562         { 0x0, 0x00, 0x00 },    /* 0              3   */
 563         { 0x0, 0x23, 0x00 },    /* 1              0   */
 564         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 565         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 566         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 567         { 0x0, 0x33, 0x0C },    /* 2              1   */
 568         { 0x0, 0x00, 0x00 },    /* 3              0   */
 569 };
 570
 571 static const struct ddi_buf_trans *
 572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 573 {
 574         if (dev_priv->vbt.edp.low_vswing) {
 575                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 576                 return bdw_ddi_translations_edp;
 577         } else {
 578                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 579                 return bdw_ddi_translations_dp;
 580         }
 581 }
 582
 583 static const struct ddi_buf_trans *
 584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 585 {
 586         if (IS_SKL_ULX(dev_priv)) {
 587                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 588                 return skl_y_ddi_translations_dp;
 589         } else if (IS_SKL_ULT(dev_priv)) {
 590                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 591                 return skl_u_ddi_translations_dp;
 592         } else {
 593                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 594                 return skl_ddi_translations_dp;
 595         }
 596 }
 597
 598 static const struct ddi_buf_trans *
 599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 600 {
 601         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 602                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 603                 return kbl_y_ddi_translations_dp;
 604         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 606                 return kbl_u_ddi_translations_dp;
 607         } else {
 608                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 609                 return kbl_ddi_translations_dp;
 610         }
 611 }
 612
 613 static const struct ddi_buf_trans *
 614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 615 {
 616         if (dev_priv->vbt.edp.low_vswing) {
 617                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 618                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 619                         return skl_y_ddi_translations_edp;
 620                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 621                            IS_CFL_ULT(dev_priv)) {
 622                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 623                         return skl_u_ddi_translations_edp;
 624                 } else {
 625                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 626                         return skl_ddi_translations_edp;
 627                 }
 628         }
 629
 630         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 631                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 632         else
 633                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 634 }
 635
 636 static const struct ddi_buf_trans *
 637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 638 {
 639         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 640                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 641                 return skl_y_ddi_translations_hdmi;
 642         } else {
 643                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 644                 return skl_ddi_translations_hdmi;
 645         }
 646 }
 647
 648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 649 {
 650         /* Only DDIA and DDIE can select the 10th register with DP */
 651         if (port == PORT_A || port == PORT_E)
 652                 return min(n_entries, 10);
 653         else
 654                 return min(n_entries, 9);
 655 }
 656
 657 static const struct ddi_buf_trans *
 658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 659                            enum port port, int *n_entries)
 660 {
 661         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 662                 const struct ddi_buf_trans *ddi_translations =
 663                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 664                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 665                 return ddi_translations;
 666         } else if (IS_SKYLAKE(dev_priv)) {
 667                 const struct ddi_buf_trans *ddi_translations =
 668                         skl_get_buf_trans_dp(dev_priv, n_entries);
 669                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 670                 return ddi_translations;
 671         } else if (IS_BROADWELL(dev_priv)) {
 672                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 673                 return  bdw_ddi_translations_dp;
 674         } else if (IS_HASWELL(dev_priv)) {
 675                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 676                 return hsw_ddi_translations_dp;
 677         }
 678
 679         *n_entries = 0;
 680         return NULL;
 681 }
 682
 683 static const struct ddi_buf_trans *
 684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 685                             enum port port, int *n_entries)
 686 {
 687         if (IS_GEN9_BC(dev_priv)) {
 688                 const struct ddi_buf_trans *ddi_translations =
 689                         skl_get_buf_trans_edp(dev_priv, n_entries);
 690                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 691                 return ddi_translations;
 692         } else if (IS_BROADWELL(dev_priv)) {
 693                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 705                             int *n_entries)
 706 {
 707         if (IS_BROADWELL(dev_priv)) {
 708                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 709                 return bdw_ddi_translations_fdi;
 710         } else if (IS_HASWELL(dev_priv)) {
 711                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 712                 return hsw_ddi_translations_fdi;
 713         }
 714
 715         *n_entries = 0;
 716         return NULL;
 717 }
 718
 719 static const struct ddi_buf_trans *
 720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 721                              int *n_entries)
 722 {
 723         if (IS_GEN9_BC(dev_priv)) {
 724                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 725         } else if (IS_BROADWELL(dev_priv)) {
 726                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 727                 return bdw_ddi_translations_hdmi;
 728         } else if (IS_HASWELL(dev_priv)) {
 729                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 730                 return hsw_ddi_translations_hdmi;
 731         }
 732
 733         *n_entries = 0;
 734         return NULL;
 735 }
 736
 737 static const struct bxt_ddi_buf_trans *
 738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 739 {
 740         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 741         return bxt_ddi_translations_dp;
 742 }
 743
 744 static const struct bxt_ddi_buf_trans *
 745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 746 {
 747         if (dev_priv->vbt.edp.low_vswing) {
 748                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 749                 return bxt_ddi_translations_edp;
 750         }
 751
 752         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 753 }
 754
 755 static const struct bxt_ddi_buf_trans *
 756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 757 {
 758         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 759         return bxt_ddi_translations_hdmi;
 760 }
 761
 762 static const struct cnl_ddi_buf_trans *
 763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 764 {
 765         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 766
 767         if (voltage == VOLTAGE_INFO_0_85V) {
 768                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 769                 return cnl_ddi_translations_hdmi_0_85V;
 770         } else if (voltage == VOLTAGE_INFO_0_95V) {
 771                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 772                 return cnl_ddi_translations_hdmi_0_95V;
 773         } else if (voltage == VOLTAGE_INFO_1_05V) {
 774                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 775                 return cnl_ddi_translations_hdmi_1_05V;
 776         } else {
 777                 *n_entries = 1; /* shut up gcc */
 778                 MISSING_CASE(voltage);
 779         }
 780         return NULL;
 781 }
 782
 783 static const struct cnl_ddi_buf_trans *
 784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 785 {
 786         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 787
 788         if (voltage == VOLTAGE_INFO_0_85V) {
 789                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 790                 return cnl_ddi_translations_dp_0_85V;
 791         } else if (voltage == VOLTAGE_INFO_0_95V) {
 792                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 793                 return cnl_ddi_translations_dp_0_95V;
 794         } else if (voltage == VOLTAGE_INFO_1_05V) {
 795                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 796                 return cnl_ddi_translations_dp_1_05V;
 797         } else {
 798                 *n_entries = 1; /* shut up gcc */
 799                 MISSING_CASE(voltage);
 800         }
 801         return NULL;
 802 }
 803
 804 static const struct cnl_ddi_buf_trans *
 805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 806 {
 807         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 808
 809         if (dev_priv->vbt.edp.low_vswing) {
 810                 if (voltage == VOLTAGE_INFO_0_85V) {
 811                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 812                         return cnl_ddi_translations_edp_0_85V;
 813                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 814                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 815                         return cnl_ddi_translations_edp_0_95V;
 816                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 817                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 818                         return cnl_ddi_translations_edp_1_05V;
 819                 } else {
 820                         *n_entries = 1; /* shut up gcc */
 821                         MISSING_CASE(voltage);
 822                 }
 823                 return NULL;
 824         } else {
 825                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 826         }
 827 }
 828
 829 static const struct cnl_ddi_buf_trans *
 830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 831                         int type, int rate, int *n_entries)
 832 {
 833         if (type == INTEL_OUTPUT_HDMI) {
 834                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 835                 return icl_combo_phy_ddi_translations_hdmi;
 836         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 837                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 838                 return icl_combo_phy_ddi_translations_edp_hbr3;
 839         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 840                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 841                 return icl_combo_phy_ddi_translations_edp_hbr2;
 842         }
 843
 844         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 845         return icl_combo_phy_ddi_translations_dp_hbr2;
 846 }
 847
 848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 849 {
 850         int n_entries, level, default_entry;
 851
 852         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 853
 854         if (IS_ICELAKE(dev_priv)) {
 855                 if (intel_port_is_combophy(dev_priv, port))
 856                         icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
 857                                                 0, &n_entries);
 858                 else
 859                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 860                 default_entry = n_entries - 1;
 861         } else if (IS_CANNONLAKE(dev_priv)) {
 862                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 863                 default_entry = n_entries - 1;
 864         } else if (IS_GEN9_LP(dev_priv)) {
 865                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 866                 default_entry = n_entries - 1;
 867         } else if (IS_GEN9_BC(dev_priv)) {
 868                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 869                 default_entry = 8;
 870         } else if (IS_BROADWELL(dev_priv)) {
 871                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 872                 default_entry = 7;
 873         } else if (IS_HASWELL(dev_priv)) {
 874                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 875                 default_entry = 6;
 876         } else {
 877                 WARN(1, "ddi translation table missing\n");
 878                 return 0;
 879         }
 880
 881         /* Choose a good default if VBT is badly populated */
 882         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 883                 level = default_entry;
 884
 885         if (WARN_ON_ONCE(n_entries == 0))
 886                 return 0;
 887         if (WARN_ON_ONCE(level >= n_entries))
 888                 level = n_entries - 1;
 889
 890         return level;
 891 }
 892
 893 /*
 894  * Starting with Haswell, DDI port buffers must be programmed with correct
 895  * values in advance. This function programs the correct values for
 896  * DP/eDP/FDI use cases.
 897  */
 898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 899                                          const struct intel_crtc_state *crtc_state)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 902         u32 iboost_bit = 0;
 903         int i, n_entries;
 904         enum port port = encoder->port;
 905         const struct ddi_buf_trans *ddi_translations;
 906
 907         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 908                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 909                                                                &n_entries);
 910         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 911                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 912                                                                &n_entries);
 913         else
 914                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 915                                                               &n_entries);
 916
 917         /* If we're boosting the current, set bit 31 of trans1 */
 918         if (IS_GEN9_BC(dev_priv) &&
 919             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 920                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 921
 922         for (i = 0; i < n_entries; i++) {
 923                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 924                            ddi_translations[i].trans1 | iboost_bit);
 925                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 926                            ddi_translations[i].trans2);
 927         }
 928 }
 929
 930 /*
 931  * Starting with Haswell, DDI port buffers must be programmed with correct
 932  * values in advance. This function programs the correct values for
 933  * HDMI/DVI use cases.
 934  */
 935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 936                                            int level)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 939         u32 iboost_bit = 0;
 940         int n_entries;
 941         enum port port = encoder->port;
 942         const struct ddi_buf_trans *ddi_translations;
 943
 944         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 945
 946         if (WARN_ON_ONCE(!ddi_translations))
 947                 return;
 948         if (WARN_ON_ONCE(level >= n_entries))
 949                 level = n_entries - 1;
 950
 951         /* If we're boosting the current, set bit 31 of trans1 */
 952         if (IS_GEN9_BC(dev_priv) &&
 953             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 954                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 955
 956         /* Entry 9 is for HDMI: */
 957         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 958                    ddi_translations[level].trans1 | iboost_bit);
 959         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 960                    ddi_translations[level].trans2);
 961 }
 962
 963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 964                                     enum port port)
 965 {
 966         i915_reg_t reg = DDI_BUF_CTL(port);
 967         int i;
 968
 969         for (i = 0; i < 16; i++) {
 970                 udelay(1);
 971                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 972                         return;
 973         }
 974         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 975 }
 976
 977 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 978 {
 979         switch (pll->info->id) {
 980         case DPLL_ID_WRPLL1:
 981                 return PORT_CLK_SEL_WRPLL1;
 982         case DPLL_ID_WRPLL2:
 983                 return PORT_CLK_SEL_WRPLL2;
 984         case DPLL_ID_SPLL:
 985                 return PORT_CLK_SEL_SPLL;
 986         case DPLL_ID_LCPLL_810:
 987                 return PORT_CLK_SEL_LCPLL_810;
 988         case DPLL_ID_LCPLL_1350:
 989                 return PORT_CLK_SEL_LCPLL_1350;
 990         case DPLL_ID_LCPLL_2700:
 991                 return PORT_CLK_SEL_LCPLL_2700;
 992         default:
 993                 MISSING_CASE(pll->info->id);
 994                 return PORT_CLK_SEL_NONE;
 995         }
 996 }
 997
 998 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
 999                                        const struct intel_crtc_state *crtc_state)
1000 {
1001         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002         int clock = crtc_state->port_clock;
1003         const enum intel_dpll_id id = pll->info->id;
1004
1005         switch (id) {
1006         default:
1007                 MISSING_CASE(id);
1008                 /* fall through */
1009         case DPLL_ID_ICL_DPLL0:
1010         case DPLL_ID_ICL_DPLL1:
1011                 return DDI_CLK_SEL_NONE;
1012         case DPLL_ID_ICL_TBTPLL:
1013                 switch (clock) {
1014                 case 162000:
1015                         return DDI_CLK_SEL_TBT_162;
1016                 case 270000:
1017                         return DDI_CLK_SEL_TBT_270;
1018                 case 540000:
1019                         return DDI_CLK_SEL_TBT_540;
1020                 case 810000:
1021                         return DDI_CLK_SEL_TBT_810;
1022                 default:
1023                         MISSING_CASE(clock);
1024                         break;
1025                 }
1026         case DPLL_ID_ICL_MGPLL1:
1027         case DPLL_ID_ICL_MGPLL2:
1028         case DPLL_ID_ICL_MGPLL3:
1029         case DPLL_ID_ICL_MGPLL4:
1030                 return DDI_CLK_SEL_MG;
1031         }
1032 }
1033
1034 /* Starting with Haswell, different DDI ports can work in FDI mode for
1035  * connection to the PCH-located connectors. For this, it is necessary to train
1036  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1037  *
1038  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1039  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1040  * DDI A (which is used for eDP)
1041  */
1042
1043 void hsw_fdi_link_train(struct intel_crtc *crtc,
1044                         const struct intel_crtc_state *crtc_state)
1045 {
1046         struct drm_device *dev = crtc->base.dev;
1047         struct drm_i915_private *dev_priv = to_i915(dev);
1048         struct intel_encoder *encoder;
1049         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1050
1051         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1052                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1053                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1054         }
1055
1056         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1057          * mode set "sequence for CRT port" document:
1058          * - TP1 to TP2 time with the default value
1059          * - FDI delay to 90h
1060          *
1061          * WaFDIAutoLinkSetTimingOverrride:hsw
1062          */
1063         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1064                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1065                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1066
1067         /* Enable the PCH Receiver FDI PLL */
1068         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1069                      FDI_RX_PLL_ENABLE |
1070                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1071         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1072         POSTING_READ(FDI_RX_CTL(PIPE_A));
1073         udelay(220);
1074
1075         /* Switch from Rawclk to PCDclk */
1076         rx_ctl_val |= FDI_PCDCLK;
1077         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1078
1079         /* Configure Port Clock Select */
1080         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1081         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1082         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1083
1084         /* Start the training iterating through available voltages and emphasis,
1085          * testing each value twice. */
1086         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1087                 /* Configure DP_TP_CTL with auto-training */
1088                 I915_WRITE(DP_TP_CTL(PORT_E),
1089                                         DP_TP_CTL_FDI_AUTOTRAIN |
1090                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1091                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1092                                         DP_TP_CTL_ENABLE);
1093
1094                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1095                  * DDI E does not support port reversal, the functionality is
1096                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1097                  * port reversal bit */
1098                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1099                            DDI_BUF_CTL_ENABLE |
1100                            ((crtc_state->fdi_lanes - 1) << 1) |
1101                            DDI_BUF_TRANS_SELECT(i / 2));
1102                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1103
1104                 udelay(600);
1105
1106                 /* Program PCH FDI Receiver TU */
1107                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1108
1109                 /* Enable PCH FDI Receiver with auto-training */
1110                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1111                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1112                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1113
1114                 /* Wait for FDI receiver lane calibration */
1115                 udelay(30);
1116
1117                 /* Unset FDI_RX_MISC pwrdn lanes */
1118                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1119                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1120                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1121                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1122
1123                 /* Wait for FDI auto training time */
1124                 udelay(5);
1125
1126                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1127                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1128                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1129                         break;
1130                 }
1131
1132                 /*
1133                  * Leave things enabled even if we failed to train FDI.
1134                  * Results in less fireworks from the state checker.
1135                  */
1136                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1137                         DRM_ERROR("FDI link training failed!\n");
1138                         break;
1139                 }
1140
1141                 rx_ctl_val &= ~FDI_RX_ENABLE;
1142                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1143                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1144
1145                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1146                 temp &= ~DDI_BUF_CTL_ENABLE;
1147                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1148                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1149
1150                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1151                 temp = I915_READ(DP_TP_CTL(PORT_E));
1152                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1153                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1154                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1155                 POSTING_READ(DP_TP_CTL(PORT_E));
1156
1157                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1158
1159                 /* Reset FDI_RX_MISC pwrdn lanes */
1160                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1161                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1162                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1163                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1164                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1165         }
1166
1167         /* Enable normal pixel sending for FDI */
1168         I915_WRITE(DP_TP_CTL(PORT_E),
1169                    DP_TP_CTL_FDI_AUTOTRAIN |
1170                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1171                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1172                    DP_TP_CTL_ENABLE);
1173 }
1174
1175 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1176 {
1177         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1178         struct intel_digital_port *intel_dig_port =
1179                 enc_to_dig_port(&encoder->base);
1180
1181         intel_dp->DP = intel_dig_port->saved_port_bits |
1182                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1183         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1184 }
1185
1186 static struct intel_encoder *
1187 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1188 {
1189         struct drm_device *dev = crtc->base.dev;
1190         struct intel_encoder *encoder, *ret = NULL;
1191         int num_encoders = 0;
1192
1193         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1194                 ret = encoder;
1195                 num_encoders++;
1196         }
1197
1198         if (num_encoders != 1)
1199                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1200                      pipe_name(crtc->pipe));
1201
1202         BUG_ON(ret == NULL);
1203         return ret;
1204 }
1205
1206 #define LC_FREQ 2700
1207
1208 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1209                                    i915_reg_t reg)
1210 {
1211         int refclk = LC_FREQ;
1212         int n, p, r;
1213         u32 wrpll;
1214
1215         wrpll = I915_READ(reg);
1216         switch (wrpll & WRPLL_PLL_REF_MASK) {
1217         case WRPLL_PLL_SSC:
1218         case WRPLL_PLL_NON_SSC:
1219                 /*
1220                  * We could calculate spread here, but our checking
1221                  * code only cares about 5% accuracy, and spread is a max of
1222                  * 0.5% downspread.
1223                  */
1224                 refclk = 135;
1225                 break;
1226         case WRPLL_PLL_LCPLL:
1227                 refclk = LC_FREQ;
1228                 break;
1229         default:
1230                 WARN(1, "bad wrpll refclk\n");
1231                 return 0;
1232         }
1233
1234         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1235         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1236         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1237
1238         /* Convert to KHz, p & r have a fixed point portion */
1239         return (refclk * n * 100) / (p * r);
1240 }
1241
1242 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1243                                enum intel_dpll_id pll_id)
1244 {
1245         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1246         uint32_t cfgcr1_val, cfgcr2_val;
1247         uint32_t p0, p1, p2, dco_freq;
1248
1249         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1250         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1251
1252         cfgcr1_val = I915_READ(cfgcr1_reg);
1253         cfgcr2_val = I915_READ(cfgcr2_reg);
1254
1255         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1256         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1257
1258         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1259                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1260         else
1261                 p1 = 1;
1262
1263
1264         switch (p0) {
1265         case DPLL_CFGCR2_PDIV_1:
1266                 p0 = 1;
1267                 break;
1268         case DPLL_CFGCR2_PDIV_2:
1269                 p0 = 2;
1270                 break;
1271         case DPLL_CFGCR2_PDIV_3:
1272                 p0 = 3;
1273                 break;
1274         case DPLL_CFGCR2_PDIV_7:
1275                 p0 = 7;
1276                 break;
1277         }
1278
1279         switch (p2) {
1280         case DPLL_CFGCR2_KDIV_5:
1281                 p2 = 5;
1282                 break;
1283         case DPLL_CFGCR2_KDIV_2:
1284                 p2 = 2;
1285                 break;
1286         case DPLL_CFGCR2_KDIV_3:
1287                 p2 = 3;
1288                 break;
1289         case DPLL_CFGCR2_KDIV_1:
1290                 p2 = 1;
1291                 break;
1292         }
1293
1294         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1295
1296         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1297                 1000) / 0x8000;
1298
1299         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1300                 return 0;
1301
1302         return dco_freq / (p0 * p1 * p2 * 5);
1303 }
1304
1305 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1306                         enum intel_dpll_id pll_id)
1307 {
1308         uint32_t cfgcr0, cfgcr1;
1309         uint32_t p0, p1, p2, dco_freq, ref_clock;
1310
1311         if (INTEL_GEN(dev_priv) >= 11) {
1312                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1313                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1314         } else {
1315                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1316                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1317         }
1318
1319         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1320         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1321
1322         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1323                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1324                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1325         else
1326                 p1 = 1;
1327
1328
1329         switch (p0) {
1330         case DPLL_CFGCR1_PDIV_2:
1331                 p0 = 2;
1332                 break;
1333         case DPLL_CFGCR1_PDIV_3:
1334                 p0 = 3;
1335                 break;
1336         case DPLL_CFGCR1_PDIV_5:
1337                 p0 = 5;
1338                 break;
1339         case DPLL_CFGCR1_PDIV_7:
1340                 p0 = 7;
1341                 break;
1342         }
1343
1344         switch (p2) {
1345         case DPLL_CFGCR1_KDIV_1:
1346                 p2 = 1;
1347                 break;
1348         case DPLL_CFGCR1_KDIV_2:
1349                 p2 = 2;
1350                 break;
1351         case DPLL_CFGCR1_KDIV_4:
1352                 p2 = 4;
1353                 break;
1354         }
1355
1356         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1357
1358         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1359
1360         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1361                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1362
1363         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1364                 return 0;
1365
1366         return dco_freq / (p0 * p1 * p2 * 5);
1367 }
1368
1369 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1370                                  enum port port)
1371 {
1372         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1373
1374         switch (val) {
1375         case DDI_CLK_SEL_NONE:
1376                 return 0;
1377         case DDI_CLK_SEL_TBT_162:
1378                 return 162000;
1379         case DDI_CLK_SEL_TBT_270:
1380                 return 270000;
1381         case DDI_CLK_SEL_TBT_540:
1382                 return 540000;
1383         case DDI_CLK_SEL_TBT_810:
1384                 return 810000;
1385         default:
1386                 MISSING_CASE(val);
1387                 return 0;
1388         }
1389 }
1390
1391 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1392                                 enum port port)
1393 {
1394         u32 mg_pll_div0, mg_clktop_hsclkctl;
1395         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1396         u64 tmp;
1397
1398         refclk = dev_priv->cdclk.hw.ref;
1399
1400         mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1401         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1402
1403         m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1404         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1405         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1406                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1407                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1408
1409         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1410         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1411                 div1 = 2;
1412                 break;
1413         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1414                 div1 = 3;
1415                 break;
1416         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1417                 div1 = 5;
1418                 break;
1419         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1420                 div1 = 7;
1421                 break;
1422         default:
1423                 MISSING_CASE(mg_clktop_hsclkctl);
1424                 return 0;
1425         }
1426
1427         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1428                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1429         /* div2 value of 0 is same as 1 means no div */
1430         if (div2 == 0)
1431                 div2 = 1;
1432
1433         /*
1434          * Adjust the original formula to delay the division by 2^22 in order to
1435          * minimize possible rounding errors.
1436          */
1437         tmp = (u64)m1 * m2_int * refclk +
1438               (((u64)m1 * m2_frac * refclk) >> 22);
1439         tmp = div_u64(tmp, 5 * div1 * div2);
1440
1441         return tmp;
1442 }
1443
1444 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1445 {
1446         int dotclock;
1447
1448         if (pipe_config->has_pch_encoder)
1449                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1450                                                     &pipe_config->fdi_m_n);
1451         else if (intel_crtc_has_dp_encoder(pipe_config))
1452                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1453                                                     &pipe_config->dp_m_n);
1454         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1455                 dotclock = pipe_config->port_clock * 2 / 3;
1456         else
1457                 dotclock = pipe_config->port_clock;
1458
1459         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1460                 dotclock *= 2;
1461
1462         if (pipe_config->pixel_multiplier)
1463                 dotclock /= pipe_config->pixel_multiplier;
1464
1465         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1466 }
1467
1468 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1469                               struct intel_crtc_state *pipe_config)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1472         enum port port = encoder->port;
1473         int link_clock = 0;
1474         uint32_t pll_id;
1475
1476         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1477         if (intel_port_is_combophy(dev_priv, port)) {
1478                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1479                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1480                 else
1481                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1482                                                                 pll_id);
1483         } else {
1484                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1485                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1486                 else
1487                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1488         }
1489
1490         pipe_config->port_clock = link_clock;
1491         ddi_dotclock_get(pipe_config);
1492 }
1493
1494 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1495                               struct intel_crtc_state *pipe_config)
1496 {
1497         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1498         int link_clock = 0;
1499         uint32_t cfgcr0;
1500         enum intel_dpll_id pll_id;
1501
1502         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1503
1504         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1505
1506         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1507                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1508         } else {
1509                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1510
1511                 switch (link_clock) {
1512                 case DPLL_CFGCR0_LINK_RATE_810:
1513                         link_clock = 81000;
1514                         break;
1515                 case DPLL_CFGCR0_LINK_RATE_1080:
1516                         link_clock = 108000;
1517                         break;
1518                 case DPLL_CFGCR0_LINK_RATE_1350:
1519                         link_clock = 135000;
1520                         break;
1521                 case DPLL_CFGCR0_LINK_RATE_1620:
1522                         link_clock = 162000;
1523                         break;
1524                 case DPLL_CFGCR0_LINK_RATE_2160:
1525                         link_clock = 216000;
1526                         break;
1527                 case DPLL_CFGCR0_LINK_RATE_2700:
1528                         link_clock = 270000;
1529                         break;
1530                 case DPLL_CFGCR0_LINK_RATE_3240:
1531                         link_clock = 324000;
1532                         break;
1533                 case DPLL_CFGCR0_LINK_RATE_4050:
1534                         link_clock = 405000;
1535                         break;
1536                 default:
1537                         WARN(1, "Unsupported link rate\n");
1538                         break;
1539                 }
1540                 link_clock *= 2;
1541         }
1542
1543         pipe_config->port_clock = link_clock;
1544
1545         ddi_dotclock_get(pipe_config);
1546 }
1547
1548 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1549                                 struct intel_crtc_state *pipe_config)
1550 {
1551         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1552         int link_clock = 0;
1553         uint32_t dpll_ctl1;
1554         enum intel_dpll_id pll_id;
1555
1556         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1557
1558         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1559
1560         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1561                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1562         } else {
1563                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1564                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1565
1566                 switch (link_clock) {
1567                 case DPLL_CTRL1_LINK_RATE_810:
1568                         link_clock = 81000;
1569                         break;
1570                 case DPLL_CTRL1_LINK_RATE_1080:
1571                         link_clock = 108000;
1572                         break;
1573                 case DPLL_CTRL1_LINK_RATE_1350:
1574                         link_clock = 135000;
1575                         break;
1576                 case DPLL_CTRL1_LINK_RATE_1620:
1577                         link_clock = 162000;
1578                         break;
1579                 case DPLL_CTRL1_LINK_RATE_2160:
1580                         link_clock = 216000;
1581                         break;
1582                 case DPLL_CTRL1_LINK_RATE_2700:
1583                         link_clock = 270000;
1584                         break;
1585                 default:
1586                         WARN(1, "Unsupported link rate\n");
1587                         break;
1588                 }
1589                 link_clock *= 2;
1590         }
1591
1592         pipe_config->port_clock = link_clock;
1593
1594         ddi_dotclock_get(pipe_config);
1595 }
1596
1597 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1598                               struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1601         int link_clock = 0;
1602         u32 val, pll;
1603
1604         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1605         switch (val & PORT_CLK_SEL_MASK) {
1606         case PORT_CLK_SEL_LCPLL_810:
1607                 link_clock = 81000;
1608                 break;
1609         case PORT_CLK_SEL_LCPLL_1350:
1610                 link_clock = 135000;
1611                 break;
1612         case PORT_CLK_SEL_LCPLL_2700:
1613                 link_clock = 270000;
1614                 break;
1615         case PORT_CLK_SEL_WRPLL1:
1616                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1617                 break;
1618         case PORT_CLK_SEL_WRPLL2:
1619                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1620                 break;
1621         case PORT_CLK_SEL_SPLL:
1622                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1623                 if (pll == SPLL_PLL_FREQ_810MHz)
1624                         link_clock = 81000;
1625                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1626                         link_clock = 135000;
1627                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1628                         link_clock = 270000;
1629                 else {
1630                         WARN(1, "bad spll freq\n");
1631                         return;
1632                 }
1633                 break;
1634         default:
1635                 WARN(1, "bad port clock sel\n");
1636                 return;
1637         }
1638
1639         pipe_config->port_clock = link_clock * 2;
1640
1641         ddi_dotclock_get(pipe_config);
1642 }
1643
1644 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1645 {
1646         struct intel_dpll_hw_state *state;
1647         struct dpll clock;
1648
1649         /* For DDI ports we always use a shared PLL. */
1650         if (WARN_ON(!crtc_state->shared_dpll))
1651                 return 0;
1652
1653         state = &crtc_state->dpll_hw_state;
1654
1655         clock.m1 = 2;
1656         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1657         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1658                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1659         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1660         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1661         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1662
1663         return chv_calc_dpll_params(100000, &clock);
1664 }
1665
1666 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1667                               struct intel_crtc_state *pipe_config)
1668 {
1669         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1670
1671         ddi_dotclock_get(pipe_config);
1672 }
1673
1674 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1675                                 struct intel_crtc_state *pipe_config)
1676 {
1677         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1678
1679         if (IS_ICELAKE(dev_priv))
1680                 icl_ddi_clock_get(encoder, pipe_config);
1681         else if (IS_CANNONLAKE(dev_priv))
1682                 cnl_ddi_clock_get(encoder, pipe_config);
1683         else if (IS_GEN9_LP(dev_priv))
1684                 bxt_ddi_clock_get(encoder, pipe_config);
1685         else if (IS_GEN9_BC(dev_priv))
1686                 skl_ddi_clock_get(encoder, pipe_config);
1687         else if (INTEL_GEN(dev_priv) <= 8)
1688                 hsw_ddi_clock_get(encoder, pipe_config);
1689 }
1690
1691 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1692 {
1693         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1694         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1695         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1696         u32 temp;
1697
1698         if (!intel_crtc_has_dp_encoder(crtc_state))
1699                 return;
1700
1701         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1702
1703         temp = TRANS_MSA_SYNC_CLK;
1704
1705         if (crtc_state->limited_color_range)
1706                 temp |= TRANS_MSA_CEA_RANGE;
1707
1708         switch (crtc_state->pipe_bpp) {
1709         case 18:
1710                 temp |= TRANS_MSA_6_BPC;
1711                 break;
1712         case 24:
1713                 temp |= TRANS_MSA_8_BPC;
1714                 break;
1715         case 30:
1716                 temp |= TRANS_MSA_10_BPC;
1717                 break;
1718         case 36:
1719                 temp |= TRANS_MSA_12_BPC;
1720                 break;
1721         default:
1722                 MISSING_CASE(crtc_state->pipe_bpp);
1723                 break;
1724         }
1725
1726         /*
1727          * As per DP 1.2 spec section 2.3.4.3 while sending
1728          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1729          * colorspace information. The output colorspace encoding is BT601.
1730          */
1731         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1732                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1733         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1734 }
1735
1736 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1737                                     bool state)
1738 {
1739         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1740         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1741         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1742         uint32_t temp;
1743
1744         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1745         if (state == true)
1746                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1747         else
1748                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1749         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1750 }
1751
1752 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1753 {
1754         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1755         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1757         enum pipe pipe = crtc->pipe;
1758         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1759         enum port port = encoder->port;
1760         uint32_t temp;
1761
1762         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1763         temp = TRANS_DDI_FUNC_ENABLE;
1764         temp |= TRANS_DDI_SELECT_PORT(port);
1765
1766         switch (crtc_state->pipe_bpp) {
1767         case 18:
1768                 temp |= TRANS_DDI_BPC_6;
1769                 break;
1770         case 24:
1771                 temp |= TRANS_DDI_BPC_8;
1772                 break;
1773         case 30:
1774                 temp |= TRANS_DDI_BPC_10;
1775                 break;
1776         case 36:
1777                 temp |= TRANS_DDI_BPC_12;
1778                 break;
1779         default:
1780                 BUG();
1781         }
1782
1783         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1784                 temp |= TRANS_DDI_PVSYNC;
1785         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1786                 temp |= TRANS_DDI_PHSYNC;
1787
1788         if (cpu_transcoder == TRANSCODER_EDP) {
1789                 switch (pipe) {
1790                 case PIPE_A:
1791                         /* On Haswell, can only use the always-on power well for
1792                          * eDP when not using the panel fitter, and when not
1793                          * using motion blur mitigation (which we don't
1794                          * support). */
1795                         if (IS_HASWELL(dev_priv) &&
1796                             (crtc_state->pch_pfit.enabled ||
1797                              crtc_state->pch_pfit.force_thru))
1798                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1799                         else
1800                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1801                         break;
1802                 case PIPE_B:
1803                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1804                         break;
1805                 case PIPE_C:
1806                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1807                         break;
1808                 default:
1809                         BUG();
1810                         break;
1811                 }
1812         }
1813
1814         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1815                 if (crtc_state->has_hdmi_sink)
1816                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1817                 else
1818                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1819
1820                 if (crtc_state->hdmi_scrambling)
1821                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1822                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1823                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1824         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1825                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1826                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1827         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1828                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1829                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1830         } else {
1831                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1832                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1833         }
1834
1835         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1836 }
1837
1838 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1841         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1843         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1844         uint32_t val = I915_READ(reg);
1845
1846         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1847         val |= TRANS_DDI_PORT_NONE;
1848         I915_WRITE(reg, val);
1849
1850         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1851             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1852                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1853                 /* Quirk time at 100ms for reliable operation */
1854                 msleep(100);
1855         }
1856 }
1857
1858 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1859                                      bool enable)
1860 {
1861         struct drm_device *dev = intel_encoder->base.dev;
1862         struct drm_i915_private *dev_priv = to_i915(dev);
1863         intel_wakeref_t wakeref;
1864         enum pipe pipe = 0;
1865         int ret = 0;
1866         uint32_t tmp;
1867
1868         wakeref = intel_display_power_get_if_enabled(dev_priv,
1869                                                      intel_encoder->power_domain);
1870         if (WARN_ON(!wakeref))
1871                 return -ENXIO;
1872
1873         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1874                 ret = -EIO;
1875                 goto out;
1876         }
1877
1878         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1879         if (enable)
1880                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1881         else
1882                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1883         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1884 out:
1885         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1886         return ret;
1887 }
1888
1889 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1890 {
1891         struct drm_device *dev = intel_connector->base.dev;
1892         struct drm_i915_private *dev_priv = to_i915(dev);
1893         struct intel_encoder *encoder = intel_connector->encoder;
1894         int type = intel_connector->base.connector_type;
1895         enum port port = encoder->port;
1896         enum transcoder cpu_transcoder;
1897         intel_wakeref_t wakeref;
1898         enum pipe pipe = 0;
1899         uint32_t tmp;
1900         bool ret;
1901
1902         wakeref = intel_display_power_get_if_enabled(dev_priv,
1903                                                      encoder->power_domain);
1904         if (!wakeref)
1905                 return false;
1906
1907         if (!encoder->get_hw_state(encoder, &pipe)) {
1908                 ret = false;
1909                 goto out;
1910         }
1911
1912         if (port == PORT_A)
1913                 cpu_transcoder = TRANSCODER_EDP;
1914         else
1915                 cpu_transcoder = (enum transcoder) pipe;
1916
1917         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1918
1919         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1920         case TRANS_DDI_MODE_SELECT_HDMI:
1921         case TRANS_DDI_MODE_SELECT_DVI:
1922                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1923                 break;
1924
1925         case TRANS_DDI_MODE_SELECT_DP_SST:
1926                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1927                       type == DRM_MODE_CONNECTOR_DisplayPort;
1928                 break;
1929
1930         case TRANS_DDI_MODE_SELECT_DP_MST:
1931                 /* if the transcoder is in MST state then
1932                  * connector isn't connected */
1933                 ret = false;
1934                 break;
1935
1936         case TRANS_DDI_MODE_SELECT_FDI:
1937                 ret = type == DRM_MODE_CONNECTOR_VGA;
1938                 break;
1939
1940         default:
1941                 ret = false;
1942                 break;
1943         }
1944
1945 out:
1946         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1947
1948         return ret;
1949 }
1950
1951 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1952                                         u8 *pipe_mask, bool *is_dp_mst)
1953 {
1954         struct drm_device *dev = encoder->base.dev;
1955         struct drm_i915_private *dev_priv = to_i915(dev);
1956         enum port port = encoder->port;
1957         intel_wakeref_t wakeref;
1958         enum pipe p;
1959         u32 tmp;
1960         u8 mst_pipe_mask;
1961
1962         *pipe_mask = 0;
1963         *is_dp_mst = false;
1964
1965         wakeref = intel_display_power_get_if_enabled(dev_priv,
1966                                                      encoder->power_domain);
1967         if (!wakeref)
1968                 return;
1969
1970         tmp = I915_READ(DDI_BUF_CTL(port));
1971         if (!(tmp & DDI_BUF_CTL_ENABLE))
1972                 goto out;
1973
1974         if (port == PORT_A) {
1975                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1976
1977                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1978                 default:
1979                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1980                         /* fallthrough */
1981                 case TRANS_DDI_EDP_INPUT_A_ON:
1982                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1983                         *pipe_mask = BIT(PIPE_A);
1984                         break;
1985                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1986                         *pipe_mask = BIT(PIPE_B);
1987                         break;
1988                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1989                         *pipe_mask = BIT(PIPE_C);
1990                         break;
1991                 }
1992
1993                 goto out;
1994         }
1995
1996         mst_pipe_mask = 0;
1997         for_each_pipe(dev_priv, p) {
1998                 enum transcoder cpu_transcoder = (enum transcoder)p;
1999
2000                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2001
2002                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2003                         continue;
2004
2005                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2006                     TRANS_DDI_MODE_SELECT_DP_MST)
2007                         mst_pipe_mask |= BIT(p);
2008
2009                 *pipe_mask |= BIT(p);
2010         }
2011
2012         if (!*pipe_mask)
2013                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2014                               port_name(port));
2015
2016         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2017                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2018                               port_name(port), *pipe_mask);
2019                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2020         }
2021
2022         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2023                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2024                               port_name(port), *pipe_mask, mst_pipe_mask);
2025         else
2026                 *is_dp_mst = mst_pipe_mask;
2027
2028 out:
2029         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2030                 tmp = I915_READ(BXT_PHY_CTL(port));
2031                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2032                             BXT_PHY_LANE_POWERDOWN_ACK |
2033                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2034                         DRM_ERROR("Port %c enabled but PHY powered down? "
2035                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2036         }
2037
2038         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2039 }
2040
2041 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2042                             enum pipe *pipe)
2043 {
2044         u8 pipe_mask;
2045         bool is_mst;
2046
2047         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2048
2049         if (is_mst || !pipe_mask)
2050                 return false;
2051
2052         *pipe = ffs(pipe_mask) - 1;
2053
2054         return true;
2055 }
2056
2057 static inline enum intel_display_power_domain
2058 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2059 {
2060         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2061          * DC states enabled at the same time, while for driver initiated AUX
2062          * transfers we need the same AUX IOs to be powered but with DC states
2063          * disabled. Accordingly use the AUX power domain here which leaves DC
2064          * states enabled.
2065          * However, for non-A AUX ports the corresponding non-EDP transcoders
2066          * would have already enabled power well 2 and DC_OFF. This means we can
2067          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2068          * specific AUX_IO reference without powering up any extra wells.
2069          * Note that PSR is enabled only on Port A even though this function
2070          * returns the correct domain for other ports too.
2071          */
2072         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2073                                               intel_aux_power_domain(dig_port);
2074 }
2075
2076 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2077                                        struct intel_crtc_state *crtc_state)
2078 {
2079         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2080         struct intel_digital_port *dig_port;
2081         u64 domains;
2082
2083         /*
2084          * TODO: Add support for MST encoders. Atm, the following should never
2085          * happen since fake-MST encoders don't set their get_power_domains()
2086          * hook.
2087          */
2088         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2089                 return 0;
2090
2091         dig_port = enc_to_dig_port(&encoder->base);
2092         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2093
2094         /*
2095          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2096          * ports.
2097          */
2098         if (intel_crtc_has_dp_encoder(crtc_state) ||
2099             intel_port_is_tc(dev_priv, encoder->port))
2100                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2101
2102         /*
2103          * VDSC power is needed when DSC is enabled
2104          */
2105         if (crtc_state->dsc_params.compression_enable)
2106                 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2107
2108         return domains;
2109 }
2110
2111 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2112 {
2113         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2114         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2115         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2116         enum port port = encoder->port;
2117         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2118
2119         if (cpu_transcoder != TRANSCODER_EDP)
2120                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2121                            TRANS_CLK_SEL_PORT(port));
2122 }
2123
2124 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2125 {
2126         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2127         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2128
2129         if (cpu_transcoder != TRANSCODER_EDP)
2130                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2131                            TRANS_CLK_SEL_DISABLED);
2132 }
2133
2134 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2135                                 enum port port, uint8_t iboost)
2136 {
2137         u32 tmp;
2138
2139         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2140         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2141         if (iboost)
2142                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2143         else
2144                 tmp |= BALANCE_LEG_DISABLE(port);
2145         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2146 }
2147
2148 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2149                                int level, enum intel_output_type type)
2150 {
2151         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2152         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2153         enum port port = encoder->port;
2154         uint8_t iboost;
2155
2156         if (type == INTEL_OUTPUT_HDMI)
2157                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2158         else
2159                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2160
2161         if (iboost == 0) {
2162                 const struct ddi_buf_trans *ddi_translations;
2163                 int n_entries;
2164
2165                 if (type == INTEL_OUTPUT_HDMI)
2166                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2167                 else if (type == INTEL_OUTPUT_EDP)
2168                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2169                 else
2170                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2171
2172                 if (WARN_ON_ONCE(!ddi_translations))
2173                         return;
2174                 if (WARN_ON_ONCE(level >= n_entries))
2175                         level = n_entries - 1;
2176
2177                 iboost = ddi_translations[level].i_boost;
2178         }
2179
2180         /* Make sure that the requested I_boost is valid */
2181         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2182                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2183                 return;
2184         }
2185
2186         _skl_ddi_set_iboost(dev_priv, port, iboost);
2187
2188         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2189                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2190 }
2191
2192 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2193                                     int level, enum intel_output_type type)
2194 {
2195         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2196         const struct bxt_ddi_buf_trans *ddi_translations;
2197         enum port port = encoder->port;
2198         int n_entries;
2199
2200         if (type == INTEL_OUTPUT_HDMI)
2201                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2202         else if (type == INTEL_OUTPUT_EDP)
2203                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2204         else
2205                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2206
2207         if (WARN_ON_ONCE(!ddi_translations))
2208                 return;
2209         if (WARN_ON_ONCE(level >= n_entries))
2210                 level = n_entries - 1;
2211
2212         bxt_ddi_phy_set_signal_level(dev_priv, port,
2213                                      ddi_translations[level].margin,
2214                                      ddi_translations[level].scale,
2215                                      ddi_translations[level].enable,
2216                                      ddi_translations[level].deemphasis);
2217 }
2218
2219 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2220 {
2221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2222         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2223         enum port port = encoder->port;
2224         int n_entries;
2225
2226         if (IS_ICELAKE(dev_priv)) {
2227                 if (intel_port_is_combophy(dev_priv, port))
2228                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2229                                                 intel_dp->link_rate, &n_entries);
2230                 else
2231                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2232         } else if (IS_CANNONLAKE(dev_priv)) {
2233                 if (encoder->type == INTEL_OUTPUT_EDP)
2234                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2235                 else
2236                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2237         } else if (IS_GEN9_LP(dev_priv)) {
2238                 if (encoder->type == INTEL_OUTPUT_EDP)
2239                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2240                 else
2241                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2242         } else {
2243                 if (encoder->type == INTEL_OUTPUT_EDP)
2244                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2245                 else
2246                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2247         }
2248
2249         if (WARN_ON(n_entries < 1))
2250                 n_entries = 1;
2251         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2252                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2253
2254         return index_to_dp_signal_levels[n_entries - 1] &
2255                 DP_TRAIN_VOLTAGE_SWING_MASK;
2256 }
2257
2258 /*
2259  * We assume that the full set of pre-emphasis values can be
2260  * used on all DDI platforms. Should that change we need to
2261  * rethink this code.
2262  */
2263 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2264 {
2265         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2266         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2267                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2268         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2269                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2270         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2271                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2272         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2273         default:
2274                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2275         }
2276 }
2277
2278 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2279                                    int level, enum intel_output_type type)
2280 {
2281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2282         const struct cnl_ddi_buf_trans *ddi_translations;
2283         enum port port = encoder->port;
2284         int n_entries, ln;
2285         u32 val;
2286
2287         if (type == INTEL_OUTPUT_HDMI)
2288                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2289         else if (type == INTEL_OUTPUT_EDP)
2290                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2291         else
2292                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2293
2294         if (WARN_ON_ONCE(!ddi_translations))
2295                 return;
2296         if (WARN_ON_ONCE(level >= n_entries))
2297                 level = n_entries - 1;
2298
2299         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2300         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2301         val &= ~SCALING_MODE_SEL_MASK;
2302         val |= SCALING_MODE_SEL(2);
2303         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2304
2305         /* Program PORT_TX_DW2 */
2306         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2307         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2308                  RCOMP_SCALAR_MASK);
2309         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2310         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2311         /* Rcomp scalar is fixed as 0x98 for every table entry */
2312         val |= RCOMP_SCALAR(0x98);
2313         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2314
2315         /* Program PORT_TX_DW4 */
2316         /* We cannot write to GRP. It would overrite individual loadgen */
2317         for (ln = 0; ln < 4; ln++) {
2318                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2319                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2320                          CURSOR_COEFF_MASK);
2321                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2322                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2323                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2324                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2325         }
2326
2327         /* Program PORT_TX_DW5 */
2328         /* All DW5 values are fixed for every table entry */
2329         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2330         val &= ~RTERM_SELECT_MASK;
2331         val |= RTERM_SELECT(6);
2332         val |= TAP3_DISABLE;
2333         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2334
2335         /* Program PORT_TX_DW7 */
2336         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2337         val &= ~N_SCALAR_MASK;
2338         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2339         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2340 }
2341
2342 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2343                                     int level, enum intel_output_type type)
2344 {
2345         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2346         enum port port = encoder->port;
2347         int width, rate, ln;
2348         u32 val;
2349
2350         if (type == INTEL_OUTPUT_HDMI) {
2351                 width = 4;
2352                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2353         } else {
2354                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2355
2356                 width = intel_dp->lane_count;
2357                 rate = intel_dp->link_rate;
2358         }
2359
2360         /*
2361          * 1. If port type is eDP or DP,
2362          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2363          * else clear to 0b.
2364          */
2365         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2366         if (type != INTEL_OUTPUT_HDMI)
2367                 val |= COMMON_KEEPER_EN;
2368         else
2369                 val &= ~COMMON_KEEPER_EN;
2370         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2371
2372         /* 2. Program loadgen select */
2373         /*
2374          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2375          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2376          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2377          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2378          */
2379         for (ln = 0; ln <= 3; ln++) {
2380                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2381                 val &= ~LOADGEN_SELECT;
2382
2383                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2384                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2385                         val |= LOADGEN_SELECT;
2386                 }
2387                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2388         }
2389
2390         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2391         val = I915_READ(CNL_PORT_CL1CM_DW5);
2392         val |= SUS_CLOCK_CONFIG;
2393         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2394
2395         /* 4. Clear training enable to change swing values */
2396         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2397         val &= ~TX_TRAINING_EN;
2398         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2399
2400         /* 5. Program swing and de-emphasis */
2401         cnl_ddi_vswing_program(encoder, level, type);
2402
2403         /* 6. Set training enable to trigger update */
2404         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2405         val |= TX_TRAINING_EN;
2406         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2407 }
2408
2409 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2410                                         u32 level, enum port port, int type,
2411                                         int rate)
2412 {
2413         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2414         u32 n_entries, val;
2415         int ln;
2416
2417         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2418                                                    rate, &n_entries);
2419         if (!ddi_translations)
2420                 return;
2421
2422         if (level >= n_entries) {
2423                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2424                 level = n_entries - 1;
2425         }
2426
2427         /* Set PORT_TX_DW5 */
2428         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2429         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2430                   TAP2_DISABLE | TAP3_DISABLE);
2431         val |= SCALING_MODE_SEL(0x2);
2432         val |= RTERM_SELECT(0x6);
2433         val |= TAP3_DISABLE;
2434         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2435
2436         /* Program PORT_TX_DW2 */
2437         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2438         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2439                  RCOMP_SCALAR_MASK);
2440         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2441         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2442         /* Program Rcomp scalar for every table entry */
2443         val |= RCOMP_SCALAR(0x98);
2444         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2445
2446         /* Program PORT_TX_DW4 */
2447         /* We cannot write to GRP. It would overwrite individual loadgen. */
2448         for (ln = 0; ln <= 3; ln++) {
2449                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2450                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2451                          CURSOR_COEFF_MASK);
2452                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2453                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2454                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2455                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2456         }
2457
2458         /* Program PORT_TX_DW7 */
2459         val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2460         val &= ~N_SCALAR_MASK;
2461         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2462         I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2463 }
2464
2465 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2466                                               u32 level,
2467                                               enum intel_output_type type)
2468 {
2469         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2470         enum port port = encoder->port;
2471         int width = 0;
2472         int rate = 0;
2473         u32 val;
2474         int ln = 0;
2475
2476         if (type == INTEL_OUTPUT_HDMI) {
2477                 width = 4;
2478                 /* Rate is always < than 6GHz for HDMI */
2479         } else {
2480                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2481
2482                 width = intel_dp->lane_count;
2483                 rate = intel_dp->link_rate;
2484         }
2485
2486         /*
2487          * 1. If port type is eDP or DP,
2488          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2489          * else clear to 0b.
2490          */
2491         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2492         if (type == INTEL_OUTPUT_HDMI)
2493                 val &= ~COMMON_KEEPER_EN;
2494         else
2495                 val |= COMMON_KEEPER_EN;
2496         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2497
2498         /* 2. Program loadgen select */
2499         /*
2500          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2501          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2502          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2503          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2504          */
2505         for (ln = 0; ln <= 3; ln++) {
2506                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2507                 val &= ~LOADGEN_SELECT;
2508
2509                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2510                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2511                         val |= LOADGEN_SELECT;
2512                 }
2513                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2514         }
2515
2516         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2517         val = I915_READ(ICL_PORT_CL_DW5(port));
2518         val |= SUS_CLOCK_CONFIG;
2519         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2520
2521         /* 4. Clear training enable to change swing values */
2522         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2523         val &= ~TX_TRAINING_EN;
2524         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2525
2526         /* 5. Program swing and de-emphasis */
2527         icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2528
2529         /* 6. Set training enable to trigger update */
2530         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2531         val |= TX_TRAINING_EN;
2532         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2533 }
2534
2535 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2536                                            int link_clock,
2537                                            u32 level)
2538 {
2539         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2540         enum port port = encoder->port;
2541         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2542         u32 n_entries, val;
2543         int ln;
2544
2545         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2546         ddi_translations = icl_mg_phy_ddi_translations;
2547         /* The table does not have values for level 3 and level 9. */
2548         if (level >= n_entries || level == 3 || level == 9) {
2549                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2550                               level, n_entries - 2);
2551                 level = n_entries - 2;
2552         }
2553
2554         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2555         for (ln = 0; ln < 2; ln++) {
2556                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2557                 val &= ~CRI_USE_FS32;
2558                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2559
2560                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2561                 val &= ~CRI_USE_FS32;
2562                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2563         }
2564
2565         /* Program MG_TX_SWINGCTRL with values from vswing table */
2566         for (ln = 0; ln < 2; ln++) {
2567                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2568                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2569                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2570                         ddi_translations[level].cri_txdeemph_override_17_12);
2571                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2572
2573                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2574                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2575                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2576                         ddi_translations[level].cri_txdeemph_override_17_12);
2577                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2578         }
2579
2580         /* Program MG_TX_DRVCTRL with values from vswing table */
2581         for (ln = 0; ln < 2; ln++) {
2582                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2583                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2584                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2585                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2586                         ddi_translations[level].cri_txdeemph_override_5_0) |
2587                         CRI_TXDEEMPH_OVERRIDE_11_6(
2588                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2589                         CRI_TXDEEMPH_OVERRIDE_EN;
2590                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2591
2592                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2593                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2594                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2595                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2596                         ddi_translations[level].cri_txdeemph_override_5_0) |
2597                         CRI_TXDEEMPH_OVERRIDE_11_6(
2598                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2599                         CRI_TXDEEMPH_OVERRIDE_EN;
2600                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2601
2602                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2603         }
2604
2605         /*
2606          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2607          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2608          * values from table for which TX1 and TX2 enabled.
2609          */
2610         for (ln = 0; ln < 2; ln++) {
2611                 val = I915_READ(MG_CLKHUB(port, ln));
2612                 if (link_clock < 300000)
2613                         val |= CFG_LOW_RATE_LKREN_EN;
2614                 else
2615                         val &= ~CFG_LOW_RATE_LKREN_EN;
2616                 I915_WRITE(MG_CLKHUB(port, ln), val);
2617         }
2618
2619         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2620         for (ln = 0; ln < 2; ln++) {
2621                 val = I915_READ(MG_TX1_DCC(port, ln));
2622                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2623                 if (link_clock <= 500000) {
2624                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2625                 } else {
2626                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2627                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2628                 }
2629                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2630
2631                 val = I915_READ(MG_TX2_DCC(port, ln));
2632                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2633                 if (link_clock <= 500000) {
2634                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2635                 } else {
2636                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2637                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2638                 }
2639                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2640         }
2641
2642         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2643         for (ln = 0; ln < 2; ln++) {
2644                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2645                 val |= CRI_CALCINIT;
2646                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2647
2648                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2649                 val |= CRI_CALCINIT;
2650                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2651         }
2652 }
2653
2654 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2655                                     int link_clock,
2656                                     u32 level,
2657                                     enum intel_output_type type)
2658 {
2659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2660         enum port port = encoder->port;
2661
2662         if (intel_port_is_combophy(dev_priv, port))
2663                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2664         else
2665                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2666 }
2667
2668 static uint32_t translate_signal_level(int signal_levels)
2669 {
2670         int i;
2671
2672         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2673                 if (index_to_dp_signal_levels[i] == signal_levels)
2674                         return i;
2675         }
2676
2677         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2678              signal_levels);
2679
2680         return 0;
2681 }
2682
2683 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2684 {
2685         uint8_t train_set = intel_dp->train_set[0];
2686         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2687                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2688
2689         return translate_signal_level(signal_levels);
2690 }
2691
2692 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2693 {
2694         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2695         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2696         struct intel_encoder *encoder = &dport->base;
2697         int level = intel_ddi_dp_level(intel_dp);
2698
2699         if (IS_ICELAKE(dev_priv))
2700                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2701                                         level, encoder->type);
2702         else if (IS_CANNONLAKE(dev_priv))
2703                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2704         else
2705                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2706
2707         return 0;
2708 }
2709
2710 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2711 {
2712         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2713         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2714         struct intel_encoder *encoder = &dport->base;
2715         int level = intel_ddi_dp_level(intel_dp);
2716
2717         if (IS_GEN9_BC(dev_priv))
2718                 skl_ddi_set_iboost(encoder, level, encoder->type);
2719
2720         return DDI_BUF_TRANS_SELECT(level);
2721 }
2722
2723 static inline
2724 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2725                                    enum port port)
2726 {
2727         if (intel_port_is_combophy(dev_priv, port)) {
2728                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2729         } else if (intel_port_is_tc(dev_priv, port)) {
2730                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2731
2732                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2733         }
2734
2735         return 0;
2736 }
2737
2738 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2739                                   const struct intel_crtc_state *crtc_state)
2740 {
2741         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2742         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2743         enum port port = encoder->port;
2744         u32 val;
2745
2746         mutex_lock(&dev_priv->dpll_lock);
2747
2748         val = I915_READ(DPCLKA_CFGCR0_ICL);
2749         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2750
2751         if (intel_port_is_combophy(dev_priv, port)) {
2752                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2753                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2754                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2755                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2756         }
2757
2758         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2759         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2760
2761         mutex_unlock(&dev_priv->dpll_lock);
2762 }
2763
2764 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2765 {
2766         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2767         enum port port = encoder->port;
2768         u32 val;
2769
2770         mutex_lock(&dev_priv->dpll_lock);
2771
2772         val = I915_READ(DPCLKA_CFGCR0_ICL);
2773         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2774         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2775
2776         mutex_unlock(&dev_priv->dpll_lock);
2777 }
2778
2779 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2780 {
2781         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2782         u32 val;
2783         enum port port;
2784         u32 port_mask;
2785         bool ddi_clk_needed;
2786
2787         /*
2788          * In case of DP MST, we sanitize the primary encoder only, not the
2789          * virtual ones.
2790          */
2791         if (encoder->type == INTEL_OUTPUT_DP_MST)
2792                 return;
2793
2794         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2795                 u8 pipe_mask;
2796                 bool is_mst;
2797
2798                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2799                 /*
2800                  * In the unlikely case that BIOS enables DP in MST mode, just
2801                  * warn since our MST HW readout is incomplete.
2802                  */
2803                 if (WARN_ON(is_mst))
2804                         return;
2805         }
2806
2807         port_mask = BIT(encoder->port);
2808         ddi_clk_needed = encoder->base.crtc;
2809
2810         if (encoder->type == INTEL_OUTPUT_DSI) {
2811                 struct intel_encoder *other_encoder;
2812
2813                 port_mask = intel_dsi_encoder_ports(encoder);
2814                 /*
2815                  * Sanity check that we haven't incorrectly registered another
2816                  * encoder using any of the ports of this DSI encoder.
2817                  */
2818                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2819                         if (other_encoder == encoder)
2820                                 continue;
2821
2822                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2823                                 return;
2824                 }
2825                 /*
2826                  * DSI ports should have their DDI clock ungated when disabled
2827                  * and gated when enabled.
2828                  */
2829                 ddi_clk_needed = !encoder->base.crtc;
2830         }
2831
2832         val = I915_READ(DPCLKA_CFGCR0_ICL);
2833         for_each_port_masked(port, port_mask) {
2834                 bool ddi_clk_ungated = !(val &
2835                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2836                                                                    port));
2837
2838                 if (ddi_clk_needed == ddi_clk_ungated)
2839                         continue;
2840
2841                 /*
2842                  * Punt on the case now where clock is gated, but it would
2843                  * be needed by the port. Something else is really broken then.
2844                  */
2845                 if (WARN_ON(ddi_clk_needed))
2846                         continue;
2847
2848                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2849                          port_name(port));
2850                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2851                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2852         }
2853 }
2854
2855 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2856                                  const struct intel_crtc_state *crtc_state)
2857 {
2858         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2859         enum port port = encoder->port;
2860         uint32_t val;
2861         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2862
2863         if (WARN_ON(!pll))
2864                 return;
2865
2866         mutex_lock(&dev_priv->dpll_lock);
2867
2868         if (IS_ICELAKE(dev_priv)) {
2869                 if (!intel_port_is_combophy(dev_priv, port))
2870                         I915_WRITE(DDI_CLK_SEL(port),
2871                                    icl_pll_to_ddi_pll_sel(encoder, crtc_state));
2872         } else if (IS_CANNONLAKE(dev_priv)) {
2873                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2874                 val = I915_READ(DPCLKA_CFGCR0);
2875                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2876                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2877                 I915_WRITE(DPCLKA_CFGCR0, val);
2878
2879                 /*
2880                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2881                  * This step and the step before must be done with separate
2882                  * register writes.
2883                  */
2884                 val = I915_READ(DPCLKA_CFGCR0);
2885                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2886                 I915_WRITE(DPCLKA_CFGCR0, val);
2887         } else if (IS_GEN9_BC(dev_priv)) {
2888                 /* DDI -> PLL mapping  */
2889                 val = I915_READ(DPLL_CTRL2);
2890
2891                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2892                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2893                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2894                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2895
2896                 I915_WRITE(DPLL_CTRL2, val);
2897
2898         } else if (INTEL_GEN(dev_priv) < 9) {
2899                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2900         }
2901
2902         mutex_unlock(&dev_priv->dpll_lock);
2903 }
2904
2905 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2906 {
2907         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2908         enum port port = encoder->port;
2909
2910         if (IS_ICELAKE(dev_priv)) {
2911                 if (!intel_port_is_combophy(dev_priv, port))
2912                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2913         } else if (IS_CANNONLAKE(dev_priv)) {
2914                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2915                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2916         } else if (IS_GEN9_BC(dev_priv)) {
2917                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2918                            DPLL_CTRL2_DDI_CLK_OFF(port));
2919         } else if (INTEL_GEN(dev_priv) < 9) {
2920                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2921         }
2922 }
2923
2924 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2925 {
2926         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2927         enum port port = dig_port->base.port;
2928         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2929         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2930         u32 val;
2931         int i;
2932
2933         if (tc_port == PORT_TC_NONE)
2934                 return;
2935
2936         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2937                 val = I915_READ(mg_regs[i]);
2938                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2939                        MG_DP_MODE_CFG_TRPWR_GATING |
2940                        MG_DP_MODE_CFG_CLNPWR_GATING |
2941                        MG_DP_MODE_CFG_DIGPWR_GATING |
2942                        MG_DP_MODE_CFG_GAONPWR_GATING;
2943                 I915_WRITE(mg_regs[i], val);
2944         }
2945
2946         val = I915_READ(MG_MISC_SUS0(tc_port));
2947         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2948                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2949                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2950                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2951                MG_MISC_SUS0_CFG_TRPWR_GATING |
2952                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2953                MG_MISC_SUS0_CFG_DGPWR_GATING;
2954         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2955 }
2956
2957 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2958 {
2959         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2960         enum port port = dig_port->base.port;
2961         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2962         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2963         u32 val;
2964         int i;
2965
2966         if (tc_port == PORT_TC_NONE)
2967                 return;
2968
2969         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2970                 val = I915_READ(mg_regs[i]);
2971                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2972                          MG_DP_MODE_CFG_TRPWR_GATING |
2973                          MG_DP_MODE_CFG_CLNPWR_GATING |
2974                          MG_DP_MODE_CFG_DIGPWR_GATING |
2975                          MG_DP_MODE_CFG_GAONPWR_GATING);
2976                 I915_WRITE(mg_regs[i], val);
2977         }
2978
2979         val = I915_READ(MG_MISC_SUS0(tc_port));
2980         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2981                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
2982                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
2983                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
2984                  MG_MISC_SUS0_CFG_TRPWR_GATING |
2985                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
2986                  MG_MISC_SUS0_CFG_DGPWR_GATING);
2987         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2988 }
2989
2990 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2991 {
2992         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2993         enum port port = intel_dig_port->base.port;
2994         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2995         u32 ln0, ln1, lane_info;
2996
2997         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2998                 return;
2999
3000         ln0 = I915_READ(MG_DP_MODE(port, 0));
3001         ln1 = I915_READ(MG_DP_MODE(port, 1));
3002
3003         switch (intel_dig_port->tc_type) {
3004         case TC_PORT_TYPEC:
3005                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3006                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3007
3008                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3009                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3010                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3011
3012                 switch (lane_info) {
3013                 case 0x1:
3014                 case 0x4:
3015                         break;
3016                 case 0x2:
3017                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3018                         break;
3019                 case 0x3:
3020                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3021                                MG_DP_MODE_CFG_DP_X2_MODE;
3022                         break;
3023                 case 0x8:
3024                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3025                         break;
3026                 case 0xC:
3027                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3028                                MG_DP_MODE_CFG_DP_X2_MODE;
3029                         break;
3030                 case 0xF:
3031                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3032                                MG_DP_MODE_CFG_DP_X2_MODE;
3033                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3034                                MG_DP_MODE_CFG_DP_X2_MODE;
3035                         break;
3036                 default:
3037                         MISSING_CASE(lane_info);
3038                 }
3039                 break;
3040
3041         case TC_PORT_LEGACY:
3042                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3043                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3044                 break;
3045
3046         default:
3047                 MISSING_CASE(intel_dig_port->tc_type);
3048                 return;
3049         }
3050
3051         I915_WRITE(MG_DP_MODE(port, 0), ln0);
3052         I915_WRITE(MG_DP_MODE(port, 1), ln1);
3053 }
3054
3055 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3056                                         const struct intel_crtc_state *crtc_state)
3057 {
3058         if (!crtc_state->fec_enable)
3059                 return;
3060
3061         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3062                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3063 }
3064
3065 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3066                                  const struct intel_crtc_state *crtc_state)
3067 {
3068         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3069         enum port port = encoder->port;
3070         u32 val;
3071
3072         if (!crtc_state->fec_enable)
3073                 return;
3074
3075         val = I915_READ(DP_TP_CTL(port));
3076         val |= DP_TP_CTL_FEC_ENABLE;
3077         I915_WRITE(DP_TP_CTL(port), val);
3078
3079         if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3080                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3081                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3082                                     1))
3083                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3084 }
3085
3086 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3087                                         const struct intel_crtc_state *crtc_state)
3088 {
3089         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3090         enum port port = encoder->port;
3091         u32 val;
3092
3093         if (!crtc_state->fec_enable)
3094                 return;
3095
3096         val = I915_READ(DP_TP_CTL(port));
3097         val &= ~DP_TP_CTL_FEC_ENABLE;
3098         I915_WRITE(DP_TP_CTL(port), val);
3099         POSTING_READ(DP_TP_CTL(port));
3100 }
3101
3102 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3103                                     const struct intel_crtc_state *crtc_state,
3104                                     const struct drm_connector_state *conn_state)
3105 {
3106         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3107         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3108         enum port port = encoder->port;
3109         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3110         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3111         int level = intel_ddi_dp_level(intel_dp);
3112
3113         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3114
3115         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3116                                  crtc_state->lane_count, is_mst);
3117
3118         intel_edp_panel_on(intel_dp);
3119
3120         intel_ddi_clk_select(encoder, crtc_state);
3121
3122         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3123
3124         icl_program_mg_dp_mode(dig_port);
3125         icl_disable_phy_clock_gating(dig_port);
3126
3127         if (IS_ICELAKE(dev_priv))
3128                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3129                                         level, encoder->type);
3130         else if (IS_CANNONLAKE(dev_priv))
3131                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3132         else if (IS_GEN9_LP(dev_priv))
3133                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3134         else
3135                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3136
3137         intel_ddi_init_dp_buf_reg(encoder);
3138         if (!is_mst)
3139                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3140         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3141                                               true);
3142         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3143         intel_dp_start_link_train(intel_dp);
3144         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3145                 intel_dp_stop_link_train(intel_dp);
3146
3147         intel_ddi_enable_fec(encoder, crtc_state);
3148
3149         icl_enable_phy_clock_gating(dig_port);
3150
3151         if (!is_mst)
3152                 intel_ddi_enable_pipe_clock(crtc_state);
3153
3154         intel_dsc_enable(encoder, crtc_state);
3155 }
3156
3157 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3158                                       const struct intel_crtc_state *crtc_state,
3159                                       const struct drm_connector_state *conn_state)
3160 {
3161         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3162         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3163         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3164         enum port port = encoder->port;
3165         int level = intel_ddi_hdmi_level(dev_priv, port);
3166         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3167
3168         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3169         intel_ddi_clk_select(encoder, crtc_state);
3170
3171         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3172
3173         icl_program_mg_dp_mode(dig_port);
3174         icl_disable_phy_clock_gating(dig_port);
3175
3176         if (IS_ICELAKE(dev_priv))
3177                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3178                                         level, INTEL_OUTPUT_HDMI);
3179         else if (IS_CANNONLAKE(dev_priv))
3180                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3181         else if (IS_GEN9_LP(dev_priv))
3182                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3183         else
3184                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3185
3186         icl_enable_phy_clock_gating(dig_port);
3187
3188         if (IS_GEN9_BC(dev_priv))
3189                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3190
3191         intel_ddi_enable_pipe_clock(crtc_state);
3192
3193         intel_dig_port->set_infoframes(encoder,
3194                                        crtc_state->has_infoframe,
3195                                        crtc_state, conn_state);
3196 }
3197
3198 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3199                                  const struct intel_crtc_state *crtc_state,
3200                                  const struct drm_connector_state *conn_state)
3201 {
3202         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3204         enum pipe pipe = crtc->pipe;
3205
3206         /*
3207          * When called from DP MST code:
3208          * - conn_state will be NULL
3209          * - encoder will be the main encoder (ie. mst->primary)
3210          * - the main connector associated with this port
3211          *   won't be active or linked to a crtc
3212          * - crtc_state will be the state of the first stream to
3213          *   be activated on this port, and it may not be the same
3214          *   stream that will be deactivated last, but each stream
3215          *   should have a state that is identical when it comes to
3216          *   the DP link parameteres
3217          */
3218
3219         WARN_ON(crtc_state->has_pch_encoder);
3220
3221         if (INTEL_GEN(dev_priv) >= 11)
3222                 icl_map_plls_to_ports(encoder, crtc_state);
3223
3224         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3225
3226         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3227                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3228         } else {
3229                 struct intel_lspcon *lspcon =
3230                                 enc_to_intel_lspcon(&encoder->base);
3231
3232                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3233                 if (lspcon->active) {
3234                         struct intel_digital_port *dig_port =
3235                                         enc_to_dig_port(&encoder->base);
3236
3237                         dig_port->set_infoframes(encoder,
3238                                                  crtc_state->has_infoframe,
3239                                                  crtc_state, conn_state);
3240                 }
3241         }
3242 }
3243
3244 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3245                                   const struct intel_crtc_state *crtc_state)
3246 {
3247         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3248         enum port port = encoder->port;
3249         bool wait = false;
3250         u32 val;
3251
3252         val = I915_READ(DDI_BUF_CTL(port));
3253         if (val & DDI_BUF_CTL_ENABLE) {
3254                 val &= ~DDI_BUF_CTL_ENABLE;
3255                 I915_WRITE(DDI_BUF_CTL(port), val);
3256                 wait = true;
3257         }
3258
3259         val = I915_READ(DP_TP_CTL(port));
3260         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3261         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3262         I915_WRITE(DP_TP_CTL(port), val);
3263
3264         /* Disable FEC in DP Sink */
3265         intel_ddi_disable_fec_state(encoder, crtc_state);
3266
3267         if (wait)
3268                 intel_wait_ddi_buf_idle(dev_priv, port);
3269 }
3270
3271 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3272                                       const struct intel_crtc_state *old_crtc_state,
3273                                       const struct drm_connector_state *old_conn_state)
3274 {
3275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3276         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3277         struct intel_dp *intel_dp = &dig_port->dp;
3278         bool is_mst = intel_crtc_has_type(old_crtc_state,
3279                                           INTEL_OUTPUT_DP_MST);
3280
3281         if (!is_mst) {
3282                 intel_ddi_disable_pipe_clock(old_crtc_state);
3283                 /*
3284                  * Power down sink before disabling the port, otherwise we end
3285                  * up getting interrupts from the sink on detecting link loss.
3286                  */
3287                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3288         }
3289
3290         intel_disable_ddi_buf(encoder, old_crtc_state);
3291
3292         intel_edp_panel_vdd_on(intel_dp);
3293         intel_edp_panel_off(intel_dp);
3294
3295         intel_display_power_put_unchecked(dev_priv,
3296                                           dig_port->ddi_io_power_domain);
3297
3298         intel_ddi_clk_disable(encoder);
3299 }
3300
3301 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3302                                         const struct intel_crtc_state *old_crtc_state,
3303                                         const struct drm_connector_state *old_conn_state)
3304 {
3305         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3306         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3307         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3308
3309         dig_port->set_infoframes(encoder, false,
3310                                  old_crtc_state, old_conn_state);
3311
3312         intel_ddi_disable_pipe_clock(old_crtc_state);
3313
3314         intel_disable_ddi_buf(encoder, old_crtc_state);
3315
3316         intel_display_power_put_unchecked(dev_priv,
3317                                           dig_port->ddi_io_power_domain);
3318
3319         intel_ddi_clk_disable(encoder);
3320
3321         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3322 }
3323
3324 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3325                                    const struct intel_crtc_state *old_crtc_state,
3326                                    const struct drm_connector_state *old_conn_state)
3327 {
3328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3329
3330         /*
3331          * When called from DP MST code:
3332          * - old_conn_state will be NULL
3333          * - encoder will be the main encoder (ie. mst->primary)
3334          * - the main connector associated with this port
3335          *   won't be active or linked to a crtc
3336          * - old_crtc_state will be the state of the last stream to
3337          *   be deactivated on this port, and it may not be the same
3338          *   stream that was activated last, but each stream
3339          *   should have a state that is identical when it comes to
3340          *   the DP link parameteres
3341          */
3342
3343         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3344                 intel_ddi_post_disable_hdmi(encoder,
3345                                             old_crtc_state, old_conn_state);
3346         else
3347                 intel_ddi_post_disable_dp(encoder,
3348                                           old_crtc_state, old_conn_state);
3349
3350         if (INTEL_GEN(dev_priv) >= 11)
3351                 icl_unmap_plls_to_ports(encoder);
3352 }
3353
3354 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3355                                 const struct intel_crtc_state *old_crtc_state,
3356                                 const struct drm_connector_state *old_conn_state)
3357 {
3358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3359         uint32_t val;
3360
3361         /*
3362          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3363          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3364          * step 13 is the correct place for it. Step 18 is where it was
3365          * originally before the BUN.
3366          */
3367         val = I915_READ(FDI_RX_CTL(PIPE_A));
3368         val &= ~FDI_RX_ENABLE;
3369         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3370
3371         intel_disable_ddi_buf(encoder, old_crtc_state);
3372         intel_ddi_clk_disable(encoder);
3373
3374         val = I915_READ(FDI_RX_MISC(PIPE_A));
3375         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3376         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3377         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3378
3379         val = I915_READ(FDI_RX_CTL(PIPE_A));
3380         val &= ~FDI_PCDCLK;
3381         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3382
3383         val = I915_READ(FDI_RX_CTL(PIPE_A));
3384         val &= ~FDI_RX_PLL_ENABLE;
3385         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3386 }
3387
3388 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3389                                 const struct intel_crtc_state *crtc_state,
3390                                 const struct drm_connector_state *conn_state)
3391 {
3392         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3393         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3394         enum port port = encoder->port;
3395
3396         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3397                 intel_dp_stop_link_train(intel_dp);
3398
3399         intel_edp_backlight_on(crtc_state, conn_state);
3400         intel_psr_enable(intel_dp, crtc_state);
3401         intel_edp_drrs_enable(intel_dp, crtc_state);
3402
3403         if (crtc_state->has_audio)
3404                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3405 }
3406
3407 static i915_reg_t
3408 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3409                                enum port port)
3410 {
3411         static const i915_reg_t regs[] = {
3412                 [PORT_A] = CHICKEN_TRANS_EDP,
3413                 [PORT_B] = CHICKEN_TRANS_A,
3414                 [PORT_C] = CHICKEN_TRANS_B,
3415                 [PORT_D] = CHICKEN_TRANS_C,
3416                 [PORT_E] = CHICKEN_TRANS_A,
3417         };
3418
3419         WARN_ON(INTEL_GEN(dev_priv) < 9);
3420
3421         if (WARN_ON(port < PORT_A || port > PORT_E))
3422                 port = PORT_A;
3423
3424         return regs[port];
3425 }
3426
3427 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3428                                   const struct intel_crtc_state *crtc_state,
3429                                   const struct drm_connector_state *conn_state)
3430 {
3431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3432         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3433         struct drm_connector *connector = conn_state->connector;
3434         enum port port = encoder->port;
3435
3436         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3437                                                crtc_state->hdmi_high_tmds_clock_ratio,
3438                                                crtc_state->hdmi_scrambling))
3439                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3440                           connector->base.id, connector->name);
3441
3442         /* Display WA #1143: skl,kbl,cfl */
3443         if (IS_GEN9_BC(dev_priv)) {
3444                 /*
3445                  * For some reason these chicken bits have been
3446                  * stuffed into a transcoder register, event though
3447                  * the bits affect a specific DDI port rather than
3448                  * a specific transcoder.
3449                  */
3450                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3451                 u32 val;
3452
3453                 val = I915_READ(reg);
3454
3455                 if (port == PORT_E)
3456                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3457                                 DDIE_TRAINING_OVERRIDE_VALUE;
3458                 else
3459                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3460                                 DDI_TRAINING_OVERRIDE_VALUE;
3461
3462                 I915_WRITE(reg, val);
3463                 POSTING_READ(reg);
3464
3465                 udelay(1);
3466
3467                 if (port == PORT_E)
3468                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3469                                  DDIE_TRAINING_OVERRIDE_VALUE);
3470                 else
3471                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3472                                  DDI_TRAINING_OVERRIDE_VALUE);
3473
3474                 I915_WRITE(reg, val);
3475         }
3476
3477         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3478          * are ignored so nothing special needs to be done besides
3479          * enabling the port.
3480          */
3481         I915_WRITE(DDI_BUF_CTL(port),
3482                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3483
3484         if (crtc_state->has_audio)
3485                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3486 }
3487
3488 static void intel_enable_ddi(struct intel_encoder *encoder,
3489                              const struct intel_crtc_state *crtc_state,
3490                              const struct drm_connector_state *conn_state)
3491 {
3492         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3493                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3494         else
3495                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3496
3497         /* Enable hdcp if it's desired */
3498         if (conn_state->content_protection ==
3499             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3500                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3501 }
3502
3503 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3504                                  const struct intel_crtc_state *old_crtc_state,
3505                                  const struct drm_connector_state *old_conn_state)
3506 {
3507         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3508
3509         intel_dp->link_trained = false;
3510
3511         if (old_crtc_state->has_audio)
3512                 intel_audio_codec_disable(encoder,
3513                                           old_crtc_state, old_conn_state);
3514
3515         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3516         intel_psr_disable(intel_dp, old_crtc_state);
3517         intel_edp_backlight_off(old_conn_state);
3518         /* Disable the decompression in DP Sink */
3519         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3520                                               false);
3521 }
3522
3523 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3524                                    const struct intel_crtc_state *old_crtc_state,
3525                                    const struct drm_connector_state *old_conn_state)
3526 {
3527         struct drm_connector *connector = old_conn_state->connector;
3528
3529         if (old_crtc_state->has_audio)
3530                 intel_audio_codec_disable(encoder,
3531                                           old_crtc_state, old_conn_state);
3532
3533         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3534                                                false, false))
3535                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3536                               connector->base.id, connector->name);
3537 }
3538
3539 static void intel_disable_ddi(struct intel_encoder *encoder,
3540                               const struct intel_crtc_state *old_crtc_state,
3541                               const struct drm_connector_state *old_conn_state)
3542 {
3543         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3544
3545         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3546                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3547         else
3548                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3549 }
3550
3551 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3552                                      const struct intel_crtc_state *crtc_state,
3553                                      const struct drm_connector_state *conn_state)
3554 {
3555         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3556
3557         intel_psr_enable(intel_dp, crtc_state);
3558         intel_edp_drrs_enable(intel_dp, crtc_state);
3559 }
3560
3561 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3562                                   const struct intel_crtc_state *crtc_state,
3563                                   const struct drm_connector_state *conn_state)
3564 {
3565         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3566                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3567 }
3568
3569 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3570                                          const struct intel_crtc_state *pipe_config,
3571                                          enum port port)
3572 {
3573         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3574         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3575         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3576         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3577         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3578
3579         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3580         switch (pipe_config->lane_count) {
3581         case 1:
3582                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3583                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3584                 break;
3585         case 2:
3586                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3587                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3588                 break;
3589         case 4:
3590                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3591                 break;
3592         default:
3593                 MISSING_CASE(pipe_config->lane_count);
3594         }
3595         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3596 }
3597
3598 static void
3599 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3600                          const struct intel_crtc_state *crtc_state,
3601                          const struct drm_connector_state *conn_state)
3602 {
3603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3604         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3605         enum port port = encoder->port;
3606
3607         if (intel_crtc_has_dp_encoder(crtc_state) ||
3608             intel_port_is_tc(dev_priv, encoder->port))
3609                 intel_display_power_get(dev_priv,
3610                                         intel_ddi_main_link_aux_domain(dig_port));
3611
3612         if (IS_GEN9_LP(dev_priv))
3613                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3614                                                 crtc_state->lane_lat_optim_mask);
3615
3616         /*
3617          * Program the lane count for static/dynamic connections on Type-C ports.
3618          * Skip this step for TBT.
3619          */
3620         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3621             dig_port->tc_type == TC_PORT_TBT)
3622                 return;
3623
3624         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3625 }
3626
3627 static void
3628 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3629                            const struct intel_crtc_state *crtc_state,
3630                            const struct drm_connector_state *conn_state)
3631 {
3632         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3633         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3634
3635         if (intel_crtc_has_dp_encoder(crtc_state) ||
3636             intel_port_is_tc(dev_priv, encoder->port))
3637                 intel_display_power_put_unchecked(dev_priv,
3638                                                   intel_ddi_main_link_aux_domain(dig_port));
3639 }
3640
3641 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3642 {
3643         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3644         struct drm_i915_private *dev_priv =
3645                 to_i915(intel_dig_port->base.base.dev);
3646         enum port port = intel_dig_port->base.port;
3647         uint32_t val;
3648         bool wait = false;
3649
3650         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3651                 val = I915_READ(DDI_BUF_CTL(port));
3652                 if (val & DDI_BUF_CTL_ENABLE) {
3653                         val &= ~DDI_BUF_CTL_ENABLE;
3654                         I915_WRITE(DDI_BUF_CTL(port), val);
3655                         wait = true;
3656                 }
3657
3658                 val = I915_READ(DP_TP_CTL(port));
3659                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3660                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3661                 I915_WRITE(DP_TP_CTL(port), val);
3662                 POSTING_READ(DP_TP_CTL(port));
3663
3664                 if (wait)
3665                         intel_wait_ddi_buf_idle(dev_priv, port);
3666         }
3667
3668         val = DP_TP_CTL_ENABLE |
3669               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3670         if (intel_dp->link_mst)
3671                 val |= DP_TP_CTL_MODE_MST;
3672         else {
3673                 val |= DP_TP_CTL_MODE_SST;
3674                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3675                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3676         }
3677         I915_WRITE(DP_TP_CTL(port), val);
3678         POSTING_READ(DP_TP_CTL(port));
3679
3680         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3681         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3682         POSTING_READ(DDI_BUF_CTL(port));
3683
3684         udelay(600);
3685 }
3686
3687 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3688                                        enum transcoder cpu_transcoder)
3689 {
3690         if (cpu_transcoder == TRANSCODER_EDP)
3691                 return false;
3692
3693         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3694                 return false;
3695
3696         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3697                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3698 }
3699
3700 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3701                                          struct intel_crtc_state *crtc_state)
3702 {
3703         if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3704                 crtc_state->min_voltage_level = 1;
3705         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3706                 crtc_state->min_voltage_level = 2;
3707 }
3708
3709 void intel_ddi_get_config(struct intel_encoder *encoder,
3710                           struct intel_crtc_state *pipe_config)
3711 {
3712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3713         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3714         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3715         struct intel_digital_port *intel_dig_port;
3716         u32 temp, flags = 0;
3717
3718         /* XXX: DSI transcoder paranoia */
3719         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3720                 return;
3721
3722         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3723         if (temp & TRANS_DDI_PHSYNC)
3724                 flags |= DRM_MODE_FLAG_PHSYNC;
3725         else
3726                 flags |= DRM_MODE_FLAG_NHSYNC;
3727         if (temp & TRANS_DDI_PVSYNC)
3728                 flags |= DRM_MODE_FLAG_PVSYNC;
3729         else
3730                 flags |= DRM_MODE_FLAG_NVSYNC;
3731
3732         pipe_config->base.adjusted_mode.flags |= flags;
3733
3734         switch (temp & TRANS_DDI_BPC_MASK) {
3735         case TRANS_DDI_BPC_6:
3736                 pipe_config->pipe_bpp = 18;
3737                 break;
3738         case TRANS_DDI_BPC_8:
3739                 pipe_config->pipe_bpp = 24;
3740                 break;
3741         case TRANS_DDI_BPC_10:
3742                 pipe_config->pipe_bpp = 30;
3743                 break;
3744         case TRANS_DDI_BPC_12:
3745                 pipe_config->pipe_bpp = 36;
3746                 break;
3747         default:
3748                 break;
3749         }
3750
3751         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3752         case TRANS_DDI_MODE_SELECT_HDMI:
3753                 pipe_config->has_hdmi_sink = true;
3754                 intel_dig_port = enc_to_dig_port(&encoder->base);
3755
3756                 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3757                         pipe_config->has_infoframe = true;
3758
3759                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3760                         pipe_config->hdmi_scrambling = true;
3761                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3762                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3763                 /* fall through */
3764         case TRANS_DDI_MODE_SELECT_DVI:
3765                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3766                 pipe_config->lane_count = 4;
3767                 break;
3768         case TRANS_DDI_MODE_SELECT_FDI:
3769                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3770                 break;
3771         case TRANS_DDI_MODE_SELECT_DP_SST:
3772                 if (encoder->type == INTEL_OUTPUT_EDP)
3773                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3774                 else
3775                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3776                 pipe_config->lane_count =
3777                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3778                 intel_dp_get_m_n(intel_crtc, pipe_config);
3779                 break;
3780         case TRANS_DDI_MODE_SELECT_DP_MST:
3781                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3782                 pipe_config->lane_count =
3783                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3784                 intel_dp_get_m_n(intel_crtc, pipe_config);
3785                 break;
3786         default:
3787                 break;
3788         }
3789
3790         pipe_config->has_audio =
3791                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3792
3793         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3794             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3795                 /*
3796                  * This is a big fat ugly hack.
3797                  *
3798                  * Some machines in UEFI boot mode provide us a VBT that has 18
3799                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3800                  * unknown we fail to light up. Yet the same BIOS boots up with
3801                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3802                  * max, not what it tells us to use.
3803                  *
3804                  * Note: This will still be broken if the eDP panel is not lit
3805                  * up by the BIOS, and thus we can't get the mode at module
3806                  * load.
3807                  */
3808                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3809                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3810                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3811         }
3812
3813         intel_ddi_clock_get(encoder, pipe_config);
3814
3815         if (IS_GEN9_LP(dev_priv))
3816                 pipe_config->lane_lat_optim_mask =
3817                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3818
3819         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3820 }
3821
3822 static enum intel_output_type
3823 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3824                               struct intel_crtc_state *crtc_state,
3825                               struct drm_connector_state *conn_state)
3826 {
3827         switch (conn_state->connector->connector_type) {
3828         case DRM_MODE_CONNECTOR_HDMIA:
3829                 return INTEL_OUTPUT_HDMI;
3830         case DRM_MODE_CONNECTOR_eDP:
3831                 return INTEL_OUTPUT_EDP;
3832         case DRM_MODE_CONNECTOR_DisplayPort:
3833                 return INTEL_OUTPUT_DP;
3834         default:
3835                 MISSING_CASE(conn_state->connector->connector_type);
3836                 return INTEL_OUTPUT_UNUSED;
3837         }
3838 }
3839
3840 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3841                                     struct intel_crtc_state *pipe_config,
3842                                     struct drm_connector_state *conn_state)
3843 {
3844         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3845         enum port port = encoder->port;
3846         int ret;
3847
3848         if (port == PORT_A)
3849                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3850
3851         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3852                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3853         else
3854                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3855
3856         if (IS_GEN9_LP(dev_priv) && ret)
3857                 pipe_config->lane_lat_optim_mask =
3858                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3859
3860         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3861
3862         return ret;
3863
3864 }
3865
3866 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3867 {
3868         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3869         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3870
3871         intel_dp_encoder_suspend(encoder);
3872
3873         /*
3874          * TODO: disconnect also from USB DP alternate mode once we have a
3875          * way to handle the modeset restore in that mode during resume
3876          * even if the sink has disappeared while being suspended.
3877          */
3878         if (dig_port->tc_legacy_port)
3879                 icl_tc_phy_disconnect(i915, dig_port);
3880 }
3881
3882 static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3883 {
3884         struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3885         struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3886
3887         if (intel_port_is_tc(i915, dig_port->base.port))
3888                 intel_digital_port_connected(&dig_port->base);
3889
3890         intel_dp_encoder_reset(drm_encoder);
3891 }
3892
3893 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3894 {
3895         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3896         struct drm_i915_private *i915 = to_i915(encoder->dev);
3897
3898         intel_dp_encoder_flush_work(encoder);
3899
3900         if (intel_port_is_tc(i915, dig_port->base.port))
3901                 icl_tc_phy_disconnect(i915, dig_port);
3902
3903         drm_encoder_cleanup(encoder);
3904         kfree(dig_port);
3905 }
3906
3907 static const struct drm_encoder_funcs intel_ddi_funcs = {
3908         .reset = intel_ddi_encoder_reset,
3909         .destroy = intel_ddi_encoder_destroy,
3910 };
3911
3912 static struct intel_connector *
3913 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3914 {
3915         struct intel_connector *connector;
3916         enum port port = intel_dig_port->base.port;
3917
3918         connector = intel_connector_alloc();
3919         if (!connector)
3920                 return NULL;
3921
3922         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3923         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3924                 kfree(connector);
3925                 return NULL;
3926         }
3927
3928         return connector;
3929 }
3930
3931 static int modeset_pipe(struct drm_crtc *crtc,
3932                         struct drm_modeset_acquire_ctx *ctx)
3933 {
3934         struct drm_atomic_state *state;
3935         struct drm_crtc_state *crtc_state;
3936         int ret;
3937
3938         state = drm_atomic_state_alloc(crtc->dev);
3939         if (!state)
3940                 return -ENOMEM;
3941
3942         state->acquire_ctx = ctx;
3943
3944         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3945         if (IS_ERR(crtc_state)) {
3946                 ret = PTR_ERR(crtc_state);
3947                 goto out;
3948         }
3949
3950         crtc_state->mode_changed = true;
3951
3952         ret = drm_atomic_add_affected_connectors(state, crtc);
3953         if (ret)
3954                 goto out;
3955
3956         ret = drm_atomic_add_affected_planes(state, crtc);
3957         if (ret)
3958                 goto out;
3959
3960         ret = drm_atomic_commit(state);
3961         if (ret)
3962                 goto out;
3963
3964         return 0;
3965
3966  out:
3967         drm_atomic_state_put(state);
3968
3969         return ret;
3970 }
3971
3972 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3973                                  struct drm_modeset_acquire_ctx *ctx)
3974 {
3975         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3976         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3977         struct intel_connector *connector = hdmi->attached_connector;
3978         struct i2c_adapter *adapter =
3979                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3980         struct drm_connector_state *conn_state;
3981         struct intel_crtc_state *crtc_state;
3982         struct intel_crtc *crtc;
3983         u8 config;
3984         int ret;
3985
3986         if (!connector || connector->base.status != connector_status_connected)
3987                 return 0;
3988
3989         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3990                                ctx);
3991         if (ret)
3992                 return ret;
3993
3994         conn_state = connector->base.state;
3995
3996         crtc = to_intel_crtc(conn_state->crtc);
3997         if (!crtc)
3998                 return 0;
3999
4000         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4001         if (ret)
4002                 return ret;
4003
4004         crtc_state = to_intel_crtc_state(crtc->base.state);
4005
4006         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4007
4008         if (!crtc_state->base.active)
4009                 return 0;
4010
4011         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4012             !crtc_state->hdmi_scrambling)
4013                 return 0;
4014
4015         if (conn_state->commit &&
4016             !try_wait_for_completion(&conn_state->commit->hw_done))
4017                 return 0;
4018
4019         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4020         if (ret < 0) {
4021                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4022                 return 0;
4023         }
4024
4025         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4026             crtc_state->hdmi_high_tmds_clock_ratio &&
4027             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4028             crtc_state->hdmi_scrambling)
4029                 return 0;
4030
4031         /*
4032          * HDMI 2.0 says that one should not send scrambled data
4033          * prior to configuring the sink scrambling, and that
4034          * TMDS clock/data transmission should be suspended when
4035          * changing the TMDS clock rate in the sink. So let's
4036          * just do a full modeset here, even though some sinks
4037          * would be perfectly happy if were to just reconfigure
4038          * the SCDC settings on the fly.
4039          */
4040         return modeset_pipe(&crtc->base, ctx);
4041 }
4042
4043 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4044                               struct intel_connector *connector)
4045 {
4046         struct drm_modeset_acquire_ctx ctx;
4047         bool changed;
4048         int ret;
4049
4050         changed = intel_encoder_hotplug(encoder, connector);
4051
4052         drm_modeset_acquire_init(&ctx, 0);
4053
4054         for (;;) {
4055                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4056                         ret = intel_hdmi_reset_link(encoder, &ctx);
4057                 else
4058                         ret = intel_dp_retrain_link(encoder, &ctx);
4059
4060                 if (ret == -EDEADLK) {
4061                         drm_modeset_backoff(&ctx);
4062                         continue;
4063                 }
4064
4065                 break;
4066         }
4067
4068         drm_modeset_drop_locks(&ctx);
4069         drm_modeset_acquire_fini(&ctx);
4070         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4071
4072         return changed;
4073 }
4074
4075 static struct intel_connector *
4076 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4077 {
4078         struct intel_connector *connector;
4079         enum port port = intel_dig_port->base.port;
4080
4081         connector = intel_connector_alloc();
4082         if (!connector)
4083                 return NULL;
4084
4085         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4086         intel_hdmi_init_connector(intel_dig_port, connector);
4087
4088         return connector;
4089 }
4090
4091 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4092 {
4093         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4094
4095         if (dport->base.port != PORT_A)
4096                 return false;
4097
4098         if (dport->saved_port_bits & DDI_A_4_LANES)
4099                 return false;
4100
4101         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4102          *                     supported configuration
4103          */
4104         if (IS_GEN9_LP(dev_priv))
4105                 return true;
4106
4107         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4108          *             one who does also have a full A/E split called
4109          *             DDI_F what makes DDI_E useless. However for this
4110          *             case let's trust VBT info.
4111          */
4112         if (IS_CANNONLAKE(dev_priv) &&
4113             !intel_bios_is_port_present(dev_priv, PORT_E))
4114                 return true;
4115
4116         return false;
4117 }
4118
4119 static int
4120 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4121 {
4122         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4123         enum port port = intel_dport->base.port;
4124         int max_lanes = 4;
4125
4126         if (INTEL_GEN(dev_priv) >= 11)
4127                 return max_lanes;
4128
4129         if (port == PORT_A || port == PORT_E) {
4130                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4131                         max_lanes = port == PORT_A ? 4 : 0;
4132                 else
4133                         /* Both A and E share 2 lanes */
4134                         max_lanes = 2;
4135         }
4136
4137         /*
4138          * Some BIOS might fail to set this bit on port A if eDP
4139          * wasn't lit up at boot.  Force this bit set when needed
4140          * so we use the proper lane count for our calculations.
4141          */
4142         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4143                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4144                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4145                 max_lanes = 4;
4146         }
4147
4148         return max_lanes;
4149 }
4150
4151 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4152 {
4153         struct ddi_vbt_port_info *port_info =
4154                 &dev_priv->vbt.ddi_port_info[port];
4155         struct intel_digital_port *intel_dig_port;
4156         struct intel_encoder *intel_encoder;
4157         struct drm_encoder *encoder;
4158         bool init_hdmi, init_dp, init_lspcon = false;
4159         enum pipe pipe;
4160
4161         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4162         init_dp = port_info->supports_dp;
4163
4164         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4165                 /*
4166                  * Lspcon device needs to be driven with DP connector
4167                  * with special detection sequence. So make sure DP
4168                  * is initialized before lspcon.
4169                  */
4170                 init_dp = true;
4171                 init_lspcon = true;
4172                 init_hdmi = false;
4173                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4174         }
4175
4176         if (!init_dp && !init_hdmi) {
4177                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4178                               port_name(port));
4179                 return;
4180         }
4181
4182         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4183         if (!intel_dig_port)
4184                 return;
4185
4186         intel_encoder = &intel_dig_port->base;
4187         encoder = &intel_encoder->base;
4188
4189         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4190                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4191
4192         intel_encoder->hotplug = intel_ddi_hotplug;
4193         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4194         intel_encoder->compute_config = intel_ddi_compute_config;
4195         intel_encoder->enable = intel_enable_ddi;
4196         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4197         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4198         intel_encoder->pre_enable = intel_ddi_pre_enable;
4199         intel_encoder->disable = intel_disable_ddi;
4200         intel_encoder->post_disable = intel_ddi_post_disable;
4201         intel_encoder->update_pipe = intel_ddi_update_pipe;
4202         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4203         intel_encoder->get_config = intel_ddi_get_config;
4204         intel_encoder->suspend = intel_ddi_encoder_suspend;
4205         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4206         intel_encoder->type = INTEL_OUTPUT_DDI;
4207         intel_encoder->power_domain = intel_port_to_power_domain(port);
4208         intel_encoder->port = port;
4209         intel_encoder->cloneable = 0;
4210         for_each_pipe(dev_priv, pipe)
4211                 intel_encoder->crtc_mask |= BIT(pipe);
4212
4213         if (INTEL_GEN(dev_priv) >= 11)
4214                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4215                         DDI_BUF_PORT_REVERSAL;
4216         else
4217                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4218                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4219         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4220         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4221         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4222
4223         intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
4224                                          !port_info->supports_typec_usb &&
4225                                          !port_info->supports_tbt;
4226
4227         switch (port) {
4228         case PORT_A:
4229                 intel_dig_port->ddi_io_power_domain =
4230                         POWER_DOMAIN_PORT_DDI_A_IO;
4231                 break;
4232         case PORT_B:
4233                 intel_dig_port->ddi_io_power_domain =
4234                         POWER_DOMAIN_PORT_DDI_B_IO;
4235                 break;
4236         case PORT_C:
4237                 intel_dig_port->ddi_io_power_domain =
4238                         POWER_DOMAIN_PORT_DDI_C_IO;
4239                 break;
4240         case PORT_D:
4241                 intel_dig_port->ddi_io_power_domain =
4242                         POWER_DOMAIN_PORT_DDI_D_IO;
4243                 break;
4244         case PORT_E:
4245                 intel_dig_port->ddi_io_power_domain =
4246                         POWER_DOMAIN_PORT_DDI_E_IO;
4247                 break;
4248         case PORT_F:
4249                 intel_dig_port->ddi_io_power_domain =
4250                         POWER_DOMAIN_PORT_DDI_F_IO;
4251                 break;
4252         default:
4253                 MISSING_CASE(port);
4254         }
4255
4256         if (init_dp) {
4257                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4258                         goto err;
4259
4260                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4261         }
4262
4263         /* In theory we don't need the encoder->type check, but leave it just in
4264          * case we have some really bad VBTs... */
4265         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4266                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4267                         goto err;
4268         }
4269
4270         if (init_lspcon) {
4271                 if (lspcon_init(intel_dig_port))
4272                         /* TODO: handle hdmi info frame part */
4273                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4274                                 port_name(port));
4275                 else
4276                         /*
4277                          * LSPCON init faied, but DP init was success, so
4278                          * lets try to drive as DP++ port.
4279                          */
4280                         DRM_ERROR("LSPCON init failed on port %c\n",
4281                                 port_name(port));
4282         }
4283
4284         intel_infoframe_init(intel_dig_port);
4285
4286         if (intel_port_is_tc(dev_priv, port))
4287                 intel_digital_port_connected(intel_encoder);
4288
4289         return;
4290
4291 err:
4292         drm_encoder_cleanup(encoder);
4293         kfree(intel_dig_port);
4294 }