2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <drm/drm_scdc_helper.h>
30 #include "intel_drv.h"
31 #include "intel_dsi.h"
33 struct ddi_buf_trans {
34 u32 trans1; /* balance leg enable, de-emph level */
35 u32 trans2; /* vref sel, vswing */
36 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
39 static const u8 index_to_dp_signal_levels[] = {
40 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
41 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
42 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
43 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
44 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
45 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
46 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
47 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
49 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
53 * them for both DP and FDI transports, allowing those ports to
54 * automatically adapt to HDMI connections as well
56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
57 { 0x00FFFFFF, 0x0006000E, 0x0 },
58 { 0x00D75FFF, 0x0005000A, 0x0 },
59 { 0x00C30FFF, 0x00040006, 0x0 },
60 { 0x80AAAFFF, 0x000B0000, 0x0 },
61 { 0x00FFFFFF, 0x0005000A, 0x0 },
62 { 0x00D75FFF, 0x000C0004, 0x0 },
63 { 0x80C30FFF, 0x000B0000, 0x0 },
64 { 0x00FFFFFF, 0x00040006, 0x0 },
65 { 0x80D75FFF, 0x000B0000, 0x0 },
68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
69 { 0x00FFFFFF, 0x0007000E, 0x0 },
70 { 0x00D75FFF, 0x000F000A, 0x0 },
71 { 0x00C30FFF, 0x00060006, 0x0 },
72 { 0x00AAAFFF, 0x001E0000, 0x0 },
73 { 0x00FFFFFF, 0x000F000A, 0x0 },
74 { 0x00D75FFF, 0x00160004, 0x0 },
75 { 0x00C30FFF, 0x001E0000, 0x0 },
76 { 0x00FFFFFF, 0x00060006, 0x0 },
77 { 0x00D75FFF, 0x001E0000, 0x0 },
80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
81 /* Idx NT mV d T mV d db */
82 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
83 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
84 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
85 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
86 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
87 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
88 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
89 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
90 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
91 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
92 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
93 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
97 { 0x00FFFFFF, 0x00000012, 0x0 },
98 { 0x00EBAFFF, 0x00020011, 0x0 },
99 { 0x00C71FFF, 0x0006000F, 0x0 },
100 { 0x00AAAFFF, 0x000E000A, 0x0 },
101 { 0x00FFFFFF, 0x00020011, 0x0 },
102 { 0x00DB6FFF, 0x0005000F, 0x0 },
103 { 0x00BEEFFF, 0x000A000C, 0x0 },
104 { 0x00FFFFFF, 0x0005000F, 0x0 },
105 { 0x00DB6FFF, 0x000A000C, 0x0 },
108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
109 { 0x00FFFFFF, 0x0007000E, 0x0 },
110 { 0x00D75FFF, 0x000E000A, 0x0 },
111 { 0x00BEFFFF, 0x00140006, 0x0 },
112 { 0x80B2CFFF, 0x001B0002, 0x0 },
113 { 0x00FFFFFF, 0x000E000A, 0x0 },
114 { 0x00DB6FFF, 0x00160005, 0x0 },
115 { 0x80C71FFF, 0x001A0002, 0x0 },
116 { 0x00F7DFFF, 0x00180004, 0x0 },
117 { 0x80D75FFF, 0x001B0002, 0x0 },
120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
121 { 0x00FFFFFF, 0x0001000E, 0x0 },
122 { 0x00D75FFF, 0x0004000A, 0x0 },
123 { 0x00C30FFF, 0x00070006, 0x0 },
124 { 0x00AAAFFF, 0x000C0000, 0x0 },
125 { 0x00FFFFFF, 0x0004000A, 0x0 },
126 { 0x00D75FFF, 0x00090004, 0x0 },
127 { 0x00C30FFF, 0x000C0000, 0x0 },
128 { 0x00FFFFFF, 0x00070006, 0x0 },
129 { 0x00D75FFF, 0x000C0000, 0x0 },
132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
133 /* Idx NT mV d T mV df db */
134 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
135 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
136 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
137 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
138 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
139 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
140 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
141 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
142 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
143 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
146 /* Skylake H and S */
147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
148 { 0x00002016, 0x000000A0, 0x0 },
149 { 0x00005012, 0x0000009B, 0x0 },
150 { 0x00007011, 0x00000088, 0x0 },
151 { 0x80009010, 0x000000C0, 0x1 },
152 { 0x00002016, 0x0000009B, 0x0 },
153 { 0x00005012, 0x00000088, 0x0 },
154 { 0x80007011, 0x000000C0, 0x1 },
155 { 0x00002016, 0x000000DF, 0x0 },
156 { 0x80005012, 0x000000C0, 0x1 },
160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
161 { 0x0000201B, 0x000000A2, 0x0 },
162 { 0x00005012, 0x00000088, 0x0 },
163 { 0x80007011, 0x000000CD, 0x1 },
164 { 0x80009010, 0x000000C0, 0x1 },
165 { 0x0000201B, 0x0000009D, 0x0 },
166 { 0x80005012, 0x000000C0, 0x1 },
167 { 0x80007011, 0x000000C0, 0x1 },
168 { 0x00002016, 0x00000088, 0x0 },
169 { 0x80005012, 0x000000C0, 0x1 },
173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
174 { 0x00000018, 0x000000A2, 0x0 },
175 { 0x00005012, 0x00000088, 0x0 },
176 { 0x80007011, 0x000000CD, 0x3 },
177 { 0x80009010, 0x000000C0, 0x3 },
178 { 0x00000018, 0x0000009D, 0x0 },
179 { 0x80005012, 0x000000C0, 0x3 },
180 { 0x80007011, 0x000000C0, 0x3 },
181 { 0x00000018, 0x00000088, 0x0 },
182 { 0x80005012, 0x000000C0, 0x3 },
185 /* Kabylake H and S */
186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
187 { 0x00002016, 0x000000A0, 0x0 },
188 { 0x00005012, 0x0000009B, 0x0 },
189 { 0x00007011, 0x00000088, 0x0 },
190 { 0x80009010, 0x000000C0, 0x1 },
191 { 0x00002016, 0x0000009B, 0x0 },
192 { 0x00005012, 0x00000088, 0x0 },
193 { 0x80007011, 0x000000C0, 0x1 },
194 { 0x00002016, 0x00000097, 0x0 },
195 { 0x80005012, 0x000000C0, 0x1 },
199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
200 { 0x0000201B, 0x000000A1, 0x0 },
201 { 0x00005012, 0x00000088, 0x0 },
202 { 0x80007011, 0x000000CD, 0x3 },
203 { 0x80009010, 0x000000C0, 0x3 },
204 { 0x0000201B, 0x0000009D, 0x0 },
205 { 0x80005012, 0x000000C0, 0x3 },
206 { 0x80007011, 0x000000C0, 0x3 },
207 { 0x00002016, 0x0000004F, 0x0 },
208 { 0x80005012, 0x000000C0, 0x3 },
212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
213 { 0x00001017, 0x000000A1, 0x0 },
214 { 0x00005012, 0x00000088, 0x0 },
215 { 0x80007011, 0x000000CD, 0x3 },
216 { 0x8000800F, 0x000000C0, 0x3 },
217 { 0x00001017, 0x0000009D, 0x0 },
218 { 0x80005012, 0x000000C0, 0x3 },
219 { 0x80007011, 0x000000C0, 0x3 },
220 { 0x00001017, 0x0000004C, 0x0 },
221 { 0x80005012, 0x000000C0, 0x3 },
225 * Skylake/Kabylake H and S
226 * eDP 1.4 low vswing translation parameters
228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
229 { 0x00000018, 0x000000A8, 0x0 },
230 { 0x00004013, 0x000000A9, 0x0 },
231 { 0x00007011, 0x000000A2, 0x0 },
232 { 0x00009010, 0x0000009C, 0x0 },
233 { 0x00000018, 0x000000A9, 0x0 },
234 { 0x00006013, 0x000000A2, 0x0 },
235 { 0x00007011, 0x000000A6, 0x0 },
236 { 0x00000018, 0x000000AB, 0x0 },
237 { 0x00007013, 0x0000009F, 0x0 },
238 { 0x00000018, 0x000000DF, 0x0 },
243 * eDP 1.4 low vswing translation parameters
245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
246 { 0x00000018, 0x000000A8, 0x0 },
247 { 0x00004013, 0x000000A9, 0x0 },
248 { 0x00007011, 0x000000A2, 0x0 },
249 { 0x00009010, 0x0000009C, 0x0 },
250 { 0x00000018, 0x000000A9, 0x0 },
251 { 0x00006013, 0x000000A2, 0x0 },
252 { 0x00007011, 0x000000A6, 0x0 },
253 { 0x00002016, 0x000000AB, 0x0 },
254 { 0x00005013, 0x0000009F, 0x0 },
255 { 0x00000018, 0x000000DF, 0x0 },
260 * eDP 1.4 low vswing translation parameters
262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
263 { 0x00000018, 0x000000A8, 0x0 },
264 { 0x00004013, 0x000000AB, 0x0 },
265 { 0x00007011, 0x000000A4, 0x0 },
266 { 0x00009010, 0x000000DF, 0x0 },
267 { 0x00000018, 0x000000AA, 0x0 },
268 { 0x00006013, 0x000000A4, 0x0 },
269 { 0x00007011, 0x0000009D, 0x0 },
270 { 0x00000018, 0x000000A0, 0x0 },
271 { 0x00006012, 0x000000DF, 0x0 },
272 { 0x00000018, 0x0000008A, 0x0 },
275 /* Skylake/Kabylake U, H and S */
276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
277 { 0x00000018, 0x000000AC, 0x0 },
278 { 0x00005012, 0x0000009D, 0x0 },
279 { 0x00007011, 0x00000088, 0x0 },
280 { 0x00000018, 0x000000A1, 0x0 },
281 { 0x00000018, 0x00000098, 0x0 },
282 { 0x00004013, 0x00000088, 0x0 },
283 { 0x80006012, 0x000000CD, 0x1 },
284 { 0x00000018, 0x000000DF, 0x0 },
285 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
286 { 0x80003015, 0x000000C0, 0x1 },
287 { 0x80000018, 0x000000C0, 0x1 },
290 /* Skylake/Kabylake Y */
291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
292 { 0x00000018, 0x000000A1, 0x0 },
293 { 0x00005012, 0x000000DF, 0x0 },
294 { 0x80007011, 0x000000CB, 0x3 },
295 { 0x00000018, 0x000000A4, 0x0 },
296 { 0x00000018, 0x0000009D, 0x0 },
297 { 0x00004013, 0x00000080, 0x0 },
298 { 0x80006013, 0x000000C0, 0x3 },
299 { 0x00000018, 0x0000008A, 0x0 },
300 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
301 { 0x80003015, 0x000000C0, 0x3 },
302 { 0x80000018, 0x000000C0, 0x3 },
305 struct bxt_ddi_buf_trans {
306 u8 margin; /* swing value */
307 u8 scale; /* scale value */
308 u8 enable; /* scale enable */
312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
313 /* Idx NT mV diff db */
314 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
315 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
316 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
317 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
318 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
319 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
320 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
321 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
322 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
323 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
327 /* Idx NT mV diff db */
328 { 26, 0, 0, 128, }, /* 0: 200 0 */
329 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
330 { 48, 0, 0, 96, }, /* 2: 200 4 */
331 { 54, 0, 0, 69, }, /* 3: 200 6 */
332 { 32, 0, 0, 128, }, /* 4: 250 0 */
333 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
334 { 54, 0, 0, 85, }, /* 6: 250 4 */
335 { 43, 0, 0, 128, }, /* 7: 300 0 */
336 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
337 { 48, 0, 0, 128, }, /* 9: 300 0 */
340 /* BSpec has 2 recommended values - entries 0 and 8.
341 * Using the entry with higher vswing.
343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
344 /* Idx NT mV diff db */
345 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
346 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
347 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
348 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
349 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
350 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
351 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
352 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
353 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
354 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
357 struct cnl_ddi_buf_trans {
361 u8 dw4_post_cursor_2;
362 u8 dw4_post_cursor_1;
365 /* Voltage Swing Programming for VccIO 0.85V for DP */
366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
367 /* NT mV Trans mV db */
368 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
369 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
370 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
371 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
372 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
373 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
374 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
375 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
376 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
377 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
382 /* NT mV Trans mV db */
383 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
384 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
385 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
386 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
387 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
388 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
389 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
394 /* NT mV Trans mV db */
395 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
396 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
397 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
398 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
399 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
400 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
401 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
402 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
403 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
406 /* Voltage Swing Programming for VccIO 0.95V for DP */
407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
408 /* NT mV Trans mV db */
409 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
410 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
411 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
412 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
413 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
414 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
415 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
416 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
417 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
418 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
423 /* NT mV Trans mV db */
424 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
425 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
426 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
427 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
428 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
429 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
430 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
431 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
432 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
433 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
434 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
439 /* NT mV Trans mV db */
440 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
441 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
442 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
443 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
444 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
445 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
446 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
447 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
448 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
449 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
452 /* Voltage Swing Programming for VccIO 1.05V for DP */
453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
454 /* NT mV Trans mV db */
455 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
456 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
457 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
458 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
459 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
460 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
461 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
462 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
463 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
464 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
469 /* NT mV Trans mV db */
470 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
471 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
472 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
473 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
474 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
475 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
476 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
477 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
478 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
479 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
480 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
485 /* NT mV Trans mV db */
486 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
487 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
488 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
489 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
490 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
491 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
492 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
493 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
494 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
497 /* icl_combo_phy_ddi_translations */
498 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
499 /* NT mV Trans mV db */
500 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
501 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
502 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
503 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
504 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
505 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
506 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
507 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
508 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
509 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
512 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
513 /* NT mV Trans mV db */
514 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
515 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
516 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
517 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
518 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
519 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
520 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
521 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
522 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
523 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
526 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
527 /* NT mV Trans mV db */
528 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
529 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
530 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
531 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
532 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
533 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
534 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
535 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
536 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
537 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
540 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
541 /* NT mV Trans mV db */
542 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
543 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
544 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
545 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
546 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
547 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
548 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
551 struct icl_mg_phy_ddi_buf_trans {
552 u32 cri_txdeemph_override_5_0;
553 u32 cri_txdeemph_override_11_6;
554 u32 cri_txdeemph_override_17_12;
557 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
558 /* Voltage swing pre-emphasis */
559 { 0x0, 0x1B, 0x00 }, /* 0 0 */
560 { 0x0, 0x23, 0x08 }, /* 0 1 */
561 { 0x0, 0x2D, 0x12 }, /* 0 2 */
562 { 0x0, 0x00, 0x00 }, /* 0 3 */
563 { 0x0, 0x23, 0x00 }, /* 1 0 */
564 { 0x0, 0x2B, 0x09 }, /* 1 1 */
565 { 0x0, 0x2E, 0x11 }, /* 1 2 */
566 { 0x0, 0x2F, 0x00 }, /* 2 0 */
567 { 0x0, 0x33, 0x0C }, /* 2 1 */
568 { 0x0, 0x00, 0x00 }, /* 3 0 */
571 static const struct ddi_buf_trans *
572 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
574 if (dev_priv->vbt.edp.low_vswing) {
575 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
576 return bdw_ddi_translations_edp;
578 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
579 return bdw_ddi_translations_dp;
583 static const struct ddi_buf_trans *
584 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
586 if (IS_SKL_ULX(dev_priv)) {
587 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
588 return skl_y_ddi_translations_dp;
589 } else if (IS_SKL_ULT(dev_priv)) {
590 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
591 return skl_u_ddi_translations_dp;
593 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
594 return skl_ddi_translations_dp;
598 static const struct ddi_buf_trans *
599 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
601 if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
602 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
603 return kbl_y_ddi_translations_dp;
604 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
605 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
606 return kbl_u_ddi_translations_dp;
608 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
609 return kbl_ddi_translations_dp;
613 static const struct ddi_buf_trans *
614 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
616 if (dev_priv->vbt.edp.low_vswing) {
617 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
618 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
619 return skl_y_ddi_translations_edp;
620 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
621 IS_CFL_ULT(dev_priv)) {
622 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
623 return skl_u_ddi_translations_edp;
625 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
626 return skl_ddi_translations_edp;
630 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
631 return kbl_get_buf_trans_dp(dev_priv, n_entries);
633 return skl_get_buf_trans_dp(dev_priv, n_entries);
636 static const struct ddi_buf_trans *
637 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
639 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
640 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
641 return skl_y_ddi_translations_hdmi;
643 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
644 return skl_ddi_translations_hdmi;
648 static int skl_buf_trans_num_entries(enum port port, int n_entries)
650 /* Only DDIA and DDIE can select the 10th register with DP */
651 if (port == PORT_A || port == PORT_E)
652 return min(n_entries, 10);
654 return min(n_entries, 9);
657 static const struct ddi_buf_trans *
658 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
659 enum port port, int *n_entries)
661 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
662 const struct ddi_buf_trans *ddi_translations =
663 kbl_get_buf_trans_dp(dev_priv, n_entries);
664 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
665 return ddi_translations;
666 } else if (IS_SKYLAKE(dev_priv)) {
667 const struct ddi_buf_trans *ddi_translations =
668 skl_get_buf_trans_dp(dev_priv, n_entries);
669 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
670 return ddi_translations;
671 } else if (IS_BROADWELL(dev_priv)) {
672 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
673 return bdw_ddi_translations_dp;
674 } else if (IS_HASWELL(dev_priv)) {
675 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
676 return hsw_ddi_translations_dp;
683 static const struct ddi_buf_trans *
684 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
685 enum port port, int *n_entries)
687 if (IS_GEN9_BC(dev_priv)) {
688 const struct ddi_buf_trans *ddi_translations =
689 skl_get_buf_trans_edp(dev_priv, n_entries);
690 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
691 return ddi_translations;
692 } else if (IS_BROADWELL(dev_priv)) {
693 return bdw_get_buf_trans_edp(dev_priv, n_entries);
694 } else if (IS_HASWELL(dev_priv)) {
695 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
696 return hsw_ddi_translations_dp;
703 static const struct ddi_buf_trans *
704 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
707 if (IS_BROADWELL(dev_priv)) {
708 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
709 return bdw_ddi_translations_fdi;
710 } else if (IS_HASWELL(dev_priv)) {
711 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
712 return hsw_ddi_translations_fdi;
719 static const struct ddi_buf_trans *
720 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
723 if (IS_GEN9_BC(dev_priv)) {
724 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
725 } else if (IS_BROADWELL(dev_priv)) {
726 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
727 return bdw_ddi_translations_hdmi;
728 } else if (IS_HASWELL(dev_priv)) {
729 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
730 return hsw_ddi_translations_hdmi;
737 static const struct bxt_ddi_buf_trans *
738 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
740 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
741 return bxt_ddi_translations_dp;
744 static const struct bxt_ddi_buf_trans *
745 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
747 if (dev_priv->vbt.edp.low_vswing) {
748 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
749 return bxt_ddi_translations_edp;
752 return bxt_get_buf_trans_dp(dev_priv, n_entries);
755 static const struct bxt_ddi_buf_trans *
756 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
758 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
759 return bxt_ddi_translations_hdmi;
762 static const struct cnl_ddi_buf_trans *
763 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
765 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
767 if (voltage == VOLTAGE_INFO_0_85V) {
768 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
769 return cnl_ddi_translations_hdmi_0_85V;
770 } else if (voltage == VOLTAGE_INFO_0_95V) {
771 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
772 return cnl_ddi_translations_hdmi_0_95V;
773 } else if (voltage == VOLTAGE_INFO_1_05V) {
774 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
775 return cnl_ddi_translations_hdmi_1_05V;
777 *n_entries = 1; /* shut up gcc */
778 MISSING_CASE(voltage);
783 static const struct cnl_ddi_buf_trans *
784 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
786 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
788 if (voltage == VOLTAGE_INFO_0_85V) {
789 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
790 return cnl_ddi_translations_dp_0_85V;
791 } else if (voltage == VOLTAGE_INFO_0_95V) {
792 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
793 return cnl_ddi_translations_dp_0_95V;
794 } else if (voltage == VOLTAGE_INFO_1_05V) {
795 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
796 return cnl_ddi_translations_dp_1_05V;
798 *n_entries = 1; /* shut up gcc */
799 MISSING_CASE(voltage);
804 static const struct cnl_ddi_buf_trans *
805 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
807 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
809 if (dev_priv->vbt.edp.low_vswing) {
810 if (voltage == VOLTAGE_INFO_0_85V) {
811 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
812 return cnl_ddi_translations_edp_0_85V;
813 } else if (voltage == VOLTAGE_INFO_0_95V) {
814 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
815 return cnl_ddi_translations_edp_0_95V;
816 } else if (voltage == VOLTAGE_INFO_1_05V) {
817 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
818 return cnl_ddi_translations_edp_1_05V;
820 *n_entries = 1; /* shut up gcc */
821 MISSING_CASE(voltage);
825 return cnl_get_buf_trans_dp(dev_priv, n_entries);
829 static const struct cnl_ddi_buf_trans *
830 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
831 int type, int rate, int *n_entries)
833 if (type == INTEL_OUTPUT_HDMI) {
834 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
835 return icl_combo_phy_ddi_translations_hdmi;
836 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
837 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
838 return icl_combo_phy_ddi_translations_edp_hbr3;
839 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
840 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
841 return icl_combo_phy_ddi_translations_edp_hbr2;
844 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
845 return icl_combo_phy_ddi_translations_dp_hbr2;
848 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
850 int n_entries, level, default_entry;
852 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
854 if (IS_ICELAKE(dev_priv)) {
855 if (intel_port_is_combophy(dev_priv, port))
856 icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
859 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
860 default_entry = n_entries - 1;
861 } else if (IS_CANNONLAKE(dev_priv)) {
862 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
863 default_entry = n_entries - 1;
864 } else if (IS_GEN9_LP(dev_priv)) {
865 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
866 default_entry = n_entries - 1;
867 } else if (IS_GEN9_BC(dev_priv)) {
868 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
870 } else if (IS_BROADWELL(dev_priv)) {
871 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
873 } else if (IS_HASWELL(dev_priv)) {
874 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
877 WARN(1, "ddi translation table missing\n");
881 /* Choose a good default if VBT is badly populated */
882 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
883 level = default_entry;
885 if (WARN_ON_ONCE(n_entries == 0))
887 if (WARN_ON_ONCE(level >= n_entries))
888 level = n_entries - 1;
894 * Starting with Haswell, DDI port buffers must be programmed with correct
895 * values in advance. This function programs the correct values for
896 * DP/eDP/FDI use cases.
898 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
899 const struct intel_crtc_state *crtc_state)
901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
904 enum port port = encoder->port;
905 const struct ddi_buf_trans *ddi_translations;
907 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
908 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
910 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
911 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
914 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
917 /* If we're boosting the current, set bit 31 of trans1 */
918 if (IS_GEN9_BC(dev_priv) &&
919 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
920 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
922 for (i = 0; i < n_entries; i++) {
923 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
924 ddi_translations[i].trans1 | iboost_bit);
925 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
926 ddi_translations[i].trans2);
931 * Starting with Haswell, DDI port buffers must be programmed with correct
932 * values in advance. This function programs the correct values for
933 * HDMI/DVI use cases.
935 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
941 enum port port = encoder->port;
942 const struct ddi_buf_trans *ddi_translations;
944 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
946 if (WARN_ON_ONCE(!ddi_translations))
948 if (WARN_ON_ONCE(level >= n_entries))
949 level = n_entries - 1;
951 /* If we're boosting the current, set bit 31 of trans1 */
952 if (IS_GEN9_BC(dev_priv) &&
953 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
954 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
956 /* Entry 9 is for HDMI: */
957 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
958 ddi_translations[level].trans1 | iboost_bit);
959 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
960 ddi_translations[level].trans2);
963 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
966 i915_reg_t reg = DDI_BUF_CTL(port);
969 for (i = 0; i < 16; i++) {
971 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
974 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
977 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
979 switch (pll->info->id) {
981 return PORT_CLK_SEL_WRPLL1;
983 return PORT_CLK_SEL_WRPLL2;
985 return PORT_CLK_SEL_SPLL;
986 case DPLL_ID_LCPLL_810:
987 return PORT_CLK_SEL_LCPLL_810;
988 case DPLL_ID_LCPLL_1350:
989 return PORT_CLK_SEL_LCPLL_1350;
990 case DPLL_ID_LCPLL_2700:
991 return PORT_CLK_SEL_LCPLL_2700;
993 MISSING_CASE(pll->info->id);
994 return PORT_CLK_SEL_NONE;
998 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
999 const struct intel_crtc_state *crtc_state)
1001 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1002 int clock = crtc_state->port_clock;
1003 const enum intel_dpll_id id = pll->info->id;
1009 case DPLL_ID_ICL_DPLL0:
1010 case DPLL_ID_ICL_DPLL1:
1011 return DDI_CLK_SEL_NONE;
1012 case DPLL_ID_ICL_TBTPLL:
1015 return DDI_CLK_SEL_TBT_162;
1017 return DDI_CLK_SEL_TBT_270;
1019 return DDI_CLK_SEL_TBT_540;
1021 return DDI_CLK_SEL_TBT_810;
1023 MISSING_CASE(clock);
1024 return DDI_CLK_SEL_NONE;
1026 case DPLL_ID_ICL_MGPLL1:
1027 case DPLL_ID_ICL_MGPLL2:
1028 case DPLL_ID_ICL_MGPLL3:
1029 case DPLL_ID_ICL_MGPLL4:
1030 return DDI_CLK_SEL_MG;
1034 /* Starting with Haswell, different DDI ports can work in FDI mode for
1035 * connection to the PCH-located connectors. For this, it is necessary to train
1036 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1038 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1039 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1040 * DDI A (which is used for eDP)
1043 void hsw_fdi_link_train(struct intel_crtc *crtc,
1044 const struct intel_crtc_state *crtc_state)
1046 struct drm_device *dev = crtc->base.dev;
1047 struct drm_i915_private *dev_priv = to_i915(dev);
1048 struct intel_encoder *encoder;
1049 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1051 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1052 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1053 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1056 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1057 * mode set "sequence for CRT port" document:
1058 * - TP1 to TP2 time with the default value
1059 * - FDI delay to 90h
1061 * WaFDIAutoLinkSetTimingOverrride:hsw
1063 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1064 FDI_RX_PWRDN_LANE0_VAL(2) |
1065 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1067 /* Enable the PCH Receiver FDI PLL */
1068 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1070 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1071 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1072 POSTING_READ(FDI_RX_CTL(PIPE_A));
1075 /* Switch from Rawclk to PCDclk */
1076 rx_ctl_val |= FDI_PCDCLK;
1077 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1079 /* Configure Port Clock Select */
1080 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1081 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1082 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1084 /* Start the training iterating through available voltages and emphasis,
1085 * testing each value twice. */
1086 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1087 /* Configure DP_TP_CTL with auto-training */
1088 I915_WRITE(DP_TP_CTL(PORT_E),
1089 DP_TP_CTL_FDI_AUTOTRAIN |
1090 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1091 DP_TP_CTL_LINK_TRAIN_PAT1 |
1094 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1095 * DDI E does not support port reversal, the functionality is
1096 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1097 * port reversal bit */
1098 I915_WRITE(DDI_BUF_CTL(PORT_E),
1099 DDI_BUF_CTL_ENABLE |
1100 ((crtc_state->fdi_lanes - 1) << 1) |
1101 DDI_BUF_TRANS_SELECT(i / 2));
1102 POSTING_READ(DDI_BUF_CTL(PORT_E));
1106 /* Program PCH FDI Receiver TU */
1107 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1109 /* Enable PCH FDI Receiver with auto-training */
1110 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1111 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1112 POSTING_READ(FDI_RX_CTL(PIPE_A));
1114 /* Wait for FDI receiver lane calibration */
1117 /* Unset FDI_RX_MISC pwrdn lanes */
1118 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1119 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1120 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1121 POSTING_READ(FDI_RX_MISC(PIPE_A));
1123 /* Wait for FDI auto training time */
1126 temp = I915_READ(DP_TP_STATUS(PORT_E));
1127 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1128 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1133 * Leave things enabled even if we failed to train FDI.
1134 * Results in less fireworks from the state checker.
1136 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1137 DRM_ERROR("FDI link training failed!\n");
1141 rx_ctl_val &= ~FDI_RX_ENABLE;
1142 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1143 POSTING_READ(FDI_RX_CTL(PIPE_A));
1145 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1146 temp &= ~DDI_BUF_CTL_ENABLE;
1147 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1148 POSTING_READ(DDI_BUF_CTL(PORT_E));
1150 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1151 temp = I915_READ(DP_TP_CTL(PORT_E));
1152 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1153 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1154 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1155 POSTING_READ(DP_TP_CTL(PORT_E));
1157 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1159 /* Reset FDI_RX_MISC pwrdn lanes */
1160 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1161 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1162 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1163 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1164 POSTING_READ(FDI_RX_MISC(PIPE_A));
1167 /* Enable normal pixel sending for FDI */
1168 I915_WRITE(DP_TP_CTL(PORT_E),
1169 DP_TP_CTL_FDI_AUTOTRAIN |
1170 DP_TP_CTL_LINK_TRAIN_NORMAL |
1171 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1175 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1177 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1178 struct intel_digital_port *intel_dig_port =
1179 enc_to_dig_port(&encoder->base);
1181 intel_dp->DP = intel_dig_port->saved_port_bits |
1182 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1183 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1186 static struct intel_encoder *
1187 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1189 struct drm_device *dev = crtc->base.dev;
1190 struct intel_encoder *encoder, *ret = NULL;
1191 int num_encoders = 0;
1193 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1198 if (num_encoders != 1)
1199 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1200 pipe_name(crtc->pipe));
1202 BUG_ON(ret == NULL);
1206 #define LC_FREQ 2700
1208 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1211 int refclk = LC_FREQ;
1215 wrpll = I915_READ(reg);
1216 switch (wrpll & WRPLL_PLL_REF_MASK) {
1218 case WRPLL_PLL_NON_SSC:
1220 * We could calculate spread here, but our checking
1221 * code only cares about 5% accuracy, and spread is a max of
1226 case WRPLL_PLL_LCPLL:
1230 WARN(1, "bad wrpll refclk\n");
1234 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1235 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1236 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1238 /* Convert to KHz, p & r have a fixed point portion */
1239 return (refclk * n * 100) / (p * r);
1242 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1243 enum intel_dpll_id pll_id)
1245 i915_reg_t cfgcr1_reg, cfgcr2_reg;
1246 uint32_t cfgcr1_val, cfgcr2_val;
1247 uint32_t p0, p1, p2, dco_freq;
1249 cfgcr1_reg = DPLL_CFGCR1(pll_id);
1250 cfgcr2_reg = DPLL_CFGCR2(pll_id);
1252 cfgcr1_val = I915_READ(cfgcr1_reg);
1253 cfgcr2_val = I915_READ(cfgcr2_reg);
1255 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1256 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1258 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
1259 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1265 case DPLL_CFGCR2_PDIV_1:
1268 case DPLL_CFGCR2_PDIV_2:
1271 case DPLL_CFGCR2_PDIV_3:
1274 case DPLL_CFGCR2_PDIV_7:
1280 case DPLL_CFGCR2_KDIV_5:
1283 case DPLL_CFGCR2_KDIV_2:
1286 case DPLL_CFGCR2_KDIV_3:
1289 case DPLL_CFGCR2_KDIV_1:
1294 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1296 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1299 return dco_freq / (p0 * p1 * p2 * 5);
1302 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1303 enum intel_dpll_id pll_id)
1305 uint32_t cfgcr0, cfgcr1;
1306 uint32_t p0, p1, p2, dco_freq, ref_clock;
1308 if (INTEL_GEN(dev_priv) >= 11) {
1309 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1310 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1312 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1313 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1316 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1317 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1319 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1320 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1321 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1327 case DPLL_CFGCR1_PDIV_2:
1330 case DPLL_CFGCR1_PDIV_3:
1333 case DPLL_CFGCR1_PDIV_5:
1336 case DPLL_CFGCR1_PDIV_7:
1342 case DPLL_CFGCR1_KDIV_1:
1345 case DPLL_CFGCR1_KDIV_2:
1348 case DPLL_CFGCR1_KDIV_4:
1353 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1355 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1357 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1358 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1360 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1363 return dco_freq / (p0 * p1 * p2 * 5);
1366 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1369 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1372 case DDI_CLK_SEL_NONE:
1374 case DDI_CLK_SEL_TBT_162:
1376 case DDI_CLK_SEL_TBT_270:
1378 case DDI_CLK_SEL_TBT_540:
1380 case DDI_CLK_SEL_TBT_810:
1388 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1391 u32 mg_pll_div0, mg_clktop_hsclkctl;
1392 u32 m1, m2_int, m2_frac, div1, div2, refclk;
1395 refclk = dev_priv->cdclk.hw.ref;
1397 mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1398 mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1400 m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1401 m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1402 m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1403 (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1404 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1406 switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1407 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1410 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1413 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1416 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1420 MISSING_CASE(mg_clktop_hsclkctl);
1424 div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1425 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1426 /* div2 value of 0 is same as 1 means no div */
1431 * Adjust the original formula to delay the division by 2^22 in order to
1432 * minimize possible rounding errors.
1434 tmp = (u64)m1 * m2_int * refclk +
1435 (((u64)m1 * m2_frac * refclk) >> 22);
1436 tmp = div_u64(tmp, 5 * div1 * div2);
1441 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1445 if (pipe_config->has_pch_encoder)
1446 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1447 &pipe_config->fdi_m_n);
1448 else if (intel_crtc_has_dp_encoder(pipe_config))
1449 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1450 &pipe_config->dp_m_n);
1451 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1452 dotclock = pipe_config->port_clock * 2 / 3;
1454 dotclock = pipe_config->port_clock;
1456 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1459 if (pipe_config->pixel_multiplier)
1460 dotclock /= pipe_config->pixel_multiplier;
1462 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1465 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1466 struct intel_crtc_state *pipe_config)
1468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1469 enum port port = encoder->port;
1473 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1474 if (intel_port_is_combophy(dev_priv, port)) {
1475 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1476 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1478 link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1481 if (pll_id == DPLL_ID_ICL_TBTPLL)
1482 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1484 link_clock = icl_calc_mg_pll_link(dev_priv, port);
1487 pipe_config->port_clock = link_clock;
1488 ddi_dotclock_get(pipe_config);
1491 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1492 struct intel_crtc_state *pipe_config)
1494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1497 enum intel_dpll_id pll_id;
1499 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1501 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1503 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1504 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1506 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1508 switch (link_clock) {
1509 case DPLL_CFGCR0_LINK_RATE_810:
1512 case DPLL_CFGCR0_LINK_RATE_1080:
1513 link_clock = 108000;
1515 case DPLL_CFGCR0_LINK_RATE_1350:
1516 link_clock = 135000;
1518 case DPLL_CFGCR0_LINK_RATE_1620:
1519 link_clock = 162000;
1521 case DPLL_CFGCR0_LINK_RATE_2160:
1522 link_clock = 216000;
1524 case DPLL_CFGCR0_LINK_RATE_2700:
1525 link_clock = 270000;
1527 case DPLL_CFGCR0_LINK_RATE_3240:
1528 link_clock = 324000;
1530 case DPLL_CFGCR0_LINK_RATE_4050:
1531 link_clock = 405000;
1534 WARN(1, "Unsupported link rate\n");
1540 pipe_config->port_clock = link_clock;
1542 ddi_dotclock_get(pipe_config);
1545 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1546 struct intel_crtc_state *pipe_config)
1548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1551 enum intel_dpll_id pll_id;
1553 pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1555 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1557 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1558 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1560 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1561 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1563 switch (link_clock) {
1564 case DPLL_CTRL1_LINK_RATE_810:
1567 case DPLL_CTRL1_LINK_RATE_1080:
1568 link_clock = 108000;
1570 case DPLL_CTRL1_LINK_RATE_1350:
1571 link_clock = 135000;
1573 case DPLL_CTRL1_LINK_RATE_1620:
1574 link_clock = 162000;
1576 case DPLL_CTRL1_LINK_RATE_2160:
1577 link_clock = 216000;
1579 case DPLL_CTRL1_LINK_RATE_2700:
1580 link_clock = 270000;
1583 WARN(1, "Unsupported link rate\n");
1589 pipe_config->port_clock = link_clock;
1591 ddi_dotclock_get(pipe_config);
1594 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1595 struct intel_crtc_state *pipe_config)
1597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1601 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1602 switch (val & PORT_CLK_SEL_MASK) {
1603 case PORT_CLK_SEL_LCPLL_810:
1606 case PORT_CLK_SEL_LCPLL_1350:
1607 link_clock = 135000;
1609 case PORT_CLK_SEL_LCPLL_2700:
1610 link_clock = 270000;
1612 case PORT_CLK_SEL_WRPLL1:
1613 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1615 case PORT_CLK_SEL_WRPLL2:
1616 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1618 case PORT_CLK_SEL_SPLL:
1619 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1620 if (pll == SPLL_PLL_FREQ_810MHz)
1622 else if (pll == SPLL_PLL_FREQ_1350MHz)
1623 link_clock = 135000;
1624 else if (pll == SPLL_PLL_FREQ_2700MHz)
1625 link_clock = 270000;
1627 WARN(1, "bad spll freq\n");
1632 WARN(1, "bad port clock sel\n");
1636 pipe_config->port_clock = link_clock * 2;
1638 ddi_dotclock_get(pipe_config);
1641 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1643 struct intel_dpll_hw_state *state;
1646 /* For DDI ports we always use a shared PLL. */
1647 if (WARN_ON(!crtc_state->shared_dpll))
1650 state = &crtc_state->dpll_hw_state;
1653 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1654 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1655 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1656 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1657 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1658 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1660 return chv_calc_dpll_params(100000, &clock);
1663 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1664 struct intel_crtc_state *pipe_config)
1666 pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1668 ddi_dotclock_get(pipe_config);
1671 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1672 struct intel_crtc_state *pipe_config)
1674 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1676 if (IS_ICELAKE(dev_priv))
1677 icl_ddi_clock_get(encoder, pipe_config);
1678 else if (IS_CANNONLAKE(dev_priv))
1679 cnl_ddi_clock_get(encoder, pipe_config);
1680 else if (IS_GEN9_LP(dev_priv))
1681 bxt_ddi_clock_get(encoder, pipe_config);
1682 else if (IS_GEN9_BC(dev_priv))
1683 skl_ddi_clock_get(encoder, pipe_config);
1684 else if (INTEL_GEN(dev_priv) <= 8)
1685 hsw_ddi_clock_get(encoder, pipe_config);
1688 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1692 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1695 if (!intel_crtc_has_dp_encoder(crtc_state))
1698 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1700 temp = TRANS_MSA_SYNC_CLK;
1702 if (crtc_state->limited_color_range)
1703 temp |= TRANS_MSA_CEA_RANGE;
1705 switch (crtc_state->pipe_bpp) {
1707 temp |= TRANS_MSA_6_BPC;
1710 temp |= TRANS_MSA_8_BPC;
1713 temp |= TRANS_MSA_10_BPC;
1716 temp |= TRANS_MSA_12_BPC;
1719 MISSING_CASE(crtc_state->pipe_bpp);
1724 * As per DP 1.2 spec section 2.3.4.3 while sending
1725 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1726 * colorspace information. The output colorspace encoding is BT601.
1728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1729 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1730 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1733 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1737 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1738 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1741 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1743 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1745 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1746 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1749 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1752 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1753 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1754 enum pipe pipe = crtc->pipe;
1755 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1756 enum port port = encoder->port;
1759 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1760 temp = TRANS_DDI_FUNC_ENABLE;
1761 temp |= TRANS_DDI_SELECT_PORT(port);
1763 switch (crtc_state->pipe_bpp) {
1765 temp |= TRANS_DDI_BPC_6;
1768 temp |= TRANS_DDI_BPC_8;
1771 temp |= TRANS_DDI_BPC_10;
1774 temp |= TRANS_DDI_BPC_12;
1780 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1781 temp |= TRANS_DDI_PVSYNC;
1782 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1783 temp |= TRANS_DDI_PHSYNC;
1785 if (cpu_transcoder == TRANSCODER_EDP) {
1788 /* On Haswell, can only use the always-on power well for
1789 * eDP when not using the panel fitter, and when not
1790 * using motion blur mitigation (which we don't
1792 if (IS_HASWELL(dev_priv) &&
1793 (crtc_state->pch_pfit.enabled ||
1794 crtc_state->pch_pfit.force_thru))
1795 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1797 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1800 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1803 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1811 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1812 if (crtc_state->has_hdmi_sink)
1813 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1815 temp |= TRANS_DDI_MODE_SELECT_DVI;
1817 if (crtc_state->hdmi_scrambling)
1818 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1819 if (crtc_state->hdmi_high_tmds_clock_ratio)
1820 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1821 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1822 temp |= TRANS_DDI_MODE_SELECT_FDI;
1823 temp |= (crtc_state->fdi_lanes - 1) << 1;
1824 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1825 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1826 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1828 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1829 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1832 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1835 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1837 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1838 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1839 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1840 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1841 uint32_t val = I915_READ(reg);
1843 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1844 val |= TRANS_DDI_PORT_NONE;
1845 I915_WRITE(reg, val);
1847 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1848 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1849 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1850 /* Quirk time at 100ms for reliable operation */
1855 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1858 struct drm_device *dev = intel_encoder->base.dev;
1859 struct drm_i915_private *dev_priv = to_i915(dev);
1864 if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1865 intel_encoder->power_domain)))
1868 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1873 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1875 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1877 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1878 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1880 intel_display_power_put(dev_priv, intel_encoder->power_domain);
1884 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1886 struct drm_device *dev = intel_connector->base.dev;
1887 struct drm_i915_private *dev_priv = to_i915(dev);
1888 struct intel_encoder *encoder = intel_connector->encoder;
1889 int type = intel_connector->base.connector_type;
1890 enum port port = encoder->port;
1892 enum transcoder cpu_transcoder;
1896 if (!intel_display_power_get_if_enabled(dev_priv,
1897 encoder->power_domain))
1900 if (!encoder->get_hw_state(encoder, &pipe)) {
1906 cpu_transcoder = TRANSCODER_EDP;
1908 cpu_transcoder = (enum transcoder) pipe;
1910 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1912 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1913 case TRANS_DDI_MODE_SELECT_HDMI:
1914 case TRANS_DDI_MODE_SELECT_DVI:
1915 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1918 case TRANS_DDI_MODE_SELECT_DP_SST:
1919 ret = type == DRM_MODE_CONNECTOR_eDP ||
1920 type == DRM_MODE_CONNECTOR_DisplayPort;
1923 case TRANS_DDI_MODE_SELECT_DP_MST:
1924 /* if the transcoder is in MST state then
1925 * connector isn't connected */
1929 case TRANS_DDI_MODE_SELECT_FDI:
1930 ret = type == DRM_MODE_CONNECTOR_VGA;
1939 intel_display_power_put(dev_priv, encoder->power_domain);
1944 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1945 u8 *pipe_mask, bool *is_dp_mst)
1947 struct drm_device *dev = encoder->base.dev;
1948 struct drm_i915_private *dev_priv = to_i915(dev);
1949 enum port port = encoder->port;
1957 if (!intel_display_power_get_if_enabled(dev_priv,
1958 encoder->power_domain))
1961 tmp = I915_READ(DDI_BUF_CTL(port));
1962 if (!(tmp & DDI_BUF_CTL_ENABLE))
1965 if (port == PORT_A) {
1966 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1968 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1970 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1972 case TRANS_DDI_EDP_INPUT_A_ON:
1973 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1974 *pipe_mask = BIT(PIPE_A);
1976 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1977 *pipe_mask = BIT(PIPE_B);
1979 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1980 *pipe_mask = BIT(PIPE_C);
1988 for_each_pipe(dev_priv, p) {
1989 enum transcoder cpu_transcoder = (enum transcoder)p;
1991 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1993 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
1996 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1997 TRANS_DDI_MODE_SELECT_DP_MST)
1998 mst_pipe_mask |= BIT(p);
2000 *pipe_mask |= BIT(p);
2004 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2007 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2008 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2009 port_name(port), *pipe_mask);
2010 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2013 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2014 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2015 port_name(port), *pipe_mask, mst_pipe_mask);
2017 *is_dp_mst = mst_pipe_mask;
2020 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2021 tmp = I915_READ(BXT_PHY_CTL(port));
2022 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2023 BXT_PHY_LANE_POWERDOWN_ACK |
2024 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2025 DRM_ERROR("Port %c enabled but PHY powered down? "
2026 "(PHY_CTL %08x)\n", port_name(port), tmp);
2029 intel_display_power_put(dev_priv, encoder->power_domain);
2032 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2038 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2040 if (is_mst || !pipe_mask)
2043 *pipe = ffs(pipe_mask) - 1;
2048 static inline enum intel_display_power_domain
2049 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2051 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2052 * DC states enabled at the same time, while for driver initiated AUX
2053 * transfers we need the same AUX IOs to be powered but with DC states
2054 * disabled. Accordingly use the AUX power domain here which leaves DC
2056 * However, for non-A AUX ports the corresponding non-EDP transcoders
2057 * would have already enabled power well 2 and DC_OFF. This means we can
2058 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2059 * specific AUX_IO reference without powering up any extra wells.
2060 * Note that PSR is enabled only on Port A even though this function
2061 * returns the correct domain for other ports too.
2063 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2064 intel_aux_power_domain(dig_port);
2067 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2068 struct intel_crtc_state *crtc_state)
2070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2071 struct intel_digital_port *dig_port;
2075 * TODO: Add support for MST encoders. Atm, the following should never
2076 * happen since fake-MST encoders don't set their get_power_domains()
2079 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2082 dig_port = enc_to_dig_port(&encoder->base);
2083 domains = BIT_ULL(dig_port->ddi_io_power_domain);
2086 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2089 if (intel_crtc_has_dp_encoder(crtc_state) ||
2090 intel_port_is_tc(dev_priv, encoder->port))
2091 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2094 * VDSC power is needed when DSC is enabled
2096 if (crtc_state->dsc_params.compression_enable)
2097 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2102 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2106 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2107 enum port port = encoder->port;
2108 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2110 if (cpu_transcoder != TRANSCODER_EDP)
2111 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2112 TRANS_CLK_SEL_PORT(port));
2115 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2117 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2118 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2120 if (cpu_transcoder != TRANSCODER_EDP)
2121 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2122 TRANS_CLK_SEL_DISABLED);
2125 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2126 enum port port, uint8_t iboost)
2130 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2131 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2133 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2135 tmp |= BALANCE_LEG_DISABLE(port);
2136 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2139 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2140 int level, enum intel_output_type type)
2142 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2144 enum port port = encoder->port;
2147 if (type == INTEL_OUTPUT_HDMI)
2148 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2150 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2153 const struct ddi_buf_trans *ddi_translations;
2156 if (type == INTEL_OUTPUT_HDMI)
2157 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2158 else if (type == INTEL_OUTPUT_EDP)
2159 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2161 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2163 if (WARN_ON_ONCE(!ddi_translations))
2165 if (WARN_ON_ONCE(level >= n_entries))
2166 level = n_entries - 1;
2168 iboost = ddi_translations[level].i_boost;
2171 /* Make sure that the requested I_boost is valid */
2172 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2173 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2177 _skl_ddi_set_iboost(dev_priv, port, iboost);
2179 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2180 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2183 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2184 int level, enum intel_output_type type)
2186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2187 const struct bxt_ddi_buf_trans *ddi_translations;
2188 enum port port = encoder->port;
2191 if (type == INTEL_OUTPUT_HDMI)
2192 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2193 else if (type == INTEL_OUTPUT_EDP)
2194 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2196 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2198 if (WARN_ON_ONCE(!ddi_translations))
2200 if (WARN_ON_ONCE(level >= n_entries))
2201 level = n_entries - 1;
2203 bxt_ddi_phy_set_signal_level(dev_priv, port,
2204 ddi_translations[level].margin,
2205 ddi_translations[level].scale,
2206 ddi_translations[level].enable,
2207 ddi_translations[level].deemphasis);
2210 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2213 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2214 enum port port = encoder->port;
2217 if (IS_ICELAKE(dev_priv)) {
2218 if (intel_port_is_combophy(dev_priv, port))
2219 icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2220 intel_dp->link_rate, &n_entries);
2222 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2223 } else if (IS_CANNONLAKE(dev_priv)) {
2224 if (encoder->type == INTEL_OUTPUT_EDP)
2225 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2227 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2228 } else if (IS_GEN9_LP(dev_priv)) {
2229 if (encoder->type == INTEL_OUTPUT_EDP)
2230 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2232 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2234 if (encoder->type == INTEL_OUTPUT_EDP)
2235 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2237 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2240 if (WARN_ON(n_entries < 1))
2242 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2243 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2245 return index_to_dp_signal_levels[n_entries - 1] &
2246 DP_TRAIN_VOLTAGE_SWING_MASK;
2250 * We assume that the full set of pre-emphasis values can be
2251 * used on all DDI platforms. Should that change we need to
2252 * rethink this code.
2254 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2256 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2258 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2260 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2261 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2262 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2265 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2269 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2270 int level, enum intel_output_type type)
2272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2273 const struct cnl_ddi_buf_trans *ddi_translations;
2274 enum port port = encoder->port;
2278 if (type == INTEL_OUTPUT_HDMI)
2279 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2280 else if (type == INTEL_OUTPUT_EDP)
2281 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2283 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2285 if (WARN_ON_ONCE(!ddi_translations))
2287 if (WARN_ON_ONCE(level >= n_entries))
2288 level = n_entries - 1;
2290 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2291 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2292 val &= ~SCALING_MODE_SEL_MASK;
2293 val |= SCALING_MODE_SEL(2);
2294 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2296 /* Program PORT_TX_DW2 */
2297 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2298 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2300 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2301 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2302 /* Rcomp scalar is fixed as 0x98 for every table entry */
2303 val |= RCOMP_SCALAR(0x98);
2304 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2306 /* Program PORT_TX_DW4 */
2307 /* We cannot write to GRP. It would overrite individual loadgen */
2308 for (ln = 0; ln < 4; ln++) {
2309 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2310 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2312 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2313 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2314 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2315 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2318 /* Program PORT_TX_DW5 */
2319 /* All DW5 values are fixed for every table entry */
2320 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2321 val &= ~RTERM_SELECT_MASK;
2322 val |= RTERM_SELECT(6);
2323 val |= TAP3_DISABLE;
2324 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2326 /* Program PORT_TX_DW7 */
2327 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2328 val &= ~N_SCALAR_MASK;
2329 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2330 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2333 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2334 int level, enum intel_output_type type)
2336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2337 enum port port = encoder->port;
2338 int width, rate, ln;
2341 if (type == INTEL_OUTPUT_HDMI) {
2343 rate = 0; /* Rate is always < than 6GHz for HDMI */
2345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2347 width = intel_dp->lane_count;
2348 rate = intel_dp->link_rate;
2352 * 1. If port type is eDP or DP,
2353 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2356 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2357 if (type != INTEL_OUTPUT_HDMI)
2358 val |= COMMON_KEEPER_EN;
2360 val &= ~COMMON_KEEPER_EN;
2361 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2363 /* 2. Program loadgen select */
2365 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2366 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2367 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2368 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2370 for (ln = 0; ln <= 3; ln++) {
2371 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2372 val &= ~LOADGEN_SELECT;
2374 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2375 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2376 val |= LOADGEN_SELECT;
2378 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2381 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2382 val = I915_READ(CNL_PORT_CL1CM_DW5);
2383 val |= SUS_CLOCK_CONFIG;
2384 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2386 /* 4. Clear training enable to change swing values */
2387 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2388 val &= ~TX_TRAINING_EN;
2389 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2391 /* 5. Program swing and de-emphasis */
2392 cnl_ddi_vswing_program(encoder, level, type);
2394 /* 6. Set training enable to trigger update */
2395 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2396 val |= TX_TRAINING_EN;
2397 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2400 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2401 u32 level, enum port port, int type,
2404 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2408 ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2410 if (!ddi_translations)
2413 if (level >= n_entries) {
2414 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2415 level = n_entries - 1;
2418 /* Set PORT_TX_DW5 */
2419 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2420 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2421 TAP2_DISABLE | TAP3_DISABLE);
2422 val |= SCALING_MODE_SEL(0x2);
2423 val |= RTERM_SELECT(0x6);
2424 val |= TAP3_DISABLE;
2425 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2427 /* Program PORT_TX_DW2 */
2428 val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2429 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2431 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2432 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2433 /* Program Rcomp scalar for every table entry */
2434 val |= RCOMP_SCALAR(0x98);
2435 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2437 /* Program PORT_TX_DW4 */
2438 /* We cannot write to GRP. It would overwrite individual loadgen. */
2439 for (ln = 0; ln <= 3; ln++) {
2440 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2441 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2443 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2444 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2445 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2446 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2449 /* Program PORT_TX_DW7 */
2450 val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
2451 val &= ~N_SCALAR_MASK;
2452 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2453 I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
2456 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2458 enum intel_output_type type)
2460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2461 enum port port = encoder->port;
2467 if (type == INTEL_OUTPUT_HDMI) {
2469 /* Rate is always < than 6GHz for HDMI */
2471 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2473 width = intel_dp->lane_count;
2474 rate = intel_dp->link_rate;
2478 * 1. If port type is eDP or DP,
2479 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2482 val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2483 if (type == INTEL_OUTPUT_HDMI)
2484 val &= ~COMMON_KEEPER_EN;
2486 val |= COMMON_KEEPER_EN;
2487 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2489 /* 2. Program loadgen select */
2491 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2492 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2493 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2494 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2496 for (ln = 0; ln <= 3; ln++) {
2497 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2498 val &= ~LOADGEN_SELECT;
2500 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2501 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2502 val |= LOADGEN_SELECT;
2504 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2507 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2508 val = I915_READ(ICL_PORT_CL_DW5(port));
2509 val |= SUS_CLOCK_CONFIG;
2510 I915_WRITE(ICL_PORT_CL_DW5(port), val);
2512 /* 4. Clear training enable to change swing values */
2513 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2514 val &= ~TX_TRAINING_EN;
2515 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2517 /* 5. Program swing and de-emphasis */
2518 icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
2520 /* 6. Set training enable to trigger update */
2521 val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2522 val |= TX_TRAINING_EN;
2523 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2526 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2530 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2531 enum port port = encoder->port;
2532 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2536 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2537 ddi_translations = icl_mg_phy_ddi_translations;
2538 /* The table does not have values for level 3 and level 9. */
2539 if (level >= n_entries || level == 3 || level == 9) {
2540 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2541 level, n_entries - 2);
2542 level = n_entries - 2;
2545 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2546 for (ln = 0; ln < 2; ln++) {
2547 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2548 val &= ~CRI_USE_FS32;
2549 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2551 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2552 val &= ~CRI_USE_FS32;
2553 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2556 /* Program MG_TX_SWINGCTRL with values from vswing table */
2557 for (ln = 0; ln < 2; ln++) {
2558 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2559 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2560 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2561 ddi_translations[level].cri_txdeemph_override_17_12);
2562 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2564 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2565 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2566 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2567 ddi_translations[level].cri_txdeemph_override_17_12);
2568 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2571 /* Program MG_TX_DRVCTRL with values from vswing table */
2572 for (ln = 0; ln < 2; ln++) {
2573 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2574 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2575 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2576 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2577 ddi_translations[level].cri_txdeemph_override_5_0) |
2578 CRI_TXDEEMPH_OVERRIDE_11_6(
2579 ddi_translations[level].cri_txdeemph_override_11_6) |
2580 CRI_TXDEEMPH_OVERRIDE_EN;
2581 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2583 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2584 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2585 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2586 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2587 ddi_translations[level].cri_txdeemph_override_5_0) |
2588 CRI_TXDEEMPH_OVERRIDE_11_6(
2589 ddi_translations[level].cri_txdeemph_override_11_6) |
2590 CRI_TXDEEMPH_OVERRIDE_EN;
2591 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2593 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2597 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2598 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2599 * values from table for which TX1 and TX2 enabled.
2601 for (ln = 0; ln < 2; ln++) {
2602 val = I915_READ(MG_CLKHUB(port, ln));
2603 if (link_clock < 300000)
2604 val |= CFG_LOW_RATE_LKREN_EN;
2606 val &= ~CFG_LOW_RATE_LKREN_EN;
2607 I915_WRITE(MG_CLKHUB(port, ln), val);
2610 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2611 for (ln = 0; ln < 2; ln++) {
2612 val = I915_READ(MG_TX1_DCC(port, ln));
2613 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2614 if (link_clock <= 500000) {
2615 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2617 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2618 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2620 I915_WRITE(MG_TX1_DCC(port, ln), val);
2622 val = I915_READ(MG_TX2_DCC(port, ln));
2623 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2624 if (link_clock <= 500000) {
2625 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2627 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2628 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2630 I915_WRITE(MG_TX2_DCC(port, ln), val);
2633 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2634 for (ln = 0; ln < 2; ln++) {
2635 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2636 val |= CRI_CALCINIT;
2637 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2639 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2640 val |= CRI_CALCINIT;
2641 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2645 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2648 enum intel_output_type type)
2650 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651 enum port port = encoder->port;
2653 if (intel_port_is_combophy(dev_priv, port))
2654 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2656 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2659 static uint32_t translate_signal_level(int signal_levels)
2663 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2664 if (index_to_dp_signal_levels[i] == signal_levels)
2668 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2674 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2676 uint8_t train_set = intel_dp->train_set[0];
2677 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2678 DP_TRAIN_PRE_EMPHASIS_MASK);
2680 return translate_signal_level(signal_levels);
2683 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2685 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2686 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2687 struct intel_encoder *encoder = &dport->base;
2688 int level = intel_ddi_dp_level(intel_dp);
2690 if (IS_ICELAKE(dev_priv))
2691 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2692 level, encoder->type);
2693 else if (IS_CANNONLAKE(dev_priv))
2694 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2696 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2701 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2703 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2704 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2705 struct intel_encoder *encoder = &dport->base;
2706 int level = intel_ddi_dp_level(intel_dp);
2708 if (IS_GEN9_BC(dev_priv))
2709 skl_ddi_set_iboost(encoder, level, encoder->type);
2711 return DDI_BUF_TRANS_SELECT(level);
2715 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2718 if (intel_port_is_combophy(dev_priv, port)) {
2719 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2720 } else if (intel_port_is_tc(dev_priv, port)) {
2721 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2723 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2729 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2730 const struct intel_crtc_state *crtc_state)
2732 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2733 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2734 enum port port = encoder->port;
2737 mutex_lock(&dev_priv->dpll_lock);
2739 val = I915_READ(DPCLKA_CFGCR0_ICL);
2740 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2742 if (intel_port_is_combophy(dev_priv, port)) {
2743 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2744 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2745 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2746 POSTING_READ(DPCLKA_CFGCR0_ICL);
2749 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2750 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2752 mutex_unlock(&dev_priv->dpll_lock);
2755 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2758 enum port port = encoder->port;
2761 mutex_lock(&dev_priv->dpll_lock);
2763 val = I915_READ(DPCLKA_CFGCR0_ICL);
2764 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2765 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2767 mutex_unlock(&dev_priv->dpll_lock);
2770 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2772 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2776 bool ddi_clk_needed;
2779 * In case of DP MST, we sanitize the primary encoder only, not the
2782 if (encoder->type == INTEL_OUTPUT_DP_MST)
2785 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2789 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2791 * In the unlikely case that BIOS enables DP in MST mode, just
2792 * warn since our MST HW readout is incomplete.
2794 if (WARN_ON(is_mst))
2798 port_mask = BIT(encoder->port);
2799 ddi_clk_needed = encoder->base.crtc;
2801 if (encoder->type == INTEL_OUTPUT_DSI) {
2802 struct intel_encoder *other_encoder;
2804 port_mask = intel_dsi_encoder_ports(encoder);
2806 * Sanity check that we haven't incorrectly registered another
2807 * encoder using any of the ports of this DSI encoder.
2809 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2810 if (other_encoder == encoder)
2813 if (WARN_ON(port_mask & BIT(other_encoder->port)))
2817 * DSI ports should have their DDI clock ungated when disabled
2818 * and gated when enabled.
2820 ddi_clk_needed = !encoder->base.crtc;
2823 val = I915_READ(DPCLKA_CFGCR0_ICL);
2824 for_each_port_masked(port, port_mask) {
2825 bool ddi_clk_ungated = !(val &
2826 icl_dpclka_cfgcr0_clk_off(dev_priv,
2829 if (ddi_clk_needed == ddi_clk_ungated)
2833 * Punt on the case now where clock is gated, but it would
2834 * be needed by the port. Something else is really broken then.
2836 if (WARN_ON(ddi_clk_needed))
2839 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2841 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2842 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2846 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2847 const struct intel_crtc_state *crtc_state)
2849 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2850 enum port port = encoder->port;
2852 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2857 mutex_lock(&dev_priv->dpll_lock);
2859 if (IS_ICELAKE(dev_priv)) {
2860 if (!intel_port_is_combophy(dev_priv, port))
2861 I915_WRITE(DDI_CLK_SEL(port),
2862 icl_pll_to_ddi_pll_sel(encoder, crtc_state));
2863 } else if (IS_CANNONLAKE(dev_priv)) {
2864 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2865 val = I915_READ(DPCLKA_CFGCR0);
2866 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2867 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2868 I915_WRITE(DPCLKA_CFGCR0, val);
2871 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2872 * This step and the step before must be done with separate
2875 val = I915_READ(DPCLKA_CFGCR0);
2876 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2877 I915_WRITE(DPCLKA_CFGCR0, val);
2878 } else if (IS_GEN9_BC(dev_priv)) {
2879 /* DDI -> PLL mapping */
2880 val = I915_READ(DPLL_CTRL2);
2882 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2883 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2884 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2885 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2887 I915_WRITE(DPLL_CTRL2, val);
2889 } else if (INTEL_GEN(dev_priv) < 9) {
2890 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2893 mutex_unlock(&dev_priv->dpll_lock);
2896 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2898 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2899 enum port port = encoder->port;
2901 if (IS_ICELAKE(dev_priv)) {
2902 if (!intel_port_is_combophy(dev_priv, port))
2903 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2904 } else if (IS_CANNONLAKE(dev_priv)) {
2905 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2906 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2907 } else if (IS_GEN9_BC(dev_priv)) {
2908 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2909 DPLL_CTRL2_DDI_CLK_OFF(port));
2910 } else if (INTEL_GEN(dev_priv) < 9) {
2911 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2915 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2917 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2918 enum port port = dig_port->base.port;
2919 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2920 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2924 if (tc_port == PORT_TC_NONE)
2927 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2928 val = I915_READ(mg_regs[i]);
2929 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2930 MG_DP_MODE_CFG_TRPWR_GATING |
2931 MG_DP_MODE_CFG_CLNPWR_GATING |
2932 MG_DP_MODE_CFG_DIGPWR_GATING |
2933 MG_DP_MODE_CFG_GAONPWR_GATING;
2934 I915_WRITE(mg_regs[i], val);
2937 val = I915_READ(MG_MISC_SUS0(tc_port));
2938 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2939 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2940 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2941 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2942 MG_MISC_SUS0_CFG_TRPWR_GATING |
2943 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2944 MG_MISC_SUS0_CFG_DGPWR_GATING;
2945 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2948 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2950 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2951 enum port port = dig_port->base.port;
2952 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2953 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2957 if (tc_port == PORT_TC_NONE)
2960 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2961 val = I915_READ(mg_regs[i]);
2962 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2963 MG_DP_MODE_CFG_TRPWR_GATING |
2964 MG_DP_MODE_CFG_CLNPWR_GATING |
2965 MG_DP_MODE_CFG_DIGPWR_GATING |
2966 MG_DP_MODE_CFG_GAONPWR_GATING);
2967 I915_WRITE(mg_regs[i], val);
2970 val = I915_READ(MG_MISC_SUS0(tc_port));
2971 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2972 MG_MISC_SUS0_CFG_TR2PWR_GATING |
2973 MG_MISC_SUS0_CFG_CL2PWR_GATING |
2974 MG_MISC_SUS0_CFG_GAONPWR_GATING |
2975 MG_MISC_SUS0_CFG_TRPWR_GATING |
2976 MG_MISC_SUS0_CFG_CL1PWR_GATING |
2977 MG_MISC_SUS0_CFG_DGPWR_GATING);
2978 I915_WRITE(MG_MISC_SUS0(tc_port), val);
2981 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
2983 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2984 enum port port = intel_dig_port->base.port;
2985 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2986 u32 ln0, ln1, lane_info;
2988 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
2991 ln0 = I915_READ(MG_DP_MODE(port, 0));
2992 ln1 = I915_READ(MG_DP_MODE(port, 1));
2994 switch (intel_dig_port->tc_type) {
2996 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2997 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2999 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3000 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3001 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3003 switch (lane_info) {
3008 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3011 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3012 MG_DP_MODE_CFG_DP_X2_MODE;
3015 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3018 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3019 MG_DP_MODE_CFG_DP_X2_MODE;
3022 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3023 MG_DP_MODE_CFG_DP_X2_MODE;
3024 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3025 MG_DP_MODE_CFG_DP_X2_MODE;
3028 MISSING_CASE(lane_info);
3032 case TC_PORT_LEGACY:
3033 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3034 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3038 MISSING_CASE(intel_dig_port->tc_type);
3042 I915_WRITE(MG_DP_MODE(port, 0), ln0);
3043 I915_WRITE(MG_DP_MODE(port, 1), ln1);
3046 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3047 const struct intel_crtc_state *crtc_state)
3049 if (!crtc_state->fec_enable)
3052 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3053 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3056 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3057 const struct intel_crtc_state *crtc_state)
3059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3060 enum port port = encoder->port;
3063 if (!crtc_state->fec_enable)
3066 val = I915_READ(DP_TP_CTL(port));
3067 val |= DP_TP_CTL_FEC_ENABLE;
3068 I915_WRITE(DP_TP_CTL(port), val);
3070 if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3071 DP_TP_STATUS_FEC_ENABLE_LIVE,
3072 DP_TP_STATUS_FEC_ENABLE_LIVE,
3074 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3077 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3078 const struct intel_crtc_state *crtc_state)
3080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3081 enum port port = encoder->port;
3084 if (!crtc_state->fec_enable)
3087 val = I915_READ(DP_TP_CTL(port));
3088 val &= ~DP_TP_CTL_FEC_ENABLE;
3089 I915_WRITE(DP_TP_CTL(port), val);
3090 POSTING_READ(DP_TP_CTL(port));
3093 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3094 const struct intel_crtc_state *crtc_state,
3095 const struct drm_connector_state *conn_state)
3097 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3099 enum port port = encoder->port;
3100 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3101 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3102 int level = intel_ddi_dp_level(intel_dp);
3104 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3106 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3107 crtc_state->lane_count, is_mst);
3109 intel_edp_panel_on(intel_dp);
3111 intel_ddi_clk_select(encoder, crtc_state);
3113 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3115 icl_program_mg_dp_mode(dig_port);
3116 icl_disable_phy_clock_gating(dig_port);
3118 if (IS_ICELAKE(dev_priv))
3119 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3120 level, encoder->type);
3121 else if (IS_CANNONLAKE(dev_priv))
3122 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3123 else if (IS_GEN9_LP(dev_priv))
3124 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3126 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3128 intel_ddi_init_dp_buf_reg(encoder);
3130 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3131 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3133 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3134 intel_dp_start_link_train(intel_dp);
3135 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3136 intel_dp_stop_link_train(intel_dp);
3138 intel_ddi_enable_fec(encoder, crtc_state);
3140 icl_enable_phy_clock_gating(dig_port);
3143 intel_ddi_enable_pipe_clock(crtc_state);
3145 intel_dsc_enable(encoder, crtc_state);
3148 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3149 const struct intel_crtc_state *crtc_state,
3150 const struct drm_connector_state *conn_state)
3152 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3153 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3155 enum port port = encoder->port;
3156 int level = intel_ddi_hdmi_level(dev_priv, port);
3157 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3159 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3160 intel_ddi_clk_select(encoder, crtc_state);
3162 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3164 icl_program_mg_dp_mode(dig_port);
3165 icl_disable_phy_clock_gating(dig_port);
3167 if (IS_ICELAKE(dev_priv))
3168 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3169 level, INTEL_OUTPUT_HDMI);
3170 else if (IS_CANNONLAKE(dev_priv))
3171 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3172 else if (IS_GEN9_LP(dev_priv))
3173 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3175 intel_prepare_hdmi_ddi_buffers(encoder, level);
3177 icl_enable_phy_clock_gating(dig_port);
3179 if (IS_GEN9_BC(dev_priv))
3180 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3182 intel_ddi_enable_pipe_clock(crtc_state);
3184 intel_dig_port->set_infoframes(encoder,
3185 crtc_state->has_infoframe,
3186 crtc_state, conn_state);
3189 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3190 const struct intel_crtc_state *crtc_state,
3191 const struct drm_connector_state *conn_state)
3193 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195 enum pipe pipe = crtc->pipe;
3198 * When called from DP MST code:
3199 * - conn_state will be NULL
3200 * - encoder will be the main encoder (ie. mst->primary)
3201 * - the main connector associated with this port
3202 * won't be active or linked to a crtc
3203 * - crtc_state will be the state of the first stream to
3204 * be activated on this port, and it may not be the same
3205 * stream that will be deactivated last, but each stream
3206 * should have a state that is identical when it comes to
3207 * the DP link parameteres
3210 WARN_ON(crtc_state->has_pch_encoder);
3212 if (INTEL_GEN(dev_priv) >= 11)
3213 icl_map_plls_to_ports(encoder, crtc_state);
3215 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3217 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3218 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3220 struct intel_lspcon *lspcon =
3221 enc_to_intel_lspcon(&encoder->base);
3223 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3224 if (lspcon->active) {
3225 struct intel_digital_port *dig_port =
3226 enc_to_dig_port(&encoder->base);
3228 dig_port->set_infoframes(encoder,
3229 crtc_state->has_infoframe,
3230 crtc_state, conn_state);
3235 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3236 const struct intel_crtc_state *crtc_state)
3238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3239 enum port port = encoder->port;
3243 val = I915_READ(DDI_BUF_CTL(port));
3244 if (val & DDI_BUF_CTL_ENABLE) {
3245 val &= ~DDI_BUF_CTL_ENABLE;
3246 I915_WRITE(DDI_BUF_CTL(port), val);
3250 val = I915_READ(DP_TP_CTL(port));
3251 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3252 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3253 I915_WRITE(DP_TP_CTL(port), val);
3255 /* Disable FEC in DP Sink */
3256 intel_ddi_disable_fec_state(encoder, crtc_state);
3259 intel_wait_ddi_buf_idle(dev_priv, port);
3262 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3263 const struct intel_crtc_state *old_crtc_state,
3264 const struct drm_connector_state *old_conn_state)
3266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3267 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3268 struct intel_dp *intel_dp = &dig_port->dp;
3269 bool is_mst = intel_crtc_has_type(old_crtc_state,
3270 INTEL_OUTPUT_DP_MST);
3273 intel_ddi_disable_pipe_clock(old_crtc_state);
3275 * Power down sink before disabling the port, otherwise we end
3276 * up getting interrupts from the sink on detecting link loss.
3278 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3281 intel_disable_ddi_buf(encoder, old_crtc_state);
3283 intel_edp_panel_vdd_on(intel_dp);
3284 intel_edp_panel_off(intel_dp);
3286 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3288 intel_ddi_clk_disable(encoder);
3291 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3292 const struct intel_crtc_state *old_crtc_state,
3293 const struct drm_connector_state *old_conn_state)
3295 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3296 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3297 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3299 dig_port->set_infoframes(encoder, false,
3300 old_crtc_state, old_conn_state);
3302 intel_ddi_disable_pipe_clock(old_crtc_state);
3304 intel_disable_ddi_buf(encoder, old_crtc_state);
3306 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3308 intel_ddi_clk_disable(encoder);
3310 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3313 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3314 const struct intel_crtc_state *old_crtc_state,
3315 const struct drm_connector_state *old_conn_state)
3317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3320 * When called from DP MST code:
3321 * - old_conn_state will be NULL
3322 * - encoder will be the main encoder (ie. mst->primary)
3323 * - the main connector associated with this port
3324 * won't be active or linked to a crtc
3325 * - old_crtc_state will be the state of the last stream to
3326 * be deactivated on this port, and it may not be the same
3327 * stream that was activated last, but each stream
3328 * should have a state that is identical when it comes to
3329 * the DP link parameteres
3332 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3333 intel_ddi_post_disable_hdmi(encoder,
3334 old_crtc_state, old_conn_state);
3336 intel_ddi_post_disable_dp(encoder,
3337 old_crtc_state, old_conn_state);
3339 if (INTEL_GEN(dev_priv) >= 11)
3340 icl_unmap_plls_to_ports(encoder);
3343 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3344 const struct intel_crtc_state *old_crtc_state,
3345 const struct drm_connector_state *old_conn_state)
3347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3351 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3352 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3353 * step 13 is the correct place for it. Step 18 is where it was
3354 * originally before the BUN.
3356 val = I915_READ(FDI_RX_CTL(PIPE_A));
3357 val &= ~FDI_RX_ENABLE;
3358 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3360 intel_disable_ddi_buf(encoder, old_crtc_state);
3361 intel_ddi_clk_disable(encoder);
3363 val = I915_READ(FDI_RX_MISC(PIPE_A));
3364 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3365 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3366 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3368 val = I915_READ(FDI_RX_CTL(PIPE_A));
3370 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3372 val = I915_READ(FDI_RX_CTL(PIPE_A));
3373 val &= ~FDI_RX_PLL_ENABLE;
3374 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3377 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3378 const struct intel_crtc_state *crtc_state,
3379 const struct drm_connector_state *conn_state)
3381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3382 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3383 enum port port = encoder->port;
3385 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3386 intel_dp_stop_link_train(intel_dp);
3388 intel_edp_backlight_on(crtc_state, conn_state);
3389 intel_psr_enable(intel_dp, crtc_state);
3390 intel_edp_drrs_enable(intel_dp, crtc_state);
3392 if (crtc_state->has_audio)
3393 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3397 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3400 static const i915_reg_t regs[] = {
3401 [PORT_A] = CHICKEN_TRANS_EDP,
3402 [PORT_B] = CHICKEN_TRANS_A,
3403 [PORT_C] = CHICKEN_TRANS_B,
3404 [PORT_D] = CHICKEN_TRANS_C,
3405 [PORT_E] = CHICKEN_TRANS_A,
3408 WARN_ON(INTEL_GEN(dev_priv) < 9);
3410 if (WARN_ON(port < PORT_A || port > PORT_E))
3416 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3417 const struct intel_crtc_state *crtc_state,
3418 const struct drm_connector_state *conn_state)
3420 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3421 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3422 struct drm_connector *connector = conn_state->connector;
3423 enum port port = encoder->port;
3425 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3426 crtc_state->hdmi_high_tmds_clock_ratio,
3427 crtc_state->hdmi_scrambling))
3428 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3429 connector->base.id, connector->name);
3431 /* Display WA #1143: skl,kbl,cfl */
3432 if (IS_GEN9_BC(dev_priv)) {
3434 * For some reason these chicken bits have been
3435 * stuffed into a transcoder register, event though
3436 * the bits affect a specific DDI port rather than
3437 * a specific transcoder.
3439 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3442 val = I915_READ(reg);
3445 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3446 DDIE_TRAINING_OVERRIDE_VALUE;
3448 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3449 DDI_TRAINING_OVERRIDE_VALUE;
3451 I915_WRITE(reg, val);
3457 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3458 DDIE_TRAINING_OVERRIDE_VALUE);
3460 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3461 DDI_TRAINING_OVERRIDE_VALUE);
3463 I915_WRITE(reg, val);
3466 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3467 * are ignored so nothing special needs to be done besides
3468 * enabling the port.
3470 I915_WRITE(DDI_BUF_CTL(port),
3471 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3473 if (crtc_state->has_audio)
3474 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3477 static void intel_enable_ddi(struct intel_encoder *encoder,
3478 const struct intel_crtc_state *crtc_state,
3479 const struct drm_connector_state *conn_state)
3481 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3482 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3484 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3486 /* Enable hdcp if it's desired */
3487 if (conn_state->content_protection ==
3488 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3489 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3492 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3493 const struct intel_crtc_state *old_crtc_state,
3494 const struct drm_connector_state *old_conn_state)
3496 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3498 intel_dp->link_trained = false;
3500 if (old_crtc_state->has_audio)
3501 intel_audio_codec_disable(encoder,
3502 old_crtc_state, old_conn_state);
3504 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3505 intel_psr_disable(intel_dp, old_crtc_state);
3506 intel_edp_backlight_off(old_conn_state);
3507 /* Disable the decompression in DP Sink */
3508 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3512 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3513 const struct intel_crtc_state *old_crtc_state,
3514 const struct drm_connector_state *old_conn_state)
3516 struct drm_connector *connector = old_conn_state->connector;
3518 if (old_crtc_state->has_audio)
3519 intel_audio_codec_disable(encoder,
3520 old_crtc_state, old_conn_state);
3522 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3524 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3525 connector->base.id, connector->name);
3528 static void intel_disable_ddi(struct intel_encoder *encoder,
3529 const struct intel_crtc_state *old_crtc_state,
3530 const struct drm_connector_state *old_conn_state)
3532 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3534 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3535 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3537 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3540 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *pipe_config,
3544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3545 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3546 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3547 u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3548 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3550 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3551 switch (pipe_config->lane_count) {
3553 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3554 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3557 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3558 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3561 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3564 MISSING_CASE(pipe_config->lane_count);
3566 I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3570 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3571 const struct intel_crtc_state *crtc_state,
3572 const struct drm_connector_state *conn_state)
3574 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3575 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3576 enum port port = encoder->port;
3578 if (intel_crtc_has_dp_encoder(crtc_state) ||
3579 intel_port_is_tc(dev_priv, encoder->port))
3580 intel_display_power_get(dev_priv,
3581 intel_ddi_main_link_aux_domain(dig_port));
3583 if (IS_GEN9_LP(dev_priv))
3584 bxt_ddi_phy_set_lane_optim_mask(encoder,
3585 crtc_state->lane_lat_optim_mask);
3588 * Program the lane count for static/dynamic connections on Type-C ports.
3589 * Skip this step for TBT.
3591 if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3592 dig_port->tc_type == TC_PORT_TBT)
3595 intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3599 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3600 const struct intel_crtc_state *crtc_state,
3601 const struct drm_connector_state *conn_state)
3603 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3604 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3606 if (intel_crtc_has_dp_encoder(crtc_state) ||
3607 intel_port_is_tc(dev_priv, encoder->port))
3608 intel_display_power_put(dev_priv,
3609 intel_ddi_main_link_aux_domain(dig_port));
3612 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3614 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3615 struct drm_i915_private *dev_priv =
3616 to_i915(intel_dig_port->base.base.dev);
3617 enum port port = intel_dig_port->base.port;
3621 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3622 val = I915_READ(DDI_BUF_CTL(port));
3623 if (val & DDI_BUF_CTL_ENABLE) {
3624 val &= ~DDI_BUF_CTL_ENABLE;
3625 I915_WRITE(DDI_BUF_CTL(port), val);
3629 val = I915_READ(DP_TP_CTL(port));
3630 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3631 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3632 I915_WRITE(DP_TP_CTL(port), val);
3633 POSTING_READ(DP_TP_CTL(port));
3636 intel_wait_ddi_buf_idle(dev_priv, port);
3639 val = DP_TP_CTL_ENABLE |
3640 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3641 if (intel_dp->link_mst)
3642 val |= DP_TP_CTL_MODE_MST;
3644 val |= DP_TP_CTL_MODE_SST;
3645 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3646 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3648 I915_WRITE(DP_TP_CTL(port), val);
3649 POSTING_READ(DP_TP_CTL(port));
3651 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3652 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3653 POSTING_READ(DDI_BUF_CTL(port));
3658 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3659 enum transcoder cpu_transcoder)
3661 if (cpu_transcoder == TRANSCODER_EDP)
3664 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3667 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3668 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3671 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3672 struct intel_crtc_state *crtc_state)
3674 if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3675 crtc_state->min_voltage_level = 1;
3676 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3677 crtc_state->min_voltage_level = 2;
3680 void intel_ddi_get_config(struct intel_encoder *encoder,
3681 struct intel_crtc_state *pipe_config)
3683 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3684 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3685 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3686 struct intel_digital_port *intel_dig_port;
3687 u32 temp, flags = 0;
3689 /* XXX: DSI transcoder paranoia */
3690 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3693 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3694 if (temp & TRANS_DDI_PHSYNC)
3695 flags |= DRM_MODE_FLAG_PHSYNC;
3697 flags |= DRM_MODE_FLAG_NHSYNC;
3698 if (temp & TRANS_DDI_PVSYNC)
3699 flags |= DRM_MODE_FLAG_PVSYNC;
3701 flags |= DRM_MODE_FLAG_NVSYNC;
3703 pipe_config->base.adjusted_mode.flags |= flags;
3705 switch (temp & TRANS_DDI_BPC_MASK) {
3706 case TRANS_DDI_BPC_6:
3707 pipe_config->pipe_bpp = 18;
3709 case TRANS_DDI_BPC_8:
3710 pipe_config->pipe_bpp = 24;
3712 case TRANS_DDI_BPC_10:
3713 pipe_config->pipe_bpp = 30;
3715 case TRANS_DDI_BPC_12:
3716 pipe_config->pipe_bpp = 36;
3722 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3723 case TRANS_DDI_MODE_SELECT_HDMI:
3724 pipe_config->has_hdmi_sink = true;
3725 intel_dig_port = enc_to_dig_port(&encoder->base);
3727 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3728 pipe_config->has_infoframe = true;
3730 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3731 TRANS_DDI_HDMI_SCRAMBLING_MASK)
3732 pipe_config->hdmi_scrambling = true;
3733 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3734 pipe_config->hdmi_high_tmds_clock_ratio = true;
3736 case TRANS_DDI_MODE_SELECT_DVI:
3737 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3738 pipe_config->lane_count = 4;
3740 case TRANS_DDI_MODE_SELECT_FDI:
3741 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3743 case TRANS_DDI_MODE_SELECT_DP_SST:
3744 if (encoder->type == INTEL_OUTPUT_EDP)
3745 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3747 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3748 pipe_config->lane_count =
3749 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3750 intel_dp_get_m_n(intel_crtc, pipe_config);
3752 case TRANS_DDI_MODE_SELECT_DP_MST:
3753 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3754 pipe_config->lane_count =
3755 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3756 intel_dp_get_m_n(intel_crtc, pipe_config);
3762 pipe_config->has_audio =
3763 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3765 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3766 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3768 * This is a big fat ugly hack.
3770 * Some machines in UEFI boot mode provide us a VBT that has 18
3771 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3772 * unknown we fail to light up. Yet the same BIOS boots up with
3773 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3774 * max, not what it tells us to use.
3776 * Note: This will still be broken if the eDP panel is not lit
3777 * up by the BIOS, and thus we can't get the mode at module
3780 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3781 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3782 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3785 intel_ddi_clock_get(encoder, pipe_config);
3787 if (IS_GEN9_LP(dev_priv))
3788 pipe_config->lane_lat_optim_mask =
3789 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3791 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3794 static enum intel_output_type
3795 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3796 struct intel_crtc_state *crtc_state,
3797 struct drm_connector_state *conn_state)
3799 switch (conn_state->connector->connector_type) {
3800 case DRM_MODE_CONNECTOR_HDMIA:
3801 return INTEL_OUTPUT_HDMI;
3802 case DRM_MODE_CONNECTOR_eDP:
3803 return INTEL_OUTPUT_EDP;
3804 case DRM_MODE_CONNECTOR_DisplayPort:
3805 return INTEL_OUTPUT_DP;
3807 MISSING_CASE(conn_state->connector->connector_type);
3808 return INTEL_OUTPUT_UNUSED;
3812 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3813 struct intel_crtc_state *pipe_config,
3814 struct drm_connector_state *conn_state)
3816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3817 enum port port = encoder->port;
3821 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3823 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3824 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3826 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3828 if (IS_GEN9_LP(dev_priv) && ret)
3829 pipe_config->lane_lat_optim_mask =
3830 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3832 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3838 static const struct drm_encoder_funcs intel_ddi_funcs = {
3839 .reset = intel_dp_encoder_reset,
3840 .destroy = intel_dp_encoder_destroy,
3843 static struct intel_connector *
3844 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3846 struct intel_connector *connector;
3847 enum port port = intel_dig_port->base.port;
3849 connector = intel_connector_alloc();
3853 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3854 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3862 static int modeset_pipe(struct drm_crtc *crtc,
3863 struct drm_modeset_acquire_ctx *ctx)
3865 struct drm_atomic_state *state;
3866 struct drm_crtc_state *crtc_state;
3869 state = drm_atomic_state_alloc(crtc->dev);
3873 state->acquire_ctx = ctx;
3875 crtc_state = drm_atomic_get_crtc_state(state, crtc);
3876 if (IS_ERR(crtc_state)) {
3877 ret = PTR_ERR(crtc_state);
3881 crtc_state->mode_changed = true;
3883 ret = drm_atomic_add_affected_connectors(state, crtc);
3887 ret = drm_atomic_add_affected_planes(state, crtc);
3891 ret = drm_atomic_commit(state);
3898 drm_atomic_state_put(state);
3903 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3904 struct drm_modeset_acquire_ctx *ctx)
3906 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3907 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3908 struct intel_connector *connector = hdmi->attached_connector;
3909 struct i2c_adapter *adapter =
3910 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3911 struct drm_connector_state *conn_state;
3912 struct intel_crtc_state *crtc_state;
3913 struct intel_crtc *crtc;
3917 if (!connector || connector->base.status != connector_status_connected)
3920 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3925 conn_state = connector->base.state;
3927 crtc = to_intel_crtc(conn_state->crtc);
3931 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3935 crtc_state = to_intel_crtc_state(crtc->base.state);
3937 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3939 if (!crtc_state->base.active)
3942 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3943 !crtc_state->hdmi_scrambling)
3946 if (conn_state->commit &&
3947 !try_wait_for_completion(&conn_state->commit->hw_done))
3950 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3952 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
3956 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3957 crtc_state->hdmi_high_tmds_clock_ratio &&
3958 !!(config & SCDC_SCRAMBLING_ENABLE) ==
3959 crtc_state->hdmi_scrambling)
3963 * HDMI 2.0 says that one should not send scrambled data
3964 * prior to configuring the sink scrambling, and that
3965 * TMDS clock/data transmission should be suspended when
3966 * changing the TMDS clock rate in the sink. So let's
3967 * just do a full modeset here, even though some sinks
3968 * would be perfectly happy if were to just reconfigure
3969 * the SCDC settings on the fly.
3971 return modeset_pipe(&crtc->base, ctx);
3974 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
3975 struct intel_connector *connector)
3977 struct drm_modeset_acquire_ctx ctx;
3981 changed = intel_encoder_hotplug(encoder, connector);
3983 drm_modeset_acquire_init(&ctx, 0);
3986 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3987 ret = intel_hdmi_reset_link(encoder, &ctx);
3989 ret = intel_dp_retrain_link(encoder, &ctx);
3991 if (ret == -EDEADLK) {
3992 drm_modeset_backoff(&ctx);
3999 drm_modeset_drop_locks(&ctx);
4000 drm_modeset_acquire_fini(&ctx);
4001 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4006 static struct intel_connector *
4007 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4009 struct intel_connector *connector;
4010 enum port port = intel_dig_port->base.port;
4012 connector = intel_connector_alloc();
4016 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4017 intel_hdmi_init_connector(intel_dig_port, connector);
4022 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4024 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4026 if (dport->base.port != PORT_A)
4029 if (dport->saved_port_bits & DDI_A_4_LANES)
4032 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4033 * supported configuration
4035 if (IS_GEN9_LP(dev_priv))
4038 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4039 * one who does also have a full A/E split called
4040 * DDI_F what makes DDI_E useless. However for this
4041 * case let's trust VBT info.
4043 if (IS_CANNONLAKE(dev_priv) &&
4044 !intel_bios_is_port_present(dev_priv, PORT_E))
4051 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4053 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4054 enum port port = intel_dport->base.port;
4057 if (INTEL_GEN(dev_priv) >= 11)
4060 if (port == PORT_A || port == PORT_E) {
4061 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4062 max_lanes = port == PORT_A ? 4 : 0;
4064 /* Both A and E share 2 lanes */
4069 * Some BIOS might fail to set this bit on port A if eDP
4070 * wasn't lit up at boot. Force this bit set when needed
4071 * so we use the proper lane count for our calculations.
4073 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4074 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4075 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4082 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4084 struct intel_digital_port *intel_dig_port;
4085 struct intel_encoder *intel_encoder;
4086 struct drm_encoder *encoder;
4087 bool init_hdmi, init_dp, init_lspcon = false;
4091 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
4092 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
4093 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
4095 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4097 * Lspcon device needs to be driven with DP connector
4098 * with special detection sequence. So make sure DP
4099 * is initialized before lspcon.
4104 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4107 if (!init_dp && !init_hdmi) {
4108 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4113 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4114 if (!intel_dig_port)
4117 intel_encoder = &intel_dig_port->base;
4118 encoder = &intel_encoder->base;
4120 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4121 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4123 intel_encoder->hotplug = intel_ddi_hotplug;
4124 intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4125 intel_encoder->compute_config = intel_ddi_compute_config;
4126 intel_encoder->enable = intel_enable_ddi;
4127 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4128 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4129 intel_encoder->pre_enable = intel_ddi_pre_enable;
4130 intel_encoder->disable = intel_disable_ddi;
4131 intel_encoder->post_disable = intel_ddi_post_disable;
4132 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4133 intel_encoder->get_config = intel_ddi_get_config;
4134 intel_encoder->suspend = intel_dp_encoder_suspend;
4135 intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4136 intel_encoder->type = INTEL_OUTPUT_DDI;
4137 intel_encoder->power_domain = intel_port_to_power_domain(port);
4138 intel_encoder->port = port;
4139 intel_encoder->cloneable = 0;
4140 for_each_pipe(dev_priv, pipe)
4141 intel_encoder->crtc_mask |= BIT(pipe);
4143 if (INTEL_GEN(dev_priv) >= 11)
4144 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4145 DDI_BUF_PORT_REVERSAL;
4147 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4148 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4149 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4150 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4151 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4155 intel_dig_port->ddi_io_power_domain =
4156 POWER_DOMAIN_PORT_DDI_A_IO;
4159 intel_dig_port->ddi_io_power_domain =
4160 POWER_DOMAIN_PORT_DDI_B_IO;
4163 intel_dig_port->ddi_io_power_domain =
4164 POWER_DOMAIN_PORT_DDI_C_IO;
4167 intel_dig_port->ddi_io_power_domain =
4168 POWER_DOMAIN_PORT_DDI_D_IO;
4171 intel_dig_port->ddi_io_power_domain =
4172 POWER_DOMAIN_PORT_DDI_E_IO;
4175 intel_dig_port->ddi_io_power_domain =
4176 POWER_DOMAIN_PORT_DDI_F_IO;
4183 if (!intel_ddi_init_dp_connector(intel_dig_port))
4186 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4189 /* In theory we don't need the encoder->type check, but leave it just in
4190 * case we have some really bad VBTs... */
4191 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4192 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4197 if (lspcon_init(intel_dig_port))
4198 /* TODO: handle hdmi info frame part */
4199 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4203 * LSPCON init faied, but DP init was success, so
4204 * lets try to drive as DP++ port.
4206 DRM_ERROR("LSPCON init failed on port %c\n",
4210 intel_infoframe_init(intel_dig_port);
4214 drm_encoder_cleanup(encoder);
4215 kfree(intel_dig_port);