2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
47 static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
59 static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
75 static const u32 bdw_ddi_translations_edp[] = {
76 0x00FFFFFF, 0x00000012, /* eDP parameters */
77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00AAAFFF, 0x000E000A,
80 0x00FFFFFF, 0x00020011,
81 0x00DB6FFF, 0x0005000F,
82 0x00BEEFFF, 0x000A000C,
83 0x00FFFFFF, 0x0005000F,
84 0x00DB6FFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
88 static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x80B2CFFF, 0x001B0002,
93 0x00FFFFFF, 0x000E000A,
94 0x00D75FFF, 0x00180004,
95 0x80CB2FFF, 0x001B0002,
96 0x00F7DFFF, 0x00180004,
97 0x80D75FFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
101 static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
116 struct drm_encoder *encoder = &intel_encoder->base;
117 int type = intel_encoder->type;
119 if (type == INTEL_OUTPUT_DP_MST) {
120 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
121 return intel_dig_port->port;
122 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
123 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
124 struct intel_digital_port *intel_dig_port =
125 enc_to_dig_port(encoder);
126 return intel_dig_port->port;
128 } else if (type == INTEL_OUTPUT_ANALOG) {
132 DRM_ERROR("Invalid DDI encoder type %d\n", type);
138 * Starting with Haswell, DDI port buffers must be programmed with correct
139 * values in advance. The buffer values are different for FDI and DP modes,
140 * but the HDMI/DVI fields are shared among those. So we program the DDI
141 * in either FDI or DP modes only, as HDMI connections will work with both
144 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
146 struct drm_i915_private *dev_priv = dev->dev_private;
149 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
150 const u32 *ddi_translations_fdi;
151 const u32 *ddi_translations_dp;
152 const u32 *ddi_translations_edp;
153 const u32 *ddi_translations;
155 if (IS_BROADWELL(dev)) {
156 ddi_translations_fdi = bdw_ddi_translations_fdi;
157 ddi_translations_dp = bdw_ddi_translations_dp;
158 ddi_translations_edp = bdw_ddi_translations_edp;
159 } else if (IS_HASWELL(dev)) {
160 ddi_translations_fdi = hsw_ddi_translations_fdi;
161 ddi_translations_dp = hsw_ddi_translations_dp;
162 ddi_translations_edp = hsw_ddi_translations_dp;
164 WARN(1, "ddi translation table missing\n");
165 ddi_translations_edp = bdw_ddi_translations_dp;
166 ddi_translations_fdi = bdw_ddi_translations_fdi;
167 ddi_translations_dp = bdw_ddi_translations_dp;
172 ddi_translations = ddi_translations_edp;
176 ddi_translations = ddi_translations_dp;
179 if (intel_dp_is_edp(dev, PORT_D))
180 ddi_translations = ddi_translations_edp;
182 ddi_translations = ddi_translations_dp;
185 ddi_translations = ddi_translations_fdi;
191 for (i = 0, reg = DDI_BUF_TRANS(port);
192 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
193 I915_WRITE(reg, ddi_translations[i]);
196 /* Entry 9 is for HDMI: */
197 for (i = 0; i < 2; i++) {
198 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
203 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
204 * mode and port E for FDI.
206 void intel_prepare_ddi(struct drm_device *dev)
213 for (port = PORT_A; port <= PORT_E; port++)
214 intel_prepare_ddi_buffers(dev, port);
217 static const long hsw_ddi_buf_ctl_values[] = {
218 DDI_BUF_EMP_400MV_0DB_HSW,
219 DDI_BUF_EMP_400MV_3_5DB_HSW,
220 DDI_BUF_EMP_400MV_6DB_HSW,
221 DDI_BUF_EMP_400MV_9_5DB_HSW,
222 DDI_BUF_EMP_600MV_0DB_HSW,
223 DDI_BUF_EMP_600MV_3_5DB_HSW,
224 DDI_BUF_EMP_600MV_6DB_HSW,
225 DDI_BUF_EMP_800MV_0DB_HSW,
226 DDI_BUF_EMP_800MV_3_5DB_HSW
229 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
232 uint32_t reg = DDI_BUF_CTL(port);
235 for (i = 0; i < 8; i++) {
237 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
240 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
243 /* Starting with Haswell, different DDI ports can work in FDI mode for
244 * connection to the PCH-located connectors. For this, it is necessary to train
245 * both the DDI port and PCH receiver for the desired DDI buffer settings.
247 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
248 * please note that when FDI mode is active on DDI E, it shares 2 lines with
249 * DDI A (which is used for eDP)
252 void hsw_fdi_link_train(struct drm_crtc *crtc)
254 struct drm_device *dev = crtc->dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
257 u32 temp, i, rx_ctl_val;
259 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
260 * mode set "sequence for CRT port" document:
261 * - TP1 to TP2 time with the default value
264 * WaFDIAutoLinkSetTimingOverrride:hsw
266 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
267 FDI_RX_PWRDN_LANE0_VAL(2) |
268 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
270 /* Enable the PCH Receiver FDI PLL */
271 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
273 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
274 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
275 POSTING_READ(_FDI_RXA_CTL);
278 /* Switch from Rawclk to PCDclk */
279 rx_ctl_val |= FDI_PCDCLK;
280 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
282 /* Configure Port Clock Select */
283 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
284 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
286 /* Start the training iterating through available voltages and emphasis,
287 * testing each value twice. */
288 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
289 /* Configure DP_TP_CTL with auto-training */
290 I915_WRITE(DP_TP_CTL(PORT_E),
291 DP_TP_CTL_FDI_AUTOTRAIN |
292 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
293 DP_TP_CTL_LINK_TRAIN_PAT1 |
296 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
297 * DDI E does not support port reversal, the functionality is
298 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
299 * port reversal bit */
300 I915_WRITE(DDI_BUF_CTL(PORT_E),
302 ((intel_crtc->config.fdi_lanes - 1) << 1) |
303 hsw_ddi_buf_ctl_values[i / 2]);
304 POSTING_READ(DDI_BUF_CTL(PORT_E));
308 /* Program PCH FDI Receiver TU */
309 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
311 /* Enable PCH FDI Receiver with auto-training */
312 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
313 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
314 POSTING_READ(_FDI_RXA_CTL);
316 /* Wait for FDI receiver lane calibration */
319 /* Unset FDI_RX_MISC pwrdn lanes */
320 temp = I915_READ(_FDI_RXA_MISC);
321 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
322 I915_WRITE(_FDI_RXA_MISC, temp);
323 POSTING_READ(_FDI_RXA_MISC);
325 /* Wait for FDI auto training time */
328 temp = I915_READ(DP_TP_STATUS(PORT_E));
329 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
330 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
332 /* Enable normal pixel sending for FDI */
333 I915_WRITE(DP_TP_CTL(PORT_E),
334 DP_TP_CTL_FDI_AUTOTRAIN |
335 DP_TP_CTL_LINK_TRAIN_NORMAL |
336 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
342 temp = I915_READ(DDI_BUF_CTL(PORT_E));
343 temp &= ~DDI_BUF_CTL_ENABLE;
344 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
345 POSTING_READ(DDI_BUF_CTL(PORT_E));
347 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
348 temp = I915_READ(DP_TP_CTL(PORT_E));
349 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
350 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
351 I915_WRITE(DP_TP_CTL(PORT_E), temp);
352 POSTING_READ(DP_TP_CTL(PORT_E));
354 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
356 rx_ctl_val &= ~FDI_RX_ENABLE;
357 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
358 POSTING_READ(_FDI_RXA_CTL);
360 /* Reset FDI_RX_MISC pwrdn lanes */
361 temp = I915_READ(_FDI_RXA_MISC);
362 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
363 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
364 I915_WRITE(_FDI_RXA_MISC, temp);
365 POSTING_READ(_FDI_RXA_MISC);
368 DRM_ERROR("FDI link training failed!\n");
371 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
373 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
374 struct intel_digital_port *intel_dig_port =
375 enc_to_dig_port(&encoder->base);
377 intel_dp->DP = intel_dig_port->saved_port_bits |
378 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
379 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
383 static struct intel_encoder *
384 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
386 struct drm_device *dev = crtc->dev;
387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
388 struct intel_encoder *intel_encoder, *ret = NULL;
389 int num_encoders = 0;
391 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
396 if (num_encoders != 1)
397 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
398 pipe_name(intel_crtc->pipe));
405 #define LC_FREQ_2K (LC_FREQ * 2000)
411 /* Constraints for PLL good behavior */
417 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
423 static unsigned wrpll_get_budget_for_freq(int clock)
497 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
498 unsigned r2, unsigned n2, unsigned p,
499 struct wrpll_rnp *best)
501 uint64_t a, b, c, d, diff, diff_best;
503 /* No best (r,n,p) yet */
512 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
516 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
519 * and we would like delta <= budget.
521 * If the discrepancy is above the PPM-based budget, always prefer to
522 * improve upon the previous solution. However, if you're within the
523 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
525 a = freq2k * budget * p * r2;
526 b = freq2k * budget * best->p * best->r2;
527 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
528 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
529 (LC_FREQ_2K * best->n2));
531 d = 1000000 * diff_best;
533 if (a < c && b < d) {
534 /* If both are above the budget, pick the closer */
535 if (best->p * best->r2 * diff < p * r2 * diff_best) {
540 } else if (a >= c && b < d) {
541 /* If A is below the threshold but B is above it? Update. */
545 } else if (a >= c && b >= d) {
546 /* Both are below the limit, so pick the higher n2/(r2*r2) */
547 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
553 /* Otherwise a < c && b >= d, do nothing */
556 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
559 int refclk = LC_FREQ;
563 wrpll = I915_READ(reg);
564 switch (wrpll & WRPLL_PLL_REF_MASK) {
566 case WRPLL_PLL_NON_SSC:
568 * We could calculate spread here, but our checking
569 * code only cares about 5% accuracy, and spread is a max of
574 case WRPLL_PLL_LCPLL:
578 WARN(1, "bad wrpll refclk\n");
582 r = wrpll & WRPLL_DIVIDER_REF_MASK;
583 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
584 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
586 /* Convert to KHz, p & r have a fixed point portion */
587 return (refclk * n * 100) / (p * r);
590 void intel_ddi_clock_get(struct intel_encoder *encoder,
591 struct intel_crtc_config *pipe_config)
593 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
597 val = pipe_config->ddi_pll_sel;
598 switch (val & PORT_CLK_SEL_MASK) {
599 case PORT_CLK_SEL_LCPLL_810:
602 case PORT_CLK_SEL_LCPLL_1350:
605 case PORT_CLK_SEL_LCPLL_2700:
608 case PORT_CLK_SEL_WRPLL1:
609 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
611 case PORT_CLK_SEL_WRPLL2:
612 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
614 case PORT_CLK_SEL_SPLL:
615 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
616 if (pll == SPLL_PLL_FREQ_810MHz)
618 else if (pll == SPLL_PLL_FREQ_1350MHz)
620 else if (pll == SPLL_PLL_FREQ_2700MHz)
623 WARN(1, "bad spll freq\n");
628 WARN(1, "bad port clock sel\n");
632 pipe_config->port_clock = link_clock * 2;
634 if (pipe_config->has_pch_encoder)
635 pipe_config->adjusted_mode.crtc_clock =
636 intel_dotclock_calculate(pipe_config->port_clock,
637 &pipe_config->fdi_m_n);
638 else if (pipe_config->has_dp_encoder)
639 pipe_config->adjusted_mode.crtc_clock =
640 intel_dotclock_calculate(pipe_config->port_clock,
641 &pipe_config->dp_m_n);
643 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
647 intel_ddi_calculate_wrpll(int clock /* in Hz */,
648 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
652 struct wrpll_rnp best = { 0, 0, 0 };
655 freq2k = clock / 100;
657 budget = wrpll_get_budget_for_freq(clock);
659 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
660 * and directly pass the LC PLL to it. */
661 if (freq2k == 5400000) {
669 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
672 * We want R so that REF_MIN <= Ref <= REF_MAX.
673 * Injecting R2 = 2 * R gives:
674 * REF_MAX * r2 > LC_FREQ * 2 and
675 * REF_MIN * r2 < LC_FREQ * 2
677 * Which means the desired boundaries for r2 are:
678 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
681 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
682 r2 <= LC_FREQ * 2 / REF_MIN;
686 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
688 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
689 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
690 * VCO_MAX * r2 > n2 * LC_FREQ and
691 * VCO_MIN * r2 < n2 * LC_FREQ)
693 * Which means the desired boundaries for n2 are:
694 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
696 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
697 n2 <= VCO_MAX * r2 / LC_FREQ;
700 for (p = P_MIN; p <= P_MAX; p += P_INC)
701 wrpll_update_rnp(freq2k, budget,
712 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
713 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
714 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
717 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
719 struct drm_crtc *crtc = &intel_crtc->base;
720 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
721 int type = intel_encoder->type;
722 int clock = intel_crtc->config.port_clock;
724 intel_put_shared_dpll(intel_crtc);
726 if (type == INTEL_OUTPUT_HDMI) {
727 struct intel_shared_dpll *pll;
731 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
733 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
734 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
735 WRPLL_DIVIDER_POST(p);
737 intel_crtc->config.dpll_hw_state.wrpll = val;
739 pll = intel_get_shared_dpll(intel_crtc);
741 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
742 pipe_name(intel_crtc->pipe));
746 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
752 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
754 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
757 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
758 int type = intel_encoder->type;
761 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
762 temp = TRANS_MSA_SYNC_CLK;
763 switch (intel_crtc->config.pipe_bpp) {
765 temp |= TRANS_MSA_6_BPC;
768 temp |= TRANS_MSA_8_BPC;
771 temp |= TRANS_MSA_10_BPC;
774 temp |= TRANS_MSA_12_BPC;
779 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
783 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
786 struct drm_device *dev = crtc->dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
790 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
792 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
794 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
795 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
798 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
801 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
802 struct drm_encoder *encoder = &intel_encoder->base;
803 struct drm_device *dev = crtc->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 enum pipe pipe = intel_crtc->pipe;
806 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
807 enum port port = intel_ddi_get_encoder_port(intel_encoder);
808 int type = intel_encoder->type;
811 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
812 temp = TRANS_DDI_FUNC_ENABLE;
813 temp |= TRANS_DDI_SELECT_PORT(port);
815 switch (intel_crtc->config.pipe_bpp) {
817 temp |= TRANS_DDI_BPC_6;
820 temp |= TRANS_DDI_BPC_8;
823 temp |= TRANS_DDI_BPC_10;
826 temp |= TRANS_DDI_BPC_12;
832 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
833 temp |= TRANS_DDI_PVSYNC;
834 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
835 temp |= TRANS_DDI_PHSYNC;
837 if (cpu_transcoder == TRANSCODER_EDP) {
840 /* On Haswell, can only use the always-on power well for
841 * eDP when not using the panel fitter, and when not
842 * using motion blur mitigation (which we don't
844 if (IS_HASWELL(dev) &&
845 (intel_crtc->config.pch_pfit.enabled ||
846 intel_crtc->config.pch_pfit.force_thru))
847 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
849 temp |= TRANS_DDI_EDP_INPUT_A_ON;
852 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
855 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
863 if (type == INTEL_OUTPUT_HDMI) {
864 if (intel_crtc->config.has_hdmi_sink)
865 temp |= TRANS_DDI_MODE_SELECT_HDMI;
867 temp |= TRANS_DDI_MODE_SELECT_DVI;
869 } else if (type == INTEL_OUTPUT_ANALOG) {
870 temp |= TRANS_DDI_MODE_SELECT_FDI;
871 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
873 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
874 type == INTEL_OUTPUT_EDP) {
875 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
877 if (intel_dp->is_mst) {
878 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
880 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
882 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
883 } else if (type == INTEL_OUTPUT_DP_MST) {
884 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
886 if (intel_dp->is_mst) {
887 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
889 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
891 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
893 WARN(1, "Invalid encoder type %d for pipe %c\n",
894 intel_encoder->type, pipe_name(pipe));
897 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
900 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
901 enum transcoder cpu_transcoder)
903 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
904 uint32_t val = I915_READ(reg);
906 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
907 val |= TRANS_DDI_PORT_NONE;
908 I915_WRITE(reg, val);
911 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
913 struct drm_device *dev = intel_connector->base.dev;
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 struct intel_encoder *intel_encoder = intel_connector->encoder;
916 int type = intel_connector->base.connector_type;
917 enum port port = intel_ddi_get_encoder_port(intel_encoder);
919 enum transcoder cpu_transcoder;
920 enum intel_display_power_domain power_domain;
923 power_domain = intel_display_port_power_domain(intel_encoder);
924 if (!intel_display_power_enabled(dev_priv, power_domain))
927 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
931 cpu_transcoder = TRANSCODER_EDP;
933 cpu_transcoder = (enum transcoder) pipe;
935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
937 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
938 case TRANS_DDI_MODE_SELECT_HDMI:
939 case TRANS_DDI_MODE_SELECT_DVI:
940 return (type == DRM_MODE_CONNECTOR_HDMIA);
942 case TRANS_DDI_MODE_SELECT_DP_SST:
943 if (type == DRM_MODE_CONNECTOR_eDP)
945 return (type == DRM_MODE_CONNECTOR_DisplayPort);
946 case TRANS_DDI_MODE_SELECT_DP_MST:
947 /* if the transcoder is in MST state then
948 * connector isn't connected */
951 case TRANS_DDI_MODE_SELECT_FDI:
952 return (type == DRM_MODE_CONNECTOR_VGA);
959 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
962 struct drm_device *dev = encoder->base.dev;
963 struct drm_i915_private *dev_priv = dev->dev_private;
964 enum port port = intel_ddi_get_encoder_port(encoder);
965 enum intel_display_power_domain power_domain;
969 power_domain = intel_display_port_power_domain(encoder);
970 if (!intel_display_power_enabled(dev_priv, power_domain))
973 tmp = I915_READ(DDI_BUF_CTL(port));
975 if (!(tmp & DDI_BUF_CTL_ENABLE))
978 if (port == PORT_A) {
979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
981 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
982 case TRANS_DDI_EDP_INPUT_A_ON:
983 case TRANS_DDI_EDP_INPUT_A_ONOFF:
986 case TRANS_DDI_EDP_INPUT_B_ONOFF:
989 case TRANS_DDI_EDP_INPUT_C_ONOFF:
996 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
999 if ((tmp & TRANS_DDI_PORT_MASK)
1000 == TRANS_DDI_SELECT_PORT(port)) {
1001 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1010 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1015 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1017 struct drm_crtc *crtc = &intel_crtc->base;
1018 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1019 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1020 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1021 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1023 if (cpu_transcoder != TRANSCODER_EDP)
1024 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1025 TRANS_CLK_SEL_PORT(port));
1028 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1030 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1031 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1033 if (cpu_transcoder != TRANSCODER_EDP)
1034 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1035 TRANS_CLK_SEL_DISABLED);
1038 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1040 struct drm_encoder *encoder = &intel_encoder->base;
1041 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1042 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1043 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1044 int type = intel_encoder->type;
1046 if (crtc->config.has_audio) {
1047 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1048 pipe_name(crtc->pipe));
1051 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1052 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1055 if (type == INTEL_OUTPUT_EDP) {
1056 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1057 intel_edp_panel_on(intel_dp);
1060 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1061 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1063 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1066 intel_ddi_init_dp_buf_reg(intel_encoder);
1068 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1069 intel_dp_start_link_train(intel_dp);
1070 intel_dp_complete_link_train(intel_dp);
1072 intel_dp_stop_link_train(intel_dp);
1073 } else if (type == INTEL_OUTPUT_HDMI) {
1074 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1076 intel_hdmi->set_infoframes(encoder,
1077 crtc->config.has_hdmi_sink,
1078 &crtc->config.adjusted_mode);
1082 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1084 struct drm_encoder *encoder = &intel_encoder->base;
1085 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1086 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1087 int type = intel_encoder->type;
1091 val = I915_READ(DDI_BUF_CTL(port));
1092 if (val & DDI_BUF_CTL_ENABLE) {
1093 val &= ~DDI_BUF_CTL_ENABLE;
1094 I915_WRITE(DDI_BUF_CTL(port), val);
1098 val = I915_READ(DP_TP_CTL(port));
1099 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1100 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1101 I915_WRITE(DP_TP_CTL(port), val);
1104 intel_wait_ddi_buf_idle(dev_priv, port);
1106 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1107 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1108 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1109 intel_edp_panel_vdd_on(intel_dp);
1110 intel_edp_panel_off(intel_dp);
1113 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1116 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1118 struct drm_encoder *encoder = &intel_encoder->base;
1119 struct drm_crtc *crtc = encoder->crtc;
1120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1121 int pipe = intel_crtc->pipe;
1122 struct drm_device *dev = encoder->dev;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1125 int type = intel_encoder->type;
1128 if (type == INTEL_OUTPUT_HDMI) {
1129 struct intel_digital_port *intel_dig_port =
1130 enc_to_dig_port(encoder);
1132 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1133 * are ignored so nothing special needs to be done besides
1134 * enabling the port.
1136 I915_WRITE(DDI_BUF_CTL(port),
1137 intel_dig_port->saved_port_bits |
1138 DDI_BUF_CTL_ENABLE);
1139 } else if (type == INTEL_OUTPUT_EDP) {
1140 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1143 intel_dp_stop_link_train(intel_dp);
1145 intel_edp_backlight_on(intel_dp);
1146 intel_edp_psr_enable(intel_dp);
1149 if (intel_crtc->config.has_audio) {
1150 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1151 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1152 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1153 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1157 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1159 struct drm_encoder *encoder = &intel_encoder->base;
1160 struct drm_crtc *crtc = encoder->crtc;
1161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1162 int pipe = intel_crtc->pipe;
1163 int type = intel_encoder->type;
1164 struct drm_device *dev = encoder->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1168 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1169 * register is part of the power well on Haswell. */
1170 if (intel_crtc->config.has_audio) {
1171 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1172 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1174 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1175 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1178 if (type == INTEL_OUTPUT_EDP) {
1179 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1181 intel_edp_psr_disable(intel_dp);
1182 intel_edp_backlight_off(intel_dp);
1186 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1188 struct drm_device *dev = dev_priv->dev;
1189 uint32_t lcpll = I915_READ(LCPLL_CTL);
1190 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1192 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1194 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1196 } else if (freq == LCPLL_CLK_FREQ_450) {
1198 } else if (IS_HASWELL(dev)) {
1204 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1206 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1213 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1214 struct intel_shared_dpll *pll)
1216 I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1217 POSTING_READ(WRPLL_CTL(pll->id));
1221 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1222 struct intel_shared_dpll *pll)
1226 val = I915_READ(WRPLL_CTL(pll->id));
1227 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1228 POSTING_READ(WRPLL_CTL(pll->id));
1231 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1232 struct intel_shared_dpll *pll,
1233 struct intel_dpll_hw_state *hw_state)
1237 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
1240 val = I915_READ(WRPLL_CTL(pll->id));
1241 hw_state->wrpll = val;
1243 return val & WRPLL_PLL_ENABLE;
1246 static const char * const hsw_ddi_pll_names[] = {
1251 void intel_ddi_pll_init(struct drm_device *dev)
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 uint32_t val = I915_READ(LCPLL_CTL);
1257 dev_priv->num_shared_dpll = 2;
1259 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1260 dev_priv->shared_dplls[i].id = i;
1261 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1262 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1263 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1264 dev_priv->shared_dplls[i].get_hw_state =
1265 hsw_ddi_pll_get_hw_state;
1268 /* The LCPLL register should be turned on by the BIOS. For now let's
1269 * just check its state and print errors in case something is wrong.
1270 * Don't even try to turn it on.
1273 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1274 intel_ddi_get_cdclk_freq(dev_priv));
1276 if (val & LCPLL_CD_SOURCE_FCLK)
1277 DRM_ERROR("CDCLK source is not LCPLL\n");
1279 if (val & LCPLL_PLL_DISABLE)
1280 DRM_ERROR("LCPLL is disabled\n");
1283 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1285 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1286 struct intel_dp *intel_dp = &intel_dig_port->dp;
1287 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1288 enum port port = intel_dig_port->port;
1292 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1293 val = I915_READ(DDI_BUF_CTL(port));
1294 if (val & DDI_BUF_CTL_ENABLE) {
1295 val &= ~DDI_BUF_CTL_ENABLE;
1296 I915_WRITE(DDI_BUF_CTL(port), val);
1300 val = I915_READ(DP_TP_CTL(port));
1301 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1302 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1303 I915_WRITE(DP_TP_CTL(port), val);
1304 POSTING_READ(DP_TP_CTL(port));
1307 intel_wait_ddi_buf_idle(dev_priv, port);
1310 val = DP_TP_CTL_ENABLE |
1311 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1312 if (intel_dp->is_mst)
1313 val |= DP_TP_CTL_MODE_MST;
1315 val |= DP_TP_CTL_MODE_SST;
1316 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1317 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1319 I915_WRITE(DP_TP_CTL(port), val);
1320 POSTING_READ(DP_TP_CTL(port));
1322 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1323 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1324 POSTING_READ(DDI_BUF_CTL(port));
1329 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1331 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1332 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1335 intel_ddi_post_disable(intel_encoder);
1337 val = I915_READ(_FDI_RXA_CTL);
1338 val &= ~FDI_RX_ENABLE;
1339 I915_WRITE(_FDI_RXA_CTL, val);
1341 val = I915_READ(_FDI_RXA_MISC);
1342 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1343 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1344 I915_WRITE(_FDI_RXA_MISC, val);
1346 val = I915_READ(_FDI_RXA_CTL);
1348 I915_WRITE(_FDI_RXA_CTL, val);
1350 val = I915_READ(_FDI_RXA_CTL);
1351 val &= ~FDI_RX_PLL_ENABLE;
1352 I915_WRITE(_FDI_RXA_CTL, val);
1355 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1357 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1358 int type = intel_dig_port->base.type;
1360 if (type != INTEL_OUTPUT_DISPLAYPORT &&
1361 type != INTEL_OUTPUT_EDP &&
1362 type != INTEL_OUTPUT_UNKNOWN) {
1366 intel_dp_hot_plug(intel_encoder);
1369 void intel_ddi_get_config(struct intel_encoder *encoder,
1370 struct intel_crtc_config *pipe_config)
1372 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1373 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1374 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1375 u32 temp, flags = 0;
1377 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1378 if (temp & TRANS_DDI_PHSYNC)
1379 flags |= DRM_MODE_FLAG_PHSYNC;
1381 flags |= DRM_MODE_FLAG_NHSYNC;
1382 if (temp & TRANS_DDI_PVSYNC)
1383 flags |= DRM_MODE_FLAG_PVSYNC;
1385 flags |= DRM_MODE_FLAG_NVSYNC;
1387 pipe_config->adjusted_mode.flags |= flags;
1389 switch (temp & TRANS_DDI_BPC_MASK) {
1390 case TRANS_DDI_BPC_6:
1391 pipe_config->pipe_bpp = 18;
1393 case TRANS_DDI_BPC_8:
1394 pipe_config->pipe_bpp = 24;
1396 case TRANS_DDI_BPC_10:
1397 pipe_config->pipe_bpp = 30;
1399 case TRANS_DDI_BPC_12:
1400 pipe_config->pipe_bpp = 36;
1406 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1407 case TRANS_DDI_MODE_SELECT_HDMI:
1408 pipe_config->has_hdmi_sink = true;
1409 case TRANS_DDI_MODE_SELECT_DVI:
1410 case TRANS_DDI_MODE_SELECT_FDI:
1412 case TRANS_DDI_MODE_SELECT_DP_SST:
1413 case TRANS_DDI_MODE_SELECT_DP_MST:
1414 pipe_config->has_dp_encoder = true;
1415 intel_dp_get_m_n(intel_crtc, pipe_config);
1421 if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1422 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1423 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1424 pipe_config->has_audio = true;
1427 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1428 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1430 * This is a big fat ugly hack.
1432 * Some machines in UEFI boot mode provide us a VBT that has 18
1433 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1434 * unknown we fail to light up. Yet the same BIOS boots up with
1435 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1436 * max, not what it tells us to use.
1438 * Note: This will still be broken if the eDP panel is not lit
1439 * up by the BIOS, and thus we can't get the mode at module
1442 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1443 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1444 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1447 intel_ddi_clock_get(encoder, pipe_config);
1450 static void intel_ddi_destroy(struct drm_encoder *encoder)
1452 /* HDMI has nothing special to destroy, so we can go with this. */
1453 intel_dp_encoder_destroy(encoder);
1456 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1457 struct intel_crtc_config *pipe_config)
1459 int type = encoder->type;
1460 int port = intel_ddi_get_encoder_port(encoder);
1462 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1465 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1467 if (type == INTEL_OUTPUT_HDMI)
1468 return intel_hdmi_compute_config(encoder, pipe_config);
1470 return intel_dp_compute_config(encoder, pipe_config);
1473 static const struct drm_encoder_funcs intel_ddi_funcs = {
1474 .destroy = intel_ddi_destroy,
1477 static struct intel_connector *
1478 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1480 struct intel_connector *connector;
1481 enum port port = intel_dig_port->port;
1483 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1487 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1488 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1496 static struct intel_connector *
1497 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1499 struct intel_connector *connector;
1500 enum port port = intel_dig_port->port;
1502 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1506 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1507 intel_hdmi_init_connector(intel_dig_port, connector);
1512 void intel_ddi_init(struct drm_device *dev, enum port port)
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 struct intel_digital_port *intel_dig_port;
1516 struct intel_encoder *intel_encoder;
1517 struct drm_encoder *encoder;
1518 bool init_hdmi, init_dp;
1520 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1521 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1522 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1523 if (!init_dp && !init_hdmi) {
1524 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1530 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1531 if (!intel_dig_port)
1534 intel_encoder = &intel_dig_port->base;
1535 encoder = &intel_encoder->base;
1537 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1538 DRM_MODE_ENCODER_TMDS);
1540 intel_encoder->compute_config = intel_ddi_compute_config;
1541 intel_encoder->enable = intel_enable_ddi;
1542 intel_encoder->pre_enable = intel_ddi_pre_enable;
1543 intel_encoder->disable = intel_disable_ddi;
1544 intel_encoder->post_disable = intel_ddi_post_disable;
1545 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1546 intel_encoder->get_config = intel_ddi_get_config;
1548 intel_dig_port->port = port;
1549 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1550 (DDI_BUF_PORT_REVERSAL |
1553 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1554 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1555 intel_encoder->cloneable = 0;
1556 intel_encoder->hot_plug = intel_ddi_hot_plug;
1559 if (!intel_ddi_init_dp_connector(intel_dig_port))
1562 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1563 dev_priv->hpd_irq_port[port] = intel_dig_port;
1566 /* In theory we don't need the encoder->type check, but leave it just in
1567 * case we have some really bad VBTs... */
1568 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1569 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1576 drm_encoder_cleanup(encoder);
1577 kfree(intel_dig_port);