2 * Copyright © 2014 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
38 MODULE_FIRMWARE(I915_CSR_ICL);
39 #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
41 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
42 MODULE_FIRMWARE(I915_CSR_GLK);
43 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
45 #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
46 MODULE_FIRMWARE(I915_CSR_CNL);
47 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
49 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
50 MODULE_FIRMWARE(I915_CSR_KBL);
51 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
53 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
54 MODULE_FIRMWARE(I915_CSR_SKL);
55 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
57 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
58 MODULE_FIRMWARE(I915_CSR_BXT);
59 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
62 #define BXT_CSR_MAX_FW_SIZE 0x3000
63 #define GLK_CSR_MAX_FW_SIZE 0x4000
64 #define ICL_CSR_MAX_FW_SIZE 0x6000
65 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
67 struct intel_css_header {
71 /* Includes the DMC specific header in dwords */
74 /* always value would be 0x10000 */
81 uint32_t module_vendor;
83 /* in YYYYMMDD format */
86 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
93 uint32_t modulus_size;
96 uint32_t exponent_size;
99 uint32_t reserved1[12];
105 uint32_t reserved2[8];
108 uint32_t kernel_header_info;
111 struct intel_fw_info {
114 /* Stepping (A, B, C, ..., *). * is a wildcard */
117 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
124 struct intel_package_header {
125 /* DMC container header length in dwords */
126 unsigned char header_len;
128 /* always value would be 0x01 */
129 unsigned char header_ver;
131 unsigned char reserved[10];
133 /* Number of valid entries in the FWInfo array below */
134 uint32_t num_entries;
136 struct intel_fw_info fw_info[20];
139 struct intel_dmc_header {
140 /* always value would be 0x40403E3E */
143 /* DMC binary header length */
144 unsigned char header_len;
147 unsigned char header_ver;
155 /* Firmware program size (excluding header) in dwords */
158 /* Major Minor version */
161 /* Number of valid MMIO cycles present. */
165 uint32_t mmioaddr[8];
168 uint32_t mmiodata[8];
171 unsigned char dfile[32];
173 uint32_t reserved1[2];
176 struct stepping_info {
181 static const struct stepping_info skl_stepping_info[] = {
182 {'A', '0'}, {'B', '0'}, {'C', '0'},
183 {'D', '0'}, {'E', '0'}, {'F', '0'},
184 {'G', '0'}, {'H', '0'}, {'I', '0'},
185 {'J', '0'}, {'K', '0'}
188 static const struct stepping_info bxt_stepping_info[] = {
189 {'A', '0'}, {'A', '1'}, {'A', '2'},
190 {'B', '0'}, {'B', '1'}, {'B', '2'}
193 static const struct stepping_info no_stepping_info = { '*', '*' };
195 static const struct stepping_info *
196 intel_get_stepping_info(struct drm_i915_private *dev_priv)
198 const struct stepping_info *si;
201 if (IS_SKYLAKE(dev_priv)) {
202 size = ARRAY_SIZE(skl_stepping_info);
203 si = skl_stepping_info;
204 } else if (IS_BROXTON(dev_priv)) {
205 size = ARRAY_SIZE(bxt_stepping_info);
206 si = bxt_stepping_info;
212 if (INTEL_REVID(dev_priv) < size)
213 return si + INTEL_REVID(dev_priv);
215 return &no_stepping_info;
218 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
222 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
224 if (IS_GEN9_LP(dev_priv))
225 mask |= DC_STATE_DEBUG_MASK_CORES;
227 /* The below bit doesn't need to be cleared ever afterwards */
228 val = I915_READ(DC_STATE_DEBUG);
229 if ((val & mask) != mask) {
231 I915_WRITE(DC_STATE_DEBUG, val);
232 POSTING_READ(DC_STATE_DEBUG);
237 * intel_csr_load_program() - write the firmware from memory to register.
238 * @dev_priv: i915 drm device.
240 * CSR firmware is read from a .bin file and kept in internal memory one time.
241 * Everytime display comes back from low power state this function is called to
242 * copy the firmware from internal memory to registers.
244 void intel_csr_load_program(struct drm_i915_private *dev_priv)
246 u32 *payload = dev_priv->csr.dmc_payload;
249 if (!HAS_CSR(dev_priv)) {
250 DRM_ERROR("No CSR support available for this platform\n");
254 if (!dev_priv->csr.dmc_payload) {
255 DRM_ERROR("Tried to program CSR with empty payload\n");
259 fw_size = dev_priv->csr.dmc_fw_size;
260 assert_rpm_wakelock_held(dev_priv);
264 for (i = 0; i < fw_size; i++)
265 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
269 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
270 I915_WRITE(dev_priv->csr.mmioaddr[i],
271 dev_priv->csr.mmiodata[i]);
274 dev_priv->csr.dc_state = 0;
276 gen9_set_dc_state_debugmask(dev_priv);
279 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
280 const struct firmware *fw)
282 struct intel_css_header *css_header;
283 struct intel_package_header *package_header;
284 struct intel_dmc_header *dmc_header;
285 struct intel_csr *csr = &dev_priv->csr;
286 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
287 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
288 uint32_t max_fw_size = 0;
290 uint32_t *dmc_payload;
291 uint32_t required_version;
296 /* Extract CSS Header information*/
297 css_header = (struct intel_css_header *)fw->data;
298 if (sizeof(struct intel_css_header) !=
299 (css_header->header_len * 4)) {
300 DRM_ERROR("DMC firmware has wrong CSS header length "
302 (css_header->header_len * 4));
306 csr->version = css_header->version;
308 if (csr->fw_path == i915_modparams.dmc_firmware_path) {
309 /* Bypass version check for firmware override. */
310 required_version = csr->version;
311 } else if (IS_ICELAKE(dev_priv)) {
312 required_version = ICL_CSR_VERSION_REQUIRED;
313 } else if (IS_CANNONLAKE(dev_priv)) {
314 required_version = CNL_CSR_VERSION_REQUIRED;
315 } else if (IS_GEMINILAKE(dev_priv)) {
316 required_version = GLK_CSR_VERSION_REQUIRED;
317 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
318 required_version = KBL_CSR_VERSION_REQUIRED;
319 } else if (IS_SKYLAKE(dev_priv)) {
320 required_version = SKL_CSR_VERSION_REQUIRED;
321 } else if (IS_BROXTON(dev_priv)) {
322 required_version = BXT_CSR_VERSION_REQUIRED;
324 MISSING_CASE(INTEL_REVID(dev_priv));
325 required_version = 0;
328 if (csr->version != required_version) {
329 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
330 " please use v%u.%u\n",
331 CSR_VERSION_MAJOR(csr->version),
332 CSR_VERSION_MINOR(csr->version),
333 CSR_VERSION_MAJOR(required_version),
334 CSR_VERSION_MINOR(required_version));
338 readcount += sizeof(struct intel_css_header);
340 /* Extract Package Header information*/
341 package_header = (struct intel_package_header *)
342 &fw->data[readcount];
343 if (sizeof(struct intel_package_header) !=
344 (package_header->header_len * 4)) {
345 DRM_ERROR("DMC firmware has wrong package header length "
347 (package_header->header_len * 4));
350 readcount += sizeof(struct intel_package_header);
352 /* Search for dmc_offset to find firware binary. */
353 for (i = 0; i < package_header->num_entries; i++) {
354 if (package_header->fw_info[i].substepping == '*' &&
355 si->stepping == package_header->fw_info[i].stepping) {
356 dmc_offset = package_header->fw_info[i].offset;
358 } else if (si->stepping == package_header->fw_info[i].stepping &&
359 si->substepping == package_header->fw_info[i].substepping) {
360 dmc_offset = package_header->fw_info[i].offset;
362 } else if (package_header->fw_info[i].stepping == '*' &&
363 package_header->fw_info[i].substepping == '*')
364 dmc_offset = package_header->fw_info[i].offset;
366 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
367 DRM_ERROR("DMC firmware not supported for %c stepping\n",
371 /* Convert dmc_offset into number of bytes. By default it is in dwords*/
373 readcount += dmc_offset;
375 /* Extract dmc_header information. */
376 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
377 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
378 DRM_ERROR("DMC firmware has wrong dmc header length "
380 (dmc_header->header_len));
383 readcount += sizeof(struct intel_dmc_header);
385 /* Cache the dmc header info. */
386 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
387 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
388 dmc_header->mmio_count);
391 csr->mmio_count = dmc_header->mmio_count;
392 for (i = 0; i < dmc_header->mmio_count; i++) {
393 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
394 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
395 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
396 dmc_header->mmioaddr[i]);
399 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
400 csr->mmiodata[i] = dmc_header->mmiodata[i];
403 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
404 nbytes = dmc_header->fw_size * 4;
405 if (INTEL_GEN(dev_priv) >= 11)
406 max_fw_size = ICL_CSR_MAX_FW_SIZE;
407 else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
408 max_fw_size = GLK_CSR_MAX_FW_SIZE;
409 else if (IS_GEN9(dev_priv))
410 max_fw_size = BXT_CSR_MAX_FW_SIZE;
412 MISSING_CASE(INTEL_REVID(dev_priv));
413 if (nbytes > max_fw_size) {
414 DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
417 csr->dmc_fw_size = dmc_header->fw_size;
419 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
421 DRM_ERROR("Memory allocation failed for dmc payload\n");
425 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
428 static void csr_load_work_fn(struct work_struct *work)
430 struct drm_i915_private *dev_priv;
431 struct intel_csr *csr;
432 const struct firmware *fw = NULL;
434 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
435 csr = &dev_priv->csr;
437 request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
439 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
441 if (dev_priv->csr.dmc_payload) {
442 intel_csr_load_program(dev_priv);
444 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
446 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
447 dev_priv->csr.fw_path,
448 CSR_VERSION_MAJOR(csr->version),
449 CSR_VERSION_MINOR(csr->version));
451 dev_notice(dev_priv->drm.dev,
452 "Failed to load DMC firmware %s."
453 " Disabling runtime power management.\n",
455 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
456 INTEL_UC_FIRMWARE_URL);
459 release_firmware(fw);
463 * intel_csr_ucode_init() - initialize the firmware loading.
464 * @dev_priv: i915 drm device.
466 * This function is called at the time of loading the display driver to read
467 * firmware from a .bin file and copied into a internal memory.
469 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
471 struct intel_csr *csr = &dev_priv->csr;
473 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
475 if (!HAS_CSR(dev_priv))
478 if (i915_modparams.dmc_firmware_path)
479 csr->fw_path = i915_modparams.dmc_firmware_path;
480 else if (IS_ICELAKE(dev_priv))
481 csr->fw_path = I915_CSR_ICL;
482 else if (IS_CANNONLAKE(dev_priv))
483 csr->fw_path = I915_CSR_CNL;
484 else if (IS_GEMINILAKE(dev_priv))
485 csr->fw_path = I915_CSR_GLK;
486 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
487 csr->fw_path = I915_CSR_KBL;
488 else if (IS_SKYLAKE(dev_priv))
489 csr->fw_path = I915_CSR_SKL;
490 else if (IS_BROXTON(dev_priv))
491 csr->fw_path = I915_CSR_BXT;
494 * Obtain a runtime pm reference, until CSR is loaded,
495 * to avoid entering runtime-suspend.
497 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
499 if (csr->fw_path == NULL) {
500 DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
501 WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));
506 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
507 schedule_work(&dev_priv->csr.work);
511 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
512 * @dev_priv: i915 drm device
514 * Prepare the DMC firmware before entering system suspend. This includes
515 * flushing pending work items and releasing any resources acquired during
518 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
520 if (!HAS_CSR(dev_priv))
523 flush_work(&dev_priv->csr.work);
525 /* Drop the reference held in case DMC isn't loaded. */
526 if (!dev_priv->csr.dmc_payload)
527 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
531 * intel_csr_ucode_resume() - init CSR firmware during system resume
532 * @dev_priv: i915 drm device
534 * Reinitialize the DMC firmware during system resume, reacquiring any
535 * resources released in intel_csr_ucode_suspend().
537 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
539 if (!HAS_CSR(dev_priv))
543 * Reacquire the reference to keep RPM disabled in case DMC isn't
546 if (!dev_priv->csr.dmc_payload)
547 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
551 * intel_csr_ucode_fini() - unload the CSR firmware.
552 * @dev_priv: i915 drm device.
554 * Firmmware unloading includes freeing the internal memory and reset the
555 * firmware loading status.
557 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
559 if (!HAS_CSR(dev_priv))
562 intel_csr_ucode_suspend(dev_priv);
564 kfree(dev_priv->csr.dmc_payload);