2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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24 #include <linux/firmware.h>
29 * DOC: csr support for dmc
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
38 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
40 #define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
41 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
43 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
44 MODULE_FIRMWARE(I915_CSR_KBL);
45 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
47 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
48 MODULE_FIRMWARE(I915_CSR_SKL);
49 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26)
51 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
52 MODULE_FIRMWARE(I915_CSR_BXT);
53 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
56 #define CSR_MAX_FW_SIZE 0x2FFF
57 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
59 struct intel_css_header {
63 /* Includes the DMC specific header in dwords */
66 /* always value would be 0x10000 */
73 uint32_t module_vendor;
75 /* in YYYYMMDD format */
78 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
85 uint32_t modulus_size;
88 uint32_t exponent_size;
91 uint32_t reserved1[12];
97 uint32_t reserved2[8];
100 uint32_t kernel_header_info;
103 struct intel_fw_info {
106 /* Stepping (A, B, C, ..., *). * is a wildcard */
109 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
116 struct intel_package_header {
117 /* DMC container header length in dwords */
118 unsigned char header_len;
120 /* always value would be 0x01 */
121 unsigned char header_ver;
123 unsigned char reserved[10];
125 /* Number of valid entries in the FWInfo array below */
126 uint32_t num_entries;
128 struct intel_fw_info fw_info[20];
131 struct intel_dmc_header {
132 /* always value would be 0x40403E3E */
135 /* DMC binary header length */
136 unsigned char header_len;
139 unsigned char header_ver;
147 /* Firmware program size (excluding header) in dwords */
150 /* Major Minor version */
153 /* Number of valid MMIO cycles present. */
157 uint32_t mmioaddr[8];
160 uint32_t mmiodata[8];
163 unsigned char dfile[32];
165 uint32_t reserved1[2];
168 struct stepping_info {
173 static const struct stepping_info skl_stepping_info[] = {
174 {'A', '0'}, {'B', '0'}, {'C', '0'},
175 {'D', '0'}, {'E', '0'}, {'F', '0'},
176 {'G', '0'}, {'H', '0'}, {'I', '0'},
177 {'J', '0'}, {'K', '0'}
180 static const struct stepping_info bxt_stepping_info[] = {
181 {'A', '0'}, {'A', '1'}, {'A', '2'},
182 {'B', '0'}, {'B', '1'}, {'B', '2'}
185 static const struct stepping_info no_stepping_info = { '*', '*' };
187 static const struct stepping_info *
188 intel_get_stepping_info(struct drm_i915_private *dev_priv)
190 const struct stepping_info *si;
193 if (IS_SKYLAKE(dev_priv)) {
194 size = ARRAY_SIZE(skl_stepping_info);
195 si = skl_stepping_info;
196 } else if (IS_BROXTON(dev_priv)) {
197 size = ARRAY_SIZE(bxt_stepping_info);
198 si = bxt_stepping_info;
203 if (INTEL_REVID(dev_priv) < size)
204 return si + INTEL_REVID(dev_priv);
206 return &no_stepping_info;
209 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
213 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
215 if (IS_GEN9_LP(dev_priv))
216 mask |= DC_STATE_DEBUG_MASK_CORES;
218 /* The below bit doesn't need to be cleared ever afterwards */
219 val = I915_READ(DC_STATE_DEBUG);
220 if ((val & mask) != mask) {
222 I915_WRITE(DC_STATE_DEBUG, val);
223 POSTING_READ(DC_STATE_DEBUG);
228 * intel_csr_load_program() - write the firmware from memory to register.
229 * @dev_priv: i915 drm device.
231 * CSR firmware is read from a .bin file and kept in internal memory one time.
232 * Everytime display comes back from low power state this function is called to
233 * copy the firmware from internal memory to registers.
235 void intel_csr_load_program(struct drm_i915_private *dev_priv)
237 u32 *payload = dev_priv->csr.dmc_payload;
240 if (!HAS_CSR(dev_priv)) {
241 DRM_ERROR("No CSR support available for this platform\n");
245 if (!dev_priv->csr.dmc_payload) {
246 DRM_ERROR("Tried to program CSR with empty payload\n");
250 fw_size = dev_priv->csr.dmc_fw_size;
251 assert_rpm_wakelock_held(dev_priv);
255 for (i = 0; i < fw_size; i++)
256 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
260 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
261 I915_WRITE(dev_priv->csr.mmioaddr[i],
262 dev_priv->csr.mmiodata[i]);
265 dev_priv->csr.dc_state = 0;
267 gen9_set_dc_state_debugmask(dev_priv);
270 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
271 const struct firmware *fw)
273 struct intel_css_header *css_header;
274 struct intel_package_header *package_header;
275 struct intel_dmc_header *dmc_header;
276 struct intel_csr *csr = &dev_priv->csr;
277 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
278 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
280 uint32_t *dmc_payload;
281 uint32_t required_version;
286 /* Extract CSS Header information*/
287 css_header = (struct intel_css_header *)fw->data;
288 if (sizeof(struct intel_css_header) !=
289 (css_header->header_len * 4)) {
290 DRM_ERROR("DMC firmware has wrong CSS header length "
292 (css_header->header_len * 4));
296 csr->version = css_header->version;
298 if (IS_CANNONLAKE(dev_priv)) {
299 required_version = CNL_CSR_VERSION_REQUIRED;
300 } else if (IS_GEMINILAKE(dev_priv)) {
301 required_version = GLK_CSR_VERSION_REQUIRED;
302 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
303 required_version = KBL_CSR_VERSION_REQUIRED;
304 } else if (IS_SKYLAKE(dev_priv)) {
305 required_version = SKL_CSR_VERSION_REQUIRED;
306 } else if (IS_BROXTON(dev_priv)) {
307 required_version = BXT_CSR_VERSION_REQUIRED;
309 MISSING_CASE(INTEL_REVID(dev_priv));
310 required_version = 0;
313 if (csr->version != required_version) {
314 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
315 " please use v%u.%u\n",
316 CSR_VERSION_MAJOR(csr->version),
317 CSR_VERSION_MINOR(csr->version),
318 CSR_VERSION_MAJOR(required_version),
319 CSR_VERSION_MINOR(required_version));
323 readcount += sizeof(struct intel_css_header);
325 /* Extract Package Header information*/
326 package_header = (struct intel_package_header *)
327 &fw->data[readcount];
328 if (sizeof(struct intel_package_header) !=
329 (package_header->header_len * 4)) {
330 DRM_ERROR("DMC firmware has wrong package header length "
332 (package_header->header_len * 4));
335 readcount += sizeof(struct intel_package_header);
337 /* Search for dmc_offset to find firware binary. */
338 for (i = 0; i < package_header->num_entries; i++) {
339 if (package_header->fw_info[i].substepping == '*' &&
340 si->stepping == package_header->fw_info[i].stepping) {
341 dmc_offset = package_header->fw_info[i].offset;
343 } else if (si->stepping == package_header->fw_info[i].stepping &&
344 si->substepping == package_header->fw_info[i].substepping) {
345 dmc_offset = package_header->fw_info[i].offset;
347 } else if (package_header->fw_info[i].stepping == '*' &&
348 package_header->fw_info[i].substepping == '*')
349 dmc_offset = package_header->fw_info[i].offset;
351 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
352 DRM_ERROR("DMC firmware not supported for %c stepping\n",
356 readcount += dmc_offset;
358 /* Extract dmc_header information. */
359 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
360 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
361 DRM_ERROR("DMC firmware has wrong dmc header length "
363 (dmc_header->header_len));
366 readcount += sizeof(struct intel_dmc_header);
368 /* Cache the dmc header info. */
369 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
370 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
371 dmc_header->mmio_count);
374 csr->mmio_count = dmc_header->mmio_count;
375 for (i = 0; i < dmc_header->mmio_count; i++) {
376 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
377 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
378 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
379 dmc_header->mmioaddr[i]);
382 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
383 csr->mmiodata[i] = dmc_header->mmiodata[i];
386 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
387 nbytes = dmc_header->fw_size * 4;
388 if (nbytes > CSR_MAX_FW_SIZE) {
389 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
392 csr->dmc_fw_size = dmc_header->fw_size;
394 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
396 DRM_ERROR("Memory allocation failed for dmc payload\n");
400 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
403 static void csr_load_work_fn(struct work_struct *work)
405 struct drm_i915_private *dev_priv;
406 struct intel_csr *csr;
407 const struct firmware *fw = NULL;
409 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
410 csr = &dev_priv->csr;
412 request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
414 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
416 if (dev_priv->csr.dmc_payload) {
417 intel_csr_load_program(dev_priv);
419 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
421 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
422 dev_priv->csr.fw_path,
423 CSR_VERSION_MAJOR(csr->version),
424 CSR_VERSION_MINOR(csr->version));
426 dev_notice(dev_priv->drm.dev,
427 "Failed to load DMC firmware %s."
428 " Disabling runtime power management.\n",
430 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
431 INTEL_UC_FIRMWARE_URL);
434 release_firmware(fw);
438 * intel_csr_ucode_init() - initialize the firmware loading.
439 * @dev_priv: i915 drm device.
441 * This function is called at the time of loading the display driver to read
442 * firmware from a .bin file and copied into a internal memory.
444 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
446 struct intel_csr *csr = &dev_priv->csr;
448 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
450 if (!HAS_CSR(dev_priv))
453 if (IS_CANNONLAKE(dev_priv))
454 csr->fw_path = I915_CSR_CNL;
455 else if (IS_GEMINILAKE(dev_priv))
456 csr->fw_path = I915_CSR_GLK;
457 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
458 csr->fw_path = I915_CSR_KBL;
459 else if (IS_SKYLAKE(dev_priv))
460 csr->fw_path = I915_CSR_SKL;
461 else if (IS_BROXTON(dev_priv))
462 csr->fw_path = I915_CSR_BXT;
464 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
468 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
471 * Obtain a runtime pm reference, until CSR is loaded,
472 * to avoid entering runtime-suspend.
474 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
476 schedule_work(&dev_priv->csr.work);
480 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
481 * @dev_priv: i915 drm device
483 * Prepare the DMC firmware before entering system suspend. This includes
484 * flushing pending work items and releasing any resources acquired during
487 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
489 if (!HAS_CSR(dev_priv))
492 flush_work(&dev_priv->csr.work);
494 /* Drop the reference held in case DMC isn't loaded. */
495 if (!dev_priv->csr.dmc_payload)
496 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
500 * intel_csr_ucode_resume() - init CSR firmware during system resume
501 * @dev_priv: i915 drm device
503 * Reinitialize the DMC firmware during system resume, reacquiring any
504 * resources released in intel_csr_ucode_suspend().
506 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
508 if (!HAS_CSR(dev_priv))
512 * Reacquire the reference to keep RPM disabled in case DMC isn't
515 if (!dev_priv->csr.dmc_payload)
516 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
520 * intel_csr_ucode_fini() - unload the CSR firmware.
521 * @dev_priv: i915 drm device.
523 * Firmmware unloading includes freeing the internal memory and reset the
524 * firmware loading status.
526 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
528 if (!HAS_CSR(dev_priv))
531 intel_csr_ucode_suspend(dev_priv);
533 kfree(dev_priv->csr.dmc_payload);