drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_ICL "i915/icl_dmc_ver1_07.bin"
  38 MODULE_FIRMWARE(I915_CSR_ICL);
  39 #define ICL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  40
  41 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
  42 MODULE_FIRMWARE(I915_CSR_GLK);
  43 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  44
  45 #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
  46 MODULE_FIRMWARE(I915_CSR_CNL);
  47 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  48
  49 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
  50 MODULE_FIRMWARE(I915_CSR_KBL);
  51 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  52
  53 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
  54 MODULE_FIRMWARE(I915_CSR_SKL);
  55 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  56
  57 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
  58 MODULE_FIRMWARE(I915_CSR_BXT);
  59 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  60
  61
  62 #define BXT_CSR_MAX_FW_SIZE             0x3000
  63 #define GLK_CSR_MAX_FW_SIZE             0x4000
  64 #define ICL_CSR_MAX_FW_SIZE             0x6000
  65 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  66
  67 struct intel_css_header {
  68         /* 0x09 for DMC */
  69         uint32_t module_type;
  70
  71         /* Includes the DMC specific header in dwords */
  72         uint32_t header_len;
  73
  74         /* always value would be 0x10000 */
  75         uint32_t header_ver;
  76
  77         /* Not used */
  78         uint32_t module_id;
  79
  80         /* Not used */
  81         uint32_t module_vendor;
  82
  83         /* in YYYYMMDD format */
  84         uint32_t date;
  85
  86         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  87         uint32_t size;
  88
  89         /* Not used */
  90         uint32_t key_size;
  91
  92         /* Not used */
  93         uint32_t modulus_size;
  94
  95         /* Not used */
  96         uint32_t exponent_size;
  97
  98         /* Not used */
  99         uint32_t reserved1[12];
 100
 101         /* Major Minor */
 102         uint32_t version;
 103
 104         /* Not used */
 105         uint32_t reserved2[8];
 106
 107         /* Not used */
 108         uint32_t kernel_header_info;
 109 } __packed;
 110
 111 struct intel_fw_info {
 112         uint16_t reserved1;
 113
 114         /* Stepping (A, B, C, ..., *). * is a wildcard */
 115         char stepping;
 116
 117         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 118         char substepping;
 119
 120         uint32_t offset;
 121         uint32_t reserved2;
 122 } __packed;
 123
 124 struct intel_package_header {
 125         /* DMC container header length in dwords */
 126         unsigned char header_len;
 127
 128         /* always value would be 0x01 */
 129         unsigned char header_ver;
 130
 131         unsigned char reserved[10];
 132
 133         /* Number of valid entries in the FWInfo array below */
 134         uint32_t num_entries;
 135
 136         struct intel_fw_info fw_info[20];
 137 } __packed;
 138
 139 struct intel_dmc_header {
 140         /* always value would be 0x40403E3E */
 141         uint32_t signature;
 142
 143         /* DMC binary header length */
 144         unsigned char header_len;
 145
 146         /* 0x01 */
 147         unsigned char header_ver;
 148
 149         /* Reserved */
 150         uint16_t dmcc_ver;
 151
 152         /* Major, Minor */
 153         uint32_t        project;
 154
 155         /* Firmware program size (excluding header) in dwords */
 156         uint32_t        fw_size;
 157
 158         /* Major Minor version */
 159         uint32_t fw_version;
 160
 161         /* Number of valid MMIO cycles present. */
 162         uint32_t mmio_count;
 163
 164         /* MMIO address */
 165         uint32_t mmioaddr[8];
 166
 167         /* MMIO data */
 168         uint32_t mmiodata[8];
 169
 170         /* FW filename  */
 171         unsigned char dfile[32];
 172
 173         uint32_t reserved1[2];
 174 } __packed;
 175
 176 struct stepping_info {
 177         char stepping;
 178         char substepping;
 179 };
 180
 181 static const struct stepping_info skl_stepping_info[] = {
 182         {'A', '0'}, {'B', '0'}, {'C', '0'},
 183         {'D', '0'}, {'E', '0'}, {'F', '0'},
 184         {'G', '0'}, {'H', '0'}, {'I', '0'},
 185         {'J', '0'}, {'K', '0'}
 186 };
 187
 188 static const struct stepping_info bxt_stepping_info[] = {
 189         {'A', '0'}, {'A', '1'}, {'A', '2'},
 190         {'B', '0'}, {'B', '1'}, {'B', '2'}
 191 };
 192
 193 static const struct stepping_info no_stepping_info = { '*', '*' };
 194
 195 static const struct stepping_info *
 196 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 197 {
 198         const struct stepping_info *si;
 199         unsigned int size;
 200
 201         if (IS_SKYLAKE(dev_priv)) {
 202                 size = ARRAY_SIZE(skl_stepping_info);
 203                 si = skl_stepping_info;
 204         } else if (IS_BROXTON(dev_priv)) {
 205                 size = ARRAY_SIZE(bxt_stepping_info);
 206                 si = bxt_stepping_info;
 207         } else {
 208                 size = 0;
 209                 si = NULL;
 210         }
 211
 212         if (INTEL_REVID(dev_priv) < size)
 213                 return si + INTEL_REVID(dev_priv);
 214
 215         return &no_stepping_info;
 216 }
 217
 218 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 219 {
 220         uint32_t val, mask;
 221
 222         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 223
 224         if (IS_GEN9_LP(dev_priv))
 225                 mask |= DC_STATE_DEBUG_MASK_CORES;
 226
 227         /* The below bit doesn't need to be cleared ever afterwards */
 228         val = I915_READ(DC_STATE_DEBUG);
 229         if ((val & mask) != mask) {
 230                 val |= mask;
 231                 I915_WRITE(DC_STATE_DEBUG, val);
 232                 POSTING_READ(DC_STATE_DEBUG);
 233         }
 234 }
 235
 236 /**
 237  * intel_csr_load_program() - write the firmware from memory to register.
 238  * @dev_priv: i915 drm device.
 239  *
 240  * CSR firmware is read from a .bin file and kept in internal memory one time.
 241  * Everytime display comes back from low power state this function is called to
 242  * copy the firmware from internal memory to registers.
 243  */
 244 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 245 {
 246         u32 *payload = dev_priv->csr.dmc_payload;
 247         uint32_t i, fw_size;
 248
 249         if (!HAS_CSR(dev_priv)) {
 250                 DRM_ERROR("No CSR support available for this platform\n");
 251                 return;
 252         }
 253
 254         if (!dev_priv->csr.dmc_payload) {
 255                 DRM_ERROR("Tried to program CSR with empty payload\n");
 256                 return;
 257         }
 258
 259         fw_size = dev_priv->csr.dmc_fw_size;
 260         assert_rpm_wakelock_held(dev_priv);
 261
 262         preempt_disable();
 263
 264         for (i = 0; i < fw_size; i++)
 265                 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
 266
 267         preempt_enable();
 268
 269         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 270                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 271                            dev_priv->csr.mmiodata[i]);
 272         }
 273
 274         dev_priv->csr.dc_state = 0;
 275
 276         gen9_set_dc_state_debugmask(dev_priv);
 277 }
 278
 279 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 280                               const struct firmware *fw)
 281 {
 282         struct intel_css_header *css_header;
 283         struct intel_package_header *package_header;
 284         struct intel_dmc_header *dmc_header;
 285         struct intel_csr *csr = &dev_priv->csr;
 286         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 287         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 288         uint32_t max_fw_size = 0;
 289         uint32_t i;
 290         uint32_t *dmc_payload;
 291         uint32_t required_version;
 292
 293         if (!fw)
 294                 return NULL;
 295
 296         /* Extract CSS Header information*/
 297         css_header = (struct intel_css_header *)fw->data;
 298         if (sizeof(struct intel_css_header) !=
 299             (css_header->header_len * 4)) {
 300                 DRM_ERROR("DMC firmware has wrong CSS header length "
 301                           "(%u bytes)\n",
 302                           (css_header->header_len * 4));
 303                 return NULL;
 304         }
 305
 306         csr->version = css_header->version;
 307
 308         if (csr->fw_path == i915_modparams.dmc_firmware_path) {
 309                 /* Bypass version check for firmware override. */
 310                 required_version = csr->version;
 311         } else if (IS_ICELAKE(dev_priv)) {
 312                 required_version = ICL_CSR_VERSION_REQUIRED;
 313         } else if (IS_CANNONLAKE(dev_priv)) {
 314                 required_version = CNL_CSR_VERSION_REQUIRED;
 315         } else if (IS_GEMINILAKE(dev_priv)) {
 316                 required_version = GLK_CSR_VERSION_REQUIRED;
 317         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 318                 required_version = KBL_CSR_VERSION_REQUIRED;
 319         } else if (IS_SKYLAKE(dev_priv)) {
 320                 required_version = SKL_CSR_VERSION_REQUIRED;
 321         } else if (IS_BROXTON(dev_priv)) {
 322                 required_version = BXT_CSR_VERSION_REQUIRED;
 323         } else {
 324                 MISSING_CASE(INTEL_REVID(dev_priv));
 325                 required_version = 0;
 326         }
 327
 328         if (csr->version != required_version) {
 329                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 330                          " please use v%u.%u\n",
 331                          CSR_VERSION_MAJOR(csr->version),
 332                          CSR_VERSION_MINOR(csr->version),
 333                          CSR_VERSION_MAJOR(required_version),
 334                          CSR_VERSION_MINOR(required_version));
 335                 return NULL;
 336         }
 337
 338         readcount += sizeof(struct intel_css_header);
 339
 340         /* Extract Package Header information*/
 341         package_header = (struct intel_package_header *)
 342                 &fw->data[readcount];
 343         if (sizeof(struct intel_package_header) !=
 344             (package_header->header_len * 4)) {
 345                 DRM_ERROR("DMC firmware has wrong package header length "
 346                           "(%u bytes)\n",
 347                           (package_header->header_len * 4));
 348                 return NULL;
 349         }
 350         readcount += sizeof(struct intel_package_header);
 351
 352         /* Search for dmc_offset to find firware binary. */
 353         for (i = 0; i < package_header->num_entries; i++) {
 354                 if (package_header->fw_info[i].substepping == '*' &&
 355                     si->stepping == package_header->fw_info[i].stepping) {
 356                         dmc_offset = package_header->fw_info[i].offset;
 357                         break;
 358                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 359                            si->substepping == package_header->fw_info[i].substepping) {
 360                         dmc_offset = package_header->fw_info[i].offset;
 361                         break;
 362                 } else if (package_header->fw_info[i].stepping == '*' &&
 363                            package_header->fw_info[i].substepping == '*')
 364                         dmc_offset = package_header->fw_info[i].offset;
 365         }
 366         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 367                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 368                           si->stepping);
 369                 return NULL;
 370         }
 371         /* Convert dmc_offset into number of bytes. By default it is in dwords*/
 372         dmc_offset *= 4;
 373         readcount += dmc_offset;
 374
 375         /* Extract dmc_header information. */
 376         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 377         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 378                 DRM_ERROR("DMC firmware has wrong dmc header length "
 379                           "(%u bytes)\n",
 380                           (dmc_header->header_len));
 381                 return NULL;
 382         }
 383         readcount += sizeof(struct intel_dmc_header);
 384
 385         /* Cache the dmc header info. */
 386         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 387                 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
 388                           dmc_header->mmio_count);
 389                 return NULL;
 390         }
 391         csr->mmio_count = dmc_header->mmio_count;
 392         for (i = 0; i < dmc_header->mmio_count; i++) {
 393                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 394                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 395                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 396                                   dmc_header->mmioaddr[i]);
 397                         return NULL;
 398                 }
 399                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 400                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 401         }
 402
 403         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 404         nbytes = dmc_header->fw_size * 4;
 405         if (INTEL_GEN(dev_priv) >= 11)
 406                 max_fw_size = ICL_CSR_MAX_FW_SIZE;
 407         else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
 408                 max_fw_size = GLK_CSR_MAX_FW_SIZE;
 409         else if (IS_GEN9(dev_priv))
 410                 max_fw_size = BXT_CSR_MAX_FW_SIZE;
 411         else
 412                 MISSING_CASE(INTEL_REVID(dev_priv));
 413         if (nbytes > max_fw_size) {
 414                 DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes);
 415                 return NULL;
 416         }
 417         csr->dmc_fw_size = dmc_header->fw_size;
 418
 419         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 420         if (!dmc_payload) {
 421                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 422                 return NULL;
 423         }
 424
 425         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 426 }
 427
 428 static void csr_load_work_fn(struct work_struct *work)
 429 {
 430         struct drm_i915_private *dev_priv;
 431         struct intel_csr *csr;
 432         const struct firmware *fw = NULL;
 433
 434         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 435         csr = &dev_priv->csr;
 436
 437         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 438         if (fw)
 439                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 440
 441         if (dev_priv->csr.dmc_payload) {
 442                 intel_csr_load_program(dev_priv);
 443
 444                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 445
 446                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 447                          dev_priv->csr.fw_path,
 448                          CSR_VERSION_MAJOR(csr->version),
 449                          CSR_VERSION_MINOR(csr->version));
 450         } else {
 451                 dev_notice(dev_priv->drm.dev,
 452                            "Failed to load DMC firmware %s."
 453                            " Disabling runtime power management.\n",
 454                            csr->fw_path);
 455                 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
 456                            INTEL_UC_FIRMWARE_URL);
 457         }
 458
 459         release_firmware(fw);
 460 }
 461
 462 /**
 463  * intel_csr_ucode_init() - initialize the firmware loading.
 464  * @dev_priv: i915 drm device.
 465  *
 466  * This function is called at the time of loading the display driver to read
 467  * firmware from a .bin file and copied into a internal memory.
 468  */
 469 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 470 {
 471         struct intel_csr *csr = &dev_priv->csr;
 472
 473         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 474
 475         if (!HAS_CSR(dev_priv))
 476                 return;
 477
 478         if (i915_modparams.dmc_firmware_path)
 479                 csr->fw_path = i915_modparams.dmc_firmware_path;
 480         else if (IS_ICELAKE(dev_priv))
 481                 csr->fw_path = I915_CSR_ICL;
 482         else if (IS_CANNONLAKE(dev_priv))
 483                 csr->fw_path = I915_CSR_CNL;
 484         else if (IS_GEMINILAKE(dev_priv))
 485                 csr->fw_path = I915_CSR_GLK;
 486         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 487                 csr->fw_path = I915_CSR_KBL;
 488         else if (IS_SKYLAKE(dev_priv))
 489                 csr->fw_path = I915_CSR_SKL;
 490         else if (IS_BROXTON(dev_priv))
 491                 csr->fw_path = I915_CSR_BXT;
 492
 493         /*
 494          * Obtain a runtime pm reference, until CSR is loaded,
 495          * to avoid entering runtime-suspend.
 496          */
 497         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 498
 499         if (csr->fw_path == NULL) {
 500                 DRM_DEBUG_KMS("No known CSR firmware for platform, disabling runtime PM\n");
 501                 WARN_ON(!IS_ALPHA_SUPPORT(INTEL_INFO(dev_priv)));
 502
 503                 return;
 504         }
 505
 506         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 507         schedule_work(&dev_priv->csr.work);
 508 }
 509
 510 /**
 511  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 512  * @dev_priv: i915 drm device
 513  *
 514  * Prepare the DMC firmware before entering system suspend. This includes
 515  * flushing pending work items and releasing any resources acquired during
 516  * init.
 517  */
 518 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 519 {
 520         if (!HAS_CSR(dev_priv))
 521                 return;
 522
 523         flush_work(&dev_priv->csr.work);
 524
 525         /* Drop the reference held in case DMC isn't loaded. */
 526         if (!dev_priv->csr.dmc_payload)
 527                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 528 }
 529
 530 /**
 531  * intel_csr_ucode_resume() - init CSR firmware during system resume
 532  * @dev_priv: i915 drm device
 533  *
 534  * Reinitialize the DMC firmware during system resume, reacquiring any
 535  * resources released in intel_csr_ucode_suspend().
 536  */
 537 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 538 {
 539         if (!HAS_CSR(dev_priv))
 540                 return;
 541
 542         /*
 543          * Reacquire the reference to keep RPM disabled in case DMC isn't
 544          * loaded.
 545          */
 546         if (!dev_priv->csr.dmc_payload)
 547                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 548 }
 549
 550 /**
 551  * intel_csr_ucode_fini() - unload the CSR firmware.
 552  * @dev_priv: i915 drm device.
 553  *
 554  * Firmmware unloading includes freeing the internal memory and reset the
 555  * firmware loading status.
 556  */
 557 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 558 {
 559         if (!HAS_CSR(dev_priv))
 560                 return;
 561
 562         intel_csr_ucode_suspend(dev_priv);
 563
 564         kfree(dev_priv->csr.dmc_payload);
 565 }