drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  67                             i915_reg_t adpa_reg, enum pipe *pipe)
  68 {
  69         u32 val;
  70
  71         val = I915_READ(adpa_reg);
  72
  73         /* asserts want to know the pipe even if the port is disabled */
  74         if (HAS_PCH_CPT(dev_priv))
  75                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  76         else
  77                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  78
  79         return val & ADPA_DAC_ENABLE;
  80 }
  81
  82 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  83                                    enum pipe *pipe)
  84 {
  85         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  86         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  87         bool ret;
  88
  89         if (!intel_display_power_get_if_enabled(dev_priv,
  90                                                 encoder->power_domain))
  91                 return false;
  92
  93         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
  94
  95         intel_display_power_put(dev_priv, encoder->power_domain);
  96
  97         return ret;
  98 }
  99
 100 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 101 {
 102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 103         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 104         u32 tmp, flags = 0;
 105
 106         tmp = I915_READ(crt->adpa_reg);
 107
 108         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 109                 flags |= DRM_MODE_FLAG_PHSYNC;
 110         else
 111                 flags |= DRM_MODE_FLAG_NHSYNC;
 112
 113         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 114                 flags |= DRM_MODE_FLAG_PVSYNC;
 115         else
 116                 flags |= DRM_MODE_FLAG_NVSYNC;
 117
 118         return flags;
 119 }
 120
 121 static void intel_crt_get_config(struct intel_encoder *encoder,
 122                                  struct intel_crtc_state *pipe_config)
 123 {
 124         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 125
 126         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 127
 128         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 129 }
 130
 131 static void hsw_crt_get_config(struct intel_encoder *encoder,
 132                                struct intel_crtc_state *pipe_config)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 135
 136         intel_ddi_get_config(encoder, pipe_config);
 137
 138         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 139                                               DRM_MODE_FLAG_NHSYNC |
 140                                               DRM_MODE_FLAG_PVSYNC |
 141                                               DRM_MODE_FLAG_NVSYNC);
 142         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 143
 144         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 145 }
 146
 147 /* Note: The caller is required to filter out dpms modes not supported by the
 148  * platform. */
 149 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 150                                const struct intel_crtc_state *crtc_state,
 151                                int mode)
 152 {
 153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 154         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 155         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 156         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 157         u32 adpa;
 158
 159         if (INTEL_GEN(dev_priv) >= 5)
 160                 adpa = ADPA_HOTPLUG_BITS;
 161         else
 162                 adpa = 0;
 163
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 165                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 166         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 167                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 168
 169         /* For CPT allow 3 pipe config, for others just use A or B */
 170         if (HAS_PCH_LPT(dev_priv))
 171                 ; /* Those bits don't exist here */
 172         else if (HAS_PCH_CPT(dev_priv))
 173                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 174         else
 175                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 176
 177         if (!HAS_PCH_SPLIT(dev_priv))
 178                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 179
 180         switch (mode) {
 181         case DRM_MODE_DPMS_ON:
 182                 adpa |= ADPA_DAC_ENABLE;
 183                 break;
 184         case DRM_MODE_DPMS_STANDBY:
 185                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 186                 break;
 187         case DRM_MODE_DPMS_SUSPEND:
 188                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 189                 break;
 190         case DRM_MODE_DPMS_OFF:
 191                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 192                 break;
 193         }
 194
 195         I915_WRITE(crt->adpa_reg, adpa);
 196 }
 197
 198 static void intel_disable_crt(struct intel_encoder *encoder,
 199                               const struct intel_crtc_state *old_crtc_state,
 200                               const struct drm_connector_state *old_conn_state)
 201 {
 202         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder,
 206                             const struct intel_crtc_state *old_crtc_state,
 207                             const struct drm_connector_state *old_conn_state)
 208 {
 209 }
 210
 211 static void pch_post_disable_crt(struct intel_encoder *encoder,
 212                                  const struct intel_crtc_state *old_crtc_state,
 213                                  const struct drm_connector_state *old_conn_state)
 214 {
 215         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 216 }
 217
 218 static void hsw_disable_crt(struct intel_encoder *encoder,
 219                             const struct intel_crtc_state *old_crtc_state,
 220                             const struct drm_connector_state *old_conn_state)
 221 {
 222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 223
 224         WARN_ON(!old_crtc_state->has_pch_encoder);
 225
 226         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 227 }
 228
 229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 230                                  const struct intel_crtc_state *old_crtc_state,
 231                                  const struct drm_connector_state *old_conn_state)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234
 235         intel_ddi_disable_pipe_clock(old_crtc_state);
 236
 237         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 238
 239         lpt_disable_pch_transcoder(dev_priv);
 240         lpt_disable_iclkip(dev_priv);
 241
 242         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 243
 244         WARN_ON(!old_crtc_state->has_pch_encoder);
 245
 246         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 247 }
 248
 249 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 250                                    const struct intel_crtc_state *crtc_state,
 251                                    const struct drm_connector_state *conn_state)
 252 {
 253         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 254
 255         WARN_ON(!crtc_state->has_pch_encoder);
 256
 257         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 258 }
 259
 260 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 261                                const struct intel_crtc_state *crtc_state,
 262                                const struct drm_connector_state *conn_state)
 263 {
 264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 265         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 266         enum pipe pipe = crtc->pipe;
 267
 268         WARN_ON(!crtc_state->has_pch_encoder);
 269
 270         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 271
 272         dev_priv->display.fdi_link_train(crtc, crtc_state);
 273
 274         intel_ddi_enable_pipe_clock(crtc_state);
 275 }
 276
 277 static void hsw_enable_crt(struct intel_encoder *encoder,
 278                            const struct intel_crtc_state *crtc_state,
 279                            const struct drm_connector_state *conn_state)
 280 {
 281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 283         enum pipe pipe = crtc->pipe;
 284
 285         WARN_ON(!crtc_state->has_pch_encoder);
 286
 287         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 288
 289         intel_wait_for_vblank(dev_priv, pipe);
 290         intel_wait_for_vblank(dev_priv, pipe);
 291         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 292         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 293 }
 294
 295 static void intel_enable_crt(struct intel_encoder *encoder,
 296                              const struct intel_crtc_state *crtc_state,
 297                              const struct drm_connector_state *conn_state)
 298 {
 299         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 300 }
 301
 302 static enum drm_mode_status
 303 intel_crt_mode_valid(struct drm_connector *connector,
 304                      struct drm_display_mode *mode)
 305 {
 306         struct drm_device *dev = connector->dev;
 307         struct drm_i915_private *dev_priv = to_i915(dev);
 308         int max_dotclk = dev_priv->max_dotclk_freq;
 309         int max_clock;
 310
 311         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 312                 return MODE_NO_DBLESCAN;
 313
 314         if (mode->clock < 25000)
 315                 return MODE_CLOCK_LOW;
 316
 317         if (HAS_PCH_LPT(dev_priv))
 318                 max_clock = 180000;
 319         else if (IS_VALLEYVIEW(dev_priv))
 320                 /*
 321                  * 270 MHz due to current DPLL limits,
 322                  * DAC limit supposedly 355 MHz.
 323                  */
 324                 max_clock = 270000;
 325         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 326                 max_clock = 400000;
 327         else
 328                 max_clock = 350000;
 329         if (mode->clock > max_clock)
 330                 return MODE_CLOCK_HIGH;
 331
 332         if (mode->clock > max_dotclk)
 333                 return MODE_CLOCK_HIGH;
 334
 335         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 336         if (HAS_PCH_LPT(dev_priv) &&
 337             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 338                 return MODE_CLOCK_HIGH;
 339
 340         /* HSW/BDW FDI limited to 4k */
 341         if (mode->hdisplay > 4096)
 342                 return MODE_H_ILLEGAL;
 343
 344         return MODE_OK;
 345 }
 346
 347 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 348                                      struct intel_crtc_state *pipe_config,
 349                                      struct drm_connector_state *conn_state)
 350 {
 351         struct drm_display_mode *adjusted_mode =
 352                 &pipe_config->base.adjusted_mode;
 353
 354         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 355                 return false;
 356
 357         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 358         return true;
 359 }
 360
 361 static bool pch_crt_compute_config(struct intel_encoder *encoder,
 362                                    struct intel_crtc_state *pipe_config,
 363                                    struct drm_connector_state *conn_state)
 364 {
 365         struct drm_display_mode *adjusted_mode =
 366                 &pipe_config->base.adjusted_mode;
 367
 368         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 369                 return false;
 370
 371         pipe_config->has_pch_encoder = true;
 372         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 373
 374         return true;
 375 }
 376
 377 static bool hsw_crt_compute_config(struct intel_encoder *encoder,
 378                                    struct intel_crtc_state *pipe_config,
 379                                    struct drm_connector_state *conn_state)
 380 {
 381         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 382         struct drm_display_mode *adjusted_mode =
 383                 &pipe_config->base.adjusted_mode;
 384
 385         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 386                 return false;
 387
 388         /* HSW/BDW FDI limited to 4k */
 389         if (adjusted_mode->crtc_hdisplay > 4096 ||
 390             adjusted_mode->crtc_hblank_start > 4096)
 391                 return false;
 392
 393         pipe_config->has_pch_encoder = true;
 394         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 395
 396         /* LPT FDI RX only supports 8bpc. */
 397         if (HAS_PCH_LPT(dev_priv)) {
 398                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 399                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 400                         return false;
 401                 }
 402
 403                 pipe_config->pipe_bpp = 24;
 404         }
 405
 406         /* FDI must always be 2.7 GHz */
 407         pipe_config->port_clock = 135000 * 2;
 408
 409         return true;
 410 }
 411
 412 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 413 {
 414         struct drm_device *dev = connector->dev;
 415         struct intel_crt *crt = intel_attached_crt(connector);
 416         struct drm_i915_private *dev_priv = to_i915(dev);
 417         u32 adpa;
 418         bool ret;
 419
 420         /* The first time through, trigger an explicit detection cycle */
 421         if (crt->force_hotplug_required) {
 422                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 423                 u32 save_adpa;
 424
 425                 crt->force_hotplug_required = 0;
 426
 427                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 428                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 429
 430                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 431                 if (turn_off_dac)
 432                         adpa &= ~ADPA_DAC_ENABLE;
 433
 434                 I915_WRITE(crt->adpa_reg, adpa);
 435
 436                 if (intel_wait_for_register(dev_priv,
 437                                             crt->adpa_reg,
 438                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 439                                             1000))
 440                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 441
 442                 if (turn_off_dac) {
 443                         I915_WRITE(crt->adpa_reg, save_adpa);
 444                         POSTING_READ(crt->adpa_reg);
 445                 }
 446         }
 447
 448         /* Check the status to see if both blue and green are on now */
 449         adpa = I915_READ(crt->adpa_reg);
 450         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 451                 ret = true;
 452         else
 453                 ret = false;
 454         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 455
 456         return ret;
 457 }
 458
 459 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 460 {
 461         struct drm_device *dev = connector->dev;
 462         struct intel_crt *crt = intel_attached_crt(connector);
 463         struct drm_i915_private *dev_priv = to_i915(dev);
 464         bool reenable_hpd;
 465         u32 adpa;
 466         bool ret;
 467         u32 save_adpa;
 468
 469         /*
 470          * Doing a force trigger causes a hpd interrupt to get sent, which can
 471          * get us stuck in a loop if we're polling:
 472          *  - We enable power wells and reset the ADPA
 473          *  - output_poll_exec does force probe on VGA, triggering a hpd
 474          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 475          *  - output_poll_exec shuts off the ADPA, unlocks
 476          *    dev->mode_config.mutex
 477          *  - HPD handler runs, resets ADPA and brings us back to the start
 478          *
 479          * Just disable HPD interrupts here to prevent this
 480          */
 481         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 482
 483         save_adpa = adpa = I915_READ(crt->adpa_reg);
 484         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 485
 486         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 487
 488         I915_WRITE(crt->adpa_reg, adpa);
 489
 490         if (intel_wait_for_register(dev_priv,
 491                                     crt->adpa_reg,
 492                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 493                                     1000)) {
 494                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 495                 I915_WRITE(crt->adpa_reg, save_adpa);
 496         }
 497
 498         /* Check the status to see if both blue and green are on now */
 499         adpa = I915_READ(crt->adpa_reg);
 500         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 501                 ret = true;
 502         else
 503                 ret = false;
 504
 505         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 506
 507         if (reenable_hpd)
 508                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 509
 510         return ret;
 511 }
 512
 513 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 514 {
 515         struct drm_device *dev = connector->dev;
 516         struct drm_i915_private *dev_priv = to_i915(dev);
 517         u32 stat;
 518         bool ret = false;
 519         int i, tries = 0;
 520
 521         if (HAS_PCH_SPLIT(dev_priv))
 522                 return intel_ironlake_crt_detect_hotplug(connector);
 523
 524         if (IS_VALLEYVIEW(dev_priv))
 525                 return valleyview_crt_detect_hotplug(connector);
 526
 527         /*
 528          * On 4 series desktop, CRT detect sequence need to be done twice
 529          * to get a reliable result.
 530          */
 531
 532         if (IS_G45(dev_priv))
 533                 tries = 2;
 534         else
 535                 tries = 1;
 536
 537         for (i = 0; i < tries ; i++) {
 538                 /* turn on the FORCE_DETECT */
 539                 i915_hotplug_interrupt_update(dev_priv,
 540                                               CRT_HOTPLUG_FORCE_DETECT,
 541                                               CRT_HOTPLUG_FORCE_DETECT);
 542                 /* wait for FORCE_DETECT to go off */
 543                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 544                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 545                                             1000))
 546                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 547         }
 548
 549         stat = I915_READ(PORT_HOTPLUG_STAT);
 550         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 551                 ret = true;
 552
 553         /* clear the interrupt we just generated, if any */
 554         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 555
 556         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 557
 558         return ret;
 559 }
 560
 561 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 562                                 struct i2c_adapter *i2c)
 563 {
 564         struct edid *edid;
 565
 566         edid = drm_get_edid(connector, i2c);
 567
 568         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 569                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 570                 intel_gmbus_force_bit(i2c, true);
 571                 edid = drm_get_edid(connector, i2c);
 572                 intel_gmbus_force_bit(i2c, false);
 573         }
 574
 575         return edid;
 576 }
 577
 578 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 579 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 580                                 struct i2c_adapter *adapter)
 581 {
 582         struct edid *edid;
 583         int ret;
 584
 585         edid = intel_crt_get_edid(connector, adapter);
 586         if (!edid)
 587                 return 0;
 588
 589         ret = intel_connector_update_modes(connector, edid);
 590         kfree(edid);
 591
 592         return ret;
 593 }
 594
 595 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 596 {
 597         struct intel_crt *crt = intel_attached_crt(connector);
 598         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 599         struct edid *edid;
 600         struct i2c_adapter *i2c;
 601         bool ret = false;
 602
 603         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 604
 605         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 606         edid = intel_crt_get_edid(connector, i2c);
 607
 608         if (edid) {
 609                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 610
 611                 /*
 612                  * This may be a DVI-I connector with a shared DDC
 613                  * link between analog and digital outputs, so we
 614                  * have to check the EDID input spec of the attached device.
 615                  */
 616                 if (!is_digital) {
 617                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 618                         ret = true;
 619                 } else {
 620                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 621                 }
 622         } else {
 623                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 624         }
 625
 626         kfree(edid);
 627
 628         return ret;
 629 }
 630
 631 static enum drm_connector_status
 632 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 633 {
 634         struct drm_device *dev = crt->base.base.dev;
 635         struct drm_i915_private *dev_priv = to_i915(dev);
 636         uint32_t save_bclrpat;
 637         uint32_t save_vtotal;
 638         uint32_t vtotal, vactive;
 639         uint32_t vsample;
 640         uint32_t vblank, vblank_start, vblank_end;
 641         uint32_t dsl;
 642         i915_reg_t bclrpat_reg, vtotal_reg,
 643                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 644         uint8_t st00;
 645         enum drm_connector_status status;
 646
 647         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 648
 649         bclrpat_reg = BCLRPAT(pipe);
 650         vtotal_reg = VTOTAL(pipe);
 651         vblank_reg = VBLANK(pipe);
 652         vsync_reg = VSYNC(pipe);
 653         pipeconf_reg = PIPECONF(pipe);
 654         pipe_dsl_reg = PIPEDSL(pipe);
 655
 656         save_bclrpat = I915_READ(bclrpat_reg);
 657         save_vtotal = I915_READ(vtotal_reg);
 658         vblank = I915_READ(vblank_reg);
 659
 660         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 661         vactive = (save_vtotal & 0x7ff) + 1;
 662
 663         vblank_start = (vblank & 0xfff) + 1;
 664         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 665
 666         /* Set the border color to purple. */
 667         I915_WRITE(bclrpat_reg, 0x500050);
 668
 669         if (!IS_GEN2(dev_priv)) {
 670                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 671                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 672                 POSTING_READ(pipeconf_reg);
 673                 /* Wait for next Vblank to substitue
 674                  * border color for Color info */
 675                 intel_wait_for_vblank(dev_priv, pipe);
 676                 st00 = I915_READ8(_VGA_MSR_WRITE);
 677                 status = ((st00 & (1 << 4)) != 0) ?
 678                         connector_status_connected :
 679                         connector_status_disconnected;
 680
 681                 I915_WRITE(pipeconf_reg, pipeconf);
 682         } else {
 683                 bool restore_vblank = false;
 684                 int count, detect;
 685
 686                 /*
 687                 * If there isn't any border, add some.
 688                 * Yes, this will flicker
 689                 */
 690                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 691                         uint32_t vsync = I915_READ(vsync_reg);
 692                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 693
 694                         vblank_start = vsync_start;
 695                         I915_WRITE(vblank_reg,
 696                                    (vblank_start - 1) |
 697                                    ((vblank_end - 1) << 16));
 698                         restore_vblank = true;
 699                 }
 700                 /* sample in the vertical border, selecting the larger one */
 701                 if (vblank_start - vactive >= vtotal - vblank_end)
 702                         vsample = (vblank_start + vactive) >> 1;
 703                 else
 704                         vsample = (vtotal + vblank_end) >> 1;
 705
 706                 /*
 707                  * Wait for the border to be displayed
 708                  */
 709                 while (I915_READ(pipe_dsl_reg) >= vactive)
 710                         ;
 711                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 712                         ;
 713                 /*
 714                  * Watch ST00 for an entire scanline
 715                  */
 716                 detect = 0;
 717                 count = 0;
 718                 do {
 719                         count++;
 720                         /* Read the ST00 VGA status register */
 721                         st00 = I915_READ8(_VGA_MSR_WRITE);
 722                         if (st00 & (1 << 4))
 723                                 detect++;
 724                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 725
 726                 /* restore vblank if necessary */
 727                 if (restore_vblank)
 728                         I915_WRITE(vblank_reg, vblank);
 729                 /*
 730                  * If more than 3/4 of the scanline detected a monitor,
 731                  * then it is assumed to be present. This works even on i830,
 732                  * where there isn't any way to force the border color across
 733                  * the screen
 734                  */
 735                 status = detect * 4 > count * 3 ?
 736                          connector_status_connected :
 737                          connector_status_disconnected;
 738         }
 739
 740         /* Restore previous settings */
 741         I915_WRITE(bclrpat_reg, save_bclrpat);
 742
 743         return status;
 744 }
 745
 746 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 747 {
 748         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 749         return 1;
 750 }
 751
 752 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 753         {
 754                 .callback = intel_spurious_crt_detect_dmi_callback,
 755                 .ident = "ACER ZGB",
 756                 .matches = {
 757                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 758                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 759                 },
 760         },
 761         {
 762                 .callback = intel_spurious_crt_detect_dmi_callback,
 763                 .ident = "Intel DZ77BH-55K",
 764                 .matches = {
 765                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 766                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 767                 },
 768         },
 769         { }
 770 };
 771
 772 static int
 773 intel_crt_detect(struct drm_connector *connector,
 774                  struct drm_modeset_acquire_ctx *ctx,
 775                  bool force)
 776 {
 777         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 778         struct intel_crt *crt = intel_attached_crt(connector);
 779         struct intel_encoder *intel_encoder = &crt->base;
 780         int status, ret;
 781         struct intel_load_detect_pipe tmp;
 782
 783         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 784                       connector->base.id, connector->name,
 785                       force);
 786
 787         if (i915_modparams.load_detect_test) {
 788                 intel_display_power_get(dev_priv, intel_encoder->power_domain);
 789                 goto load_detect;
 790         }
 791
 792         /* Skip machines without VGA that falsely report hotplug events */
 793         if (dmi_check_system(intel_spurious_crt_detect))
 794                 return connector_status_disconnected;
 795
 796         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 797
 798         if (I915_HAS_HOTPLUG(dev_priv)) {
 799                 /* We can not rely on the HPD pin always being correctly wired
 800                  * up, for example many KVM do not pass it through, and so
 801                  * only trust an assertion that the monitor is connected.
 802                  */
 803                 if (intel_crt_detect_hotplug(connector)) {
 804                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 805                         status = connector_status_connected;
 806                         goto out;
 807                 } else
 808                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 809         }
 810
 811         if (intel_crt_detect_ddc(connector)) {
 812                 status = connector_status_connected;
 813                 goto out;
 814         }
 815
 816         /* Load detection is broken on HPD capable machines. Whoever wants a
 817          * broken monitor (without edid) to work behind a broken kvm (that fails
 818          * to have the right resistors for HP detection) needs to fix this up.
 819          * For now just bail out. */
 820         if (I915_HAS_HOTPLUG(dev_priv)) {
 821                 status = connector_status_disconnected;
 822                 goto out;
 823         }
 824
 825 load_detect:
 826         if (!force) {
 827                 status = connector->status;
 828                 goto out;
 829         }
 830
 831         /* for pre-945g platforms use load detect */
 832         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 833         if (ret > 0) {
 834                 if (intel_crt_detect_ddc(connector))
 835                         status = connector_status_connected;
 836                 else if (INTEL_GEN(dev_priv) < 4)
 837                         status = intel_crt_load_detect(crt,
 838                                 to_intel_crtc(connector->state->crtc)->pipe);
 839                 else if (i915_modparams.load_detect_test)
 840                         status = connector_status_disconnected;
 841                 else
 842                         status = connector_status_unknown;
 843                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 844         } else if (ret == 0) {
 845                 status = connector_status_unknown;
 846         } else {
 847                 status = ret;
 848         }
 849
 850 out:
 851         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 852         return status;
 853 }
 854
 855 static int intel_crt_get_modes(struct drm_connector *connector)
 856 {
 857         struct drm_device *dev = connector->dev;
 858         struct drm_i915_private *dev_priv = to_i915(dev);
 859         struct intel_crt *crt = intel_attached_crt(connector);
 860         struct intel_encoder *intel_encoder = &crt->base;
 861         int ret;
 862         struct i2c_adapter *i2c;
 863
 864         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 865
 866         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 867         ret = intel_crt_ddc_get_modes(connector, i2c);
 868         if (ret || !IS_G4X(dev_priv))
 869                 goto out;
 870
 871         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 872         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 873         ret = intel_crt_ddc_get_modes(connector, i2c);
 874
 875 out:
 876         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 877
 878         return ret;
 879 }
 880
 881 void intel_crt_reset(struct drm_encoder *encoder)
 882 {
 883         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 884         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 885
 886         if (INTEL_GEN(dev_priv) >= 5) {
 887                 u32 adpa;
 888
 889                 adpa = I915_READ(crt->adpa_reg);
 890                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 891                 adpa |= ADPA_HOTPLUG_BITS;
 892                 I915_WRITE(crt->adpa_reg, adpa);
 893                 POSTING_READ(crt->adpa_reg);
 894
 895                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 896                 crt->force_hotplug_required = 1;
 897         }
 898
 899 }
 900
 901 /*
 902  * Routines for controlling stuff on the analog port
 903  */
 904
 905 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 906         .fill_modes = drm_helper_probe_single_connector_modes,
 907         .late_register = intel_connector_register,
 908         .early_unregister = intel_connector_unregister,
 909         .destroy = intel_connector_destroy,
 910         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 911         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 912 };
 913
 914 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 915         .detect_ctx = intel_crt_detect,
 916         .mode_valid = intel_crt_mode_valid,
 917         .get_modes = intel_crt_get_modes,
 918 };
 919
 920 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 921         .reset = intel_crt_reset,
 922         .destroy = intel_encoder_destroy,
 923 };
 924
 925 void intel_crt_init(struct drm_i915_private *dev_priv)
 926 {
 927         struct drm_connector *connector;
 928         struct intel_crt *crt;
 929         struct intel_connector *intel_connector;
 930         i915_reg_t adpa_reg;
 931         u32 adpa;
 932
 933         if (HAS_PCH_SPLIT(dev_priv))
 934                 adpa_reg = PCH_ADPA;
 935         else if (IS_VALLEYVIEW(dev_priv))
 936                 adpa_reg = VLV_ADPA;
 937         else
 938                 adpa_reg = ADPA;
 939
 940         adpa = I915_READ(adpa_reg);
 941         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 942                 /*
 943                  * On some machines (some IVB at least) CRT can be
 944                  * fused off, but there's no known fuse bit to
 945                  * indicate that. On these machine the ADPA register
 946                  * works normally, except the DAC enable bit won't
 947                  * take. So the only way to tell is attempt to enable
 948                  * it and see what happens.
 949                  */
 950                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 951                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 952                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 953                         return;
 954                 I915_WRITE(adpa_reg, adpa);
 955         }
 956
 957         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 958         if (!crt)
 959                 return;
 960
 961         intel_connector = intel_connector_alloc();
 962         if (!intel_connector) {
 963                 kfree(crt);
 964                 return;
 965         }
 966
 967         connector = &intel_connector->base;
 968         crt->connector = intel_connector;
 969         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 970                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 971
 972         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 973                          DRM_MODE_ENCODER_DAC, "CRT");
 974
 975         intel_connector_attach_encoder(intel_connector, &crt->base);
 976
 977         crt->base.type = INTEL_OUTPUT_ANALOG;
 978         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 979         if (IS_I830(dev_priv))
 980                 crt->base.crtc_mask = (1 << 0);
 981         else
 982                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 983
 984         if (IS_GEN2(dev_priv))
 985                 connector->interlace_allowed = 0;
 986         else
 987                 connector->interlace_allowed = 1;
 988         connector->doublescan_allowed = 0;
 989
 990         crt->adpa_reg = adpa_reg;
 991
 992         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 993
 994         if (I915_HAS_HOTPLUG(dev_priv) &&
 995             !dmi_check_system(intel_spurious_crt_detect)) {
 996                 crt->base.hpd_pin = HPD_CRT;
 997                 crt->base.hotplug = intel_encoder_hotplug;
 998         }
 999
1000         if (HAS_DDI(dev_priv)) {
1001                 crt->base.port = PORT_E;
1002                 crt->base.get_config = hsw_crt_get_config;
1003                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1004                 crt->base.compute_config = hsw_crt_compute_config;
1005                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1006                 crt->base.pre_enable = hsw_pre_enable_crt;
1007                 crt->base.enable = hsw_enable_crt;
1008                 crt->base.disable = hsw_disable_crt;
1009                 crt->base.post_disable = hsw_post_disable_crt;
1010         } else {
1011                 if (HAS_PCH_SPLIT(dev_priv)) {
1012                         crt->base.compute_config = pch_crt_compute_config;
1013                         crt->base.disable = pch_disable_crt;
1014                         crt->base.post_disable = pch_post_disable_crt;
1015                 } else {
1016                         crt->base.compute_config = intel_crt_compute_config;
1017                         crt->base.disable = intel_disable_crt;
1018                 }
1019                 crt->base.port = PORT_NONE;
1020                 crt->base.get_config = intel_crt_get_config;
1021                 crt->base.get_hw_state = intel_crt_get_hw_state;
1022                 crt->base.enable = intel_enable_crt;
1023         }
1024         intel_connector->get_hw_state = intel_connector_get_hw_state;
1025
1026         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1027
1028         if (!I915_HAS_HOTPLUG(dev_priv))
1029                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1030
1031         /*
1032          * Configure the automatic hotplug detection stuff
1033          */
1034         crt->force_hotplug_required = 0;
1035
1036         /*
1037          * TODO: find a proper way to discover whether we need to set the the
1038          * polarity and link reversal bits or not, instead of relying on the
1039          * BIOS.
1040          */
1041         if (HAS_PCH_LPT(dev_priv)) {
1042                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1043                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1044
1045                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1046         }
1047
1048         intel_crt_reset(&crt->base.base);
1049 }