drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  67                             i915_reg_t adpa_reg, enum pipe *pipe)
  68 {
  69         u32 val;
  70
  71         val = I915_READ(adpa_reg);
  72
  73         /* asserts want to know the pipe even if the port is disabled */
  74         if (HAS_PCH_CPT(dev_priv))
  75                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  76         else
  77                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  78
  79         return val & ADPA_DAC_ENABLE;
  80 }
  81
  82 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  83                                    enum pipe *pipe)
  84 {
  85         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  86         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  87         bool ret;
  88
  89         if (!intel_display_power_get_if_enabled(dev_priv,
  90                                                 encoder->power_domain))
  91                 return false;
  92
  93         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
  94
  95         intel_display_power_put(dev_priv, encoder->power_domain);
  96
  97         return ret;
  98 }
  99
 100 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 101 {
 102         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 103         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 104         u32 tmp, flags = 0;
 105
 106         tmp = I915_READ(crt->adpa_reg);
 107
 108         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 109                 flags |= DRM_MODE_FLAG_PHSYNC;
 110         else
 111                 flags |= DRM_MODE_FLAG_NHSYNC;
 112
 113         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 114                 flags |= DRM_MODE_FLAG_PVSYNC;
 115         else
 116                 flags |= DRM_MODE_FLAG_NVSYNC;
 117
 118         return flags;
 119 }
 120
 121 static void intel_crt_get_config(struct intel_encoder *encoder,
 122                                  struct intel_crtc_state *pipe_config)
 123 {
 124         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 125
 126         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 127
 128         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 129 }
 130
 131 static void hsw_crt_get_config(struct intel_encoder *encoder,
 132                                struct intel_crtc_state *pipe_config)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 135
 136         intel_ddi_get_config(encoder, pipe_config);
 137
 138         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 139                                               DRM_MODE_FLAG_NHSYNC |
 140                                               DRM_MODE_FLAG_PVSYNC |
 141                                               DRM_MODE_FLAG_NVSYNC);
 142         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 143
 144         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 145 }
 146
 147 /* Note: The caller is required to filter out dpms modes not supported by the
 148  * platform. */
 149 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 150                                const struct intel_crtc_state *crtc_state,
 151                                int mode)
 152 {
 153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 154         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 155         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 156         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 157         u32 adpa;
 158
 159         if (INTEL_GEN(dev_priv) >= 5)
 160                 adpa = ADPA_HOTPLUG_BITS;
 161         else
 162                 adpa = 0;
 163
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 165                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 166         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 167                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 168
 169         /* For CPT allow 3 pipe config, for others just use A or B */
 170         if (HAS_PCH_LPT(dev_priv))
 171                 ; /* Those bits don't exist here */
 172         else if (HAS_PCH_CPT(dev_priv))
 173                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 174         else
 175                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 176
 177         if (!HAS_PCH_SPLIT(dev_priv))
 178                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 179
 180         switch (mode) {
 181         case DRM_MODE_DPMS_ON:
 182                 adpa |= ADPA_DAC_ENABLE;
 183                 break;
 184         case DRM_MODE_DPMS_STANDBY:
 185                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 186                 break;
 187         case DRM_MODE_DPMS_SUSPEND:
 188                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 189                 break;
 190         case DRM_MODE_DPMS_OFF:
 191                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 192                 break;
 193         }
 194
 195         I915_WRITE(crt->adpa_reg, adpa);
 196 }
 197
 198 static void intel_disable_crt(struct intel_encoder *encoder,
 199                               const struct intel_crtc_state *old_crtc_state,
 200                               const struct drm_connector_state *old_conn_state)
 201 {
 202         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder,
 206                             const struct intel_crtc_state *old_crtc_state,
 207                             const struct drm_connector_state *old_conn_state)
 208 {
 209 }
 210
 211 static void pch_post_disable_crt(struct intel_encoder *encoder,
 212                                  const struct intel_crtc_state *old_crtc_state,
 213                                  const struct drm_connector_state *old_conn_state)
 214 {
 215         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 216 }
 217
 218 static void hsw_disable_crt(struct intel_encoder *encoder,
 219                             const struct intel_crtc_state *old_crtc_state,
 220                             const struct drm_connector_state *old_conn_state)
 221 {
 222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 223
 224         WARN_ON(!old_crtc_state->has_pch_encoder);
 225
 226         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 227 }
 228
 229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 230                                  const struct intel_crtc_state *old_crtc_state,
 231                                  const struct drm_connector_state *old_conn_state)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234
 235         intel_ddi_disable_pipe_clock(old_crtc_state);
 236
 237         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 238
 239         lpt_disable_pch_transcoder(dev_priv);
 240         lpt_disable_iclkip(dev_priv);
 241
 242         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 243
 244         WARN_ON(!old_crtc_state->has_pch_encoder);
 245
 246         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 247 }
 248
 249 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 250                                    const struct intel_crtc_state *crtc_state,
 251                                    const struct drm_connector_state *conn_state)
 252 {
 253         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 254
 255         WARN_ON(!crtc_state->has_pch_encoder);
 256
 257         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 258 }
 259
 260 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 261                                const struct intel_crtc_state *crtc_state,
 262                                const struct drm_connector_state *conn_state)
 263 {
 264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 265         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 266         enum pipe pipe = crtc->pipe;
 267
 268         WARN_ON(!crtc_state->has_pch_encoder);
 269
 270         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 271
 272         dev_priv->display.fdi_link_train(crtc, crtc_state);
 273
 274         intel_ddi_enable_pipe_clock(crtc_state);
 275 }
 276
 277 static void hsw_enable_crt(struct intel_encoder *encoder,
 278                            const struct intel_crtc_state *crtc_state,
 279                            const struct drm_connector_state *conn_state)
 280 {
 281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 283         enum pipe pipe = crtc->pipe;
 284
 285         WARN_ON(!crtc_state->has_pch_encoder);
 286
 287         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 288
 289         intel_wait_for_vblank(dev_priv, pipe);
 290         intel_wait_for_vblank(dev_priv, pipe);
 291         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 292         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 293 }
 294
 295 static void intel_enable_crt(struct intel_encoder *encoder,
 296                              const struct intel_crtc_state *crtc_state,
 297                              const struct drm_connector_state *conn_state)
 298 {
 299         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 300 }
 301
 302 static enum drm_mode_status
 303 intel_crt_mode_valid(struct drm_connector *connector,
 304                      struct drm_display_mode *mode)
 305 {
 306         struct drm_device *dev = connector->dev;
 307         struct drm_i915_private *dev_priv = to_i915(dev);
 308         int max_dotclk = dev_priv->max_dotclk_freq;
 309         int max_clock;
 310
 311         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 312                 return MODE_NO_DBLESCAN;
 313
 314         if (mode->clock < 25000)
 315                 return MODE_CLOCK_LOW;
 316
 317         if (HAS_PCH_LPT(dev_priv))
 318                 max_clock = 180000;
 319         else if (IS_VALLEYVIEW(dev_priv))
 320                 /*
 321                  * 270 MHz due to current DPLL limits,
 322                  * DAC limit supposedly 355 MHz.
 323                  */
 324                 max_clock = 270000;
 325         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 326                 max_clock = 400000;
 327         else
 328                 max_clock = 350000;
 329         if (mode->clock > max_clock)
 330                 return MODE_CLOCK_HIGH;
 331
 332         if (mode->clock > max_dotclk)
 333                 return MODE_CLOCK_HIGH;
 334
 335         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 336         if (HAS_PCH_LPT(dev_priv) &&
 337             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 338                 return MODE_CLOCK_HIGH;
 339
 340         /* HSW/BDW FDI limited to 4k */
 341         if (mode->hdisplay > 4096)
 342                 return MODE_H_ILLEGAL;
 343
 344         return MODE_OK;
 345 }
 346
 347 static int intel_crt_compute_config(struct intel_encoder *encoder,
 348                                     struct intel_crtc_state *pipe_config,
 349                                     struct drm_connector_state *conn_state)
 350 {
 351         struct drm_display_mode *adjusted_mode =
 352                 &pipe_config->base.adjusted_mode;
 353
 354         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 355                 return -EINVAL;
 356
 357         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 358
 359         return 0;
 360 }
 361
 362 static int pch_crt_compute_config(struct intel_encoder *encoder,
 363                                   struct intel_crtc_state *pipe_config,
 364                                   struct drm_connector_state *conn_state)
 365 {
 366         struct drm_display_mode *adjusted_mode =
 367                 &pipe_config->base.adjusted_mode;
 368
 369         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 370                 return -EINVAL;
 371
 372         pipe_config->has_pch_encoder = true;
 373         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 374
 375         return 0;
 376 }
 377
 378 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 379                                   struct intel_crtc_state *pipe_config,
 380                                   struct drm_connector_state *conn_state)
 381 {
 382         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 383         struct drm_display_mode *adjusted_mode =
 384                 &pipe_config->base.adjusted_mode;
 385
 386         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 387                 return -EINVAL;
 388
 389         /* HSW/BDW FDI limited to 4k */
 390         if (adjusted_mode->crtc_hdisplay > 4096 ||
 391             adjusted_mode->crtc_hblank_start > 4096)
 392                 return -EINVAL;
 393
 394         pipe_config->has_pch_encoder = true;
 395         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 396
 397         /* LPT FDI RX only supports 8bpc. */
 398         if (HAS_PCH_LPT(dev_priv)) {
 399                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 400                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 401                         return -EINVAL;
 402                 }
 403
 404                 pipe_config->pipe_bpp = 24;
 405         }
 406
 407         /* FDI must always be 2.7 GHz */
 408         pipe_config->port_clock = 135000 * 2;
 409
 410         return 0;
 411 }
 412
 413 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 414 {
 415         struct drm_device *dev = connector->dev;
 416         struct intel_crt *crt = intel_attached_crt(connector);
 417         struct drm_i915_private *dev_priv = to_i915(dev);
 418         u32 adpa;
 419         bool ret;
 420
 421         /* The first time through, trigger an explicit detection cycle */
 422         if (crt->force_hotplug_required) {
 423                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 424                 u32 save_adpa;
 425
 426                 crt->force_hotplug_required = 0;
 427
 428                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 429                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 430
 431                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 432                 if (turn_off_dac)
 433                         adpa &= ~ADPA_DAC_ENABLE;
 434
 435                 I915_WRITE(crt->adpa_reg, adpa);
 436
 437                 if (intel_wait_for_register(dev_priv,
 438                                             crt->adpa_reg,
 439                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 440                                             1000))
 441                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 442
 443                 if (turn_off_dac) {
 444                         I915_WRITE(crt->adpa_reg, save_adpa);
 445                         POSTING_READ(crt->adpa_reg);
 446                 }
 447         }
 448
 449         /* Check the status to see if both blue and green are on now */
 450         adpa = I915_READ(crt->adpa_reg);
 451         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 452                 ret = true;
 453         else
 454                 ret = false;
 455         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 456
 457         return ret;
 458 }
 459
 460 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 461 {
 462         struct drm_device *dev = connector->dev;
 463         struct intel_crt *crt = intel_attached_crt(connector);
 464         struct drm_i915_private *dev_priv = to_i915(dev);
 465         bool reenable_hpd;
 466         u32 adpa;
 467         bool ret;
 468         u32 save_adpa;
 469
 470         /*
 471          * Doing a force trigger causes a hpd interrupt to get sent, which can
 472          * get us stuck in a loop if we're polling:
 473          *  - We enable power wells and reset the ADPA
 474          *  - output_poll_exec does force probe on VGA, triggering a hpd
 475          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 476          *  - output_poll_exec shuts off the ADPA, unlocks
 477          *    dev->mode_config.mutex
 478          *  - HPD handler runs, resets ADPA and brings us back to the start
 479          *
 480          * Just disable HPD interrupts here to prevent this
 481          */
 482         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 483
 484         save_adpa = adpa = I915_READ(crt->adpa_reg);
 485         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 486
 487         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 488
 489         I915_WRITE(crt->adpa_reg, adpa);
 490
 491         if (intel_wait_for_register(dev_priv,
 492                                     crt->adpa_reg,
 493                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 494                                     1000)) {
 495                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 496                 I915_WRITE(crt->adpa_reg, save_adpa);
 497         }
 498
 499         /* Check the status to see if both blue and green are on now */
 500         adpa = I915_READ(crt->adpa_reg);
 501         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 502                 ret = true;
 503         else
 504                 ret = false;
 505
 506         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 507
 508         if (reenable_hpd)
 509                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 510
 511         return ret;
 512 }
 513
 514 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 515 {
 516         struct drm_device *dev = connector->dev;
 517         struct drm_i915_private *dev_priv = to_i915(dev);
 518         u32 stat;
 519         bool ret = false;
 520         int i, tries = 0;
 521
 522         if (HAS_PCH_SPLIT(dev_priv))
 523                 return intel_ironlake_crt_detect_hotplug(connector);
 524
 525         if (IS_VALLEYVIEW(dev_priv))
 526                 return valleyview_crt_detect_hotplug(connector);
 527
 528         /*
 529          * On 4 series desktop, CRT detect sequence need to be done twice
 530          * to get a reliable result.
 531          */
 532
 533         if (IS_G45(dev_priv))
 534                 tries = 2;
 535         else
 536                 tries = 1;
 537
 538         for (i = 0; i < tries ; i++) {
 539                 /* turn on the FORCE_DETECT */
 540                 i915_hotplug_interrupt_update(dev_priv,
 541                                               CRT_HOTPLUG_FORCE_DETECT,
 542                                               CRT_HOTPLUG_FORCE_DETECT);
 543                 /* wait for FORCE_DETECT to go off */
 544                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 545                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 546                                             1000))
 547                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 548         }
 549
 550         stat = I915_READ(PORT_HOTPLUG_STAT);
 551         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 552                 ret = true;
 553
 554         /* clear the interrupt we just generated, if any */
 555         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 556
 557         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 558
 559         return ret;
 560 }
 561
 562 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 563                                 struct i2c_adapter *i2c)
 564 {
 565         struct edid *edid;
 566
 567         edid = drm_get_edid(connector, i2c);
 568
 569         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 570                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 571                 intel_gmbus_force_bit(i2c, true);
 572                 edid = drm_get_edid(connector, i2c);
 573                 intel_gmbus_force_bit(i2c, false);
 574         }
 575
 576         return edid;
 577 }
 578
 579 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 580 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 581                                 struct i2c_adapter *adapter)
 582 {
 583         struct edid *edid;
 584         int ret;
 585
 586         edid = intel_crt_get_edid(connector, adapter);
 587         if (!edid)
 588                 return 0;
 589
 590         ret = intel_connector_update_modes(connector, edid);
 591         kfree(edid);
 592
 593         return ret;
 594 }
 595
 596 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 597 {
 598         struct intel_crt *crt = intel_attached_crt(connector);
 599         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 600         struct edid *edid;
 601         struct i2c_adapter *i2c;
 602         bool ret = false;
 603
 604         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 605
 606         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 607         edid = intel_crt_get_edid(connector, i2c);
 608
 609         if (edid) {
 610                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 611
 612                 /*
 613                  * This may be a DVI-I connector with a shared DDC
 614                  * link between analog and digital outputs, so we
 615                  * have to check the EDID input spec of the attached device.
 616                  */
 617                 if (!is_digital) {
 618                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 619                         ret = true;
 620                 } else {
 621                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 622                 }
 623         } else {
 624                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 625         }
 626
 627         kfree(edid);
 628
 629         return ret;
 630 }
 631
 632 static enum drm_connector_status
 633 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 634 {
 635         struct drm_device *dev = crt->base.base.dev;
 636         struct drm_i915_private *dev_priv = to_i915(dev);
 637         uint32_t save_bclrpat;
 638         uint32_t save_vtotal;
 639         uint32_t vtotal, vactive;
 640         uint32_t vsample;
 641         uint32_t vblank, vblank_start, vblank_end;
 642         uint32_t dsl;
 643         i915_reg_t bclrpat_reg, vtotal_reg,
 644                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 645         uint8_t st00;
 646         enum drm_connector_status status;
 647
 648         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 649
 650         bclrpat_reg = BCLRPAT(pipe);
 651         vtotal_reg = VTOTAL(pipe);
 652         vblank_reg = VBLANK(pipe);
 653         vsync_reg = VSYNC(pipe);
 654         pipeconf_reg = PIPECONF(pipe);
 655         pipe_dsl_reg = PIPEDSL(pipe);
 656
 657         save_bclrpat = I915_READ(bclrpat_reg);
 658         save_vtotal = I915_READ(vtotal_reg);
 659         vblank = I915_READ(vblank_reg);
 660
 661         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 662         vactive = (save_vtotal & 0x7ff) + 1;
 663
 664         vblank_start = (vblank & 0xfff) + 1;
 665         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 666
 667         /* Set the border color to purple. */
 668         I915_WRITE(bclrpat_reg, 0x500050);
 669
 670         if (!IS_GEN2(dev_priv)) {
 671                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 672                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 673                 POSTING_READ(pipeconf_reg);
 674                 /* Wait for next Vblank to substitue
 675                  * border color for Color info */
 676                 intel_wait_for_vblank(dev_priv, pipe);
 677                 st00 = I915_READ8(_VGA_MSR_WRITE);
 678                 status = ((st00 & (1 << 4)) != 0) ?
 679                         connector_status_connected :
 680                         connector_status_disconnected;
 681
 682                 I915_WRITE(pipeconf_reg, pipeconf);
 683         } else {
 684                 bool restore_vblank = false;
 685                 int count, detect;
 686
 687                 /*
 688                 * If there isn't any border, add some.
 689                 * Yes, this will flicker
 690                 */
 691                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 692                         uint32_t vsync = I915_READ(vsync_reg);
 693                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 694
 695                         vblank_start = vsync_start;
 696                         I915_WRITE(vblank_reg,
 697                                    (vblank_start - 1) |
 698                                    ((vblank_end - 1) << 16));
 699                         restore_vblank = true;
 700                 }
 701                 /* sample in the vertical border, selecting the larger one */
 702                 if (vblank_start - vactive >= vtotal - vblank_end)
 703                         vsample = (vblank_start + vactive) >> 1;
 704                 else
 705                         vsample = (vtotal + vblank_end) >> 1;
 706
 707                 /*
 708                  * Wait for the border to be displayed
 709                  */
 710                 while (I915_READ(pipe_dsl_reg) >= vactive)
 711                         ;
 712                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 713                         ;
 714                 /*
 715                  * Watch ST00 for an entire scanline
 716                  */
 717                 detect = 0;
 718                 count = 0;
 719                 do {
 720                         count++;
 721                         /* Read the ST00 VGA status register */
 722                         st00 = I915_READ8(_VGA_MSR_WRITE);
 723                         if (st00 & (1 << 4))
 724                                 detect++;
 725                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 726
 727                 /* restore vblank if necessary */
 728                 if (restore_vblank)
 729                         I915_WRITE(vblank_reg, vblank);
 730                 /*
 731                  * If more than 3/4 of the scanline detected a monitor,
 732                  * then it is assumed to be present. This works even on i830,
 733                  * where there isn't any way to force the border color across
 734                  * the screen
 735                  */
 736                 status = detect * 4 > count * 3 ?
 737                          connector_status_connected :
 738                          connector_status_disconnected;
 739         }
 740
 741         /* Restore previous settings */
 742         I915_WRITE(bclrpat_reg, save_bclrpat);
 743
 744         return status;
 745 }
 746
 747 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 748 {
 749         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 750         return 1;
 751 }
 752
 753 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 754         {
 755                 .callback = intel_spurious_crt_detect_dmi_callback,
 756                 .ident = "ACER ZGB",
 757                 .matches = {
 758                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 759                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 760                 },
 761         },
 762         {
 763                 .callback = intel_spurious_crt_detect_dmi_callback,
 764                 .ident = "Intel DZ77BH-55K",
 765                 .matches = {
 766                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 767                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 768                 },
 769         },
 770         { }
 771 };
 772
 773 static int
 774 intel_crt_detect(struct drm_connector *connector,
 775                  struct drm_modeset_acquire_ctx *ctx,
 776                  bool force)
 777 {
 778         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 779         struct intel_crt *crt = intel_attached_crt(connector);
 780         struct intel_encoder *intel_encoder = &crt->base;
 781         int status, ret;
 782         struct intel_load_detect_pipe tmp;
 783
 784         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 785                       connector->base.id, connector->name,
 786                       force);
 787
 788         if (i915_modparams.load_detect_test) {
 789                 intel_display_power_get(dev_priv, intel_encoder->power_domain);
 790                 goto load_detect;
 791         }
 792
 793         /* Skip machines without VGA that falsely report hotplug events */
 794         if (dmi_check_system(intel_spurious_crt_detect))
 795                 return connector_status_disconnected;
 796
 797         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 798
 799         if (I915_HAS_HOTPLUG(dev_priv)) {
 800                 /* We can not rely on the HPD pin always being correctly wired
 801                  * up, for example many KVM do not pass it through, and so
 802                  * only trust an assertion that the monitor is connected.
 803                  */
 804                 if (intel_crt_detect_hotplug(connector)) {
 805                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 806                         status = connector_status_connected;
 807                         goto out;
 808                 } else
 809                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 810         }
 811
 812         if (intel_crt_detect_ddc(connector)) {
 813                 status = connector_status_connected;
 814                 goto out;
 815         }
 816
 817         /* Load detection is broken on HPD capable machines. Whoever wants a
 818          * broken monitor (without edid) to work behind a broken kvm (that fails
 819          * to have the right resistors for HP detection) needs to fix this up.
 820          * For now just bail out. */
 821         if (I915_HAS_HOTPLUG(dev_priv)) {
 822                 status = connector_status_disconnected;
 823                 goto out;
 824         }
 825
 826 load_detect:
 827         if (!force) {
 828                 status = connector->status;
 829                 goto out;
 830         }
 831
 832         /* for pre-945g platforms use load detect */
 833         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 834         if (ret > 0) {
 835                 if (intel_crt_detect_ddc(connector))
 836                         status = connector_status_connected;
 837                 else if (INTEL_GEN(dev_priv) < 4)
 838                         status = intel_crt_load_detect(crt,
 839                                 to_intel_crtc(connector->state->crtc)->pipe);
 840                 else if (i915_modparams.load_detect_test)
 841                         status = connector_status_disconnected;
 842                 else
 843                         status = connector_status_unknown;
 844                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 845         } else if (ret == 0) {
 846                 status = connector_status_unknown;
 847         } else {
 848                 status = ret;
 849         }
 850
 851 out:
 852         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 853         return status;
 854 }
 855
 856 static int intel_crt_get_modes(struct drm_connector *connector)
 857 {
 858         struct drm_device *dev = connector->dev;
 859         struct drm_i915_private *dev_priv = to_i915(dev);
 860         struct intel_crt *crt = intel_attached_crt(connector);
 861         struct intel_encoder *intel_encoder = &crt->base;
 862         int ret;
 863         struct i2c_adapter *i2c;
 864
 865         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 866
 867         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 868         ret = intel_crt_ddc_get_modes(connector, i2c);
 869         if (ret || !IS_G4X(dev_priv))
 870                 goto out;
 871
 872         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 873         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 874         ret = intel_crt_ddc_get_modes(connector, i2c);
 875
 876 out:
 877         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 878
 879         return ret;
 880 }
 881
 882 void intel_crt_reset(struct drm_encoder *encoder)
 883 {
 884         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 885         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 886
 887         if (INTEL_GEN(dev_priv) >= 5) {
 888                 u32 adpa;
 889
 890                 adpa = I915_READ(crt->adpa_reg);
 891                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 892                 adpa |= ADPA_HOTPLUG_BITS;
 893                 I915_WRITE(crt->adpa_reg, adpa);
 894                 POSTING_READ(crt->adpa_reg);
 895
 896                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 897                 crt->force_hotplug_required = 1;
 898         }
 899
 900 }
 901
 902 /*
 903  * Routines for controlling stuff on the analog port
 904  */
 905
 906 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 907         .fill_modes = drm_helper_probe_single_connector_modes,
 908         .late_register = intel_connector_register,
 909         .early_unregister = intel_connector_unregister,
 910         .destroy = intel_connector_destroy,
 911         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 912         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 913 };
 914
 915 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 916         .detect_ctx = intel_crt_detect,
 917         .mode_valid = intel_crt_mode_valid,
 918         .get_modes = intel_crt_get_modes,
 919 };
 920
 921 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 922         .reset = intel_crt_reset,
 923         .destroy = intel_encoder_destroy,
 924 };
 925
 926 void intel_crt_init(struct drm_i915_private *dev_priv)
 927 {
 928         struct drm_connector *connector;
 929         struct intel_crt *crt;
 930         struct intel_connector *intel_connector;
 931         i915_reg_t adpa_reg;
 932         u32 adpa;
 933
 934         if (HAS_PCH_SPLIT(dev_priv))
 935                 adpa_reg = PCH_ADPA;
 936         else if (IS_VALLEYVIEW(dev_priv))
 937                 adpa_reg = VLV_ADPA;
 938         else
 939                 adpa_reg = ADPA;
 940
 941         adpa = I915_READ(adpa_reg);
 942         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 943                 /*
 944                  * On some machines (some IVB at least) CRT can be
 945                  * fused off, but there's no known fuse bit to
 946                  * indicate that. On these machine the ADPA register
 947                  * works normally, except the DAC enable bit won't
 948                  * take. So the only way to tell is attempt to enable
 949                  * it and see what happens.
 950                  */
 951                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 952                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 953                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 954                         return;
 955                 I915_WRITE(adpa_reg, adpa);
 956         }
 957
 958         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 959         if (!crt)
 960                 return;
 961
 962         intel_connector = intel_connector_alloc();
 963         if (!intel_connector) {
 964                 kfree(crt);
 965                 return;
 966         }
 967
 968         connector = &intel_connector->base;
 969         crt->connector = intel_connector;
 970         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 971                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 972
 973         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 974                          DRM_MODE_ENCODER_DAC, "CRT");
 975
 976         intel_connector_attach_encoder(intel_connector, &crt->base);
 977
 978         crt->base.type = INTEL_OUTPUT_ANALOG;
 979         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 980         if (IS_I830(dev_priv))
 981                 crt->base.crtc_mask = (1 << 0);
 982         else
 983                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 984
 985         if (IS_GEN2(dev_priv))
 986                 connector->interlace_allowed = 0;
 987         else
 988                 connector->interlace_allowed = 1;
 989         connector->doublescan_allowed = 0;
 990
 991         crt->adpa_reg = adpa_reg;
 992
 993         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 994
 995         if (I915_HAS_HOTPLUG(dev_priv) &&
 996             !dmi_check_system(intel_spurious_crt_detect)) {
 997                 crt->base.hpd_pin = HPD_CRT;
 998                 crt->base.hotplug = intel_encoder_hotplug;
 999         }
1000
1001         if (HAS_DDI(dev_priv)) {
1002                 crt->base.port = PORT_E;
1003                 crt->base.get_config = hsw_crt_get_config;
1004                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1005                 crt->base.compute_config = hsw_crt_compute_config;
1006                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1007                 crt->base.pre_enable = hsw_pre_enable_crt;
1008                 crt->base.enable = hsw_enable_crt;
1009                 crt->base.disable = hsw_disable_crt;
1010                 crt->base.post_disable = hsw_post_disable_crt;
1011         } else {
1012                 if (HAS_PCH_SPLIT(dev_priv)) {
1013                         crt->base.compute_config = pch_crt_compute_config;
1014                         crt->base.disable = pch_disable_crt;
1015                         crt->base.post_disable = pch_post_disable_crt;
1016                 } else {
1017                         crt->base.compute_config = intel_crt_compute_config;
1018                         crt->base.disable = intel_disable_crt;
1019                 }
1020                 crt->base.port = PORT_NONE;
1021                 crt->base.get_config = intel_crt_get_config;
1022                 crt->base.get_hw_state = intel_crt_get_hw_state;
1023                 crt->base.enable = intel_enable_crt;
1024         }
1025         intel_connector->get_hw_state = intel_connector_get_hw_state;
1026
1027         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1028
1029         if (!I915_HAS_HOTPLUG(dev_priv))
1030                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1031
1032         /*
1033          * Configure the automatic hotplug detection stuff
1034          */
1035         crt->force_hotplug_required = 0;
1036
1037         /*
1038          * TODO: find a proper way to discover whether we need to set the the
1039          * polarity and link reversal bits or not, instead of relying on the
1040          * BIOS.
1041          */
1042         if (HAS_PCH_LPT(dev_priv)) {
1043                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1044                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1045
1046                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1047         }
1048
1049         intel_crt_reset(&crt->base.base);
1050 }