drivers/gpu/drm/i915/intel_combo_phy.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  */
   5
   6 #include "intel_drv.h"
   7
   8 #define for_each_combo_port(__dev_priv, __port) \
   9         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)  \
  10                 for_each_if(intel_port_is_combophy(__dev_priv, __port))
  11
  12 #define for_each_combo_port_reverse(__dev_priv, __port) \
  13         for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
  14                 for_each_if(intel_port_is_combophy(__dev_priv, __port))
  15
  16 enum {
  17         PROCMON_0_85V_DOT_0,
  18         PROCMON_0_95V_DOT_0,
  19         PROCMON_0_95V_DOT_1,
  20         PROCMON_1_05V_DOT_0,
  21         PROCMON_1_05V_DOT_1,
  22 };
  23
  24 static const struct cnl_procmon {
  25         u32 dw1, dw9, dw10;
  26 } cnl_procmon_values[] = {
  27         [PROCMON_0_85V_DOT_0] =
  28                 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
  29         [PROCMON_0_95V_DOT_0] =
  30                 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
  31         [PROCMON_0_95V_DOT_1] =
  32                 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
  33         [PROCMON_1_05V_DOT_0] =
  34                 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
  35         [PROCMON_1_05V_DOT_1] =
  36                 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
  37 };
  38
  39 /*
  40  * CNL has just one set of registers, while ICL has two sets: one for port A and
  41  * the other for port B. The CNL registers are equivalent to the ICL port A
  42  * registers, that's why we call the ICL macros even though the function has CNL
  43  * on its name.
  44  */
  45 static const struct cnl_procmon *
  46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
  47 {
  48         const struct cnl_procmon *procmon;
  49         u32 val;
  50
  51         val = I915_READ(ICL_PORT_COMP_DW3(port));
  52         switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
  53         default:
  54                 MISSING_CASE(val);
  55                 /* fall through */
  56         case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
  57                 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
  58                 break;
  59         case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
  60                 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
  61                 break;
  62         case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
  63                 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
  64                 break;
  65         case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
  66                 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
  67                 break;
  68         case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
  69                 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
  70                 break;
  71         }
  72
  73         return procmon;
  74 }
  75
  76 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
  77                                        enum port port)
  78 {
  79         const struct cnl_procmon *procmon;
  80         u32 val;
  81
  82         procmon = cnl_get_procmon_ref_values(dev_priv, port);
  83
  84         val = I915_READ(ICL_PORT_COMP_DW1(port));
  85         val &= ~((0xff << 16) | 0xff);
  86         val |= procmon->dw1;
  87         I915_WRITE(ICL_PORT_COMP_DW1(port), val);
  88
  89         I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
  90         I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
  91 }
  92
  93 static bool check_phy_reg(struct drm_i915_private *dev_priv,
  94                           enum port port, i915_reg_t reg, u32 mask,
  95                           u32 expected_val)
  96 {
  97         u32 val = I915_READ(reg);
  98
  99         if ((val & mask) != expected_val) {
 100                 DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
 101                                  "current %08x mask %08x expected %08x\n",
 102                                  port_name(port),
 103                                  reg.reg, val, mask, expected_val);
 104                 return false;
 105         }
 106
 107         return true;
 108 }
 109
 110 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
 111                                           enum port port)
 112 {
 113         const struct cnl_procmon *procmon;
 114         bool ret;
 115
 116         procmon = cnl_get_procmon_ref_values(dev_priv, port);
 117
 118         ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
 119                             (0xff << 16) | 0xff, procmon->dw1);
 120         ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
 121                              -1U, procmon->dw9);
 122         ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
 123                              -1U, procmon->dw10);
 124
 125         return ret;
 126 }
 127
 128 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
 129 {
 130         return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
 131                 (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
 132 }
 133
 134 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
 135 {
 136         enum port port = PORT_A;
 137         bool ret;
 138
 139         if (!cnl_combo_phy_enabled(dev_priv))
 140                 return false;
 141
 142         ret = cnl_verify_procmon_ref_values(dev_priv, port);
 143
 144         ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
 145                              CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 146
 147         return ret;
 148 }
 149
 150 void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
 151 {
 152         u32 val;
 153
 154         val = I915_READ(CHICKEN_MISC_2);
 155         val &= ~CNL_COMP_PWR_DOWN;
 156         I915_WRITE(CHICKEN_MISC_2, val);
 157
 158         /* Dummy PORT_A to get the correct CNL register from the ICL macro */
 159         cnl_set_procmon_ref_values(dev_priv, PORT_A);
 160
 161         val = I915_READ(CNL_PORT_COMP_DW0);
 162         val |= COMP_INIT;
 163         I915_WRITE(CNL_PORT_COMP_DW0, val);
 164
 165         val = I915_READ(CNL_PORT_CL1CM_DW5);
 166         val |= CL_POWER_DOWN_ENABLE;
 167         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
 168 }
 169
 170 void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 171 {
 172         u32 val;
 173
 174         if (!cnl_combo_phy_verify_state(dev_priv))
 175                 DRM_WARN("Combo PHY HW state changed unexpectedly.\n");
 176
 177         val = I915_READ(CHICKEN_MISC_2);
 178         val |= CNL_COMP_PWR_DOWN;
 179         I915_WRITE(CHICKEN_MISC_2, val);
 180 }
 181
 182 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 183                                   enum port port)
 184 {
 185         return !(I915_READ(ICL_PHY_MISC(port)) &
 186                  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
 187                 (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
 188 }
 189
 190 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 191                                        enum port port)
 192 {
 193         bool ret;
 194
 195         if (!icl_combo_phy_enabled(dev_priv, port))
 196                 return false;
 197
 198         ret = cnl_verify_procmon_ref_values(dev_priv, port);
 199
 200         ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
 201                              CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 202
 203         return ret;
 204 }
 205
 206 void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 207 {
 208         enum port port;
 209
 210         for_each_combo_port(dev_priv, port) {
 211                 u32 val;
 212
 213                 if (icl_combo_phy_verify_state(dev_priv, port)) {
 214                         DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
 215                                          port_name(port));
 216                         continue;
 217                 }
 218
 219                 val = I915_READ(ICL_PHY_MISC(port));
 220                 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 221                 I915_WRITE(ICL_PHY_MISC(port), val);
 222
 223                 cnl_set_procmon_ref_values(dev_priv, port);
 224
 225                 val = I915_READ(ICL_PORT_COMP_DW0(port));
 226                 val |= COMP_INIT;
 227                 I915_WRITE(ICL_PORT_COMP_DW0(port), val);
 228
 229                 val = I915_READ(ICL_PORT_CL_DW5(port));
 230                 val |= CL_POWER_DOWN_ENABLE;
 231                 I915_WRITE(ICL_PORT_CL_DW5(port), val);
 232         }
 233 }
 234
 235 void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 236 {
 237         enum port port;
 238
 239         for_each_combo_port_reverse(dev_priv, port) {
 240                 u32 val;
 241
 242                 if (port == PORT_A &&
 243                     !icl_combo_phy_verify_state(dev_priv, port))
 244                         DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
 245                                  port_name(port));
 246
 247                 val = I915_READ(ICL_PHY_MISC(port));
 248                 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 249                 I915_WRITE(ICL_PHY_MISC(port), val);
 250
 251                 val = I915_READ(ICL_PORT_COMP_DW0(port));
 252                 val &= ~COMP_INIT;
 253                 I915_WRITE(ICL_PORT_COMP_DW0(port), val);
 254         }
 255 }