2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
57 cdclk_state->cdclk = 133333;
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
63 cdclk_state->cdclk = 200000;
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
69 cdclk_state->cdclk = 266667;
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
75 cdclk_state->cdclk = 333333;
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
81 cdclk_state->cdclk = 400000;
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
87 cdclk_state->cdclk = 450000;
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
93 struct pci_dev *pdev = dev_priv->drm.pdev;
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
116 cdclk_state->cdclk = 200000;
118 case GC_CLOCK_166_250:
119 cdclk_state->cdclk = 250000;
121 case GC_CLOCK_100_133:
122 cdclk_state->cdclk = 133333;
124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
127 cdclk_state->cdclk = 266667;
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
135 struct pci_dev *pdev = dev_priv->drm.pdev;
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
147 cdclk_state->cdclk = 333333;
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
151 cdclk_state->cdclk = 190000;
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
159 struct pci_dev *pdev = dev_priv->drm.pdev;
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
171 cdclk_state->cdclk = 320000;
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
175 cdclk_state->cdclk = 200000;
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
182 static const unsigned int blb_vco[8] = {
189 static const unsigned int pnv_vco[8] = {
196 static const unsigned int cl_vco[8] = {
205 static const unsigned int elk_vco[8] = {
211 static const unsigned int ctg_vco[8] = {
219 const unsigned int *vco_table;
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
226 else if (IS_G45(dev_priv))
228 else if (IS_I965GM(dev_priv))
230 else if (IS_PINEVIEW(dev_priv))
232 else if (IS_G33(dev_priv))
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
239 vco = vco_table[tmp & 0x7];
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
257 unsigned int cdclk_sel;
260 cdclk_state->vco = intel_hpll_vco(dev_priv);
262 pci_read_config_word(pdev, GCFGC, &tmp);
264 cdclk_sel = (tmp >> 4) & 0x7;
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
269 switch (cdclk_state->vco) {
271 div_table = div_3200;
274 div_table = div_4000;
277 div_table = div_4800;
280 div_table = div_5333;
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
299 struct pci_dev *pdev = dev_priv->drm.pdev;
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
306 cdclk_state->cdclk = 266667;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
309 cdclk_state->cdclk = 333333;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
312 cdclk_state->cdclk = 444444;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
315 cdclk_state->cdclk = 200000;
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
320 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
321 cdclk_state->cdclk = 133333;
323 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
324 cdclk_state->cdclk = 166667;
329 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
330 struct intel_cdclk_state *cdclk_state)
332 struct pci_dev *pdev = dev_priv->drm.pdev;
333 static const u8 div_3200[] = { 16, 10, 8 };
334 static const u8 div_4000[] = { 20, 12, 10 };
335 static const u8 div_5333[] = { 24, 16, 14 };
337 unsigned int cdclk_sel;
340 cdclk_state->vco = intel_hpll_vco(dev_priv);
342 pci_read_config_word(pdev, GCFGC, &tmp);
344 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
346 if (cdclk_sel >= ARRAY_SIZE(div_3200))
349 switch (cdclk_state->vco) {
351 div_table = div_3200;
354 div_table = div_4000;
357 div_table = div_5333;
363 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
364 div_table[cdclk_sel]);
368 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
369 cdclk_state->vco, tmp);
370 cdclk_state->cdclk = 200000;
373 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
374 struct intel_cdclk_state *cdclk_state)
376 struct pci_dev *pdev = dev_priv->drm.pdev;
377 unsigned int cdclk_sel;
380 cdclk_state->vco = intel_hpll_vco(dev_priv);
382 pci_read_config_word(pdev, GCFGC, &tmp);
384 cdclk_sel = (tmp >> 12) & 0x1;
386 switch (cdclk_state->vco) {
390 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
393 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
396 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
397 cdclk_state->vco, tmp);
398 cdclk_state->cdclk = 222222;
403 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
404 struct intel_cdclk_state *cdclk_state)
406 u32 lcpll = I915_READ(LCPLL_CTL);
407 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
409 if (lcpll & LCPLL_CD_SOURCE_FCLK)
410 cdclk_state->cdclk = 800000;
411 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
412 cdclk_state->cdclk = 450000;
413 else if (freq == LCPLL_CLK_FREQ_450)
414 cdclk_state->cdclk = 450000;
415 else if (IS_HSW_ULT(dev_priv))
416 cdclk_state->cdclk = 337500;
418 cdclk_state->cdclk = 540000;
421 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
427 * We seem to get an unstable or solid color picture at 200MHz.
428 * Not sure what's wrong. For now use 200MHz only when all pipes
431 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
433 else if (min_cdclk > 266667)
435 else if (min_cdclk > 0)
441 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
443 if (IS_VALLEYVIEW(dev_priv)) {
444 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
446 else if (cdclk >= 266667)
452 * Specs are full of misinformation, but testing on actual
453 * hardware has shown that we just need to write the desired
454 * CCK divider into the Punit register.
456 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
460 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
461 struct intel_cdclk_state *cdclk_state)
465 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
466 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
467 CCK_DISPLAY_CLOCK_CONTROL,
470 mutex_lock(&dev_priv->pcu_lock);
471 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
472 mutex_unlock(&dev_priv->pcu_lock);
474 if (IS_VALLEYVIEW(dev_priv))
475 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
478 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
479 DSPFREQGUAR_SHIFT_CHV;
482 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
484 unsigned int credits, default_credits;
486 if (IS_CHERRYVIEW(dev_priv))
487 default_credits = PFI_CREDIT(12);
489 default_credits = PFI_CREDIT(8);
491 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
492 /* CHV suggested value is 31 or 63 */
493 if (IS_CHERRYVIEW(dev_priv))
494 credits = PFI_CREDIT_63;
496 credits = PFI_CREDIT(15);
498 credits = default_credits;
502 * WA - write default credits before re-programming
503 * FIXME: should we also set the resend bit here?
505 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
508 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
509 credits | PFI_CREDIT_RESEND);
512 * FIXME is this guaranteed to clear
513 * immediately or should we poll for it?
515 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
518 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
519 const struct intel_cdclk_state *cdclk_state)
521 int cdclk = cdclk_state->cdclk;
522 u32 val, cmd = cdclk_state->voltage_level;
523 intel_wakeref_t wakeref;
537 /* There are cases where we can end up here with power domains
538 * off and a CDCLK frequency other than the minimum, like when
539 * issuing a modeset without actually changing any display after
540 * a system suspend. So grab the PIPE-A domain, which covers
541 * the HW blocks needed for the following programming.
543 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
545 mutex_lock(&dev_priv->pcu_lock);
546 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
547 val &= ~DSPFREQGUAR_MASK;
548 val |= (cmd << DSPFREQGUAR_SHIFT);
549 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
550 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
551 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
553 DRM_ERROR("timed out waiting for CDclk change\n");
555 mutex_unlock(&dev_priv->pcu_lock);
557 mutex_lock(&dev_priv->sb_lock);
559 if (cdclk == 400000) {
562 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
565 /* adjust cdclk divider */
566 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
567 val &= ~CCK_FREQUENCY_VALUES;
569 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
571 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
572 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
574 DRM_ERROR("timed out waiting for CDclk change\n");
577 /* adjust self-refresh exit latency value */
578 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
582 * For high bandwidth configs, we set a higher latency in the bunit
583 * so that the core display fetch happens in time to avoid underruns.
586 val |= 4500 / 250; /* 4.5 usec */
588 val |= 3000 / 250; /* 3.0 usec */
589 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
591 mutex_unlock(&dev_priv->sb_lock);
593 intel_update_cdclk(dev_priv);
595 vlv_program_pfi_credits(dev_priv);
597 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
600 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
601 const struct intel_cdclk_state *cdclk_state)
603 int cdclk = cdclk_state->cdclk;
604 u32 val, cmd = cdclk_state->voltage_level;
605 intel_wakeref_t wakeref;
618 /* There are cases where we can end up here with power domains
619 * off and a CDCLK frequency other than the minimum, like when
620 * issuing a modeset without actually changing any display after
621 * a system suspend. So grab the PIPE-A domain, which covers
622 * the HW blocks needed for the following programming.
624 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
626 mutex_lock(&dev_priv->pcu_lock);
627 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
628 val &= ~DSPFREQGUAR_MASK_CHV;
629 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
630 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
631 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
632 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
634 DRM_ERROR("timed out waiting for CDclk change\n");
636 mutex_unlock(&dev_priv->pcu_lock);
638 intel_update_cdclk(dev_priv);
640 vlv_program_pfi_credits(dev_priv);
642 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
645 static int bdw_calc_cdclk(int min_cdclk)
647 if (min_cdclk > 540000)
649 else if (min_cdclk > 450000)
651 else if (min_cdclk > 337500)
657 static u8 bdw_calc_voltage_level(int cdclk)
672 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
673 struct intel_cdclk_state *cdclk_state)
675 u32 lcpll = I915_READ(LCPLL_CTL);
676 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
678 if (lcpll & LCPLL_CD_SOURCE_FCLK)
679 cdclk_state->cdclk = 800000;
680 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
681 cdclk_state->cdclk = 450000;
682 else if (freq == LCPLL_CLK_FREQ_450)
683 cdclk_state->cdclk = 450000;
684 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
685 cdclk_state->cdclk = 540000;
686 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
687 cdclk_state->cdclk = 337500;
689 cdclk_state->cdclk = 675000;
692 * Can't read this out :( Let's assume it's
693 * at least what the CDCLK frequency requires.
695 cdclk_state->voltage_level =
696 bdw_calc_voltage_level(cdclk_state->cdclk);
699 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
700 const struct intel_cdclk_state *cdclk_state)
702 int cdclk = cdclk_state->cdclk;
706 if (WARN((I915_READ(LCPLL_CTL) &
707 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
708 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
709 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
710 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
711 "trying to change cdclk frequency with cdclk not enabled\n"))
714 mutex_lock(&dev_priv->pcu_lock);
715 ret = sandybridge_pcode_write(dev_priv,
716 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
717 mutex_unlock(&dev_priv->pcu_lock);
719 DRM_ERROR("failed to inform pcode about cdclk change\n");
723 val = I915_READ(LCPLL_CTL);
724 val |= LCPLL_CD_SOURCE_FCLK;
725 I915_WRITE(LCPLL_CTL, val);
728 * According to the spec, it should be enough to poll for this 1 us.
729 * However, extensive testing shows that this can take longer.
731 if (wait_for_us(I915_READ(LCPLL_CTL) &
732 LCPLL_CD_SOURCE_FCLK_DONE, 100))
733 DRM_ERROR("Switching to FCLK failed\n");
735 val = I915_READ(LCPLL_CTL);
736 val &= ~LCPLL_CLK_FREQ_MASK;
743 val |= LCPLL_CLK_FREQ_337_5_BDW;
746 val |= LCPLL_CLK_FREQ_450;
749 val |= LCPLL_CLK_FREQ_54O_BDW;
752 val |= LCPLL_CLK_FREQ_675_BDW;
756 I915_WRITE(LCPLL_CTL, val);
758 val = I915_READ(LCPLL_CTL);
759 val &= ~LCPLL_CD_SOURCE_FCLK;
760 I915_WRITE(LCPLL_CTL, val);
762 if (wait_for_us((I915_READ(LCPLL_CTL) &
763 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
764 DRM_ERROR("Switching back to LCPLL failed\n");
766 mutex_lock(&dev_priv->pcu_lock);
767 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
768 cdclk_state->voltage_level);
769 mutex_unlock(&dev_priv->pcu_lock);
771 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
773 intel_update_cdclk(dev_priv);
776 static int skl_calc_cdclk(int min_cdclk, int vco)
778 if (vco == 8640000) {
779 if (min_cdclk > 540000)
781 else if (min_cdclk > 432000)
783 else if (min_cdclk > 308571)
788 if (min_cdclk > 540000)
790 else if (min_cdclk > 450000)
792 else if (min_cdclk > 337500)
799 static u8 skl_calc_voltage_level(int cdclk)
817 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
818 struct intel_cdclk_state *cdclk_state)
822 cdclk_state->ref = 24000;
823 cdclk_state->vco = 0;
825 val = I915_READ(LCPLL1_CTL);
826 if ((val & LCPLL_PLL_ENABLE) == 0)
829 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
832 val = I915_READ(DPLL_CTRL1);
834 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
835 DPLL_CTRL1_SSC(SKL_DPLL0) |
836 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
837 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
840 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
841 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
842 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
843 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
844 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
845 cdclk_state->vco = 8100000;
847 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
848 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
849 cdclk_state->vco = 8640000;
852 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
857 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
858 struct intel_cdclk_state *cdclk_state)
862 skl_dpll0_update(dev_priv, cdclk_state);
864 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
866 if (cdclk_state->vco == 0)
869 cdctl = I915_READ(CDCLK_CTL);
871 if (cdclk_state->vco == 8640000) {
872 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
873 case CDCLK_FREQ_450_432:
874 cdclk_state->cdclk = 432000;
876 case CDCLK_FREQ_337_308:
877 cdclk_state->cdclk = 308571;
880 cdclk_state->cdclk = 540000;
882 case CDCLK_FREQ_675_617:
883 cdclk_state->cdclk = 617143;
886 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
890 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
891 case CDCLK_FREQ_450_432:
892 cdclk_state->cdclk = 450000;
894 case CDCLK_FREQ_337_308:
895 cdclk_state->cdclk = 337500;
898 cdclk_state->cdclk = 540000;
900 case CDCLK_FREQ_675_617:
901 cdclk_state->cdclk = 675000;
904 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
911 * Can't read this out :( Let's assume it's
912 * at least what the CDCLK frequency requires.
914 cdclk_state->voltage_level =
915 skl_calc_voltage_level(cdclk_state->cdclk);
918 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
919 static int skl_cdclk_decimal(int cdclk)
921 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
924 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
927 bool changed = dev_priv->skl_preferred_vco_freq != vco;
929 dev_priv->skl_preferred_vco_freq = vco;
932 intel_update_max_cdclk(dev_priv);
935 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
939 WARN_ON(vco != 8100000 && vco != 8640000);
942 * We always enable DPLL0 with the lowest link rate possible, but still
943 * taking into account the VCO required to operate the eDP panel at the
944 * desired frequency. The usual DP link rates operate with a VCO of
945 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
946 * The modeset code is responsible for the selection of the exact link
947 * rate later on, with the constraint of choosing a frequency that
950 val = I915_READ(DPLL_CTRL1);
952 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
953 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
954 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
956 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
959 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
962 I915_WRITE(DPLL_CTRL1, val);
963 POSTING_READ(DPLL_CTRL1);
965 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
967 if (intel_wait_for_register(dev_priv,
968 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
970 DRM_ERROR("DPLL0 not locked\n");
972 dev_priv->cdclk.hw.vco = vco;
974 /* We'll want to keep using the current vco from now on. */
975 skl_set_preferred_cdclk_vco(dev_priv, vco);
978 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
980 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
981 if (intel_wait_for_register(dev_priv,
982 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
984 DRM_ERROR("Couldn't disable DPLL0\n");
986 dev_priv->cdclk.hw.vco = 0;
989 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
990 const struct intel_cdclk_state *cdclk_state)
992 int cdclk = cdclk_state->cdclk;
993 int vco = cdclk_state->vco;
994 u32 freq_select, cdclk_ctl;
998 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
999 * unsupported on SKL. In theory this should never happen since only
1000 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1001 * supported on SKL either, see the above WA. WARN whenever trying to
1002 * use the corresponding VCO freq as that always leads to using the
1003 * minimum 308MHz CDCLK.
1005 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1007 mutex_lock(&dev_priv->pcu_lock);
1008 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1009 SKL_CDCLK_PREPARE_FOR_CHANGE,
1010 SKL_CDCLK_READY_FOR_CHANGE,
1011 SKL_CDCLK_READY_FOR_CHANGE, 3);
1012 mutex_unlock(&dev_priv->pcu_lock);
1014 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1019 /* Choose frequency for this cdclk */
1022 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1027 freq_select = CDCLK_FREQ_337_308;
1031 freq_select = CDCLK_FREQ_450_432;
1034 freq_select = CDCLK_FREQ_540;
1038 freq_select = CDCLK_FREQ_675_617;
1042 if (dev_priv->cdclk.hw.vco != 0 &&
1043 dev_priv->cdclk.hw.vco != vco)
1044 skl_dpll0_disable(dev_priv);
1046 cdclk_ctl = I915_READ(CDCLK_CTL);
1048 if (dev_priv->cdclk.hw.vco != vco) {
1049 /* Wa Display #1183: skl,kbl,cfl */
1050 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1051 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1052 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1055 /* Wa Display #1183: skl,kbl,cfl */
1056 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1057 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1058 POSTING_READ(CDCLK_CTL);
1060 if (dev_priv->cdclk.hw.vco != vco)
1061 skl_dpll0_enable(dev_priv, vco);
1063 /* Wa Display #1183: skl,kbl,cfl */
1064 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1065 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1067 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1068 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1070 /* Wa Display #1183: skl,kbl,cfl */
1071 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1072 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1073 POSTING_READ(CDCLK_CTL);
1075 /* inform PCU of the change */
1076 mutex_lock(&dev_priv->pcu_lock);
1077 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1078 cdclk_state->voltage_level);
1079 mutex_unlock(&dev_priv->pcu_lock);
1081 intel_update_cdclk(dev_priv);
1084 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1086 u32 cdctl, expected;
1089 * check if the pre-os initialized the display
1090 * There is SWF18 scratchpad register defined which is set by the
1091 * pre-os which can be used by the OS drivers to check the status
1093 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1096 intel_update_cdclk(dev_priv);
1097 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1099 /* Is PLL enabled and locked ? */
1100 if (dev_priv->cdclk.hw.vco == 0 ||
1101 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1104 /* DPLL okay; verify the cdclock
1106 * Noticed in some instances that the freq selection is correct but
1107 * decimal part is programmed wrong from BIOS where pre-os does not
1108 * enable display. Verify the same as well.
1110 cdctl = I915_READ(CDCLK_CTL);
1111 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1112 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1113 if (cdctl == expected)
1114 /* All well; nothing to sanitize */
1118 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1120 /* force cdclk programming */
1121 dev_priv->cdclk.hw.cdclk = 0;
1122 /* force full PLL disable + enable */
1123 dev_priv->cdclk.hw.vco = -1;
1127 * skl_init_cdclk - Initialize CDCLK on SKL
1128 * @dev_priv: i915 device
1130 * Initialize CDCLK for SKL and derivatives. This is generally
1131 * done only during the display core initialization sequence,
1132 * after which the DMC will take care of turning CDCLK off/on
1135 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1137 struct intel_cdclk_state cdclk_state;
1139 skl_sanitize_cdclk(dev_priv);
1141 if (dev_priv->cdclk.hw.cdclk != 0 &&
1142 dev_priv->cdclk.hw.vco != 0) {
1144 * Use the current vco as our initial
1145 * guess as to what the preferred vco is.
1147 if (dev_priv->skl_preferred_vco_freq == 0)
1148 skl_set_preferred_cdclk_vco(dev_priv,
1149 dev_priv->cdclk.hw.vco);
1153 cdclk_state = dev_priv->cdclk.hw;
1155 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1156 if (cdclk_state.vco == 0)
1157 cdclk_state.vco = 8100000;
1158 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1159 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1161 skl_set_cdclk(dev_priv, &cdclk_state);
1165 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1166 * @dev_priv: i915 device
1168 * Uninitialize CDCLK for SKL and derivatives. This is done only
1169 * during the display core uninitialization sequence.
1171 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1173 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1175 cdclk_state.cdclk = cdclk_state.bypass;
1176 cdclk_state.vco = 0;
1177 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1179 skl_set_cdclk(dev_priv, &cdclk_state);
1182 static int bxt_calc_cdclk(int min_cdclk)
1184 if (min_cdclk > 576000)
1186 else if (min_cdclk > 384000)
1188 else if (min_cdclk > 288000)
1190 else if (min_cdclk > 144000)
1196 static int glk_calc_cdclk(int min_cdclk)
1198 if (min_cdclk > 158400)
1200 else if (min_cdclk > 79200)
1206 static u8 bxt_calc_voltage_level(int cdclk)
1208 return DIV_ROUND_UP(cdclk, 25000);
1211 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1215 if (cdclk == dev_priv->cdclk.hw.bypass)
1220 MISSING_CASE(cdclk);
1233 return dev_priv->cdclk.hw.ref * ratio;
1236 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1240 if (cdclk == dev_priv->cdclk.hw.bypass)
1245 MISSING_CASE(cdclk);
1254 return dev_priv->cdclk.hw.ref * ratio;
1257 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1258 struct intel_cdclk_state *cdclk_state)
1262 cdclk_state->ref = 19200;
1263 cdclk_state->vco = 0;
1265 val = I915_READ(BXT_DE_PLL_ENABLE);
1266 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1269 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1272 val = I915_READ(BXT_DE_PLL_CTL);
1273 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1276 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1277 struct intel_cdclk_state *cdclk_state)
1282 bxt_de_pll_update(dev_priv, cdclk_state);
1284 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1286 if (cdclk_state->vco == 0)
1289 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1292 case BXT_CDCLK_CD2X_DIV_SEL_1:
1295 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1296 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1299 case BXT_CDCLK_CD2X_DIV_SEL_2:
1302 case BXT_CDCLK_CD2X_DIV_SEL_4:
1306 MISSING_CASE(divider);
1310 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1314 * Can't read this out :( Let's assume it's
1315 * at least what the CDCLK frequency requires.
1317 cdclk_state->voltage_level =
1318 bxt_calc_voltage_level(cdclk_state->cdclk);
1321 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1323 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1326 if (intel_wait_for_register(dev_priv,
1327 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1329 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1331 dev_priv->cdclk.hw.vco = 0;
1334 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1336 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1339 val = I915_READ(BXT_DE_PLL_CTL);
1340 val &= ~BXT_DE_PLL_RATIO_MASK;
1341 val |= BXT_DE_PLL_RATIO(ratio);
1342 I915_WRITE(BXT_DE_PLL_CTL, val);
1344 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1347 if (intel_wait_for_register(dev_priv,
1352 DRM_ERROR("timeout waiting for DE PLL lock\n");
1354 dev_priv->cdclk.hw.vco = vco;
1357 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1358 const struct intel_cdclk_state *cdclk_state)
1360 int cdclk = cdclk_state->cdclk;
1361 int vco = cdclk_state->vco;
1365 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1366 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1368 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1375 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1376 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1379 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1382 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1387 * Inform power controller of upcoming frequency change. BSpec
1388 * requires us to wait up to 150usec, but that leads to timeouts;
1389 * the 2ms used here is based on experiment.
1391 mutex_lock(&dev_priv->pcu_lock);
1392 ret = sandybridge_pcode_write_timeout(dev_priv,
1393 HSW_PCODE_DE_WRITE_FREQ_REQ,
1394 0x80000000, 150, 2);
1395 mutex_unlock(&dev_priv->pcu_lock);
1398 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1403 if (dev_priv->cdclk.hw.vco != 0 &&
1404 dev_priv->cdclk.hw.vco != vco)
1405 bxt_de_pll_disable(dev_priv);
1407 if (dev_priv->cdclk.hw.vco != vco)
1408 bxt_de_pll_enable(dev_priv, vco);
1410 val = divider | skl_cdclk_decimal(cdclk);
1412 * FIXME if only the cd2x divider needs changing, it could be done
1413 * without shutting off the pipe (if only one pipe is active).
1415 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1417 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1420 if (cdclk >= 500000)
1421 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1422 I915_WRITE(CDCLK_CTL, val);
1424 mutex_lock(&dev_priv->pcu_lock);
1426 * The timeout isn't specified, the 2ms used here is based on
1428 * FIXME: Waiting for the request completion could be delayed until
1429 * the next PCODE request based on BSpec.
1431 ret = sandybridge_pcode_write_timeout(dev_priv,
1432 HSW_PCODE_DE_WRITE_FREQ_REQ,
1433 cdclk_state->voltage_level, 150, 2);
1434 mutex_unlock(&dev_priv->pcu_lock);
1437 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1442 intel_update_cdclk(dev_priv);
1445 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1447 u32 cdctl, expected;
1449 intel_update_cdclk(dev_priv);
1450 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1452 if (dev_priv->cdclk.hw.vco == 0 ||
1453 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1456 /* DPLL okay; verify the cdclock
1458 * Some BIOS versions leave an incorrect decimal frequency value and
1459 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1460 * so sanitize this register.
1462 cdctl = I915_READ(CDCLK_CTL);
1464 * Let's ignore the pipe field, since BIOS could have configured the
1465 * dividers both synching to an active pipe, or asynchronously
1468 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1470 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1471 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1473 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1476 if (dev_priv->cdclk.hw.cdclk >= 500000)
1477 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1479 if (cdctl == expected)
1480 /* All well; nothing to sanitize */
1484 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1486 /* force cdclk programming */
1487 dev_priv->cdclk.hw.cdclk = 0;
1489 /* force full PLL disable + enable */
1490 dev_priv->cdclk.hw.vco = -1;
1494 * bxt_init_cdclk - Initialize CDCLK on BXT
1495 * @dev_priv: i915 device
1497 * Initialize CDCLK for BXT and derivatives. This is generally
1498 * done only during the display core initialization sequence,
1499 * after which the DMC will take care of turning CDCLK off/on
1502 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1504 struct intel_cdclk_state cdclk_state;
1506 bxt_sanitize_cdclk(dev_priv);
1508 if (dev_priv->cdclk.hw.cdclk != 0 &&
1509 dev_priv->cdclk.hw.vco != 0)
1512 cdclk_state = dev_priv->cdclk.hw;
1516 * - The initial CDCLK needs to be read from VBT.
1517 * Need to make this change after VBT has changes for BXT.
1519 if (IS_GEMINILAKE(dev_priv)) {
1520 cdclk_state.cdclk = glk_calc_cdclk(0);
1521 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1523 cdclk_state.cdclk = bxt_calc_cdclk(0);
1524 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1526 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1528 bxt_set_cdclk(dev_priv, &cdclk_state);
1532 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1533 * @dev_priv: i915 device
1535 * Uninitialize CDCLK for BXT and derivatives. This is done only
1536 * during the display core uninitialization sequence.
1538 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1540 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1542 cdclk_state.cdclk = cdclk_state.bypass;
1543 cdclk_state.vco = 0;
1544 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1546 bxt_set_cdclk(dev_priv, &cdclk_state);
1549 static int cnl_calc_cdclk(int min_cdclk)
1551 if (min_cdclk > 336000)
1553 else if (min_cdclk > 168000)
1559 static u8 cnl_calc_voltage_level(int cdclk)
1572 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1573 struct intel_cdclk_state *cdclk_state)
1577 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1578 cdclk_state->ref = 24000;
1580 cdclk_state->ref = 19200;
1582 cdclk_state->vco = 0;
1584 val = I915_READ(BXT_DE_PLL_ENABLE);
1585 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1588 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1591 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1594 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1595 struct intel_cdclk_state *cdclk_state)
1600 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1602 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1604 if (cdclk_state->vco == 0)
1607 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1610 case BXT_CDCLK_CD2X_DIV_SEL_1:
1613 case BXT_CDCLK_CD2X_DIV_SEL_2:
1617 MISSING_CASE(divider);
1621 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1625 * Can't read this out :( Let's assume it's
1626 * at least what the CDCLK frequency requires.
1628 cdclk_state->voltage_level =
1629 cnl_calc_voltage_level(cdclk_state->cdclk);
1632 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1636 val = I915_READ(BXT_DE_PLL_ENABLE);
1637 val &= ~BXT_DE_PLL_PLL_ENABLE;
1638 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1641 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1642 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1644 dev_priv->cdclk.hw.vco = 0;
1647 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1649 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1652 val = CNL_CDCLK_PLL_RATIO(ratio);
1653 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1655 val |= BXT_DE_PLL_PLL_ENABLE;
1656 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1659 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1660 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1662 dev_priv->cdclk.hw.vco = vco;
1665 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1666 const struct intel_cdclk_state *cdclk_state)
1668 int cdclk = cdclk_state->cdclk;
1669 int vco = cdclk_state->vco;
1673 mutex_lock(&dev_priv->pcu_lock);
1674 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1675 SKL_CDCLK_PREPARE_FOR_CHANGE,
1676 SKL_CDCLK_READY_FOR_CHANGE,
1677 SKL_CDCLK_READY_FOR_CHANGE, 3);
1678 mutex_unlock(&dev_priv->pcu_lock);
1680 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1685 /* cdclk = vco / 2 / div{1,2} */
1686 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1688 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1692 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1695 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1699 if (dev_priv->cdclk.hw.vco != 0 &&
1700 dev_priv->cdclk.hw.vco != vco)
1701 cnl_cdclk_pll_disable(dev_priv);
1703 if (dev_priv->cdclk.hw.vco != vco)
1704 cnl_cdclk_pll_enable(dev_priv, vco);
1706 val = divider | skl_cdclk_decimal(cdclk);
1708 * FIXME if only the cd2x divider needs changing, it could be done
1709 * without shutting off the pipe (if only one pipe is active).
1711 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1712 I915_WRITE(CDCLK_CTL, val);
1714 /* inform PCU of the change */
1715 mutex_lock(&dev_priv->pcu_lock);
1716 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1717 cdclk_state->voltage_level);
1718 mutex_unlock(&dev_priv->pcu_lock);
1720 intel_update_cdclk(dev_priv);
1723 * Can't read out the voltage level :(
1724 * Let's just assume everything is as expected.
1726 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1729 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1733 if (cdclk == dev_priv->cdclk.hw.bypass)
1738 MISSING_CASE(cdclk);
1742 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1745 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1749 return dev_priv->cdclk.hw.ref * ratio;
1752 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1754 u32 cdctl, expected;
1756 intel_update_cdclk(dev_priv);
1757 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1759 if (dev_priv->cdclk.hw.vco == 0 ||
1760 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1763 /* DPLL okay; verify the cdclock
1765 * Some BIOS versions leave an incorrect decimal frequency value and
1766 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1767 * so sanitize this register.
1769 cdctl = I915_READ(CDCLK_CTL);
1771 * Let's ignore the pipe field, since BIOS could have configured the
1772 * dividers both synching to an active pipe, or asynchronously
1775 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1777 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1778 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1780 if (cdctl == expected)
1781 /* All well; nothing to sanitize */
1785 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1787 /* force cdclk programming */
1788 dev_priv->cdclk.hw.cdclk = 0;
1790 /* force full PLL disable + enable */
1791 dev_priv->cdclk.hw.vco = -1;
1794 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1796 int ranges_24[] = { 312000, 552000, 648000 };
1797 int ranges_19_38[] = { 307200, 556800, 652800 };
1809 ranges = ranges_19_38;
1813 if (min_cdclk > ranges[1])
1815 else if (min_cdclk > ranges[0])
1821 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1825 if (cdclk == dev_priv->cdclk.hw.bypass)
1830 MISSING_CASE(cdclk);
1835 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1836 dev_priv->cdclk.hw.ref != 38400);
1841 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1844 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1846 return dev_priv->cdclk.hw.ref * ratio;
1849 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1850 const struct intel_cdclk_state *cdclk_state)
1852 unsigned int cdclk = cdclk_state->cdclk;
1853 unsigned int vco = cdclk_state->vco;
1856 mutex_lock(&dev_priv->pcu_lock);
1857 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1858 SKL_CDCLK_PREPARE_FOR_CHANGE,
1859 SKL_CDCLK_READY_FOR_CHANGE,
1860 SKL_CDCLK_READY_FOR_CHANGE, 3);
1861 mutex_unlock(&dev_priv->pcu_lock);
1863 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1868 if (dev_priv->cdclk.hw.vco != 0 &&
1869 dev_priv->cdclk.hw.vco != vco)
1870 cnl_cdclk_pll_disable(dev_priv);
1872 if (dev_priv->cdclk.hw.vco != vco)
1873 cnl_cdclk_pll_enable(dev_priv, vco);
1875 I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1876 skl_cdclk_decimal(cdclk));
1878 mutex_lock(&dev_priv->pcu_lock);
1879 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1880 cdclk_state->voltage_level);
1881 mutex_unlock(&dev_priv->pcu_lock);
1883 intel_update_cdclk(dev_priv);
1886 * Can't read out the voltage level :(
1887 * Let's just assume everything is as expected.
1889 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1892 static u8 icl_calc_voltage_level(int cdclk)
1903 MISSING_CASE(cdclk);
1911 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1912 struct intel_cdclk_state *cdclk_state)
1916 cdclk_state->bypass = 50000;
1918 val = I915_READ(SKL_DSSM);
1919 switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1923 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1924 cdclk_state->ref = 24000;
1926 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1927 cdclk_state->ref = 19200;
1929 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1930 cdclk_state->ref = 38400;
1934 val = I915_READ(BXT_DE_PLL_ENABLE);
1935 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1936 (val & BXT_DE_PLL_LOCK) == 0) {
1938 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1939 * setting it to zero is a way to signal that.
1941 cdclk_state->vco = 0;
1942 cdclk_state->cdclk = cdclk_state->bypass;
1946 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1948 val = I915_READ(CDCLK_CTL);
1949 WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1951 cdclk_state->cdclk = cdclk_state->vco / 2;
1955 * Can't read this out :( Let's assume it's
1956 * at least what the CDCLK frequency requires.
1958 cdclk_state->voltage_level =
1959 icl_calc_voltage_level(cdclk_state->cdclk);
1963 * icl_init_cdclk - Initialize CDCLK on ICL
1964 * @dev_priv: i915 device
1966 * Initialize CDCLK for ICL. This consists mainly of initializing
1967 * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
1968 * is generally done only during the display core initialization sequence, after
1969 * which the DMC will take care of turning CDCLK off/on as needed.
1971 void icl_init_cdclk(struct drm_i915_private *dev_priv)
1973 struct intel_cdclk_state sanitized_state;
1976 /* This sets dev_priv->cdclk.hw. */
1977 intel_update_cdclk(dev_priv);
1978 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1980 /* This means CDCLK disabled. */
1981 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1984 val = I915_READ(CDCLK_CTL);
1986 if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1989 if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1990 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1996 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1998 sanitized_state.ref = dev_priv->cdclk.hw.ref;
1999 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
2000 sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
2001 sanitized_state.cdclk);
2002 sanitized_state.voltage_level =
2003 icl_calc_voltage_level(sanitized_state.cdclk);
2005 icl_set_cdclk(dev_priv, &sanitized_state);
2009 * icl_uninit_cdclk - Uninitialize CDCLK on ICL
2010 * @dev_priv: i915 device
2012 * Uninitialize CDCLK for ICL. This is done only during the display core
2013 * uninitialization sequence.
2015 void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
2017 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2019 cdclk_state.cdclk = cdclk_state.bypass;
2020 cdclk_state.vco = 0;
2021 cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
2023 icl_set_cdclk(dev_priv, &cdclk_state);
2027 * cnl_init_cdclk - Initialize CDCLK on CNL
2028 * @dev_priv: i915 device
2030 * Initialize CDCLK for CNL. This is generally
2031 * done only during the display core initialization sequence,
2032 * after which the DMC will take care of turning CDCLK off/on
2035 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
2037 struct intel_cdclk_state cdclk_state;
2039 cnl_sanitize_cdclk(dev_priv);
2041 if (dev_priv->cdclk.hw.cdclk != 0 &&
2042 dev_priv->cdclk.hw.vco != 0)
2045 cdclk_state = dev_priv->cdclk.hw;
2047 cdclk_state.cdclk = cnl_calc_cdclk(0);
2048 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
2049 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2051 cnl_set_cdclk(dev_priv, &cdclk_state);
2055 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
2056 * @dev_priv: i915 device
2058 * Uninitialize CDCLK for CNL. This is done only
2059 * during the display core uninitialization sequence.
2061 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2063 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2065 cdclk_state.cdclk = cdclk_state.bypass;
2066 cdclk_state.vco = 0;
2067 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2069 cnl_set_cdclk(dev_priv, &cdclk_state);
2073 * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2074 * @a: first CDCLK state
2075 * @b: second CDCLK state
2078 * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2080 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2081 const struct intel_cdclk_state *b)
2083 return a->cdclk != b->cdclk ||
2089 * intel_cdclk_changed - Determine if two CDCLK states are different
2090 * @a: first CDCLK state
2091 * @b: second CDCLK state
2094 * True if the CDCLK states don't match, false if they do.
2096 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2097 const struct intel_cdclk_state *b)
2099 return intel_cdclk_needs_modeset(a, b) ||
2100 a->voltage_level != b->voltage_level;
2103 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2104 const char *context)
2106 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2107 context, cdclk_state->cdclk, cdclk_state->vco,
2108 cdclk_state->ref, cdclk_state->bypass,
2109 cdclk_state->voltage_level);
2113 * intel_set_cdclk - Push the CDCLK state to the hardware
2114 * @dev_priv: i915 device
2115 * @cdclk_state: new CDCLK state
2117 * Program the hardware based on the passed in CDCLK state,
2120 void intel_set_cdclk(struct drm_i915_private *dev_priv,
2121 const struct intel_cdclk_state *cdclk_state)
2123 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2126 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2129 intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2131 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
2133 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2134 "cdclk state doesn't match!\n")) {
2135 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2136 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2140 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2143 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2144 return DIV_ROUND_UP(pixel_rate, 2);
2145 else if (IS_GEN(dev_priv, 9) ||
2146 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2148 else if (IS_CHERRYVIEW(dev_priv))
2149 return DIV_ROUND_UP(pixel_rate * 100, 95);
2151 return DIV_ROUND_UP(pixel_rate * 100, 90);
2154 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2156 struct drm_i915_private *dev_priv =
2157 to_i915(crtc_state->base.crtc->dev);
2160 if (!crtc_state->base.enable)
2163 min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2165 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2166 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2167 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2169 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2170 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2171 * there may be audio corruption or screen corruption." This cdclk
2172 * restriction for GLK is 316.8 MHz.
2174 if (intel_crtc_has_dp_encoder(crtc_state) &&
2175 crtc_state->has_audio &&
2176 crtc_state->port_clock >= 540000 &&
2177 crtc_state->lane_count == 4) {
2178 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2179 /* Display WA #1145: glk,cnl */
2180 min_cdclk = max(316800, min_cdclk);
2181 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2182 /* Display WA #1144: skl,bxt */
2183 min_cdclk = max(432000, min_cdclk);
2188 * According to BSpec, "The CD clock frequency must be at least twice
2189 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2191 * FIXME: Check the actual, not default, BCLK being used.
2193 * FIXME: This does not depend on ->has_audio because the higher CDCLK
2194 * is required for audio probe, also when there are no audio capable
2195 * displays connected at probe time. This leads to unnecessarily high
2196 * CDCLK when audio is not required.
2198 * FIXME: This limit is only applied when there are displays connected
2199 * at probe time. If we probe without displays, we'll still end up using
2200 * the platform minimum CDCLK, failing audio probe.
2202 if (INTEL_GEN(dev_priv) >= 9)
2203 min_cdclk = max(2 * 96000, min_cdclk);
2206 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2209 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2210 IS_VALLEYVIEW(dev_priv))
2211 min_cdclk = max(320000, min_cdclk);
2213 if (min_cdclk > dev_priv->max_cdclk_freq) {
2214 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2215 min_cdclk, dev_priv->max_cdclk_freq);
2222 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
2224 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2225 struct drm_i915_private *dev_priv = to_i915(state->dev);
2226 struct intel_crtc *crtc;
2227 struct intel_crtc_state *crtc_state;
2231 memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2232 sizeof(intel_state->min_cdclk));
2234 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2235 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2239 intel_state->min_cdclk[i] = min_cdclk;
2243 for_each_pipe(dev_priv, pipe)
2244 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
2250 * Note that this functions assumes that 0 is
2251 * the lowest voltage value, and higher values
2252 * correspond to increasingly higher voltages.
2254 * Should that relationship no longer hold on
2255 * future platforms this code will need to be
2258 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2260 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2261 struct intel_crtc *crtc;
2262 struct intel_crtc_state *crtc_state;
2263 u8 min_voltage_level;
2267 memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2268 sizeof(state->min_voltage_level));
2270 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2271 if (crtc_state->base.enable)
2272 state->min_voltage_level[i] =
2273 crtc_state->min_voltage_level;
2275 state->min_voltage_level[i] = 0;
2278 min_voltage_level = 0;
2279 for_each_pipe(dev_priv, pipe)
2280 min_voltage_level = max(state->min_voltage_level[pipe],
2283 return min_voltage_level;
2286 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2288 struct drm_i915_private *dev_priv = to_i915(state->dev);
2289 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2290 int min_cdclk, cdclk;
2292 min_cdclk = intel_compute_min_cdclk(state);
2296 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2298 intel_state->cdclk.logical.cdclk = cdclk;
2299 intel_state->cdclk.logical.voltage_level =
2300 vlv_calc_voltage_level(dev_priv, cdclk);
2302 if (!intel_state->active_crtcs) {
2303 cdclk = vlv_calc_cdclk(dev_priv, 0);
2305 intel_state->cdclk.actual.cdclk = cdclk;
2306 intel_state->cdclk.actual.voltage_level =
2307 vlv_calc_voltage_level(dev_priv, cdclk);
2309 intel_state->cdclk.actual =
2310 intel_state->cdclk.logical;
2316 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2318 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2319 int min_cdclk, cdclk;
2321 min_cdclk = intel_compute_min_cdclk(state);
2326 * FIXME should also account for plane ratio
2327 * once 64bpp pixel formats are supported.
2329 cdclk = bdw_calc_cdclk(min_cdclk);
2331 intel_state->cdclk.logical.cdclk = cdclk;
2332 intel_state->cdclk.logical.voltage_level =
2333 bdw_calc_voltage_level(cdclk);
2335 if (!intel_state->active_crtcs) {
2336 cdclk = bdw_calc_cdclk(0);
2338 intel_state->cdclk.actual.cdclk = cdclk;
2339 intel_state->cdclk.actual.voltage_level =
2340 bdw_calc_voltage_level(cdclk);
2342 intel_state->cdclk.actual =
2343 intel_state->cdclk.logical;
2349 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2351 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2352 struct intel_crtc *crtc;
2353 struct intel_crtc_state *crtc_state;
2356 vco = intel_state->cdclk.logical.vco;
2358 vco = dev_priv->skl_preferred_vco_freq;
2360 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2361 if (!crtc_state->base.enable)
2364 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2368 * DPLL0 VCO may need to be adjusted to get the correct
2369 * clock for eDP. This will affect cdclk as well.
2371 switch (crtc_state->port_clock / 2) {
2385 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2387 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2388 int min_cdclk, cdclk, vco;
2390 min_cdclk = intel_compute_min_cdclk(state);
2394 vco = skl_dpll0_vco(intel_state);
2397 * FIXME should also account for plane ratio
2398 * once 64bpp pixel formats are supported.
2400 cdclk = skl_calc_cdclk(min_cdclk, vco);
2402 intel_state->cdclk.logical.vco = vco;
2403 intel_state->cdclk.logical.cdclk = cdclk;
2404 intel_state->cdclk.logical.voltage_level =
2405 skl_calc_voltage_level(cdclk);
2407 if (!intel_state->active_crtcs) {
2408 cdclk = skl_calc_cdclk(0, vco);
2410 intel_state->cdclk.actual.vco = vco;
2411 intel_state->cdclk.actual.cdclk = cdclk;
2412 intel_state->cdclk.actual.voltage_level =
2413 skl_calc_voltage_level(cdclk);
2415 intel_state->cdclk.actual =
2416 intel_state->cdclk.logical;
2422 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2424 struct drm_i915_private *dev_priv = to_i915(state->dev);
2425 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2426 int min_cdclk, cdclk, vco;
2428 min_cdclk = intel_compute_min_cdclk(state);
2432 if (IS_GEMINILAKE(dev_priv)) {
2433 cdclk = glk_calc_cdclk(min_cdclk);
2434 vco = glk_de_pll_vco(dev_priv, cdclk);
2436 cdclk = bxt_calc_cdclk(min_cdclk);
2437 vco = bxt_de_pll_vco(dev_priv, cdclk);
2440 intel_state->cdclk.logical.vco = vco;
2441 intel_state->cdclk.logical.cdclk = cdclk;
2442 intel_state->cdclk.logical.voltage_level =
2443 bxt_calc_voltage_level(cdclk);
2445 if (!intel_state->active_crtcs) {
2446 if (IS_GEMINILAKE(dev_priv)) {
2447 cdclk = glk_calc_cdclk(0);
2448 vco = glk_de_pll_vco(dev_priv, cdclk);
2450 cdclk = bxt_calc_cdclk(0);
2451 vco = bxt_de_pll_vco(dev_priv, cdclk);
2454 intel_state->cdclk.actual.vco = vco;
2455 intel_state->cdclk.actual.cdclk = cdclk;
2456 intel_state->cdclk.actual.voltage_level =
2457 bxt_calc_voltage_level(cdclk);
2459 intel_state->cdclk.actual =
2460 intel_state->cdclk.logical;
2466 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2468 struct drm_i915_private *dev_priv = to_i915(state->dev);
2469 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2470 int min_cdclk, cdclk, vco;
2472 min_cdclk = intel_compute_min_cdclk(state);
2476 cdclk = cnl_calc_cdclk(min_cdclk);
2477 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2479 intel_state->cdclk.logical.vco = vco;
2480 intel_state->cdclk.logical.cdclk = cdclk;
2481 intel_state->cdclk.logical.voltage_level =
2482 max(cnl_calc_voltage_level(cdclk),
2483 cnl_compute_min_voltage_level(intel_state));
2485 if (!intel_state->active_crtcs) {
2486 cdclk = cnl_calc_cdclk(0);
2487 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2489 intel_state->cdclk.actual.vco = vco;
2490 intel_state->cdclk.actual.cdclk = cdclk;
2491 intel_state->cdclk.actual.voltage_level =
2492 cnl_calc_voltage_level(cdclk);
2494 intel_state->cdclk.actual =
2495 intel_state->cdclk.logical;
2501 static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2503 struct drm_i915_private *dev_priv = to_i915(state->dev);
2504 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2505 unsigned int ref = intel_state->cdclk.logical.ref;
2506 int min_cdclk, cdclk, vco;
2508 min_cdclk = intel_compute_min_cdclk(state);
2512 cdclk = icl_calc_cdclk(min_cdclk, ref);
2513 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2515 intel_state->cdclk.logical.vco = vco;
2516 intel_state->cdclk.logical.cdclk = cdclk;
2517 intel_state->cdclk.logical.voltage_level =
2518 max(icl_calc_voltage_level(cdclk),
2519 cnl_compute_min_voltage_level(intel_state));
2521 if (!intel_state->active_crtcs) {
2522 cdclk = icl_calc_cdclk(0, ref);
2523 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2525 intel_state->cdclk.actual.vco = vco;
2526 intel_state->cdclk.actual.cdclk = cdclk;
2527 intel_state->cdclk.actual.voltage_level =
2528 icl_calc_voltage_level(cdclk);
2530 intel_state->cdclk.actual = intel_state->cdclk.logical;
2536 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2538 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2540 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2541 return 2 * max_cdclk_freq;
2542 else if (IS_GEN(dev_priv, 9) ||
2543 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2544 return max_cdclk_freq;
2545 else if (IS_CHERRYVIEW(dev_priv))
2546 return max_cdclk_freq*95/100;
2547 else if (INTEL_GEN(dev_priv) < 4)
2548 return 2*max_cdclk_freq*90/100;
2550 return max_cdclk_freq*90/100;
2554 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2555 * @dev_priv: i915 device
2557 * Determine the maximum CDCLK frequency the platform supports, and also
2558 * derive the maximum dot clock frequency the maximum CDCLK frequency
2561 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2563 if (IS_ICELAKE(dev_priv)) {
2564 if (dev_priv->cdclk.hw.ref == 24000)
2565 dev_priv->max_cdclk_freq = 648000;
2567 dev_priv->max_cdclk_freq = 652800;
2568 } else if (IS_CANNONLAKE(dev_priv)) {
2569 dev_priv->max_cdclk_freq = 528000;
2570 } else if (IS_GEN9_BC(dev_priv)) {
2571 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2574 vco = dev_priv->skl_preferred_vco_freq;
2575 WARN_ON(vco != 8100000 && vco != 8640000);
2578 * Use the lower (vco 8640) cdclk values as a
2579 * first guess. skl_calc_cdclk() will correct it
2580 * if the preferred vco is 8100 instead.
2582 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2584 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2586 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2591 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2592 } else if (IS_GEMINILAKE(dev_priv)) {
2593 dev_priv->max_cdclk_freq = 316800;
2594 } else if (IS_BROXTON(dev_priv)) {
2595 dev_priv->max_cdclk_freq = 624000;
2596 } else if (IS_BROADWELL(dev_priv)) {
2598 * FIXME with extra cooling we can allow
2599 * 540 MHz for ULX and 675 Mhz for ULT.
2600 * How can we know if extra cooling is
2601 * available? PCI ID, VTB, something else?
2603 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2604 dev_priv->max_cdclk_freq = 450000;
2605 else if (IS_BDW_ULX(dev_priv))
2606 dev_priv->max_cdclk_freq = 450000;
2607 else if (IS_BDW_ULT(dev_priv))
2608 dev_priv->max_cdclk_freq = 540000;
2610 dev_priv->max_cdclk_freq = 675000;
2611 } else if (IS_CHERRYVIEW(dev_priv)) {
2612 dev_priv->max_cdclk_freq = 320000;
2613 } else if (IS_VALLEYVIEW(dev_priv)) {
2614 dev_priv->max_cdclk_freq = 400000;
2616 /* otherwise assume cdclk is fixed */
2617 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2620 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2622 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2623 dev_priv->max_cdclk_freq);
2625 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2626 dev_priv->max_dotclk_freq);
2630 * intel_update_cdclk - Determine the current CDCLK frequency
2631 * @dev_priv: i915 device
2633 * Determine the current CDCLK frequency.
2635 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2637 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2640 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2641 * Programmng [sic] note: bit[9:2] should be programmed to the number
2642 * of cdclk that generates 4MHz reference clock freq which is used to
2643 * generate GMBus clock. This will vary with the cdclk freq.
2645 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2646 I915_WRITE(GMBUSFREQ_VLV,
2647 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2650 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2653 int divider, fraction;
2655 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2665 rawclk = CNP_RAWCLK_DIV(divider / 1000);
2669 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2671 if (HAS_PCH_ICP(dev_priv))
2672 rawclk |= ICP_RAWCLK_NUM(numerator);
2675 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2676 return divider + fraction;
2679 static int pch_rawclk(struct drm_i915_private *dev_priv)
2681 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2684 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2686 /* RAWCLK_FREQ_VLV register updated from power well code */
2687 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2688 CCK_DISPLAY_REF_CLOCK_CONTROL);
2691 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2695 /* hrawclock is 1/4 the FSB frequency */
2696 clkcfg = I915_READ(CLKCFG);
2697 switch (clkcfg & CLKCFG_FSB_MASK) {
2698 case CLKCFG_FSB_400:
2700 case CLKCFG_FSB_533:
2702 case CLKCFG_FSB_667:
2704 case CLKCFG_FSB_800:
2706 case CLKCFG_FSB_1067:
2707 case CLKCFG_FSB_1067_ALT:
2709 case CLKCFG_FSB_1333:
2710 case CLKCFG_FSB_1333_ALT:
2718 * intel_update_rawclk - Determine the current RAWCLK frequency
2719 * @dev_priv: i915 device
2721 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2722 * frequency clock so this needs to done only once.
2724 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2726 if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv))
2727 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2728 else if (HAS_PCH_SPLIT(dev_priv))
2729 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2730 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2731 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2732 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2733 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2735 /* no rawclk on other platforms, or no need to know it */
2738 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2742 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2743 * @dev_priv: i915 device
2745 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2747 if (IS_CHERRYVIEW(dev_priv)) {
2748 dev_priv->display.set_cdclk = chv_set_cdclk;
2749 dev_priv->display.modeset_calc_cdclk =
2750 vlv_modeset_calc_cdclk;
2751 } else if (IS_VALLEYVIEW(dev_priv)) {
2752 dev_priv->display.set_cdclk = vlv_set_cdclk;
2753 dev_priv->display.modeset_calc_cdclk =
2754 vlv_modeset_calc_cdclk;
2755 } else if (IS_BROADWELL(dev_priv)) {
2756 dev_priv->display.set_cdclk = bdw_set_cdclk;
2757 dev_priv->display.modeset_calc_cdclk =
2758 bdw_modeset_calc_cdclk;
2759 } else if (IS_GEN9_LP(dev_priv)) {
2760 dev_priv->display.set_cdclk = bxt_set_cdclk;
2761 dev_priv->display.modeset_calc_cdclk =
2762 bxt_modeset_calc_cdclk;
2763 } else if (IS_GEN9_BC(dev_priv)) {
2764 dev_priv->display.set_cdclk = skl_set_cdclk;
2765 dev_priv->display.modeset_calc_cdclk =
2766 skl_modeset_calc_cdclk;
2767 } else if (IS_CANNONLAKE(dev_priv)) {
2768 dev_priv->display.set_cdclk = cnl_set_cdclk;
2769 dev_priv->display.modeset_calc_cdclk =
2770 cnl_modeset_calc_cdclk;
2771 } else if (IS_ICELAKE(dev_priv)) {
2772 dev_priv->display.set_cdclk = icl_set_cdclk;
2773 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2776 if (IS_ICELAKE(dev_priv))
2777 dev_priv->display.get_cdclk = icl_get_cdclk;
2778 else if (IS_CANNONLAKE(dev_priv))
2779 dev_priv->display.get_cdclk = cnl_get_cdclk;
2780 else if (IS_GEN9_BC(dev_priv))
2781 dev_priv->display.get_cdclk = skl_get_cdclk;
2782 else if (IS_GEN9_LP(dev_priv))
2783 dev_priv->display.get_cdclk = bxt_get_cdclk;
2784 else if (IS_BROADWELL(dev_priv))
2785 dev_priv->display.get_cdclk = bdw_get_cdclk;
2786 else if (IS_HASWELL(dev_priv))
2787 dev_priv->display.get_cdclk = hsw_get_cdclk;
2788 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2789 dev_priv->display.get_cdclk = vlv_get_cdclk;
2790 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2791 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2792 else if (IS_GEN(dev_priv, 5))
2793 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2794 else if (IS_GM45(dev_priv))
2795 dev_priv->display.get_cdclk = gm45_get_cdclk;
2796 else if (IS_G45(dev_priv))
2797 dev_priv->display.get_cdclk = g33_get_cdclk;
2798 else if (IS_I965GM(dev_priv))
2799 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2800 else if (IS_I965G(dev_priv))
2801 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2802 else if (IS_PINEVIEW(dev_priv))
2803 dev_priv->display.get_cdclk = pnv_get_cdclk;
2804 else if (IS_G33(dev_priv))
2805 dev_priv->display.get_cdclk = g33_get_cdclk;
2806 else if (IS_I945GM(dev_priv))
2807 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2808 else if (IS_I945G(dev_priv))
2809 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2810 else if (IS_I915GM(dev_priv))
2811 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2812 else if (IS_I915G(dev_priv))
2813 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2814 else if (IS_I865G(dev_priv))
2815 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2816 else if (IS_I85X(dev_priv))
2817 dev_priv->display.get_cdclk = i85x_get_cdclk;
2818 else if (IS_I845G(dev_priv))
2819 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2821 WARN(!IS_I830(dev_priv),
2822 "Unknown platform. Assuming 133 MHz CDCLK\n");
2823 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;