drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_cdclk.h"
  25 #include "intel_drv.h"
  26 #include "intel_sideband.h"
  27
  28 /**
  29  * DOC: CDCLK / RAWCLK
  30  *
  31  * The display engine uses several different clocks to do its work. There
  32  * are two main clocks involved that aren't directly related to the actual
  33  * pixel clock or any symbol/bit clock of the actual output port. These
  34  * are the core display clock (CDCLK) and RAWCLK.
  35  *
  36  * CDCLK clocks most of the display pipe logic, and thus its frequency
  37  * must be high enough to support the rate at which pixels are flowing
  38  * through the pipes. Downscaling must also be accounted as that increases
  39  * the effective pixel rate.
  40  *
  41  * On several platforms the CDCLK frequency can be changed dynamically
  42  * to minimize power consumption for a given display configuration.
  43  * Typically changes to the CDCLK frequency require all the display pipes
  44  * to be shut down while the frequency is being changed.
  45  *
  46  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  47  * DMC will not change the active CDCLK frequency however, so that part
  48  * will still be performed by the driver directly.
  49  *
  50  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  51  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  52  * really need to know about RAWCLK is its frequency so that various
  53  * dividers can be programmed correctly.
  54  */
  55
  56 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  57                                    struct intel_cdclk_state *cdclk_state)
  58 {
  59         cdclk_state->cdclk = 133333;
  60 }
  61
  62 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  63                                    struct intel_cdclk_state *cdclk_state)
  64 {
  65         cdclk_state->cdclk = 200000;
  66 }
  67
  68 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  69                                    struct intel_cdclk_state *cdclk_state)
  70 {
  71         cdclk_state->cdclk = 266667;
  72 }
  73
  74 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  75                                    struct intel_cdclk_state *cdclk_state)
  76 {
  77         cdclk_state->cdclk = 333333;
  78 }
  79
  80 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  81                                    struct intel_cdclk_state *cdclk_state)
  82 {
  83         cdclk_state->cdclk = 400000;
  84 }
  85
  86 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  87                                    struct intel_cdclk_state *cdclk_state)
  88 {
  89         cdclk_state->cdclk = 450000;
  90 }
  91
  92 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  93                            struct intel_cdclk_state *cdclk_state)
  94 {
  95         struct pci_dev *pdev = dev_priv->drm.pdev;
  96         u16 hpllcc = 0;
  97
  98         /*
  99          * 852GM/852GMV only supports 133 MHz and the HPLLCC
 100          * encoding is different :(
 101          * FIXME is this the right way to detect 852GM/852GMV?
 102          */
 103         if (pdev->revision == 0x1) {
 104                 cdclk_state->cdclk = 133333;
 105                 return;
 106         }
 107
 108         pci_bus_read_config_word(pdev->bus,
 109                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 110
 111         /* Assume that the hardware is in the high speed state.  This
 112          * should be the default.
 113          */
 114         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 115         case GC_CLOCK_133_200:
 116         case GC_CLOCK_133_200_2:
 117         case GC_CLOCK_100_200:
 118                 cdclk_state->cdclk = 200000;
 119                 break;
 120         case GC_CLOCK_166_250:
 121                 cdclk_state->cdclk = 250000;
 122                 break;
 123         case GC_CLOCK_100_133:
 124                 cdclk_state->cdclk = 133333;
 125                 break;
 126         case GC_CLOCK_133_266:
 127         case GC_CLOCK_133_266_2:
 128         case GC_CLOCK_166_266:
 129                 cdclk_state->cdclk = 266667;
 130                 break;
 131         }
 132 }
 133
 134 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 135                              struct intel_cdclk_state *cdclk_state)
 136 {
 137         struct pci_dev *pdev = dev_priv->drm.pdev;
 138         u16 gcfgc = 0;
 139
 140         pci_read_config_word(pdev, GCFGC, &gcfgc);
 141
 142         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 143                 cdclk_state->cdclk = 133333;
 144                 return;
 145         }
 146
 147         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 148         case GC_DISPLAY_CLOCK_333_320_MHZ:
 149                 cdclk_state->cdclk = 333333;
 150                 break;
 151         default:
 152         case GC_DISPLAY_CLOCK_190_200_MHZ:
 153                 cdclk_state->cdclk = 190000;
 154                 break;
 155         }
 156 }
 157
 158 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 159                              struct intel_cdclk_state *cdclk_state)
 160 {
 161         struct pci_dev *pdev = dev_priv->drm.pdev;
 162         u16 gcfgc = 0;
 163
 164         pci_read_config_word(pdev, GCFGC, &gcfgc);
 165
 166         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 167                 cdclk_state->cdclk = 133333;
 168                 return;
 169         }
 170
 171         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 172         case GC_DISPLAY_CLOCK_333_320_MHZ:
 173                 cdclk_state->cdclk = 320000;
 174                 break;
 175         default:
 176         case GC_DISPLAY_CLOCK_190_200_MHZ:
 177                 cdclk_state->cdclk = 200000;
 178                 break;
 179         }
 180 }
 181
 182 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 183 {
 184         static const unsigned int blb_vco[8] = {
 185                 [0] = 3200000,
 186                 [1] = 4000000,
 187                 [2] = 5333333,
 188                 [3] = 4800000,
 189                 [4] = 6400000,
 190         };
 191         static const unsigned int pnv_vco[8] = {
 192                 [0] = 3200000,
 193                 [1] = 4000000,
 194                 [2] = 5333333,
 195                 [3] = 4800000,
 196                 [4] = 2666667,
 197         };
 198         static const unsigned int cl_vco[8] = {
 199                 [0] = 3200000,
 200                 [1] = 4000000,
 201                 [2] = 5333333,
 202                 [3] = 6400000,
 203                 [4] = 3333333,
 204                 [5] = 3566667,
 205                 [6] = 4266667,
 206         };
 207         static const unsigned int elk_vco[8] = {
 208                 [0] = 3200000,
 209                 [1] = 4000000,
 210                 [2] = 5333333,
 211                 [3] = 4800000,
 212         };
 213         static const unsigned int ctg_vco[8] = {
 214                 [0] = 3200000,
 215                 [1] = 4000000,
 216                 [2] = 5333333,
 217                 [3] = 6400000,
 218                 [4] = 2666667,
 219                 [5] = 4266667,
 220         };
 221         const unsigned int *vco_table;
 222         unsigned int vco;
 223         u8 tmp = 0;
 224
 225         /* FIXME other chipsets? */
 226         if (IS_GM45(dev_priv))
 227                 vco_table = ctg_vco;
 228         else if (IS_G45(dev_priv))
 229                 vco_table = elk_vco;
 230         else if (IS_I965GM(dev_priv))
 231                 vco_table = cl_vco;
 232         else if (IS_PINEVIEW(dev_priv))
 233                 vco_table = pnv_vco;
 234         else if (IS_G33(dev_priv))
 235                 vco_table = blb_vco;
 236         else
 237                 return 0;
 238
 239         tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
 240                         HPLLVCO_MOBILE : HPLLVCO);
 241
 242         vco = vco_table[tmp & 0x7];
 243         if (vco == 0)
 244                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 245         else
 246                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 247
 248         return vco;
 249 }
 250
 251 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 252                           struct intel_cdclk_state *cdclk_state)
 253 {
 254         struct pci_dev *pdev = dev_priv->drm.pdev;
 255         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 256         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 257         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 258         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 259         const u8 *div_table;
 260         unsigned int cdclk_sel;
 261         u16 tmp = 0;
 262
 263         cdclk_state->vco = intel_hpll_vco(dev_priv);
 264
 265         pci_read_config_word(pdev, GCFGC, &tmp);
 266
 267         cdclk_sel = (tmp >> 4) & 0x7;
 268
 269         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 270                 goto fail;
 271
 272         switch (cdclk_state->vco) {
 273         case 3200000:
 274                 div_table = div_3200;
 275                 break;
 276         case 4000000:
 277                 div_table = div_4000;
 278                 break;
 279         case 4800000:
 280                 div_table = div_4800;
 281                 break;
 282         case 5333333:
 283                 div_table = div_5333;
 284                 break;
 285         default:
 286                 goto fail;
 287         }
 288
 289         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 290                                                div_table[cdclk_sel]);
 291         return;
 292
 293 fail:
 294         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 295                   cdclk_state->vco, tmp);
 296         cdclk_state->cdclk = 190476;
 297 }
 298
 299 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 300                           struct intel_cdclk_state *cdclk_state)
 301 {
 302         struct pci_dev *pdev = dev_priv->drm.pdev;
 303         u16 gcfgc = 0;
 304
 305         pci_read_config_word(pdev, GCFGC, &gcfgc);
 306
 307         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 308         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 309                 cdclk_state->cdclk = 266667;
 310                 break;
 311         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 312                 cdclk_state->cdclk = 333333;
 313                 break;
 314         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 315                 cdclk_state->cdclk = 444444;
 316                 break;
 317         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 318                 cdclk_state->cdclk = 200000;
 319                 break;
 320         default:
 321                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 322                 /* fall through */
 323         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 324                 cdclk_state->cdclk = 133333;
 325                 break;
 326         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 327                 cdclk_state->cdclk = 166667;
 328                 break;
 329         }
 330 }
 331
 332 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 333                              struct intel_cdclk_state *cdclk_state)
 334 {
 335         struct pci_dev *pdev = dev_priv->drm.pdev;
 336         static const u8 div_3200[] = { 16, 10,  8 };
 337         static const u8 div_4000[] = { 20, 12, 10 };
 338         static const u8 div_5333[] = { 24, 16, 14 };
 339         const u8 *div_table;
 340         unsigned int cdclk_sel;
 341         u16 tmp = 0;
 342
 343         cdclk_state->vco = intel_hpll_vco(dev_priv);
 344
 345         pci_read_config_word(pdev, GCFGC, &tmp);
 346
 347         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 348
 349         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 350                 goto fail;
 351
 352         switch (cdclk_state->vco) {
 353         case 3200000:
 354                 div_table = div_3200;
 355                 break;
 356         case 4000000:
 357                 div_table = div_4000;
 358                 break;
 359         case 5333333:
 360                 div_table = div_5333;
 361                 break;
 362         default:
 363                 goto fail;
 364         }
 365
 366         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 367                                                div_table[cdclk_sel]);
 368         return;
 369
 370 fail:
 371         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 372                   cdclk_state->vco, tmp);
 373         cdclk_state->cdclk = 200000;
 374 }
 375
 376 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 377                            struct intel_cdclk_state *cdclk_state)
 378 {
 379         struct pci_dev *pdev = dev_priv->drm.pdev;
 380         unsigned int cdclk_sel;
 381         u16 tmp = 0;
 382
 383         cdclk_state->vco = intel_hpll_vco(dev_priv);
 384
 385         pci_read_config_word(pdev, GCFGC, &tmp);
 386
 387         cdclk_sel = (tmp >> 12) & 0x1;
 388
 389         switch (cdclk_state->vco) {
 390         case 2666667:
 391         case 4000000:
 392         case 5333333:
 393                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 394                 break;
 395         case 3200000:
 396                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 397                 break;
 398         default:
 399                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 400                           cdclk_state->vco, tmp);
 401                 cdclk_state->cdclk = 222222;
 402                 break;
 403         }
 404 }
 405
 406 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 407                           struct intel_cdclk_state *cdclk_state)
 408 {
 409         u32 lcpll = I915_READ(LCPLL_CTL);
 410         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 411
 412         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 413                 cdclk_state->cdclk = 800000;
 414         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 415                 cdclk_state->cdclk = 450000;
 416         else if (freq == LCPLL_CLK_FREQ_450)
 417                 cdclk_state->cdclk = 450000;
 418         else if (IS_HSW_ULT(dev_priv))
 419                 cdclk_state->cdclk = 337500;
 420         else
 421                 cdclk_state->cdclk = 540000;
 422 }
 423
 424 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 425 {
 426         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 427                 333333 : 320000;
 428
 429         /*
 430          * We seem to get an unstable or solid color picture at 200MHz.
 431          * Not sure what's wrong. For now use 200MHz only when all pipes
 432          * are off.
 433          */
 434         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 435                 return 400000;
 436         else if (min_cdclk > 266667)
 437                 return freq_320;
 438         else if (min_cdclk > 0)
 439                 return 266667;
 440         else
 441                 return 200000;
 442 }
 443
 444 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 445 {
 446         if (IS_VALLEYVIEW(dev_priv)) {
 447                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 448                         return 2;
 449                 else if (cdclk >= 266667)
 450                         return 1;
 451                 else
 452                         return 0;
 453         } else {
 454                 /*
 455                  * Specs are full of misinformation, but testing on actual
 456                  * hardware has shown that we just need to write the desired
 457                  * CCK divider into the Punit register.
 458                  */
 459                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 460         }
 461 }
 462
 463 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 464                           struct intel_cdclk_state *cdclk_state)
 465 {
 466         u32 val;
 467
 468         vlv_iosf_sb_get(dev_priv,
 469                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 470
 471         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 472         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 473                                                CCK_DISPLAY_CLOCK_CONTROL,
 474                                                cdclk_state->vco);
 475
 476         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 477
 478         vlv_iosf_sb_put(dev_priv,
 479                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 480
 481         if (IS_VALLEYVIEW(dev_priv))
 482                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 483                         DSPFREQGUAR_SHIFT;
 484         else
 485                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 486                         DSPFREQGUAR_SHIFT_CHV;
 487 }
 488
 489 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 490 {
 491         unsigned int credits, default_credits;
 492
 493         if (IS_CHERRYVIEW(dev_priv))
 494                 default_credits = PFI_CREDIT(12);
 495         else
 496                 default_credits = PFI_CREDIT(8);
 497
 498         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 499                 /* CHV suggested value is 31 or 63 */
 500                 if (IS_CHERRYVIEW(dev_priv))
 501                         credits = PFI_CREDIT_63;
 502                 else
 503                         credits = PFI_CREDIT(15);
 504         } else {
 505                 credits = default_credits;
 506         }
 507
 508         /*
 509          * WA - write default credits before re-programming
 510          * FIXME: should we also set the resend bit here?
 511          */
 512         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 513                    default_credits);
 514
 515         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 516                    credits | PFI_CREDIT_RESEND);
 517
 518         /*
 519          * FIXME is this guaranteed to clear
 520          * immediately or should we poll for it?
 521          */
 522         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 523 }
 524
 525 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 526                           const struct intel_cdclk_state *cdclk_state,
 527                           enum pipe pipe)
 528 {
 529         int cdclk = cdclk_state->cdclk;
 530         u32 val, cmd = cdclk_state->voltage_level;
 531         intel_wakeref_t wakeref;
 532
 533         switch (cdclk) {
 534         case 400000:
 535         case 333333:
 536         case 320000:
 537         case 266667:
 538         case 200000:
 539                 break;
 540         default:
 541                 MISSING_CASE(cdclk);
 542                 return;
 543         }
 544
 545         /* There are cases where we can end up here with power domains
 546          * off and a CDCLK frequency other than the minimum, like when
 547          * issuing a modeset without actually changing any display after
 548          * a system suspend.  So grab the PIPE-A domain, which covers
 549          * the HW blocks needed for the following programming.
 550          */
 551         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 552
 553         vlv_iosf_sb_get(dev_priv,
 554                         BIT(VLV_IOSF_SB_CCK) |
 555                         BIT(VLV_IOSF_SB_BUNIT) |
 556                         BIT(VLV_IOSF_SB_PUNIT));
 557
 558         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 559         val &= ~DSPFREQGUAR_MASK;
 560         val |= (cmd << DSPFREQGUAR_SHIFT);
 561         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 562         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 563                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 564                      50)) {
 565                 DRM_ERROR("timed out waiting for CDclk change\n");
 566         }
 567
 568         if (cdclk == 400000) {
 569                 u32 divider;
 570
 571                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 572                                             cdclk) - 1;
 573
 574                 /* adjust cdclk divider */
 575                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 576                 val &= ~CCK_FREQUENCY_VALUES;
 577                 val |= divider;
 578                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 579
 580                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 581                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 582                              50))
 583                         DRM_ERROR("timed out waiting for CDclk change\n");
 584         }
 585
 586         /* adjust self-refresh exit latency value */
 587         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 588         val &= ~0x7f;
 589
 590         /*
 591          * For high bandwidth configs, we set a higher latency in the bunit
 592          * so that the core display fetch happens in time to avoid underruns.
 593          */
 594         if (cdclk == 400000)
 595                 val |= 4500 / 250; /* 4.5 usec */
 596         else
 597                 val |= 3000 / 250; /* 3.0 usec */
 598         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 599
 600         vlv_iosf_sb_put(dev_priv,
 601                         BIT(VLV_IOSF_SB_CCK) |
 602                         BIT(VLV_IOSF_SB_BUNIT) |
 603                         BIT(VLV_IOSF_SB_PUNIT));
 604
 605         intel_update_cdclk(dev_priv);
 606
 607         vlv_program_pfi_credits(dev_priv);
 608
 609         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
 610 }
 611
 612 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 613                           const struct intel_cdclk_state *cdclk_state,
 614                           enum pipe pipe)
 615 {
 616         int cdclk = cdclk_state->cdclk;
 617         u32 val, cmd = cdclk_state->voltage_level;
 618         intel_wakeref_t wakeref;
 619
 620         switch (cdclk) {
 621         case 333333:
 622         case 320000:
 623         case 266667:
 624         case 200000:
 625                 break;
 626         default:
 627                 MISSING_CASE(cdclk);
 628                 return;
 629         }
 630
 631         /* There are cases where we can end up here with power domains
 632          * off and a CDCLK frequency other than the minimum, like when
 633          * issuing a modeset without actually changing any display after
 634          * a system suspend.  So grab the PIPE-A domain, which covers
 635          * the HW blocks needed for the following programming.
 636          */
 637         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 638
 639         vlv_punit_get(dev_priv);
 640         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 641         val &= ~DSPFREQGUAR_MASK_CHV;
 642         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 643         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 644         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 645                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 646                      50)) {
 647                 DRM_ERROR("timed out waiting for CDclk change\n");
 648         }
 649
 650         vlv_punit_put(dev_priv);
 651
 652         intel_update_cdclk(dev_priv);
 653
 654         vlv_program_pfi_credits(dev_priv);
 655
 656         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
 657 }
 658
 659 static int bdw_calc_cdclk(int min_cdclk)
 660 {
 661         if (min_cdclk > 540000)
 662                 return 675000;
 663         else if (min_cdclk > 450000)
 664                 return 540000;
 665         else if (min_cdclk > 337500)
 666                 return 450000;
 667         else
 668                 return 337500;
 669 }
 670
 671 static u8 bdw_calc_voltage_level(int cdclk)
 672 {
 673         switch (cdclk) {
 674         default:
 675         case 337500:
 676                 return 2;
 677         case 450000:
 678                 return 0;
 679         case 540000:
 680                 return 1;
 681         case 675000:
 682                 return 3;
 683         }
 684 }
 685
 686 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 687                           struct intel_cdclk_state *cdclk_state)
 688 {
 689         u32 lcpll = I915_READ(LCPLL_CTL);
 690         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 691
 692         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 693                 cdclk_state->cdclk = 800000;
 694         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 695                 cdclk_state->cdclk = 450000;
 696         else if (freq == LCPLL_CLK_FREQ_450)
 697                 cdclk_state->cdclk = 450000;
 698         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 699                 cdclk_state->cdclk = 540000;
 700         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 701                 cdclk_state->cdclk = 337500;
 702         else
 703                 cdclk_state->cdclk = 675000;
 704
 705         /*
 706          * Can't read this out :( Let's assume it's
 707          * at least what the CDCLK frequency requires.
 708          */
 709         cdclk_state->voltage_level =
 710                 bdw_calc_voltage_level(cdclk_state->cdclk);
 711 }
 712
 713 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 714                           const struct intel_cdclk_state *cdclk_state,
 715                           enum pipe pipe)
 716 {
 717         int cdclk = cdclk_state->cdclk;
 718         u32 val;
 719         int ret;
 720
 721         if (WARN((I915_READ(LCPLL_CTL) &
 722                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 723                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 724                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 725                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 726                  "trying to change cdclk frequency with cdclk not enabled\n"))
 727                 return;
 728
 729         ret = sandybridge_pcode_write(dev_priv,
 730                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 731         if (ret) {
 732                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 733                 return;
 734         }
 735
 736         val = I915_READ(LCPLL_CTL);
 737         val |= LCPLL_CD_SOURCE_FCLK;
 738         I915_WRITE(LCPLL_CTL, val);
 739
 740         /*
 741          * According to the spec, it should be enough to poll for this 1 us.
 742          * However, extensive testing shows that this can take longer.
 743          */
 744         if (wait_for_us(I915_READ(LCPLL_CTL) &
 745                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 746                 DRM_ERROR("Switching to FCLK failed\n");
 747
 748         val = I915_READ(LCPLL_CTL);
 749         val &= ~LCPLL_CLK_FREQ_MASK;
 750
 751         switch (cdclk) {
 752         default:
 753                 MISSING_CASE(cdclk);
 754                 /* fall through */
 755         case 337500:
 756                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 757                 break;
 758         case 450000:
 759                 val |= LCPLL_CLK_FREQ_450;
 760                 break;
 761         case 540000:
 762                 val |= LCPLL_CLK_FREQ_54O_BDW;
 763                 break;
 764         case 675000:
 765                 val |= LCPLL_CLK_FREQ_675_BDW;
 766                 break;
 767         }
 768
 769         I915_WRITE(LCPLL_CTL, val);
 770
 771         val = I915_READ(LCPLL_CTL);
 772         val &= ~LCPLL_CD_SOURCE_FCLK;
 773         I915_WRITE(LCPLL_CTL, val);
 774
 775         if (wait_for_us((I915_READ(LCPLL_CTL) &
 776                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 777                 DRM_ERROR("Switching back to LCPLL failed\n");
 778
 779         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 780                                 cdclk_state->voltage_level);
 781
 782         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 783
 784         intel_update_cdclk(dev_priv);
 785 }
 786
 787 static int skl_calc_cdclk(int min_cdclk, int vco)
 788 {
 789         if (vco == 8640000) {
 790                 if (min_cdclk > 540000)
 791                         return 617143;
 792                 else if (min_cdclk > 432000)
 793                         return 540000;
 794                 else if (min_cdclk > 308571)
 795                         return 432000;
 796                 else
 797                         return 308571;
 798         } else {
 799                 if (min_cdclk > 540000)
 800                         return 675000;
 801                 else if (min_cdclk > 450000)
 802                         return 540000;
 803                 else if (min_cdclk > 337500)
 804                         return 450000;
 805                 else
 806                         return 337500;
 807         }
 808 }
 809
 810 static u8 skl_calc_voltage_level(int cdclk)
 811 {
 812         switch (cdclk) {
 813         default:
 814         case 308571:
 815         case 337500:
 816                 return 0;
 817         case 450000:
 818         case 432000:
 819                 return 1;
 820         case 540000:
 821                 return 2;
 822         case 617143:
 823         case 675000:
 824                 return 3;
 825         }
 826 }
 827
 828 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 829                              struct intel_cdclk_state *cdclk_state)
 830 {
 831         u32 val;
 832
 833         cdclk_state->ref = 24000;
 834         cdclk_state->vco = 0;
 835
 836         val = I915_READ(LCPLL1_CTL);
 837         if ((val & LCPLL_PLL_ENABLE) == 0)
 838                 return;
 839
 840         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 841                 return;
 842
 843         val = I915_READ(DPLL_CTRL1);
 844
 845         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 846                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 847                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 848                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 849                 return;
 850
 851         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 852         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 853         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 854         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 855         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 856                 cdclk_state->vco = 8100000;
 857                 break;
 858         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 859         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 860                 cdclk_state->vco = 8640000;
 861                 break;
 862         default:
 863                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 864                 break;
 865         }
 866 }
 867
 868 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 869                           struct intel_cdclk_state *cdclk_state)
 870 {
 871         u32 cdctl;
 872
 873         skl_dpll0_update(dev_priv, cdclk_state);
 874
 875         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 876
 877         if (cdclk_state->vco == 0)
 878                 goto out;
 879
 880         cdctl = I915_READ(CDCLK_CTL);
 881
 882         if (cdclk_state->vco == 8640000) {
 883                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 884                 case CDCLK_FREQ_450_432:
 885                         cdclk_state->cdclk = 432000;
 886                         break;
 887                 case CDCLK_FREQ_337_308:
 888                         cdclk_state->cdclk = 308571;
 889                         break;
 890                 case CDCLK_FREQ_540:
 891                         cdclk_state->cdclk = 540000;
 892                         break;
 893                 case CDCLK_FREQ_675_617:
 894                         cdclk_state->cdclk = 617143;
 895                         break;
 896                 default:
 897                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 898                         break;
 899                 }
 900         } else {
 901                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 902                 case CDCLK_FREQ_450_432:
 903                         cdclk_state->cdclk = 450000;
 904                         break;
 905                 case CDCLK_FREQ_337_308:
 906                         cdclk_state->cdclk = 337500;
 907                         break;
 908                 case CDCLK_FREQ_540:
 909                         cdclk_state->cdclk = 540000;
 910                         break;
 911                 case CDCLK_FREQ_675_617:
 912                         cdclk_state->cdclk = 675000;
 913                         break;
 914                 default:
 915                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 916                         break;
 917                 }
 918         }
 919
 920  out:
 921         /*
 922          * Can't read this out :( Let's assume it's
 923          * at least what the CDCLK frequency requires.
 924          */
 925         cdclk_state->voltage_level =
 926                 skl_calc_voltage_level(cdclk_state->cdclk);
 927 }
 928
 929 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 930 static int skl_cdclk_decimal(int cdclk)
 931 {
 932         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 933 }
 934
 935 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 936                                         int vco)
 937 {
 938         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 939
 940         dev_priv->skl_preferred_vco_freq = vco;
 941
 942         if (changed)
 943                 intel_update_max_cdclk(dev_priv);
 944 }
 945
 946 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 947 {
 948         u32 val;
 949
 950         WARN_ON(vco != 8100000 && vco != 8640000);
 951
 952         /*
 953          * We always enable DPLL0 with the lowest link rate possible, but still
 954          * taking into account the VCO required to operate the eDP panel at the
 955          * desired frequency. The usual DP link rates operate with a VCO of
 956          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 957          * The modeset code is responsible for the selection of the exact link
 958          * rate later on, with the constraint of choosing a frequency that
 959          * works with vco.
 960          */
 961         val = I915_READ(DPLL_CTRL1);
 962
 963         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 964                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 965         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 966         if (vco == 8640000)
 967                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 968                                             SKL_DPLL0);
 969         else
 970                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 971                                             SKL_DPLL0);
 972
 973         I915_WRITE(DPLL_CTRL1, val);
 974         POSTING_READ(DPLL_CTRL1);
 975
 976         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 977
 978         if (intel_wait_for_register(&dev_priv->uncore,
 979                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 980                                     5))
 981                 DRM_ERROR("DPLL0 not locked\n");
 982
 983         dev_priv->cdclk.hw.vco = vco;
 984
 985         /* We'll want to keep using the current vco from now on. */
 986         skl_set_preferred_cdclk_vco(dev_priv, vco);
 987 }
 988
 989 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 990 {
 991         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 992         if (intel_wait_for_register(&dev_priv->uncore,
 993                                     LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 994                                     1))
 995                 DRM_ERROR("Couldn't disable DPLL0\n");
 996
 997         dev_priv->cdclk.hw.vco = 0;
 998 }
 999
1000 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1001                           const struct intel_cdclk_state *cdclk_state,
1002                           enum pipe pipe)
1003 {
1004         int cdclk = cdclk_state->cdclk;
1005         int vco = cdclk_state->vco;
1006         u32 freq_select, cdclk_ctl;
1007         int ret;
1008
1009         /*
1010          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1011          * unsupported on SKL. In theory this should never happen since only
1012          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1013          * supported on SKL either, see the above WA. WARN whenever trying to
1014          * use the corresponding VCO freq as that always leads to using the
1015          * minimum 308MHz CDCLK.
1016          */
1017         WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1018
1019         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1020                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1021                                 SKL_CDCLK_READY_FOR_CHANGE,
1022                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1023         if (ret) {
1024                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1025                           ret);
1026                 return;
1027         }
1028
1029         /* Choose frequency for this cdclk */
1030         switch (cdclk) {
1031         default:
1032                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1033                 WARN_ON(vco != 0);
1034                 /* fall through */
1035         case 308571:
1036         case 337500:
1037                 freq_select = CDCLK_FREQ_337_308;
1038                 break;
1039         case 450000:
1040         case 432000:
1041                 freq_select = CDCLK_FREQ_450_432;
1042                 break;
1043         case 540000:
1044                 freq_select = CDCLK_FREQ_540;
1045                 break;
1046         case 617143:
1047         case 675000:
1048                 freq_select = CDCLK_FREQ_675_617;
1049                 break;
1050         }
1051
1052         if (dev_priv->cdclk.hw.vco != 0 &&
1053             dev_priv->cdclk.hw.vco != vco)
1054                 skl_dpll0_disable(dev_priv);
1055
1056         cdclk_ctl = I915_READ(CDCLK_CTL);
1057
1058         if (dev_priv->cdclk.hw.vco != vco) {
1059                 /* Wa Display #1183: skl,kbl,cfl */
1060                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1061                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1062                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1063         }
1064
1065         /* Wa Display #1183: skl,kbl,cfl */
1066         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1067         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1068         POSTING_READ(CDCLK_CTL);
1069
1070         if (dev_priv->cdclk.hw.vco != vco)
1071                 skl_dpll0_enable(dev_priv, vco);
1072
1073         /* Wa Display #1183: skl,kbl,cfl */
1074         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1075         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1076
1077         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1078         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1079
1080         /* Wa Display #1183: skl,kbl,cfl */
1081         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1082         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1083         POSTING_READ(CDCLK_CTL);
1084
1085         /* inform PCU of the change */
1086         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1087                                 cdclk_state->voltage_level);
1088
1089         intel_update_cdclk(dev_priv);
1090 }
1091
1092 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1093 {
1094         u32 cdctl, expected;
1095
1096         /*
1097          * check if the pre-os initialized the display
1098          * There is SWF18 scratchpad register defined which is set by the
1099          * pre-os which can be used by the OS drivers to check the status
1100          */
1101         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1102                 goto sanitize;
1103
1104         intel_update_cdclk(dev_priv);
1105         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1106
1107         /* Is PLL enabled and locked ? */
1108         if (dev_priv->cdclk.hw.vco == 0 ||
1109             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1110                 goto sanitize;
1111
1112         /* DPLL okay; verify the cdclock
1113          *
1114          * Noticed in some instances that the freq selection is correct but
1115          * decimal part is programmed wrong from BIOS where pre-os does not
1116          * enable display. Verify the same as well.
1117          */
1118         cdctl = I915_READ(CDCLK_CTL);
1119         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1120                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1121         if (cdctl == expected)
1122                 /* All well; nothing to sanitize */
1123                 return;
1124
1125 sanitize:
1126         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1127
1128         /* force cdclk programming */
1129         dev_priv->cdclk.hw.cdclk = 0;
1130         /* force full PLL disable + enable */
1131         dev_priv->cdclk.hw.vco = -1;
1132 }
1133
1134 static void skl_init_cdclk(struct drm_i915_private *dev_priv)
1135 {
1136         struct intel_cdclk_state cdclk_state;
1137
1138         skl_sanitize_cdclk(dev_priv);
1139
1140         if (dev_priv->cdclk.hw.cdclk != 0 &&
1141             dev_priv->cdclk.hw.vco != 0) {
1142                 /*
1143                  * Use the current vco as our initial
1144                  * guess as to what the preferred vco is.
1145                  */
1146                 if (dev_priv->skl_preferred_vco_freq == 0)
1147                         skl_set_preferred_cdclk_vco(dev_priv,
1148                                                     dev_priv->cdclk.hw.vco);
1149                 return;
1150         }
1151
1152         cdclk_state = dev_priv->cdclk.hw;
1153
1154         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1155         if (cdclk_state.vco == 0)
1156                 cdclk_state.vco = 8100000;
1157         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1158         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1159
1160         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1161 }
1162
1163 static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1164 {
1165         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1166
1167         cdclk_state.cdclk = cdclk_state.bypass;
1168         cdclk_state.vco = 0;
1169         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1170
1171         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1172 }
1173
1174 static int bxt_calc_cdclk(int min_cdclk)
1175 {
1176         if (min_cdclk > 576000)
1177                 return 624000;
1178         else if (min_cdclk > 384000)
1179                 return 576000;
1180         else if (min_cdclk > 288000)
1181                 return 384000;
1182         else if (min_cdclk > 144000)
1183                 return 288000;
1184         else
1185                 return 144000;
1186 }
1187
1188 static int glk_calc_cdclk(int min_cdclk)
1189 {
1190         if (min_cdclk > 158400)
1191                 return 316800;
1192         else if (min_cdclk > 79200)
1193                 return 158400;
1194         else
1195                 return 79200;
1196 }
1197
1198 static u8 bxt_calc_voltage_level(int cdclk)
1199 {
1200         return DIV_ROUND_UP(cdclk, 25000);
1201 }
1202
1203 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1204 {
1205         int ratio;
1206
1207         if (cdclk == dev_priv->cdclk.hw.bypass)
1208                 return 0;
1209
1210         switch (cdclk) {
1211         default:
1212                 MISSING_CASE(cdclk);
1213                 /* fall through */
1214         case 144000:
1215         case 288000:
1216         case 384000:
1217         case 576000:
1218                 ratio = 60;
1219                 break;
1220         case 624000:
1221                 ratio = 65;
1222                 break;
1223         }
1224
1225         return dev_priv->cdclk.hw.ref * ratio;
1226 }
1227
1228 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1229 {
1230         int ratio;
1231
1232         if (cdclk == dev_priv->cdclk.hw.bypass)
1233                 return 0;
1234
1235         switch (cdclk) {
1236         default:
1237                 MISSING_CASE(cdclk);
1238                 /* fall through */
1239         case  79200:
1240         case 158400:
1241         case 316800:
1242                 ratio = 33;
1243                 break;
1244         }
1245
1246         return dev_priv->cdclk.hw.ref * ratio;
1247 }
1248
1249 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1250                               struct intel_cdclk_state *cdclk_state)
1251 {
1252         u32 val;
1253
1254         cdclk_state->ref = 19200;
1255         cdclk_state->vco = 0;
1256
1257         val = I915_READ(BXT_DE_PLL_ENABLE);
1258         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1259                 return;
1260
1261         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1262                 return;
1263
1264         val = I915_READ(BXT_DE_PLL_CTL);
1265         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1266 }
1267
1268 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1269                           struct intel_cdclk_state *cdclk_state)
1270 {
1271         u32 divider;
1272         int div;
1273
1274         bxt_de_pll_update(dev_priv, cdclk_state);
1275
1276         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1277
1278         if (cdclk_state->vco == 0)
1279                 goto out;
1280
1281         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1282
1283         switch (divider) {
1284         case BXT_CDCLK_CD2X_DIV_SEL_1:
1285                 div = 2;
1286                 break;
1287         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1288                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1289                 div = 3;
1290                 break;
1291         case BXT_CDCLK_CD2X_DIV_SEL_2:
1292                 div = 4;
1293                 break;
1294         case BXT_CDCLK_CD2X_DIV_SEL_4:
1295                 div = 8;
1296                 break;
1297         default:
1298                 MISSING_CASE(divider);
1299                 return;
1300         }
1301
1302         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1303
1304  out:
1305         /*
1306          * Can't read this out :( Let's assume it's
1307          * at least what the CDCLK frequency requires.
1308          */
1309         cdclk_state->voltage_level =
1310                 bxt_calc_voltage_level(cdclk_state->cdclk);
1311 }
1312
1313 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1314 {
1315         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1316
1317         /* Timeout 200us */
1318         if (intel_wait_for_register(&dev_priv->uncore,
1319                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1320                                     1))
1321                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1322
1323         dev_priv->cdclk.hw.vco = 0;
1324 }
1325
1326 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1327 {
1328         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1329         u32 val;
1330
1331         val = I915_READ(BXT_DE_PLL_CTL);
1332         val &= ~BXT_DE_PLL_RATIO_MASK;
1333         val |= BXT_DE_PLL_RATIO(ratio);
1334         I915_WRITE(BXT_DE_PLL_CTL, val);
1335
1336         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1337
1338         /* Timeout 200us */
1339         if (intel_wait_for_register(&dev_priv->uncore,
1340                                     BXT_DE_PLL_ENABLE,
1341                                     BXT_DE_PLL_LOCK,
1342                                     BXT_DE_PLL_LOCK,
1343                                     1))
1344                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1345
1346         dev_priv->cdclk.hw.vco = vco;
1347 }
1348
1349 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1350                           const struct intel_cdclk_state *cdclk_state,
1351                           enum pipe pipe)
1352 {
1353         int cdclk = cdclk_state->cdclk;
1354         int vco = cdclk_state->vco;
1355         u32 val, divider;
1356         int ret;
1357
1358         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1359         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1360         default:
1361                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1362                 WARN_ON(vco != 0);
1363                 /* fall through */
1364         case 2:
1365                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1366                 break;
1367         case 3:
1368                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1369                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1370                 break;
1371         case 4:
1372                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1373                 break;
1374         case 8:
1375                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1376                 break;
1377         }
1378
1379         /*
1380          * Inform power controller of upcoming frequency change. BSpec
1381          * requires us to wait up to 150usec, but that leads to timeouts;
1382          * the 2ms used here is based on experiment.
1383          */
1384         ret = sandybridge_pcode_write_timeout(dev_priv,
1385                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1386                                               0x80000000, 150, 2);
1387         if (ret) {
1388                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1389                           ret, cdclk);
1390                 return;
1391         }
1392
1393         if (dev_priv->cdclk.hw.vco != 0 &&
1394             dev_priv->cdclk.hw.vco != vco)
1395                 bxt_de_pll_disable(dev_priv);
1396
1397         if (dev_priv->cdclk.hw.vco != vco)
1398                 bxt_de_pll_enable(dev_priv, vco);
1399
1400         val = divider | skl_cdclk_decimal(cdclk);
1401         if (pipe == INVALID_PIPE)
1402                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1403         else
1404                 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1405         /*
1406          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1407          * enable otherwise.
1408          */
1409         if (cdclk >= 500000)
1410                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1411         I915_WRITE(CDCLK_CTL, val);
1412
1413         if (pipe != INVALID_PIPE)
1414                 intel_wait_for_vblank(dev_priv, pipe);
1415
1416         /*
1417          * The timeout isn't specified, the 2ms used here is based on
1418          * experiment.
1419          * FIXME: Waiting for the request completion could be delayed until
1420          * the next PCODE request based on BSpec.
1421          */
1422         ret = sandybridge_pcode_write_timeout(dev_priv,
1423                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1424                                               cdclk_state->voltage_level, 150, 2);
1425         if (ret) {
1426                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1427                           ret, cdclk);
1428                 return;
1429         }
1430
1431         intel_update_cdclk(dev_priv);
1432 }
1433
1434 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1435 {
1436         u32 cdctl, expected;
1437
1438         intel_update_cdclk(dev_priv);
1439         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1440
1441         if (dev_priv->cdclk.hw.vco == 0 ||
1442             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1443                 goto sanitize;
1444
1445         /* DPLL okay; verify the cdclock
1446          *
1447          * Some BIOS versions leave an incorrect decimal frequency value and
1448          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1449          * so sanitize this register.
1450          */
1451         cdctl = I915_READ(CDCLK_CTL);
1452         /*
1453          * Let's ignore the pipe field, since BIOS could have configured the
1454          * dividers both synching to an active pipe, or asynchronously
1455          * (PIPE_NONE).
1456          */
1457         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1458
1459         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1460                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1461         /*
1462          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1463          * enable otherwise.
1464          */
1465         if (dev_priv->cdclk.hw.cdclk >= 500000)
1466                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1467
1468         if (cdctl == expected)
1469                 /* All well; nothing to sanitize */
1470                 return;
1471
1472 sanitize:
1473         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1474
1475         /* force cdclk programming */
1476         dev_priv->cdclk.hw.cdclk = 0;
1477
1478         /* force full PLL disable + enable */
1479         dev_priv->cdclk.hw.vco = -1;
1480 }
1481
1482 static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1483 {
1484         struct intel_cdclk_state cdclk_state;
1485
1486         bxt_sanitize_cdclk(dev_priv);
1487
1488         if (dev_priv->cdclk.hw.cdclk != 0 &&
1489             dev_priv->cdclk.hw.vco != 0)
1490                 return;
1491
1492         cdclk_state = dev_priv->cdclk.hw;
1493
1494         /*
1495          * FIXME:
1496          * - The initial CDCLK needs to be read from VBT.
1497          *   Need to make this change after VBT has changes for BXT.
1498          */
1499         if (IS_GEMINILAKE(dev_priv)) {
1500                 cdclk_state.cdclk = glk_calc_cdclk(0);
1501                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1502         } else {
1503                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1504                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1505         }
1506         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1507
1508         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1509 }
1510
1511 static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1512 {
1513         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1514
1515         cdclk_state.cdclk = cdclk_state.bypass;
1516         cdclk_state.vco = 0;
1517         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1518
1519         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1520 }
1521
1522 static int cnl_calc_cdclk(int min_cdclk)
1523 {
1524         if (min_cdclk > 336000)
1525                 return 528000;
1526         else if (min_cdclk > 168000)
1527                 return 336000;
1528         else
1529                 return 168000;
1530 }
1531
1532 static u8 cnl_calc_voltage_level(int cdclk)
1533 {
1534         switch (cdclk) {
1535         default:
1536         case 168000:
1537                 return 0;
1538         case 336000:
1539                 return 1;
1540         case 528000:
1541                 return 2;
1542         }
1543 }
1544
1545 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1546                                  struct intel_cdclk_state *cdclk_state)
1547 {
1548         u32 val;
1549
1550         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1551                 cdclk_state->ref = 24000;
1552         else
1553                 cdclk_state->ref = 19200;
1554
1555         cdclk_state->vco = 0;
1556
1557         val = I915_READ(BXT_DE_PLL_ENABLE);
1558         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1559                 return;
1560
1561         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1562                 return;
1563
1564         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1565 }
1566
1567 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1568                          struct intel_cdclk_state *cdclk_state)
1569 {
1570         u32 divider;
1571         int div;
1572
1573         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1574
1575         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1576
1577         if (cdclk_state->vco == 0)
1578                 goto out;
1579
1580         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1581
1582         switch (divider) {
1583         case BXT_CDCLK_CD2X_DIV_SEL_1:
1584                 div = 2;
1585                 break;
1586         case BXT_CDCLK_CD2X_DIV_SEL_2:
1587                 div = 4;
1588                 break;
1589         default:
1590                 MISSING_CASE(divider);
1591                 return;
1592         }
1593
1594         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1595
1596  out:
1597         /*
1598          * Can't read this out :( Let's assume it's
1599          * at least what the CDCLK frequency requires.
1600          */
1601         cdclk_state->voltage_level =
1602                 cnl_calc_voltage_level(cdclk_state->cdclk);
1603 }
1604
1605 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1606 {
1607         u32 val;
1608
1609         val = I915_READ(BXT_DE_PLL_ENABLE);
1610         val &= ~BXT_DE_PLL_PLL_ENABLE;
1611         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1612
1613         /* Timeout 200us */
1614         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1615                 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1616
1617         dev_priv->cdclk.hw.vco = 0;
1618 }
1619
1620 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1621 {
1622         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1623         u32 val;
1624
1625         val = CNL_CDCLK_PLL_RATIO(ratio);
1626         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1627
1628         val |= BXT_DE_PLL_PLL_ENABLE;
1629         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1630
1631         /* Timeout 200us */
1632         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1633                 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1634
1635         dev_priv->cdclk.hw.vco = vco;
1636 }
1637
1638 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1639                           const struct intel_cdclk_state *cdclk_state,
1640                           enum pipe pipe)
1641 {
1642         int cdclk = cdclk_state->cdclk;
1643         int vco = cdclk_state->vco;
1644         u32 val, divider;
1645         int ret;
1646
1647         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1648                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1649                                 SKL_CDCLK_READY_FOR_CHANGE,
1650                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1651         if (ret) {
1652                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1653                           ret);
1654                 return;
1655         }
1656
1657         /* cdclk = vco / 2 / div{1,2} */
1658         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1659         default:
1660                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1661                 WARN_ON(vco != 0);
1662                 /* fall through */
1663         case 2:
1664                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1665                 break;
1666         case 4:
1667                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1668                 break;
1669         }
1670
1671         if (dev_priv->cdclk.hw.vco != 0 &&
1672             dev_priv->cdclk.hw.vco != vco)
1673                 cnl_cdclk_pll_disable(dev_priv);
1674
1675         if (dev_priv->cdclk.hw.vco != vco)
1676                 cnl_cdclk_pll_enable(dev_priv, vco);
1677
1678         val = divider | skl_cdclk_decimal(cdclk);
1679         if (pipe == INVALID_PIPE)
1680                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1681         else
1682                 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1683         I915_WRITE(CDCLK_CTL, val);
1684
1685         if (pipe != INVALID_PIPE)
1686                 intel_wait_for_vblank(dev_priv, pipe);
1687
1688         /* inform PCU of the change */
1689         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1690                                 cdclk_state->voltage_level);
1691
1692         intel_update_cdclk(dev_priv);
1693
1694         /*
1695          * Can't read out the voltage level :(
1696          * Let's just assume everything is as expected.
1697          */
1698         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1699 }
1700
1701 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1702 {
1703         int ratio;
1704
1705         if (cdclk == dev_priv->cdclk.hw.bypass)
1706                 return 0;
1707
1708         switch (cdclk) {
1709         default:
1710                 MISSING_CASE(cdclk);
1711                 /* fall through */
1712         case 168000:
1713         case 336000:
1714                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1715                 break;
1716         case 528000:
1717                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1718                 break;
1719         }
1720
1721         return dev_priv->cdclk.hw.ref * ratio;
1722 }
1723
1724 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1725 {
1726         u32 cdctl, expected;
1727
1728         intel_update_cdclk(dev_priv);
1729         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1730
1731         if (dev_priv->cdclk.hw.vco == 0 ||
1732             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1733                 goto sanitize;
1734
1735         /* DPLL okay; verify the cdclock
1736          *
1737          * Some BIOS versions leave an incorrect decimal frequency value and
1738          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1739          * so sanitize this register.
1740          */
1741         cdctl = I915_READ(CDCLK_CTL);
1742         /*
1743          * Let's ignore the pipe field, since BIOS could have configured the
1744          * dividers both synching to an active pipe, or asynchronously
1745          * (PIPE_NONE).
1746          */
1747         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1748
1749         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1750                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1751
1752         if (cdctl == expected)
1753                 /* All well; nothing to sanitize */
1754                 return;
1755
1756 sanitize:
1757         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1758
1759         /* force cdclk programming */
1760         dev_priv->cdclk.hw.cdclk = 0;
1761
1762         /* force full PLL disable + enable */
1763         dev_priv->cdclk.hw.vco = -1;
1764 }
1765
1766 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1767 {
1768         int ranges_24[] = { 312000, 552000, 648000 };
1769         int ranges_19_38[] = { 307200, 556800, 652800 };
1770         int *ranges;
1771
1772         switch (ref) {
1773         default:
1774                 MISSING_CASE(ref);
1775                 /* fall through */
1776         case 24000:
1777                 ranges = ranges_24;
1778                 break;
1779         case 19200:
1780         case 38400:
1781                 ranges = ranges_19_38;
1782                 break;
1783         }
1784
1785         if (min_cdclk > ranges[1])
1786                 return ranges[2];
1787         else if (min_cdclk > ranges[0])
1788                 return ranges[1];
1789         else
1790                 return ranges[0];
1791 }
1792
1793 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1794 {
1795         int ratio;
1796
1797         if (cdclk == dev_priv->cdclk.hw.bypass)
1798                 return 0;
1799
1800         switch (cdclk) {
1801         default:
1802                 MISSING_CASE(cdclk);
1803                 /* fall through */
1804         case 307200:
1805         case 556800:
1806         case 652800:
1807                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1808                         dev_priv->cdclk.hw.ref != 38400);
1809                 break;
1810         case 312000:
1811         case 552000:
1812         case 648000:
1813                 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1814         }
1815
1816         ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1817
1818         return dev_priv->cdclk.hw.ref * ratio;
1819 }
1820
1821 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1822                           const struct intel_cdclk_state *cdclk_state,
1823                           enum pipe pipe)
1824 {
1825         unsigned int cdclk = cdclk_state->cdclk;
1826         unsigned int vco = cdclk_state->vco;
1827         int ret;
1828
1829         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1830                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1831                                 SKL_CDCLK_READY_FOR_CHANGE,
1832                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1833         if (ret) {
1834                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1835                           ret);
1836                 return;
1837         }
1838
1839         if (dev_priv->cdclk.hw.vco != 0 &&
1840             dev_priv->cdclk.hw.vco != vco)
1841                 cnl_cdclk_pll_disable(dev_priv);
1842
1843         if (dev_priv->cdclk.hw.vco != vco)
1844                 cnl_cdclk_pll_enable(dev_priv, vco);
1845
1846         /*
1847          * On ICL CD2X_DIV can only be 1, so we'll never end up changing the
1848          * divider here synchronized to a pipe while CDCLK is on, nor will we
1849          * need the corresponding vblank wait.
1850          */
1851         I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1852                               skl_cdclk_decimal(cdclk));
1853
1854         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1855                                 cdclk_state->voltage_level);
1856
1857         intel_update_cdclk(dev_priv);
1858
1859         /*
1860          * Can't read out the voltage level :(
1861          * Let's just assume everything is as expected.
1862          */
1863         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1864 }
1865
1866 static u8 icl_calc_voltage_level(int cdclk)
1867 {
1868         switch (cdclk) {
1869         case 50000:
1870         case 307200:
1871         case 312000:
1872                 return 0;
1873         case 556800:
1874         case 552000:
1875                 return 1;
1876         default:
1877                 MISSING_CASE(cdclk);
1878                 /* fall through */
1879         case 652800:
1880         case 648000:
1881                 return 2;
1882         }
1883 }
1884
1885 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1886                           struct intel_cdclk_state *cdclk_state)
1887 {
1888         u32 val;
1889
1890         cdclk_state->bypass = 50000;
1891
1892         val = I915_READ(SKL_DSSM);
1893         switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1894         default:
1895                 MISSING_CASE(val);
1896                 /* fall through */
1897         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1898                 cdclk_state->ref = 24000;
1899                 break;
1900         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1901                 cdclk_state->ref = 19200;
1902                 break;
1903         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1904                 cdclk_state->ref = 38400;
1905                 break;
1906         }
1907
1908         val = I915_READ(BXT_DE_PLL_ENABLE);
1909         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1910             (val & BXT_DE_PLL_LOCK) == 0) {
1911                 /*
1912                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1913                  * setting it to zero is a way to signal that.
1914                  */
1915                 cdclk_state->vco = 0;
1916                 cdclk_state->cdclk = cdclk_state->bypass;
1917                 goto out;
1918         }
1919
1920         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1921
1922         val = I915_READ(CDCLK_CTL);
1923         WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1924
1925         cdclk_state->cdclk = cdclk_state->vco / 2;
1926
1927 out:
1928         /*
1929          * Can't read this out :( Let's assume it's
1930          * at least what the CDCLK frequency requires.
1931          */
1932         cdclk_state->voltage_level =
1933                 icl_calc_voltage_level(cdclk_state->cdclk);
1934 }
1935
1936 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
1937 {
1938         struct intel_cdclk_state sanitized_state;
1939         u32 val;
1940
1941         /* This sets dev_priv->cdclk.hw. */
1942         intel_update_cdclk(dev_priv);
1943         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1944
1945         /* This means CDCLK disabled. */
1946         if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1947                 goto sanitize;
1948
1949         val = I915_READ(CDCLK_CTL);
1950
1951         if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1952                 goto sanitize;
1953
1954         if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1955             skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1956                 goto sanitize;
1957
1958         return;
1959
1960 sanitize:
1961         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1962
1963         sanitized_state.ref = dev_priv->cdclk.hw.ref;
1964         sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1965         sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1966                                                      sanitized_state.cdclk);
1967         sanitized_state.voltage_level =
1968                                 icl_calc_voltage_level(sanitized_state.cdclk);
1969
1970         icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
1971 }
1972
1973 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
1974 {
1975         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1976
1977         cdclk_state.cdclk = cdclk_state.bypass;
1978         cdclk_state.vco = 0;
1979         cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
1980
1981         icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1982 }
1983
1984 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1985 {
1986         struct intel_cdclk_state cdclk_state;
1987
1988         cnl_sanitize_cdclk(dev_priv);
1989
1990         if (dev_priv->cdclk.hw.cdclk != 0 &&
1991             dev_priv->cdclk.hw.vco != 0)
1992                 return;
1993
1994         cdclk_state = dev_priv->cdclk.hw;
1995
1996         cdclk_state.cdclk = cnl_calc_cdclk(0);
1997         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1998         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1999
2000         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
2001 }
2002
2003 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2004 {
2005         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2006
2007         cdclk_state.cdclk = cdclk_state.bypass;
2008         cdclk_state.vco = 0;
2009         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2010
2011         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
2012 }
2013
2014 /**
2015  * intel_cdclk_init - Initialize CDCLK
2016  * @i915: i915 device
2017  *
2018  * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
2019  * sanitizing the state of the hardware if needed. This is generally done only
2020  * during the display core initialization sequence, after which the DMC will
2021  * take care of turning CDCLK off/on as needed.
2022  */
2023 void intel_cdclk_init(struct drm_i915_private *i915)
2024 {
2025         if (INTEL_GEN(i915) >= 11)
2026                 icl_init_cdclk(i915);
2027         else if (IS_CANNONLAKE(i915))
2028                 cnl_init_cdclk(i915);
2029         else if (IS_GEN9_BC(i915))
2030                 skl_init_cdclk(i915);
2031         else if (IS_GEN9_LP(i915))
2032                 bxt_init_cdclk(i915);
2033 }
2034
2035 /**
2036  * intel_cdclk_uninit - Uninitialize CDCLK
2037  * @i915: i915 device
2038  *
2039  * Uninitialize CDCLK. This is done only during the display core
2040  * uninitialization sequence.
2041  */
2042 void intel_cdclk_uninit(struct drm_i915_private *i915)
2043 {
2044         if (INTEL_GEN(i915) >= 11)
2045                 icl_uninit_cdclk(i915);
2046         else if (IS_CANNONLAKE(i915))
2047                 cnl_uninit_cdclk(i915);
2048         else if (IS_GEN9_BC(i915))
2049                 skl_uninit_cdclk(i915);
2050         else if (IS_GEN9_LP(i915))
2051                 bxt_uninit_cdclk(i915);
2052 }
2053
2054 /**
2055  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2056  * @a: first CDCLK state
2057  * @b: second CDCLK state
2058  *
2059  * Returns:
2060  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2061  */
2062 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2063                                const struct intel_cdclk_state *b)
2064 {
2065         return a->cdclk != b->cdclk ||
2066                 a->vco != b->vco ||
2067                 a->ref != b->ref;
2068 }
2069
2070 /**
2071  * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
2072  * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
2073  * @a: first CDCLK state
2074  * @b: second CDCLK state
2075  *
2076  * Returns:
2077  * True if the CDCLK states require just a cd2x divider update, false if not.
2078  */
2079 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
2080                                    const struct intel_cdclk_state *a,
2081                                    const struct intel_cdclk_state *b)
2082 {
2083         /* Older hw doesn't have the capability */
2084         if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
2085                 return false;
2086
2087         return a->cdclk != b->cdclk &&
2088                 a->vco == b->vco &&
2089                 a->ref == b->ref;
2090 }
2091
2092 /**
2093  * intel_cdclk_changed - Determine if two CDCLK states are different
2094  * @a: first CDCLK state
2095  * @b: second CDCLK state
2096  *
2097  * Returns:
2098  * True if the CDCLK states don't match, false if they do.
2099  */
2100 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2101                          const struct intel_cdclk_state *b)
2102 {
2103         return intel_cdclk_needs_modeset(a, b) ||
2104                 a->voltage_level != b->voltage_level;
2105 }
2106
2107 /**
2108  * intel_cdclk_swap_state - make atomic CDCLK configuration effective
2109  * @state: atomic state
2110  *
2111  * This is the CDCLK version of drm_atomic_helper_swap_state() since the
2112  * helper does not handle driver-specific global state.
2113  *
2114  * Similarly to the atomic helpers this function does a complete swap,
2115  * i.e. it also puts the old state into @state. This is used by the commit
2116  * code to determine how CDCLK has changed (for instance did it increase or
2117  * decrease).
2118  */
2119 void intel_cdclk_swap_state(struct intel_atomic_state *state)
2120 {
2121         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2122
2123         swap(state->cdclk.logical, dev_priv->cdclk.logical);
2124         swap(state->cdclk.actual, dev_priv->cdclk.actual);
2125 }
2126
2127 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2128                             const char *context)
2129 {
2130         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2131                          context, cdclk_state->cdclk, cdclk_state->vco,
2132                          cdclk_state->ref, cdclk_state->bypass,
2133                          cdclk_state->voltage_level);
2134 }
2135
2136 /**
2137  * intel_set_cdclk - Push the CDCLK state to the hardware
2138  * @dev_priv: i915 device
2139  * @cdclk_state: new CDCLK state
2140  * @pipe: pipe with which to synchronize the update
2141  *
2142  * Program the hardware based on the passed in CDCLK state,
2143  * if necessary.
2144  */
2145 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2146                             const struct intel_cdclk_state *cdclk_state,
2147                             enum pipe pipe)
2148 {
2149         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2150                 return;
2151
2152         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2153                 return;
2154
2155         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2156
2157         dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
2158
2159         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2160                  "cdclk state doesn't match!\n")) {
2161                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2162                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2163         }
2164 }
2165
2166 /**
2167  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2168  * @dev_priv: i915 device
2169  * @old_state: old CDCLK state
2170  * @new_state: new CDCLK state
2171  * @pipe: pipe with which to synchronize the update
2172  *
2173  * Program the hardware before updating the HW plane state based on the passed
2174  * in CDCLK state, if necessary.
2175  */
2176 void
2177 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
2178                                  const struct intel_cdclk_state *old_state,
2179                                  const struct intel_cdclk_state *new_state,
2180                                  enum pipe pipe)
2181 {
2182         if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
2183                 intel_set_cdclk(dev_priv, new_state, pipe);
2184 }
2185
2186 /**
2187  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2188  * @dev_priv: i915 device
2189  * @old_state: old CDCLK state
2190  * @new_state: new CDCLK state
2191  * @pipe: pipe with which to synchronize the update
2192  *
2193  * Program the hardware after updating the HW plane state based on the passed
2194  * in CDCLK state, if necessary.
2195  */
2196 void
2197 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
2198                                   const struct intel_cdclk_state *old_state,
2199                                   const struct intel_cdclk_state *new_state,
2200                                   enum pipe pipe)
2201 {
2202         if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
2203                 intel_set_cdclk(dev_priv, new_state, pipe);
2204 }
2205
2206 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2207                                      int pixel_rate)
2208 {
2209         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2210                 return DIV_ROUND_UP(pixel_rate, 2);
2211         else if (IS_GEN(dev_priv, 9) ||
2212                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2213                 return pixel_rate;
2214         else if (IS_CHERRYVIEW(dev_priv))
2215                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2216         else
2217                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2218 }
2219
2220 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2221 {
2222         struct drm_i915_private *dev_priv =
2223                 to_i915(crtc_state->base.crtc->dev);
2224         int min_cdclk;
2225
2226         if (!crtc_state->base.enable)
2227                 return 0;
2228
2229         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2230
2231         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2232         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2233                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2234
2235         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2236          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2237          * there may be audio corruption or screen corruption." This cdclk
2238          * restriction for GLK is 316.8 MHz.
2239          */
2240         if (intel_crtc_has_dp_encoder(crtc_state) &&
2241             crtc_state->has_audio &&
2242             crtc_state->port_clock >= 540000 &&
2243             crtc_state->lane_count == 4) {
2244                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2245                         /* Display WA #1145: glk,cnl */
2246                         min_cdclk = max(316800, min_cdclk);
2247                 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2248                         /* Display WA #1144: skl,bxt */
2249                         min_cdclk = max(432000, min_cdclk);
2250                 }
2251         }
2252
2253         /*
2254          * According to BSpec, "The CD clock frequency must be at least twice
2255          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2256          */
2257         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2258                 min_cdclk = max(2 * 96000, min_cdclk);
2259
2260         /*
2261          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2262          * than 320000KHz.
2263          */
2264         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2265             IS_VALLEYVIEW(dev_priv))
2266                 min_cdclk = max(320000, min_cdclk);
2267
2268         /*
2269          * On Geminilake once the CDCLK gets as low as 79200
2270          * picture gets unstable, despite that values are
2271          * correct for DSI PLL and DE PLL.
2272          */
2273         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2274             IS_GEMINILAKE(dev_priv))
2275                 min_cdclk = max(158400, min_cdclk);
2276
2277         if (min_cdclk > dev_priv->max_cdclk_freq) {
2278                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2279                               min_cdclk, dev_priv->max_cdclk_freq);
2280                 return -EINVAL;
2281         }
2282
2283         return min_cdclk;
2284 }
2285
2286 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
2287 {
2288         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2289         struct drm_i915_private *dev_priv = to_i915(state->dev);
2290         struct intel_crtc *crtc;
2291         struct intel_crtc_state *crtc_state;
2292         int min_cdclk, i;
2293         enum pipe pipe;
2294
2295         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2296                sizeof(intel_state->min_cdclk));
2297
2298         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2299                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2300                 if (min_cdclk < 0)
2301                         return min_cdclk;
2302
2303                 intel_state->min_cdclk[i] = min_cdclk;
2304         }
2305
2306         min_cdclk = intel_state->cdclk.force_min_cdclk;
2307         for_each_pipe(dev_priv, pipe)
2308                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
2309
2310         return min_cdclk;
2311 }
2312
2313 /*
2314  * Note that this functions assumes that 0 is
2315  * the lowest voltage value, and higher values
2316  * correspond to increasingly higher voltages.
2317  *
2318  * Should that relationship no longer hold on
2319  * future platforms this code will need to be
2320  * adjusted.
2321  */
2322 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2323 {
2324         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2325         struct intel_crtc *crtc;
2326         struct intel_crtc_state *crtc_state;
2327         u8 min_voltage_level;
2328         int i;
2329         enum pipe pipe;
2330
2331         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2332                sizeof(state->min_voltage_level));
2333
2334         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2335                 if (crtc_state->base.enable)
2336                         state->min_voltage_level[i] =
2337                                 crtc_state->min_voltage_level;
2338                 else
2339                         state->min_voltage_level[i] = 0;
2340         }
2341
2342         min_voltage_level = 0;
2343         for_each_pipe(dev_priv, pipe)
2344                 min_voltage_level = max(state->min_voltage_level[pipe],
2345                                         min_voltage_level);
2346
2347         return min_voltage_level;
2348 }
2349
2350 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2351 {
2352         struct drm_i915_private *dev_priv = to_i915(state->dev);
2353         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2354         int min_cdclk, cdclk;
2355
2356         min_cdclk = intel_compute_min_cdclk(state);
2357         if (min_cdclk < 0)
2358                 return min_cdclk;
2359
2360         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2361
2362         intel_state->cdclk.logical.cdclk = cdclk;
2363         intel_state->cdclk.logical.voltage_level =
2364                 vlv_calc_voltage_level(dev_priv, cdclk);
2365
2366         if (!intel_state->active_crtcs) {
2367                 cdclk = vlv_calc_cdclk(dev_priv,
2368                                        intel_state->cdclk.force_min_cdclk);
2369
2370                 intel_state->cdclk.actual.cdclk = cdclk;
2371                 intel_state->cdclk.actual.voltage_level =
2372                         vlv_calc_voltage_level(dev_priv, cdclk);
2373         } else {
2374                 intel_state->cdclk.actual =
2375                         intel_state->cdclk.logical;
2376         }
2377
2378         return 0;
2379 }
2380
2381 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2382 {
2383         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2384         int min_cdclk, cdclk;
2385
2386         min_cdclk = intel_compute_min_cdclk(state);
2387         if (min_cdclk < 0)
2388                 return min_cdclk;
2389
2390         /*
2391          * FIXME should also account for plane ratio
2392          * once 64bpp pixel formats are supported.
2393          */
2394         cdclk = bdw_calc_cdclk(min_cdclk);
2395
2396         intel_state->cdclk.logical.cdclk = cdclk;
2397         intel_state->cdclk.logical.voltage_level =
2398                 bdw_calc_voltage_level(cdclk);
2399
2400         if (!intel_state->active_crtcs) {
2401                 cdclk = bdw_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2402
2403                 intel_state->cdclk.actual.cdclk = cdclk;
2404                 intel_state->cdclk.actual.voltage_level =
2405                         bdw_calc_voltage_level(cdclk);
2406         } else {
2407                 intel_state->cdclk.actual =
2408                         intel_state->cdclk.logical;
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2415 {
2416         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2417         struct intel_crtc *crtc;
2418         struct intel_crtc_state *crtc_state;
2419         int vco, i;
2420
2421         vco = intel_state->cdclk.logical.vco;
2422         if (!vco)
2423                 vco = dev_priv->skl_preferred_vco_freq;
2424
2425         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2426                 if (!crtc_state->base.enable)
2427                         continue;
2428
2429                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2430                         continue;
2431
2432                 /*
2433                  * DPLL0 VCO may need to be adjusted to get the correct
2434                  * clock for eDP. This will affect cdclk as well.
2435                  */
2436                 switch (crtc_state->port_clock / 2) {
2437                 case 108000:
2438                 case 216000:
2439                         vco = 8640000;
2440                         break;
2441                 default:
2442                         vco = 8100000;
2443                         break;
2444                 }
2445         }
2446
2447         return vco;
2448 }
2449
2450 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2451 {
2452         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2453         int min_cdclk, cdclk, vco;
2454
2455         min_cdclk = intel_compute_min_cdclk(state);
2456         if (min_cdclk < 0)
2457                 return min_cdclk;
2458
2459         vco = skl_dpll0_vco(intel_state);
2460
2461         /*
2462          * FIXME should also account for plane ratio
2463          * once 64bpp pixel formats are supported.
2464          */
2465         cdclk = skl_calc_cdclk(min_cdclk, vco);
2466
2467         intel_state->cdclk.logical.vco = vco;
2468         intel_state->cdclk.logical.cdclk = cdclk;
2469         intel_state->cdclk.logical.voltage_level =
2470                 skl_calc_voltage_level(cdclk);
2471
2472         if (!intel_state->active_crtcs) {
2473                 cdclk = skl_calc_cdclk(intel_state->cdclk.force_min_cdclk, vco);
2474
2475                 intel_state->cdclk.actual.vco = vco;
2476                 intel_state->cdclk.actual.cdclk = cdclk;
2477                 intel_state->cdclk.actual.voltage_level =
2478                         skl_calc_voltage_level(cdclk);
2479         } else {
2480                 intel_state->cdclk.actual =
2481                         intel_state->cdclk.logical;
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2488 {
2489         struct drm_i915_private *dev_priv = to_i915(state->dev);
2490         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2491         int min_cdclk, cdclk, vco;
2492
2493         min_cdclk = intel_compute_min_cdclk(state);
2494         if (min_cdclk < 0)
2495                 return min_cdclk;
2496
2497         if (IS_GEMINILAKE(dev_priv)) {
2498                 cdclk = glk_calc_cdclk(min_cdclk);
2499                 vco = glk_de_pll_vco(dev_priv, cdclk);
2500         } else {
2501                 cdclk = bxt_calc_cdclk(min_cdclk);
2502                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2503         }
2504
2505         intel_state->cdclk.logical.vco = vco;
2506         intel_state->cdclk.logical.cdclk = cdclk;
2507         intel_state->cdclk.logical.voltage_level =
2508                 bxt_calc_voltage_level(cdclk);
2509
2510         if (!intel_state->active_crtcs) {
2511                 if (IS_GEMINILAKE(dev_priv)) {
2512                         cdclk = glk_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2513                         vco = glk_de_pll_vco(dev_priv, cdclk);
2514                 } else {
2515                         cdclk = bxt_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2516                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2517                 }
2518
2519                 intel_state->cdclk.actual.vco = vco;
2520                 intel_state->cdclk.actual.cdclk = cdclk;
2521                 intel_state->cdclk.actual.voltage_level =
2522                         bxt_calc_voltage_level(cdclk);
2523         } else {
2524                 intel_state->cdclk.actual =
2525                         intel_state->cdclk.logical;
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2532 {
2533         struct drm_i915_private *dev_priv = to_i915(state->dev);
2534         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2535         int min_cdclk, cdclk, vco;
2536
2537         min_cdclk = intel_compute_min_cdclk(state);
2538         if (min_cdclk < 0)
2539                 return min_cdclk;
2540
2541         cdclk = cnl_calc_cdclk(min_cdclk);
2542         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2543
2544         intel_state->cdclk.logical.vco = vco;
2545         intel_state->cdclk.logical.cdclk = cdclk;
2546         intel_state->cdclk.logical.voltage_level =
2547                 max(cnl_calc_voltage_level(cdclk),
2548                     cnl_compute_min_voltage_level(intel_state));
2549
2550         if (!intel_state->active_crtcs) {
2551                 cdclk = cnl_calc_cdclk(intel_state->cdclk.force_min_cdclk);
2552                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2553
2554                 intel_state->cdclk.actual.vco = vco;
2555                 intel_state->cdclk.actual.cdclk = cdclk;
2556                 intel_state->cdclk.actual.voltage_level =
2557                         cnl_calc_voltage_level(cdclk);
2558         } else {
2559                 intel_state->cdclk.actual =
2560                         intel_state->cdclk.logical;
2561         }
2562
2563         return 0;
2564 }
2565
2566 static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2567 {
2568         struct drm_i915_private *dev_priv = to_i915(state->dev);
2569         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2570         unsigned int ref = intel_state->cdclk.logical.ref;
2571         int min_cdclk, cdclk, vco;
2572
2573         min_cdclk = intel_compute_min_cdclk(state);
2574         if (min_cdclk < 0)
2575                 return min_cdclk;
2576
2577         cdclk = icl_calc_cdclk(min_cdclk, ref);
2578         vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2579
2580         intel_state->cdclk.logical.vco = vco;
2581         intel_state->cdclk.logical.cdclk = cdclk;
2582         intel_state->cdclk.logical.voltage_level =
2583                 max(icl_calc_voltage_level(cdclk),
2584                     cnl_compute_min_voltage_level(intel_state));
2585
2586         if (!intel_state->active_crtcs) {
2587                 cdclk = icl_calc_cdclk(intel_state->cdclk.force_min_cdclk, ref);
2588                 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2589
2590                 intel_state->cdclk.actual.vco = vco;
2591                 intel_state->cdclk.actual.cdclk = cdclk;
2592                 intel_state->cdclk.actual.voltage_level =
2593                         icl_calc_voltage_level(cdclk);
2594         } else {
2595                 intel_state->cdclk.actual = intel_state->cdclk.logical;
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2602 {
2603         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2604
2605         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2606                 return 2 * max_cdclk_freq;
2607         else if (IS_GEN(dev_priv, 9) ||
2608                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2609                 return max_cdclk_freq;
2610         else if (IS_CHERRYVIEW(dev_priv))
2611                 return max_cdclk_freq*95/100;
2612         else if (INTEL_GEN(dev_priv) < 4)
2613                 return 2*max_cdclk_freq*90/100;
2614         else
2615                 return max_cdclk_freq*90/100;
2616 }
2617
2618 /**
2619  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2620  * @dev_priv: i915 device
2621  *
2622  * Determine the maximum CDCLK frequency the platform supports, and also
2623  * derive the maximum dot clock frequency the maximum CDCLK frequency
2624  * allows.
2625  */
2626 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2627 {
2628         if (INTEL_GEN(dev_priv) >= 11) {
2629                 if (dev_priv->cdclk.hw.ref == 24000)
2630                         dev_priv->max_cdclk_freq = 648000;
2631                 else
2632                         dev_priv->max_cdclk_freq = 652800;
2633         } else if (IS_CANNONLAKE(dev_priv)) {
2634                 dev_priv->max_cdclk_freq = 528000;
2635         } else if (IS_GEN9_BC(dev_priv)) {
2636                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2637                 int max_cdclk, vco;
2638
2639                 vco = dev_priv->skl_preferred_vco_freq;
2640                 WARN_ON(vco != 8100000 && vco != 8640000);
2641
2642                 /*
2643                  * Use the lower (vco 8640) cdclk values as a
2644                  * first guess. skl_calc_cdclk() will correct it
2645                  * if the preferred vco is 8100 instead.
2646                  */
2647                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2648                         max_cdclk = 617143;
2649                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2650                         max_cdclk = 540000;
2651                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2652                         max_cdclk = 432000;
2653                 else
2654                         max_cdclk = 308571;
2655
2656                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2657         } else if (IS_GEMINILAKE(dev_priv)) {
2658                 dev_priv->max_cdclk_freq = 316800;
2659         } else if (IS_BROXTON(dev_priv)) {
2660                 dev_priv->max_cdclk_freq = 624000;
2661         } else if (IS_BROADWELL(dev_priv))  {
2662                 /*
2663                  * FIXME with extra cooling we can allow
2664                  * 540 MHz for ULX and 675 Mhz for ULT.
2665                  * How can we know if extra cooling is
2666                  * available? PCI ID, VTB, something else?
2667                  */
2668                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2669                         dev_priv->max_cdclk_freq = 450000;
2670                 else if (IS_BDW_ULX(dev_priv))
2671                         dev_priv->max_cdclk_freq = 450000;
2672                 else if (IS_BDW_ULT(dev_priv))
2673                         dev_priv->max_cdclk_freq = 540000;
2674                 else
2675                         dev_priv->max_cdclk_freq = 675000;
2676         } else if (IS_CHERRYVIEW(dev_priv)) {
2677                 dev_priv->max_cdclk_freq = 320000;
2678         } else if (IS_VALLEYVIEW(dev_priv)) {
2679                 dev_priv->max_cdclk_freq = 400000;
2680         } else {
2681                 /* otherwise assume cdclk is fixed */
2682                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2683         }
2684
2685         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2686
2687         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2688                          dev_priv->max_cdclk_freq);
2689
2690         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2691                          dev_priv->max_dotclk_freq);
2692 }
2693
2694 /**
2695  * intel_update_cdclk - Determine the current CDCLK frequency
2696  * @dev_priv: i915 device
2697  *
2698  * Determine the current CDCLK frequency.
2699  */
2700 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2701 {
2702         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2703
2704         /*
2705          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2706          * Programmng [sic] note: bit[9:2] should be programmed to the number
2707          * of cdclk that generates 4MHz reference clock freq which is used to
2708          * generate GMBus clock. This will vary with the cdclk freq.
2709          */
2710         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2711                 I915_WRITE(GMBUSFREQ_VLV,
2712                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2713 }
2714
2715 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2716 {
2717         u32 rawclk;
2718         int divider, fraction;
2719
2720         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2721                 /* 24 MHz */
2722                 divider = 24000;
2723                 fraction = 0;
2724         } else {
2725                 /* 19.2 MHz */
2726                 divider = 19000;
2727                 fraction = 200;
2728         }
2729
2730         rawclk = CNP_RAWCLK_DIV(divider / 1000);
2731         if (fraction) {
2732                 int numerator = 1;
2733
2734                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2735                                                            fraction) - 1);
2736                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2737                         rawclk |= ICP_RAWCLK_NUM(numerator);
2738         }
2739
2740         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2741         return divider + fraction;
2742 }
2743
2744 static int pch_rawclk(struct drm_i915_private *dev_priv)
2745 {
2746         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2747 }
2748
2749 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2750 {
2751         /* RAWCLK_FREQ_VLV register updated from power well code */
2752         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2753                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2754 }
2755
2756 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2757 {
2758         u32 clkcfg;
2759
2760         /* hrawclock is 1/4 the FSB frequency */
2761         clkcfg = I915_READ(CLKCFG);
2762         switch (clkcfg & CLKCFG_FSB_MASK) {
2763         case CLKCFG_FSB_400:
2764                 return 100000;
2765         case CLKCFG_FSB_533:
2766                 return 133333;
2767         case CLKCFG_FSB_667:
2768                 return 166667;
2769         case CLKCFG_FSB_800:
2770                 return 200000;
2771         case CLKCFG_FSB_1067:
2772         case CLKCFG_FSB_1067_ALT:
2773                 return 266667;
2774         case CLKCFG_FSB_1333:
2775         case CLKCFG_FSB_1333_ALT:
2776                 return 333333;
2777         default:
2778                 return 133333;
2779         }
2780 }
2781
2782 /**
2783  * intel_update_rawclk - Determine the current RAWCLK frequency
2784  * @dev_priv: i915 device
2785  *
2786  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2787  * frequency clock so this needs to done only once.
2788  */
2789 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2790 {
2791         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2792                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2793         else if (HAS_PCH_SPLIT(dev_priv))
2794                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2795         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2796                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2797         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2798                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2799         else
2800                 /* no rawclk on other platforms, or no need to know it */
2801                 return;
2802
2803         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2804 }
2805
2806 /**
2807  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2808  * @dev_priv: i915 device
2809  */
2810 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2811 {
2812         if (INTEL_GEN(dev_priv) >= 11) {
2813                 dev_priv->display.set_cdclk = icl_set_cdclk;
2814                 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2815         } else if (IS_CANNONLAKE(dev_priv)) {
2816                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2817                 dev_priv->display.modeset_calc_cdclk =
2818                         cnl_modeset_calc_cdclk;
2819         } else if (IS_GEN9_LP(dev_priv)) {
2820                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2821                 dev_priv->display.modeset_calc_cdclk =
2822                         bxt_modeset_calc_cdclk;
2823         } else if (IS_GEN9_BC(dev_priv)) {
2824                 dev_priv->display.set_cdclk = skl_set_cdclk;
2825                 dev_priv->display.modeset_calc_cdclk =
2826                         skl_modeset_calc_cdclk;
2827         } else if (IS_BROADWELL(dev_priv)) {
2828                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2829                 dev_priv->display.modeset_calc_cdclk =
2830                         bdw_modeset_calc_cdclk;
2831         } else if (IS_CHERRYVIEW(dev_priv)) {
2832                 dev_priv->display.set_cdclk = chv_set_cdclk;
2833                 dev_priv->display.modeset_calc_cdclk =
2834                         vlv_modeset_calc_cdclk;
2835         } else if (IS_VALLEYVIEW(dev_priv)) {
2836                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2837                 dev_priv->display.modeset_calc_cdclk =
2838                         vlv_modeset_calc_cdclk;
2839         }
2840
2841         if (INTEL_GEN(dev_priv) >= 11)
2842                 dev_priv->display.get_cdclk = icl_get_cdclk;
2843         else if (IS_CANNONLAKE(dev_priv))
2844                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2845         else if (IS_GEN9_LP(dev_priv))
2846                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2847         else if (IS_GEN9_BC(dev_priv))
2848                 dev_priv->display.get_cdclk = skl_get_cdclk;
2849         else if (IS_BROADWELL(dev_priv))
2850                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2851         else if (IS_HASWELL(dev_priv))
2852                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2853         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2854                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2855         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2856                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2857         else if (IS_GEN(dev_priv, 5))
2858                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2859         else if (IS_GM45(dev_priv))
2860                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2861         else if (IS_G45(dev_priv))
2862                 dev_priv->display.get_cdclk = g33_get_cdclk;
2863         else if (IS_I965GM(dev_priv))
2864                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2865         else if (IS_I965G(dev_priv))
2866                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2867         else if (IS_PINEVIEW(dev_priv))
2868                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2869         else if (IS_G33(dev_priv))
2870                 dev_priv->display.get_cdclk = g33_get_cdclk;
2871         else if (IS_I945GM(dev_priv))
2872                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2873         else if (IS_I945G(dev_priv))
2874                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2875         else if (IS_I915GM(dev_priv))
2876                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2877         else if (IS_I915G(dev_priv))
2878                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2879         else if (IS_I865G(dev_priv))
2880                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2881         else if (IS_I85X(dev_priv))
2882                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2883         else if (IS_I845G(dev_priv))
2884                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2885         else { /* 830 */
2886                 WARN(!IS_I830(dev_priv),
2887                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2888                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2889         }
2890 }