drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 421 {
 422         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 423                 333333 : 320000;
 424
 425         /*
 426          * We seem to get an unstable or solid color picture at 200MHz.
 427          * Not sure what's wrong. For now use 200MHz only when all pipes
 428          * are off.
 429          */
 430         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 431                 return 400000;
 432         else if (min_cdclk > 266667)
 433                 return freq_320;
 434         else if (min_cdclk > 0)
 435                 return 266667;
 436         else
 437                 return 200000;
 438 }
 439
 440 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 441 {
 442         if (IS_VALLEYVIEW(dev_priv)) {
 443                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 444                         return 2;
 445                 else if (cdclk >= 266667)
 446                         return 1;
 447                 else
 448                         return 0;
 449         } else {
 450                 /*
 451                  * Specs are full of misinformation, but testing on actual
 452                  * hardware has shown that we just need to write the desired
 453                  * CCK divider into the Punit register.
 454                  */
 455                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 456         }
 457 }
 458
 459 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 460                           struct intel_cdclk_state *cdclk_state)
 461 {
 462         u32 val;
 463
 464         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 465         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 466                                                CCK_DISPLAY_CLOCK_CONTROL,
 467                                                cdclk_state->vco);
 468
 469         mutex_lock(&dev_priv->pcu_lock);
 470         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 471         mutex_unlock(&dev_priv->pcu_lock);
 472
 473         if (IS_VALLEYVIEW(dev_priv))
 474                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 475                         DSPFREQGUAR_SHIFT;
 476         else
 477                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 478                         DSPFREQGUAR_SHIFT_CHV;
 479 }
 480
 481 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 482 {
 483         unsigned int credits, default_credits;
 484
 485         if (IS_CHERRYVIEW(dev_priv))
 486                 default_credits = PFI_CREDIT(12);
 487         else
 488                 default_credits = PFI_CREDIT(8);
 489
 490         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 491                 /* CHV suggested value is 31 or 63 */
 492                 if (IS_CHERRYVIEW(dev_priv))
 493                         credits = PFI_CREDIT_63;
 494                 else
 495                         credits = PFI_CREDIT(15);
 496         } else {
 497                 credits = default_credits;
 498         }
 499
 500         /*
 501          * WA - write default credits before re-programming
 502          * FIXME: should we also set the resend bit here?
 503          */
 504         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 505                    default_credits);
 506
 507         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 508                    credits | PFI_CREDIT_RESEND);
 509
 510         /*
 511          * FIXME is this guaranteed to clear
 512          * immediately or should we poll for it?
 513          */
 514         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 515 }
 516
 517 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 518                           const struct intel_cdclk_state *cdclk_state)
 519 {
 520         int cdclk = cdclk_state->cdclk;
 521         u32 val, cmd = cdclk_state->voltage_level;
 522
 523         switch (cdclk) {
 524         case 400000:
 525         case 333333:
 526         case 320000:
 527         case 266667:
 528         case 200000:
 529                 break;
 530         default:
 531                 MISSING_CASE(cdclk);
 532                 return;
 533         }
 534
 535         /* There are cases where we can end up here with power domains
 536          * off and a CDCLK frequency other than the minimum, like when
 537          * issuing a modeset without actually changing any display after
 538          * a system suspend.  So grab the PIPE-A domain, which covers
 539          * the HW blocks needed for the following programming.
 540          */
 541         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 542
 543         mutex_lock(&dev_priv->pcu_lock);
 544         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 545         val &= ~DSPFREQGUAR_MASK;
 546         val |= (cmd << DSPFREQGUAR_SHIFT);
 547         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 548         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 549                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 550                      50)) {
 551                 DRM_ERROR("timed out waiting for CDclk change\n");
 552         }
 553         mutex_unlock(&dev_priv->pcu_lock);
 554
 555         mutex_lock(&dev_priv->sb_lock);
 556
 557         if (cdclk == 400000) {
 558                 u32 divider;
 559
 560                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 561                                             cdclk) - 1;
 562
 563                 /* adjust cdclk divider */
 564                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 565                 val &= ~CCK_FREQUENCY_VALUES;
 566                 val |= divider;
 567                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 568
 569                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 570                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 571                              50))
 572                         DRM_ERROR("timed out waiting for CDclk change\n");
 573         }
 574
 575         /* adjust self-refresh exit latency value */
 576         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 577         val &= ~0x7f;
 578
 579         /*
 580          * For high bandwidth configs, we set a higher latency in the bunit
 581          * so that the core display fetch happens in time to avoid underruns.
 582          */
 583         if (cdclk == 400000)
 584                 val |= 4500 / 250; /* 4.5 usec */
 585         else
 586                 val |= 3000 / 250; /* 3.0 usec */
 587         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 588
 589         mutex_unlock(&dev_priv->sb_lock);
 590
 591         intel_update_cdclk(dev_priv);
 592
 593         vlv_program_pfi_credits(dev_priv);
 594
 595         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 596 }
 597
 598 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 599                           const struct intel_cdclk_state *cdclk_state)
 600 {
 601         int cdclk = cdclk_state->cdclk;
 602         u32 val, cmd = cdclk_state->voltage_level;
 603
 604         switch (cdclk) {
 605         case 333333:
 606         case 320000:
 607         case 266667:
 608         case 200000:
 609                 break;
 610         default:
 611                 MISSING_CASE(cdclk);
 612                 return;
 613         }
 614
 615         /* There are cases where we can end up here with power domains
 616          * off and a CDCLK frequency other than the minimum, like when
 617          * issuing a modeset without actually changing any display after
 618          * a system suspend.  So grab the PIPE-A domain, which covers
 619          * the HW blocks needed for the following programming.
 620          */
 621         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 622
 623         mutex_lock(&dev_priv->pcu_lock);
 624         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 625         val &= ~DSPFREQGUAR_MASK_CHV;
 626         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 627         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 628         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 629                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 630                      50)) {
 631                 DRM_ERROR("timed out waiting for CDclk change\n");
 632         }
 633         mutex_unlock(&dev_priv->pcu_lock);
 634
 635         intel_update_cdclk(dev_priv);
 636
 637         vlv_program_pfi_credits(dev_priv);
 638
 639         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 640 }
 641
 642 static int bdw_calc_cdclk(int min_cdclk)
 643 {
 644         if (min_cdclk > 540000)
 645                 return 675000;
 646         else if (min_cdclk > 450000)
 647                 return 540000;
 648         else if (min_cdclk > 337500)
 649                 return 450000;
 650         else
 651                 return 337500;
 652 }
 653
 654 static u8 bdw_calc_voltage_level(int cdclk)
 655 {
 656         switch (cdclk) {
 657         default:
 658         case 337500:
 659                 return 2;
 660         case 450000:
 661                 return 0;
 662         case 540000:
 663                 return 1;
 664         case 675000:
 665                 return 3;
 666         }
 667 }
 668
 669 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 670                           struct intel_cdclk_state *cdclk_state)
 671 {
 672         uint32_t lcpll = I915_READ(LCPLL_CTL);
 673         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 674
 675         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 676                 cdclk_state->cdclk = 800000;
 677         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 678                 cdclk_state->cdclk = 450000;
 679         else if (freq == LCPLL_CLK_FREQ_450)
 680                 cdclk_state->cdclk = 450000;
 681         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 682                 cdclk_state->cdclk = 540000;
 683         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 684                 cdclk_state->cdclk = 337500;
 685         else
 686                 cdclk_state->cdclk = 675000;
 687
 688         /*
 689          * Can't read this out :( Let's assume it's
 690          * at least what the CDCLK frequency requires.
 691          */
 692         cdclk_state->voltage_level =
 693                 bdw_calc_voltage_level(cdclk_state->cdclk);
 694 }
 695
 696 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 697                           const struct intel_cdclk_state *cdclk_state)
 698 {
 699         int cdclk = cdclk_state->cdclk;
 700         uint32_t val;
 701         int ret;
 702
 703         if (WARN((I915_READ(LCPLL_CTL) &
 704                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 705                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 706                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 707                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 708                  "trying to change cdclk frequency with cdclk not enabled\n"))
 709                 return;
 710
 711         mutex_lock(&dev_priv->pcu_lock);
 712         ret = sandybridge_pcode_write(dev_priv,
 713                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 714         mutex_unlock(&dev_priv->pcu_lock);
 715         if (ret) {
 716                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 717                 return;
 718         }
 719
 720         val = I915_READ(LCPLL_CTL);
 721         val |= LCPLL_CD_SOURCE_FCLK;
 722         I915_WRITE(LCPLL_CTL, val);
 723
 724         /*
 725          * According to the spec, it should be enough to poll for this 1 us.
 726          * However, extensive testing shows that this can take longer.
 727          */
 728         if (wait_for_us(I915_READ(LCPLL_CTL) &
 729                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 730                 DRM_ERROR("Switching to FCLK failed\n");
 731
 732         val = I915_READ(LCPLL_CTL);
 733         val &= ~LCPLL_CLK_FREQ_MASK;
 734
 735         switch (cdclk) {
 736         default:
 737                 MISSING_CASE(cdclk);
 738                 /* fall through */
 739         case 337500:
 740                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 741                 break;
 742         case 450000:
 743                 val |= LCPLL_CLK_FREQ_450;
 744                 break;
 745         case 540000:
 746                 val |= LCPLL_CLK_FREQ_54O_BDW;
 747                 break;
 748         case 675000:
 749                 val |= LCPLL_CLK_FREQ_675_BDW;
 750                 break;
 751         }
 752
 753         I915_WRITE(LCPLL_CTL, val);
 754
 755         val = I915_READ(LCPLL_CTL);
 756         val &= ~LCPLL_CD_SOURCE_FCLK;
 757         I915_WRITE(LCPLL_CTL, val);
 758
 759         if (wait_for_us((I915_READ(LCPLL_CTL) &
 760                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 761                 DRM_ERROR("Switching back to LCPLL failed\n");
 762
 763         mutex_lock(&dev_priv->pcu_lock);
 764         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 765                                 cdclk_state->voltage_level);
 766         mutex_unlock(&dev_priv->pcu_lock);
 767
 768         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 769
 770         intel_update_cdclk(dev_priv);
 771 }
 772
 773 static int skl_calc_cdclk(int min_cdclk, int vco)
 774 {
 775         if (vco == 8640000) {
 776                 if (min_cdclk > 540000)
 777                         return 617143;
 778                 else if (min_cdclk > 432000)
 779                         return 540000;
 780                 else if (min_cdclk > 308571)
 781                         return 432000;
 782                 else
 783                         return 308571;
 784         } else {
 785                 if (min_cdclk > 540000)
 786                         return 675000;
 787                 else if (min_cdclk > 450000)
 788                         return 540000;
 789                 else if (min_cdclk > 337500)
 790                         return 450000;
 791                 else
 792                         return 337500;
 793         }
 794 }
 795
 796 static u8 skl_calc_voltage_level(int cdclk)
 797 {
 798         switch (cdclk) {
 799         default:
 800         case 308571:
 801         case 337500:
 802                 return 0;
 803         case 450000:
 804         case 432000:
 805                 return 1;
 806         case 540000:
 807                 return 2;
 808         case 617143:
 809         case 675000:
 810                 return 3;
 811         }
 812 }
 813
 814 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 815                              struct intel_cdclk_state *cdclk_state)
 816 {
 817         u32 val;
 818
 819         cdclk_state->ref = 24000;
 820         cdclk_state->vco = 0;
 821
 822         val = I915_READ(LCPLL1_CTL);
 823         if ((val & LCPLL_PLL_ENABLE) == 0)
 824                 return;
 825
 826         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 827                 return;
 828
 829         val = I915_READ(DPLL_CTRL1);
 830
 831         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 832                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 833                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 834                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 835                 return;
 836
 837         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 838         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 839         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 840         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 841         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 842                 cdclk_state->vco = 8100000;
 843                 break;
 844         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 845         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 846                 cdclk_state->vco = 8640000;
 847                 break;
 848         default:
 849                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 850                 break;
 851         }
 852 }
 853
 854 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 855                           struct intel_cdclk_state *cdclk_state)
 856 {
 857         u32 cdctl;
 858
 859         skl_dpll0_update(dev_priv, cdclk_state);
 860
 861         cdclk_state->cdclk = cdclk_state->ref;
 862
 863         if (cdclk_state->vco == 0)
 864                 goto out;
 865
 866         cdctl = I915_READ(CDCLK_CTL);
 867
 868         if (cdclk_state->vco == 8640000) {
 869                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 870                 case CDCLK_FREQ_450_432:
 871                         cdclk_state->cdclk = 432000;
 872                         break;
 873                 case CDCLK_FREQ_337_308:
 874                         cdclk_state->cdclk = 308571;
 875                         break;
 876                 case CDCLK_FREQ_540:
 877                         cdclk_state->cdclk = 540000;
 878                         break;
 879                 case CDCLK_FREQ_675_617:
 880                         cdclk_state->cdclk = 617143;
 881                         break;
 882                 default:
 883                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 884                         break;
 885                 }
 886         } else {
 887                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 888                 case CDCLK_FREQ_450_432:
 889                         cdclk_state->cdclk = 450000;
 890                         break;
 891                 case CDCLK_FREQ_337_308:
 892                         cdclk_state->cdclk = 337500;
 893                         break;
 894                 case CDCLK_FREQ_540:
 895                         cdclk_state->cdclk = 540000;
 896                         break;
 897                 case CDCLK_FREQ_675_617:
 898                         cdclk_state->cdclk = 675000;
 899                         break;
 900                 default:
 901                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 902                         break;
 903                 }
 904         }
 905
 906  out:
 907         /*
 908          * Can't read this out :( Let's assume it's
 909          * at least what the CDCLK frequency requires.
 910          */
 911         cdclk_state->voltage_level =
 912                 skl_calc_voltage_level(cdclk_state->cdclk);
 913 }
 914
 915 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 916 static int skl_cdclk_decimal(int cdclk)
 917 {
 918         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 919 }
 920
 921 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 922                                         int vco)
 923 {
 924         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 925
 926         dev_priv->skl_preferred_vco_freq = vco;
 927
 928         if (changed)
 929                 intel_update_max_cdclk(dev_priv);
 930 }
 931
 932 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 933 {
 934         u32 val;
 935
 936         WARN_ON(vco != 8100000 && vco != 8640000);
 937
 938         /*
 939          * We always enable DPLL0 with the lowest link rate possible, but still
 940          * taking into account the VCO required to operate the eDP panel at the
 941          * desired frequency. The usual DP link rates operate with a VCO of
 942          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 943          * The modeset code is responsible for the selection of the exact link
 944          * rate later on, with the constraint of choosing a frequency that
 945          * works with vco.
 946          */
 947         val = I915_READ(DPLL_CTRL1);
 948
 949         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 950                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 951         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 952         if (vco == 8640000)
 953                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 954                                             SKL_DPLL0);
 955         else
 956                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 957                                             SKL_DPLL0);
 958
 959         I915_WRITE(DPLL_CTRL1, val);
 960         POSTING_READ(DPLL_CTRL1);
 961
 962         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 963
 964         if (intel_wait_for_register(dev_priv,
 965                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 966                                     5))
 967                 DRM_ERROR("DPLL0 not locked\n");
 968
 969         dev_priv->cdclk.hw.vco = vco;
 970
 971         /* We'll want to keep using the current vco from now on. */
 972         skl_set_preferred_cdclk_vco(dev_priv, vco);
 973 }
 974
 975 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 976 {
 977         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 978         if (intel_wait_for_register(dev_priv,
 979                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 980                                    1))
 981                 DRM_ERROR("Couldn't disable DPLL0\n");
 982
 983         dev_priv->cdclk.hw.vco = 0;
 984 }
 985
 986 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 987                           const struct intel_cdclk_state *cdclk_state)
 988 {
 989         int cdclk = cdclk_state->cdclk;
 990         int vco = cdclk_state->vco;
 991         u32 freq_select, cdclk_ctl;
 992         int ret;
 993
 994         mutex_lock(&dev_priv->pcu_lock);
 995         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 996                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 997                                 SKL_CDCLK_READY_FOR_CHANGE,
 998                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 999         mutex_unlock(&dev_priv->pcu_lock);
1000         if (ret) {
1001                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1002                           ret);
1003                 return;
1004         }
1005
1006         /* Choose frequency for this cdclk */
1007         switch (cdclk) {
1008         default:
1009                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1010                 WARN_ON(vco != 0);
1011                 /* fall through */
1012         case 308571:
1013         case 337500:
1014                 freq_select = CDCLK_FREQ_337_308;
1015                 break;
1016         case 450000:
1017         case 432000:
1018                 freq_select = CDCLK_FREQ_450_432;
1019                 break;
1020         case 540000:
1021                 freq_select = CDCLK_FREQ_540;
1022                 break;
1023         case 617143:
1024         case 675000:
1025                 freq_select = CDCLK_FREQ_675_617;
1026                 break;
1027         }
1028
1029         if (dev_priv->cdclk.hw.vco != 0 &&
1030             dev_priv->cdclk.hw.vco != vco)
1031                 skl_dpll0_disable(dev_priv);
1032
1033         cdclk_ctl = I915_READ(CDCLK_CTL);
1034
1035         if (dev_priv->cdclk.hw.vco != vco) {
1036                 /* Wa Display #1183: skl,kbl,cfl */
1037                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1038                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1039                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1040         }
1041
1042         /* Wa Display #1183: skl,kbl,cfl */
1043         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1044         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1045         POSTING_READ(CDCLK_CTL);
1046
1047         if (dev_priv->cdclk.hw.vco != vco)
1048                 skl_dpll0_enable(dev_priv, vco);
1049
1050         /* Wa Display #1183: skl,kbl,cfl */
1051         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1052         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1053
1054         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1055         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1056
1057         /* Wa Display #1183: skl,kbl,cfl */
1058         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1059         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1060         POSTING_READ(CDCLK_CTL);
1061
1062         /* inform PCU of the change */
1063         mutex_lock(&dev_priv->pcu_lock);
1064         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1065                                 cdclk_state->voltage_level);
1066         mutex_unlock(&dev_priv->pcu_lock);
1067
1068         intel_update_cdclk(dev_priv);
1069 }
1070
1071 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1072 {
1073         uint32_t cdctl, expected;
1074
1075         /*
1076          * check if the pre-os initialized the display
1077          * There is SWF18 scratchpad register defined which is set by the
1078          * pre-os which can be used by the OS drivers to check the status
1079          */
1080         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1081                 goto sanitize;
1082
1083         intel_update_cdclk(dev_priv);
1084         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1085
1086         /* Is PLL enabled and locked ? */
1087         if (dev_priv->cdclk.hw.vco == 0 ||
1088             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1089                 goto sanitize;
1090
1091         /* DPLL okay; verify the cdclock
1092          *
1093          * Noticed in some instances that the freq selection is correct but
1094          * decimal part is programmed wrong from BIOS where pre-os does not
1095          * enable display. Verify the same as well.
1096          */
1097         cdctl = I915_READ(CDCLK_CTL);
1098         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1099                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1100         if (cdctl == expected)
1101                 /* All well; nothing to sanitize */
1102                 return;
1103
1104 sanitize:
1105         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1106
1107         /* force cdclk programming */
1108         dev_priv->cdclk.hw.cdclk = 0;
1109         /* force full PLL disable + enable */
1110         dev_priv->cdclk.hw.vco = -1;
1111 }
1112
1113 /**
1114  * skl_init_cdclk - Initialize CDCLK on SKL
1115  * @dev_priv: i915 device
1116  *
1117  * Initialize CDCLK for SKL and derivatives. This is generally
1118  * done only during the display core initialization sequence,
1119  * after which the DMC will take care of turning CDCLK off/on
1120  * as needed.
1121  */
1122 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1123 {
1124         struct intel_cdclk_state cdclk_state;
1125
1126         skl_sanitize_cdclk(dev_priv);
1127
1128         if (dev_priv->cdclk.hw.cdclk != 0 &&
1129             dev_priv->cdclk.hw.vco != 0) {
1130                 /*
1131                  * Use the current vco as our initial
1132                  * guess as to what the preferred vco is.
1133                  */
1134                 if (dev_priv->skl_preferred_vco_freq == 0)
1135                         skl_set_preferred_cdclk_vco(dev_priv,
1136                                                     dev_priv->cdclk.hw.vco);
1137                 return;
1138         }
1139
1140         cdclk_state = dev_priv->cdclk.hw;
1141
1142         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1143         if (cdclk_state.vco == 0)
1144                 cdclk_state.vco = 8100000;
1145         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1146         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1147
1148         skl_set_cdclk(dev_priv, &cdclk_state);
1149 }
1150
1151 /**
1152  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1153  * @dev_priv: i915 device
1154  *
1155  * Uninitialize CDCLK for SKL and derivatives. This is done only
1156  * during the display core uninitialization sequence.
1157  */
1158 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1159 {
1160         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1161
1162         cdclk_state.cdclk = cdclk_state.ref;
1163         cdclk_state.vco = 0;
1164         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1165
1166         skl_set_cdclk(dev_priv, &cdclk_state);
1167 }
1168
1169 static int bxt_calc_cdclk(int min_cdclk)
1170 {
1171         if (min_cdclk > 576000)
1172                 return 624000;
1173         else if (min_cdclk > 384000)
1174                 return 576000;
1175         else if (min_cdclk > 288000)
1176                 return 384000;
1177         else if (min_cdclk > 144000)
1178                 return 288000;
1179         else
1180                 return 144000;
1181 }
1182
1183 static int glk_calc_cdclk(int min_cdclk)
1184 {
1185         if (min_cdclk > 158400)
1186                 return 316800;
1187         else if (min_cdclk > 79200)
1188                 return 158400;
1189         else
1190                 return 79200;
1191 }
1192
1193 static u8 bxt_calc_voltage_level(int cdclk)
1194 {
1195         return DIV_ROUND_UP(cdclk, 25000);
1196 }
1197
1198 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1199 {
1200         int ratio;
1201
1202         if (cdclk == dev_priv->cdclk.hw.ref)
1203                 return 0;
1204
1205         switch (cdclk) {
1206         default:
1207                 MISSING_CASE(cdclk);
1208                 /* fall through */
1209         case 144000:
1210         case 288000:
1211         case 384000:
1212         case 576000:
1213                 ratio = 60;
1214                 break;
1215         case 624000:
1216                 ratio = 65;
1217                 break;
1218         }
1219
1220         return dev_priv->cdclk.hw.ref * ratio;
1221 }
1222
1223 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1224 {
1225         int ratio;
1226
1227         if (cdclk == dev_priv->cdclk.hw.ref)
1228                 return 0;
1229
1230         switch (cdclk) {
1231         default:
1232                 MISSING_CASE(cdclk);
1233                 /* fall through */
1234         case  79200:
1235         case 158400:
1236         case 316800:
1237                 ratio = 33;
1238                 break;
1239         }
1240
1241         return dev_priv->cdclk.hw.ref * ratio;
1242 }
1243
1244 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1245                               struct intel_cdclk_state *cdclk_state)
1246 {
1247         u32 val;
1248
1249         cdclk_state->ref = 19200;
1250         cdclk_state->vco = 0;
1251
1252         val = I915_READ(BXT_DE_PLL_ENABLE);
1253         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1254                 return;
1255
1256         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1257                 return;
1258
1259         val = I915_READ(BXT_DE_PLL_CTL);
1260         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1261 }
1262
1263 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1264                           struct intel_cdclk_state *cdclk_state)
1265 {
1266         u32 divider;
1267         int div;
1268
1269         bxt_de_pll_update(dev_priv, cdclk_state);
1270
1271         cdclk_state->cdclk = cdclk_state->ref;
1272
1273         if (cdclk_state->vco == 0)
1274                 goto out;
1275
1276         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1277
1278         switch (divider) {
1279         case BXT_CDCLK_CD2X_DIV_SEL_1:
1280                 div = 2;
1281                 break;
1282         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1283                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1284                 div = 3;
1285                 break;
1286         case BXT_CDCLK_CD2X_DIV_SEL_2:
1287                 div = 4;
1288                 break;
1289         case BXT_CDCLK_CD2X_DIV_SEL_4:
1290                 div = 8;
1291                 break;
1292         default:
1293                 MISSING_CASE(divider);
1294                 return;
1295         }
1296
1297         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1298
1299  out:
1300         /*
1301          * Can't read this out :( Let's assume it's
1302          * at least what the CDCLK frequency requires.
1303          */
1304         cdclk_state->voltage_level =
1305                 bxt_calc_voltage_level(cdclk_state->cdclk);
1306 }
1307
1308 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1309 {
1310         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1311
1312         /* Timeout 200us */
1313         if (intel_wait_for_register(dev_priv,
1314                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1315                                     1))
1316                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1317
1318         dev_priv->cdclk.hw.vco = 0;
1319 }
1320
1321 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1322 {
1323         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1324         u32 val;
1325
1326         val = I915_READ(BXT_DE_PLL_CTL);
1327         val &= ~BXT_DE_PLL_RATIO_MASK;
1328         val |= BXT_DE_PLL_RATIO(ratio);
1329         I915_WRITE(BXT_DE_PLL_CTL, val);
1330
1331         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1332
1333         /* Timeout 200us */
1334         if (intel_wait_for_register(dev_priv,
1335                                     BXT_DE_PLL_ENABLE,
1336                                     BXT_DE_PLL_LOCK,
1337                                     BXT_DE_PLL_LOCK,
1338                                     1))
1339                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1340
1341         dev_priv->cdclk.hw.vco = vco;
1342 }
1343
1344 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1345                           const struct intel_cdclk_state *cdclk_state)
1346 {
1347         int cdclk = cdclk_state->cdclk;
1348         int vco = cdclk_state->vco;
1349         u32 val, divider;
1350         int ret;
1351
1352         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1353         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1354         default:
1355                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1356                 WARN_ON(vco != 0);
1357                 /* fall through */
1358         case 2:
1359                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1360                 break;
1361         case 3:
1362                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1363                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1364                 break;
1365         case 4:
1366                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1367                 break;
1368         case 8:
1369                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1370                 break;
1371         }
1372
1373         /*
1374          * Inform power controller of upcoming frequency change. BSpec
1375          * requires us to wait up to 150usec, but that leads to timeouts;
1376          * the 2ms used here is based on experiment.
1377          */
1378         mutex_lock(&dev_priv->pcu_lock);
1379         ret = sandybridge_pcode_write_timeout(dev_priv,
1380                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1381                                               0x80000000, 2000);
1382         mutex_unlock(&dev_priv->pcu_lock);
1383
1384         if (ret) {
1385                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1386                           ret, cdclk);
1387                 return;
1388         }
1389
1390         if (dev_priv->cdclk.hw.vco != 0 &&
1391             dev_priv->cdclk.hw.vco != vco)
1392                 bxt_de_pll_disable(dev_priv);
1393
1394         if (dev_priv->cdclk.hw.vco != vco)
1395                 bxt_de_pll_enable(dev_priv, vco);
1396
1397         val = divider | skl_cdclk_decimal(cdclk);
1398         /*
1399          * FIXME if only the cd2x divider needs changing, it could be done
1400          * without shutting off the pipe (if only one pipe is active).
1401          */
1402         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1403         /*
1404          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1405          * enable otherwise.
1406          */
1407         if (cdclk >= 500000)
1408                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1409         I915_WRITE(CDCLK_CTL, val);
1410
1411         mutex_lock(&dev_priv->pcu_lock);
1412         /*
1413          * The timeout isn't specified, the 2ms used here is based on
1414          * experiment.
1415          * FIXME: Waiting for the request completion could be delayed until
1416          * the next PCODE request based on BSpec.
1417          */
1418         ret = sandybridge_pcode_write_timeout(dev_priv,
1419                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1420                                               cdclk_state->voltage_level, 2000);
1421         mutex_unlock(&dev_priv->pcu_lock);
1422
1423         if (ret) {
1424                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1425                           ret, cdclk);
1426                 return;
1427         }
1428
1429         intel_update_cdclk(dev_priv);
1430 }
1431
1432 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1433 {
1434         u32 cdctl, expected;
1435
1436         intel_update_cdclk(dev_priv);
1437         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1438
1439         if (dev_priv->cdclk.hw.vco == 0 ||
1440             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1441                 goto sanitize;
1442
1443         /* DPLL okay; verify the cdclock
1444          *
1445          * Some BIOS versions leave an incorrect decimal frequency value and
1446          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1447          * so sanitize this register.
1448          */
1449         cdctl = I915_READ(CDCLK_CTL);
1450         /*
1451          * Let's ignore the pipe field, since BIOS could have configured the
1452          * dividers both synching to an active pipe, or asynchronously
1453          * (PIPE_NONE).
1454          */
1455         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1456
1457         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1458                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1459         /*
1460          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1461          * enable otherwise.
1462          */
1463         if (dev_priv->cdclk.hw.cdclk >= 500000)
1464                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1465
1466         if (cdctl == expected)
1467                 /* All well; nothing to sanitize */
1468                 return;
1469
1470 sanitize:
1471         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1472
1473         /* force cdclk programming */
1474         dev_priv->cdclk.hw.cdclk = 0;
1475
1476         /* force full PLL disable + enable */
1477         dev_priv->cdclk.hw.vco = -1;
1478 }
1479
1480 /**
1481  * bxt_init_cdclk - Initialize CDCLK on BXT
1482  * @dev_priv: i915 device
1483  *
1484  * Initialize CDCLK for BXT and derivatives. This is generally
1485  * done only during the display core initialization sequence,
1486  * after which the DMC will take care of turning CDCLK off/on
1487  * as needed.
1488  */
1489 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1490 {
1491         struct intel_cdclk_state cdclk_state;
1492
1493         bxt_sanitize_cdclk(dev_priv);
1494
1495         if (dev_priv->cdclk.hw.cdclk != 0 &&
1496             dev_priv->cdclk.hw.vco != 0)
1497                 return;
1498
1499         cdclk_state = dev_priv->cdclk.hw;
1500
1501         /*
1502          * FIXME:
1503          * - The initial CDCLK needs to be read from VBT.
1504          *   Need to make this change after VBT has changes for BXT.
1505          */
1506         if (IS_GEMINILAKE(dev_priv)) {
1507                 cdclk_state.cdclk = glk_calc_cdclk(0);
1508                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1509         } else {
1510                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1511                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1512         }
1513         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1514
1515         bxt_set_cdclk(dev_priv, &cdclk_state);
1516 }
1517
1518 /**
1519  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1520  * @dev_priv: i915 device
1521  *
1522  * Uninitialize CDCLK for BXT and derivatives. This is done only
1523  * during the display core uninitialization sequence.
1524  */
1525 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1526 {
1527         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1528
1529         cdclk_state.cdclk = cdclk_state.ref;
1530         cdclk_state.vco = 0;
1531         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1532
1533         bxt_set_cdclk(dev_priv, &cdclk_state);
1534 }
1535
1536 static int cnl_calc_cdclk(int min_cdclk)
1537 {
1538         if (min_cdclk > 336000)
1539                 return 528000;
1540         else if (min_cdclk > 168000)
1541                 return 336000;
1542         else
1543                 return 168000;
1544 }
1545
1546 static u8 cnl_calc_voltage_level(int cdclk)
1547 {
1548         switch (cdclk) {
1549         default:
1550         case 168000:
1551                 return 0;
1552         case 336000:
1553                 return 1;
1554         case 528000:
1555                 return 2;
1556         }
1557 }
1558
1559 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1560                                  struct intel_cdclk_state *cdclk_state)
1561 {
1562         u32 val;
1563
1564         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1565                 cdclk_state->ref = 24000;
1566         else
1567                 cdclk_state->ref = 19200;
1568
1569         cdclk_state->vco = 0;
1570
1571         val = I915_READ(BXT_DE_PLL_ENABLE);
1572         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1573                 return;
1574
1575         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1576                 return;
1577
1578         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1579 }
1580
1581 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1582                          struct intel_cdclk_state *cdclk_state)
1583 {
1584         u32 divider;
1585         int div;
1586
1587         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1588
1589         cdclk_state->cdclk = cdclk_state->ref;
1590
1591         if (cdclk_state->vco == 0)
1592                 goto out;
1593
1594         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1595
1596         switch (divider) {
1597         case BXT_CDCLK_CD2X_DIV_SEL_1:
1598                 div = 2;
1599                 break;
1600         case BXT_CDCLK_CD2X_DIV_SEL_2:
1601                 div = 4;
1602                 break;
1603         default:
1604                 MISSING_CASE(divider);
1605                 return;
1606         }
1607
1608         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1609
1610  out:
1611         /*
1612          * Can't read this out :( Let's assume it's
1613          * at least what the CDCLK frequency requires.
1614          */
1615         cdclk_state->voltage_level =
1616                 cnl_calc_voltage_level(cdclk_state->cdclk);
1617 }
1618
1619 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1620 {
1621         u32 val;
1622
1623         val = I915_READ(BXT_DE_PLL_ENABLE);
1624         val &= ~BXT_DE_PLL_PLL_ENABLE;
1625         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1626
1627         /* Timeout 200us */
1628         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1629                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1630
1631         dev_priv->cdclk.hw.vco = 0;
1632 }
1633
1634 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1635 {
1636         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1637         u32 val;
1638
1639         val = CNL_CDCLK_PLL_RATIO(ratio);
1640         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1641
1642         val |= BXT_DE_PLL_PLL_ENABLE;
1643         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1644
1645         /* Timeout 200us */
1646         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1647                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1648
1649         dev_priv->cdclk.hw.vco = vco;
1650 }
1651
1652 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1653                           const struct intel_cdclk_state *cdclk_state)
1654 {
1655         int cdclk = cdclk_state->cdclk;
1656         int vco = cdclk_state->vco;
1657         u32 val, divider;
1658         int ret;
1659
1660         mutex_lock(&dev_priv->pcu_lock);
1661         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1662                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1663                                 SKL_CDCLK_READY_FOR_CHANGE,
1664                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1665         mutex_unlock(&dev_priv->pcu_lock);
1666         if (ret) {
1667                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1668                           ret);
1669                 return;
1670         }
1671
1672         /* cdclk = vco / 2 / div{1,2} */
1673         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1674         default:
1675                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1676                 WARN_ON(vco != 0);
1677                 /* fall through */
1678         case 2:
1679                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1680                 break;
1681         case 4:
1682                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1683                 break;
1684         }
1685
1686         if (dev_priv->cdclk.hw.vco != 0 &&
1687             dev_priv->cdclk.hw.vco != vco)
1688                 cnl_cdclk_pll_disable(dev_priv);
1689
1690         if (dev_priv->cdclk.hw.vco != vco)
1691                 cnl_cdclk_pll_enable(dev_priv, vco);
1692
1693         val = divider | skl_cdclk_decimal(cdclk);
1694         /*
1695          * FIXME if only the cd2x divider needs changing, it could be done
1696          * without shutting off the pipe (if only one pipe is active).
1697          */
1698         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1699         I915_WRITE(CDCLK_CTL, val);
1700
1701         /* inform PCU of the change */
1702         mutex_lock(&dev_priv->pcu_lock);
1703         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1704                                 cdclk_state->voltage_level);
1705         mutex_unlock(&dev_priv->pcu_lock);
1706
1707         intel_update_cdclk(dev_priv);
1708
1709         /*
1710          * Can't read out the voltage level :(
1711          * Let's just assume everything is as expected.
1712          */
1713         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1714 }
1715
1716 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1717 {
1718         int ratio;
1719
1720         if (cdclk == dev_priv->cdclk.hw.ref)
1721                 return 0;
1722
1723         switch (cdclk) {
1724         default:
1725                 MISSING_CASE(cdclk);
1726                 /* fall through */
1727         case 168000:
1728         case 336000:
1729                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1730                 break;
1731         case 528000:
1732                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1733                 break;
1734         }
1735
1736         return dev_priv->cdclk.hw.ref * ratio;
1737 }
1738
1739 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1740 {
1741         u32 cdctl, expected;
1742
1743         intel_update_cdclk(dev_priv);
1744         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1745
1746         if (dev_priv->cdclk.hw.vco == 0 ||
1747             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1748                 goto sanitize;
1749
1750         /* DPLL okay; verify the cdclock
1751          *
1752          * Some BIOS versions leave an incorrect decimal frequency value and
1753          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1754          * so sanitize this register.
1755          */
1756         cdctl = I915_READ(CDCLK_CTL);
1757         /*
1758          * Let's ignore the pipe field, since BIOS could have configured the
1759          * dividers both synching to an active pipe, or asynchronously
1760          * (PIPE_NONE).
1761          */
1762         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1763
1764         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1765                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1766
1767         if (cdctl == expected)
1768                 /* All well; nothing to sanitize */
1769                 return;
1770
1771 sanitize:
1772         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1773
1774         /* force cdclk programming */
1775         dev_priv->cdclk.hw.cdclk = 0;
1776
1777         /* force full PLL disable + enable */
1778         dev_priv->cdclk.hw.vco = -1;
1779 }
1780
1781 /**
1782  * cnl_init_cdclk - Initialize CDCLK on CNL
1783  * @dev_priv: i915 device
1784  *
1785  * Initialize CDCLK for CNL. This is generally
1786  * done only during the display core initialization sequence,
1787  * after which the DMC will take care of turning CDCLK off/on
1788  * as needed.
1789  */
1790 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1791 {
1792         struct intel_cdclk_state cdclk_state;
1793
1794         cnl_sanitize_cdclk(dev_priv);
1795
1796         if (dev_priv->cdclk.hw.cdclk != 0 &&
1797             dev_priv->cdclk.hw.vco != 0)
1798                 return;
1799
1800         cdclk_state = dev_priv->cdclk.hw;
1801
1802         cdclk_state.cdclk = cnl_calc_cdclk(0);
1803         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1804         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1805
1806         cnl_set_cdclk(dev_priv, &cdclk_state);
1807 }
1808
1809 /**
1810  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1811  * @dev_priv: i915 device
1812  *
1813  * Uninitialize CDCLK for CNL. This is done only
1814  * during the display core uninitialization sequence.
1815  */
1816 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1817 {
1818         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1819
1820         cdclk_state.cdclk = cdclk_state.ref;
1821         cdclk_state.vco = 0;
1822         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1823
1824         cnl_set_cdclk(dev_priv, &cdclk_state);
1825 }
1826
1827 /**
1828  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
1829  * @a: first CDCLK state
1830  * @b: second CDCLK state
1831  *
1832  * Returns:
1833  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
1834  */
1835 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1836                                const struct intel_cdclk_state *b)
1837 {
1838         return a->cdclk != b->cdclk ||
1839                 a->vco != b->vco ||
1840                 a->ref != b->ref;
1841 }
1842
1843 /**
1844  * intel_cdclk_changed - Determine if two CDCLK states are different
1845  * @a: first CDCLK state
1846  * @b: second CDCLK state
1847  *
1848  * Returns:
1849  * True if the CDCLK states don't match, false if they do.
1850  */
1851 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1852                          const struct intel_cdclk_state *b)
1853 {
1854         return intel_cdclk_needs_modeset(a, b) ||
1855                 a->voltage_level != b->voltage_level;
1856 }
1857
1858 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1859                             const char *context)
1860 {
1861         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
1862                          context, cdclk_state->cdclk, cdclk_state->vco,
1863                          cdclk_state->ref, cdclk_state->voltage_level);
1864 }
1865
1866 /**
1867  * intel_set_cdclk - Push the CDCLK state to the hardware
1868  * @dev_priv: i915 device
1869  * @cdclk_state: new CDCLK state
1870  *
1871  * Program the hardware based on the passed in CDCLK state,
1872  * if necessary.
1873  */
1874 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1875                      const struct intel_cdclk_state *cdclk_state)
1876 {
1877         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
1878                 return;
1879
1880         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1881                 return;
1882
1883         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
1884
1885         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1886
1887         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
1888                  "cdclk state doesn't match!\n")) {
1889                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
1890                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
1891         }
1892 }
1893
1894 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
1895                                      int pixel_rate)
1896 {
1897         if (INTEL_GEN(dev_priv) >= 10)
1898                 return DIV_ROUND_UP(pixel_rate, 2);
1899         else if (IS_GEMINILAKE(dev_priv))
1900                 /*
1901                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1902                  * as a temporary workaround. Use a higher cdclk instead. (Note that
1903                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1904                  * cdclk.)
1905                  */
1906                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
1907         else if (IS_GEN9(dev_priv) ||
1908                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1909                 return pixel_rate;
1910         else if (IS_CHERRYVIEW(dev_priv))
1911                 return DIV_ROUND_UP(pixel_rate * 100, 95);
1912         else
1913                 return DIV_ROUND_UP(pixel_rate * 100, 90);
1914 }
1915
1916 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
1917 {
1918         struct drm_i915_private *dev_priv =
1919                 to_i915(crtc_state->base.crtc->dev);
1920         int min_cdclk;
1921
1922         if (!crtc_state->base.enable)
1923                 return 0;
1924
1925         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
1926
1927         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1928         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
1929                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
1930
1931         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1932          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1933          * there may be audio corruption or screen corruption." This cdclk
1934          * restriction for GLK is 316.8 MHz.
1935          */
1936         if (intel_crtc_has_dp_encoder(crtc_state) &&
1937             crtc_state->has_audio &&
1938             crtc_state->port_clock >= 540000 &&
1939             crtc_state->lane_count == 4) {
1940                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1941                         /* Display WA #1145: glk,cnl */
1942                         min_cdclk = max(316800, min_cdclk);
1943                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
1944                         /* Display WA #1144: skl,bxt */
1945                         min_cdclk = max(432000, min_cdclk);
1946                 }
1947         }
1948
1949         /* According to BSpec, "The CD clock frequency must be at least twice
1950          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1951          */
1952         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
1953                 min_cdclk = max(2 * 96000, min_cdclk);
1954
1955         /*
1956          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
1957          * than 320000KHz.
1958          */
1959         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
1960             IS_VALLEYVIEW(dev_priv))
1961                 min_cdclk = max(320000, min_cdclk);
1962
1963         if (min_cdclk > dev_priv->max_cdclk_freq) {
1964                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
1965                               min_cdclk, dev_priv->max_cdclk_freq);
1966                 return -EINVAL;
1967         }
1968
1969         return min_cdclk;
1970 }
1971
1972 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
1973 {
1974         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1975         struct drm_i915_private *dev_priv = to_i915(state->dev);
1976         struct intel_crtc *crtc;
1977         struct intel_crtc_state *crtc_state;
1978         int min_cdclk, i;
1979         enum pipe pipe;
1980
1981         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
1982                sizeof(intel_state->min_cdclk));
1983
1984         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
1985                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
1986                 if (min_cdclk < 0)
1987                         return min_cdclk;
1988
1989                 intel_state->min_cdclk[i] = min_cdclk;
1990         }
1991
1992         min_cdclk = 0;
1993         for_each_pipe(dev_priv, pipe)
1994                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
1995
1996         return min_cdclk;
1997 }
1998
1999 /*
2000  * Note that this functions assumes that 0 is
2001  * the lowest voltage value, and higher values
2002  * correspond to increasingly higher voltages.
2003  *
2004  * Should that relationship no longer hold on
2005  * future platforms this code will need to be
2006  * adjusted.
2007  */
2008 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2009 {
2010         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2011         struct intel_crtc *crtc;
2012         struct intel_crtc_state *crtc_state;
2013         u8 min_voltage_level;
2014         int i;
2015         enum pipe pipe;
2016
2017         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2018                sizeof(state->min_voltage_level));
2019
2020         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2021                 if (crtc_state->base.enable)
2022                         state->min_voltage_level[i] =
2023                                 crtc_state->min_voltage_level;
2024                 else
2025                         state->min_voltage_level[i] = 0;
2026         }
2027
2028         min_voltage_level = 0;
2029         for_each_pipe(dev_priv, pipe)
2030                 min_voltage_level = max(state->min_voltage_level[pipe],
2031                                         min_voltage_level);
2032
2033         return min_voltage_level;
2034 }
2035
2036 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2037 {
2038         struct drm_i915_private *dev_priv = to_i915(state->dev);
2039         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2040         int min_cdclk, cdclk;
2041
2042         min_cdclk = intel_compute_min_cdclk(state);
2043         if (min_cdclk < 0)
2044                 return min_cdclk;
2045
2046         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2047
2048         intel_state->cdclk.logical.cdclk = cdclk;
2049         intel_state->cdclk.logical.voltage_level =
2050                 vlv_calc_voltage_level(dev_priv, cdclk);
2051
2052         if (!intel_state->active_crtcs) {
2053                 cdclk = vlv_calc_cdclk(dev_priv, 0);
2054
2055                 intel_state->cdclk.actual.cdclk = cdclk;
2056                 intel_state->cdclk.actual.voltage_level =
2057                         vlv_calc_voltage_level(dev_priv, cdclk);
2058         } else {
2059                 intel_state->cdclk.actual =
2060                         intel_state->cdclk.logical;
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2067 {
2068         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2069         int min_cdclk, cdclk;
2070
2071         min_cdclk = intel_compute_min_cdclk(state);
2072         if (min_cdclk < 0)
2073                 return min_cdclk;
2074
2075         /*
2076          * FIXME should also account for plane ratio
2077          * once 64bpp pixel formats are supported.
2078          */
2079         cdclk = bdw_calc_cdclk(min_cdclk);
2080
2081         intel_state->cdclk.logical.cdclk = cdclk;
2082         intel_state->cdclk.logical.voltage_level =
2083                 bdw_calc_voltage_level(cdclk);
2084
2085         if (!intel_state->active_crtcs) {
2086                 cdclk = bdw_calc_cdclk(0);
2087
2088                 intel_state->cdclk.actual.cdclk = cdclk;
2089                 intel_state->cdclk.actual.voltage_level =
2090                         bdw_calc_voltage_level(cdclk);
2091         } else {
2092                 intel_state->cdclk.actual =
2093                         intel_state->cdclk.logical;
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2100 {
2101         struct drm_i915_private *dev_priv = to_i915(state->dev);
2102         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2103         int min_cdclk, cdclk, vco;
2104
2105         min_cdclk = intel_compute_min_cdclk(state);
2106         if (min_cdclk < 0)
2107                 return min_cdclk;
2108
2109         vco = intel_state->cdclk.logical.vco;
2110         if (!vco)
2111                 vco = dev_priv->skl_preferred_vco_freq;
2112
2113         /*
2114          * FIXME should also account for plane ratio
2115          * once 64bpp pixel formats are supported.
2116          */
2117         cdclk = skl_calc_cdclk(min_cdclk, vco);
2118
2119         intel_state->cdclk.logical.vco = vco;
2120         intel_state->cdclk.logical.cdclk = cdclk;
2121         intel_state->cdclk.logical.voltage_level =
2122                 skl_calc_voltage_level(cdclk);
2123
2124         if (!intel_state->active_crtcs) {
2125                 cdclk = skl_calc_cdclk(0, vco);
2126
2127                 intel_state->cdclk.actual.vco = vco;
2128                 intel_state->cdclk.actual.cdclk = cdclk;
2129                 intel_state->cdclk.actual.voltage_level =
2130                         skl_calc_voltage_level(cdclk);
2131         } else {
2132                 intel_state->cdclk.actual =
2133                         intel_state->cdclk.logical;
2134         }
2135
2136         return 0;
2137 }
2138
2139 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2140 {
2141         struct drm_i915_private *dev_priv = to_i915(state->dev);
2142         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2143         int min_cdclk, cdclk, vco;
2144
2145         min_cdclk = intel_compute_min_cdclk(state);
2146         if (min_cdclk < 0)
2147                 return min_cdclk;
2148
2149         if (IS_GEMINILAKE(dev_priv)) {
2150                 cdclk = glk_calc_cdclk(min_cdclk);
2151                 vco = glk_de_pll_vco(dev_priv, cdclk);
2152         } else {
2153                 cdclk = bxt_calc_cdclk(min_cdclk);
2154                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2155         }
2156
2157         intel_state->cdclk.logical.vco = vco;
2158         intel_state->cdclk.logical.cdclk = cdclk;
2159         intel_state->cdclk.logical.voltage_level =
2160                 bxt_calc_voltage_level(cdclk);
2161
2162         if (!intel_state->active_crtcs) {
2163                 if (IS_GEMINILAKE(dev_priv)) {
2164                         cdclk = glk_calc_cdclk(0);
2165                         vco = glk_de_pll_vco(dev_priv, cdclk);
2166                 } else {
2167                         cdclk = bxt_calc_cdclk(0);
2168                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2169                 }
2170
2171                 intel_state->cdclk.actual.vco = vco;
2172                 intel_state->cdclk.actual.cdclk = cdclk;
2173                 intel_state->cdclk.actual.voltage_level =
2174                         bxt_calc_voltage_level(cdclk);
2175         } else {
2176                 intel_state->cdclk.actual =
2177                         intel_state->cdclk.logical;
2178         }
2179
2180         return 0;
2181 }
2182
2183 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2184 {
2185         struct drm_i915_private *dev_priv = to_i915(state->dev);
2186         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2187         int min_cdclk, cdclk, vco;
2188
2189         min_cdclk = intel_compute_min_cdclk(state);
2190         if (min_cdclk < 0)
2191                 return min_cdclk;
2192
2193         cdclk = cnl_calc_cdclk(min_cdclk);
2194         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2195
2196         intel_state->cdclk.logical.vco = vco;
2197         intel_state->cdclk.logical.cdclk = cdclk;
2198         intel_state->cdclk.logical.voltage_level =
2199                 max(cnl_calc_voltage_level(cdclk),
2200                     cnl_compute_min_voltage_level(intel_state));
2201
2202         if (!intel_state->active_crtcs) {
2203                 cdclk = cnl_calc_cdclk(0);
2204                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2205
2206                 intel_state->cdclk.actual.vco = vco;
2207                 intel_state->cdclk.actual.cdclk = cdclk;
2208                 intel_state->cdclk.actual.voltage_level =
2209                         cnl_calc_voltage_level(cdclk);
2210         } else {
2211                 intel_state->cdclk.actual =
2212                         intel_state->cdclk.logical;
2213         }
2214
2215         return 0;
2216 }
2217
2218 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2219 {
2220         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2221
2222         if (INTEL_GEN(dev_priv) >= 10)
2223                 return 2 * max_cdclk_freq;
2224         else if (IS_GEMINILAKE(dev_priv))
2225                 /*
2226                  * FIXME: Limiting to 99% as a temporary workaround. See
2227                  * intel_min_cdclk() for details.
2228                  */
2229                 return 2 * max_cdclk_freq * 99 / 100;
2230         else if (IS_GEN9(dev_priv) ||
2231                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2232                 return max_cdclk_freq;
2233         else if (IS_CHERRYVIEW(dev_priv))
2234                 return max_cdclk_freq*95/100;
2235         else if (INTEL_INFO(dev_priv)->gen < 4)
2236                 return 2*max_cdclk_freq*90/100;
2237         else
2238                 return max_cdclk_freq*90/100;
2239 }
2240
2241 /**
2242  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2243  * @dev_priv: i915 device
2244  *
2245  * Determine the maximum CDCLK frequency the platform supports, and also
2246  * derive the maximum dot clock frequency the maximum CDCLK frequency
2247  * allows.
2248  */
2249 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2250 {
2251         if (IS_CANNONLAKE(dev_priv)) {
2252                 dev_priv->max_cdclk_freq = 528000;
2253         } else if (IS_GEN9_BC(dev_priv)) {
2254                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2255                 int max_cdclk, vco;
2256
2257                 vco = dev_priv->skl_preferred_vco_freq;
2258                 WARN_ON(vco != 8100000 && vco != 8640000);
2259
2260                 /*
2261                  * Use the lower (vco 8640) cdclk values as a
2262                  * first guess. skl_calc_cdclk() will correct it
2263                  * if the preferred vco is 8100 instead.
2264                  */
2265                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2266                         max_cdclk = 617143;
2267                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2268                         max_cdclk = 540000;
2269                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2270                         max_cdclk = 432000;
2271                 else
2272                         max_cdclk = 308571;
2273
2274                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2275         } else if (IS_GEMINILAKE(dev_priv)) {
2276                 dev_priv->max_cdclk_freq = 316800;
2277         } else if (IS_BROXTON(dev_priv)) {
2278                 dev_priv->max_cdclk_freq = 624000;
2279         } else if (IS_BROADWELL(dev_priv))  {
2280                 /*
2281                  * FIXME with extra cooling we can allow
2282                  * 540 MHz for ULX and 675 Mhz for ULT.
2283                  * How can we know if extra cooling is
2284                  * available? PCI ID, VTB, something else?
2285                  */
2286                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2287                         dev_priv->max_cdclk_freq = 450000;
2288                 else if (IS_BDW_ULX(dev_priv))
2289                         dev_priv->max_cdclk_freq = 450000;
2290                 else if (IS_BDW_ULT(dev_priv))
2291                         dev_priv->max_cdclk_freq = 540000;
2292                 else
2293                         dev_priv->max_cdclk_freq = 675000;
2294         } else if (IS_CHERRYVIEW(dev_priv)) {
2295                 dev_priv->max_cdclk_freq = 320000;
2296         } else if (IS_VALLEYVIEW(dev_priv)) {
2297                 dev_priv->max_cdclk_freq = 400000;
2298         } else {
2299                 /* otherwise assume cdclk is fixed */
2300                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2301         }
2302
2303         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2304
2305         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2306                          dev_priv->max_cdclk_freq);
2307
2308         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2309                          dev_priv->max_dotclk_freq);
2310 }
2311
2312 /**
2313  * intel_update_cdclk - Determine the current CDCLK frequency
2314  * @dev_priv: i915 device
2315  *
2316  * Determine the current CDCLK frequency.
2317  */
2318 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2319 {
2320         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2321
2322         /*
2323          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2324          * Programmng [sic] note: bit[9:2] should be programmed to the number
2325          * of cdclk that generates 4MHz reference clock freq which is used to
2326          * generate GMBus clock. This will vary with the cdclk freq.
2327          */
2328         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2329                 I915_WRITE(GMBUSFREQ_VLV,
2330                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2331 }
2332
2333 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2334 {
2335         u32 rawclk;
2336         int divider, fraction;
2337
2338         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2339                 /* 24 MHz */
2340                 divider = 24000;
2341                 fraction = 0;
2342         } else {
2343                 /* 19.2 MHz */
2344                 divider = 19000;
2345                 fraction = 200;
2346         }
2347
2348         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2349         if (fraction)
2350                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2351                                                             fraction) - 1);
2352
2353         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2354         return divider + fraction;
2355 }
2356
2357 static int pch_rawclk(struct drm_i915_private *dev_priv)
2358 {
2359         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2360 }
2361
2362 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2363 {
2364         /* RAWCLK_FREQ_VLV register updated from power well code */
2365         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2366                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2367 }
2368
2369 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2370 {
2371         uint32_t clkcfg;
2372
2373         /* hrawclock is 1/4 the FSB frequency */
2374         clkcfg = I915_READ(CLKCFG);
2375         switch (clkcfg & CLKCFG_FSB_MASK) {
2376         case CLKCFG_FSB_400:
2377                 return 100000;
2378         case CLKCFG_FSB_533:
2379                 return 133333;
2380         case CLKCFG_FSB_667:
2381                 return 166667;
2382         case CLKCFG_FSB_800:
2383                 return 200000;
2384         case CLKCFG_FSB_1067:
2385         case CLKCFG_FSB_1067_ALT:
2386                 return 266667;
2387         case CLKCFG_FSB_1333:
2388         case CLKCFG_FSB_1333_ALT:
2389                 return 333333;
2390         default:
2391                 return 133333;
2392         }
2393 }
2394
2395 /**
2396  * intel_update_rawclk - Determine the current RAWCLK frequency
2397  * @dev_priv: i915 device
2398  *
2399  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2400  * frequency clock so this needs to done only once.
2401  */
2402 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2403 {
2404
2405         if (HAS_PCH_CNP(dev_priv))
2406                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2407         else if (HAS_PCH_SPLIT(dev_priv))
2408                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2409         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2410                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2411         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2412                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2413         else
2414                 /* no rawclk on other platforms, or no need to know it */
2415                 return;
2416
2417         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2418 }
2419
2420 /**
2421  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2422  * @dev_priv: i915 device
2423  */
2424 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2425 {
2426         if (IS_CHERRYVIEW(dev_priv)) {
2427                 dev_priv->display.set_cdclk = chv_set_cdclk;
2428                 dev_priv->display.modeset_calc_cdclk =
2429                         vlv_modeset_calc_cdclk;
2430         } else if (IS_VALLEYVIEW(dev_priv)) {
2431                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2432                 dev_priv->display.modeset_calc_cdclk =
2433                         vlv_modeset_calc_cdclk;
2434         } else if (IS_BROADWELL(dev_priv)) {
2435                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2436                 dev_priv->display.modeset_calc_cdclk =
2437                         bdw_modeset_calc_cdclk;
2438         } else if (IS_GEN9_LP(dev_priv)) {
2439                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2440                 dev_priv->display.modeset_calc_cdclk =
2441                         bxt_modeset_calc_cdclk;
2442         } else if (IS_GEN9_BC(dev_priv)) {
2443                 dev_priv->display.set_cdclk = skl_set_cdclk;
2444                 dev_priv->display.modeset_calc_cdclk =
2445                         skl_modeset_calc_cdclk;
2446         } else if (IS_CANNONLAKE(dev_priv)) {
2447                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2448                 dev_priv->display.modeset_calc_cdclk =
2449                         cnl_modeset_calc_cdclk;
2450         }
2451
2452         if (IS_CANNONLAKE(dev_priv))
2453                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2454         else if (IS_GEN9_BC(dev_priv))
2455                 dev_priv->display.get_cdclk = skl_get_cdclk;
2456         else if (IS_GEN9_LP(dev_priv))
2457                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2458         else if (IS_BROADWELL(dev_priv))
2459                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2460         else if (IS_HASWELL(dev_priv))
2461                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2462         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2463                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2464         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2465                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2466         else if (IS_GEN5(dev_priv))
2467                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2468         else if (IS_GM45(dev_priv))
2469                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2470         else if (IS_G45(dev_priv))
2471                 dev_priv->display.get_cdclk = g33_get_cdclk;
2472         else if (IS_I965GM(dev_priv))
2473                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2474         else if (IS_I965G(dev_priv))
2475                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2476         else if (IS_PINEVIEW(dev_priv))
2477                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2478         else if (IS_G33(dev_priv))
2479                 dev_priv->display.get_cdclk = g33_get_cdclk;
2480         else if (IS_I945GM(dev_priv))
2481                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2482         else if (IS_I945G(dev_priv))
2483                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2484         else if (IS_I915GM(dev_priv))
2485                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2486         else if (IS_I915G(dev_priv))
2487                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2488         else if (IS_I865G(dev_priv))
2489                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2490         else if (IS_I85X(dev_priv))
2491                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2492         else if (IS_I845G(dev_priv))
2493                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2494         else { /* 830 */
2495                 WARN(!IS_I830(dev_priv),
2496                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2497                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2498         }
2499 }