2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include <drm/intel_lpe_audio.h>
28 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct &i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
61 #define LC_810M 810000
62 #define LC_540M 540000
63 #define LC_270M 270000
64 #define LC_162M 162000
73 /* Values according to DP 1.4 Table 2-104 */
74 static const struct dp_aud_n_m dp_aud_n_m[] = {
75 { 32000, LC_162M, 1024, 10125 },
76 { 44100, LC_162M, 784, 5625 },
77 { 48000, LC_162M, 512, 3375 },
78 { 64000, LC_162M, 2048, 10125 },
79 { 88200, LC_162M, 1568, 5625 },
80 { 96000, LC_162M, 1024, 3375 },
81 { 128000, LC_162M, 4096, 10125 },
82 { 176400, LC_162M, 3136, 5625 },
83 { 192000, LC_162M, 2048, 3375 },
84 { 32000, LC_270M, 1024, 16875 },
85 { 44100, LC_270M, 784, 9375 },
86 { 48000, LC_270M, 512, 5625 },
87 { 64000, LC_270M, 2048, 16875 },
88 { 88200, LC_270M, 1568, 9375 },
89 { 96000, LC_270M, 1024, 5625 },
90 { 128000, LC_270M, 4096, 16875 },
91 { 176400, LC_270M, 3136, 9375 },
92 { 192000, LC_270M, 2048, 5625 },
93 { 32000, LC_540M, 1024, 33750 },
94 { 44100, LC_540M, 784, 18750 },
95 { 48000, LC_540M, 512, 11250 },
96 { 64000, LC_540M, 2048, 33750 },
97 { 88200, LC_540M, 1568, 18750 },
98 { 96000, LC_540M, 1024, 11250 },
99 { 128000, LC_540M, 4096, 33750 },
100 { 176400, LC_540M, 3136, 18750 },
101 { 192000, LC_540M, 2048, 11250 },
102 { 32000, LC_810M, 1024, 50625 },
103 { 44100, LC_810M, 784, 28125 },
104 { 48000, LC_810M, 512, 16875 },
105 { 64000, LC_810M, 2048, 50625 },
106 { 88200, LC_810M, 1568, 28125 },
107 { 96000, LC_810M, 1024, 16875 },
108 { 128000, LC_810M, 4096, 50625 },
109 { 176400, LC_810M, 3136, 28125 },
110 { 192000, LC_810M, 2048, 16875 },
113 static const struct dp_aud_n_m *
114 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
118 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
119 if (rate == dp_aud_n_m[i].sample_rate &&
120 crtc_state->port_clock == dp_aud_n_m[i].clock)
121 return &dp_aud_n_m[i];
127 static const struct {
130 } hdmi_audio_clock[] = {
131 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
132 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
133 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
134 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
135 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
136 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
137 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
138 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
139 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
140 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
143 /* HDMI N/CTS table */
144 #define TMDS_297M 297000
145 #define TMDS_296M 296703
146 #define TMDS_594M 594000
147 #define TMDS_593M 593407
149 static const struct {
154 } hdmi_aud_ncts[] = {
155 { 32000, TMDS_296M, 5824, 421875 },
156 { 32000, TMDS_297M, 3072, 222750 },
157 { 32000, TMDS_593M, 5824, 843750 },
158 { 32000, TMDS_594M, 3072, 445500 },
159 { 44100, TMDS_296M, 4459, 234375 },
160 { 44100, TMDS_297M, 4704, 247500 },
161 { 44100, TMDS_593M, 8918, 937500 },
162 { 44100, TMDS_594M, 9408, 990000 },
163 { 88200, TMDS_296M, 8918, 234375 },
164 { 88200, TMDS_297M, 9408, 247500 },
165 { 88200, TMDS_593M, 17836, 937500 },
166 { 88200, TMDS_594M, 18816, 990000 },
167 { 176400, TMDS_296M, 17836, 234375 },
168 { 176400, TMDS_297M, 18816, 247500 },
169 { 176400, TMDS_593M, 35672, 937500 },
170 { 176400, TMDS_594M, 37632, 990000 },
171 { 48000, TMDS_296M, 5824, 281250 },
172 { 48000, TMDS_297M, 5120, 247500 },
173 { 48000, TMDS_593M, 5824, 562500 },
174 { 48000, TMDS_594M, 6144, 594000 },
175 { 96000, TMDS_296M, 11648, 281250 },
176 { 96000, TMDS_297M, 10240, 247500 },
177 { 96000, TMDS_593M, 11648, 562500 },
178 { 96000, TMDS_594M, 12288, 594000 },
179 { 192000, TMDS_296M, 23296, 281250 },
180 { 192000, TMDS_297M, 20480, 247500 },
181 { 192000, TMDS_593M, 23296, 562500 },
182 { 192000, TMDS_594M, 24576, 594000 },
185 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
186 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
188 const struct drm_display_mode *adjusted_mode =
189 &crtc_state->base.adjusted_mode;
192 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
193 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
197 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
198 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
199 adjusted_mode->crtc_clock);
203 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
204 hdmi_audio_clock[i].clock,
205 hdmi_audio_clock[i].config);
207 return hdmi_audio_clock[i].config;
210 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
213 const struct drm_display_mode *adjusted_mode =
214 &crtc_state->base.adjusted_mode;
217 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
218 if (rate == hdmi_aud_ncts[i].sample_rate &&
219 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
220 return hdmi_aud_ncts[i].n;
226 static bool intel_eld_uptodate(struct drm_connector *connector,
227 i915_reg_t reg_eldv, u32 bits_eldv,
228 i915_reg_t reg_elda, u32 bits_elda,
231 struct drm_i915_private *dev_priv = to_i915(connector->dev);
232 const u8 *eld = connector->eld;
236 tmp = I915_READ(reg_eldv);
242 tmp = I915_READ(reg_elda);
244 I915_WRITE(reg_elda, tmp);
246 for (i = 0; i < drm_eld_size(eld) / 4; i++)
247 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
253 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
254 const struct intel_crtc_state *old_crtc_state,
255 const struct drm_connector_state *old_conn_state)
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
260 DRM_DEBUG_KMS("Disable audio codec\n");
262 tmp = I915_READ(G4X_AUD_VID_DID);
263 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
264 eldv = G4X_ELDV_DEVCL_DEVBLC;
266 eldv = G4X_ELDV_DEVCTG;
269 tmp = I915_READ(G4X_AUD_CNTL_ST);
271 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
274 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
275 const struct intel_crtc_state *crtc_state,
276 const struct drm_connector_state *conn_state)
278 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
279 struct drm_connector *connector = conn_state->connector;
280 const u8 *eld = connector->eld;
285 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
287 tmp = I915_READ(G4X_AUD_VID_DID);
288 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
289 eldv = G4X_ELDV_DEVCL_DEVBLC;
291 eldv = G4X_ELDV_DEVCTG;
293 if (intel_eld_uptodate(connector,
294 G4X_AUD_CNTL_ST, eldv,
295 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
299 tmp = I915_READ(G4X_AUD_CNTL_ST);
300 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
301 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
302 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
304 len = min(drm_eld_size(eld) / 4, len);
305 DRM_DEBUG_DRIVER("ELD size %d\n", len);
306 for (i = 0; i < len; i++)
307 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
309 tmp = I915_READ(G4X_AUD_CNTL_ST);
311 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
315 hsw_dp_audio_config_update(struct intel_encoder *encoder,
316 const struct intel_crtc_state *crtc_state)
318 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
319 struct i915_audio_component *acomp = dev_priv->audio_component;
320 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
321 enum port port = encoder->port;
322 enum pipe pipe = crtc->pipe;
323 const struct dp_aud_n_m *nm;
327 rate = acomp ? acomp->aud_sample_rate[port] : 0;
328 nm = audio_config_dp_get_n_m(crtc_state, rate);
330 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
332 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
334 tmp = I915_READ(HSW_AUD_CFG(pipe));
335 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
336 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
337 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
338 tmp |= AUD_CONFIG_N_VALUE_INDEX;
341 tmp &= ~AUD_CONFIG_N_MASK;
342 tmp |= AUD_CONFIG_N(nm->n);
343 tmp |= AUD_CONFIG_N_PROG_ENABLE;
346 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
348 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
349 tmp &= ~AUD_CONFIG_M_MASK;
350 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
351 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
355 tmp |= AUD_M_CTS_M_VALUE_INDEX;
356 tmp |= AUD_M_CTS_M_PROG_ENABLE;
359 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
363 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
364 const struct intel_crtc_state *crtc_state)
366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
367 struct i915_audio_component *acomp = dev_priv->audio_component;
368 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
369 enum port port = encoder->port;
370 enum pipe pipe = crtc->pipe;
374 rate = acomp ? acomp->aud_sample_rate[port] : 0;
376 tmp = I915_READ(HSW_AUD_CFG(pipe));
377 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
378 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
379 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
380 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
382 n = audio_config_hdmi_get_n(crtc_state, rate);
384 DRM_DEBUG_KMS("using N %d\n", n);
386 tmp &= ~AUD_CONFIG_N_MASK;
387 tmp |= AUD_CONFIG_N(n);
388 tmp |= AUD_CONFIG_N_PROG_ENABLE;
390 DRM_DEBUG_KMS("using automatic N\n");
393 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
396 * Let's disable "Enable CTS or M Prog bit"
397 * and let HW calculate the value
399 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
400 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
401 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
402 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
406 hsw_audio_config_update(struct intel_encoder *encoder,
407 const struct intel_crtc_state *crtc_state)
409 if (intel_crtc_has_dp_encoder(crtc_state))
410 hsw_dp_audio_config_update(encoder, crtc_state);
412 hsw_hdmi_audio_config_update(encoder, crtc_state);
415 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
416 const struct intel_crtc_state *old_crtc_state,
417 const struct drm_connector_state *old_conn_state)
419 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
420 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
421 enum pipe pipe = crtc->pipe;
424 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
426 mutex_lock(&dev_priv->av_mutex);
428 /* Disable timestamps */
429 tmp = I915_READ(HSW_AUD_CFG(pipe));
430 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
431 tmp |= AUD_CONFIG_N_PROG_ENABLE;
432 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
433 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
434 if (intel_crtc_has_dp_encoder(old_crtc_state))
435 tmp |= AUD_CONFIG_N_VALUE_INDEX;
436 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
439 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
440 tmp &= ~AUDIO_ELD_VALID(pipe);
441 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
442 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
444 mutex_unlock(&dev_priv->av_mutex);
447 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
448 const struct intel_crtc_state *crtc_state,
449 const struct drm_connector_state *conn_state)
451 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
452 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
453 struct drm_connector *connector = conn_state->connector;
454 enum pipe pipe = crtc->pipe;
455 const u8 *eld = connector->eld;
459 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
460 pipe_name(pipe), drm_eld_size(eld));
462 mutex_lock(&dev_priv->av_mutex);
464 /* Enable audio presence detect, invalidate ELD */
465 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
466 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
467 tmp &= ~AUDIO_ELD_VALID(pipe);
468 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
471 * FIXME: We're supposed to wait for vblank here, but we have vblanks
472 * disabled during the mode set. The proper fix would be to push the
473 * rest of the setup into a vblank work item, queued here, but the
474 * infrastructure is not there yet.
477 /* Reset ELD write address */
478 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
479 tmp &= ~IBX_ELD_ADDRESS_MASK;
480 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
482 /* Up to 84 bytes of hw ELD buffer */
483 len = min(drm_eld_size(eld), 84);
484 for (i = 0; i < len / 4; i++)
485 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));
488 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
489 tmp |= AUDIO_ELD_VALID(pipe);
490 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
492 /* Enable timestamps */
493 hsw_audio_config_update(encoder, crtc_state);
495 mutex_unlock(&dev_priv->av_mutex);
498 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
499 const struct intel_crtc_state *old_crtc_state,
500 const struct drm_connector_state *old_conn_state)
502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
503 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
504 enum pipe pipe = crtc->pipe;
505 enum port port = encoder->port;
507 i915_reg_t aud_config, aud_cntrl_st2;
509 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
510 port_name(port), pipe_name(pipe));
512 if (WARN_ON(port == PORT_A))
515 if (HAS_PCH_IBX(dev_priv)) {
516 aud_config = IBX_AUD_CFG(pipe);
517 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
518 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
519 aud_config = VLV_AUD_CFG(pipe);
520 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
522 aud_config = CPT_AUD_CFG(pipe);
523 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
526 /* Disable timestamps */
527 tmp = I915_READ(aud_config);
528 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
529 tmp |= AUD_CONFIG_N_PROG_ENABLE;
530 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
531 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
532 if (intel_crtc_has_dp_encoder(old_crtc_state))
533 tmp |= AUD_CONFIG_N_VALUE_INDEX;
534 I915_WRITE(aud_config, tmp);
536 eldv = IBX_ELD_VALID(port);
539 tmp = I915_READ(aud_cntrl_st2);
541 I915_WRITE(aud_cntrl_st2, tmp);
544 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
545 const struct intel_crtc_state *crtc_state,
546 const struct drm_connector_state *conn_state)
548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
550 struct drm_connector *connector = conn_state->connector;
551 enum pipe pipe = crtc->pipe;
552 enum port port = encoder->port;
553 const u8 *eld = connector->eld;
556 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
558 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
559 port_name(port), pipe_name(pipe), drm_eld_size(eld));
561 if (WARN_ON(port == PORT_A))
565 * FIXME: We're supposed to wait for vblank here, but we have vblanks
566 * disabled during the mode set. The proper fix would be to push the
567 * rest of the setup into a vblank work item, queued here, but the
568 * infrastructure is not there yet.
571 if (HAS_PCH_IBX(dev_priv)) {
572 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
573 aud_config = IBX_AUD_CFG(pipe);
574 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
575 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
576 } else if (IS_VALLEYVIEW(dev_priv) ||
577 IS_CHERRYVIEW(dev_priv)) {
578 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
579 aud_config = VLV_AUD_CFG(pipe);
580 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
581 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
583 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
584 aud_config = CPT_AUD_CFG(pipe);
585 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
586 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
589 eldv = IBX_ELD_VALID(port);
592 tmp = I915_READ(aud_cntrl_st2);
594 I915_WRITE(aud_cntrl_st2, tmp);
596 /* Reset ELD write address */
597 tmp = I915_READ(aud_cntl_st);
598 tmp &= ~IBX_ELD_ADDRESS_MASK;
599 I915_WRITE(aud_cntl_st, tmp);
601 /* Up to 84 bytes of hw ELD buffer */
602 len = min(drm_eld_size(eld), 84);
603 for (i = 0; i < len / 4; i++)
604 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
607 tmp = I915_READ(aud_cntrl_st2);
609 I915_WRITE(aud_cntrl_st2, tmp);
611 /* Enable timestamps */
612 tmp = I915_READ(aud_config);
613 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
614 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
615 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
616 if (intel_crtc_has_dp_encoder(crtc_state))
617 tmp |= AUD_CONFIG_N_VALUE_INDEX;
619 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
620 I915_WRITE(aud_config, tmp);
624 * intel_audio_codec_enable - Enable the audio codec for HD audio
625 * @encoder: encoder on which to enable audio
626 * @crtc_state: pointer to the current crtc state.
627 * @conn_state: pointer to the current connector state.
629 * The enable sequences may only be performed after enabling the transcoder and
630 * port, and after completed link training.
632 void intel_audio_codec_enable(struct intel_encoder *encoder,
633 const struct intel_crtc_state *crtc_state,
634 const struct drm_connector_state *conn_state)
636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
637 struct i915_audio_component *acomp = dev_priv->audio_component;
638 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
639 struct drm_connector *connector = conn_state->connector;
640 const struct drm_display_mode *adjusted_mode =
641 &crtc_state->base.adjusted_mode;
642 enum port port = encoder->port;
643 enum pipe pipe = crtc->pipe;
645 if (!connector->eld[0])
648 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
651 connector->encoder->base.id,
652 connector->encoder->name);
654 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
656 if (dev_priv->display.audio_codec_enable)
657 dev_priv->display.audio_codec_enable(encoder,
661 mutex_lock(&dev_priv->av_mutex);
662 encoder->audio_connector = connector;
664 /* referred in audio callbacks */
665 dev_priv->av_enc_map[pipe] = encoder;
666 mutex_unlock(&dev_priv->av_mutex);
668 if (acomp && acomp->base.audio_ops &&
669 acomp->base.audio_ops->pin_eld_notify) {
670 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
671 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
673 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
674 (int) port, (int) pipe);
677 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
678 crtc_state->port_clock,
679 intel_crtc_has_dp_encoder(crtc_state));
683 * intel_audio_codec_disable - Disable the audio codec for HD audio
684 * @encoder: encoder on which to disable audio
685 * @old_crtc_state: pointer to the old crtc state.
686 * @old_conn_state: pointer to the old connector state.
688 * The disable sequences must be performed before disabling the transcoder or
691 void intel_audio_codec_disable(struct intel_encoder *encoder,
692 const struct intel_crtc_state *old_crtc_state,
693 const struct drm_connector_state *old_conn_state)
695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
696 struct i915_audio_component *acomp = dev_priv->audio_component;
697 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
698 enum port port = encoder->port;
699 enum pipe pipe = crtc->pipe;
701 if (dev_priv->display.audio_codec_disable)
702 dev_priv->display.audio_codec_disable(encoder,
706 mutex_lock(&dev_priv->av_mutex);
707 encoder->audio_connector = NULL;
708 dev_priv->av_enc_map[pipe] = NULL;
709 mutex_unlock(&dev_priv->av_mutex);
711 if (acomp && acomp->base.audio_ops &&
712 acomp->base.audio_ops->pin_eld_notify) {
713 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
714 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
716 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
717 (int) port, (int) pipe);
720 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
724 * intel_init_audio_hooks - Set up chip specific audio hooks
725 * @dev_priv: device private
727 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
729 if (IS_G4X(dev_priv)) {
730 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
731 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
732 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
733 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
734 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
735 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
736 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
737 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
738 } else if (HAS_PCH_SPLIT(dev_priv)) {
739 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
740 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
744 static void i915_audio_component_get_power(struct device *kdev)
746 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
749 static void i915_audio_component_put_power(struct device *kdev)
751 intel_display_power_put_unchecked(kdev_to_i915(kdev),
755 static void i915_audio_component_codec_wake_override(struct device *kdev,
758 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
761 if (!IS_GEN(dev_priv, 9))
764 i915_audio_component_get_power(kdev);
767 * Enable/disable generating the codec wake signal, overriding the
768 * internal logic to generate the codec wake to controller.
770 tmp = I915_READ(HSW_AUD_CHICKENBIT);
771 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
772 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
773 usleep_range(1000, 1500);
776 tmp = I915_READ(HSW_AUD_CHICKENBIT);
777 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
778 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
779 usleep_range(1000, 1500);
782 i915_audio_component_put_power(kdev);
785 /* Get CDCLK in kHz */
786 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
788 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
790 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
793 return dev_priv->cdclk.hw.cdclk;
797 * get the intel_encoder according to the parameter port and pipe
798 * intel_encoder is saved by the index of pipe
799 * MST & (pipe >= 0): return the av_enc_map[pipe],
800 * when port is matched
801 * MST & (pipe < 0): this is invalid
802 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
803 * will get the right intel_encoder with port matched
804 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
806 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
809 struct intel_encoder *encoder;
813 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
816 encoder = dev_priv->av_enc_map[pipe];
818 * when bootup, audio driver may not know it is
819 * MST or not. So it will poll all the port & pipe
822 if (encoder != NULL && encoder->port == port &&
823 encoder->type == INTEL_OUTPUT_DP_MST)
831 for_each_pipe(dev_priv, pipe) {
832 encoder = dev_priv->av_enc_map[pipe];
836 if (encoder->type == INTEL_OUTPUT_DP_MST)
839 if (port == encoder->port)
846 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
849 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
850 struct i915_audio_component *acomp = dev_priv->audio_component;
851 struct intel_encoder *encoder;
852 struct intel_crtc *crtc;
855 if (!HAS_DDI(dev_priv))
858 i915_audio_component_get_power(kdev);
859 mutex_lock(&dev_priv->av_mutex);
861 /* 1. get the pipe */
862 encoder = get_saved_enc(dev_priv, port, pipe);
863 if (!encoder || !encoder->base.crtc) {
864 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
869 crtc = to_intel_crtc(encoder->base.crtc);
871 /* port must be valid now, otherwise the pipe will be invalid */
872 acomp->aud_sample_rate[port] = rate;
874 hsw_audio_config_update(encoder, crtc->config);
877 mutex_unlock(&dev_priv->av_mutex);
878 i915_audio_component_put_power(kdev);
882 static int i915_audio_component_get_eld(struct device *kdev, int port,
883 int pipe, bool *enabled,
884 unsigned char *buf, int max_bytes)
886 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
887 struct intel_encoder *intel_encoder;
891 mutex_lock(&dev_priv->av_mutex);
893 intel_encoder = get_saved_enc(dev_priv, port, pipe);
894 if (!intel_encoder) {
895 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
896 mutex_unlock(&dev_priv->av_mutex);
901 *enabled = intel_encoder->audio_connector != NULL;
903 eld = intel_encoder->audio_connector->eld;
904 ret = drm_eld_size(eld);
905 memcpy(buf, eld, min(max_bytes, ret));
908 mutex_unlock(&dev_priv->av_mutex);
912 static const struct drm_audio_component_ops i915_audio_component_ops = {
913 .owner = THIS_MODULE,
914 .get_power = i915_audio_component_get_power,
915 .put_power = i915_audio_component_put_power,
916 .codec_wake_override = i915_audio_component_codec_wake_override,
917 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
918 .sync_audio_rate = i915_audio_component_sync_audio_rate,
919 .get_eld = i915_audio_component_get_eld,
922 static int i915_audio_component_bind(struct device *i915_kdev,
923 struct device *hda_kdev, void *data)
925 struct i915_audio_component *acomp = data;
926 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
929 if (WARN_ON(acomp->base.ops || acomp->base.dev))
932 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS)))
935 drm_modeset_lock_all(&dev_priv->drm);
936 acomp->base.ops = &i915_audio_component_ops;
937 acomp->base.dev = i915_kdev;
938 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
939 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
940 acomp->aud_sample_rate[i] = 0;
941 dev_priv->audio_component = acomp;
942 drm_modeset_unlock_all(&dev_priv->drm);
947 static void i915_audio_component_unbind(struct device *i915_kdev,
948 struct device *hda_kdev, void *data)
950 struct i915_audio_component *acomp = data;
951 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
953 drm_modeset_lock_all(&dev_priv->drm);
954 acomp->base.ops = NULL;
955 acomp->base.dev = NULL;
956 dev_priv->audio_component = NULL;
957 drm_modeset_unlock_all(&dev_priv->drm);
959 device_link_remove(hda_kdev, i915_kdev);
962 static const struct component_ops i915_audio_component_bind_ops = {
963 .bind = i915_audio_component_bind,
964 .unbind = i915_audio_component_unbind,
968 * i915_audio_component_init - initialize and register the audio component
969 * @dev_priv: i915 device instance
971 * This will register with the component framework a child component which
972 * will bind dynamically to the snd_hda_intel driver's corresponding master
973 * component when the latter is registered. During binding the child
974 * initializes an instance of struct i915_audio_component which it receives
975 * from the master. The master can then start to use the interface defined by
976 * this struct. Each side can break the binding at any point by deregistering
977 * its own component after which each side's component unbind callback is
980 * We ignore any error during registration and continue with reduced
981 * functionality (i.e. without HDMI audio).
983 void i915_audio_component_init(struct drm_i915_private *dev_priv)
987 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
989 DRM_ERROR("failed to add audio component (%d)\n", ret);
990 /* continue with reduced functionality */
994 dev_priv->audio_component_registered = true;
998 * i915_audio_component_cleanup - deregister the audio component
999 * @dev_priv: i915 device instance
1001 * Deregisters the audio component, breaking any existing binding to the
1002 * corresponding snd_hda_intel driver's master component.
1004 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1006 if (!dev_priv->audio_component_registered)
1009 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1010 dev_priv->audio_component_registered = false;
1014 * intel_audio_init() - Initialize the audio driver either using
1015 * component framework or using lpe audio bridge
1016 * @dev_priv: the i915 drm device private data
1019 void intel_audio_init(struct drm_i915_private *dev_priv)
1021 if (intel_lpe_audio_init(dev_priv) < 0)
1022 i915_audio_component_init(dev_priv);
1026 * intel_audio_deinit() - deinitialize the audio driver
1027 * @dev_priv: the i915 drm device private data
1030 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1032 if ((dev_priv)->lpe_audio.platdev != NULL)
1033 intel_lpe_audio_teardown(dev_priv);
1035 i915_audio_component_cleanup(dev_priv);