2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/component.h>
25 #include <linux/kernel.h>
27 #include <drm/drm_edid.h>
28 #include <drm/i915_component.h>
29 #include <drm/intel_lpe_audio.h>
32 #include "intel_audio.h"
33 #include "intel_drv.h"
36 * DOC: High Definition Audio over HDMI and Display Port
38 * The graphics and audio drivers together support High Definition Audio over
39 * HDMI and Display Port. The audio programming sequences are divided into audio
40 * codec and controller enable and disable sequences. The graphics driver
41 * handles the audio codec sequences, while the audio driver handles the audio
42 * controller sequences.
44 * The disable sequences must be performed before disabling the transcoder or
45 * port. The enable sequences may only be performed after enabling the
46 * transcoder and port, and after completed link training. Therefore the audio
47 * enable/disable sequences are part of the modeset sequence.
49 * The codec and controller sequences could be done either parallel or serial,
50 * but generally the ELDV/PD change in the codec sequence indicates to the audio
51 * driver that the controller sequence should start. Indeed, most of the
52 * co-operation between the graphics and audio drivers is handled via audio
53 * related registers. (The notable exception is the power management, not
56 * The struct &i915_audio_component is used to interact between the graphics
57 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
58 * defined in graphics driver and called in audio driver. The
59 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
63 #define LC_810M 810000
64 #define LC_540M 540000
65 #define LC_270M 270000
66 #define LC_162M 162000
75 /* Values according to DP 1.4 Table 2-104 */
76 static const struct dp_aud_n_m dp_aud_n_m[] = {
77 { 32000, LC_162M, 1024, 10125 },
78 { 44100, LC_162M, 784, 5625 },
79 { 48000, LC_162M, 512, 3375 },
80 { 64000, LC_162M, 2048, 10125 },
81 { 88200, LC_162M, 1568, 5625 },
82 { 96000, LC_162M, 1024, 3375 },
83 { 128000, LC_162M, 4096, 10125 },
84 { 176400, LC_162M, 3136, 5625 },
85 { 192000, LC_162M, 2048, 3375 },
86 { 32000, LC_270M, 1024, 16875 },
87 { 44100, LC_270M, 784, 9375 },
88 { 48000, LC_270M, 512, 5625 },
89 { 64000, LC_270M, 2048, 16875 },
90 { 88200, LC_270M, 1568, 9375 },
91 { 96000, LC_270M, 1024, 5625 },
92 { 128000, LC_270M, 4096, 16875 },
93 { 176400, LC_270M, 3136, 9375 },
94 { 192000, LC_270M, 2048, 5625 },
95 { 32000, LC_540M, 1024, 33750 },
96 { 44100, LC_540M, 784, 18750 },
97 { 48000, LC_540M, 512, 11250 },
98 { 64000, LC_540M, 2048, 33750 },
99 { 88200, LC_540M, 1568, 18750 },
100 { 96000, LC_540M, 1024, 11250 },
101 { 128000, LC_540M, 4096, 33750 },
102 { 176400, LC_540M, 3136, 18750 },
103 { 192000, LC_540M, 2048, 11250 },
104 { 32000, LC_810M, 1024, 50625 },
105 { 44100, LC_810M, 784, 28125 },
106 { 48000, LC_810M, 512, 16875 },
107 { 64000, LC_810M, 2048, 50625 },
108 { 88200, LC_810M, 1568, 28125 },
109 { 96000, LC_810M, 1024, 16875 },
110 { 128000, LC_810M, 4096, 50625 },
111 { 176400, LC_810M, 3136, 28125 },
112 { 192000, LC_810M, 2048, 16875 },
115 static const struct dp_aud_n_m *
116 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
120 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
121 if (rate == dp_aud_n_m[i].sample_rate &&
122 crtc_state->port_clock == dp_aud_n_m[i].clock)
123 return &dp_aud_n_m[i];
129 static const struct {
132 } hdmi_audio_clock[] = {
133 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
134 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
135 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
136 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
137 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
138 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
139 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
140 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
141 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
142 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
145 /* HDMI N/CTS table */
146 #define TMDS_297M 297000
147 #define TMDS_296M 296703
148 #define TMDS_594M 594000
149 #define TMDS_593M 593407
151 static const struct {
156 } hdmi_aud_ncts[] = {
157 { 32000, TMDS_296M, 5824, 421875 },
158 { 32000, TMDS_297M, 3072, 222750 },
159 { 32000, TMDS_593M, 5824, 843750 },
160 { 32000, TMDS_594M, 3072, 445500 },
161 { 44100, TMDS_296M, 4459, 234375 },
162 { 44100, TMDS_297M, 4704, 247500 },
163 { 44100, TMDS_593M, 8918, 937500 },
164 { 44100, TMDS_594M, 9408, 990000 },
165 { 88200, TMDS_296M, 8918, 234375 },
166 { 88200, TMDS_297M, 9408, 247500 },
167 { 88200, TMDS_593M, 17836, 937500 },
168 { 88200, TMDS_594M, 18816, 990000 },
169 { 176400, TMDS_296M, 17836, 234375 },
170 { 176400, TMDS_297M, 18816, 247500 },
171 { 176400, TMDS_593M, 35672, 937500 },
172 { 176400, TMDS_594M, 37632, 990000 },
173 { 48000, TMDS_296M, 5824, 281250 },
174 { 48000, TMDS_297M, 5120, 247500 },
175 { 48000, TMDS_593M, 5824, 562500 },
176 { 48000, TMDS_594M, 6144, 594000 },
177 { 96000, TMDS_296M, 11648, 281250 },
178 { 96000, TMDS_297M, 10240, 247500 },
179 { 96000, TMDS_593M, 11648, 562500 },
180 { 96000, TMDS_594M, 12288, 594000 },
181 { 192000, TMDS_296M, 23296, 281250 },
182 { 192000, TMDS_297M, 20480, 247500 },
183 { 192000, TMDS_593M, 23296, 562500 },
184 { 192000, TMDS_594M, 24576, 594000 },
187 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
188 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
190 const struct drm_display_mode *adjusted_mode =
191 &crtc_state->base.adjusted_mode;
194 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
195 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
199 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
200 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
201 adjusted_mode->crtc_clock);
205 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
206 hdmi_audio_clock[i].clock,
207 hdmi_audio_clock[i].config);
209 return hdmi_audio_clock[i].config;
212 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
215 const struct drm_display_mode *adjusted_mode =
216 &crtc_state->base.adjusted_mode;
219 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
220 if (rate == hdmi_aud_ncts[i].sample_rate &&
221 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
222 return hdmi_aud_ncts[i].n;
228 static bool intel_eld_uptodate(struct drm_connector *connector,
229 i915_reg_t reg_eldv, u32 bits_eldv,
230 i915_reg_t reg_elda, u32 bits_elda,
233 struct drm_i915_private *dev_priv = to_i915(connector->dev);
234 const u8 *eld = connector->eld;
238 tmp = I915_READ(reg_eldv);
244 tmp = I915_READ(reg_elda);
246 I915_WRITE(reg_elda, tmp);
248 for (i = 0; i < drm_eld_size(eld) / 4; i++)
249 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
255 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
256 const struct intel_crtc_state *old_crtc_state,
257 const struct drm_connector_state *old_conn_state)
259 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
262 DRM_DEBUG_KMS("Disable audio codec\n");
264 tmp = I915_READ(G4X_AUD_VID_DID);
265 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
266 eldv = G4X_ELDV_DEVCL_DEVBLC;
268 eldv = G4X_ELDV_DEVCTG;
271 tmp = I915_READ(G4X_AUD_CNTL_ST);
273 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
276 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
277 const struct intel_crtc_state *crtc_state,
278 const struct drm_connector_state *conn_state)
280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
281 struct drm_connector *connector = conn_state->connector;
282 const u8 *eld = connector->eld;
287 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
289 tmp = I915_READ(G4X_AUD_VID_DID);
290 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
291 eldv = G4X_ELDV_DEVCL_DEVBLC;
293 eldv = G4X_ELDV_DEVCTG;
295 if (intel_eld_uptodate(connector,
296 G4X_AUD_CNTL_ST, eldv,
297 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
301 tmp = I915_READ(G4X_AUD_CNTL_ST);
302 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
303 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
304 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
306 len = min(drm_eld_size(eld) / 4, len);
307 DRM_DEBUG_DRIVER("ELD size %d\n", len);
308 for (i = 0; i < len; i++)
309 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
311 tmp = I915_READ(G4X_AUD_CNTL_ST);
313 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
317 hsw_dp_audio_config_update(struct intel_encoder *encoder,
318 const struct intel_crtc_state *crtc_state)
320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
321 struct i915_audio_component *acomp = dev_priv->audio_component;
322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
323 enum port port = encoder->port;
324 enum pipe pipe = crtc->pipe;
325 const struct dp_aud_n_m *nm;
329 rate = acomp ? acomp->aud_sample_rate[port] : 0;
330 nm = audio_config_dp_get_n_m(crtc_state, rate);
332 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
334 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
336 tmp = I915_READ(HSW_AUD_CFG(pipe));
337 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
338 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
339 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
340 tmp |= AUD_CONFIG_N_VALUE_INDEX;
343 tmp &= ~AUD_CONFIG_N_MASK;
344 tmp |= AUD_CONFIG_N(nm->n);
345 tmp |= AUD_CONFIG_N_PROG_ENABLE;
348 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
350 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
351 tmp &= ~AUD_CONFIG_M_MASK;
352 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
353 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
357 tmp |= AUD_M_CTS_M_VALUE_INDEX;
358 tmp |= AUD_M_CTS_M_PROG_ENABLE;
361 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
365 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
366 const struct intel_crtc_state *crtc_state)
368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
369 struct i915_audio_component *acomp = dev_priv->audio_component;
370 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
371 enum port port = encoder->port;
372 enum pipe pipe = crtc->pipe;
376 rate = acomp ? acomp->aud_sample_rate[port] : 0;
378 tmp = I915_READ(HSW_AUD_CFG(pipe));
379 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
380 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
381 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
382 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
384 n = audio_config_hdmi_get_n(crtc_state, rate);
386 DRM_DEBUG_KMS("using N %d\n", n);
388 tmp &= ~AUD_CONFIG_N_MASK;
389 tmp |= AUD_CONFIG_N(n);
390 tmp |= AUD_CONFIG_N_PROG_ENABLE;
392 DRM_DEBUG_KMS("using automatic N\n");
395 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
398 * Let's disable "Enable CTS or M Prog bit"
399 * and let HW calculate the value
401 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
402 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
403 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
404 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
408 hsw_audio_config_update(struct intel_encoder *encoder,
409 const struct intel_crtc_state *crtc_state)
411 if (intel_crtc_has_dp_encoder(crtc_state))
412 hsw_dp_audio_config_update(encoder, crtc_state);
414 hsw_hdmi_audio_config_update(encoder, crtc_state);
417 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
418 const struct intel_crtc_state *old_crtc_state,
419 const struct drm_connector_state *old_conn_state)
421 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
422 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
423 enum pipe pipe = crtc->pipe;
426 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
428 mutex_lock(&dev_priv->av_mutex);
430 /* Disable timestamps */
431 tmp = I915_READ(HSW_AUD_CFG(pipe));
432 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
433 tmp |= AUD_CONFIG_N_PROG_ENABLE;
434 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
435 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
436 if (intel_crtc_has_dp_encoder(old_crtc_state))
437 tmp |= AUD_CONFIG_N_VALUE_INDEX;
438 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
441 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
442 tmp &= ~AUDIO_ELD_VALID(pipe);
443 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
444 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
446 mutex_unlock(&dev_priv->av_mutex);
449 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
450 const struct intel_crtc_state *crtc_state,
451 const struct drm_connector_state *conn_state)
453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
454 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
455 struct drm_connector *connector = conn_state->connector;
456 enum pipe pipe = crtc->pipe;
457 const u8 *eld = connector->eld;
461 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
462 pipe_name(pipe), drm_eld_size(eld));
464 mutex_lock(&dev_priv->av_mutex);
466 /* Enable audio presence detect, invalidate ELD */
467 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
468 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
469 tmp &= ~AUDIO_ELD_VALID(pipe);
470 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
473 * FIXME: We're supposed to wait for vblank here, but we have vblanks
474 * disabled during the mode set. The proper fix would be to push the
475 * rest of the setup into a vblank work item, queued here, but the
476 * infrastructure is not there yet.
479 /* Reset ELD write address */
480 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
481 tmp &= ~IBX_ELD_ADDRESS_MASK;
482 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
484 /* Up to 84 bytes of hw ELD buffer */
485 len = min(drm_eld_size(eld), 84);
486 for (i = 0; i < len / 4; i++)
487 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));
490 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
491 tmp |= AUDIO_ELD_VALID(pipe);
492 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
494 /* Enable timestamps */
495 hsw_audio_config_update(encoder, crtc_state);
497 mutex_unlock(&dev_priv->av_mutex);
500 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
501 const struct intel_crtc_state *old_crtc_state,
502 const struct drm_connector_state *old_conn_state)
504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
505 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
506 enum pipe pipe = crtc->pipe;
507 enum port port = encoder->port;
509 i915_reg_t aud_config, aud_cntrl_st2;
511 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
512 port_name(port), pipe_name(pipe));
514 if (WARN_ON(port == PORT_A))
517 if (HAS_PCH_IBX(dev_priv)) {
518 aud_config = IBX_AUD_CFG(pipe);
519 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
520 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
521 aud_config = VLV_AUD_CFG(pipe);
522 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
524 aud_config = CPT_AUD_CFG(pipe);
525 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
528 /* Disable timestamps */
529 tmp = I915_READ(aud_config);
530 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
531 tmp |= AUD_CONFIG_N_PROG_ENABLE;
532 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
533 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
534 if (intel_crtc_has_dp_encoder(old_crtc_state))
535 tmp |= AUD_CONFIG_N_VALUE_INDEX;
536 I915_WRITE(aud_config, tmp);
538 eldv = IBX_ELD_VALID(port);
541 tmp = I915_READ(aud_cntrl_st2);
543 I915_WRITE(aud_cntrl_st2, tmp);
546 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
547 const struct intel_crtc_state *crtc_state,
548 const struct drm_connector_state *conn_state)
550 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
551 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
552 struct drm_connector *connector = conn_state->connector;
553 enum pipe pipe = crtc->pipe;
554 enum port port = encoder->port;
555 const u8 *eld = connector->eld;
558 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
560 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
561 port_name(port), pipe_name(pipe), drm_eld_size(eld));
563 if (WARN_ON(port == PORT_A))
567 * FIXME: We're supposed to wait for vblank here, but we have vblanks
568 * disabled during the mode set. The proper fix would be to push the
569 * rest of the setup into a vblank work item, queued here, but the
570 * infrastructure is not there yet.
573 if (HAS_PCH_IBX(dev_priv)) {
574 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
575 aud_config = IBX_AUD_CFG(pipe);
576 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
577 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
578 } else if (IS_VALLEYVIEW(dev_priv) ||
579 IS_CHERRYVIEW(dev_priv)) {
580 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
581 aud_config = VLV_AUD_CFG(pipe);
582 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
583 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
585 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
586 aud_config = CPT_AUD_CFG(pipe);
587 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
588 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
591 eldv = IBX_ELD_VALID(port);
594 tmp = I915_READ(aud_cntrl_st2);
596 I915_WRITE(aud_cntrl_st2, tmp);
598 /* Reset ELD write address */
599 tmp = I915_READ(aud_cntl_st);
600 tmp &= ~IBX_ELD_ADDRESS_MASK;
601 I915_WRITE(aud_cntl_st, tmp);
603 /* Up to 84 bytes of hw ELD buffer */
604 len = min(drm_eld_size(eld), 84);
605 for (i = 0; i < len / 4; i++)
606 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
609 tmp = I915_READ(aud_cntrl_st2);
611 I915_WRITE(aud_cntrl_st2, tmp);
613 /* Enable timestamps */
614 tmp = I915_READ(aud_config);
615 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
616 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
617 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
618 if (intel_crtc_has_dp_encoder(crtc_state))
619 tmp |= AUD_CONFIG_N_VALUE_INDEX;
621 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
622 I915_WRITE(aud_config, tmp);
626 * intel_audio_codec_enable - Enable the audio codec for HD audio
627 * @encoder: encoder on which to enable audio
628 * @crtc_state: pointer to the current crtc state.
629 * @conn_state: pointer to the current connector state.
631 * The enable sequences may only be performed after enabling the transcoder and
632 * port, and after completed link training.
634 void intel_audio_codec_enable(struct intel_encoder *encoder,
635 const struct intel_crtc_state *crtc_state,
636 const struct drm_connector_state *conn_state)
638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
639 struct i915_audio_component *acomp = dev_priv->audio_component;
640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
641 struct drm_connector *connector = conn_state->connector;
642 const struct drm_display_mode *adjusted_mode =
643 &crtc_state->base.adjusted_mode;
644 enum port port = encoder->port;
645 enum pipe pipe = crtc->pipe;
647 if (!connector->eld[0])
650 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
653 connector->encoder->base.id,
654 connector->encoder->name);
656 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
658 if (dev_priv->display.audio_codec_enable)
659 dev_priv->display.audio_codec_enable(encoder,
663 mutex_lock(&dev_priv->av_mutex);
664 encoder->audio_connector = connector;
666 /* referred in audio callbacks */
667 dev_priv->av_enc_map[pipe] = encoder;
668 mutex_unlock(&dev_priv->av_mutex);
670 if (acomp && acomp->base.audio_ops &&
671 acomp->base.audio_ops->pin_eld_notify) {
672 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
673 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
675 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
676 (int) port, (int) pipe);
679 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
680 crtc_state->port_clock,
681 intel_crtc_has_dp_encoder(crtc_state));
685 * intel_audio_codec_disable - Disable the audio codec for HD audio
686 * @encoder: encoder on which to disable audio
687 * @old_crtc_state: pointer to the old crtc state.
688 * @old_conn_state: pointer to the old connector state.
690 * The disable sequences must be performed before disabling the transcoder or
693 void intel_audio_codec_disable(struct intel_encoder *encoder,
694 const struct intel_crtc_state *old_crtc_state,
695 const struct drm_connector_state *old_conn_state)
697 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
698 struct i915_audio_component *acomp = dev_priv->audio_component;
699 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
700 enum port port = encoder->port;
701 enum pipe pipe = crtc->pipe;
703 if (dev_priv->display.audio_codec_disable)
704 dev_priv->display.audio_codec_disable(encoder,
708 mutex_lock(&dev_priv->av_mutex);
709 encoder->audio_connector = NULL;
710 dev_priv->av_enc_map[pipe] = NULL;
711 mutex_unlock(&dev_priv->av_mutex);
713 if (acomp && acomp->base.audio_ops &&
714 acomp->base.audio_ops->pin_eld_notify) {
715 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
716 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
718 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
719 (int) port, (int) pipe);
722 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
726 * intel_init_audio_hooks - Set up chip specific audio hooks
727 * @dev_priv: device private
729 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
731 if (IS_G4X(dev_priv)) {
732 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
733 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
734 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
735 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
736 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
737 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
738 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
739 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
740 } else if (HAS_PCH_SPLIT(dev_priv)) {
741 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
742 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
746 static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
749 struct drm_modeset_acquire_ctx ctx;
750 struct drm_atomic_state *state;
753 drm_modeset_acquire_init(&ctx, 0);
754 state = drm_atomic_state_alloc(&dev_priv->drm);
758 state->acquire_ctx = &ctx;
761 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
762 to_intel_atomic_state(state)->cdclk.force_min_cdclk =
763 enable ? 2 * 96000 : 0;
766 * Protects dev_priv->cdclk.force_min_cdclk
767 * Need to lock this here in case we have no active pipes
768 * and thus wouldn't lock it during the commit otherwise.
770 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
773 ret = drm_atomic_commit(state);
775 if (ret == -EDEADLK) {
776 drm_atomic_state_clear(state);
777 drm_modeset_backoff(&ctx);
783 drm_atomic_state_put(state);
785 drm_modeset_drop_locks(&ctx);
786 drm_modeset_acquire_fini(&ctx);
789 static unsigned long i915_audio_component_get_power(struct device *kdev)
791 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
794 /* Catch potential impedance mismatches before they occur! */
795 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
797 ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
799 /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
800 if (dev_priv->audio_power_refcount++ == 0)
801 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
802 glk_force_audio_cdclk(dev_priv, true);
807 static void i915_audio_component_put_power(struct device *kdev,
808 unsigned long cookie)
810 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
812 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
813 if (--dev_priv->audio_power_refcount == 0)
814 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
815 glk_force_audio_cdclk(dev_priv, false);
817 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
820 static void i915_audio_component_codec_wake_override(struct device *kdev,
823 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
824 unsigned long cookie;
827 if (!IS_GEN(dev_priv, 9))
830 cookie = i915_audio_component_get_power(kdev);
833 * Enable/disable generating the codec wake signal, overriding the
834 * internal logic to generate the codec wake to controller.
836 tmp = I915_READ(HSW_AUD_CHICKENBIT);
837 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
838 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
839 usleep_range(1000, 1500);
842 tmp = I915_READ(HSW_AUD_CHICKENBIT);
843 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
844 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
845 usleep_range(1000, 1500);
848 i915_audio_component_put_power(kdev, cookie);
851 /* Get CDCLK in kHz */
852 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
854 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
856 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
859 return dev_priv->cdclk.hw.cdclk;
863 * get the intel_encoder according to the parameter port and pipe
864 * intel_encoder is saved by the index of pipe
865 * MST & (pipe >= 0): return the av_enc_map[pipe],
866 * when port is matched
867 * MST & (pipe < 0): this is invalid
868 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
869 * will get the right intel_encoder with port matched
870 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
872 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
875 struct intel_encoder *encoder;
879 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
882 encoder = dev_priv->av_enc_map[pipe];
884 * when bootup, audio driver may not know it is
885 * MST or not. So it will poll all the port & pipe
888 if (encoder != NULL && encoder->port == port &&
889 encoder->type == INTEL_OUTPUT_DP_MST)
897 for_each_pipe(dev_priv, pipe) {
898 encoder = dev_priv->av_enc_map[pipe];
902 if (encoder->type == INTEL_OUTPUT_DP_MST)
905 if (port == encoder->port)
912 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
915 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
916 struct i915_audio_component *acomp = dev_priv->audio_component;
917 struct intel_encoder *encoder;
918 struct intel_crtc *crtc;
919 unsigned long cookie;
922 if (!HAS_DDI(dev_priv))
925 cookie = i915_audio_component_get_power(kdev);
926 mutex_lock(&dev_priv->av_mutex);
928 /* 1. get the pipe */
929 encoder = get_saved_enc(dev_priv, port, pipe);
930 if (!encoder || !encoder->base.crtc) {
931 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
936 crtc = to_intel_crtc(encoder->base.crtc);
938 /* port must be valid now, otherwise the pipe will be invalid */
939 acomp->aud_sample_rate[port] = rate;
941 hsw_audio_config_update(encoder, crtc->config);
944 mutex_unlock(&dev_priv->av_mutex);
945 i915_audio_component_put_power(kdev, cookie);
949 static int i915_audio_component_get_eld(struct device *kdev, int port,
950 int pipe, bool *enabled,
951 unsigned char *buf, int max_bytes)
953 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
954 struct intel_encoder *intel_encoder;
958 mutex_lock(&dev_priv->av_mutex);
960 intel_encoder = get_saved_enc(dev_priv, port, pipe);
961 if (!intel_encoder) {
962 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
963 mutex_unlock(&dev_priv->av_mutex);
968 *enabled = intel_encoder->audio_connector != NULL;
970 eld = intel_encoder->audio_connector->eld;
971 ret = drm_eld_size(eld);
972 memcpy(buf, eld, min(max_bytes, ret));
975 mutex_unlock(&dev_priv->av_mutex);
979 static const struct drm_audio_component_ops i915_audio_component_ops = {
980 .owner = THIS_MODULE,
981 .get_power = i915_audio_component_get_power,
982 .put_power = i915_audio_component_put_power,
983 .codec_wake_override = i915_audio_component_codec_wake_override,
984 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
985 .sync_audio_rate = i915_audio_component_sync_audio_rate,
986 .get_eld = i915_audio_component_get_eld,
989 static int i915_audio_component_bind(struct device *i915_kdev,
990 struct device *hda_kdev, void *data)
992 struct i915_audio_component *acomp = data;
993 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
996 if (WARN_ON(acomp->base.ops || acomp->base.dev))
999 if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS)))
1002 drm_modeset_lock_all(&dev_priv->drm);
1003 acomp->base.ops = &i915_audio_component_ops;
1004 acomp->base.dev = i915_kdev;
1005 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1006 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1007 acomp->aud_sample_rate[i] = 0;
1008 dev_priv->audio_component = acomp;
1009 drm_modeset_unlock_all(&dev_priv->drm);
1014 static void i915_audio_component_unbind(struct device *i915_kdev,
1015 struct device *hda_kdev, void *data)
1017 struct i915_audio_component *acomp = data;
1018 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
1020 drm_modeset_lock_all(&dev_priv->drm);
1021 acomp->base.ops = NULL;
1022 acomp->base.dev = NULL;
1023 dev_priv->audio_component = NULL;
1024 drm_modeset_unlock_all(&dev_priv->drm);
1026 device_link_remove(hda_kdev, i915_kdev);
1029 static const struct component_ops i915_audio_component_bind_ops = {
1030 .bind = i915_audio_component_bind,
1031 .unbind = i915_audio_component_unbind,
1035 * i915_audio_component_init - initialize and register the audio component
1036 * @dev_priv: i915 device instance
1038 * This will register with the component framework a child component which
1039 * will bind dynamically to the snd_hda_intel driver's corresponding master
1040 * component when the latter is registered. During binding the child
1041 * initializes an instance of struct i915_audio_component which it receives
1042 * from the master. The master can then start to use the interface defined by
1043 * this struct. Each side can break the binding at any point by deregistering
1044 * its own component after which each side's component unbind callback is
1047 * We ignore any error during registration and continue with reduced
1048 * functionality (i.e. without HDMI audio).
1050 static void i915_audio_component_init(struct drm_i915_private *dev_priv)
1054 ret = component_add_typed(dev_priv->drm.dev,
1055 &i915_audio_component_bind_ops,
1056 I915_COMPONENT_AUDIO);
1058 DRM_ERROR("failed to add audio component (%d)\n", ret);
1059 /* continue with reduced functionality */
1063 dev_priv->audio_component_registered = true;
1067 * i915_audio_component_cleanup - deregister the audio component
1068 * @dev_priv: i915 device instance
1070 * Deregisters the audio component, breaking any existing binding to the
1071 * corresponding snd_hda_intel driver's master component.
1073 static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
1075 if (!dev_priv->audio_component_registered)
1078 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
1079 dev_priv->audio_component_registered = false;
1083 * intel_audio_init() - Initialize the audio driver either using
1084 * component framework or using lpe audio bridge
1085 * @dev_priv: the i915 drm device private data
1088 void intel_audio_init(struct drm_i915_private *dev_priv)
1090 if (intel_lpe_audio_init(dev_priv) < 0)
1091 i915_audio_component_init(dev_priv);
1095 * intel_audio_deinit() - deinitialize the audio driver
1096 * @dev_priv: the i915 drm device private data
1099 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1101 if ((dev_priv)->lpe_audio.platdev != NULL)
1102 intel_lpe_audio_teardown(dev_priv);
1104 i915_audio_component_cleanup(dev_priv);