drivers/gpu/drm/i915/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <madhav.chauhan@intel.com>
  25  *   Jani Nikula <jani.nikula@intel.com>
  26  */
  27
  28 #include <drm/drm_mipi_dsi.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include "intel_dsi.h"
  31
  32 static inline int header_credits_available(struct drm_i915_private *dev_priv,
  33                                            enum transcoder dsi_trans)
  34 {
  35         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  36                 >> FREE_HEADER_CREDIT_SHIFT;
  37 }
  38
  39 static inline int payload_credits_available(struct drm_i915_private *dev_priv,
  40                                             enum transcoder dsi_trans)
  41 {
  42         return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  43                 >> FREE_PLOAD_CREDIT_SHIFT;
  44 }
  45
  46 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
  47                                     enum transcoder dsi_trans)
  48 {
  49         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  50                         MAX_HEADER_CREDIT, 100))
  51                 DRM_ERROR("DSI header credits not released\n");
  52 }
  53
  54 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
  55                                      enum transcoder dsi_trans)
  56 {
  57         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  58                         MAX_PLOAD_CREDIT, 100))
  59                 DRM_ERROR("DSI payload credits not released\n");
  60 }
  61
  62 static enum transcoder dsi_port_to_transcoder(enum port port)
  63 {
  64         if (port == PORT_A)
  65                 return TRANSCODER_DSI_0;
  66         else
  67                 return TRANSCODER_DSI_1;
  68 }
  69
  70 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  71 {
  72         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  73         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  74         struct mipi_dsi_device *dsi;
  75         enum port port;
  76         enum transcoder dsi_trans;
  77         int ret;
  78
  79         /* wait for header/payload credits to be released */
  80         for_each_dsi_port(port, intel_dsi->ports) {
  81                 dsi_trans = dsi_port_to_transcoder(port);
  82                 wait_for_header_credits(dev_priv, dsi_trans);
  83                 wait_for_payload_credits(dev_priv, dsi_trans);
  84         }
  85
  86         /* send nop DCS command */
  87         for_each_dsi_port(port, intel_dsi->ports) {
  88                 dsi = intel_dsi->dsi_hosts[port]->device;
  89                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  90                 dsi->channel = 0;
  91                 ret = mipi_dsi_dcs_nop(dsi);
  92                 if (ret < 0)
  93                         DRM_ERROR("error sending DCS NOP command\n");
  94         }
  95
  96         /* wait for header credits to be released */
  97         for_each_dsi_port(port, intel_dsi->ports) {
  98                 dsi_trans = dsi_port_to_transcoder(port);
  99                 wait_for_header_credits(dev_priv, dsi_trans);
 100         }
 101
 102         /* wait for LP TX in progress bit to be cleared */
 103         for_each_dsi_port(port, intel_dsi->ports) {
 104                 dsi_trans = dsi_port_to_transcoder(port);
 105                 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
 106                                   LPTX_IN_PROGRESS), 20))
 107                         DRM_ERROR("LPTX bit not cleared\n");
 108         }
 109 }
 110
 111 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
 112                                u32 len)
 113 {
 114         struct intel_dsi *intel_dsi = host->intel_dsi;
 115         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 116         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 117         int free_credits;
 118         int i, j;
 119
 120         for (i = 0; i < len; i += 4) {
 121                 u32 tmp = 0;
 122
 123                 free_credits = payload_credits_available(dev_priv, dsi_trans);
 124                 if (free_credits < 1) {
 125                         DRM_ERROR("Payload credit not available\n");
 126                         return false;
 127                 }
 128
 129                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 130                         tmp |= *data++ << 8 * j;
 131
 132                 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
 133         }
 134
 135         return true;
 136 }
 137
 138 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 139                             struct mipi_dsi_packet pkt, bool enable_lpdt)
 140 {
 141         struct intel_dsi *intel_dsi = host->intel_dsi;
 142         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 143         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 144         u32 tmp;
 145         int free_credits;
 146
 147         /* check if header credit available */
 148         free_credits = header_credits_available(dev_priv, dsi_trans);
 149         if (free_credits < 1) {
 150                 DRM_ERROR("send pkt header failed, not enough hdr credits\n");
 151                 return -1;
 152         }
 153
 154         tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
 155
 156         if (pkt.payload)
 157                 tmp |= PAYLOAD_PRESENT;
 158         else
 159                 tmp &= ~PAYLOAD_PRESENT;
 160
 161         tmp &= ~VBLANK_FENCE;
 162
 163         if (enable_lpdt)
 164                 tmp |= LP_DATA_TRANSFER;
 165
 166         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 167         tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
 168         tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
 169         tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
 170         tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
 171         I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
 172
 173         return 0;
 174 }
 175
 176 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 177                               struct mipi_dsi_packet pkt)
 178 {
 179         /* payload queue can accept *256 bytes*, check limit */
 180         if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
 181                 DRM_ERROR("payload size exceeds max queue limit\n");
 182                 return -1;
 183         }
 184
 185         /* load data into command payload queue */
 186         if (!add_payld_to_queue(host, pkt.payload,
 187                                 pkt.payload_length)) {
 188                 DRM_ERROR("adding payload to queue failed\n");
 189                 return -1;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 196 {
 197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 198         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 199         enum port port;
 200         u32 tmp;
 201         int lane;
 202
 203         for_each_dsi_port(port, intel_dsi->ports) {
 204
 205                 /*
 206                  * Program voltage swing and pre-emphasis level values as per
 207                  * table in BSPEC under DDI buffer programing
 208                  */
 209                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 210                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 211                 tmp |= SCALING_MODE_SEL(0x2);
 212                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 213                 tmp |= RTERM_SELECT(0x6);
 214                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 215
 216                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 217                 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 218                 tmp |= SCALING_MODE_SEL(0x2);
 219                 tmp |= TAP2_DISABLE | TAP3_DISABLE;
 220                 tmp |= RTERM_SELECT(0x6);
 221                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 222
 223                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
 224                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 225                          RCOMP_SCALAR_MASK);
 226                 tmp |= SWING_SEL_UPPER(0x2);
 227                 tmp |= SWING_SEL_LOWER(0x2);
 228                 tmp |= RCOMP_SCALAR(0x98);
 229                 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
 230
 231                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
 232                 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 233                          RCOMP_SCALAR_MASK);
 234                 tmp |= SWING_SEL_UPPER(0x2);
 235                 tmp |= SWING_SEL_LOWER(0x2);
 236                 tmp |= RCOMP_SCALAR(0x98);
 237                 I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
 238
 239                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
 240                 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 241                          CURSOR_COEFF_MASK);
 242                 tmp |= POST_CURSOR_1(0x0);
 243                 tmp |= POST_CURSOR_2(0x0);
 244                 tmp |= CURSOR_COEFF(0x3f);
 245                 I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
 246
 247                 for (lane = 0; lane <= 3; lane++) {
 248                         /* Bspec: must not use GRP register for write */
 249                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
 250                         tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 251                                  CURSOR_COEFF_MASK);
 252                         tmp |= POST_CURSOR_1(0x0);
 253                         tmp |= POST_CURSOR_2(0x0);
 254                         tmp |= CURSOR_COEFF(0x3f);
 255                         I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
 256                 }
 257         }
 258 }
 259
 260 static void configure_dual_link_mode(struct intel_encoder *encoder,
 261                                      const struct intel_crtc_state *pipe_config)
 262 {
 263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 264         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 265         u32 dss_ctl1;
 266
 267         dss_ctl1 = I915_READ(DSS_CTL1);
 268         dss_ctl1 |= SPLITTER_ENABLE;
 269         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 270         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 271
 272         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 273                 const struct drm_display_mode *adjusted_mode =
 274                                         &pipe_config->base.adjusted_mode;
 275                 u32 dss_ctl2;
 276                 u16 hactive = adjusted_mode->crtc_hdisplay;
 277                 u16 dl_buffer_depth;
 278
 279                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 280                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 281
 282                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 283                         DRM_ERROR("DL buffer depth exceed max value\n");
 284
 285                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 286                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 287                 dss_ctl2 = I915_READ(DSS_CTL2);
 288                 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
 289                 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 290                 I915_WRITE(DSS_CTL2, dss_ctl2);
 291         } else {
 292                 /* Interleave */
 293                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 294         }
 295
 296         I915_WRITE(DSS_CTL1, dss_ctl1);
 297 }
 298
 299 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 300 {
 301         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 302         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 303         enum port port;
 304         u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 305         u32 afe_clk_khz; /* 8X Clock */
 306         u32 esc_clk_div_m;
 307
 308         afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
 309                                         intel_dsi->lane_count);
 310
 311         esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 312
 313         for_each_dsi_port(port, intel_dsi->ports) {
 314                 I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
 315                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 316                 POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
 317         }
 318
 319         for_each_dsi_port(port, intel_dsi->ports) {
 320                 I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
 321                            esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 322                 POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
 323         }
 324 }
 325
 326 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 327                                      struct intel_dsi *intel_dsi)
 328 {
 329         enum port port;
 330
 331         for_each_dsi_port(port, intel_dsi->ports) {
 332                 WARN_ON(intel_dsi->io_wakeref[port]);
 333                 intel_dsi->io_wakeref[port] =
 334                         intel_display_power_get(dev_priv,
 335                                                 port == PORT_A ?
 336                                                 POWER_DOMAIN_PORT_DDI_A_IO :
 337                                                 POWER_DOMAIN_PORT_DDI_B_IO);
 338         }
 339 }
 340
 341 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 342 {
 343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 344         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 345         enum port port;
 346         u32 tmp;
 347
 348         for_each_dsi_port(port, intel_dsi->ports) {
 349                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
 350                 tmp |= COMBO_PHY_MODE_DSI;
 351                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
 352         }
 353
 354         get_dsi_io_power_domains(dev_priv, intel_dsi);
 355 }
 356
 357 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 358 {
 359         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 360         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 361         enum port port;
 362         u32 tmp;
 363         u32 lane_mask;
 364
 365         switch (intel_dsi->lane_count) {
 366         case 1:
 367                 lane_mask = PWR_DOWN_LN_3_1_0;
 368                 break;
 369         case 2:
 370                 lane_mask = PWR_DOWN_LN_3_1;
 371                 break;
 372         case 3:
 373                 lane_mask = PWR_DOWN_LN_3;
 374                 break;
 375         case 4:
 376         default:
 377                 lane_mask = PWR_UP_ALL_LANES;
 378                 break;
 379         }
 380
 381         for_each_dsi_port(port, intel_dsi->ports) {
 382                 tmp = I915_READ(ICL_PORT_CL_DW10(port));
 383                 tmp &= ~PWR_DOWN_LN_MASK;
 384                 I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
 385         }
 386 }
 387
 388 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 389 {
 390         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 391         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 392         enum port port;
 393         u32 tmp;
 394         int lane;
 395
 396         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 397         for_each_dsi_port(port, intel_dsi->ports) {
 398                 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
 399                 tmp &= ~LOADGEN_SELECT;
 400                 I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
 401                 for (lane = 0; lane <= 3; lane++) {
 402                         tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
 403                         tmp &= ~LOADGEN_SELECT;
 404                         if (lane != 2)
 405                                 tmp |= LOADGEN_SELECT;
 406                         I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
 407                 }
 408         }
 409
 410         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 411         for_each_dsi_port(port, intel_dsi->ports) {
 412                 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
 413                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 414                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 415                 I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
 416                 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
 417                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 418                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 419                 I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
 420         }
 421
 422 }
 423
 424 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 425 {
 426         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 427         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 428         u32 tmp;
 429         enum port port;
 430
 431         /* clear common keeper enable bit */
 432         for_each_dsi_port(port, intel_dsi->ports) {
 433                 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
 434                 tmp &= ~COMMON_KEEPER_EN;
 435                 I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
 436                 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
 437                 tmp &= ~COMMON_KEEPER_EN;
 438                 I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
 439         }
 440
 441         /*
 442          * Set SUS Clock Config bitfield to 11b
 443          * Note: loadgen select program is done
 444          * as part of lane phy sequence configuration
 445          */
 446         for_each_dsi_port(port, intel_dsi->ports) {
 447                 tmp = I915_READ(ICL_PORT_CL_DW5(port));
 448                 tmp |= SUS_CLOCK_CONFIG;
 449                 I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
 450         }
 451
 452         /* Clear training enable to change swing values */
 453         for_each_dsi_port(port, intel_dsi->ports) {
 454                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 455                 tmp &= ~TX_TRAINING_EN;
 456                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 457                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 458                 tmp &= ~TX_TRAINING_EN;
 459                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 460         }
 461
 462         /* Program swing and de-emphasis */
 463         dsi_program_swing_and_deemphasis(encoder);
 464
 465         /* Set training enable to trigger update */
 466         for_each_dsi_port(port, intel_dsi->ports) {
 467                 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 468                 tmp |= TX_TRAINING_EN;
 469                 I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
 470                 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
 471                 tmp |= TX_TRAINING_EN;
 472                 I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
 473         }
 474 }
 475
 476 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 477 {
 478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 479         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 480         u32 tmp;
 481         enum port port;
 482
 483         for_each_dsi_port(port, intel_dsi->ports) {
 484                 tmp = I915_READ(DDI_BUF_CTL(port));
 485                 tmp |= DDI_BUF_CTL_ENABLE;
 486                 I915_WRITE(DDI_BUF_CTL(port), tmp);
 487
 488                 if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
 489                                   DDI_BUF_IS_IDLE),
 490                                   500))
 491                         DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
 492         }
 493 }
 494
 495 static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 496 {
 497         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 498         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 499         u32 tmp;
 500         enum port port;
 501
 502         /* Program T-INIT master registers */
 503         for_each_dsi_port(port, intel_dsi->ports) {
 504                 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
 505                 tmp &= ~MASTER_INIT_TIMER_MASK;
 506                 tmp |= intel_dsi->init_count;
 507                 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
 508         }
 509
 510         /* Program DPHY clock lanes timings */
 511         for_each_dsi_port(port, intel_dsi->ports) {
 512                 I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 513
 514                 /* shadow register inside display core */
 515                 I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
 516         }
 517
 518         /* Program DPHY data lanes timings */
 519         for_each_dsi_port(port, intel_dsi->ports) {
 520                 I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
 521                            intel_dsi->dphy_data_lane_reg);
 522
 523                 /* shadow register inside display core */
 524                 I915_WRITE(DSI_DATA_TIMING_PARAM(port),
 525                            intel_dsi->dphy_data_lane_reg);
 526         }
 527
 528         /*
 529          * If DSI link operating at or below an 800 MHz,
 530          * TA_SURE should be override and programmed to
 531          * a value '0' inside TA_PARAM_REGISTERS otherwise
 532          * leave all fields at HW default values.
 533          */
 534         if (intel_dsi_bitrate(intel_dsi) <= 800000) {
 535                 for_each_dsi_port(port, intel_dsi->ports) {
 536                         tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 537                         tmp &= ~TA_SURE_MASK;
 538                         tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 539                         I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
 540
 541                         /* shadow register inside display core */
 542                         tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
 543                         tmp &= ~TA_SURE_MASK;
 544                         tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
 545                         I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
 546                 }
 547         }
 548 }
 549
 550 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 551 {
 552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 553         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 554         u32 tmp;
 555         enum port port;
 556
 557         mutex_lock(&dev_priv->dpll_lock);
 558         tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 559         for_each_dsi_port(port, intel_dsi->ports) {
 560                 tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 561         }
 562
 563         I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
 564         mutex_unlock(&dev_priv->dpll_lock);
 565 }
 566
 567 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 570         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 571         u32 tmp;
 572         enum port port;
 573
 574         mutex_lock(&dev_priv->dpll_lock);
 575         tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 576         for_each_dsi_port(port, intel_dsi->ports) {
 577                 tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 578         }
 579
 580         I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
 581         mutex_unlock(&dev_priv->dpll_lock);
 582 }
 583
 584 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 585                               const struct intel_crtc_state *crtc_state)
 586 {
 587         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 588         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 589         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 590         enum port port;
 591         u32 val;
 592
 593         mutex_lock(&dev_priv->dpll_lock);
 594
 595         val = I915_READ(DPCLKA_CFGCR0_ICL);
 596         for_each_dsi_port(port, intel_dsi->ports) {
 597                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
 598                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 599         }
 600         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 601
 602         for_each_dsi_port(port, intel_dsi->ports) {
 603                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 604         }
 605         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 606
 607         POSTING_READ(DPCLKA_CFGCR0_ICL);
 608
 609         mutex_unlock(&dev_priv->dpll_lock);
 610 }
 611
 612 static void
 613 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 614                                const struct intel_crtc_state *pipe_config)
 615 {
 616         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 617         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 618         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 619         enum pipe pipe = intel_crtc->pipe;
 620         u32 tmp;
 621         enum port port;
 622         enum transcoder dsi_trans;
 623
 624         for_each_dsi_port(port, intel_dsi->ports) {
 625                 dsi_trans = dsi_port_to_transcoder(port);
 626                 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
 627
 628                 if (intel_dsi->eotp_pkt)
 629                         tmp &= ~EOTP_DISABLED;
 630                 else
 631                         tmp |= EOTP_DISABLED;
 632
 633                 /* enable link calibration if freq > 1.5Gbps */
 634                 if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
 635                         tmp &= ~LINK_CALIBRATION_MASK;
 636                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 637                 }
 638
 639                 /* configure continuous clock */
 640                 tmp &= ~CONTINUOUS_CLK_MASK;
 641                 if (intel_dsi->clock_stop)
 642                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 643                 else
 644                         tmp |= CLK_HS_CONTINUOUS;
 645
 646                 /* configure buffer threshold limit to minimum */
 647                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 648                 tmp |= PIX_BUF_THRESHOLD_1_4;
 649
 650                 /* set virtual channel to '0' */
 651                 tmp &= ~PIX_VIRT_CHAN_MASK;
 652                 tmp |= PIX_VIRT_CHAN(0);
 653
 654                 /* program BGR transmission */
 655                 if (intel_dsi->bgr_enabled)
 656                         tmp |= BGR_TRANSMISSION;
 657
 658                 /* select pixel format */
 659                 tmp &= ~PIX_FMT_MASK;
 660                 switch (intel_dsi->pixel_format) {
 661                 default:
 662                         MISSING_CASE(intel_dsi->pixel_format);
 663                         /* fallthrough */
 664                 case MIPI_DSI_FMT_RGB565:
 665                         tmp |= PIX_FMT_RGB565;
 666                         break;
 667                 case MIPI_DSI_FMT_RGB666_PACKED:
 668                         tmp |= PIX_FMT_RGB666_PACKED;
 669                         break;
 670                 case MIPI_DSI_FMT_RGB666:
 671                         tmp |= PIX_FMT_RGB666_LOOSE;
 672                         break;
 673                 case MIPI_DSI_FMT_RGB888:
 674                         tmp |= PIX_FMT_RGB888;
 675                         break;
 676                 }
 677
 678                 /* program DSI operation mode */
 679                 if (is_vid_mode(intel_dsi)) {
 680                         tmp &= ~OP_MODE_MASK;
 681                         switch (intel_dsi->video_mode_format) {
 682                         default:
 683                                 MISSING_CASE(intel_dsi->video_mode_format);
 684                                 /* fallthrough */
 685                         case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
 686                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 687                                 break;
 688                         case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
 689                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 690                                 break;
 691                         }
 692                 }
 693
 694                 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 695         }
 696
 697         /* enable port sync mode if dual link */
 698         if (intel_dsi->dual_link) {
 699                 for_each_dsi_port(port, intel_dsi->ports) {
 700                         dsi_trans = dsi_port_to_transcoder(port);
 701                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
 702                         tmp |= PORT_SYNC_MODE_ENABLE;
 703                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 704                 }
 705
 706                 /* configure stream splitting */
 707                 configure_dual_link_mode(encoder, pipe_config);
 708         }
 709
 710         for_each_dsi_port(port, intel_dsi->ports) {
 711                 dsi_trans = dsi_port_to_transcoder(port);
 712
 713                 /* select data lane width */
 714                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
 715                 tmp &= ~DDI_PORT_WIDTH_MASK;
 716                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 717
 718                 /* select input pipe */
 719                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 720                 switch (pipe) {
 721                 default:
 722                         MISSING_CASE(pipe);
 723                         /* fallthrough */
 724                 case PIPE_A:
 725                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 726                         break;
 727                 case PIPE_B:
 728                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 729                         break;
 730                 case PIPE_C:
 731                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 732                         break;
 733                 }
 734
 735                 /* enable DDI buffer */
 736                 tmp |= TRANS_DDI_FUNC_ENABLE;
 737                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 738         }
 739
 740         /* wait for link ready */
 741         for_each_dsi_port(port, intel_dsi->ports) {
 742                 dsi_trans = dsi_port_to_transcoder(port);
 743                 if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
 744                                 LINK_READY), 2500))
 745                         DRM_ERROR("DSI link not ready\n");
 746         }
 747 }
 748
 749 static void
 750 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 751                                  const struct intel_crtc_state *pipe_config)
 752 {
 753         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 754         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 755         const struct drm_display_mode *adjusted_mode =
 756                                         &pipe_config->base.adjusted_mode;
 757         enum port port;
 758         enum transcoder dsi_trans;
 759         /* horizontal timings */
 760         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 761         u16 hfront_porch, hback_porch;
 762         /* vertical timings */
 763         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 764
 765         hactive = adjusted_mode->crtc_hdisplay;
 766         htotal = adjusted_mode->crtc_htotal;
 767         hsync_start = adjusted_mode->crtc_hsync_start;
 768         hsync_end = adjusted_mode->crtc_hsync_end;
 769         hsync_size  = hsync_end - hsync_start;
 770         hfront_porch = (adjusted_mode->crtc_hsync_start -
 771                         adjusted_mode->crtc_hdisplay);
 772         hback_porch = (adjusted_mode->crtc_htotal -
 773                        adjusted_mode->crtc_hsync_end);
 774         vactive = adjusted_mode->crtc_vdisplay;
 775         vtotal = adjusted_mode->crtc_vtotal;
 776         vsync_start = adjusted_mode->crtc_vsync_start;
 777         vsync_end = adjusted_mode->crtc_vsync_end;
 778         vsync_shift = hsync_start - htotal / 2;
 779
 780         if (intel_dsi->dual_link) {
 781                 hactive /= 2;
 782                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 783                         hactive += intel_dsi->pixel_overlap;
 784                 htotal /= 2;
 785         }
 786
 787         /* minimum hactive as per bspec: 256 pixels */
 788         if (adjusted_mode->crtc_hdisplay < 256)
 789                 DRM_ERROR("hactive is less then 256 pixels\n");
 790
 791         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 792         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 793                 DRM_ERROR("hactive pixels are not multiple of 4\n");
 794
 795         /* program TRANS_HTOTAL register */
 796         for_each_dsi_port(port, intel_dsi->ports) {
 797                 dsi_trans = dsi_port_to_transcoder(port);
 798                 I915_WRITE(HTOTAL(dsi_trans),
 799                            (hactive - 1) | ((htotal - 1) << 16));
 800         }
 801
 802         /* TRANS_HSYNC register to be programmed only for video mode */
 803         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
 804                 if (intel_dsi->video_mode_format ==
 805                     VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
 806                         /* BSPEC: hsync size should be atleast 16 pixels */
 807                         if (hsync_size < 16)
 808                                 DRM_ERROR("hsync size < 16 pixels\n");
 809                 }
 810
 811                 if (hback_porch < 16)
 812                         DRM_ERROR("hback porch < 16 pixels\n");
 813
 814                 if (intel_dsi->dual_link) {
 815                         hsync_start /= 2;
 816                         hsync_end /= 2;
 817                 }
 818
 819                 for_each_dsi_port(port, intel_dsi->ports) {
 820                         dsi_trans = dsi_port_to_transcoder(port);
 821                         I915_WRITE(HSYNC(dsi_trans),
 822                                    (hsync_start - 1) | ((hsync_end - 1) << 16));
 823                 }
 824         }
 825
 826         /* program TRANS_VTOTAL register */
 827         for_each_dsi_port(port, intel_dsi->ports) {
 828                 dsi_trans = dsi_port_to_transcoder(port);
 829                 /*
 830                  * FIXME: Programing this by assuming progressive mode, since
 831                  * non-interlaced info from VBT is not saved inside
 832                  * struct drm_display_mode.
 833                  * For interlace mode: program required pixel minus 2
 834                  */
 835                 I915_WRITE(VTOTAL(dsi_trans),
 836                            (vactive - 1) | ((vtotal - 1) << 16));
 837         }
 838
 839         if (vsync_end < vsync_start || vsync_end > vtotal)
 840                 DRM_ERROR("Invalid vsync_end value\n");
 841
 842         if (vsync_start < vactive)
 843                 DRM_ERROR("vsync_start less than vactive\n");
 844
 845         /* program TRANS_VSYNC register */
 846         for_each_dsi_port(port, intel_dsi->ports) {
 847                 dsi_trans = dsi_port_to_transcoder(port);
 848                 I915_WRITE(VSYNC(dsi_trans),
 849                            (vsync_start - 1) | ((vsync_end - 1) << 16));
 850         }
 851
 852         /*
 853          * FIXME: It has to be programmed only for interlaced
 854          * modes. Put the check condition here once interlaced
 855          * info available as described above.
 856          * program TRANS_VSYNCSHIFT register
 857          */
 858         for_each_dsi_port(port, intel_dsi->ports) {
 859                 dsi_trans = dsi_port_to_transcoder(port);
 860                 I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
 861         }
 862 }
 863
 864 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 865 {
 866         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 867         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 868         enum port port;
 869         enum transcoder dsi_trans;
 870         u32 tmp;
 871
 872         for_each_dsi_port(port, intel_dsi->ports) {
 873                 dsi_trans = dsi_port_to_transcoder(port);
 874                 tmp = I915_READ(PIPECONF(dsi_trans));
 875                 tmp |= PIPECONF_ENABLE;
 876                 I915_WRITE(PIPECONF(dsi_trans), tmp);
 877
 878                 /* wait for transcoder to be enabled */
 879                 if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
 880                                             I965_PIPECONF_ACTIVE,
 881                                             I965_PIPECONF_ACTIVE, 10))
 882                         DRM_ERROR("DSI transcoder not enabled\n");
 883         }
 884 }
 885
 886 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 887 {
 888         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 889         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 890         enum port port;
 891         enum transcoder dsi_trans;
 892         u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
 893
 894         /*
 895          * escape clock count calculation:
 896          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
 897          * UI (nsec) = (10^6)/Bitrate
 898          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 899          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 900          */
 901         divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
 902         mul = 8 * 1000000;
 903         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 904                                      divisor);
 905         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
 906         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
 907
 908         for_each_dsi_port(port, intel_dsi->ports) {
 909                 dsi_trans = dsi_port_to_transcoder(port);
 910
 911                 /* program hst_tx_timeout */
 912                 tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
 913                 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
 914                 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
 915                 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
 916
 917                 /* FIXME: DSI_CALIB_TO */
 918
 919                 /* program lp_rx_host timeout */
 920                 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
 921                 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
 922                 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
 923                 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
 924
 925                 /* FIXME: DSI_PWAIT_TO */
 926
 927                 /* program turn around timeout */
 928                 tmp = I915_READ(DSI_TA_TO(dsi_trans));
 929                 tmp &= ~TA_TIMEOUT_VALUE_MASK;
 930                 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
 931                 I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
 932         }
 933 }
 934
 935 static void
 936 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 937                               const struct intel_crtc_state *pipe_config)
 938 {
 939         /* step 4a: power up all lanes of the DDI used by DSI */
 940         gen11_dsi_power_up_lanes(encoder);
 941
 942         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
 943         gen11_dsi_config_phy_lanes_sequence(encoder);
 944
 945         /* step 4c: configure voltage swing and skew */
 946         gen11_dsi_voltage_swing_program_seq(encoder);
 947
 948         /* enable DDI buffer */
 949         gen11_dsi_enable_ddi_buffer(encoder);
 950
 951         /* setup D-PHY timings */
 952         gen11_dsi_setup_dphy_timings(encoder);
 953
 954         /* step 4h: setup DSI protocol timeouts */
 955         gen11_dsi_setup_timeouts(encoder);
 956
 957         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
 958         gen11_dsi_configure_transcoder(encoder, pipe_config);
 959
 960         /* Step 4l: Gate DDI clocks */
 961         gen11_dsi_gate_clocks(encoder);
 962 }
 963
 964 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 965 {
 966         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 967         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 968         struct mipi_dsi_device *dsi;
 969         enum port port;
 970         enum transcoder dsi_trans;
 971         u32 tmp;
 972         int ret;
 973
 974         /* set maximum return packet size */
 975         for_each_dsi_port(port, intel_dsi->ports) {
 976                 dsi_trans = dsi_port_to_transcoder(port);
 977
 978                 /*
 979                  * FIXME: This uses the number of DW's currently in the payload
 980                  * receive queue. This is probably not what we want here.
 981                  */
 982                 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
 983                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
 984                 /* multiply "Number Rx Payload DW" by 4 to get max value */
 985                 tmp = tmp * 4;
 986                 dsi = intel_dsi->dsi_hosts[port]->device;
 987                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
 988                 if (ret < 0)
 989                         DRM_ERROR("error setting max return pkt size%d\n", tmp);
 990         }
 991
 992         /* panel power on related mipi dsi vbt sequences */
 993         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 994         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 995         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 996         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 997         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 998
 999         /* ensure all panel commands dispatched before enabling transcoder */
1000         wait_for_cmds_dispatched_to_panel(encoder);
1001 }
1002
1003 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
1004                                      const struct intel_crtc_state *pipe_config,
1005                                      const struct drm_connector_state *conn_state)
1006 {
1007         /* step2: enable IO power */
1008         gen11_dsi_enable_io_power(encoder);
1009
1010         /* step3: enable DSI PLL */
1011         gen11_dsi_program_esc_clk_div(encoder);
1012 }
1013
1014 static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
1015                                  const struct intel_crtc_state *pipe_config,
1016                                  const struct drm_connector_state *conn_state)
1017 {
1018         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1019
1020         /* step3b */
1021         gen11_dsi_map_pll(encoder, pipe_config);
1022
1023         /* step4: enable DSI port and DPHY */
1024         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1025
1026         /* step5: program and powerup panel */
1027         gen11_dsi_powerup_panel(encoder);
1028
1029         /* step6c: configure transcoder timings */
1030         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1031
1032         /* step6d: enable dsi transcoder */
1033         gen11_dsi_enable_transcoder(encoder);
1034
1035         /* step7: enable backlight */
1036         intel_panel_enable_backlight(pipe_config, conn_state);
1037         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1038 }
1039
1040 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1041 {
1042         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1044         enum port port;
1045         enum transcoder dsi_trans;
1046         u32 tmp;
1047
1048         for_each_dsi_port(port, intel_dsi->ports) {
1049                 dsi_trans = dsi_port_to_transcoder(port);
1050
1051                 /* disable transcoder */
1052                 tmp = I915_READ(PIPECONF(dsi_trans));
1053                 tmp &= ~PIPECONF_ENABLE;
1054                 I915_WRITE(PIPECONF(dsi_trans), tmp);
1055
1056                 /* wait for transcoder to be disabled */
1057                 if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
1058                                             I965_PIPECONF_ACTIVE, 0, 50))
1059                         DRM_ERROR("DSI trancoder not disabled\n");
1060         }
1061 }
1062
1063 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1064 {
1065         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1066
1067         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1068         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1069         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1070
1071         /* ensure cmds dispatched to panel */
1072         wait_for_cmds_dispatched_to_panel(encoder);
1073 }
1074
1075 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1076 {
1077         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1078         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1079         enum port port;
1080         enum transcoder dsi_trans;
1081         u32 tmp;
1082
1083         /* put dsi link in ULPS */
1084         for_each_dsi_port(port, intel_dsi->ports) {
1085                 dsi_trans = dsi_port_to_transcoder(port);
1086                 tmp = I915_READ(DSI_LP_MSG(dsi_trans));
1087                 tmp |= LINK_ENTER_ULPS;
1088                 tmp &= ~LINK_ULPS_TYPE_LP11;
1089                 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
1090
1091                 if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
1092                                 LINK_IN_ULPS),
1093                                 10))
1094                         DRM_ERROR("DSI link not in ULPS\n");
1095         }
1096
1097         /* disable ddi function */
1098         for_each_dsi_port(port, intel_dsi->ports) {
1099                 dsi_trans = dsi_port_to_transcoder(port);
1100                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1101                 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1102                 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1103         }
1104
1105         /* disable port sync mode if dual link */
1106         if (intel_dsi->dual_link) {
1107                 for_each_dsi_port(port, intel_dsi->ports) {
1108                         dsi_trans = dsi_port_to_transcoder(port);
1109                         tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
1110                         tmp &= ~PORT_SYNC_MODE_ENABLE;
1111                         I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1112                 }
1113         }
1114 }
1115
1116 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1117 {
1118         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1119         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1120         u32 tmp;
1121         enum port port;
1122
1123         gen11_dsi_ungate_clocks(encoder);
1124         for_each_dsi_port(port, intel_dsi->ports) {
1125                 tmp = I915_READ(DDI_BUF_CTL(port));
1126                 tmp &= ~DDI_BUF_CTL_ENABLE;
1127                 I915_WRITE(DDI_BUF_CTL(port), tmp);
1128
1129                 if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
1130                                  DDI_BUF_IS_IDLE),
1131                                  8))
1132                         DRM_ERROR("DDI port:%c buffer not idle\n",
1133                                   port_name(port));
1134         }
1135         gen11_dsi_gate_clocks(encoder);
1136 }
1137
1138 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1139 {
1140         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1141         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1142         enum port port;
1143         u32 tmp;
1144
1145         for_each_dsi_port(port, intel_dsi->ports) {
1146                 intel_wakeref_t wakeref;
1147
1148                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1149                 if (wakeref) {
1150                         intel_display_power_put(dev_priv,
1151                                                 port == PORT_A ?
1152                                                 POWER_DOMAIN_PORT_DDI_A_IO :
1153                                                 POWER_DOMAIN_PORT_DDI_B_IO,
1154                                                 wakeref);
1155                 }
1156         }
1157
1158         /* set mode to DDI */
1159         for_each_dsi_port(port, intel_dsi->ports) {
1160                 tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
1161                 tmp &= ~COMBO_PHY_MODE_DSI;
1162                 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
1163         }
1164 }
1165
1166 static void gen11_dsi_disable(struct intel_encoder *encoder,
1167                               const struct intel_crtc_state *old_crtc_state,
1168                               const struct drm_connector_state *old_conn_state)
1169 {
1170         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1171
1172         /* step1: turn off backlight */
1173         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1174         intel_panel_disable_backlight(old_conn_state);
1175
1176         /* step2d,e: disable transcoder and wait */
1177         gen11_dsi_disable_transcoder(encoder);
1178
1179         /* step2f,g: powerdown panel */
1180         gen11_dsi_powerdown_panel(encoder);
1181
1182         /* step2h,i,j: deconfig trancoder */
1183         gen11_dsi_deconfigure_trancoder(encoder);
1184
1185         /* step3: disable port */
1186         gen11_dsi_disable_port(encoder);
1187
1188         /* step4: disable IO power */
1189         gen11_dsi_disable_io_power(encoder);
1190 }
1191
1192 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1193                                  struct intel_crtc_state *pipe_config)
1194 {
1195         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1196         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1197         u32 pll_id;
1198
1199         /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1200         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1201         pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1202         pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
1203         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1204 }
1205
1206 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1207                                     struct intel_crtc_state *pipe_config,
1208                                     struct drm_connector_state *conn_state)
1209 {
1210         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1211                                                    base);
1212         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1213         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1214         const struct drm_display_mode *fixed_mode =
1215                                         intel_connector->panel.fixed_mode;
1216         struct drm_display_mode *adjusted_mode =
1217                                         &pipe_config->base.adjusted_mode;
1218
1219         intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1220         intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
1221
1222         adjusted_mode->flags = 0;
1223
1224         /* Dual link goes to trancoder DSI'0' */
1225         if (intel_dsi->ports == BIT(PORT_B))
1226                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1227         else
1228                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1229
1230         pipe_config->clock_set = true;
1231         pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
1232
1233         return 0;
1234 }
1235
1236 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1237                                         struct intel_crtc_state *crtc_state)
1238 {
1239         get_dsi_io_power_domains(to_i915(encoder->base.dev),
1240                                  enc_to_intel_dsi(&encoder->base));
1241 }
1242
1243 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1244                                    enum pipe *pipe)
1245 {
1246         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1247         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1248         enum transcoder dsi_trans;
1249         intel_wakeref_t wakeref;
1250         enum port port;
1251         bool ret = false;
1252         u32 tmp;
1253
1254         wakeref = intel_display_power_get_if_enabled(dev_priv,
1255                                                      encoder->power_domain);
1256         if (!wakeref)
1257                 return false;
1258
1259         for_each_dsi_port(port, intel_dsi->ports) {
1260                 dsi_trans = dsi_port_to_transcoder(port);
1261                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
1262                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1263                 case TRANS_DDI_EDP_INPUT_A_ON:
1264                         *pipe = PIPE_A;
1265                         break;
1266                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1267                         *pipe = PIPE_B;
1268                         break;
1269                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1270                         *pipe = PIPE_C;
1271                         break;
1272                 default:
1273                         DRM_ERROR("Invalid PIPE input\n");
1274                         goto out;
1275                 }
1276
1277                 tmp = I915_READ(PIPECONF(dsi_trans));
1278                 ret = tmp & PIPECONF_ENABLE;
1279         }
1280 out:
1281         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1282         return ret;
1283 }
1284
1285 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1286 {
1287         intel_encoder_destroy(encoder);
1288 }
1289
1290 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1291         .destroy = gen11_dsi_encoder_destroy,
1292 };
1293
1294 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1295         .late_register = intel_connector_register,
1296         .early_unregister = intel_connector_unregister,
1297         .destroy = intel_connector_destroy,
1298         .fill_modes = drm_helper_probe_single_connector_modes,
1299         .atomic_get_property = intel_digital_connector_atomic_get_property,
1300         .atomic_set_property = intel_digital_connector_atomic_set_property,
1301         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1302         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1303 };
1304
1305 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1306         .get_modes = intel_dsi_get_modes,
1307         .mode_valid = intel_dsi_mode_valid,
1308         .atomic_check = intel_digital_connector_atomic_check,
1309 };
1310
1311 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1312                                  struct mipi_dsi_device *dsi)
1313 {
1314         return 0;
1315 }
1316
1317 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1318                                  struct mipi_dsi_device *dsi)
1319 {
1320         return 0;
1321 }
1322
1323 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1324                                        const struct mipi_dsi_msg *msg)
1325 {
1326         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1327         struct mipi_dsi_packet dsi_pkt;
1328         ssize_t ret;
1329         bool enable_lpdt = false;
1330
1331         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1332         if (ret < 0)
1333                 return ret;
1334
1335         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1336                 enable_lpdt = true;
1337
1338         /* send packet header */
1339         ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1340         if (ret < 0)
1341                 return ret;
1342
1343         /* only long packet contains payload */
1344         if (mipi_dsi_packet_format_is_long(msg->type)) {
1345                 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1346                 if (ret < 0)
1347                         return ret;
1348         }
1349
1350         //TODO: add payload receive code if needed
1351
1352         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1353
1354         return ret;
1355 }
1356
1357 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1358         .attach = gen11_dsi_host_attach,
1359         .detach = gen11_dsi_host_detach,
1360         .transfer = gen11_dsi_host_transfer,
1361 };
1362
1363 void icl_dsi_init(struct drm_i915_private *dev_priv)
1364 {
1365         struct drm_device *dev = &dev_priv->drm;
1366         struct intel_dsi *intel_dsi;
1367         struct intel_encoder *encoder;
1368         struct intel_connector *intel_connector;
1369         struct drm_connector *connector;
1370         struct drm_display_mode *scan, *fixed_mode = NULL;
1371         enum port port;
1372
1373         if (!intel_bios_is_dsi_present(dev_priv, &port))
1374                 return;
1375
1376         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1377         if (!intel_dsi)
1378                 return;
1379
1380         intel_connector = intel_connector_alloc();
1381         if (!intel_connector) {
1382                 kfree(intel_dsi);
1383                 return;
1384         }
1385
1386         encoder = &intel_dsi->base;
1387         intel_dsi->attached_connector = intel_connector;
1388         connector = &intel_connector->base;
1389
1390         /* register DSI encoder with DRM subsystem */
1391         drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1392                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1393
1394         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1395         encoder->pre_enable = gen11_dsi_pre_enable;
1396         encoder->disable = gen11_dsi_disable;
1397         encoder->port = port;
1398         encoder->get_config = gen11_dsi_get_config;
1399         encoder->update_pipe = intel_panel_update_backlight;
1400         encoder->compute_config = gen11_dsi_compute_config;
1401         encoder->get_hw_state = gen11_dsi_get_hw_state;
1402         encoder->type = INTEL_OUTPUT_DSI;
1403         encoder->cloneable = 0;
1404         encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1405         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1406         encoder->get_power_domains = gen11_dsi_get_power_domains;
1407
1408         /* register DSI connector with DRM subsystem */
1409         drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1410                            DRM_MODE_CONNECTOR_DSI);
1411         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1412         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1413         connector->interlace_allowed = false;
1414         connector->doublescan_allowed = false;
1415         intel_connector->get_hw_state = intel_connector_get_hw_state;
1416
1417         /* attach connector to encoder */
1418         intel_connector_attach_encoder(intel_connector, encoder);
1419
1420         /* fill mode info from VBT */
1421         mutex_lock(&dev->mode_config.mutex);
1422         intel_dsi_vbt_get_modes(intel_dsi);
1423         list_for_each_entry(scan, &connector->probed_modes, head) {
1424                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1425                         fixed_mode = drm_mode_duplicate(dev, scan);
1426                         break;
1427                 }
1428         }
1429         mutex_unlock(&dev->mode_config.mutex);
1430
1431         if (!fixed_mode) {
1432                 DRM_ERROR("DSI fixed mode info missing\n");
1433                 goto err;
1434         }
1435
1436         connector->display_info.width_mm = fixed_mode->width_mm;
1437         connector->display_info.height_mm = fixed_mode->height_mm;
1438         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1439         intel_panel_setup_backlight(connector, INVALID_PIPE);
1440
1441
1442         if (dev_priv->vbt.dsi.config->dual_link)
1443                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1444         else
1445                 intel_dsi->ports = BIT(port);
1446
1447         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1448         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1449
1450         for_each_dsi_port(port, intel_dsi->ports) {
1451                 struct intel_dsi_host *host;
1452
1453                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1454                 if (!host)
1455                         goto err;
1456
1457                 intel_dsi->dsi_hosts[port] = host;
1458         }
1459
1460         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1461                 DRM_DEBUG_KMS("no device found\n");
1462                 goto err;
1463         }
1464
1465         return;
1466
1467 err:
1468         drm_encoder_cleanup(&encoder->base);
1469         kfree(intel_dsi);
1470         kfree(intel_connector);
1471 }