drivers/gpu/drm/i915/i915_sysfs.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *
  26  */
  27
  28 #include <linux/device.h>
  29 #include <linux/module.h>
  30 #include <linux/stat.h>
  31 #include <linux/sysfs.h>
  32 #include "intel_drv.h"
  33 #include "i915_drv.h"
  34
  35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
  36 {
  37         struct drm_minor *minor = dev_get_drvdata(kdev);
  38         return to_i915(minor->dev);
  39 }
  40
  41 #ifdef CONFIG_PM
  42 static u32 calc_residency(struct drm_i915_private *dev_priv,
  43                           i915_reg_t reg)
  44 {
  45         return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg),
  46                                      1000);
  47 }
  48
  49 static ssize_t
  50 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  51 {
  52         return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled());
  53 }
  54
  55 static ssize_t
  56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  57 {
  58         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  59         u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
  60         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  61 }
  62
  63 static ssize_t
  64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  65 {
  66         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  67         u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
  68         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  69 }
  70
  71 static ssize_t
  72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  73 {
  74         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  75         u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
  76         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  77 }
  78
  79 static ssize_t
  80 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  81 {
  82         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  83         u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
  84         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  85 }
  86
  87 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
  88 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
  89 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
  90 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
  91 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
  92
  93 static struct attribute *rc6_attrs[] = {
  94         &dev_attr_rc6_enable.attr,
  95         &dev_attr_rc6_residency_ms.attr,
  96         NULL
  97 };
  98
  99 static const struct attribute_group rc6_attr_group = {
 100         .name = power_group_name,
 101         .attrs =  rc6_attrs
 102 };
 103
 104 static struct attribute *rc6p_attrs[] = {
 105         &dev_attr_rc6p_residency_ms.attr,
 106         &dev_attr_rc6pp_residency_ms.attr,
 107         NULL
 108 };
 109
 110 static const struct attribute_group rc6p_attr_group = {
 111         .name = power_group_name,
 112         .attrs =  rc6p_attrs
 113 };
 114
 115 static struct attribute *media_rc6_attrs[] = {
 116         &dev_attr_media_rc6_residency_ms.attr,
 117         NULL
 118 };
 119
 120 static const struct attribute_group media_rc6_attr_group = {
 121         .name = power_group_name,
 122         .attrs =  media_rc6_attrs
 123 };
 124 #endif
 125
 126 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
 127 {
 128         if (!HAS_L3_DPF(dev_priv))
 129                 return -EPERM;
 130
 131         if (offset % 4 != 0)
 132                 return -EINVAL;
 133
 134         if (offset >= GEN7_L3LOG_SIZE)
 135                 return -ENXIO;
 136
 137         return 0;
 138 }
 139
 140 static ssize_t
 141 i915_l3_read(struct file *filp, struct kobject *kobj,
 142              struct bin_attribute *attr, char *buf,
 143              loff_t offset, size_t count)
 144 {
 145         struct device *kdev = kobj_to_dev(kobj);
 146         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 147         struct drm_device *dev = &dev_priv->drm;
 148         int slice = (int)(uintptr_t)attr->private;
 149         int ret;
 150
 151         count = round_down(count, 4);
 152
 153         ret = l3_access_valid(dev_priv, offset);
 154         if (ret)
 155                 return ret;
 156
 157         count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
 158
 159         ret = i915_mutex_lock_interruptible(dev);
 160         if (ret)
 161                 return ret;
 162
 163         if (dev_priv->l3_parity.remap_info[slice])
 164                 memcpy(buf,
 165                        dev_priv->l3_parity.remap_info[slice] + (offset/4),
 166                        count);
 167         else
 168                 memset(buf, 0, count);
 169
 170         mutex_unlock(&dev->struct_mutex);
 171
 172         return count;
 173 }
 174
 175 static ssize_t
 176 i915_l3_write(struct file *filp, struct kobject *kobj,
 177               struct bin_attribute *attr, char *buf,
 178               loff_t offset, size_t count)
 179 {
 180         struct device *kdev = kobj_to_dev(kobj);
 181         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 182         struct drm_device *dev = &dev_priv->drm;
 183         struct i915_gem_context *ctx;
 184         int slice = (int)(uintptr_t)attr->private;
 185         u32 **remap_info;
 186         int ret;
 187
 188         ret = l3_access_valid(dev_priv, offset);
 189         if (ret)
 190                 return ret;
 191
 192         ret = i915_mutex_lock_interruptible(dev);
 193         if (ret)
 194                 return ret;
 195
 196         remap_info = &dev_priv->l3_parity.remap_info[slice];
 197         if (!*remap_info) {
 198                 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
 199                 if (!*remap_info) {
 200                         ret = -ENOMEM;
 201                         goto out;
 202                 }
 203         }
 204
 205         /* TODO: Ideally we really want a GPU reset here to make sure errors
 206          * aren't propagated. Since I cannot find a stable way to reset the GPU
 207          * at this point it is left as a TODO.
 208         */
 209         memcpy(*remap_info + (offset/4), buf, count);
 210
 211         /* NB: We defer the remapping until we switch to the context */
 212         list_for_each_entry(ctx, &dev_priv->contexts.list, link)
 213                 ctx->remap_slice |= (1<<slice);
 214
 215         ret = count;
 216
 217 out:
 218         mutex_unlock(&dev->struct_mutex);
 219
 220         return ret;
 221 }
 222
 223 static const struct bin_attribute dpf_attrs = {
 224         .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
 225         .size = GEN7_L3LOG_SIZE,
 226         .read = i915_l3_read,
 227         .write = i915_l3_write,
 228         .mmap = NULL,
 229         .private = (void *)0
 230 };
 231
 232 static const struct bin_attribute dpf_attrs_1 = {
 233         .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
 234         .size = GEN7_L3LOG_SIZE,
 235         .read = i915_l3_read,
 236         .write = i915_l3_write,
 237         .mmap = NULL,
 238         .private = (void *)1
 239 };
 240
 241 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 242                                     struct device_attribute *attr, char *buf)
 243 {
 244         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 245         int ret;
 246
 247         intel_runtime_pm_get(dev_priv);
 248
 249         mutex_lock(&dev_priv->pcu_lock);
 250         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 251                 u32 freq;
 252                 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 253                 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 254         } else {
 255                 u32 rpstat = I915_READ(GEN6_RPSTAT1);
 256                 if (INTEL_GEN(dev_priv) >= 9)
 257                         ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 258                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 259                         ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 260                 else
 261                         ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 262                 ret = intel_gpu_freq(dev_priv, ret);
 263         }
 264         mutex_unlock(&dev_priv->pcu_lock);
 265
 266         intel_runtime_pm_put(dev_priv);
 267
 268         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 269 }
 270
 271 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 272                                     struct device_attribute *attr, char *buf)
 273 {
 274         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 275
 276         return snprintf(buf, PAGE_SIZE, "%d\n",
 277                         intel_gpu_freq(dev_priv,
 278                                        dev_priv->gt_pm.rps.cur_freq));
 279 }
 280
 281 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 282 {
 283         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 284
 285         return snprintf(buf, PAGE_SIZE, "%d\n",
 286                         intel_gpu_freq(dev_priv,
 287                                        dev_priv->gt_pm.rps.boost_freq));
 288 }
 289
 290 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
 291                                        struct device_attribute *attr,
 292                                        const char *buf, size_t count)
 293 {
 294         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 295         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 296         u32 val;
 297         ssize_t ret;
 298
 299         ret = kstrtou32(buf, 0, &val);
 300         if (ret)
 301                 return ret;
 302
 303         /* Validate against (static) hardware limits */
 304         val = intel_freq_opcode(dev_priv, val);
 305         if (val < rps->min_freq || val > rps->max_freq)
 306                 return -EINVAL;
 307
 308         mutex_lock(&dev_priv->pcu_lock);
 309         rps->boost_freq = val;
 310         mutex_unlock(&dev_priv->pcu_lock);
 311
 312         return count;
 313 }
 314
 315 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 316                                      struct device_attribute *attr, char *buf)
 317 {
 318         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 319
 320         return snprintf(buf, PAGE_SIZE, "%d\n",
 321                         intel_gpu_freq(dev_priv,
 322                                        dev_priv->gt_pm.rps.efficient_freq));
 323 }
 324
 325 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 326 {
 327         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 328
 329         return snprintf(buf, PAGE_SIZE, "%d\n",
 330                         intel_gpu_freq(dev_priv,
 331                                        dev_priv->gt_pm.rps.max_freq_softlimit));
 332 }
 333
 334 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 335                                      struct device_attribute *attr,
 336                                      const char *buf, size_t count)
 337 {
 338         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 339         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 340         u32 val;
 341         ssize_t ret;
 342
 343         ret = kstrtou32(buf, 0, &val);
 344         if (ret)
 345                 return ret;
 346
 347         intel_runtime_pm_get(dev_priv);
 348
 349         mutex_lock(&dev_priv->pcu_lock);
 350
 351         val = intel_freq_opcode(dev_priv, val);
 352
 353         if (val < rps->min_freq ||
 354             val > rps->max_freq ||
 355             val < rps->min_freq_softlimit) {
 356                 mutex_unlock(&dev_priv->pcu_lock);
 357                 intel_runtime_pm_put(dev_priv);
 358                 return -EINVAL;
 359         }
 360
 361         if (val > rps->rp0_freq)
 362                 DRM_DEBUG("User requested overclocking to %d\n",
 363                           intel_gpu_freq(dev_priv, val));
 364
 365         rps->max_freq_softlimit = val;
 366
 367         val = clamp_t(int, rps->cur_freq,
 368                       rps->min_freq_softlimit,
 369                       rps->max_freq_softlimit);
 370
 371         /* We still need *_set_rps to process the new max_delay and
 372          * update the interrupt limits and PMINTRMSK even though
 373          * frequency request may be unchanged. */
 374         ret = intel_set_rps(dev_priv, val);
 375
 376         mutex_unlock(&dev_priv->pcu_lock);
 377
 378         intel_runtime_pm_put(dev_priv);
 379
 380         return ret ?: count;
 381 }
 382
 383 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 384 {
 385         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 386
 387         return snprintf(buf, PAGE_SIZE, "%d\n",
 388                         intel_gpu_freq(dev_priv,
 389                                        dev_priv->gt_pm.rps.min_freq_softlimit));
 390 }
 391
 392 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 393                                      struct device_attribute *attr,
 394                                      const char *buf, size_t count)
 395 {
 396         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 397         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 398         u32 val;
 399         ssize_t ret;
 400
 401         ret = kstrtou32(buf, 0, &val);
 402         if (ret)
 403                 return ret;
 404
 405         intel_runtime_pm_get(dev_priv);
 406
 407         mutex_lock(&dev_priv->pcu_lock);
 408
 409         val = intel_freq_opcode(dev_priv, val);
 410
 411         if (val < rps->min_freq ||
 412             val > rps->max_freq ||
 413             val > rps->max_freq_softlimit) {
 414                 mutex_unlock(&dev_priv->pcu_lock);
 415                 intel_runtime_pm_put(dev_priv);
 416                 return -EINVAL;
 417         }
 418
 419         rps->min_freq_softlimit = val;
 420
 421         val = clamp_t(int, rps->cur_freq,
 422                       rps->min_freq_softlimit,
 423                       rps->max_freq_softlimit);
 424
 425         /* We still need *_set_rps to process the new min_delay and
 426          * update the interrupt limits and PMINTRMSK even though
 427          * frequency request may be unchanged. */
 428         ret = intel_set_rps(dev_priv, val);
 429
 430         mutex_unlock(&dev_priv->pcu_lock);
 431
 432         intel_runtime_pm_put(dev_priv);
 433
 434         return ret ?: count;
 435 }
 436
 437 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
 438 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
 439 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store);
 440 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 441 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
 442
 443 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
 444
 445 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
 446 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 447 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 448 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 449
 450 /* For now we have a static number of RP states */
 451 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 452 {
 453         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 454         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 455         u32 val;
 456
 457         if (attr == &dev_attr_gt_RP0_freq_mhz)
 458                 val = intel_gpu_freq(dev_priv, rps->rp0_freq);
 459         else if (attr == &dev_attr_gt_RP1_freq_mhz)
 460                 val = intel_gpu_freq(dev_priv, rps->rp1_freq);
 461         else if (attr == &dev_attr_gt_RPn_freq_mhz)
 462                 val = intel_gpu_freq(dev_priv, rps->min_freq);
 463         else
 464                 BUG();
 465
 466         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 467 }
 468
 469 static const struct attribute *gen6_attrs[] = {
 470         &dev_attr_gt_act_freq_mhz.attr,
 471         &dev_attr_gt_cur_freq_mhz.attr,
 472         &dev_attr_gt_boost_freq_mhz.attr,
 473         &dev_attr_gt_max_freq_mhz.attr,
 474         &dev_attr_gt_min_freq_mhz.attr,
 475         &dev_attr_gt_RP0_freq_mhz.attr,
 476         &dev_attr_gt_RP1_freq_mhz.attr,
 477         &dev_attr_gt_RPn_freq_mhz.attr,
 478         NULL,
 479 };
 480
 481 static const struct attribute *vlv_attrs[] = {
 482         &dev_attr_gt_act_freq_mhz.attr,
 483         &dev_attr_gt_cur_freq_mhz.attr,
 484         &dev_attr_gt_boost_freq_mhz.attr,
 485         &dev_attr_gt_max_freq_mhz.attr,
 486         &dev_attr_gt_min_freq_mhz.attr,
 487         &dev_attr_gt_RP0_freq_mhz.attr,
 488         &dev_attr_gt_RP1_freq_mhz.attr,
 489         &dev_attr_gt_RPn_freq_mhz.attr,
 490         &dev_attr_vlv_rpe_freq_mhz.attr,
 491         NULL,
 492 };
 493
 494 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 495
 496 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 497                                 struct bin_attribute *attr, char *buf,
 498                                 loff_t off, size_t count)
 499 {
 500
 501         struct device *kdev = kobj_to_dev(kobj);
 502         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 503         struct drm_i915_error_state_buf error_str;
 504         struct i915_gpu_state *gpu;
 505         ssize_t ret;
 506
 507         ret = i915_error_state_buf_init(&error_str, dev_priv, count, off);
 508         if (ret)
 509                 return ret;
 510
 511         gpu = i915_first_error_state(dev_priv);
 512         ret = i915_error_state_to_str(&error_str, gpu);
 513         if (ret)
 514                 goto out;
 515
 516         ret = count < error_str.bytes ? count : error_str.bytes;
 517         memcpy(buf, error_str.buf, ret);
 518
 519 out:
 520         i915_gpu_state_put(gpu);
 521         i915_error_state_buf_release(&error_str);
 522
 523         return ret;
 524 }
 525
 526 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
 527                                  struct bin_attribute *attr, char *buf,
 528                                  loff_t off, size_t count)
 529 {
 530         struct device *kdev = kobj_to_dev(kobj);
 531         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 532
 533         DRM_DEBUG_DRIVER("Resetting error state\n");
 534         i915_reset_error_state(dev_priv);
 535
 536         return count;
 537 }
 538
 539 static const struct bin_attribute error_state_attr = {
 540         .attr.name = "error",
 541         .attr.mode = S_IRUSR | S_IWUSR,
 542         .size = 0,
 543         .read = error_state_read,
 544         .write = error_state_write,
 545 };
 546
 547 static void i915_setup_error_capture(struct device *kdev)
 548 {
 549         if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
 550                 DRM_ERROR("error_state sysfs setup failed\n");
 551 }
 552
 553 static void i915_teardown_error_capture(struct device *kdev)
 554 {
 555         sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
 556 }
 557 #else
 558 static void i915_setup_error_capture(struct device *kdev) {}
 559 static void i915_teardown_error_capture(struct device *kdev) {}
 560 #endif
 561
 562 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 563 {
 564         struct device *kdev = dev_priv->drm.primary->kdev;
 565         int ret;
 566
 567 #ifdef CONFIG_PM
 568         if (HAS_RC6(dev_priv)) {
 569                 ret = sysfs_merge_group(&kdev->kobj,
 570                                         &rc6_attr_group);
 571                 if (ret)
 572                         DRM_ERROR("RC6 residency sysfs setup failed\n");
 573         }
 574         if (HAS_RC6p(dev_priv)) {
 575                 ret = sysfs_merge_group(&kdev->kobj,
 576                                         &rc6p_attr_group);
 577                 if (ret)
 578                         DRM_ERROR("RC6p residency sysfs setup failed\n");
 579         }
 580         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 581                 ret = sysfs_merge_group(&kdev->kobj,
 582                                         &media_rc6_attr_group);
 583                 if (ret)
 584                         DRM_ERROR("Media RC6 residency sysfs setup failed\n");
 585         }
 586 #endif
 587         if (HAS_L3_DPF(dev_priv)) {
 588                 ret = device_create_bin_file(kdev, &dpf_attrs);
 589                 if (ret)
 590                         DRM_ERROR("l3 parity sysfs setup failed\n");
 591
 592                 if (NUM_L3_SLICES(dev_priv) > 1) {
 593                         ret = device_create_bin_file(kdev,
 594                                                      &dpf_attrs_1);
 595                         if (ret)
 596                                 DRM_ERROR("l3 parity slice 1 setup failed\n");
 597                 }
 598         }
 599
 600         ret = 0;
 601         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 602                 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
 603         else if (INTEL_GEN(dev_priv) >= 6)
 604                 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
 605         if (ret)
 606                 DRM_ERROR("RPS sysfs setup failed\n");
 607
 608         i915_setup_error_capture(kdev);
 609 }
 610
 611 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
 612 {
 613         struct device *kdev = dev_priv->drm.primary->kdev;
 614
 615         i915_teardown_error_capture(kdev);
 616
 617         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 618                 sysfs_remove_files(&kdev->kobj, vlv_attrs);
 619         else
 620                 sysfs_remove_files(&kdev->kobj, gen6_attrs);
 621         device_remove_bin_file(kdev,  &dpf_attrs_1);
 622         device_remove_bin_file(kdev,  &dpf_attrs);
 623 #ifdef CONFIG_PM
 624         sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
 625         sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
 626 #endif
 627 }