2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
35 #include "i915_active.h"
37 #include "i915_globals.h"
41 struct list_head link;
43 struct i915_sw_fence *fence;
44 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
45 struct i915_request *signal;
48 static struct i915_global_request {
49 struct i915_global base;
50 struct kmem_cache *slab_requests;
51 struct kmem_cache *slab_dependencies;
52 struct kmem_cache *slab_execute_cbs;
55 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
60 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
63 * The timeline struct (as part of the ppgtt underneath a context)
64 * may be freed when the request is no longer in use by the GPU.
65 * We could extend the life of a context to beyond that of all
66 * fences, possibly keeping the hw resource around indefinitely,
67 * or we just give them a false name. Since
68 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
69 * lie seems justifiable.
71 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
74 return to_request(fence)->gem_context->name ?: "[i915]";
77 static bool i915_fence_signaled(struct dma_fence *fence)
79 return i915_request_completed(to_request(fence));
82 static bool i915_fence_enable_signaling(struct dma_fence *fence)
84 return i915_request_enable_breadcrumb(to_request(fence));
87 static signed long i915_fence_wait(struct dma_fence *fence,
91 return i915_request_wait(to_request(fence),
92 interruptible | I915_WAIT_PRIORITY,
96 static void i915_fence_release(struct dma_fence *fence)
98 struct i915_request *rq = to_request(fence);
101 * The request is put onto a RCU freelist (i.e. the address
102 * is immediately reused), mark the fences as being freed now.
103 * Otherwise the debugobjects for the fences are only marked as
104 * freed when the slab cache itself is freed, and so we would get
105 * caught trying to reuse dead objects.
107 i915_sw_fence_fini(&rq->submit);
108 i915_sw_fence_fini(&rq->semaphore);
110 kmem_cache_free(global.slab_requests, rq);
113 const struct dma_fence_ops i915_fence_ops = {
114 .get_driver_name = i915_fence_get_driver_name,
115 .get_timeline_name = i915_fence_get_timeline_name,
116 .enable_signaling = i915_fence_enable_signaling,
117 .signaled = i915_fence_signaled,
118 .wait = i915_fence_wait,
119 .release = i915_fence_release,
123 i915_request_remove_from_client(struct i915_request *request)
125 struct drm_i915_file_private *file_priv;
127 file_priv = request->file_priv;
131 spin_lock(&file_priv->mm.lock);
132 if (request->file_priv) {
133 list_del(&request->client_link);
134 request->file_priv = NULL;
136 spin_unlock(&file_priv->mm.lock);
139 static void advance_ring(struct i915_request *request)
141 struct intel_ring *ring = request->ring;
145 * We know the GPU must have read the request to have
146 * sent us the seqno + interrupt, so use the position
147 * of tail of the request to update the last known position
150 * Note this requires that we are always called in request
153 GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list));
154 if (list_is_last(&request->ring_link, &ring->request_list)) {
156 * We may race here with execlists resubmitting this request
157 * as we retire it. The resubmission will move the ring->tail
158 * forwards (to request->wa_tail). We either read the
159 * current value that was written to hw, or the value that
160 * is just about to be. Either works, if we miss the last two
161 * noops - they are safe to be replayed on a reset.
163 tail = READ_ONCE(request->tail);
164 list_del(&ring->active_link);
166 tail = request->postfix;
168 list_del_init(&request->ring_link);
173 static void free_capture_list(struct i915_request *request)
175 struct i915_capture_list *capture;
177 capture = request->capture_list;
179 struct i915_capture_list *next = capture->next;
186 static bool i915_request_retire(struct i915_request *rq)
188 struct i915_active_request *active, *next;
190 lockdep_assert_held(&rq->i915->drm.struct_mutex);
191 if (!i915_request_completed(rq))
194 GEM_TRACE("%s fence %llx:%lld, current %d\n",
196 rq->fence.context, rq->fence.seqno,
199 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
200 trace_i915_request_retire(rq);
205 * Walk through the active list, calling retire on each. This allows
206 * objects to track their GPU activity and mark themselves as idle
207 * when their *last* active request is completed (updating state
208 * tracking lists for eviction, active references for GEM, etc).
210 * As the ->retire() may free the node, we decouple it first and
211 * pass along the auxiliary information (to avoid dereferencing
212 * the node after the callback).
214 list_for_each_entry_safe(active, next, &rq->active_list, link) {
216 * In microbenchmarks or focusing upon time inside the kernel,
217 * we may spend an inordinate amount of time simply handling
218 * the retirement of requests and processing their callbacks.
219 * Of which, this loop itself is particularly hot due to the
220 * cache misses when jumping around the list of
221 * i915_active_request. So we try to keep this loop as
222 * streamlined as possible and also prefetch the next
223 * i915_active_request to try and hide the likely cache miss.
227 INIT_LIST_HEAD(&active->link);
228 RCU_INIT_POINTER(active->request, NULL);
230 active->retire(active, rq);
235 spin_lock(&rq->engine->active.lock);
236 list_del(&rq->sched.link);
237 spin_unlock(&rq->engine->active.lock);
239 spin_lock(&rq->lock);
240 i915_request_mark_complete(rq);
241 if (!i915_request_signaled(rq))
242 dma_fence_signal_locked(&rq->fence);
243 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
244 i915_request_cancel_breadcrumb(rq);
246 GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
247 atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
249 spin_unlock(&rq->lock);
253 intel_context_exit(rq->hw_context);
254 intel_context_unpin(rq->hw_context);
256 i915_request_remove_from_client(rq);
259 free_capture_list(rq);
260 i915_sched_node_fini(&rq->sched);
261 i915_request_put(rq);
266 void i915_request_retire_upto(struct i915_request *rq)
268 struct intel_ring *ring = rq->ring;
269 struct i915_request *tmp;
271 GEM_TRACE("%s fence %llx:%lld, current %d\n",
273 rq->fence.context, rq->fence.seqno,
276 lockdep_assert_held(&rq->i915->drm.struct_mutex);
277 GEM_BUG_ON(!i915_request_completed(rq));
279 if (list_empty(&rq->ring_link))
283 tmp = list_first_entry(&ring->request_list,
284 typeof(*tmp), ring_link);
285 } while (i915_request_retire(tmp) && tmp != rq);
288 static void irq_execute_cb(struct irq_work *wrk)
290 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
292 i915_sw_fence_complete(cb->fence);
293 kmem_cache_free(global.slab_execute_cbs, cb);
296 static void irq_execute_cb_hook(struct irq_work *wrk)
298 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
300 cb->hook(container_of(cb->fence, struct i915_request, submit),
302 i915_request_put(cb->signal);
307 static void __notify_execute_cb(struct i915_request *rq)
309 struct execute_cb *cb;
311 lockdep_assert_held(&rq->lock);
313 if (list_empty(&rq->execute_cb))
316 list_for_each_entry(cb, &rq->execute_cb, link)
317 irq_work_queue(&cb->work);
320 * XXX Rollback on __i915_request_unsubmit()
322 * In the future, perhaps when we have an active time-slicing scheduler,
323 * it will be interesting to unsubmit parallel execution and remove
324 * busywaits from the GPU until their master is restarted. This is
325 * quite hairy, we have to carefully rollback the fence and do a
326 * preempt-to-idle cycle on the target engine, all the while the
327 * master execute_cb may refire.
329 INIT_LIST_HEAD(&rq->execute_cb);
333 __i915_request_await_execution(struct i915_request *rq,
334 struct i915_request *signal,
335 void (*hook)(struct i915_request *rq,
336 struct dma_fence *signal),
339 struct execute_cb *cb;
341 if (i915_request_is_active(signal)) {
343 hook(rq, &signal->fence);
347 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
351 cb->fence = &rq->submit;
352 i915_sw_fence_await(cb->fence);
353 init_irq_work(&cb->work, irq_execute_cb);
357 cb->signal = i915_request_get(signal);
358 cb->work.func = irq_execute_cb_hook;
361 spin_lock_irq(&signal->lock);
362 if (i915_request_is_active(signal)) {
364 hook(rq, &signal->fence);
365 i915_request_put(signal);
367 i915_sw_fence_complete(cb->fence);
368 kmem_cache_free(global.slab_execute_cbs, cb);
370 list_add_tail(&cb->link, &signal->execute_cb);
372 spin_unlock_irq(&signal->lock);
377 void __i915_request_submit(struct i915_request *request)
379 struct intel_engine_cs *engine = request->engine;
381 GEM_TRACE("%s fence %llx:%lld, current %d\n",
383 request->fence.context, request->fence.seqno,
384 hwsp_seqno(request));
386 GEM_BUG_ON(!irqs_disabled());
387 lockdep_assert_held(&engine->active.lock);
389 if (i915_gem_context_is_banned(request->gem_context))
390 i915_request_skip(request, -EIO);
393 * Are we using semaphores when the gpu is already saturated?
395 * Using semaphores incurs a cost in having the GPU poll a
396 * memory location, busywaiting for it to change. The continual
397 * memory reads can have a noticeable impact on the rest of the
398 * system with the extra bus traffic, stalling the cpu as it too
399 * tries to access memory across the bus (perf stat -e bus-cycles).
401 * If we installed a semaphore on this request and we only submit
402 * the request after the signaler completed, that indicates the
403 * system is overloaded and using semaphores at this time only
404 * increases the amount of work we are doing. If so, we disable
405 * further use of semaphores until we are idle again, whence we
406 * optimistically try again.
408 if (request->sched.semaphores &&
409 i915_sw_fence_signaled(&request->semaphore))
410 engine->saturated |= request->sched.semaphores;
412 /* We may be recursing from the signal callback of another i915 fence */
413 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
415 list_move_tail(&request->sched.link, &engine->active.requests);
417 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
418 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
420 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
421 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
422 !i915_request_enable_breadcrumb(request))
423 intel_engine_queue_breadcrumbs(engine);
425 __notify_execute_cb(request);
427 spin_unlock(&request->lock);
429 engine->emit_fini_breadcrumb(request,
430 request->ring->vaddr + request->postfix);
434 trace_i915_request_execute(request);
437 void i915_request_submit(struct i915_request *request)
439 struct intel_engine_cs *engine = request->engine;
442 /* Will be called from irq-context when using foreign fences. */
443 spin_lock_irqsave(&engine->active.lock, flags);
445 __i915_request_submit(request);
447 spin_unlock_irqrestore(&engine->active.lock, flags);
450 void __i915_request_unsubmit(struct i915_request *request)
452 struct intel_engine_cs *engine = request->engine;
454 GEM_TRACE("%s fence %llx:%lld, current %d\n",
456 request->fence.context, request->fence.seqno,
457 hwsp_seqno(request));
459 GEM_BUG_ON(!irqs_disabled());
460 lockdep_assert_held(&engine->active.lock);
463 * Only unwind in reverse order, required so that the per-context list
464 * is kept in seqno/ring order.
467 /* We may be recursing from the signal callback of another i915 fence */
468 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
470 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
471 i915_request_cancel_breadcrumb(request);
473 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
474 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
476 spin_unlock(&request->lock);
478 /* We've already spun, don't charge on resubmitting. */
479 if (request->sched.semaphores && i915_request_started(request)) {
480 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
481 request->sched.semaphores = 0;
485 * We don't need to wake_up any waiters on request->execute, they
486 * will get woken by any other event or us re-adding this request
487 * to the engine timeline (__i915_request_submit()). The waiters
488 * should be quite adapt at finding that the request now has a new
489 * global_seqno to the one they went to sleep on.
493 void i915_request_unsubmit(struct i915_request *request)
495 struct intel_engine_cs *engine = request->engine;
498 /* Will be called from irq-context when using foreign fences. */
499 spin_lock_irqsave(&engine->active.lock, flags);
501 __i915_request_unsubmit(request);
503 spin_unlock_irqrestore(&engine->active.lock, flags);
506 static int __i915_sw_fence_call
507 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
509 struct i915_request *request =
510 container_of(fence, typeof(*request), submit);
514 trace_i915_request_submit(request);
516 * We need to serialize use of the submit_request() callback
517 * with its hotplugging performed during an emergency
518 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
519 * critical section in order to force i915_gem_set_wedged() to
520 * wait until the submit_request() is completed before
524 request->engine->submit_request(request);
529 i915_request_put(request);
536 static int __i915_sw_fence_call
537 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
539 struct i915_request *request =
540 container_of(fence, typeof(*request), semaphore);
544 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
548 i915_request_put(request);
555 static void ring_retire_requests(struct intel_ring *ring)
557 struct i915_request *rq, *rn;
559 list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link)
560 if (!i915_request_retire(rq))
564 static noinline struct i915_request *
565 request_alloc_slow(struct intel_context *ce, gfp_t gfp)
567 struct intel_ring *ring = ce->ring;
568 struct i915_request *rq;
570 if (list_empty(&ring->request_list))
573 if (!gfpflags_allow_blocking(gfp))
576 /* Move our oldest request to the slab-cache (if not in use!) */
577 rq = list_first_entry(&ring->request_list, typeof(*rq), ring_link);
578 i915_request_retire(rq);
580 rq = kmem_cache_alloc(global.slab_requests,
581 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
585 /* Ratelimit ourselves to prevent oom from malicious clients */
586 rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link);
587 cond_synchronize_rcu(rq->rcustate);
589 /* Retire our old requests in the hope that we free some */
590 ring_retire_requests(ring);
593 return kmem_cache_alloc(global.slab_requests, gfp);
596 struct i915_request *
597 __i915_request_create(struct intel_context *ce, gfp_t gfp)
599 struct i915_timeline *tl = ce->ring->timeline;
600 struct i915_request *rq;
604 might_sleep_if(gfpflags_allow_blocking(gfp));
606 /* Check that the caller provided an already pinned context */
607 __intel_context_pin(ce);
610 * Beware: Dragons be flying overhead.
612 * We use RCU to look up requests in flight. The lookups may
613 * race with the request being allocated from the slab freelist.
614 * That is the request we are writing to here, may be in the process
615 * of being read by __i915_active_request_get_rcu(). As such,
616 * we have to be very careful when overwriting the contents. During
617 * the RCU lookup, we change chase the request->engine pointer,
618 * read the request->global_seqno and increment the reference count.
620 * The reference count is incremented atomically. If it is zero,
621 * the lookup knows the request is unallocated and complete. Otherwise,
622 * it is either still in use, or has been reallocated and reset
623 * with dma_fence_init(). This increment is safe for release as we
624 * check that the request we have a reference to and matches the active
627 * Before we increment the refcount, we chase the request->engine
628 * pointer. We must not call kmem_cache_zalloc() or else we set
629 * that pointer to NULL and cause a crash during the lookup. If
630 * we see the request is completed (based on the value of the
631 * old engine and seqno), the lookup is complete and reports NULL.
632 * If we decide the request is not completed (new engine or seqno),
633 * then we grab a reference and double check that it is still the
634 * active request - which it won't be and restart the lookup.
636 * Do not use kmem_cache_zalloc() here!
638 rq = kmem_cache_alloc(global.slab_requests,
639 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
641 rq = request_alloc_slow(ce, gfp);
648 ret = i915_timeline_get_seqno(tl, rq, &seqno);
652 rq->i915 = ce->engine->i915;
654 rq->gem_context = ce->gem_context;
655 rq->engine = ce->engine;
658 rq->hwsp_seqno = tl->hwsp_seqno;
659 rq->hwsp_cacheline = tl->hwsp_cacheline;
660 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
662 spin_lock_init(&rq->lock);
663 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
664 tl->fence_context, seqno);
666 /* We bump the ref for the fence chain */
667 i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
668 i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify);
670 i915_sched_node_init(&rq->sched);
672 /* No zalloc, must clear what we need by hand */
673 rq->file_priv = NULL;
675 rq->capture_list = NULL;
676 rq->waitboost = false;
677 rq->execution_mask = ALL_ENGINES;
679 INIT_LIST_HEAD(&rq->active_list);
680 INIT_LIST_HEAD(&rq->execute_cb);
683 * Reserve space in the ring buffer for all the commands required to
684 * eventually emit this request. This is to guarantee that the
685 * i915_request_add() call can't fail. Note that the reserve may need
686 * to be redone if the request is not actually submitted straight
687 * away, e.g. because a GPU scheduler has deferred it.
689 * Note that due to how we add reserved_space to intel_ring_begin()
690 * we need to double our request to ensure that if we need to wrap
691 * around inside i915_request_add() there is sufficient space at
692 * the beginning of the ring as well.
695 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
698 * Record the position of the start of the request so that
699 * should we detect the updated seqno part-way through the
700 * GPU processing the request, we never over-estimate the
701 * position of the head.
703 rq->head = rq->ring->emit;
705 ret = rq->engine->request_alloc(rq);
709 rq->infix = rq->ring->emit; /* end of header; start of user payload */
711 intel_context_mark_active(ce);
715 ce->ring->emit = rq->head;
717 /* Make sure we didn't add ourselves to external state before freeing */
718 GEM_BUG_ON(!list_empty(&rq->active_list));
719 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
720 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
723 kmem_cache_free(global.slab_requests, rq);
725 intel_context_unpin(ce);
729 struct i915_request *
730 i915_request_create(struct intel_context *ce)
732 struct i915_request *rq;
735 err = intel_context_timeline_lock(ce);
739 /* Move our oldest request to the slab-cache (if not in use!) */
740 rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
741 if (!list_is_last(&rq->ring_link, &ce->ring->request_list))
742 i915_request_retire(rq);
744 intel_context_enter(ce);
745 rq = __i915_request_create(ce, GFP_KERNEL);
746 intel_context_exit(ce); /* active reference transferred to request */
750 /* Check that we do not interrupt ourselves with a new request */
751 rq->cookie = lockdep_pin_lock(&ce->ring->timeline->mutex);
756 intel_context_timeline_unlock(ce);
761 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
763 if (list_is_first(&signal->ring_link, &signal->ring->request_list))
766 signal = list_prev_entry(signal, ring_link);
767 if (i915_timeline_sync_is_later(rq->timeline, &signal->fence))
770 return i915_sw_fence_await_dma_fence(&rq->submit,
775 static intel_engine_mask_t
776 already_busywaiting(struct i915_request *rq)
779 * Polling a semaphore causes bus traffic, delaying other users of
780 * both the GPU and CPU. We want to limit the impact on others,
781 * while taking advantage of early submission to reduce GPU
782 * latency. Therefore we restrict ourselves to not using more
783 * than one semaphore from each source, and not using a semaphore
784 * if we have detected the engine is saturated (i.e. would not be
785 * submitted early and cause bus traffic reading an already passed
788 * See the are-we-too-late? check in __i915_request_submit().
790 return rq->sched.semaphores | rq->engine->saturated;
794 emit_semaphore_wait(struct i915_request *to,
795 struct i915_request *from,
802 GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
803 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
805 /* Just emit the first semaphore we see as request space is limited. */
806 if (already_busywaiting(to) & from->engine->mask)
807 return i915_sw_fence_await_dma_fence(&to->submit,
811 err = i915_request_await_start(to, from);
815 /* Only submit our spinner after the signaler is running! */
816 err = __i915_request_await_execution(to, from, NULL, gfp);
820 /* We need to pin the signaler's HWSP until we are finished reading. */
821 err = i915_timeline_read_hwsp(from, to, &hwsp_offset);
825 cs = intel_ring_begin(to, 4);
830 * Using greater-than-or-equal here means we have to worry
831 * about seqno wraparound. To side step that issue, we swap
832 * the timeline HWSP upon wrapping, so that everyone listening
833 * for the old (pre-wrap) values do not see the much smaller
834 * (post-wrap) values than they were expecting (and so wait
837 *cs++ = MI_SEMAPHORE_WAIT |
838 MI_SEMAPHORE_GLOBAL_GTT |
840 MI_SEMAPHORE_SAD_GTE_SDD;
841 *cs++ = from->fence.seqno;
845 intel_ring_advance(to, cs);
846 to->sched.semaphores |= from->engine->mask;
847 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
852 i915_request_await_request(struct i915_request *to, struct i915_request *from)
856 GEM_BUG_ON(to == from);
857 GEM_BUG_ON(to->timeline == from->timeline);
859 if (i915_request_completed(from))
862 if (to->engine->schedule) {
863 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
868 if (to->engine == from->engine) {
869 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
872 } else if (intel_engine_has_semaphores(to->engine) &&
873 to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) {
874 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
876 ret = i915_sw_fence_await_dma_fence(&to->submit,
883 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
884 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
895 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
897 struct dma_fence **child = &fence;
898 unsigned int nchild = 1;
902 * Note that if the fence-array was created in signal-on-any mode,
903 * we should *not* decompose it into its individual fences. However,
904 * we don't currently store which mode the fence-array is operating
905 * in. Fortunately, the only user of signal-on-any is private to
906 * amdgpu and we should not see any incoming fence-array from
907 * sync-file being in signal-on-any mode.
909 if (dma_fence_is_array(fence)) {
910 struct dma_fence_array *array = to_dma_fence_array(fence);
912 child = array->fences;
913 nchild = array->num_fences;
919 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
923 * Requests on the same timeline are explicitly ordered, along
924 * with their dependencies, by i915_request_add() which ensures
925 * that requests are submitted in-order through each ring.
927 if (fence->context == rq->fence.context)
930 /* Squash repeated waits to the same timelines */
931 if (fence->context != rq->i915->mm.unordered_timeline &&
932 i915_timeline_sync_is_later(rq->timeline, fence))
935 if (dma_fence_is_i915(fence))
936 ret = i915_request_await_request(rq, to_request(fence));
938 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
944 /* Record the latest fence used against each timeline */
945 if (fence->context != rq->i915->mm.unordered_timeline)
946 i915_timeline_sync_set(rq->timeline, fence);
953 i915_request_await_execution(struct i915_request *rq,
954 struct dma_fence *fence,
955 void (*hook)(struct i915_request *rq,
956 struct dma_fence *signal))
958 struct dma_fence **child = &fence;
959 unsigned int nchild = 1;
962 if (dma_fence_is_array(fence)) {
963 struct dma_fence_array *array = to_dma_fence_array(fence);
965 /* XXX Error for signal-on-any fence arrays */
967 child = array->fences;
968 nchild = array->num_fences;
974 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
978 * We don't squash repeated fence dependencies here as we
979 * want to run our callback in all cases.
982 if (dma_fence_is_i915(fence))
983 ret = __i915_request_await_execution(rq,
988 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
999 * i915_request_await_object - set this request to (async) wait upon a bo
1000 * @to: request we are wishing to use
1001 * @obj: object which may be in use on another ring.
1002 * @write: whether the wait is on behalf of a writer
1004 * This code is meant to abstract object synchronization with the GPU.
1005 * Conceptually we serialise writes between engines inside the GPU.
1006 * We only allow one engine to write into a buffer at any time, but
1007 * multiple readers. To ensure each has a coherent view of memory, we must:
1009 * - If there is an outstanding write request to the object, the new
1010 * request must wait for it to complete (either CPU or in hw, requests
1011 * on the same ring will be naturally ordered).
1013 * - If we are a write request (pending_write_domain is set), the new
1014 * request must wait for outstanding read requests to complete.
1016 * Returns 0 if successful, else propagates up the lower layer error.
1019 i915_request_await_object(struct i915_request *to,
1020 struct drm_i915_gem_object *obj,
1023 struct dma_fence *excl;
1027 struct dma_fence **shared;
1028 unsigned int count, i;
1030 ret = reservation_object_get_fences_rcu(obj->base.resv,
1031 &excl, &count, &shared);
1035 for (i = 0; i < count; i++) {
1036 ret = i915_request_await_dma_fence(to, shared[i]);
1040 dma_fence_put(shared[i]);
1043 for (; i < count; i++)
1044 dma_fence_put(shared[i]);
1047 excl = reservation_object_get_excl_rcu(obj->base.resv);
1052 ret = i915_request_await_dma_fence(to, excl);
1054 dma_fence_put(excl);
1060 void i915_request_skip(struct i915_request *rq, int error)
1062 void *vaddr = rq->ring->vaddr;
1065 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1066 dma_fence_set_error(&rq->fence, error);
1069 * As this request likely depends on state from the lost
1070 * context, clear out all the user operations leaving the
1071 * breadcrumb at the end (so we get the fence notifications).
1074 if (rq->postfix < head) {
1075 memset(vaddr + head, 0, rq->ring->size - head);
1078 memset(vaddr + head, 0, rq->postfix - head);
1081 static struct i915_request *
1082 __i915_request_add_to_timeline(struct i915_request *rq)
1084 struct i915_timeline *timeline = rq->timeline;
1085 struct i915_request *prev;
1088 * Dependency tracking and request ordering along the timeline
1089 * is special cased so that we can eliminate redundant ordering
1090 * operations while building the request (we know that the timeline
1091 * itself is ordered, and here we guarantee it).
1093 * As we know we will need to emit tracking along the timeline,
1094 * we embed the hooks into our request struct -- at the cost of
1095 * having to have specialised no-allocation interfaces (which will
1096 * be beneficial elsewhere).
1098 * A second benefit to open-coding i915_request_await_request is
1099 * that we can apply a slight variant of the rules specialised
1100 * for timelines that jump between engines (such as virtual engines).
1101 * If we consider the case of virtual engine, we must emit a dma-fence
1102 * to prevent scheduling of the second request until the first is
1103 * complete (to maximise our greedy late load balancing) and this
1104 * precludes optimising to use semaphores serialisation of a single
1105 * timeline across engines.
1107 prev = rcu_dereference_protected(timeline->last_request.request, 1);
1108 if (prev && !i915_request_completed(prev)) {
1109 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1110 i915_sw_fence_await_sw_fence(&rq->submit,
1114 __i915_sw_fence_await_dma_fence(&rq->submit,
1117 if (rq->engine->schedule)
1118 __i915_sched_node_add_dependency(&rq->sched,
1124 list_add_tail(&rq->link, &timeline->requests);
1127 * Make sure that no request gazumped us - if it was allocated after
1128 * our i915_request_alloc() and called __i915_request_add() before
1129 * us, the timeline will hold its seqno which is later than ours.
1131 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1132 __i915_active_request_set(&timeline->last_request, rq);
1138 * NB: This function is not allowed to fail. Doing so would mean the the
1139 * request is not being tracked for completion but the work itself is
1140 * going to happen on the hardware. This would be a Bad Thing(tm).
1142 struct i915_request *__i915_request_commit(struct i915_request *rq)
1144 struct intel_engine_cs *engine = rq->engine;
1145 struct intel_ring *ring = rq->ring;
1146 struct i915_request *prev;
1149 GEM_TRACE("%s fence %llx:%lld\n",
1150 engine->name, rq->fence.context, rq->fence.seqno);
1153 * To ensure that this call will not fail, space for its emissions
1154 * should already have been reserved in the ring buffer. Let the ring
1155 * know that it is time to use that space up.
1157 GEM_BUG_ON(rq->reserved_space > ring->space);
1158 rq->reserved_space = 0;
1161 * Record the position of the start of the breadcrumb so that
1162 * should we detect the updated seqno part-way through the
1163 * GPU processing the request, we never over-estimate the
1164 * position of the ring's HEAD.
1166 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1167 GEM_BUG_ON(IS_ERR(cs));
1168 rq->postfix = intel_ring_offset(rq, cs);
1170 prev = __i915_request_add_to_timeline(rq);
1172 list_add_tail(&rq->ring_link, &ring->request_list);
1173 if (list_is_first(&rq->ring_link, &ring->request_list))
1174 list_add(&ring->active_link, &rq->i915->gt.active_rings);
1175 rq->emitted_jiffies = jiffies;
1178 * Let the backend know a new request has arrived that may need
1179 * to adjust the existing execution schedule due to a high priority
1180 * request - i.e. we may want to preempt the current request in order
1181 * to run a high priority dependency chain *before* we can execute this
1184 * This is called before the request is ready to run so that we can
1185 * decide whether to preempt the entire chain so that it is ready to
1186 * run at the earliest possible convenience.
1189 i915_sw_fence_commit(&rq->semaphore);
1190 rcu_read_lock(); /* RCU serialisation for set-wedged protection */
1191 if (engine->schedule) {
1192 struct i915_sched_attr attr = rq->gem_context->sched;
1195 * Boost actual workloads past semaphores!
1197 * With semaphores we spin on one engine waiting for another,
1198 * simply to reduce the latency of starting our work when
1199 * the signaler completes. However, if there is any other
1200 * work that we could be doing on this engine instead, that
1201 * is better utilisation and will reduce the overall duration
1202 * of the current work. To avoid PI boosting a semaphore
1203 * far in the distance past over useful work, we keep a history
1204 * of any semaphore use along our dependency chain.
1206 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1207 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1210 * Boost priorities to new clients (new request flows).
1212 * Allow interactive/synchronous clients to jump ahead of
1213 * the bulk clients. (FQ_CODEL)
1215 if (list_empty(&rq->sched.signalers_list))
1216 attr.priority |= I915_PRIORITY_WAIT;
1218 engine->schedule(rq, &attr);
1221 i915_sw_fence_commit(&rq->submit);
1222 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1227 void i915_request_add(struct i915_request *rq)
1229 struct i915_request *prev;
1231 lockdep_assert_held(&rq->timeline->mutex);
1232 lockdep_unpin_lock(&rq->timeline->mutex, rq->cookie);
1234 trace_i915_request_add(rq);
1236 prev = __i915_request_commit(rq);
1239 * In typical scenarios, we do not expect the previous request on
1240 * the timeline to be still tracked by timeline->last_request if it
1241 * has been completed. If the completed request is still here, that
1242 * implies that request retirement is a long way behind submission,
1243 * suggesting that we haven't been retiring frequently enough from
1244 * the combination of retire-before-alloc, waiters and the background
1245 * retirement worker. So if the last request on this timeline was
1246 * already completed, do a catch up pass, flushing the retirement queue
1247 * up to this client. Since we have now moved the heaviest operations
1248 * during retirement onto secondary workers, such as freeing objects
1249 * or contexts, retiring a bunch of requests is mostly list management
1250 * (and cache misses), and so we should not be overly penalizing this
1251 * client by performing excess work, though we may still performing
1252 * work on behalf of others -- but instead we should benefit from
1253 * improved resource management. (Well, that's the theory at least.)
1255 if (prev && i915_request_completed(prev))
1256 i915_request_retire_upto(prev);
1258 mutex_unlock(&rq->timeline->mutex);
1261 static unsigned long local_clock_us(unsigned int *cpu)
1266 * Cheaply and approximately convert from nanoseconds to microseconds.
1267 * The result and subsequent calculations are also defined in the same
1268 * approximate microseconds units. The principal source of timing
1269 * error here is from the simple truncation.
1271 * Note that local_clock() is only defined wrt to the current CPU;
1272 * the comparisons are no longer valid if we switch CPUs. Instead of
1273 * blocking preemption for the entire busywait, we can detect the CPU
1274 * switch and use that as indicator of system load and a reason to
1275 * stop busywaiting, see busywait_stop().
1278 t = local_clock() >> 10;
1284 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1286 unsigned int this_cpu;
1288 if (time_after(local_clock_us(&this_cpu), timeout))
1291 return this_cpu != cpu;
1294 static bool __i915_spin_request(const struct i915_request * const rq,
1295 int state, unsigned long timeout_us)
1300 * Only wait for the request if we know it is likely to complete.
1302 * We don't track the timestamps around requests, nor the average
1303 * request length, so we do not have a good indicator that this
1304 * request will complete within the timeout. What we do know is the
1305 * order in which requests are executed by the context and so we can
1306 * tell if the request has been started. If the request is not even
1307 * running yet, it is a fair assumption that it will not complete
1308 * within our relatively short timeout.
1310 if (!i915_request_is_running(rq))
1314 * When waiting for high frequency requests, e.g. during synchronous
1315 * rendering split between the CPU and GPU, the finite amount of time
1316 * required to set up the irq and wait upon it limits the response
1317 * rate. By busywaiting on the request completion for a short while we
1318 * can service the high frequency waits as quick as possible. However,
1319 * if it is a slow request, we want to sleep as quickly as possible.
1320 * The tradeoff between waiting and sleeping is roughly the time it
1321 * takes to sleep on a request, on the order of a microsecond.
1324 timeout_us += local_clock_us(&cpu);
1326 if (i915_request_completed(rq))
1329 if (signal_pending_state(state, current))
1332 if (busywait_stop(timeout_us, cpu))
1336 } while (!need_resched());
1341 struct request_wait {
1342 struct dma_fence_cb cb;
1343 struct task_struct *tsk;
1346 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1348 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1350 wake_up_process(wait->tsk);
1354 * i915_request_wait - wait until execution of request has finished
1355 * @rq: the request to wait upon
1356 * @flags: how to wait
1357 * @timeout: how long to wait in jiffies
1359 * i915_request_wait() waits for the request to be completed, for a
1360 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1363 * Returns the remaining time (in jiffies) if the request completed, which may
1364 * be zero or -ETIME if the request is unfinished after the timeout expires.
1365 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1366 * pending before the request completes.
1368 long i915_request_wait(struct i915_request *rq,
1372 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1373 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1374 struct request_wait wait;
1377 GEM_BUG_ON(timeout < 0);
1379 if (dma_fence_is_signaled(&rq->fence))
1385 trace_i915_request_wait_begin(rq, flags);
1388 * We must never wait on the GPU while holding a lock as we
1389 * may need to perform a GPU reset. So while we don't need to
1390 * serialise wait/reset with an explicit lock, we do want
1391 * lockdep to detect potential dependency cycles.
1393 mutex_acquire(&rq->i915->gpu_error.wedge_mutex.dep_map,
1397 * Optimistic spin before touching IRQs.
1399 * We may use a rather large value here to offset the penalty of
1400 * switching away from the active task. Frequently, the client will
1401 * wait upon an old swapbuffer to throttle itself to remain within a
1402 * frame of the gpu. If the client is running in lockstep with the gpu,
1403 * then it should not be waiting long at all, and a sleep now will incur
1404 * extra scheduler latency in producing the next frame. To try to
1405 * avoid adding the cost of enabling/disabling the interrupt to the
1406 * short wait, we first spin to see if the request would have completed
1407 * in the time taken to setup the interrupt.
1409 * We need upto 5us to enable the irq, and upto 20us to hide the
1410 * scheduler latency of a context switch, ignoring the secondary
1411 * impacts from a context switch such as cache eviction.
1413 * The scheme used for low-latency IO is called "hybrid interrupt
1414 * polling". The suggestion there is to sleep until just before you
1415 * expect to be woken by the device interrupt and then poll for its
1416 * completion. That requires having a good predictor for the request
1417 * duration, which we currently lack.
1419 if (CONFIG_DRM_I915_SPIN_REQUEST &&
1420 __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
1421 dma_fence_signal(&rq->fence);
1426 * This client is about to stall waiting for the GPU. In many cases
1427 * this is undesirable and limits the throughput of the system, as
1428 * many clients cannot continue processing user input/output whilst
1429 * blocked. RPS autotuning may take tens of milliseconds to respond
1430 * to the GPU load and thus incurs additional latency for the client.
1431 * We can circumvent that by promoting the GPU frequency to maximum
1432 * before we sleep. This makes the GPU throttle up much more quickly
1433 * (good for benchmarks and user experience, e.g. window animations),
1434 * but at a cost of spending more power processing the workload
1435 * (bad for battery).
1437 if (flags & I915_WAIT_PRIORITY) {
1438 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1440 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1444 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1448 set_current_state(state);
1450 if (i915_request_completed(rq))
1453 if (signal_pending_state(state, current)) {
1454 timeout = -ERESTARTSYS;
1463 timeout = io_schedule_timeout(timeout);
1465 __set_current_state(TASK_RUNNING);
1467 dma_fence_remove_callback(&rq->fence, &wait.cb);
1470 mutex_release(&rq->i915->gpu_error.wedge_mutex.dep_map, 0, _THIS_IP_);
1471 trace_i915_request_wait_end(rq);
1475 bool i915_retire_requests(struct drm_i915_private *i915)
1477 struct intel_ring *ring, *tmp;
1479 lockdep_assert_held(&i915->drm.struct_mutex);
1481 list_for_each_entry_safe(ring, tmp,
1482 &i915->gt.active_rings, active_link) {
1483 intel_ring_get(ring); /* last rq holds reference! */
1484 ring_retire_requests(ring);
1485 intel_ring_put(ring);
1488 return !list_empty(&i915->gt.active_rings);
1491 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1492 #include "selftests/mock_request.c"
1493 #include "selftests/i915_request.c"
1496 static void i915_global_request_shrink(void)
1498 kmem_cache_shrink(global.slab_dependencies);
1499 kmem_cache_shrink(global.slab_execute_cbs);
1500 kmem_cache_shrink(global.slab_requests);
1503 static void i915_global_request_exit(void)
1505 kmem_cache_destroy(global.slab_dependencies);
1506 kmem_cache_destroy(global.slab_execute_cbs);
1507 kmem_cache_destroy(global.slab_requests);
1510 static struct i915_global_request global = { {
1511 .shrink = i915_global_request_shrink,
1512 .exit = i915_global_request_exit,
1515 int __init i915_global_request_init(void)
1517 global.slab_requests = KMEM_CACHE(i915_request,
1518 SLAB_HWCACHE_ALIGN |
1519 SLAB_RECLAIM_ACCOUNT |
1520 SLAB_TYPESAFE_BY_RCU);
1521 if (!global.slab_requests)
1524 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1525 SLAB_HWCACHE_ALIGN |
1526 SLAB_RECLAIM_ACCOUNT |
1527 SLAB_TYPESAFE_BY_RCU);
1528 if (!global.slab_execute_cbs)
1531 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1532 SLAB_HWCACHE_ALIGN |
1533 SLAB_RECLAIM_ACCOUNT);
1534 if (!global.slab_dependencies)
1535 goto err_execute_cbs;
1537 i915_global_register(&global.base);
1541 kmem_cache_destroy(global.slab_execute_cbs);
1543 kmem_cache_destroy(global.slab_requests);