2 * Copyright © 2008-2015 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
34 #include "gt/intel_ring.h"
35 #include "gt/intel_rps.h"
37 #include "i915_active.h"
39 #include "i915_globals.h"
40 #include "i915_trace.h"
44 struct list_head link;
46 struct i915_sw_fence *fence;
47 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
48 struct i915_request *signal;
51 static struct i915_global_request {
52 struct i915_global base;
53 struct kmem_cache *slab_requests;
54 struct kmem_cache *slab_execute_cbs;
57 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
59 return dev_name(to_request(fence)->i915->drm.dev);
62 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
64 const struct i915_gem_context *ctx;
67 * The timeline struct (as part of the ppgtt underneath a context)
68 * may be freed when the request is no longer in use by the GPU.
69 * We could extend the life of a context to beyond that of all
70 * fences, possibly keeping the hw resource around indefinitely,
71 * or we just give them a false name. Since
72 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
73 * lie seems justifiable.
75 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
78 ctx = i915_request_gem_context(to_request(fence));
80 return "[" DRIVER_NAME "]";
85 static bool i915_fence_signaled(struct dma_fence *fence)
87 return i915_request_completed(to_request(fence));
90 static bool i915_fence_enable_signaling(struct dma_fence *fence)
92 return i915_request_enable_breadcrumb(to_request(fence));
95 static signed long i915_fence_wait(struct dma_fence *fence,
99 return i915_request_wait(to_request(fence),
100 interruptible | I915_WAIT_PRIORITY,
104 static void i915_fence_release(struct dma_fence *fence)
106 struct i915_request *rq = to_request(fence);
109 * The request is put onto a RCU freelist (i.e. the address
110 * is immediately reused), mark the fences as being freed now.
111 * Otherwise the debugobjects for the fences are only marked as
112 * freed when the slab cache itself is freed, and so we would get
113 * caught trying to reuse dead objects.
115 i915_sw_fence_fini(&rq->submit);
116 i915_sw_fence_fini(&rq->semaphore);
118 kmem_cache_free(global.slab_requests, rq);
121 const struct dma_fence_ops i915_fence_ops = {
122 .get_driver_name = i915_fence_get_driver_name,
123 .get_timeline_name = i915_fence_get_timeline_name,
124 .enable_signaling = i915_fence_enable_signaling,
125 .signaled = i915_fence_signaled,
126 .wait = i915_fence_wait,
127 .release = i915_fence_release,
130 static void irq_execute_cb(struct irq_work *wrk)
132 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
134 i915_sw_fence_complete(cb->fence);
135 kmem_cache_free(global.slab_execute_cbs, cb);
138 static void irq_execute_cb_hook(struct irq_work *wrk)
140 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
142 cb->hook(container_of(cb->fence, struct i915_request, submit),
144 i915_request_put(cb->signal);
149 static void __notify_execute_cb(struct i915_request *rq)
151 struct execute_cb *cb;
153 lockdep_assert_held(&rq->lock);
155 if (list_empty(&rq->execute_cb))
158 list_for_each_entry(cb, &rq->execute_cb, link)
159 irq_work_queue(&cb->work);
162 * XXX Rollback on __i915_request_unsubmit()
164 * In the future, perhaps when we have an active time-slicing scheduler,
165 * it will be interesting to unsubmit parallel execution and remove
166 * busywaits from the GPU until their master is restarted. This is
167 * quite hairy, we have to carefully rollback the fence and do a
168 * preempt-to-idle cycle on the target engine, all the while the
169 * master execute_cb may refire.
171 INIT_LIST_HEAD(&rq->execute_cb);
175 remove_from_client(struct i915_request *request)
177 struct drm_i915_file_private *file_priv;
179 if (!READ_ONCE(request->file_priv))
183 file_priv = xchg(&request->file_priv, NULL);
185 spin_lock(&file_priv->mm.lock);
186 list_del(&request->client_link);
187 spin_unlock(&file_priv->mm.lock);
192 static void free_capture_list(struct i915_request *request)
194 struct i915_capture_list *capture;
196 capture = fetch_and_zero(&request->capture_list);
198 struct i915_capture_list *next = capture->next;
205 static void __i915_request_fill(struct i915_request *rq, u8 val)
207 void *vaddr = rq->ring->vaddr;
211 if (rq->postfix < head) {
212 memset(vaddr + head, val, rq->ring->size - head);
215 memset(vaddr + head, val, rq->postfix - head);
218 static void remove_from_engine(struct i915_request *rq)
220 struct intel_engine_cs *engine, *locked;
223 * Virtual engines complicate acquiring the engine timeline lock,
224 * as their rq->engine pointer is not stable until under that
225 * engine lock. The simple ploy we use is to take the lock then
226 * check that the rq still belongs to the newly locked engine.
228 locked = READ_ONCE(rq->engine);
229 spin_lock_irq(&locked->active.lock);
230 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
231 spin_unlock(&locked->active.lock);
232 spin_lock(&engine->active.lock);
235 list_del_init(&rq->sched.link);
236 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
237 clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
238 spin_unlock_irq(&locked->active.lock);
241 bool i915_request_retire(struct i915_request *rq)
243 if (!i915_request_completed(rq))
248 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
249 trace_i915_request_retire(rq);
252 * We know the GPU must have read the request to have
253 * sent us the seqno + interrupt, so use the position
254 * of tail of the request to update the last known position
257 * Note this requires that we are always called in request
260 GEM_BUG_ON(!list_is_first(&rq->link,
261 &i915_request_timeline(rq)->requests));
262 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
263 /* Poison before we release our space in the ring */
264 __i915_request_fill(rq, POISON_FREE);
265 rq->ring->head = rq->postfix;
268 * We only loosely track inflight requests across preemption,
269 * and so we may find ourselves attempting to retire a _completed_
270 * request that we have removed from the HW and put back on a run
273 remove_from_engine(rq);
275 spin_lock_irq(&rq->lock);
276 i915_request_mark_complete(rq);
277 if (!i915_request_signaled(rq))
278 dma_fence_signal_locked(&rq->fence);
279 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
280 i915_request_cancel_breadcrumb(rq);
281 if (i915_request_has_waitboost(rq)) {
282 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
283 atomic_dec(&rq->engine->gt->rps.num_waiters);
285 if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
286 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
287 __notify_execute_cb(rq);
289 GEM_BUG_ON(!list_empty(&rq->execute_cb));
290 spin_unlock_irq(&rq->lock);
292 remove_from_client(rq);
293 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
295 intel_context_exit(rq->context);
296 intel_context_unpin(rq->context);
298 free_capture_list(rq);
299 i915_sched_node_fini(&rq->sched);
300 i915_request_put(rq);
305 void i915_request_retire_upto(struct i915_request *rq)
307 struct intel_timeline * const tl = i915_request_timeline(rq);
308 struct i915_request *tmp;
312 GEM_BUG_ON(!i915_request_completed(rq));
315 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
316 } while (i915_request_retire(tmp) && tmp != rq);
320 __await_execution(struct i915_request *rq,
321 struct i915_request *signal,
322 void (*hook)(struct i915_request *rq,
323 struct dma_fence *signal),
326 struct execute_cb *cb;
328 if (i915_request_is_active(signal)) {
330 hook(rq, &signal->fence);
334 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
338 cb->fence = &rq->submit;
339 i915_sw_fence_await(cb->fence);
340 init_irq_work(&cb->work, irq_execute_cb);
344 cb->signal = i915_request_get(signal);
345 cb->work.func = irq_execute_cb_hook;
348 spin_lock_irq(&signal->lock);
349 if (i915_request_is_active(signal)) {
351 hook(rq, &signal->fence);
352 i915_request_put(signal);
354 i915_sw_fence_complete(cb->fence);
355 kmem_cache_free(global.slab_execute_cbs, cb);
357 list_add_tail(&cb->link, &signal->execute_cb);
359 spin_unlock_irq(&signal->lock);
361 /* Copy across semaphore status as we need the same behaviour */
362 rq->sched.flags |= signal->sched.flags;
366 static bool fatal_error(int error)
369 case 0: /* not an error! */
370 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
371 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
378 void __i915_request_skip(struct i915_request *rq)
380 GEM_BUG_ON(!fatal_error(rq->fence.error));
382 if (rq->infix == rq->postfix)
386 * As this request likely depends on state from the lost
387 * context, clear out all the user operations leaving the
388 * breadcrumb at the end (so we get the fence notifications).
390 __i915_request_fill(rq, 0);
391 rq->infix = rq->postfix;
394 void i915_request_set_error_once(struct i915_request *rq, int error)
398 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
400 if (i915_request_signaled(rq))
403 old = READ_ONCE(rq->fence.error);
405 if (fatal_error(old))
407 } while (!try_cmpxchg(&rq->fence.error, &old, error));
410 bool __i915_request_submit(struct i915_request *request)
412 struct intel_engine_cs *engine = request->engine;
415 RQ_TRACE(request, "\n");
417 GEM_BUG_ON(!irqs_disabled());
418 lockdep_assert_held(&engine->active.lock);
421 * With the advent of preempt-to-busy, we frequently encounter
422 * requests that we have unsubmitted from HW, but left running
423 * until the next ack and so have completed in the meantime. On
424 * resubmission of that completed request, we can skip
425 * updating the payload, and execlists can even skip submitting
428 * We must remove the request from the caller's priority queue,
429 * and the caller must only call us when the request is in their
430 * priority queue, under the active.lock. This ensures that the
431 * request has *not* yet been retired and we can safely move
432 * the request into the engine->active.list where it will be
433 * dropped upon retiring. (Otherwise if resubmit a *retired*
434 * request, this would be a horrible use-after-free.)
436 if (i915_request_completed(request))
439 if (unlikely(intel_context_is_banned(request->context)))
440 i915_request_set_error_once(request, -EIO);
441 if (unlikely(fatal_error(request->fence.error)))
442 __i915_request_skip(request);
445 * Are we using semaphores when the gpu is already saturated?
447 * Using semaphores incurs a cost in having the GPU poll a
448 * memory location, busywaiting for it to change. The continual
449 * memory reads can have a noticeable impact on the rest of the
450 * system with the extra bus traffic, stalling the cpu as it too
451 * tries to access memory across the bus (perf stat -e bus-cycles).
453 * If we installed a semaphore on this request and we only submit
454 * the request after the signaler completed, that indicates the
455 * system is overloaded and using semaphores at this time only
456 * increases the amount of work we are doing. If so, we disable
457 * further use of semaphores until we are idle again, whence we
458 * optimistically try again.
460 if (request->sched.semaphores &&
461 i915_sw_fence_signaled(&request->semaphore))
462 engine->saturated |= request->sched.semaphores;
464 engine->emit_fini_breadcrumb(request,
465 request->ring->vaddr + request->postfix);
467 trace_i915_request_execute(request);
471 xfer: /* We may be recursing from the signal callback of another i915 fence */
472 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
474 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
475 list_move_tail(&request->sched.link, &engine->active.requests);
476 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
479 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
480 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
481 !i915_request_enable_breadcrumb(request))
482 intel_engine_signal_breadcrumbs(engine);
484 __notify_execute_cb(request);
486 spin_unlock(&request->lock);
491 void i915_request_submit(struct i915_request *request)
493 struct intel_engine_cs *engine = request->engine;
496 /* Will be called from irq-context when using foreign fences. */
497 spin_lock_irqsave(&engine->active.lock, flags);
499 __i915_request_submit(request);
501 spin_unlock_irqrestore(&engine->active.lock, flags);
504 void __i915_request_unsubmit(struct i915_request *request)
506 struct intel_engine_cs *engine = request->engine;
508 RQ_TRACE(request, "\n");
510 GEM_BUG_ON(!irqs_disabled());
511 lockdep_assert_held(&engine->active.lock);
514 * Only unwind in reverse order, required so that the per-context list
515 * is kept in seqno/ring order.
518 /* We may be recursing from the signal callback of another i915 fence */
519 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
521 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
522 i915_request_cancel_breadcrumb(request);
524 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
525 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
527 spin_unlock(&request->lock);
529 /* We've already spun, don't charge on resubmitting. */
530 if (request->sched.semaphores && i915_request_started(request)) {
531 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
532 request->sched.semaphores = 0;
536 * We don't need to wake_up any waiters on request->execute, they
537 * will get woken by any other event or us re-adding this request
538 * to the engine timeline (__i915_request_submit()). The waiters
539 * should be quite adapt at finding that the request now has a new
540 * global_seqno to the one they went to sleep on.
544 void i915_request_unsubmit(struct i915_request *request)
546 struct intel_engine_cs *engine = request->engine;
549 /* Will be called from irq-context when using foreign fences. */
550 spin_lock_irqsave(&engine->active.lock, flags);
552 __i915_request_unsubmit(request);
554 spin_unlock_irqrestore(&engine->active.lock, flags);
557 static int __i915_sw_fence_call
558 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
560 struct i915_request *request =
561 container_of(fence, typeof(*request), submit);
565 trace_i915_request_submit(request);
567 if (unlikely(fence->error))
568 i915_request_set_error_once(request, fence->error);
571 * We need to serialize use of the submit_request() callback
572 * with its hotplugging performed during an emergency
573 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
574 * critical section in order to force i915_gem_set_wedged() to
575 * wait until the submit_request() is completed before
579 request->engine->submit_request(request);
584 i915_request_put(request);
591 static int __i915_sw_fence_call
592 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
594 struct i915_request *request =
595 container_of(fence, typeof(*request), semaphore);
599 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
603 i915_request_put(request);
610 static void retire_requests(struct intel_timeline *tl)
612 struct i915_request *rq, *rn;
614 list_for_each_entry_safe(rq, rn, &tl->requests, link)
615 if (!i915_request_retire(rq))
619 static noinline struct i915_request *
620 request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
622 struct i915_request *rq;
624 if (list_empty(&tl->requests))
627 if (!gfpflags_allow_blocking(gfp))
630 /* Move our oldest request to the slab-cache (if not in use!) */
631 rq = list_first_entry(&tl->requests, typeof(*rq), link);
632 i915_request_retire(rq);
634 rq = kmem_cache_alloc(global.slab_requests,
635 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
639 /* Ratelimit ourselves to prevent oom from malicious clients */
640 rq = list_last_entry(&tl->requests, typeof(*rq), link);
641 cond_synchronize_rcu(rq->rcustate);
643 /* Retire our old requests in the hope that we free some */
647 return kmem_cache_alloc(global.slab_requests, gfp);
650 static void __i915_request_ctor(void *arg)
652 struct i915_request *rq = arg;
654 spin_lock_init(&rq->lock);
655 i915_sched_node_init(&rq->sched);
656 i915_sw_fence_init(&rq->submit, submit_notify);
657 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
659 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
661 rq->file_priv = NULL;
662 rq->capture_list = NULL;
664 INIT_LIST_HEAD(&rq->execute_cb);
667 struct i915_request *
668 __i915_request_create(struct intel_context *ce, gfp_t gfp)
670 struct intel_timeline *tl = ce->timeline;
671 struct i915_request *rq;
675 might_sleep_if(gfpflags_allow_blocking(gfp));
677 /* Check that the caller provided an already pinned context */
678 __intel_context_pin(ce);
681 * Beware: Dragons be flying overhead.
683 * We use RCU to look up requests in flight. The lookups may
684 * race with the request being allocated from the slab freelist.
685 * That is the request we are writing to here, may be in the process
686 * of being read by __i915_active_request_get_rcu(). As such,
687 * we have to be very careful when overwriting the contents. During
688 * the RCU lookup, we change chase the request->engine pointer,
689 * read the request->global_seqno and increment the reference count.
691 * The reference count is incremented atomically. If it is zero,
692 * the lookup knows the request is unallocated and complete. Otherwise,
693 * it is either still in use, or has been reallocated and reset
694 * with dma_fence_init(). This increment is safe for release as we
695 * check that the request we have a reference to and matches the active
698 * Before we increment the refcount, we chase the request->engine
699 * pointer. We must not call kmem_cache_zalloc() or else we set
700 * that pointer to NULL and cause a crash during the lookup. If
701 * we see the request is completed (based on the value of the
702 * old engine and seqno), the lookup is complete and reports NULL.
703 * If we decide the request is not completed (new engine or seqno),
704 * then we grab a reference and double check that it is still the
705 * active request - which it won't be and restart the lookup.
707 * Do not use kmem_cache_zalloc() here!
709 rq = kmem_cache_alloc(global.slab_requests,
710 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
712 rq = request_alloc_slow(tl, gfp);
719 rq->i915 = ce->engine->i915;
721 rq->engine = ce->engine;
723 rq->execution_mask = ce->engine->mask;
725 kref_init(&rq->fence.refcount);
728 INIT_LIST_HEAD(&rq->fence.cb_list);
730 ret = intel_timeline_get_seqno(tl, rq, &seqno);
734 rq->fence.context = tl->fence_context;
735 rq->fence.seqno = seqno;
737 RCU_INIT_POINTER(rq->timeline, tl);
738 RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
739 rq->hwsp_seqno = tl->hwsp_seqno;
740 GEM_BUG_ON(i915_request_completed(rq));
742 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
744 /* We bump the ref for the fence chain */
745 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
746 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
748 i915_sched_node_reinit(&rq->sched);
750 /* No zalloc, everything must be cleared after use */
752 GEM_BUG_ON(rq->file_priv);
753 GEM_BUG_ON(rq->capture_list);
754 GEM_BUG_ON(!list_empty(&rq->execute_cb));
757 * Reserve space in the ring buffer for all the commands required to
758 * eventually emit this request. This is to guarantee that the
759 * i915_request_add() call can't fail. Note that the reserve may need
760 * to be redone if the request is not actually submitted straight
761 * away, e.g. because a GPU scheduler has deferred it.
763 * Note that due to how we add reserved_space to intel_ring_begin()
764 * we need to double our request to ensure that if we need to wrap
765 * around inside i915_request_add() there is sufficient space at
766 * the beginning of the ring as well.
769 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
772 * Record the position of the start of the request so that
773 * should we detect the updated seqno part-way through the
774 * GPU processing the request, we never over-estimate the
775 * position of the head.
777 rq->head = rq->ring->emit;
779 ret = rq->engine->request_alloc(rq);
783 rq->infix = rq->ring->emit; /* end of header; start of user payload */
785 intel_context_mark_active(ce);
786 list_add_tail_rcu(&rq->link, &tl->requests);
791 ce->ring->emit = rq->head;
793 /* Make sure we didn't add ourselves to external state before freeing */
794 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
795 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
798 kmem_cache_free(global.slab_requests, rq);
800 intel_context_unpin(ce);
804 struct i915_request *
805 i915_request_create(struct intel_context *ce)
807 struct i915_request *rq;
808 struct intel_timeline *tl;
810 tl = intel_context_timeline_lock(ce);
814 /* Move our oldest request to the slab-cache (if not in use!) */
815 rq = list_first_entry(&tl->requests, typeof(*rq), link);
816 if (!list_is_last(&rq->link, &tl->requests))
817 i915_request_retire(rq);
819 intel_context_enter(ce);
820 rq = __i915_request_create(ce, GFP_KERNEL);
821 intel_context_exit(ce); /* active reference transferred to request */
825 /* Check that we do not interrupt ourselves with a new request */
826 rq->cookie = lockdep_pin_lock(&tl->mutex);
831 intel_context_timeline_unlock(tl);
836 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
838 struct dma_fence *fence;
841 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
844 if (i915_request_started(signal))
849 spin_lock_irq(&signal->lock);
851 struct list_head *pos = READ_ONCE(signal->link.prev);
852 struct i915_request *prev;
854 /* Confirm signal has not been retired, the link is valid */
855 if (unlikely(i915_request_started(signal)))
858 /* Is signal the earliest request on its timeline? */
859 if (pos == &rcu_dereference(signal->timeline)->requests)
863 * Peek at the request before us in the timeline. That
864 * request will only be valid before it is retired, so
865 * after acquiring a reference to it, confirm that it is
866 * still part of the signaler's timeline.
868 prev = list_entry(pos, typeof(*prev), link);
869 if (!i915_request_get_rcu(prev))
872 /* After the strong barrier, confirm prev is still attached */
873 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
874 i915_request_put(prev);
878 fence = &prev->fence;
880 spin_unlock_irq(&signal->lock);
886 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
887 err = i915_sw_fence_await_dma_fence(&rq->submit,
890 dma_fence_put(fence);
895 static intel_engine_mask_t
896 already_busywaiting(struct i915_request *rq)
899 * Polling a semaphore causes bus traffic, delaying other users of
900 * both the GPU and CPU. We want to limit the impact on others,
901 * while taking advantage of early submission to reduce GPU
902 * latency. Therefore we restrict ourselves to not using more
903 * than one semaphore from each source, and not using a semaphore
904 * if we have detected the engine is saturated (i.e. would not be
905 * submitted early and cause bus traffic reading an already passed
908 * See the are-we-too-late? check in __i915_request_submit().
910 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
914 __emit_semaphore_wait(struct i915_request *to,
915 struct i915_request *from,
918 const int has_token = INTEL_GEN(to->i915) >= 12;
923 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
925 /* We need to pin the signaler's HWSP until we are finished reading. */
926 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
934 cs = intel_ring_begin(to, len);
939 * Using greater-than-or-equal here means we have to worry
940 * about seqno wraparound. To side step that issue, we swap
941 * the timeline HWSP upon wrapping, so that everyone listening
942 * for the old (pre-wrap) values do not see the much smaller
943 * (post-wrap) values than they were expecting (and so wait
946 *cs++ = (MI_SEMAPHORE_WAIT |
947 MI_SEMAPHORE_GLOBAL_GTT |
949 MI_SEMAPHORE_SAD_GTE_SDD) +
959 intel_ring_advance(to, cs);
964 emit_semaphore_wait(struct i915_request *to,
965 struct i915_request *from,
968 if (!intel_context_use_semaphores(to->context))
971 if (!rcu_access_pointer(from->hwsp_cacheline))
974 /* Just emit the first semaphore we see as request space is limited. */
975 if (already_busywaiting(to) & from->engine->mask)
978 if (i915_request_await_start(to, from) < 0)
981 /* Only submit our spinner after the signaler is running! */
982 if (__await_execution(to, from, NULL, gfp))
985 if (__emit_semaphore_wait(to, from, from->fence.seqno))
988 to->sched.semaphores |= from->engine->mask;
989 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
993 return i915_sw_fence_await_dma_fence(&to->submit,
999 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1003 GEM_BUG_ON(to == from);
1004 GEM_BUG_ON(to->timeline == from->timeline);
1006 if (i915_request_completed(from))
1009 if (to->engine->schedule) {
1010 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
1015 if (to->engine == from->engine)
1016 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
1020 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1024 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
1025 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
1036 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1038 struct dma_fence **child = &fence;
1039 unsigned int nchild = 1;
1043 * Note that if the fence-array was created in signal-on-any mode,
1044 * we should *not* decompose it into its individual fences. However,
1045 * we don't currently store which mode the fence-array is operating
1046 * in. Fortunately, the only user of signal-on-any is private to
1047 * amdgpu and we should not see any incoming fence-array from
1048 * sync-file being in signal-on-any mode.
1050 if (dma_fence_is_array(fence)) {
1051 struct dma_fence_array *array = to_dma_fence_array(fence);
1053 child = array->fences;
1054 nchild = array->num_fences;
1055 GEM_BUG_ON(!nchild);
1060 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1061 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1066 * Requests on the same timeline are explicitly ordered, along
1067 * with their dependencies, by i915_request_add() which ensures
1068 * that requests are submitted in-order through each ring.
1070 if (fence->context == rq->fence.context)
1073 /* Squash repeated waits to the same timelines */
1074 if (fence->context &&
1075 intel_timeline_sync_is_later(i915_request_timeline(rq),
1079 if (dma_fence_is_i915(fence))
1080 ret = i915_request_await_request(rq, to_request(fence));
1082 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1083 fence->context ? I915_FENCE_TIMEOUT : 0,
1088 /* Record the latest fence used against each timeline */
1090 intel_timeline_sync_set(i915_request_timeline(rq),
1097 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1098 struct dma_fence *fence)
1100 return __intel_timeline_sync_is_later(tl,
1105 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1106 const struct dma_fence *fence)
1108 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1112 __i915_request_await_execution(struct i915_request *to,
1113 struct i915_request *from,
1114 void (*hook)(struct i915_request *rq,
1115 struct dma_fence *signal))
1119 GEM_BUG_ON(intel_context_is_barrier(from->context));
1121 /* Submit both requests at the same time */
1122 err = __await_execution(to, from, hook, I915_FENCE_GFP);
1126 /* Squash repeated depenendices to the same timelines */
1127 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1132 * Wait until the start of this request.
1134 * The execution cb fires when we submit the request to HW. But in
1135 * many cases this may be long before the request itself is ready to
1136 * run (consider that we submit 2 requests for the same context, where
1137 * the request of interest is behind an indefinite spinner). So we hook
1138 * up to both to reduce our queues and keep the execution lag minimised
1139 * in the worst case, though we hope that the await_start is elided.
1141 err = i915_request_await_start(to, from);
1146 * Ensure both start together [after all semaphores in signal]
1148 * Now that we are queued to the HW at roughly the same time (thanks
1149 * to the execute cb) and are ready to run at roughly the same time
1150 * (thanks to the await start), our signaler may still be indefinitely
1151 * delayed by waiting on a semaphore from a remote engine. If our
1152 * signaler depends on a semaphore, so indirectly do we, and we do not
1153 * want to start our payload until our signaler also starts theirs.
1156 * However, there is also a second condition for which we need to wait
1157 * for the precise start of the signaler. Consider that the signaler
1158 * was submitted in a chain of requests following another context
1159 * (with just an ordinary intra-engine fence dependency between the
1160 * two). In this case the signaler is queued to HW, but not for
1161 * immediate execution, and so we must wait until it reaches the
1164 if (intel_engine_has_semaphores(to->engine)) {
1165 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1170 /* Couple the dependency tree for PI on this exposed to->fence */
1171 if (to->engine->schedule) {
1172 err = i915_sched_node_add_dependency(&to->sched, &from->sched);
1177 return intel_timeline_sync_set_start(i915_request_timeline(to),
1182 i915_request_await_execution(struct i915_request *rq,
1183 struct dma_fence *fence,
1184 void (*hook)(struct i915_request *rq,
1185 struct dma_fence *signal))
1187 struct dma_fence **child = &fence;
1188 unsigned int nchild = 1;
1191 if (dma_fence_is_array(fence)) {
1192 struct dma_fence_array *array = to_dma_fence_array(fence);
1194 /* XXX Error for signal-on-any fence arrays */
1196 child = array->fences;
1197 nchild = array->num_fences;
1198 GEM_BUG_ON(!nchild);
1203 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1204 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1209 * We don't squash repeated fence dependencies here as we
1210 * want to run our callback in all cases.
1213 if (dma_fence_is_i915(fence))
1214 ret = __i915_request_await_execution(rq,
1218 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1229 * i915_request_await_object - set this request to (async) wait upon a bo
1230 * @to: request we are wishing to use
1231 * @obj: object which may be in use on another ring.
1232 * @write: whether the wait is on behalf of a writer
1234 * This code is meant to abstract object synchronization with the GPU.
1235 * Conceptually we serialise writes between engines inside the GPU.
1236 * We only allow one engine to write into a buffer at any time, but
1237 * multiple readers. To ensure each has a coherent view of memory, we must:
1239 * - If there is an outstanding write request to the object, the new
1240 * request must wait for it to complete (either CPU or in hw, requests
1241 * on the same ring will be naturally ordered).
1243 * - If we are a write request (pending_write_domain is set), the new
1244 * request must wait for outstanding read requests to complete.
1246 * Returns 0 if successful, else propagates up the lower layer error.
1249 i915_request_await_object(struct i915_request *to,
1250 struct drm_i915_gem_object *obj,
1253 struct dma_fence *excl;
1257 struct dma_fence **shared;
1258 unsigned int count, i;
1260 ret = dma_resv_get_fences_rcu(obj->base.resv,
1261 &excl, &count, &shared);
1265 for (i = 0; i < count; i++) {
1266 ret = i915_request_await_dma_fence(to, shared[i]);
1270 dma_fence_put(shared[i]);
1273 for (; i < count; i++)
1274 dma_fence_put(shared[i]);
1277 excl = dma_resv_get_excl_rcu(obj->base.resv);
1282 ret = i915_request_await_dma_fence(to, excl);
1284 dma_fence_put(excl);
1290 static struct i915_request *
1291 __i915_request_add_to_timeline(struct i915_request *rq)
1293 struct intel_timeline *timeline = i915_request_timeline(rq);
1294 struct i915_request *prev;
1297 * Dependency tracking and request ordering along the timeline
1298 * is special cased so that we can eliminate redundant ordering
1299 * operations while building the request (we know that the timeline
1300 * itself is ordered, and here we guarantee it).
1302 * As we know we will need to emit tracking along the timeline,
1303 * we embed the hooks into our request struct -- at the cost of
1304 * having to have specialised no-allocation interfaces (which will
1305 * be beneficial elsewhere).
1307 * A second benefit to open-coding i915_request_await_request is
1308 * that we can apply a slight variant of the rules specialised
1309 * for timelines that jump between engines (such as virtual engines).
1310 * If we consider the case of virtual engine, we must emit a dma-fence
1311 * to prevent scheduling of the second request until the first is
1312 * complete (to maximise our greedy late load balancing) and this
1313 * precludes optimising to use semaphores serialisation of a single
1314 * timeline across engines.
1316 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1318 if (prev && !i915_request_completed(prev)) {
1320 * The requests are supposed to be kept in order. However,
1321 * we need to be wary in case the timeline->last_request
1322 * is used as a barrier for external modification to this
1325 GEM_BUG_ON(prev->context == rq->context &&
1326 i915_seqno_passed(prev->fence.seqno,
1329 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1330 i915_sw_fence_await_sw_fence(&rq->submit,
1334 __i915_sw_fence_await_dma_fence(&rq->submit,
1337 if (rq->engine->schedule)
1338 __i915_sched_node_add_dependency(&rq->sched,
1345 * Make sure that no request gazumped us - if it was allocated after
1346 * our i915_request_alloc() and called __i915_request_add() before
1347 * us, the timeline will hold its seqno which is later than ours.
1349 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1355 * NB: This function is not allowed to fail. Doing so would mean the the
1356 * request is not being tracked for completion but the work itself is
1357 * going to happen on the hardware. This would be a Bad Thing(tm).
1359 struct i915_request *__i915_request_commit(struct i915_request *rq)
1361 struct intel_engine_cs *engine = rq->engine;
1362 struct intel_ring *ring = rq->ring;
1368 * To ensure that this call will not fail, space for its emissions
1369 * should already have been reserved in the ring buffer. Let the ring
1370 * know that it is time to use that space up.
1372 GEM_BUG_ON(rq->reserved_space > ring->space);
1373 rq->reserved_space = 0;
1374 rq->emitted_jiffies = jiffies;
1377 * Record the position of the start of the breadcrumb so that
1378 * should we detect the updated seqno part-way through the
1379 * GPU processing the request, we never over-estimate the
1380 * position of the ring's HEAD.
1382 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1383 GEM_BUG_ON(IS_ERR(cs));
1384 rq->postfix = intel_ring_offset(rq, cs);
1386 return __i915_request_add_to_timeline(rq);
1389 void __i915_request_queue(struct i915_request *rq,
1390 const struct i915_sched_attr *attr)
1393 * Let the backend know a new request has arrived that may need
1394 * to adjust the existing execution schedule due to a high priority
1395 * request - i.e. we may want to preempt the current request in order
1396 * to run a high priority dependency chain *before* we can execute this
1399 * This is called before the request is ready to run so that we can
1400 * decide whether to preempt the entire chain so that it is ready to
1401 * run at the earliest possible convenience.
1403 i915_sw_fence_commit(&rq->semaphore);
1404 if (attr && rq->engine->schedule)
1405 rq->engine->schedule(rq, attr);
1406 i915_sw_fence_commit(&rq->submit);
1409 void i915_request_add(struct i915_request *rq)
1411 struct intel_timeline * const tl = i915_request_timeline(rq);
1412 struct i915_sched_attr attr = {};
1413 struct i915_gem_context *ctx;
1415 lockdep_assert_held(&tl->mutex);
1416 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1418 trace_i915_request_add(rq);
1419 __i915_request_commit(rq);
1421 /* XXX placeholder for selftests */
1423 ctx = rcu_dereference(rq->context->gem_context);
1428 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1429 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1430 if (list_empty(&rq->sched.signalers_list))
1431 attr.priority |= I915_PRIORITY_WAIT;
1434 __i915_request_queue(rq, &attr);
1435 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1437 mutex_unlock(&tl->mutex);
1440 static unsigned long local_clock_ns(unsigned int *cpu)
1445 * Cheaply and approximately convert from nanoseconds to microseconds.
1446 * The result and subsequent calculations are also defined in the same
1447 * approximate microseconds units. The principal source of timing
1448 * error here is from the simple truncation.
1450 * Note that local_clock() is only defined wrt to the current CPU;
1451 * the comparisons are no longer valid if we switch CPUs. Instead of
1452 * blocking preemption for the entire busywait, we can detect the CPU
1453 * switch and use that as indicator of system load and a reason to
1454 * stop busywaiting, see busywait_stop().
1463 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1465 unsigned int this_cpu;
1467 if (time_after(local_clock_ns(&this_cpu), timeout))
1470 return this_cpu != cpu;
1473 static bool __i915_spin_request(const struct i915_request * const rq, int state)
1475 unsigned long timeout_ns;
1479 * Only wait for the request if we know it is likely to complete.
1481 * We don't track the timestamps around requests, nor the average
1482 * request length, so we do not have a good indicator that this
1483 * request will complete within the timeout. What we do know is the
1484 * order in which requests are executed by the context and so we can
1485 * tell if the request has been started. If the request is not even
1486 * running yet, it is a fair assumption that it will not complete
1487 * within our relatively short timeout.
1489 if (!i915_request_is_running(rq))
1493 * When waiting for high frequency requests, e.g. during synchronous
1494 * rendering split between the CPU and GPU, the finite amount of time
1495 * required to set up the irq and wait upon it limits the response
1496 * rate. By busywaiting on the request completion for a short while we
1497 * can service the high frequency waits as quick as possible. However,
1498 * if it is a slow request, we want to sleep as quickly as possible.
1499 * The tradeoff between waiting and sleeping is roughly the time it
1500 * takes to sleep on a request, on the order of a microsecond.
1503 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1504 timeout_ns += local_clock_ns(&cpu);
1506 if (i915_request_completed(rq))
1509 if (signal_pending_state(state, current))
1512 if (busywait_stop(timeout_ns, cpu))
1516 } while (!need_resched());
1521 struct request_wait {
1522 struct dma_fence_cb cb;
1523 struct task_struct *tsk;
1526 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1528 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1530 wake_up_process(wait->tsk);
1534 * i915_request_wait - wait until execution of request has finished
1535 * @rq: the request to wait upon
1536 * @flags: how to wait
1537 * @timeout: how long to wait in jiffies
1539 * i915_request_wait() waits for the request to be completed, for a
1540 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1543 * Returns the remaining time (in jiffies) if the request completed, which may
1544 * be zero or -ETIME if the request is unfinished after the timeout expires.
1545 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1546 * pending before the request completes.
1548 long i915_request_wait(struct i915_request *rq,
1552 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1553 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1554 struct request_wait wait;
1557 GEM_BUG_ON(timeout < 0);
1559 if (dma_fence_is_signaled(&rq->fence))
1565 trace_i915_request_wait_begin(rq, flags);
1568 * We must never wait on the GPU while holding a lock as we
1569 * may need to perform a GPU reset. So while we don't need to
1570 * serialise wait/reset with an explicit lock, we do want
1571 * lockdep to detect potential dependency cycles.
1573 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1576 * Optimistic spin before touching IRQs.
1578 * We may use a rather large value here to offset the penalty of
1579 * switching away from the active task. Frequently, the client will
1580 * wait upon an old swapbuffer to throttle itself to remain within a
1581 * frame of the gpu. If the client is running in lockstep with the gpu,
1582 * then it should not be waiting long at all, and a sleep now will incur
1583 * extra scheduler latency in producing the next frame. To try to
1584 * avoid adding the cost of enabling/disabling the interrupt to the
1585 * short wait, we first spin to see if the request would have completed
1586 * in the time taken to setup the interrupt.
1588 * We need upto 5us to enable the irq, and upto 20us to hide the
1589 * scheduler latency of a context switch, ignoring the secondary
1590 * impacts from a context switch such as cache eviction.
1592 * The scheme used for low-latency IO is called "hybrid interrupt
1593 * polling". The suggestion there is to sleep until just before you
1594 * expect to be woken by the device interrupt and then poll for its
1595 * completion. That requires having a good predictor for the request
1596 * duration, which we currently lack.
1598 if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) &&
1599 __i915_spin_request(rq, state)) {
1600 dma_fence_signal(&rq->fence);
1605 * This client is about to stall waiting for the GPU. In many cases
1606 * this is undesirable and limits the throughput of the system, as
1607 * many clients cannot continue processing user input/output whilst
1608 * blocked. RPS autotuning may take tens of milliseconds to respond
1609 * to the GPU load and thus incurs additional latency for the client.
1610 * We can circumvent that by promoting the GPU frequency to maximum
1611 * before we sleep. This makes the GPU throttle up much more quickly
1612 * (good for benchmarks and user experience, e.g. window animations),
1613 * but at a cost of spending more power processing the workload
1614 * (bad for battery).
1616 if (flags & I915_WAIT_PRIORITY) {
1617 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1618 intel_rps_boost(rq);
1619 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1623 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1627 set_current_state(state);
1629 if (i915_request_completed(rq)) {
1630 dma_fence_signal(&rq->fence);
1634 intel_engine_flush_submission(rq->engine);
1636 if (signal_pending_state(state, current)) {
1637 timeout = -ERESTARTSYS;
1646 timeout = io_schedule_timeout(timeout);
1648 __set_current_state(TASK_RUNNING);
1650 dma_fence_remove_callback(&rq->fence, &wait.cb);
1653 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1654 trace_i915_request_wait_end(rq);
1658 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1659 #include "selftests/mock_request.c"
1660 #include "selftests/i915_request.c"
1663 static void i915_global_request_shrink(void)
1665 kmem_cache_shrink(global.slab_execute_cbs);
1666 kmem_cache_shrink(global.slab_requests);
1669 static void i915_global_request_exit(void)
1671 kmem_cache_destroy(global.slab_execute_cbs);
1672 kmem_cache_destroy(global.slab_requests);
1675 static struct i915_global_request global = { {
1676 .shrink = i915_global_request_shrink,
1677 .exit = i915_global_request_exit,
1680 int __init i915_global_request_init(void)
1682 global.slab_requests =
1683 kmem_cache_create("i915_request",
1684 sizeof(struct i915_request),
1685 __alignof__(struct i915_request),
1686 SLAB_HWCACHE_ALIGN |
1687 SLAB_RECLAIM_ACCOUNT |
1688 SLAB_TYPESAFE_BY_RCU,
1689 __i915_request_ctor);
1690 if (!global.slab_requests)
1693 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1694 SLAB_HWCACHE_ALIGN |
1695 SLAB_RECLAIM_ACCOUNT |
1696 SLAB_TYPESAFE_BY_RCU);
1697 if (!global.slab_execute_cbs)
1700 i915_global_register(&global.base);
1704 kmem_cache_destroy(global.slab_requests);