2 * Copyright © 2008-2015 Intel Corporation
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25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
33 #include "gem/i915_gem_context.h"
34 #include "gt/intel_breadcrumbs.h"
35 #include "gt/intel_context.h"
36 #include "gt/intel_engine.h"
37 #include "gt/intel_engine_heartbeat.h"
38 #include "gt/intel_gpu_commands.h"
39 #include "gt/intel_reset.h"
40 #include "gt/intel_ring.h"
41 #include "gt/intel_rps.h"
43 #include "i915_active.h"
45 #include "i915_trace.h"
50 struct i915_sw_fence *fence;
51 struct i915_request *signal;
54 static struct kmem_cache *slab_requests;
55 static struct kmem_cache *slab_execute_cbs;
57 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
59 return dev_name(to_request(fence)->engine->i915->drm.dev);
62 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
64 const struct i915_gem_context *ctx;
67 * The timeline struct (as part of the ppgtt underneath a context)
68 * may be freed when the request is no longer in use by the GPU.
69 * We could extend the life of a context to beyond that of all
70 * fences, possibly keeping the hw resource around indefinitely,
71 * or we just give them a false name. Since
72 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
73 * lie seems justifiable.
75 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
78 ctx = i915_request_gem_context(to_request(fence));
80 return "[" DRIVER_NAME "]";
85 static bool i915_fence_signaled(struct dma_fence *fence)
87 return i915_request_completed(to_request(fence));
90 static bool i915_fence_enable_signaling(struct dma_fence *fence)
92 return i915_request_enable_breadcrumb(to_request(fence));
95 static signed long i915_fence_wait(struct dma_fence *fence,
99 return i915_request_wait(to_request(fence),
100 interruptible | I915_WAIT_PRIORITY,
104 struct kmem_cache *i915_request_slab_cache(void)
106 return slab_requests;
109 static void i915_fence_release(struct dma_fence *fence)
111 struct i915_request *rq = to_request(fence);
113 GEM_BUG_ON(rq->guc_prio != GUC_PRIO_INIT &&
114 rq->guc_prio != GUC_PRIO_FINI);
117 * The request is put onto a RCU freelist (i.e. the address
118 * is immediately reused), mark the fences as being freed now.
119 * Otherwise the debugobjects for the fences are only marked as
120 * freed when the slab cache itself is freed, and so we would get
121 * caught trying to reuse dead objects.
123 i915_sw_fence_fini(&rq->submit);
124 i915_sw_fence_fini(&rq->semaphore);
127 * Keep one request on each engine for reserved use under mempressure,
128 * do not use with virtual engines as this really is only needed for
131 if (!intel_engine_is_virtual(rq->engine) &&
132 !cmpxchg(&rq->engine->request_pool, NULL, rq)) {
133 intel_context_put(rq->context);
137 intel_context_put(rq->context);
139 kmem_cache_free(slab_requests, rq);
142 const struct dma_fence_ops i915_fence_ops = {
143 .get_driver_name = i915_fence_get_driver_name,
144 .get_timeline_name = i915_fence_get_timeline_name,
145 .enable_signaling = i915_fence_enable_signaling,
146 .signaled = i915_fence_signaled,
147 .wait = i915_fence_wait,
148 .release = i915_fence_release,
151 static void irq_execute_cb(struct irq_work *wrk)
153 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
155 i915_sw_fence_complete(cb->fence);
156 kmem_cache_free(slab_execute_cbs, cb);
159 static __always_inline void
160 __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
162 struct execute_cb *cb, *cn;
164 if (llist_empty(&rq->execute_cb))
167 llist_for_each_entry_safe(cb, cn,
168 llist_del_all(&rq->execute_cb),
173 static void __notify_execute_cb_irq(struct i915_request *rq)
175 __notify_execute_cb(rq, irq_work_queue);
178 static bool irq_work_imm(struct irq_work *wrk)
184 void i915_request_notify_execute_cb_imm(struct i915_request *rq)
186 __notify_execute_cb(rq, irq_work_imm);
189 static void free_capture_list(struct i915_request *request)
191 struct i915_capture_list *capture;
193 capture = fetch_and_zero(&request->capture_list);
195 struct i915_capture_list *next = capture->next;
202 static void __i915_request_fill(struct i915_request *rq, u8 val)
204 void *vaddr = rq->ring->vaddr;
208 if (rq->postfix < head) {
209 memset(vaddr + head, val, rq->ring->size - head);
212 memset(vaddr + head, val, rq->postfix - head);
216 * i915_request_active_engine
217 * @rq: request to inspect
218 * @active: pointer in which to return the active engine
220 * Fills the currently active engine to the @active pointer if the request
221 * is active and still not completed.
223 * Returns true if request was active or false otherwise.
226 i915_request_active_engine(struct i915_request *rq,
227 struct intel_engine_cs **active)
229 struct intel_engine_cs *engine, *locked;
233 * Serialise with __i915_request_submit() so that it sees
234 * is-banned?, or we know the request is already inflight.
236 * Note that rq->engine is unstable, and so we double
237 * check that we have acquired the lock on the final engine.
239 locked = READ_ONCE(rq->engine);
240 spin_lock_irq(&locked->sched_engine->lock);
241 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
242 spin_unlock(&locked->sched_engine->lock);
244 spin_lock(&locked->sched_engine->lock);
247 if (i915_request_is_active(rq)) {
248 if (!__i915_request_is_complete(rq))
253 spin_unlock_irq(&locked->sched_engine->lock);
258 static void __rq_init_watchdog(struct i915_request *rq)
260 rq->watchdog.timer.function = NULL;
263 static enum hrtimer_restart __rq_watchdog_expired(struct hrtimer *hrtimer)
265 struct i915_request *rq =
266 container_of(hrtimer, struct i915_request, watchdog.timer);
267 struct intel_gt *gt = rq->engine->gt;
269 if (!i915_request_completed(rq)) {
270 if (llist_add(&rq->watchdog.link, >->watchdog.list))
271 schedule_work(>->watchdog.work);
273 i915_request_put(rq);
276 return HRTIMER_NORESTART;
279 static void __rq_arm_watchdog(struct i915_request *rq)
281 struct i915_request_watchdog *wdg = &rq->watchdog;
282 struct intel_context *ce = rq->context;
284 if (!ce->watchdog.timeout_us)
287 i915_request_get(rq);
289 hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
290 wdg->timer.function = __rq_watchdog_expired;
291 hrtimer_start_range_ns(&wdg->timer,
292 ns_to_ktime(ce->watchdog.timeout_us *
298 static void __rq_cancel_watchdog(struct i915_request *rq)
300 struct i915_request_watchdog *wdg = &rq->watchdog;
302 if (wdg->timer.function && hrtimer_try_to_cancel(&wdg->timer) > 0)
303 i915_request_put(rq);
306 bool i915_request_retire(struct i915_request *rq)
308 if (!__i915_request_is_complete(rq))
313 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
314 trace_i915_request_retire(rq);
315 i915_request_mark_complete(rq);
317 __rq_cancel_watchdog(rq);
320 * We know the GPU must have read the request to have
321 * sent us the seqno + interrupt, so use the position
322 * of tail of the request to update the last known position
325 * Note this requires that we are always called in request
328 GEM_BUG_ON(!list_is_first(&rq->link,
329 &i915_request_timeline(rq)->requests));
330 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
331 /* Poison before we release our space in the ring */
332 __i915_request_fill(rq, POISON_FREE);
333 rq->ring->head = rq->postfix;
335 if (!i915_request_signaled(rq)) {
336 spin_lock_irq(&rq->lock);
337 dma_fence_signal_locked(&rq->fence);
338 spin_unlock_irq(&rq->lock);
341 if (test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags))
342 atomic_dec(&rq->engine->gt->rps.num_waiters);
345 * We only loosely track inflight requests across preemption,
346 * and so we may find ourselves attempting to retire a _completed_
347 * request that we have removed from the HW and put back on a run
350 * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
351 * after removing the breadcrumb and signaling it, so that we do not
352 * inadvertently attach the breadcrumb to a completed request.
354 rq->engine->remove_active_request(rq);
355 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
357 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
359 intel_context_exit(rq->context);
360 intel_context_unpin(rq->context);
362 free_capture_list(rq);
363 i915_sched_node_fini(&rq->sched);
364 i915_request_put(rq);
369 void i915_request_retire_upto(struct i915_request *rq)
371 struct intel_timeline * const tl = i915_request_timeline(rq);
372 struct i915_request *tmp;
375 GEM_BUG_ON(!__i915_request_is_complete(rq));
378 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
379 GEM_BUG_ON(!i915_request_completed(tmp));
380 } while (i915_request_retire(tmp) && tmp != rq);
383 static struct i915_request * const *
384 __engine_active(struct intel_engine_cs *engine)
386 return READ_ONCE(engine->execlists.active);
389 static bool __request_in_flight(const struct i915_request *signal)
391 struct i915_request * const *port, *rq;
392 bool inflight = false;
394 if (!i915_request_is_ready(signal))
398 * Even if we have unwound the request, it may still be on
399 * the GPU (preempt-to-busy). If that request is inside an
400 * unpreemptible critical section, it will not be removed. Some
401 * GPU functions may even be stuck waiting for the paired request
402 * (__await_execution) to be submitted and cannot be preempted
403 * until the bond is executing.
405 * As we know that there are always preemption points between
406 * requests, we know that only the currently executing request
407 * may be still active even though we have cleared the flag.
408 * However, we can't rely on our tracking of ELSP[0] to know
409 * which request is currently active and so maybe stuck, as
410 * the tracking maybe an event behind. Instead assume that
411 * if the context is still inflight, then it is still active
412 * even if the active flag has been cleared.
414 * To further complicate matters, if there a pending promotion, the HW
415 * may either perform a context switch to the second inflight execlists,
416 * or it may switch to the pending set of execlists. In the case of the
417 * latter, it may send the ACK and we process the event copying the
418 * pending[] over top of inflight[], _overwriting_ our *active. Since
419 * this implies the HW is arbitrating and not struck in *active, we do
420 * not worry about complete accuracy, but we do require no read/write
421 * tearing of the pointer [the read of the pointer must be valid, even
422 * as the array is being overwritten, for which we require the writes
425 * Note that the read of *execlists->active may race with the promotion
426 * of execlists->pending[] to execlists->inflight[], overwritting
427 * the value at *execlists->active. This is fine. The promotion implies
428 * that we received an ACK from the HW, and so the context is not
429 * stuck -- if we do not see ourselves in *active, the inflight status
430 * is valid. If instead we see ourselves being copied into *active,
431 * we are inflight and may signal the callback.
433 if (!intel_context_inflight(signal->context))
437 for (port = __engine_active(signal->engine);
438 (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
440 if (rq->context == signal->context) {
441 inflight = i915_seqno_passed(rq->fence.seqno,
442 signal->fence.seqno);
452 __await_execution(struct i915_request *rq,
453 struct i915_request *signal,
456 struct execute_cb *cb;
458 if (i915_request_is_active(signal))
461 cb = kmem_cache_alloc(slab_execute_cbs, gfp);
465 cb->fence = &rq->submit;
466 i915_sw_fence_await(cb->fence);
467 init_irq_work(&cb->work, irq_execute_cb);
470 * Register the callback first, then see if the signaler is already
471 * active. This ensures that if we race with the
472 * __notify_execute_cb from i915_request_submit() and we are not
473 * included in that list, we get a second bite of the cherry and
474 * execute it ourselves. After this point, a future
475 * i915_request_submit() will notify us.
477 * In i915_request_retire() we set the ACTIVE bit on a completed
478 * request (then flush the execute_cb). So by registering the
479 * callback first, then checking the ACTIVE bit, we serialise with
480 * the completed/retired request.
482 if (llist_add(&cb->work.node.llist, &signal->execute_cb)) {
483 if (i915_request_is_active(signal) ||
484 __request_in_flight(signal))
485 i915_request_notify_execute_cb_imm(signal);
491 static bool fatal_error(int error)
494 case 0: /* not an error! */
495 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
496 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
503 void __i915_request_skip(struct i915_request *rq)
505 GEM_BUG_ON(!fatal_error(rq->fence.error));
507 if (rq->infix == rq->postfix)
510 RQ_TRACE(rq, "error: %d\n", rq->fence.error);
513 * As this request likely depends on state from the lost
514 * context, clear out all the user operations leaving the
515 * breadcrumb at the end (so we get the fence notifications).
517 __i915_request_fill(rq, 0);
518 rq->infix = rq->postfix;
521 bool i915_request_set_error_once(struct i915_request *rq, int error)
525 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
527 if (i915_request_signaled(rq))
530 old = READ_ONCE(rq->fence.error);
532 if (fatal_error(old))
534 } while (!try_cmpxchg(&rq->fence.error, &old, error));
539 struct i915_request *i915_request_mark_eio(struct i915_request *rq)
541 if (__i915_request_is_complete(rq))
544 GEM_BUG_ON(i915_request_signaled(rq));
546 /* As soon as the request is completed, it may be retired */
547 rq = i915_request_get(rq);
549 i915_request_set_error_once(rq, -EIO);
550 i915_request_mark_complete(rq);
555 bool __i915_request_submit(struct i915_request *request)
557 struct intel_engine_cs *engine = request->engine;
560 RQ_TRACE(request, "\n");
562 GEM_BUG_ON(!irqs_disabled());
563 lockdep_assert_held(&engine->sched_engine->lock);
566 * With the advent of preempt-to-busy, we frequently encounter
567 * requests that we have unsubmitted from HW, but left running
568 * until the next ack and so have completed in the meantime. On
569 * resubmission of that completed request, we can skip
570 * updating the payload, and execlists can even skip submitting
573 * We must remove the request from the caller's priority queue,
574 * and the caller must only call us when the request is in their
575 * priority queue, under the sched_engine->lock. This ensures that the
576 * request has *not* yet been retired and we can safely move
577 * the request into the engine->active.list where it will be
578 * dropped upon retiring. (Otherwise if resubmit a *retired*
579 * request, this would be a horrible use-after-free.)
581 if (__i915_request_is_complete(request)) {
582 list_del_init(&request->sched.link);
586 if (unlikely(intel_context_is_banned(request->context)))
587 i915_request_set_error_once(request, -EIO);
589 if (unlikely(fatal_error(request->fence.error)))
590 __i915_request_skip(request);
593 * Are we using semaphores when the gpu is already saturated?
595 * Using semaphores incurs a cost in having the GPU poll a
596 * memory location, busywaiting for it to change. The continual
597 * memory reads can have a noticeable impact on the rest of the
598 * system with the extra bus traffic, stalling the cpu as it too
599 * tries to access memory across the bus (perf stat -e bus-cycles).
601 * If we installed a semaphore on this request and we only submit
602 * the request after the signaler completed, that indicates the
603 * system is overloaded and using semaphores at this time only
604 * increases the amount of work we are doing. If so, we disable
605 * further use of semaphores until we are idle again, whence we
606 * optimistically try again.
608 if (request->sched.semaphores &&
609 i915_sw_fence_signaled(&request->semaphore))
610 engine->saturated |= request->sched.semaphores;
612 engine->emit_fini_breadcrumb(request,
613 request->ring->vaddr + request->postfix);
615 trace_i915_request_execute(request);
616 if (engine->bump_serial)
617 engine->bump_serial(engine);
623 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
624 engine->add_active_request(request);
626 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
627 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
630 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
632 * In the future, perhaps when we have an active time-slicing scheduler,
633 * it will be interesting to unsubmit parallel execution and remove
634 * busywaits from the GPU until their master is restarted. This is
635 * quite hairy, we have to carefully rollback the fence and do a
636 * preempt-to-idle cycle on the target engine, all the while the
637 * master execute_cb may refire.
639 __notify_execute_cb_irq(request);
641 /* We may be recursing from the signal callback of another i915 fence */
642 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
643 i915_request_enable_breadcrumb(request);
648 void i915_request_submit(struct i915_request *request)
650 struct intel_engine_cs *engine = request->engine;
653 /* Will be called from irq-context when using foreign fences. */
654 spin_lock_irqsave(&engine->sched_engine->lock, flags);
656 __i915_request_submit(request);
658 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
661 void __i915_request_unsubmit(struct i915_request *request)
663 struct intel_engine_cs *engine = request->engine;
666 * Only unwind in reverse order, required so that the per-context list
667 * is kept in seqno/ring order.
669 RQ_TRACE(request, "\n");
671 GEM_BUG_ON(!irqs_disabled());
672 lockdep_assert_held(&engine->sched_engine->lock);
675 * Before we remove this breadcrumb from the signal list, we have
676 * to ensure that a concurrent dma_fence_enable_signaling() does not
677 * attach itself. We first mark the request as no longer active and
678 * make sure that is visible to other cores, and then remove the
679 * breadcrumb if attached.
681 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
682 clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
683 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
684 i915_request_cancel_breadcrumb(request);
686 /* We've already spun, don't charge on resubmitting. */
687 if (request->sched.semaphores && __i915_request_has_started(request))
688 request->sched.semaphores = 0;
691 * We don't need to wake_up any waiters on request->execute, they
692 * will get woken by any other event or us re-adding this request
693 * to the engine timeline (__i915_request_submit()). The waiters
694 * should be quite adapt at finding that the request now has a new
695 * global_seqno to the one they went to sleep on.
699 void i915_request_unsubmit(struct i915_request *request)
701 struct intel_engine_cs *engine = request->engine;
704 /* Will be called from irq-context when using foreign fences. */
705 spin_lock_irqsave(&engine->sched_engine->lock, flags);
707 __i915_request_unsubmit(request);
709 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
712 void i915_request_cancel(struct i915_request *rq, int error)
714 if (!i915_request_set_error_once(rq, error))
717 set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags);
719 intel_context_cancel_request(rq->context, rq);
722 static int __i915_sw_fence_call
723 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
725 struct i915_request *request =
726 container_of(fence, typeof(*request), submit);
730 trace_i915_request_submit(request);
732 if (unlikely(fence->error))
733 i915_request_set_error_once(request, fence->error);
735 __rq_arm_watchdog(request);
738 * We need to serialize use of the submit_request() callback
739 * with its hotplugging performed during an emergency
740 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
741 * critical section in order to force i915_gem_set_wedged() to
742 * wait until the submit_request() is completed before
746 request->engine->submit_request(request);
751 i915_request_put(request);
758 static int __i915_sw_fence_call
759 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
761 struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
768 i915_request_put(rq);
775 static void retire_requests(struct intel_timeline *tl)
777 struct i915_request *rq, *rn;
779 list_for_each_entry_safe(rq, rn, &tl->requests, link)
780 if (!i915_request_retire(rq))
784 static noinline struct i915_request *
785 request_alloc_slow(struct intel_timeline *tl,
786 struct i915_request **rsvd,
789 struct i915_request *rq;
791 /* If we cannot wait, dip into our reserves */
792 if (!gfpflags_allow_blocking(gfp)) {
793 rq = xchg(rsvd, NULL);
794 if (!rq) /* Use the normal failure path for one final WARN */
800 if (list_empty(&tl->requests))
803 /* Move our oldest request to the slab-cache (if not in use!) */
804 rq = list_first_entry(&tl->requests, typeof(*rq), link);
805 i915_request_retire(rq);
807 rq = kmem_cache_alloc(slab_requests,
808 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
812 /* Ratelimit ourselves to prevent oom from malicious clients */
813 rq = list_last_entry(&tl->requests, typeof(*rq), link);
814 cond_synchronize_rcu(rq->rcustate);
816 /* Retire our old requests in the hope that we free some */
820 return kmem_cache_alloc(slab_requests, gfp);
823 static void __i915_request_ctor(void *arg)
825 struct i915_request *rq = arg;
827 spin_lock_init(&rq->lock);
828 i915_sched_node_init(&rq->sched);
829 i915_sw_fence_init(&rq->submit, submit_notify);
830 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
832 rq->capture_list = NULL;
834 init_llist_head(&rq->execute_cb);
837 struct i915_request *
838 __i915_request_create(struct intel_context *ce, gfp_t gfp)
840 struct intel_timeline *tl = ce->timeline;
841 struct i915_request *rq;
847 /* Check that the caller provided an already pinned context */
848 __intel_context_pin(ce);
851 * Beware: Dragons be flying overhead.
853 * We use RCU to look up requests in flight. The lookups may
854 * race with the request being allocated from the slab freelist.
855 * That is the request we are writing to here, may be in the process
856 * of being read by __i915_active_request_get_rcu(). As such,
857 * we have to be very careful when overwriting the contents. During
858 * the RCU lookup, we change chase the request->engine pointer,
859 * read the request->global_seqno and increment the reference count.
861 * The reference count is incremented atomically. If it is zero,
862 * the lookup knows the request is unallocated and complete. Otherwise,
863 * it is either still in use, or has been reallocated and reset
864 * with dma_fence_init(). This increment is safe for release as we
865 * check that the request we have a reference to and matches the active
868 * Before we increment the refcount, we chase the request->engine
869 * pointer. We must not call kmem_cache_zalloc() or else we set
870 * that pointer to NULL and cause a crash during the lookup. If
871 * we see the request is completed (based on the value of the
872 * old engine and seqno), the lookup is complete and reports NULL.
873 * If we decide the request is not completed (new engine or seqno),
874 * then we grab a reference and double check that it is still the
875 * active request - which it won't be and restart the lookup.
877 * Do not use kmem_cache_zalloc() here!
879 rq = kmem_cache_alloc(slab_requests,
880 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
882 rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
890 * Hold a reference to the intel_context over life of an i915_request.
891 * Without this an i915_request can exist after the context has been
892 * destroyed (e.g. request retired, context closed, but user space holds
893 * a reference to the request from an out fence). In the case of GuC
894 * submission + virtual engine, the engine that the request references
895 * is also destroyed which can trigger bad pointer dref in fence ops
896 * (e.g. i915_fence_get_driver_name). We could likely change these
897 * functions to avoid touching the engine but let's just be safe and
898 * hold the intel_context reference. In execlist mode the request always
899 * eventually points to a physical engine so this isn't an issue.
901 rq->context = intel_context_get(ce);
902 rq->engine = ce->engine;
904 rq->execution_mask = ce->engine->mask;
906 ret = intel_timeline_get_seqno(tl, rq, &seqno);
910 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
911 tl->fence_context, seqno);
913 RCU_INIT_POINTER(rq->timeline, tl);
914 rq->hwsp_seqno = tl->hwsp_seqno;
915 GEM_BUG_ON(__i915_request_is_complete(rq));
917 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
919 rq->guc_prio = GUC_PRIO_INIT;
921 /* We bump the ref for the fence chain */
922 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
923 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
925 i915_sched_node_reinit(&rq->sched);
927 /* No zalloc, everything must be cleared after use */
929 __rq_init_watchdog(rq);
930 GEM_BUG_ON(rq->capture_list);
931 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
934 * Reserve space in the ring buffer for all the commands required to
935 * eventually emit this request. This is to guarantee that the
936 * i915_request_add() call can't fail. Note that the reserve may need
937 * to be redone if the request is not actually submitted straight
938 * away, e.g. because a GPU scheduler has deferred it.
940 * Note that due to how we add reserved_space to intel_ring_begin()
941 * we need to double our request to ensure that if we need to wrap
942 * around inside i915_request_add() there is sufficient space at
943 * the beginning of the ring as well.
946 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
949 * Record the position of the start of the request so that
950 * should we detect the updated seqno part-way through the
951 * GPU processing the request, we never over-estimate the
952 * position of the head.
954 rq->head = rq->ring->emit;
956 ret = rq->engine->request_alloc(rq);
960 rq->infix = rq->ring->emit; /* end of header; start of user payload */
962 intel_context_mark_active(ce);
963 list_add_tail_rcu(&rq->link, &tl->requests);
968 ce->ring->emit = rq->head;
970 /* Make sure we didn't add ourselves to external state before freeing */
971 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
972 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
975 intel_context_put(ce);
976 kmem_cache_free(slab_requests, rq);
978 intel_context_unpin(ce);
982 struct i915_request *
983 i915_request_create(struct intel_context *ce)
985 struct i915_request *rq;
986 struct intel_timeline *tl;
988 tl = intel_context_timeline_lock(ce);
992 /* Move our oldest request to the slab-cache (if not in use!) */
993 rq = list_first_entry(&tl->requests, typeof(*rq), link);
994 if (!list_is_last(&rq->link, &tl->requests))
995 i915_request_retire(rq);
997 intel_context_enter(ce);
998 rq = __i915_request_create(ce, GFP_KERNEL);
999 intel_context_exit(ce); /* active reference transferred to request */
1003 /* Check that we do not interrupt ourselves with a new request */
1004 rq->cookie = lockdep_pin_lock(&tl->mutex);
1009 intel_context_timeline_unlock(tl);
1014 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
1016 struct dma_fence *fence;
1019 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
1022 if (i915_request_started(signal))
1026 * The caller holds a reference on @signal, but we do not serialise
1027 * against it being retired and removed from the lists.
1029 * We do not hold a reference to the request before @signal, and
1030 * so must be very careful to ensure that it is not _recycled_ as
1031 * we follow the link backwards.
1036 struct list_head *pos = READ_ONCE(signal->link.prev);
1037 struct i915_request *prev;
1039 /* Confirm signal has not been retired, the link is valid */
1040 if (unlikely(__i915_request_has_started(signal)))
1043 /* Is signal the earliest request on its timeline? */
1044 if (pos == &rcu_dereference(signal->timeline)->requests)
1048 * Peek at the request before us in the timeline. That
1049 * request will only be valid before it is retired, so
1050 * after acquiring a reference to it, confirm that it is
1051 * still part of the signaler's timeline.
1053 prev = list_entry(pos, typeof(*prev), link);
1054 if (!i915_request_get_rcu(prev))
1057 /* After the strong barrier, confirm prev is still attached */
1058 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
1059 i915_request_put(prev);
1063 fence = &prev->fence;
1070 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
1071 err = i915_sw_fence_await_dma_fence(&rq->submit,
1074 dma_fence_put(fence);
1079 static intel_engine_mask_t
1080 already_busywaiting(struct i915_request *rq)
1083 * Polling a semaphore causes bus traffic, delaying other users of
1084 * both the GPU and CPU. We want to limit the impact on others,
1085 * while taking advantage of early submission to reduce GPU
1086 * latency. Therefore we restrict ourselves to not using more
1087 * than one semaphore from each source, and not using a semaphore
1088 * if we have detected the engine is saturated (i.e. would not be
1089 * submitted early and cause bus traffic reading an already passed
1092 * See the are-we-too-late? check in __i915_request_submit().
1094 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1098 __emit_semaphore_wait(struct i915_request *to,
1099 struct i915_request *from,
1102 const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;
1107 GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);
1108 GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1110 /* We need to pin the signaler's HWSP until we are finished reading. */
1111 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1119 cs = intel_ring_begin(to, len);
1124 * Using greater-than-or-equal here means we have to worry
1125 * about seqno wraparound. To side step that issue, we swap
1126 * the timeline HWSP upon wrapping, so that everyone listening
1127 * for the old (pre-wrap) values do not see the much smaller
1128 * (post-wrap) values than they were expecting (and so wait
1131 *cs++ = (MI_SEMAPHORE_WAIT |
1132 MI_SEMAPHORE_GLOBAL_GTT |
1134 MI_SEMAPHORE_SAD_GTE_SDD) +
1137 *cs++ = hwsp_offset;
1144 intel_ring_advance(to, cs);
1149 can_use_semaphore_wait(struct i915_request *to, struct i915_request *from)
1151 return to->engine->gt->ggtt == from->engine->gt->ggtt;
1155 emit_semaphore_wait(struct i915_request *to,
1156 struct i915_request *from,
1159 const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1160 struct i915_sw_fence *wait = &to->submit;
1162 if (!can_use_semaphore_wait(to, from))
1165 if (!intel_context_use_semaphores(to->context))
1168 if (i915_request_has_initial_breadcrumb(to))
1172 * If this or its dependents are waiting on an external fence
1173 * that may fail catastrophically, then we want to avoid using
1174 * sempahores as they bypass the fence signaling metadata, and we
1175 * lose the fence->error propagation.
1177 if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1180 /* Just emit the first semaphore we see as request space is limited. */
1181 if (already_busywaiting(to) & mask)
1184 if (i915_request_await_start(to, from) < 0)
1187 /* Only submit our spinner after the signaler is running! */
1188 if (__await_execution(to, from, gfp))
1191 if (__emit_semaphore_wait(to, from, from->fence.seqno))
1194 to->sched.semaphores |= mask;
1195 wait = &to->semaphore;
1198 return i915_sw_fence_await_dma_fence(wait,
1203 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1204 struct dma_fence *fence)
1206 return __intel_timeline_sync_is_later(tl,
1211 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1212 const struct dma_fence *fence)
1214 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1218 __i915_request_await_execution(struct i915_request *to,
1219 struct i915_request *from)
1223 GEM_BUG_ON(intel_context_is_barrier(from->context));
1225 /* Submit both requests at the same time */
1226 err = __await_execution(to, from, I915_FENCE_GFP);
1230 /* Squash repeated depenendices to the same timelines */
1231 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1236 * Wait until the start of this request.
1238 * The execution cb fires when we submit the request to HW. But in
1239 * many cases this may be long before the request itself is ready to
1240 * run (consider that we submit 2 requests for the same context, where
1241 * the request of interest is behind an indefinite spinner). So we hook
1242 * up to both to reduce our queues and keep the execution lag minimised
1243 * in the worst case, though we hope that the await_start is elided.
1245 err = i915_request_await_start(to, from);
1250 * Ensure both start together [after all semaphores in signal]
1252 * Now that we are queued to the HW at roughly the same time (thanks
1253 * to the execute cb) and are ready to run at roughly the same time
1254 * (thanks to the await start), our signaler may still be indefinitely
1255 * delayed by waiting on a semaphore from a remote engine. If our
1256 * signaler depends on a semaphore, so indirectly do we, and we do not
1257 * want to start our payload until our signaler also starts theirs.
1260 * However, there is also a second condition for which we need to wait
1261 * for the precise start of the signaler. Consider that the signaler
1262 * was submitted in a chain of requests following another context
1263 * (with just an ordinary intra-engine fence dependency between the
1264 * two). In this case the signaler is queued to HW, but not for
1265 * immediate execution, and so we must wait until it reaches the
1268 if (can_use_semaphore_wait(to, from) &&
1269 intel_engine_has_semaphores(to->engine) &&
1270 !i915_request_has_initial_breadcrumb(to)) {
1271 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1276 /* Couple the dependency tree for PI on this exposed to->fence */
1277 if (to->engine->sched_engine->schedule) {
1278 err = i915_sched_node_add_dependency(&to->sched,
1280 I915_DEPENDENCY_WEAK);
1285 return intel_timeline_sync_set_start(i915_request_timeline(to),
1289 static void mark_external(struct i915_request *rq)
1292 * The downside of using semaphores is that we lose metadata passing
1293 * along the signaling chain. This is particularly nasty when we
1294 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1295 * fatal errors we want to scrub the request before it is executed,
1296 * which means that we cannot preload the request onto HW and have
1297 * it wait upon a semaphore.
1299 rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1303 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1306 return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1307 i915_fence_context_timeout(rq->engine->i915,
1313 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1315 struct dma_fence *iter;
1318 if (!to_dma_fence_chain(fence))
1319 return __i915_request_await_external(rq, fence);
1321 dma_fence_chain_for_each(iter, fence) {
1322 struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1324 if (!dma_fence_is_i915(chain->fence)) {
1325 err = __i915_request_await_external(rq, iter);
1329 err = i915_request_await_dma_fence(rq, chain->fence);
1334 dma_fence_put(iter);
1339 i915_request_await_execution(struct i915_request *rq,
1340 struct dma_fence *fence)
1342 struct dma_fence **child = &fence;
1343 unsigned int nchild = 1;
1346 if (dma_fence_is_array(fence)) {
1347 struct dma_fence_array *array = to_dma_fence_array(fence);
1349 /* XXX Error for signal-on-any fence arrays */
1351 child = array->fences;
1352 nchild = array->num_fences;
1353 GEM_BUG_ON(!nchild);
1358 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1361 if (fence->context == rq->fence.context)
1365 * We don't squash repeated fence dependencies here as we
1366 * want to run our callback in all cases.
1369 if (dma_fence_is_i915(fence))
1370 ret = __i915_request_await_execution(rq,
1373 ret = i915_request_await_external(rq, fence);
1382 await_request_submit(struct i915_request *to, struct i915_request *from)
1385 * If we are waiting on a virtual engine, then it may be
1386 * constrained to execute on a single engine *prior* to submission.
1387 * When it is submitted, it will be first submitted to the virtual
1388 * engine and then passed to the physical engine. We cannot allow
1389 * the waiter to be submitted immediately to the physical engine
1390 * as it may then bypass the virtual request.
1392 if (to->engine == READ_ONCE(from->engine))
1393 return i915_sw_fence_await_sw_fence_gfp(&to->submit,
1397 return __i915_request_await_execution(to, from);
1401 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1405 GEM_BUG_ON(to == from);
1406 GEM_BUG_ON(to->timeline == from->timeline);
1408 if (i915_request_completed(from)) {
1409 i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1413 if (to->engine->sched_engine->schedule) {
1414 ret = i915_sched_node_add_dependency(&to->sched,
1416 I915_DEPENDENCY_EXTERNAL);
1421 if (!intel_engine_uses_guc(to->engine) &&
1422 is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
1423 ret = await_request_submit(to, from);
1425 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1433 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1435 struct dma_fence **child = &fence;
1436 unsigned int nchild = 1;
1440 * Note that if the fence-array was created in signal-on-any mode,
1441 * we should *not* decompose it into its individual fences. However,
1442 * we don't currently store which mode the fence-array is operating
1443 * in. Fortunately, the only user of signal-on-any is private to
1444 * amdgpu and we should not see any incoming fence-array from
1445 * sync-file being in signal-on-any mode.
1447 if (dma_fence_is_array(fence)) {
1448 struct dma_fence_array *array = to_dma_fence_array(fence);
1450 child = array->fences;
1451 nchild = array->num_fences;
1452 GEM_BUG_ON(!nchild);
1457 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1461 * Requests on the same timeline are explicitly ordered, along
1462 * with their dependencies, by i915_request_add() which ensures
1463 * that requests are submitted in-order through each ring.
1465 if (fence->context == rq->fence.context)
1468 /* Squash repeated waits to the same timelines */
1469 if (fence->context &&
1470 intel_timeline_sync_is_later(i915_request_timeline(rq),
1474 if (dma_fence_is_i915(fence))
1475 ret = i915_request_await_request(rq, to_request(fence));
1477 ret = i915_request_await_external(rq, fence);
1481 /* Record the latest fence used against each timeline */
1483 intel_timeline_sync_set(i915_request_timeline(rq),
1491 * i915_request_await_object - set this request to (async) wait upon a bo
1492 * @to: request we are wishing to use
1493 * @obj: object which may be in use on another ring.
1494 * @write: whether the wait is on behalf of a writer
1496 * This code is meant to abstract object synchronization with the GPU.
1497 * Conceptually we serialise writes between engines inside the GPU.
1498 * We only allow one engine to write into a buffer at any time, but
1499 * multiple readers. To ensure each has a coherent view of memory, we must:
1501 * - If there is an outstanding write request to the object, the new
1502 * request must wait for it to complete (either CPU or in hw, requests
1503 * on the same ring will be naturally ordered).
1505 * - If we are a write request (pending_write_domain is set), the new
1506 * request must wait for outstanding read requests to complete.
1508 * Returns 0 if successful, else propagates up the lower layer error.
1511 i915_request_await_object(struct i915_request *to,
1512 struct drm_i915_gem_object *obj,
1515 struct dma_fence *excl;
1519 struct dma_fence **shared;
1520 unsigned int count, i;
1522 ret = dma_resv_get_fences(obj->base.resv, &excl, &count,
1527 for (i = 0; i < count; i++) {
1528 ret = i915_request_await_dma_fence(to, shared[i]);
1532 dma_fence_put(shared[i]);
1535 for (; i < count; i++)
1536 dma_fence_put(shared[i]);
1539 excl = dma_resv_get_excl_unlocked(obj->base.resv);
1544 ret = i915_request_await_dma_fence(to, excl);
1546 dma_fence_put(excl);
1552 static struct i915_request *
1553 __i915_request_add_to_timeline(struct i915_request *rq)
1555 struct intel_timeline *timeline = i915_request_timeline(rq);
1556 struct i915_request *prev;
1559 * Dependency tracking and request ordering along the timeline
1560 * is special cased so that we can eliminate redundant ordering
1561 * operations while building the request (we know that the timeline
1562 * itself is ordered, and here we guarantee it).
1564 * As we know we will need to emit tracking along the timeline,
1565 * we embed the hooks into our request struct -- at the cost of
1566 * having to have specialised no-allocation interfaces (which will
1567 * be beneficial elsewhere).
1569 * A second benefit to open-coding i915_request_await_request is
1570 * that we can apply a slight variant of the rules specialised
1571 * for timelines that jump between engines (such as virtual engines).
1572 * If we consider the case of virtual engine, we must emit a dma-fence
1573 * to prevent scheduling of the second request until the first is
1574 * complete (to maximise our greedy late load balancing) and this
1575 * precludes optimising to use semaphores serialisation of a single
1576 * timeline across engines.
1578 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1580 if (prev && !__i915_request_is_complete(prev)) {
1581 bool uses_guc = intel_engine_uses_guc(rq->engine);
1584 * The requests are supposed to be kept in order. However,
1585 * we need to be wary in case the timeline->last_request
1586 * is used as a barrier for external modification to this
1589 GEM_BUG_ON(prev->context == rq->context &&
1590 i915_seqno_passed(prev->fence.seqno,
1594 is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask)) ||
1595 (uses_guc && prev->context == rq->context))
1596 i915_sw_fence_await_sw_fence(&rq->submit,
1600 __i915_sw_fence_await_dma_fence(&rq->submit,
1603 if (rq->engine->sched_engine->schedule)
1604 __i915_sched_node_add_dependency(&rq->sched,
1611 * Make sure that no request gazumped us - if it was allocated after
1612 * our i915_request_alloc() and called __i915_request_add() before
1613 * us, the timeline will hold its seqno which is later than ours.
1615 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1621 * NB: This function is not allowed to fail. Doing so would mean the the
1622 * request is not being tracked for completion but the work itself is
1623 * going to happen on the hardware. This would be a Bad Thing(tm).
1625 struct i915_request *__i915_request_commit(struct i915_request *rq)
1627 struct intel_engine_cs *engine = rq->engine;
1628 struct intel_ring *ring = rq->ring;
1634 * To ensure that this call will not fail, space for its emissions
1635 * should already have been reserved in the ring buffer. Let the ring
1636 * know that it is time to use that space up.
1638 GEM_BUG_ON(rq->reserved_space > ring->space);
1639 rq->reserved_space = 0;
1640 rq->emitted_jiffies = jiffies;
1643 * Record the position of the start of the breadcrumb so that
1644 * should we detect the updated seqno part-way through the
1645 * GPU processing the request, we never over-estimate the
1646 * position of the ring's HEAD.
1648 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1649 GEM_BUG_ON(IS_ERR(cs));
1650 rq->postfix = intel_ring_offset(rq, cs);
1652 return __i915_request_add_to_timeline(rq);
1655 void __i915_request_queue_bh(struct i915_request *rq)
1657 i915_sw_fence_commit(&rq->semaphore);
1658 i915_sw_fence_commit(&rq->submit);
1661 void __i915_request_queue(struct i915_request *rq,
1662 const struct i915_sched_attr *attr)
1665 * Let the backend know a new request has arrived that may need
1666 * to adjust the existing execution schedule due to a high priority
1667 * request - i.e. we may want to preempt the current request in order
1668 * to run a high priority dependency chain *before* we can execute this
1671 * This is called before the request is ready to run so that we can
1672 * decide whether to preempt the entire chain so that it is ready to
1673 * run at the earliest possible convenience.
1675 if (attr && rq->engine->sched_engine->schedule)
1676 rq->engine->sched_engine->schedule(rq, attr);
1679 __i915_request_queue_bh(rq);
1680 local_bh_enable(); /* kick tasklets */
1683 void i915_request_add(struct i915_request *rq)
1685 struct intel_timeline * const tl = i915_request_timeline(rq);
1686 struct i915_sched_attr attr = {};
1687 struct i915_gem_context *ctx;
1689 lockdep_assert_held(&tl->mutex);
1690 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1692 trace_i915_request_add(rq);
1693 __i915_request_commit(rq);
1695 /* XXX placeholder for selftests */
1697 ctx = rcu_dereference(rq->context->gem_context);
1702 __i915_request_queue(rq, &attr);
1704 mutex_unlock(&tl->mutex);
1707 static unsigned long local_clock_ns(unsigned int *cpu)
1712 * Cheaply and approximately convert from nanoseconds to microseconds.
1713 * The result and subsequent calculations are also defined in the same
1714 * approximate microseconds units. The principal source of timing
1715 * error here is from the simple truncation.
1717 * Note that local_clock() is only defined wrt to the current CPU;
1718 * the comparisons are no longer valid if we switch CPUs. Instead of
1719 * blocking preemption for the entire busywait, we can detect the CPU
1720 * switch and use that as indicator of system load and a reason to
1721 * stop busywaiting, see busywait_stop().
1730 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1732 unsigned int this_cpu;
1734 if (time_after(local_clock_ns(&this_cpu), timeout))
1737 return this_cpu != cpu;
1740 static bool __i915_spin_request(struct i915_request * const rq, int state)
1742 unsigned long timeout_ns;
1746 * Only wait for the request if we know it is likely to complete.
1748 * We don't track the timestamps around requests, nor the average
1749 * request length, so we do not have a good indicator that this
1750 * request will complete within the timeout. What we do know is the
1751 * order in which requests are executed by the context and so we can
1752 * tell if the request has been started. If the request is not even
1753 * running yet, it is a fair assumption that it will not complete
1754 * within our relatively short timeout.
1756 if (!i915_request_is_running(rq))
1760 * When waiting for high frequency requests, e.g. during synchronous
1761 * rendering split between the CPU and GPU, the finite amount of time
1762 * required to set up the irq and wait upon it limits the response
1763 * rate. By busywaiting on the request completion for a short while we
1764 * can service the high frequency waits as quick as possible. However,
1765 * if it is a slow request, we want to sleep as quickly as possible.
1766 * The tradeoff between waiting and sleeping is roughly the time it
1767 * takes to sleep on a request, on the order of a microsecond.
1770 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1771 timeout_ns += local_clock_ns(&cpu);
1773 if (dma_fence_is_signaled(&rq->fence))
1776 if (signal_pending_state(state, current))
1779 if (busywait_stop(timeout_ns, cpu))
1783 } while (!need_resched());
1788 struct request_wait {
1789 struct dma_fence_cb cb;
1790 struct task_struct *tsk;
1793 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1795 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1797 wake_up_process(fetch_and_zero(&wait->tsk));
1801 * i915_request_wait - wait until execution of request has finished
1802 * @rq: the request to wait upon
1803 * @flags: how to wait
1804 * @timeout: how long to wait in jiffies
1806 * i915_request_wait() waits for the request to be completed, for a
1807 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1810 * Returns the remaining time (in jiffies) if the request completed, which may
1811 * be zero or -ETIME if the request is unfinished after the timeout expires.
1812 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1813 * pending before the request completes.
1815 long i915_request_wait(struct i915_request *rq,
1819 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1820 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1821 struct request_wait wait;
1824 GEM_BUG_ON(timeout < 0);
1826 if (dma_fence_is_signaled(&rq->fence))
1832 trace_i915_request_wait_begin(rq, flags);
1835 * We must never wait on the GPU while holding a lock as we
1836 * may need to perform a GPU reset. So while we don't need to
1837 * serialise wait/reset with an explicit lock, we do want
1838 * lockdep to detect potential dependency cycles.
1840 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1843 * Optimistic spin before touching IRQs.
1845 * We may use a rather large value here to offset the penalty of
1846 * switching away from the active task. Frequently, the client will
1847 * wait upon an old swapbuffer to throttle itself to remain within a
1848 * frame of the gpu. If the client is running in lockstep with the gpu,
1849 * then it should not be waiting long at all, and a sleep now will incur
1850 * extra scheduler latency in producing the next frame. To try to
1851 * avoid adding the cost of enabling/disabling the interrupt to the
1852 * short wait, we first spin to see if the request would have completed
1853 * in the time taken to setup the interrupt.
1855 * We need upto 5us to enable the irq, and upto 20us to hide the
1856 * scheduler latency of a context switch, ignoring the secondary
1857 * impacts from a context switch such as cache eviction.
1859 * The scheme used for low-latency IO is called "hybrid interrupt
1860 * polling". The suggestion there is to sleep until just before you
1861 * expect to be woken by the device interrupt and then poll for its
1862 * completion. That requires having a good predictor for the request
1863 * duration, which we currently lack.
1865 if (CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT &&
1866 __i915_spin_request(rq, state))
1870 * This client is about to stall waiting for the GPU. In many cases
1871 * this is undesirable and limits the throughput of the system, as
1872 * many clients cannot continue processing user input/output whilst
1873 * blocked. RPS autotuning may take tens of milliseconds to respond
1874 * to the GPU load and thus incurs additional latency for the client.
1875 * We can circumvent that by promoting the GPU frequency to maximum
1876 * before we sleep. This makes the GPU throttle up much more quickly
1877 * (good for benchmarks and user experience, e.g. window animations),
1878 * but at a cost of spending more power processing the workload
1879 * (bad for battery).
1881 if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
1882 intel_rps_boost(rq);
1885 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1889 * Flush the submission tasklet, but only if it may help this request.
1891 * We sometimes experience some latency between the HW interrupts and
1892 * tasklet execution (mostly due to ksoftirqd latency, but it can also
1893 * be due to lazy CS events), so lets run the tasklet manually if there
1894 * is a chance it may submit this request. If the request is not ready
1895 * to run, as it is waiting for other fences to be signaled, flushing
1896 * the tasklet is busy work without any advantage for this client.
1898 * If the HW is being lazy, this is the last chance before we go to
1899 * sleep to catch any pending events. We will check periodically in
1900 * the heartbeat to flush the submission tasklets as a last resort
1903 if (i915_request_is_ready(rq))
1904 __intel_engine_flush_submission(rq->engine, false);
1907 set_current_state(state);
1909 if (dma_fence_is_signaled(&rq->fence))
1912 if (signal_pending_state(state, current)) {
1913 timeout = -ERESTARTSYS;
1922 timeout = io_schedule_timeout(timeout);
1924 __set_current_state(TASK_RUNNING);
1926 if (READ_ONCE(wait.tsk))
1927 dma_fence_remove_callback(&rq->fence, &wait.cb);
1928 GEM_BUG_ON(!list_empty(&wait.cb.node));
1931 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1932 trace_i915_request_wait_end(rq);
1936 static int print_sched_attr(const struct i915_sched_attr *attr,
1937 char *buf, int x, int len)
1939 if (attr->priority == I915_PRIORITY_INVALID)
1942 x += snprintf(buf + x, len - x,
1943 " prio=%d", attr->priority);
1948 static char queue_status(const struct i915_request *rq)
1950 if (i915_request_is_active(rq))
1953 if (i915_request_is_ready(rq))
1954 return intel_engine_is_virtual(rq->engine) ? 'V' : 'R';
1959 static const char *run_status(const struct i915_request *rq)
1961 if (__i915_request_is_complete(rq))
1964 if (__i915_request_has_started(rq))
1967 if (!i915_sw_fence_signaled(&rq->semaphore))
1973 static const char *fence_status(const struct i915_request *rq)
1975 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
1978 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
1984 void i915_request_show(struct drm_printer *m,
1985 const struct i915_request *rq,
1989 const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
1994 * The prefix is used to show the queue status, for which we use
1995 * the following flags:
1998 * - initial status upon being submitted by the user
2000 * - the request is not ready for execution as it is waiting
2001 * for external fences
2004 * - all fences the request was waiting on have been signaled,
2005 * and the request is now ready for execution and will be
2006 * in a backend queue
2008 * - a ready request may still need to wait on semaphores
2012 * - same as ready, but queued over multiple backends
2015 * - the request has been transferred from the backend queue and
2016 * submitted for execution on HW
2018 * - a completed request may still be regarded as executing, its
2019 * status may not be updated until it is retired and removed
2023 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
2025 drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n",
2026 prefix, indent, " ",
2028 rq->fence.context, rq->fence.seqno,
2032 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
2036 static bool engine_match_ring(struct intel_engine_cs *engine, struct i915_request *rq)
2038 u32 ring = ENGINE_READ(engine, RING_START);
2040 return ring == i915_ggtt_offset(rq->ring->vma);
2043 static bool match_ring(struct i915_request *rq)
2045 struct intel_engine_cs *engine;
2049 if (!intel_engine_is_virtual(rq->engine))
2050 return engine_match_ring(rq->engine, rq);
2054 while ((engine = intel_engine_get_sibling(rq->engine, i++))) {
2055 found = engine_match_ring(engine, rq);
2063 enum i915_request_state i915_test_request_state(struct i915_request *rq)
2065 if (i915_request_completed(rq))
2066 return I915_REQUEST_COMPLETE;
2068 if (!i915_request_started(rq))
2069 return I915_REQUEST_PENDING;
2072 return I915_REQUEST_ACTIVE;
2074 return I915_REQUEST_QUEUED;
2077 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2078 #include "selftests/mock_request.c"
2079 #include "selftests/i915_request.c"
2082 void i915_request_module_exit(void)
2084 kmem_cache_destroy(slab_execute_cbs);
2085 kmem_cache_destroy(slab_requests);
2088 int __init i915_request_module_init(void)
2091 kmem_cache_create("i915_request",
2092 sizeof(struct i915_request),
2093 __alignof__(struct i915_request),
2094 SLAB_HWCACHE_ALIGN |
2095 SLAB_RECLAIM_ACCOUNT |
2096 SLAB_TYPESAFE_BY_RCU,
2097 __i915_request_ctor);
2101 slab_execute_cbs = KMEM_CACHE(execute_cb,
2102 SLAB_HWCACHE_ALIGN |
2103 SLAB_RECLAIM_ACCOUNT |
2104 SLAB_TYPESAFE_BY_RCU);
2105 if (!slab_execute_cbs)
2111 kmem_cache_destroy(slab_requests);