2 * Copyright © 2008-2015 Intel Corporation
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
35 #include "i915_active.h"
37 #include "i915_globals.h"
38 #include "i915_trace.h"
42 struct list_head link;
44 struct i915_sw_fence *fence;
45 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
46 struct i915_request *signal;
49 static struct i915_global_request {
50 struct i915_global base;
51 struct kmem_cache *slab_requests;
52 struct kmem_cache *slab_dependencies;
53 struct kmem_cache *slab_execute_cbs;
56 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
61 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
64 * The timeline struct (as part of the ppgtt underneath a context)
65 * may be freed when the request is no longer in use by the GPU.
66 * We could extend the life of a context to beyond that of all
67 * fences, possibly keeping the hw resource around indefinitely,
68 * or we just give them a false name. Since
69 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
70 * lie seems justifiable.
72 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
75 return to_request(fence)->gem_context->name ?: "[i915]";
78 static bool i915_fence_signaled(struct dma_fence *fence)
80 return i915_request_completed(to_request(fence));
83 static bool i915_fence_enable_signaling(struct dma_fence *fence)
85 return i915_request_enable_breadcrumb(to_request(fence));
88 static signed long i915_fence_wait(struct dma_fence *fence,
92 return i915_request_wait(to_request(fence),
93 interruptible | I915_WAIT_PRIORITY,
97 static void i915_fence_release(struct dma_fence *fence)
99 struct i915_request *rq = to_request(fence);
102 * The request is put onto a RCU freelist (i.e. the address
103 * is immediately reused), mark the fences as being freed now.
104 * Otherwise the debugobjects for the fences are only marked as
105 * freed when the slab cache itself is freed, and so we would get
106 * caught trying to reuse dead objects.
108 i915_sw_fence_fini(&rq->submit);
109 i915_sw_fence_fini(&rq->semaphore);
111 kmem_cache_free(global.slab_requests, rq);
114 const struct dma_fence_ops i915_fence_ops = {
115 .get_driver_name = i915_fence_get_driver_name,
116 .get_timeline_name = i915_fence_get_timeline_name,
117 .enable_signaling = i915_fence_enable_signaling,
118 .signaled = i915_fence_signaled,
119 .wait = i915_fence_wait,
120 .release = i915_fence_release,
123 static void irq_execute_cb(struct irq_work *wrk)
125 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
127 i915_sw_fence_complete(cb->fence);
128 kmem_cache_free(global.slab_execute_cbs, cb);
131 static void irq_execute_cb_hook(struct irq_work *wrk)
133 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
135 cb->hook(container_of(cb->fence, struct i915_request, submit),
137 i915_request_put(cb->signal);
142 static void __notify_execute_cb(struct i915_request *rq)
144 struct execute_cb *cb;
146 lockdep_assert_held(&rq->lock);
148 if (list_empty(&rq->execute_cb))
151 list_for_each_entry(cb, &rq->execute_cb, link)
152 irq_work_queue(&cb->work);
155 * XXX Rollback on __i915_request_unsubmit()
157 * In the future, perhaps when we have an active time-slicing scheduler,
158 * it will be interesting to unsubmit parallel execution and remove
159 * busywaits from the GPU until their master is restarted. This is
160 * quite hairy, we have to carefully rollback the fence and do a
161 * preempt-to-idle cycle on the target engine, all the while the
162 * master execute_cb may refire.
164 INIT_LIST_HEAD(&rq->execute_cb);
168 remove_from_client(struct i915_request *request)
170 struct drm_i915_file_private *file_priv;
172 file_priv = READ_ONCE(request->file_priv);
176 spin_lock(&file_priv->mm.lock);
177 if (request->file_priv) {
178 list_del(&request->client_link);
179 request->file_priv = NULL;
181 spin_unlock(&file_priv->mm.lock);
184 static void free_capture_list(struct i915_request *request)
186 struct i915_capture_list *capture;
188 capture = request->capture_list;
190 struct i915_capture_list *next = capture->next;
197 static bool i915_request_retire(struct i915_request *rq)
199 struct i915_active_request *active, *next;
201 lockdep_assert_held(&rq->timeline->mutex);
202 if (!i915_request_completed(rq))
205 GEM_TRACE("%s fence %llx:%lld, current %d\n",
207 rq->fence.context, rq->fence.seqno,
210 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
211 trace_i915_request_retire(rq);
214 * We know the GPU must have read the request to have
215 * sent us the seqno + interrupt, so use the position
216 * of tail of the request to update the last known position
219 * Note this requires that we are always called in request
222 GEM_BUG_ON(!list_is_first(&rq->link, &rq->timeline->requests));
223 rq->ring->head = rq->postfix;
226 * Walk through the active list, calling retire on each. This allows
227 * objects to track their GPU activity and mark themselves as idle
228 * when their *last* active request is completed (updating state
229 * tracking lists for eviction, active references for GEM, etc).
231 * As the ->retire() may free the node, we decouple it first and
232 * pass along the auxiliary information (to avoid dereferencing
233 * the node after the callback).
235 list_for_each_entry_safe(active, next, &rq->active_list, link) {
237 * In microbenchmarks or focusing upon time inside the kernel,
238 * we may spend an inordinate amount of time simply handling
239 * the retirement of requests and processing their callbacks.
240 * Of which, this loop itself is particularly hot due to the
241 * cache misses when jumping around the list of
242 * i915_active_request. So we try to keep this loop as
243 * streamlined as possible and also prefetch the next
244 * i915_active_request to try and hide the likely cache miss.
248 INIT_LIST_HEAD(&active->link);
249 RCU_INIT_POINTER(active->request, NULL);
251 active->retire(active, rq);
257 * We only loosely track inflight requests across preemption,
258 * and so we may find ourselves attempting to retire a _completed_
259 * request that we have removed from the HW and put back on a run
262 spin_lock(&rq->engine->active.lock);
263 list_del(&rq->sched.link);
264 spin_unlock(&rq->engine->active.lock);
266 spin_lock(&rq->lock);
267 i915_request_mark_complete(rq);
268 if (!i915_request_signaled(rq))
269 dma_fence_signal_locked(&rq->fence);
270 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
271 i915_request_cancel_breadcrumb(rq);
272 if (i915_request_has_waitboost(rq)) {
273 GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
274 atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
276 if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
277 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
278 __notify_execute_cb(rq);
280 GEM_BUG_ON(!list_empty(&rq->execute_cb));
281 spin_unlock(&rq->lock);
285 remove_from_client(rq);
288 intel_context_exit(rq->hw_context);
289 intel_context_unpin(rq->hw_context);
291 free_capture_list(rq);
292 i915_sched_node_fini(&rq->sched);
293 i915_request_put(rq);
298 void i915_request_retire_upto(struct i915_request *rq)
300 struct intel_timeline * const tl = rq->timeline;
301 struct i915_request *tmp;
303 GEM_TRACE("%s fence %llx:%lld, current %d\n",
305 rq->fence.context, rq->fence.seqno,
308 lockdep_assert_held(&tl->mutex);
309 GEM_BUG_ON(!i915_request_completed(rq));
312 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
313 } while (i915_request_retire(tmp) && tmp != rq);
317 __i915_request_await_execution(struct i915_request *rq,
318 struct i915_request *signal,
319 void (*hook)(struct i915_request *rq,
320 struct dma_fence *signal),
323 struct execute_cb *cb;
325 if (i915_request_is_active(signal)) {
327 hook(rq, &signal->fence);
331 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
335 cb->fence = &rq->submit;
336 i915_sw_fence_await(cb->fence);
337 init_irq_work(&cb->work, irq_execute_cb);
341 cb->signal = i915_request_get(signal);
342 cb->work.func = irq_execute_cb_hook;
345 spin_lock_irq(&signal->lock);
346 if (i915_request_is_active(signal)) {
348 hook(rq, &signal->fence);
349 i915_request_put(signal);
351 i915_sw_fence_complete(cb->fence);
352 kmem_cache_free(global.slab_execute_cbs, cb);
354 list_add_tail(&cb->link, &signal->execute_cb);
356 spin_unlock_irq(&signal->lock);
361 void __i915_request_submit(struct i915_request *request)
363 struct intel_engine_cs *engine = request->engine;
365 GEM_TRACE("%s fence %llx:%lld, current %d\n",
367 request->fence.context, request->fence.seqno,
368 hwsp_seqno(request));
370 GEM_BUG_ON(!irqs_disabled());
371 lockdep_assert_held(&engine->active.lock);
373 if (i915_gem_context_is_banned(request->gem_context))
374 i915_request_skip(request, -EIO);
377 * Are we using semaphores when the gpu is already saturated?
379 * Using semaphores incurs a cost in having the GPU poll a
380 * memory location, busywaiting for it to change. The continual
381 * memory reads can have a noticeable impact on the rest of the
382 * system with the extra bus traffic, stalling the cpu as it too
383 * tries to access memory across the bus (perf stat -e bus-cycles).
385 * If we installed a semaphore on this request and we only submit
386 * the request after the signaler completed, that indicates the
387 * system is overloaded and using semaphores at this time only
388 * increases the amount of work we are doing. If so, we disable
389 * further use of semaphores until we are idle again, whence we
390 * optimistically try again.
392 if (request->sched.semaphores &&
393 i915_sw_fence_signaled(&request->semaphore))
394 engine->saturated |= request->sched.semaphores;
396 /* We may be recursing from the signal callback of another i915 fence */
397 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
399 list_move_tail(&request->sched.link, &engine->active.requests);
401 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
402 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
404 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
405 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
406 !i915_request_enable_breadcrumb(request))
407 intel_engine_queue_breadcrumbs(engine);
409 __notify_execute_cb(request);
411 spin_unlock(&request->lock);
413 engine->emit_fini_breadcrumb(request,
414 request->ring->vaddr + request->postfix);
418 trace_i915_request_execute(request);
421 void i915_request_submit(struct i915_request *request)
423 struct intel_engine_cs *engine = request->engine;
426 /* Will be called from irq-context when using foreign fences. */
427 spin_lock_irqsave(&engine->active.lock, flags);
429 __i915_request_submit(request);
431 spin_unlock_irqrestore(&engine->active.lock, flags);
434 void __i915_request_unsubmit(struct i915_request *request)
436 struct intel_engine_cs *engine = request->engine;
438 GEM_TRACE("%s fence %llx:%lld, current %d\n",
440 request->fence.context, request->fence.seqno,
441 hwsp_seqno(request));
443 GEM_BUG_ON(!irqs_disabled());
444 lockdep_assert_held(&engine->active.lock);
447 * Only unwind in reverse order, required so that the per-context list
448 * is kept in seqno/ring order.
451 /* We may be recursing from the signal callback of another i915 fence */
452 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
454 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
455 i915_request_cancel_breadcrumb(request);
457 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
458 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
460 spin_unlock(&request->lock);
462 /* We've already spun, don't charge on resubmitting. */
463 if (request->sched.semaphores && i915_request_started(request)) {
464 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
465 request->sched.semaphores = 0;
469 * We don't need to wake_up any waiters on request->execute, they
470 * will get woken by any other event or us re-adding this request
471 * to the engine timeline (__i915_request_submit()). The waiters
472 * should be quite adapt at finding that the request now has a new
473 * global_seqno to the one they went to sleep on.
477 void i915_request_unsubmit(struct i915_request *request)
479 struct intel_engine_cs *engine = request->engine;
482 /* Will be called from irq-context when using foreign fences. */
483 spin_lock_irqsave(&engine->active.lock, flags);
485 __i915_request_unsubmit(request);
487 spin_unlock_irqrestore(&engine->active.lock, flags);
490 static int __i915_sw_fence_call
491 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
493 struct i915_request *request =
494 container_of(fence, typeof(*request), submit);
498 trace_i915_request_submit(request);
500 if (unlikely(fence->error))
501 i915_request_skip(request, fence->error);
504 * We need to serialize use of the submit_request() callback
505 * with its hotplugging performed during an emergency
506 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
507 * critical section in order to force i915_gem_set_wedged() to
508 * wait until the submit_request() is completed before
512 request->engine->submit_request(request);
517 i915_request_put(request);
524 static int __i915_sw_fence_call
525 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
527 struct i915_request *request =
528 container_of(fence, typeof(*request), semaphore);
532 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
536 i915_request_put(request);
543 static void retire_requests(struct intel_timeline *tl)
545 struct i915_request *rq, *rn;
547 list_for_each_entry_safe(rq, rn, &tl->requests, link)
548 if (!i915_request_retire(rq))
552 static noinline struct i915_request *
553 request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
555 struct i915_request *rq;
557 if (list_empty(&tl->requests))
560 if (!gfpflags_allow_blocking(gfp))
563 /* Move our oldest request to the slab-cache (if not in use!) */
564 rq = list_first_entry(&tl->requests, typeof(*rq), link);
565 i915_request_retire(rq);
567 rq = kmem_cache_alloc(global.slab_requests,
568 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
572 /* Ratelimit ourselves to prevent oom from malicious clients */
573 rq = list_last_entry(&tl->requests, typeof(*rq), link);
574 cond_synchronize_rcu(rq->rcustate);
576 /* Retire our old requests in the hope that we free some */
580 return kmem_cache_alloc(global.slab_requests, gfp);
583 struct i915_request *
584 __i915_request_create(struct intel_context *ce, gfp_t gfp)
586 struct intel_timeline *tl = ce->timeline;
587 struct i915_request *rq;
591 might_sleep_if(gfpflags_allow_blocking(gfp));
593 /* Check that the caller provided an already pinned context */
594 __intel_context_pin(ce);
597 * Beware: Dragons be flying overhead.
599 * We use RCU to look up requests in flight. The lookups may
600 * race with the request being allocated from the slab freelist.
601 * That is the request we are writing to here, may be in the process
602 * of being read by __i915_active_request_get_rcu(). As such,
603 * we have to be very careful when overwriting the contents. During
604 * the RCU lookup, we change chase the request->engine pointer,
605 * read the request->global_seqno and increment the reference count.
607 * The reference count is incremented atomically. If it is zero,
608 * the lookup knows the request is unallocated and complete. Otherwise,
609 * it is either still in use, or has been reallocated and reset
610 * with dma_fence_init(). This increment is safe for release as we
611 * check that the request we have a reference to and matches the active
614 * Before we increment the refcount, we chase the request->engine
615 * pointer. We must not call kmem_cache_zalloc() or else we set
616 * that pointer to NULL and cause a crash during the lookup. If
617 * we see the request is completed (based on the value of the
618 * old engine and seqno), the lookup is complete and reports NULL.
619 * If we decide the request is not completed (new engine or seqno),
620 * then we grab a reference and double check that it is still the
621 * active request - which it won't be and restart the lookup.
623 * Do not use kmem_cache_zalloc() here!
625 rq = kmem_cache_alloc(global.slab_requests,
626 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
628 rq = request_alloc_slow(tl, gfp);
635 ret = intel_timeline_get_seqno(tl, rq, &seqno);
639 rq->i915 = ce->engine->i915;
641 rq->gem_context = ce->gem_context;
642 rq->engine = ce->engine;
645 rq->hwsp_seqno = tl->hwsp_seqno;
646 rq->hwsp_cacheline = tl->hwsp_cacheline;
647 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
649 spin_lock_init(&rq->lock);
650 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
651 tl->fence_context, seqno);
653 /* We bump the ref for the fence chain */
654 i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
655 i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify);
657 i915_sched_node_init(&rq->sched);
659 /* No zalloc, must clear what we need by hand */
660 rq->file_priv = NULL;
662 rq->capture_list = NULL;
664 rq->execution_mask = ALL_ENGINES;
666 INIT_LIST_HEAD(&rq->active_list);
667 INIT_LIST_HEAD(&rq->execute_cb);
670 * Reserve space in the ring buffer for all the commands required to
671 * eventually emit this request. This is to guarantee that the
672 * i915_request_add() call can't fail. Note that the reserve may need
673 * to be redone if the request is not actually submitted straight
674 * away, e.g. because a GPU scheduler has deferred it.
676 * Note that due to how we add reserved_space to intel_ring_begin()
677 * we need to double our request to ensure that if we need to wrap
678 * around inside i915_request_add() there is sufficient space at
679 * the beginning of the ring as well.
682 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
685 * Record the position of the start of the request so that
686 * should we detect the updated seqno part-way through the
687 * GPU processing the request, we never over-estimate the
688 * position of the head.
690 rq->head = rq->ring->emit;
692 ret = rq->engine->request_alloc(rq);
696 rq->infix = rq->ring->emit; /* end of header; start of user payload */
698 intel_context_mark_active(ce);
702 ce->ring->emit = rq->head;
704 /* Make sure we didn't add ourselves to external state before freeing */
705 GEM_BUG_ON(!list_empty(&rq->active_list));
706 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
707 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
710 kmem_cache_free(global.slab_requests, rq);
712 intel_context_unpin(ce);
716 struct i915_request *
717 i915_request_create(struct intel_context *ce)
719 struct i915_request *rq;
720 struct intel_timeline *tl;
722 tl = intel_context_timeline_lock(ce);
726 /* Move our oldest request to the slab-cache (if not in use!) */
727 rq = list_first_entry(&tl->requests, typeof(*rq), link);
728 if (!list_is_last(&rq->link, &tl->requests))
729 i915_request_retire(rq);
731 intel_context_enter(ce);
732 rq = __i915_request_create(ce, GFP_KERNEL);
733 intel_context_exit(ce); /* active reference transferred to request */
737 /* Check that we do not interrupt ourselves with a new request */
738 rq->cookie = lockdep_pin_lock(&tl->mutex);
743 intel_context_timeline_unlock(tl);
748 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
750 if (list_is_first(&signal->link, &signal->timeline->requests))
753 signal = list_prev_entry(signal, link);
754 if (intel_timeline_sync_is_later(rq->timeline, &signal->fence))
757 return i915_sw_fence_await_dma_fence(&rq->submit,
762 static intel_engine_mask_t
763 already_busywaiting(struct i915_request *rq)
766 * Polling a semaphore causes bus traffic, delaying other users of
767 * both the GPU and CPU. We want to limit the impact on others,
768 * while taking advantage of early submission to reduce GPU
769 * latency. Therefore we restrict ourselves to not using more
770 * than one semaphore from each source, and not using a semaphore
771 * if we have detected the engine is saturated (i.e. would not be
772 * submitted early and cause bus traffic reading an already passed
775 * See the are-we-too-late? check in __i915_request_submit().
777 return rq->sched.semaphores | rq->engine->saturated;
781 emit_semaphore_wait(struct i915_request *to,
782 struct i915_request *from,
789 GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
790 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
792 /* Just emit the first semaphore we see as request space is limited. */
793 if (already_busywaiting(to) & from->engine->mask)
794 return i915_sw_fence_await_dma_fence(&to->submit,
798 err = i915_request_await_start(to, from);
802 /* Only submit our spinner after the signaler is running! */
803 err = __i915_request_await_execution(to, from, NULL, gfp);
807 /* We need to pin the signaler's HWSP until we are finished reading. */
808 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
812 cs = intel_ring_begin(to, 4);
817 * Using greater-than-or-equal here means we have to worry
818 * about seqno wraparound. To side step that issue, we swap
819 * the timeline HWSP upon wrapping, so that everyone listening
820 * for the old (pre-wrap) values do not see the much smaller
821 * (post-wrap) values than they were expecting (and so wait
824 *cs++ = MI_SEMAPHORE_WAIT |
825 MI_SEMAPHORE_GLOBAL_GTT |
827 MI_SEMAPHORE_SAD_GTE_SDD;
828 *cs++ = from->fence.seqno;
832 intel_ring_advance(to, cs);
833 to->sched.semaphores |= from->engine->mask;
834 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
839 i915_request_await_request(struct i915_request *to, struct i915_request *from)
843 GEM_BUG_ON(to == from);
844 GEM_BUG_ON(to->timeline == from->timeline);
846 if (i915_request_completed(from))
849 if (to->engine->schedule) {
850 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
855 if (to->engine == from->engine) {
856 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
859 } else if (intel_engine_has_semaphores(to->engine) &&
860 to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) {
861 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
863 ret = i915_sw_fence_await_dma_fence(&to->submit,
870 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
871 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
882 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
884 struct dma_fence **child = &fence;
885 unsigned int nchild = 1;
889 * Note that if the fence-array was created in signal-on-any mode,
890 * we should *not* decompose it into its individual fences. However,
891 * we don't currently store which mode the fence-array is operating
892 * in. Fortunately, the only user of signal-on-any is private to
893 * amdgpu and we should not see any incoming fence-array from
894 * sync-file being in signal-on-any mode.
896 if (dma_fence_is_array(fence)) {
897 struct dma_fence_array *array = to_dma_fence_array(fence);
899 child = array->fences;
900 nchild = array->num_fences;
906 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
910 * Requests on the same timeline are explicitly ordered, along
911 * with their dependencies, by i915_request_add() which ensures
912 * that requests are submitted in-order through each ring.
914 if (fence->context == rq->fence.context)
917 /* Squash repeated waits to the same timelines */
918 if (fence->context &&
919 intel_timeline_sync_is_later(rq->timeline, fence))
922 if (dma_fence_is_i915(fence))
923 ret = i915_request_await_request(rq, to_request(fence));
925 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
931 /* Record the latest fence used against each timeline */
933 intel_timeline_sync_set(rq->timeline, fence);
940 i915_request_await_execution(struct i915_request *rq,
941 struct dma_fence *fence,
942 void (*hook)(struct i915_request *rq,
943 struct dma_fence *signal))
945 struct dma_fence **child = &fence;
946 unsigned int nchild = 1;
949 if (dma_fence_is_array(fence)) {
950 struct dma_fence_array *array = to_dma_fence_array(fence);
952 /* XXX Error for signal-on-any fence arrays */
954 child = array->fences;
955 nchild = array->num_fences;
961 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
965 * We don't squash repeated fence dependencies here as we
966 * want to run our callback in all cases.
969 if (dma_fence_is_i915(fence))
970 ret = __i915_request_await_execution(rq,
975 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
986 * i915_request_await_object - set this request to (async) wait upon a bo
987 * @to: request we are wishing to use
988 * @obj: object which may be in use on another ring.
989 * @write: whether the wait is on behalf of a writer
991 * This code is meant to abstract object synchronization with the GPU.
992 * Conceptually we serialise writes between engines inside the GPU.
993 * We only allow one engine to write into a buffer at any time, but
994 * multiple readers. To ensure each has a coherent view of memory, we must:
996 * - If there is an outstanding write request to the object, the new
997 * request must wait for it to complete (either CPU or in hw, requests
998 * on the same ring will be naturally ordered).
1000 * - If we are a write request (pending_write_domain is set), the new
1001 * request must wait for outstanding read requests to complete.
1003 * Returns 0 if successful, else propagates up the lower layer error.
1006 i915_request_await_object(struct i915_request *to,
1007 struct drm_i915_gem_object *obj,
1010 struct dma_fence *excl;
1014 struct dma_fence **shared;
1015 unsigned int count, i;
1017 ret = dma_resv_get_fences_rcu(obj->base.resv,
1018 &excl, &count, &shared);
1022 for (i = 0; i < count; i++) {
1023 ret = i915_request_await_dma_fence(to, shared[i]);
1027 dma_fence_put(shared[i]);
1030 for (; i < count; i++)
1031 dma_fence_put(shared[i]);
1034 excl = dma_resv_get_excl_rcu(obj->base.resv);
1039 ret = i915_request_await_dma_fence(to, excl);
1041 dma_fence_put(excl);
1047 void i915_request_skip(struct i915_request *rq, int error)
1049 void *vaddr = rq->ring->vaddr;
1052 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1053 dma_fence_set_error(&rq->fence, error);
1055 if (rq->infix == rq->postfix)
1059 * As this request likely depends on state from the lost
1060 * context, clear out all the user operations leaving the
1061 * breadcrumb at the end (so we get the fence notifications).
1064 if (rq->postfix < head) {
1065 memset(vaddr + head, 0, rq->ring->size - head);
1068 memset(vaddr + head, 0, rq->postfix - head);
1069 rq->infix = rq->postfix;
1072 static struct i915_request *
1073 __i915_request_add_to_timeline(struct i915_request *rq)
1075 struct intel_timeline *timeline = rq->timeline;
1076 struct i915_request *prev;
1079 * Dependency tracking and request ordering along the timeline
1080 * is special cased so that we can eliminate redundant ordering
1081 * operations while building the request (we know that the timeline
1082 * itself is ordered, and here we guarantee it).
1084 * As we know we will need to emit tracking along the timeline,
1085 * we embed the hooks into our request struct -- at the cost of
1086 * having to have specialised no-allocation interfaces (which will
1087 * be beneficial elsewhere).
1089 * A second benefit to open-coding i915_request_await_request is
1090 * that we can apply a slight variant of the rules specialised
1091 * for timelines that jump between engines (such as virtual engines).
1092 * If we consider the case of virtual engine, we must emit a dma-fence
1093 * to prevent scheduling of the second request until the first is
1094 * complete (to maximise our greedy late load balancing) and this
1095 * precludes optimising to use semaphores serialisation of a single
1096 * timeline across engines.
1098 prev = rcu_dereference_protected(timeline->last_request.request,
1099 lockdep_is_held(&timeline->mutex));
1100 if (prev && !i915_request_completed(prev)) {
1101 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1102 i915_sw_fence_await_sw_fence(&rq->submit,
1106 __i915_sw_fence_await_dma_fence(&rq->submit,
1109 if (rq->engine->schedule)
1110 __i915_sched_node_add_dependency(&rq->sched,
1116 list_add_tail(&rq->link, &timeline->requests);
1119 * Make sure that no request gazumped us - if it was allocated after
1120 * our i915_request_alloc() and called __i915_request_add() before
1121 * us, the timeline will hold its seqno which is later than ours.
1123 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1124 __i915_active_request_set(&timeline->last_request, rq);
1130 * NB: This function is not allowed to fail. Doing so would mean the the
1131 * request is not being tracked for completion but the work itself is
1132 * going to happen on the hardware. This would be a Bad Thing(tm).
1134 struct i915_request *__i915_request_commit(struct i915_request *rq)
1136 struct intel_engine_cs *engine = rq->engine;
1137 struct intel_ring *ring = rq->ring;
1140 GEM_TRACE("%s fence %llx:%lld\n",
1141 engine->name, rq->fence.context, rq->fence.seqno);
1144 * To ensure that this call will not fail, space for its emissions
1145 * should already have been reserved in the ring buffer. Let the ring
1146 * know that it is time to use that space up.
1148 GEM_BUG_ON(rq->reserved_space > ring->space);
1149 rq->reserved_space = 0;
1150 rq->emitted_jiffies = jiffies;
1153 * Record the position of the start of the breadcrumb so that
1154 * should we detect the updated seqno part-way through the
1155 * GPU processing the request, we never over-estimate the
1156 * position of the ring's HEAD.
1158 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1159 GEM_BUG_ON(IS_ERR(cs));
1160 rq->postfix = intel_ring_offset(rq, cs);
1162 return __i915_request_add_to_timeline(rq);
1165 void __i915_request_queue(struct i915_request *rq,
1166 const struct i915_sched_attr *attr)
1169 * Let the backend know a new request has arrived that may need
1170 * to adjust the existing execution schedule due to a high priority
1171 * request - i.e. we may want to preempt the current request in order
1172 * to run a high priority dependency chain *before* we can execute this
1175 * This is called before the request is ready to run so that we can
1176 * decide whether to preempt the entire chain so that it is ready to
1177 * run at the earliest possible convenience.
1179 i915_sw_fence_commit(&rq->semaphore);
1180 if (attr && rq->engine->schedule)
1181 rq->engine->schedule(rq, attr);
1182 i915_sw_fence_commit(&rq->submit);
1185 void i915_request_add(struct i915_request *rq)
1187 struct i915_sched_attr attr = rq->gem_context->sched;
1188 struct intel_timeline * const tl = rq->timeline;
1189 struct i915_request *prev;
1191 lockdep_assert_held(&tl->mutex);
1192 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1194 trace_i915_request_add(rq);
1196 prev = __i915_request_commit(rq);
1199 * Boost actual workloads past semaphores!
1201 * With semaphores we spin on one engine waiting for another,
1202 * simply to reduce the latency of starting our work when
1203 * the signaler completes. However, if there is any other
1204 * work that we could be doing on this engine instead, that
1205 * is better utilisation and will reduce the overall duration
1206 * of the current work. To avoid PI boosting a semaphore
1207 * far in the distance past over useful work, we keep a history
1208 * of any semaphore use along our dependency chain.
1210 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1211 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1214 * Boost priorities to new clients (new request flows).
1216 * Allow interactive/synchronous clients to jump ahead of
1217 * the bulk clients. (FQ_CODEL)
1219 if (list_empty(&rq->sched.signalers_list))
1220 attr.priority |= I915_PRIORITY_WAIT;
1223 __i915_request_queue(rq, &attr);
1224 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1227 * In typical scenarios, we do not expect the previous request on
1228 * the timeline to be still tracked by timeline->last_request if it
1229 * has been completed. If the completed request is still here, that
1230 * implies that request retirement is a long way behind submission,
1231 * suggesting that we haven't been retiring frequently enough from
1232 * the combination of retire-before-alloc, waiters and the background
1233 * retirement worker. So if the last request on this timeline was
1234 * already completed, do a catch up pass, flushing the retirement queue
1235 * up to this client. Since we have now moved the heaviest operations
1236 * during retirement onto secondary workers, such as freeing objects
1237 * or contexts, retiring a bunch of requests is mostly list management
1238 * (and cache misses), and so we should not be overly penalizing this
1239 * client by performing excess work, though we may still performing
1240 * work on behalf of others -- but instead we should benefit from
1241 * improved resource management. (Well, that's the theory at least.)
1243 if (prev && i915_request_completed(prev) && prev->timeline == tl)
1244 i915_request_retire_upto(prev);
1246 mutex_unlock(&tl->mutex);
1249 static unsigned long local_clock_us(unsigned int *cpu)
1254 * Cheaply and approximately convert from nanoseconds to microseconds.
1255 * The result and subsequent calculations are also defined in the same
1256 * approximate microseconds units. The principal source of timing
1257 * error here is from the simple truncation.
1259 * Note that local_clock() is only defined wrt to the current CPU;
1260 * the comparisons are no longer valid if we switch CPUs. Instead of
1261 * blocking preemption for the entire busywait, we can detect the CPU
1262 * switch and use that as indicator of system load and a reason to
1263 * stop busywaiting, see busywait_stop().
1266 t = local_clock() >> 10;
1272 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1274 unsigned int this_cpu;
1276 if (time_after(local_clock_us(&this_cpu), timeout))
1279 return this_cpu != cpu;
1282 static bool __i915_spin_request(const struct i915_request * const rq,
1283 int state, unsigned long timeout_us)
1288 * Only wait for the request if we know it is likely to complete.
1290 * We don't track the timestamps around requests, nor the average
1291 * request length, so we do not have a good indicator that this
1292 * request will complete within the timeout. What we do know is the
1293 * order in which requests are executed by the context and so we can
1294 * tell if the request has been started. If the request is not even
1295 * running yet, it is a fair assumption that it will not complete
1296 * within our relatively short timeout.
1298 if (!i915_request_is_running(rq))
1302 * When waiting for high frequency requests, e.g. during synchronous
1303 * rendering split between the CPU and GPU, the finite amount of time
1304 * required to set up the irq and wait upon it limits the response
1305 * rate. By busywaiting on the request completion for a short while we
1306 * can service the high frequency waits as quick as possible. However,
1307 * if it is a slow request, we want to sleep as quickly as possible.
1308 * The tradeoff between waiting and sleeping is roughly the time it
1309 * takes to sleep on a request, on the order of a microsecond.
1312 timeout_us += local_clock_us(&cpu);
1314 if (i915_request_completed(rq))
1317 if (signal_pending_state(state, current))
1320 if (busywait_stop(timeout_us, cpu))
1324 } while (!need_resched());
1329 struct request_wait {
1330 struct dma_fence_cb cb;
1331 struct task_struct *tsk;
1334 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1336 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1338 wake_up_process(wait->tsk);
1342 * i915_request_wait - wait until execution of request has finished
1343 * @rq: the request to wait upon
1344 * @flags: how to wait
1345 * @timeout: how long to wait in jiffies
1347 * i915_request_wait() waits for the request to be completed, for a
1348 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1351 * Returns the remaining time (in jiffies) if the request completed, which may
1352 * be zero or -ETIME if the request is unfinished after the timeout expires.
1353 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1354 * pending before the request completes.
1356 long i915_request_wait(struct i915_request *rq,
1360 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1361 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1362 struct request_wait wait;
1365 GEM_BUG_ON(timeout < 0);
1367 if (dma_fence_is_signaled(&rq->fence))
1373 trace_i915_request_wait_begin(rq, flags);
1376 * We must never wait on the GPU while holding a lock as we
1377 * may need to perform a GPU reset. So while we don't need to
1378 * serialise wait/reset with an explicit lock, we do want
1379 * lockdep to detect potential dependency cycles.
1381 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1384 * Optimistic spin before touching IRQs.
1386 * We may use a rather large value here to offset the penalty of
1387 * switching away from the active task. Frequently, the client will
1388 * wait upon an old swapbuffer to throttle itself to remain within a
1389 * frame of the gpu. If the client is running in lockstep with the gpu,
1390 * then it should not be waiting long at all, and a sleep now will incur
1391 * extra scheduler latency in producing the next frame. To try to
1392 * avoid adding the cost of enabling/disabling the interrupt to the
1393 * short wait, we first spin to see if the request would have completed
1394 * in the time taken to setup the interrupt.
1396 * We need upto 5us to enable the irq, and upto 20us to hide the
1397 * scheduler latency of a context switch, ignoring the secondary
1398 * impacts from a context switch such as cache eviction.
1400 * The scheme used for low-latency IO is called "hybrid interrupt
1401 * polling". The suggestion there is to sleep until just before you
1402 * expect to be woken by the device interrupt and then poll for its
1403 * completion. That requires having a good predictor for the request
1404 * duration, which we currently lack.
1406 if (CONFIG_DRM_I915_SPIN_REQUEST &&
1407 __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
1408 dma_fence_signal(&rq->fence);
1413 * This client is about to stall waiting for the GPU. In many cases
1414 * this is undesirable and limits the throughput of the system, as
1415 * many clients cannot continue processing user input/output whilst
1416 * blocked. RPS autotuning may take tens of milliseconds to respond
1417 * to the GPU load and thus incurs additional latency for the client.
1418 * We can circumvent that by promoting the GPU frequency to maximum
1419 * before we sleep. This makes the GPU throttle up much more quickly
1420 * (good for benchmarks and user experience, e.g. window animations),
1421 * but at a cost of spending more power processing the workload
1422 * (bad for battery).
1424 if (flags & I915_WAIT_PRIORITY) {
1425 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1427 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1431 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1435 set_current_state(state);
1437 if (i915_request_completed(rq)) {
1438 dma_fence_signal(&rq->fence);
1442 if (signal_pending_state(state, current)) {
1443 timeout = -ERESTARTSYS;
1452 timeout = io_schedule_timeout(timeout);
1454 __set_current_state(TASK_RUNNING);
1456 dma_fence_remove_callback(&rq->fence, &wait.cb);
1459 mutex_release(&rq->engine->gt->reset.mutex.dep_map, 0, _THIS_IP_);
1460 trace_i915_request_wait_end(rq);
1464 bool i915_retire_requests(struct drm_i915_private *i915)
1466 struct intel_gt_timelines *timelines = &i915->gt.timelines;
1467 struct intel_timeline *tl, *tn;
1468 unsigned long flags;
1471 spin_lock_irqsave(&timelines->lock, flags);
1472 list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
1473 if (!mutex_trylock(&tl->mutex))
1476 intel_timeline_get(tl);
1477 GEM_BUG_ON(!tl->active_count);
1478 tl->active_count++; /* pin the list element */
1479 spin_unlock_irqrestore(&timelines->lock, flags);
1481 retire_requests(tl);
1483 spin_lock_irqsave(&timelines->lock, flags);
1485 /* Resume iteration after dropping lock */
1486 list_safe_reset_next(tl, tn, link);
1487 if (!--tl->active_count)
1488 list_del(&tl->link);
1490 mutex_unlock(&tl->mutex);
1492 /* Defer the final release to after the spinlock */
1493 if (refcount_dec_and_test(&tl->kref.refcount)) {
1494 GEM_BUG_ON(tl->active_count);
1495 list_add(&tl->link, &free);
1498 spin_unlock_irqrestore(&timelines->lock, flags);
1500 list_for_each_entry_safe(tl, tn, &free, link)
1501 __intel_timeline_free(&tl->kref);
1503 return !list_empty(&timelines->active_list);
1506 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1507 #include "selftests/mock_request.c"
1508 #include "selftests/i915_request.c"
1511 static void i915_global_request_shrink(void)
1513 kmem_cache_shrink(global.slab_dependencies);
1514 kmem_cache_shrink(global.slab_execute_cbs);
1515 kmem_cache_shrink(global.slab_requests);
1518 static void i915_global_request_exit(void)
1520 kmem_cache_destroy(global.slab_dependencies);
1521 kmem_cache_destroy(global.slab_execute_cbs);
1522 kmem_cache_destroy(global.slab_requests);
1525 static struct i915_global_request global = { {
1526 .shrink = i915_global_request_shrink,
1527 .exit = i915_global_request_exit,
1530 int __init i915_global_request_init(void)
1532 global.slab_requests = KMEM_CACHE(i915_request,
1533 SLAB_HWCACHE_ALIGN |
1534 SLAB_RECLAIM_ACCOUNT |
1535 SLAB_TYPESAFE_BY_RCU);
1536 if (!global.slab_requests)
1539 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1540 SLAB_HWCACHE_ALIGN |
1541 SLAB_RECLAIM_ACCOUNT |
1542 SLAB_TYPESAFE_BY_RCU);
1543 if (!global.slab_execute_cbs)
1546 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1547 SLAB_HWCACHE_ALIGN |
1548 SLAB_RECLAIM_ACCOUNT);
1549 if (!global.slab_dependencies)
1550 goto err_execute_cbs;
1552 i915_global_register(&global.base);
1556 kmem_cache_destroy(global.slab_execute_cbs);
1558 kmem_cache_destroy(global.slab_requests);