2 * Copyright © 2008-2015 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "gem/i915_gem_context.h"
33 #include "gt/intel_context.h"
34 #include "gt/intel_ring.h"
35 #include "gt/intel_rps.h"
37 #include "i915_active.h"
39 #include "i915_globals.h"
40 #include "i915_trace.h"
44 struct list_head link;
46 struct i915_sw_fence *fence;
47 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
48 struct i915_request *signal;
51 static struct i915_global_request {
52 struct i915_global base;
53 struct kmem_cache *slab_requests;
54 struct kmem_cache *slab_dependencies;
55 struct kmem_cache *slab_execute_cbs;
58 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
60 return dev_name(to_request(fence)->i915->drm.dev);
63 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
65 const struct i915_gem_context *ctx;
68 * The timeline struct (as part of the ppgtt underneath a context)
69 * may be freed when the request is no longer in use by the GPU.
70 * We could extend the life of a context to beyond that of all
71 * fences, possibly keeping the hw resource around indefinitely,
72 * or we just give them a false name. Since
73 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
74 * lie seems justifiable.
76 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
79 ctx = i915_request_gem_context(to_request(fence));
81 return "[" DRIVER_NAME "]";
86 static bool i915_fence_signaled(struct dma_fence *fence)
88 return i915_request_completed(to_request(fence));
91 static bool i915_fence_enable_signaling(struct dma_fence *fence)
93 return i915_request_enable_breadcrumb(to_request(fence));
96 static signed long i915_fence_wait(struct dma_fence *fence,
100 return i915_request_wait(to_request(fence),
101 interruptible | I915_WAIT_PRIORITY,
105 static void i915_fence_release(struct dma_fence *fence)
107 struct i915_request *rq = to_request(fence);
110 * The request is put onto a RCU freelist (i.e. the address
111 * is immediately reused), mark the fences as being freed now.
112 * Otherwise the debugobjects for the fences are only marked as
113 * freed when the slab cache itself is freed, and so we would get
114 * caught trying to reuse dead objects.
116 i915_sw_fence_fini(&rq->submit);
117 i915_sw_fence_fini(&rq->semaphore);
119 kmem_cache_free(global.slab_requests, rq);
122 const struct dma_fence_ops i915_fence_ops = {
123 .get_driver_name = i915_fence_get_driver_name,
124 .get_timeline_name = i915_fence_get_timeline_name,
125 .enable_signaling = i915_fence_enable_signaling,
126 .signaled = i915_fence_signaled,
127 .wait = i915_fence_wait,
128 .release = i915_fence_release,
131 static void irq_execute_cb(struct irq_work *wrk)
133 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
135 i915_sw_fence_complete(cb->fence);
136 kmem_cache_free(global.slab_execute_cbs, cb);
139 static void irq_execute_cb_hook(struct irq_work *wrk)
141 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
143 cb->hook(container_of(cb->fence, struct i915_request, submit),
145 i915_request_put(cb->signal);
150 static void __notify_execute_cb(struct i915_request *rq)
152 struct execute_cb *cb;
154 lockdep_assert_held(&rq->lock);
156 if (list_empty(&rq->execute_cb))
159 list_for_each_entry(cb, &rq->execute_cb, link)
160 irq_work_queue(&cb->work);
163 * XXX Rollback on __i915_request_unsubmit()
165 * In the future, perhaps when we have an active time-slicing scheduler,
166 * it will be interesting to unsubmit parallel execution and remove
167 * busywaits from the GPU until their master is restarted. This is
168 * quite hairy, we have to carefully rollback the fence and do a
169 * preempt-to-idle cycle on the target engine, all the while the
170 * master execute_cb may refire.
172 INIT_LIST_HEAD(&rq->execute_cb);
176 remove_from_client(struct i915_request *request)
178 struct drm_i915_file_private *file_priv;
180 if (!READ_ONCE(request->file_priv))
184 file_priv = xchg(&request->file_priv, NULL);
186 spin_lock(&file_priv->mm.lock);
187 list_del(&request->client_link);
188 spin_unlock(&file_priv->mm.lock);
193 static void free_capture_list(struct i915_request *request)
195 struct i915_capture_list *capture;
197 capture = fetch_and_zero(&request->capture_list);
199 struct i915_capture_list *next = capture->next;
206 static void remove_from_engine(struct i915_request *rq)
208 struct intel_engine_cs *engine, *locked;
211 * Virtual engines complicate acquiring the engine timeline lock,
212 * as their rq->engine pointer is not stable until under that
213 * engine lock. The simple ploy we use is to take the lock then
214 * check that the rq still belongs to the newly locked engine.
216 locked = READ_ONCE(rq->engine);
217 spin_lock_irq(&locked->active.lock);
218 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
219 spin_unlock(&locked->active.lock);
220 spin_lock(&engine->active.lock);
223 list_del_init(&rq->sched.link);
224 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
225 clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
226 spin_unlock_irq(&locked->active.lock);
229 bool i915_request_retire(struct i915_request *rq)
231 if (!i915_request_completed(rq))
236 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
237 trace_i915_request_retire(rq);
240 * We know the GPU must have read the request to have
241 * sent us the seqno + interrupt, so use the position
242 * of tail of the request to update the last known position
245 * Note this requires that we are always called in request
248 GEM_BUG_ON(!list_is_first(&rq->link,
249 &i915_request_timeline(rq)->requests));
250 rq->ring->head = rq->postfix;
253 * We only loosely track inflight requests across preemption,
254 * and so we may find ourselves attempting to retire a _completed_
255 * request that we have removed from the HW and put back on a run
258 remove_from_engine(rq);
260 spin_lock_irq(&rq->lock);
261 i915_request_mark_complete(rq);
262 if (!i915_request_signaled(rq))
263 dma_fence_signal_locked(&rq->fence);
264 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
265 i915_request_cancel_breadcrumb(rq);
266 if (i915_request_has_waitboost(rq)) {
267 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
268 atomic_dec(&rq->engine->gt->rps.num_waiters);
270 if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
271 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
272 __notify_execute_cb(rq);
274 GEM_BUG_ON(!list_empty(&rq->execute_cb));
275 spin_unlock_irq(&rq->lock);
277 remove_from_client(rq);
280 intel_context_exit(rq->context);
281 intel_context_unpin(rq->context);
283 free_capture_list(rq);
284 i915_sched_node_fini(&rq->sched);
285 i915_request_put(rq);
290 void i915_request_retire_upto(struct i915_request *rq)
292 struct intel_timeline * const tl = i915_request_timeline(rq);
293 struct i915_request *tmp;
297 GEM_BUG_ON(!i915_request_completed(rq));
300 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
301 } while (i915_request_retire(tmp) && tmp != rq);
305 __await_execution(struct i915_request *rq,
306 struct i915_request *signal,
307 void (*hook)(struct i915_request *rq,
308 struct dma_fence *signal),
311 struct execute_cb *cb;
313 if (i915_request_is_active(signal)) {
315 hook(rq, &signal->fence);
319 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
323 cb->fence = &rq->submit;
324 i915_sw_fence_await(cb->fence);
325 init_irq_work(&cb->work, irq_execute_cb);
329 cb->signal = i915_request_get(signal);
330 cb->work.func = irq_execute_cb_hook;
333 spin_lock_irq(&signal->lock);
334 if (i915_request_is_active(signal)) {
336 hook(rq, &signal->fence);
337 i915_request_put(signal);
339 i915_sw_fence_complete(cb->fence);
340 kmem_cache_free(global.slab_execute_cbs, cb);
342 list_add_tail(&cb->link, &signal->execute_cb);
344 spin_unlock_irq(&signal->lock);
346 /* Copy across semaphore status as we need the same behaviour */
347 rq->sched.flags |= signal->sched.flags;
351 bool __i915_request_submit(struct i915_request *request)
353 struct intel_engine_cs *engine = request->engine;
356 RQ_TRACE(request, "\n");
358 GEM_BUG_ON(!irqs_disabled());
359 lockdep_assert_held(&engine->active.lock);
362 * With the advent of preempt-to-busy, we frequently encounter
363 * requests that we have unsubmitted from HW, but left running
364 * until the next ack and so have completed in the meantime. On
365 * resubmission of that completed request, we can skip
366 * updating the payload, and execlists can even skip submitting
369 * We must remove the request from the caller's priority queue,
370 * and the caller must only call us when the request is in their
371 * priority queue, under the active.lock. This ensures that the
372 * request has *not* yet been retired and we can safely move
373 * the request into the engine->active.list where it will be
374 * dropped upon retiring. (Otherwise if resubmit a *retired*
375 * request, this would be a horrible use-after-free.)
377 if (i915_request_completed(request))
380 if (intel_context_is_banned(request->context))
381 i915_request_skip(request, -EIO);
384 * Are we using semaphores when the gpu is already saturated?
386 * Using semaphores incurs a cost in having the GPU poll a
387 * memory location, busywaiting for it to change. The continual
388 * memory reads can have a noticeable impact on the rest of the
389 * system with the extra bus traffic, stalling the cpu as it too
390 * tries to access memory across the bus (perf stat -e bus-cycles).
392 * If we installed a semaphore on this request and we only submit
393 * the request after the signaler completed, that indicates the
394 * system is overloaded and using semaphores at this time only
395 * increases the amount of work we are doing. If so, we disable
396 * further use of semaphores until we are idle again, whence we
397 * optimistically try again.
399 if (request->sched.semaphores &&
400 i915_sw_fence_signaled(&request->semaphore))
401 engine->saturated |= request->sched.semaphores;
403 engine->emit_fini_breadcrumb(request,
404 request->ring->vaddr + request->postfix);
406 trace_i915_request_execute(request);
410 xfer: /* We may be recursing from the signal callback of another i915 fence */
411 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
413 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
414 list_move_tail(&request->sched.link, &engine->active.requests);
415 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
418 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
419 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
420 !i915_request_enable_breadcrumb(request))
421 intel_engine_signal_breadcrumbs(engine);
423 __notify_execute_cb(request);
425 spin_unlock(&request->lock);
430 void i915_request_submit(struct i915_request *request)
432 struct intel_engine_cs *engine = request->engine;
435 /* Will be called from irq-context when using foreign fences. */
436 spin_lock_irqsave(&engine->active.lock, flags);
438 __i915_request_submit(request);
440 spin_unlock_irqrestore(&engine->active.lock, flags);
443 void __i915_request_unsubmit(struct i915_request *request)
445 struct intel_engine_cs *engine = request->engine;
447 RQ_TRACE(request, "\n");
449 GEM_BUG_ON(!irqs_disabled());
450 lockdep_assert_held(&engine->active.lock);
453 * Only unwind in reverse order, required so that the per-context list
454 * is kept in seqno/ring order.
457 /* We may be recursing from the signal callback of another i915 fence */
458 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
460 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
461 i915_request_cancel_breadcrumb(request);
463 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
464 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
466 spin_unlock(&request->lock);
468 /* We've already spun, don't charge on resubmitting. */
469 if (request->sched.semaphores && i915_request_started(request)) {
470 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
471 request->sched.semaphores = 0;
475 * We don't need to wake_up any waiters on request->execute, they
476 * will get woken by any other event or us re-adding this request
477 * to the engine timeline (__i915_request_submit()). The waiters
478 * should be quite adapt at finding that the request now has a new
479 * global_seqno to the one they went to sleep on.
483 void i915_request_unsubmit(struct i915_request *request)
485 struct intel_engine_cs *engine = request->engine;
488 /* Will be called from irq-context when using foreign fences. */
489 spin_lock_irqsave(&engine->active.lock, flags);
491 __i915_request_unsubmit(request);
493 spin_unlock_irqrestore(&engine->active.lock, flags);
496 static int __i915_sw_fence_call
497 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
499 struct i915_request *request =
500 container_of(fence, typeof(*request), submit);
504 trace_i915_request_submit(request);
506 if (unlikely(fence->error))
507 i915_request_skip(request, fence->error);
510 * We need to serialize use of the submit_request() callback
511 * with its hotplugging performed during an emergency
512 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
513 * critical section in order to force i915_gem_set_wedged() to
514 * wait until the submit_request() is completed before
518 request->engine->submit_request(request);
523 i915_request_put(request);
530 static int __i915_sw_fence_call
531 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
533 struct i915_request *request =
534 container_of(fence, typeof(*request), semaphore);
538 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
542 i915_request_put(request);
549 static void retire_requests(struct intel_timeline *tl)
551 struct i915_request *rq, *rn;
553 list_for_each_entry_safe(rq, rn, &tl->requests, link)
554 if (!i915_request_retire(rq))
558 static noinline struct i915_request *
559 request_alloc_slow(struct intel_timeline *tl, gfp_t gfp)
561 struct i915_request *rq;
563 if (list_empty(&tl->requests))
566 if (!gfpflags_allow_blocking(gfp))
569 /* Move our oldest request to the slab-cache (if not in use!) */
570 rq = list_first_entry(&tl->requests, typeof(*rq), link);
571 i915_request_retire(rq);
573 rq = kmem_cache_alloc(global.slab_requests,
574 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
578 /* Ratelimit ourselves to prevent oom from malicious clients */
579 rq = list_last_entry(&tl->requests, typeof(*rq), link);
580 cond_synchronize_rcu(rq->rcustate);
582 /* Retire our old requests in the hope that we free some */
586 return kmem_cache_alloc(global.slab_requests, gfp);
589 static void __i915_request_ctor(void *arg)
591 struct i915_request *rq = arg;
593 spin_lock_init(&rq->lock);
594 i915_sched_node_init(&rq->sched);
595 i915_sw_fence_init(&rq->submit, submit_notify);
596 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
598 rq->file_priv = NULL;
599 rq->capture_list = NULL;
601 INIT_LIST_HEAD(&rq->execute_cb);
604 struct i915_request *
605 __i915_request_create(struct intel_context *ce, gfp_t gfp)
607 struct intel_timeline *tl = ce->timeline;
608 struct i915_request *rq;
612 might_sleep_if(gfpflags_allow_blocking(gfp));
614 /* Check that the caller provided an already pinned context */
615 __intel_context_pin(ce);
618 * Beware: Dragons be flying overhead.
620 * We use RCU to look up requests in flight. The lookups may
621 * race with the request being allocated from the slab freelist.
622 * That is the request we are writing to here, may be in the process
623 * of being read by __i915_active_request_get_rcu(). As such,
624 * we have to be very careful when overwriting the contents. During
625 * the RCU lookup, we change chase the request->engine pointer,
626 * read the request->global_seqno and increment the reference count.
628 * The reference count is incremented atomically. If it is zero,
629 * the lookup knows the request is unallocated and complete. Otherwise,
630 * it is either still in use, or has been reallocated and reset
631 * with dma_fence_init(). This increment is safe for release as we
632 * check that the request we have a reference to and matches the active
635 * Before we increment the refcount, we chase the request->engine
636 * pointer. We must not call kmem_cache_zalloc() or else we set
637 * that pointer to NULL and cause a crash during the lookup. If
638 * we see the request is completed (based on the value of the
639 * old engine and seqno), the lookup is complete and reports NULL.
640 * If we decide the request is not completed (new engine or seqno),
641 * then we grab a reference and double check that it is still the
642 * active request - which it won't be and restart the lookup.
644 * Do not use kmem_cache_zalloc() here!
646 rq = kmem_cache_alloc(global.slab_requests,
647 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
649 rq = request_alloc_slow(tl, gfp);
656 ret = intel_timeline_get_seqno(tl, rq, &seqno);
660 rq->i915 = ce->engine->i915;
662 rq->engine = ce->engine;
664 rq->execution_mask = ce->engine->mask;
666 RCU_INIT_POINTER(rq->timeline, tl);
667 RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
668 rq->hwsp_seqno = tl->hwsp_seqno;
670 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
672 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
673 tl->fence_context, seqno);
675 /* We bump the ref for the fence chain */
676 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
677 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
679 i915_sched_node_reinit(&rq->sched);
681 /* No zalloc, everything must be cleared after use */
683 GEM_BUG_ON(rq->file_priv);
684 GEM_BUG_ON(rq->capture_list);
685 GEM_BUG_ON(!list_empty(&rq->execute_cb));
688 * Reserve space in the ring buffer for all the commands required to
689 * eventually emit this request. This is to guarantee that the
690 * i915_request_add() call can't fail. Note that the reserve may need
691 * to be redone if the request is not actually submitted straight
692 * away, e.g. because a GPU scheduler has deferred it.
694 * Note that due to how we add reserved_space to intel_ring_begin()
695 * we need to double our request to ensure that if we need to wrap
696 * around inside i915_request_add() there is sufficient space at
697 * the beginning of the ring as well.
700 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
703 * Record the position of the start of the request so that
704 * should we detect the updated seqno part-way through the
705 * GPU processing the request, we never over-estimate the
706 * position of the head.
708 rq->head = rq->ring->emit;
710 ret = rq->engine->request_alloc(rq);
714 rq->infix = rq->ring->emit; /* end of header; start of user payload */
716 intel_context_mark_active(ce);
720 ce->ring->emit = rq->head;
722 /* Make sure we didn't add ourselves to external state before freeing */
723 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
724 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
727 kmem_cache_free(global.slab_requests, rq);
729 intel_context_unpin(ce);
733 struct i915_request *
734 i915_request_create(struct intel_context *ce)
736 struct i915_request *rq;
737 struct intel_timeline *tl;
739 tl = intel_context_timeline_lock(ce);
743 /* Move our oldest request to the slab-cache (if not in use!) */
744 rq = list_first_entry(&tl->requests, typeof(*rq), link);
745 if (!list_is_last(&rq->link, &tl->requests))
746 i915_request_retire(rq);
748 intel_context_enter(ce);
749 rq = __i915_request_create(ce, GFP_KERNEL);
750 intel_context_exit(ce); /* active reference transferred to request */
754 /* Check that we do not interrupt ourselves with a new request */
755 rq->cookie = lockdep_pin_lock(&tl->mutex);
760 intel_context_timeline_unlock(tl);
765 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
767 struct dma_fence *fence;
770 GEM_BUG_ON(i915_request_timeline(rq) ==
771 rcu_access_pointer(signal->timeline));
775 spin_lock_irq(&signal->lock);
776 if (!i915_request_started(signal) &&
777 !list_is_first(&signal->link,
778 &rcu_dereference(signal->timeline)->requests)) {
779 struct i915_request *prev = list_prev_entry(signal, link);
782 * Peek at the request before us in the timeline. That
783 * request will only be valid before it is retired, so
784 * after acquiring a reference to it, confirm that it is
785 * still part of the signaler's timeline.
787 if (i915_request_get_rcu(prev)) {
788 if (list_next_entry(prev, link) == signal)
789 fence = &prev->fence;
791 i915_request_put(prev);
794 spin_unlock_irq(&signal->lock);
800 if (intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
801 err = i915_sw_fence_await_dma_fence(&rq->submit,
804 dma_fence_put(fence);
809 static intel_engine_mask_t
810 already_busywaiting(struct i915_request *rq)
813 * Polling a semaphore causes bus traffic, delaying other users of
814 * both the GPU and CPU. We want to limit the impact on others,
815 * while taking advantage of early submission to reduce GPU
816 * latency. Therefore we restrict ourselves to not using more
817 * than one semaphore from each source, and not using a semaphore
818 * if we have detected the engine is saturated (i.e. would not be
819 * submitted early and cause bus traffic reading an already passed
822 * See the are-we-too-late? check in __i915_request_submit().
824 return rq->sched.semaphores | rq->engine->saturated;
828 __emit_semaphore_wait(struct i915_request *to,
829 struct i915_request *from,
832 const int has_token = INTEL_GEN(to->i915) >= 12;
837 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
839 /* We need to pin the signaler's HWSP until we are finished reading. */
840 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
848 cs = intel_ring_begin(to, len);
853 * Using greater-than-or-equal here means we have to worry
854 * about seqno wraparound. To side step that issue, we swap
855 * the timeline HWSP upon wrapping, so that everyone listening
856 * for the old (pre-wrap) values do not see the much smaller
857 * (post-wrap) values than they were expecting (and so wait
860 *cs++ = (MI_SEMAPHORE_WAIT |
861 MI_SEMAPHORE_GLOBAL_GTT |
863 MI_SEMAPHORE_SAD_GTE_SDD) +
873 intel_ring_advance(to, cs);
878 emit_semaphore_wait(struct i915_request *to,
879 struct i915_request *from,
882 /* Just emit the first semaphore we see as request space is limited. */
883 if (already_busywaiting(to) & from->engine->mask)
886 if (i915_request_await_start(to, from) < 0)
889 /* Only submit our spinner after the signaler is running! */
890 if (__await_execution(to, from, NULL, gfp))
893 if (__emit_semaphore_wait(to, from, from->fence.seqno))
896 to->sched.semaphores |= from->engine->mask;
897 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
901 return i915_sw_fence_await_dma_fence(&to->submit,
907 i915_request_await_request(struct i915_request *to, struct i915_request *from)
911 GEM_BUG_ON(to == from);
912 GEM_BUG_ON(to->timeline == from->timeline);
914 if (i915_request_completed(from))
917 if (to->engine->schedule) {
918 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
923 if (to->engine == from->engine)
924 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
927 else if (intel_context_use_semaphores(to->context))
928 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
930 ret = i915_sw_fence_await_dma_fence(&to->submit,
936 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
937 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
948 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
950 struct dma_fence **child = &fence;
951 unsigned int nchild = 1;
955 * Note that if the fence-array was created in signal-on-any mode,
956 * we should *not* decompose it into its individual fences. However,
957 * we don't currently store which mode the fence-array is operating
958 * in. Fortunately, the only user of signal-on-any is private to
959 * amdgpu and we should not see any incoming fence-array from
960 * sync-file being in signal-on-any mode.
962 if (dma_fence_is_array(fence)) {
963 struct dma_fence_array *array = to_dma_fence_array(fence);
965 child = array->fences;
966 nchild = array->num_fences;
972 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
973 i915_sw_fence_set_error_once(&rq->submit, fence->error);
978 * Requests on the same timeline are explicitly ordered, along
979 * with their dependencies, by i915_request_add() which ensures
980 * that requests are submitted in-order through each ring.
982 if (fence->context == rq->fence.context)
985 /* Squash repeated waits to the same timelines */
986 if (fence->context &&
987 intel_timeline_sync_is_later(i915_request_timeline(rq),
991 if (dma_fence_is_i915(fence))
992 ret = i915_request_await_request(rq, to_request(fence));
994 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
995 fence->context ? I915_FENCE_TIMEOUT : 0,
1000 /* Record the latest fence used against each timeline */
1002 intel_timeline_sync_set(i915_request_timeline(rq),
1009 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1010 struct dma_fence *fence)
1012 return __intel_timeline_sync_is_later(tl,
1017 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1018 const struct dma_fence *fence)
1020 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1024 __i915_request_await_execution(struct i915_request *to,
1025 struct i915_request *from,
1026 void (*hook)(struct i915_request *rq,
1027 struct dma_fence *signal))
1031 /* Submit both requests at the same time */
1032 err = __await_execution(to, from, hook, I915_FENCE_GFP);
1036 /* Squash repeated depenendices to the same timelines */
1037 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1041 /* Ensure both start together [after all semaphores in signal] */
1042 if (intel_engine_has_semaphores(to->engine))
1043 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1045 err = i915_request_await_start(to, from);
1049 /* Couple the dependency tree for PI on this exposed to->fence */
1050 if (to->engine->schedule) {
1051 err = i915_sched_node_add_dependency(&to->sched, &from->sched);
1056 return intel_timeline_sync_set_start(i915_request_timeline(to),
1061 i915_request_await_execution(struct i915_request *rq,
1062 struct dma_fence *fence,
1063 void (*hook)(struct i915_request *rq,
1064 struct dma_fence *signal))
1066 struct dma_fence **child = &fence;
1067 unsigned int nchild = 1;
1070 if (dma_fence_is_array(fence)) {
1071 struct dma_fence_array *array = to_dma_fence_array(fence);
1073 /* XXX Error for signal-on-any fence arrays */
1075 child = array->fences;
1076 nchild = array->num_fences;
1077 GEM_BUG_ON(!nchild);
1082 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1083 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1088 * We don't squash repeated fence dependencies here as we
1089 * want to run our callback in all cases.
1092 if (dma_fence_is_i915(fence))
1093 ret = __i915_request_await_execution(rq,
1097 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1108 * i915_request_await_object - set this request to (async) wait upon a bo
1109 * @to: request we are wishing to use
1110 * @obj: object which may be in use on another ring.
1111 * @write: whether the wait is on behalf of a writer
1113 * This code is meant to abstract object synchronization with the GPU.
1114 * Conceptually we serialise writes between engines inside the GPU.
1115 * We only allow one engine to write into a buffer at any time, but
1116 * multiple readers. To ensure each has a coherent view of memory, we must:
1118 * - If there is an outstanding write request to the object, the new
1119 * request must wait for it to complete (either CPU or in hw, requests
1120 * on the same ring will be naturally ordered).
1122 * - If we are a write request (pending_write_domain is set), the new
1123 * request must wait for outstanding read requests to complete.
1125 * Returns 0 if successful, else propagates up the lower layer error.
1128 i915_request_await_object(struct i915_request *to,
1129 struct drm_i915_gem_object *obj,
1132 struct dma_fence *excl;
1136 struct dma_fence **shared;
1137 unsigned int count, i;
1139 ret = dma_resv_get_fences_rcu(obj->base.resv,
1140 &excl, &count, &shared);
1144 for (i = 0; i < count; i++) {
1145 ret = i915_request_await_dma_fence(to, shared[i]);
1149 dma_fence_put(shared[i]);
1152 for (; i < count; i++)
1153 dma_fence_put(shared[i]);
1156 excl = dma_resv_get_excl_rcu(obj->base.resv);
1161 ret = i915_request_await_dma_fence(to, excl);
1163 dma_fence_put(excl);
1169 void i915_request_skip(struct i915_request *rq, int error)
1171 void *vaddr = rq->ring->vaddr;
1174 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1175 dma_fence_set_error(&rq->fence, error);
1177 if (rq->infix == rq->postfix)
1181 * As this request likely depends on state from the lost
1182 * context, clear out all the user operations leaving the
1183 * breadcrumb at the end (so we get the fence notifications).
1186 if (rq->postfix < head) {
1187 memset(vaddr + head, 0, rq->ring->size - head);
1190 memset(vaddr + head, 0, rq->postfix - head);
1191 rq->infix = rq->postfix;
1194 static struct i915_request *
1195 __i915_request_add_to_timeline(struct i915_request *rq)
1197 struct intel_timeline *timeline = i915_request_timeline(rq);
1198 struct i915_request *prev;
1201 * Dependency tracking and request ordering along the timeline
1202 * is special cased so that we can eliminate redundant ordering
1203 * operations while building the request (we know that the timeline
1204 * itself is ordered, and here we guarantee it).
1206 * As we know we will need to emit tracking along the timeline,
1207 * we embed the hooks into our request struct -- at the cost of
1208 * having to have specialised no-allocation interfaces (which will
1209 * be beneficial elsewhere).
1211 * A second benefit to open-coding i915_request_await_request is
1212 * that we can apply a slight variant of the rules specialised
1213 * for timelines that jump between engines (such as virtual engines).
1214 * If we consider the case of virtual engine, we must emit a dma-fence
1215 * to prevent scheduling of the second request until the first is
1216 * complete (to maximise our greedy late load balancing) and this
1217 * precludes optimising to use semaphores serialisation of a single
1218 * timeline across engines.
1220 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1222 if (prev && !i915_request_completed(prev)) {
1223 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1224 i915_sw_fence_await_sw_fence(&rq->submit,
1228 __i915_sw_fence_await_dma_fence(&rq->submit,
1231 if (rq->engine->schedule)
1232 __i915_sched_node_add_dependency(&rq->sched,
1238 list_add_tail(&rq->link, &timeline->requests);
1241 * Make sure that no request gazumped us - if it was allocated after
1242 * our i915_request_alloc() and called __i915_request_add() before
1243 * us, the timeline will hold its seqno which is later than ours.
1245 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1251 * NB: This function is not allowed to fail. Doing so would mean the the
1252 * request is not being tracked for completion but the work itself is
1253 * going to happen on the hardware. This would be a Bad Thing(tm).
1255 struct i915_request *__i915_request_commit(struct i915_request *rq)
1257 struct intel_engine_cs *engine = rq->engine;
1258 struct intel_ring *ring = rq->ring;
1264 * To ensure that this call will not fail, space for its emissions
1265 * should already have been reserved in the ring buffer. Let the ring
1266 * know that it is time to use that space up.
1268 GEM_BUG_ON(rq->reserved_space > ring->space);
1269 rq->reserved_space = 0;
1270 rq->emitted_jiffies = jiffies;
1273 * Record the position of the start of the breadcrumb so that
1274 * should we detect the updated seqno part-way through the
1275 * GPU processing the request, we never over-estimate the
1276 * position of the ring's HEAD.
1278 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1279 GEM_BUG_ON(IS_ERR(cs));
1280 rq->postfix = intel_ring_offset(rq, cs);
1282 return __i915_request_add_to_timeline(rq);
1285 void __i915_request_queue(struct i915_request *rq,
1286 const struct i915_sched_attr *attr)
1289 * Let the backend know a new request has arrived that may need
1290 * to adjust the existing execution schedule due to a high priority
1291 * request - i.e. we may want to preempt the current request in order
1292 * to run a high priority dependency chain *before* we can execute this
1295 * This is called before the request is ready to run so that we can
1296 * decide whether to preempt the entire chain so that it is ready to
1297 * run at the earliest possible convenience.
1299 i915_sw_fence_commit(&rq->semaphore);
1300 if (attr && rq->engine->schedule)
1301 rq->engine->schedule(rq, attr);
1302 i915_sw_fence_commit(&rq->submit);
1305 void i915_request_add(struct i915_request *rq)
1307 struct intel_timeline * const tl = i915_request_timeline(rq);
1308 struct i915_sched_attr attr = {};
1309 struct i915_request *prev;
1311 lockdep_assert_held(&tl->mutex);
1312 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1314 trace_i915_request_add(rq);
1316 prev = __i915_request_commit(rq);
1318 if (rcu_access_pointer(rq->context->gem_context))
1319 attr = i915_request_gem_context(rq)->sched;
1322 * Boost actual workloads past semaphores!
1324 * With semaphores we spin on one engine waiting for another,
1325 * simply to reduce the latency of starting our work when
1326 * the signaler completes. However, if there is any other
1327 * work that we could be doing on this engine instead, that
1328 * is better utilisation and will reduce the overall duration
1329 * of the current work. To avoid PI boosting a semaphore
1330 * far in the distance past over useful work, we keep a history
1331 * of any semaphore use along our dependency chain.
1333 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1334 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1337 * Boost priorities to new clients (new request flows).
1339 * Allow interactive/synchronous clients to jump ahead of
1340 * the bulk clients. (FQ_CODEL)
1342 if (list_empty(&rq->sched.signalers_list))
1343 attr.priority |= I915_PRIORITY_WAIT;
1346 __i915_request_queue(rq, &attr);
1347 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1350 * In typical scenarios, we do not expect the previous request on
1351 * the timeline to be still tracked by timeline->last_request if it
1352 * has been completed. If the completed request is still here, that
1353 * implies that request retirement is a long way behind submission,
1354 * suggesting that we haven't been retiring frequently enough from
1355 * the combination of retire-before-alloc, waiters and the background
1356 * retirement worker. So if the last request on this timeline was
1357 * already completed, do a catch up pass, flushing the retirement queue
1358 * up to this client. Since we have now moved the heaviest operations
1359 * during retirement onto secondary workers, such as freeing objects
1360 * or contexts, retiring a bunch of requests is mostly list management
1361 * (and cache misses), and so we should not be overly penalizing this
1362 * client by performing excess work, though we may still performing
1363 * work on behalf of others -- but instead we should benefit from
1364 * improved resource management. (Well, that's the theory at least.)
1367 i915_request_completed(prev) &&
1368 rcu_access_pointer(prev->timeline) == tl)
1369 i915_request_retire_upto(prev);
1371 mutex_unlock(&tl->mutex);
1374 static unsigned long local_clock_us(unsigned int *cpu)
1379 * Cheaply and approximately convert from nanoseconds to microseconds.
1380 * The result and subsequent calculations are also defined in the same
1381 * approximate microseconds units. The principal source of timing
1382 * error here is from the simple truncation.
1384 * Note that local_clock() is only defined wrt to the current CPU;
1385 * the comparisons are no longer valid if we switch CPUs. Instead of
1386 * blocking preemption for the entire busywait, we can detect the CPU
1387 * switch and use that as indicator of system load and a reason to
1388 * stop busywaiting, see busywait_stop().
1391 t = local_clock() >> 10;
1397 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1399 unsigned int this_cpu;
1401 if (time_after(local_clock_us(&this_cpu), timeout))
1404 return this_cpu != cpu;
1407 static bool __i915_spin_request(const struct i915_request * const rq,
1408 int state, unsigned long timeout_us)
1413 * Only wait for the request if we know it is likely to complete.
1415 * We don't track the timestamps around requests, nor the average
1416 * request length, so we do not have a good indicator that this
1417 * request will complete within the timeout. What we do know is the
1418 * order in which requests are executed by the context and so we can
1419 * tell if the request has been started. If the request is not even
1420 * running yet, it is a fair assumption that it will not complete
1421 * within our relatively short timeout.
1423 if (!i915_request_is_running(rq))
1427 * When waiting for high frequency requests, e.g. during synchronous
1428 * rendering split between the CPU and GPU, the finite amount of time
1429 * required to set up the irq and wait upon it limits the response
1430 * rate. By busywaiting on the request completion for a short while we
1431 * can service the high frequency waits as quick as possible. However,
1432 * if it is a slow request, we want to sleep as quickly as possible.
1433 * The tradeoff between waiting and sleeping is roughly the time it
1434 * takes to sleep on a request, on the order of a microsecond.
1437 timeout_us += local_clock_us(&cpu);
1439 if (i915_request_completed(rq))
1442 if (signal_pending_state(state, current))
1445 if (busywait_stop(timeout_us, cpu))
1449 } while (!need_resched());
1454 struct request_wait {
1455 struct dma_fence_cb cb;
1456 struct task_struct *tsk;
1459 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1461 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1463 wake_up_process(wait->tsk);
1467 * i915_request_wait - wait until execution of request has finished
1468 * @rq: the request to wait upon
1469 * @flags: how to wait
1470 * @timeout: how long to wait in jiffies
1472 * i915_request_wait() waits for the request to be completed, for a
1473 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1476 * Returns the remaining time (in jiffies) if the request completed, which may
1477 * be zero or -ETIME if the request is unfinished after the timeout expires.
1478 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1479 * pending before the request completes.
1481 long i915_request_wait(struct i915_request *rq,
1485 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1486 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1487 struct request_wait wait;
1490 GEM_BUG_ON(timeout < 0);
1492 if (dma_fence_is_signaled(&rq->fence))
1498 trace_i915_request_wait_begin(rq, flags);
1501 * We must never wait on the GPU while holding a lock as we
1502 * may need to perform a GPU reset. So while we don't need to
1503 * serialise wait/reset with an explicit lock, we do want
1504 * lockdep to detect potential dependency cycles.
1506 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1509 * Optimistic spin before touching IRQs.
1511 * We may use a rather large value here to offset the penalty of
1512 * switching away from the active task. Frequently, the client will
1513 * wait upon an old swapbuffer to throttle itself to remain within a
1514 * frame of the gpu. If the client is running in lockstep with the gpu,
1515 * then it should not be waiting long at all, and a sleep now will incur
1516 * extra scheduler latency in producing the next frame. To try to
1517 * avoid adding the cost of enabling/disabling the interrupt to the
1518 * short wait, we first spin to see if the request would have completed
1519 * in the time taken to setup the interrupt.
1521 * We need upto 5us to enable the irq, and upto 20us to hide the
1522 * scheduler latency of a context switch, ignoring the secondary
1523 * impacts from a context switch such as cache eviction.
1525 * The scheme used for low-latency IO is called "hybrid interrupt
1526 * polling". The suggestion there is to sleep until just before you
1527 * expect to be woken by the device interrupt and then poll for its
1528 * completion. That requires having a good predictor for the request
1529 * duration, which we currently lack.
1531 if (IS_ACTIVE(CONFIG_DRM_I915_SPIN_REQUEST) &&
1532 __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
1533 dma_fence_signal(&rq->fence);
1538 * This client is about to stall waiting for the GPU. In many cases
1539 * this is undesirable and limits the throughput of the system, as
1540 * many clients cannot continue processing user input/output whilst
1541 * blocked. RPS autotuning may take tens of milliseconds to respond
1542 * to the GPU load and thus incurs additional latency for the client.
1543 * We can circumvent that by promoting the GPU frequency to maximum
1544 * before we sleep. This makes the GPU throttle up much more quickly
1545 * (good for benchmarks and user experience, e.g. window animations),
1546 * but at a cost of spending more power processing the workload
1547 * (bad for battery).
1549 if (flags & I915_WAIT_PRIORITY) {
1550 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1551 intel_rps_boost(rq);
1552 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1556 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1560 set_current_state(state);
1562 if (i915_request_completed(rq)) {
1563 dma_fence_signal(&rq->fence);
1567 if (signal_pending_state(state, current)) {
1568 timeout = -ERESTARTSYS;
1577 intel_engine_flush_submission(rq->engine);
1578 timeout = io_schedule_timeout(timeout);
1580 __set_current_state(TASK_RUNNING);
1582 dma_fence_remove_callback(&rq->fence, &wait.cb);
1585 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1586 trace_i915_request_wait_end(rq);
1590 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1591 #include "selftests/mock_request.c"
1592 #include "selftests/i915_request.c"
1595 static void i915_global_request_shrink(void)
1597 kmem_cache_shrink(global.slab_dependencies);
1598 kmem_cache_shrink(global.slab_execute_cbs);
1599 kmem_cache_shrink(global.slab_requests);
1602 static void i915_global_request_exit(void)
1604 kmem_cache_destroy(global.slab_dependencies);
1605 kmem_cache_destroy(global.slab_execute_cbs);
1606 kmem_cache_destroy(global.slab_requests);
1609 static struct i915_global_request global = { {
1610 .shrink = i915_global_request_shrink,
1611 .exit = i915_global_request_exit,
1614 int __init i915_global_request_init(void)
1616 global.slab_requests =
1617 kmem_cache_create("i915_request",
1618 sizeof(struct i915_request),
1619 __alignof__(struct i915_request),
1620 SLAB_HWCACHE_ALIGN |
1621 SLAB_RECLAIM_ACCOUNT |
1622 SLAB_TYPESAFE_BY_RCU,
1623 __i915_request_ctor);
1624 if (!global.slab_requests)
1627 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1628 SLAB_HWCACHE_ALIGN |
1629 SLAB_RECLAIM_ACCOUNT |
1630 SLAB_TYPESAFE_BY_RCU);
1631 if (!global.slab_execute_cbs)
1634 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1635 SLAB_HWCACHE_ALIGN |
1636 SLAB_RECLAIM_ACCOUNT);
1637 if (!global.slab_dependencies)
1638 goto err_execute_cbs;
1640 i915_global_register(&global.base);
1644 kmem_cache_destroy(global.slab_execute_cbs);
1646 kmem_cache_destroy(global.slab_requests);