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25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
33 #include "gem/i915_gem_context.h"
34 #include "gt/intel_breadcrumbs.h"
35 #include "gt/intel_context.h"
36 #include "gt/intel_gpu_commands.h"
37 #include "gt/intel_ring.h"
38 #include "gt/intel_rps.h"
40 #include "i915_active.h"
42 #include "i915_globals.h"
43 #include "i915_trace.h"
48 struct i915_sw_fence *fence;
49 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
50 struct i915_request *signal;
53 static struct i915_global_request {
54 struct i915_global base;
55 struct kmem_cache *slab_requests;
56 struct kmem_cache *slab_execute_cbs;
59 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
61 return dev_name(to_request(fence)->engine->i915->drm.dev);
64 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
66 const struct i915_gem_context *ctx;
69 * The timeline struct (as part of the ppgtt underneath a context)
70 * may be freed when the request is no longer in use by the GPU.
71 * We could extend the life of a context to beyond that of all
72 * fences, possibly keeping the hw resource around indefinitely,
73 * or we just give them a false name. Since
74 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
75 * lie seems justifiable.
77 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
80 ctx = i915_request_gem_context(to_request(fence));
82 return "[" DRIVER_NAME "]";
87 static bool i915_fence_signaled(struct dma_fence *fence)
89 return i915_request_completed(to_request(fence));
92 static bool i915_fence_enable_signaling(struct dma_fence *fence)
94 return i915_request_enable_breadcrumb(to_request(fence));
97 static signed long i915_fence_wait(struct dma_fence *fence,
101 return i915_request_wait(to_request(fence),
102 interruptible | I915_WAIT_PRIORITY,
106 struct kmem_cache *i915_request_slab_cache(void)
108 return global.slab_requests;
111 static void i915_fence_release(struct dma_fence *fence)
113 struct i915_request *rq = to_request(fence);
116 * The request is put onto a RCU freelist (i.e. the address
117 * is immediately reused), mark the fences as being freed now.
118 * Otherwise the debugobjects for the fences are only marked as
119 * freed when the slab cache itself is freed, and so we would get
120 * caught trying to reuse dead objects.
122 i915_sw_fence_fini(&rq->submit);
123 i915_sw_fence_fini(&rq->semaphore);
126 * Keep one request on each engine for reserved use under mempressure
128 * We do not hold a reference to the engine here and so have to be
129 * very careful in what rq->engine we poke. The virtual engine is
130 * referenced via the rq->context and we released that ref during
131 * i915_request_retire(), ergo we must not dereference a virtual
132 * engine here. Not that we would want to, as the only consumer of
133 * the reserved engine->request_pool is the power management parking,
134 * which must-not-fail, and that is only run on the physical engines.
136 * Since the request must have been executed to be have completed,
137 * we know that it will have been processed by the HW and will
138 * not be unsubmitted again, so rq->engine and rq->execution_mask
139 * at this point is stable. rq->execution_mask will be a single
140 * bit if the last and _only_ engine it could execution on was a
141 * physical engine, if it's multiple bits then it started on and
142 * could still be on a virtual engine. Thus if the mask is not a
143 * power-of-two we assume that rq->engine may still be a virtual
144 * engine and so a dangling invalid pointer that we cannot dereference
146 * For example, consider the flow of a bonded request through a virtual
147 * engine. The request is created with a wide engine mask (all engines
148 * that we might execute on). On processing the bond, the request mask
149 * is reduced to one or more engines. If the request is subsequently
150 * bound to a single engine, it will then be constrained to only
151 * execute on that engine and never returned to the virtual engine
152 * after timeslicing away, see __unwind_incomplete_requests(). Thus we
153 * know that if the rq->execution_mask is a single bit, rq->engine
154 * can be a physical engine with the exact corresponding mask.
156 if (is_power_of_2(rq->execution_mask) &&
157 !cmpxchg(&rq->engine->request_pool, NULL, rq))
160 kmem_cache_free(global.slab_requests, rq);
163 const struct dma_fence_ops i915_fence_ops = {
164 .get_driver_name = i915_fence_get_driver_name,
165 .get_timeline_name = i915_fence_get_timeline_name,
166 .enable_signaling = i915_fence_enable_signaling,
167 .signaled = i915_fence_signaled,
168 .wait = i915_fence_wait,
169 .release = i915_fence_release,
172 static void irq_execute_cb(struct irq_work *wrk)
174 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
176 i915_sw_fence_complete(cb->fence);
177 kmem_cache_free(global.slab_execute_cbs, cb);
180 static void irq_execute_cb_hook(struct irq_work *wrk)
182 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
184 cb->hook(container_of(cb->fence, struct i915_request, submit),
186 i915_request_put(cb->signal);
191 static __always_inline void
192 __notify_execute_cb(struct i915_request *rq, bool (*fn)(struct irq_work *wrk))
194 struct execute_cb *cb, *cn;
196 if (llist_empty(&rq->execute_cb))
199 llist_for_each_entry_safe(cb, cn,
200 llist_del_all(&rq->execute_cb),
205 static void __notify_execute_cb_irq(struct i915_request *rq)
207 __notify_execute_cb(rq, irq_work_queue);
210 static bool irq_work_imm(struct irq_work *wrk)
216 static void __notify_execute_cb_imm(struct i915_request *rq)
218 __notify_execute_cb(rq, irq_work_imm);
221 static void free_capture_list(struct i915_request *request)
223 struct i915_capture_list *capture;
225 capture = fetch_and_zero(&request->capture_list);
227 struct i915_capture_list *next = capture->next;
234 static void __i915_request_fill(struct i915_request *rq, u8 val)
236 void *vaddr = rq->ring->vaddr;
240 if (rq->postfix < head) {
241 memset(vaddr + head, val, rq->ring->size - head);
244 memset(vaddr + head, val, rq->postfix - head);
247 static void remove_from_engine(struct i915_request *rq)
249 struct intel_engine_cs *engine, *locked;
252 * Virtual engines complicate acquiring the engine timeline lock,
253 * as their rq->engine pointer is not stable until under that
254 * engine lock. The simple ploy we use is to take the lock then
255 * check that the rq still belongs to the newly locked engine.
257 locked = READ_ONCE(rq->engine);
258 spin_lock_irq(&locked->active.lock);
259 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
260 spin_unlock(&locked->active.lock);
261 spin_lock(&engine->active.lock);
264 list_del_init(&rq->sched.link);
266 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
267 clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
269 /* Prevent further __await_execution() registering a cb, then flush */
270 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
272 spin_unlock_irq(&locked->active.lock);
274 __notify_execute_cb_imm(rq);
277 bool i915_request_retire(struct i915_request *rq)
279 if (!i915_request_completed(rq))
284 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
285 trace_i915_request_retire(rq);
286 i915_request_mark_complete(rq);
289 * We know the GPU must have read the request to have
290 * sent us the seqno + interrupt, so use the position
291 * of tail of the request to update the last known position
294 * Note this requires that we are always called in request
297 GEM_BUG_ON(!list_is_first(&rq->link,
298 &i915_request_timeline(rq)->requests));
299 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
300 /* Poison before we release our space in the ring */
301 __i915_request_fill(rq, POISON_FREE);
302 rq->ring->head = rq->postfix;
304 if (!i915_request_signaled(rq)) {
305 spin_lock_irq(&rq->lock);
306 dma_fence_signal_locked(&rq->fence);
307 spin_unlock_irq(&rq->lock);
310 if (i915_request_has_waitboost(rq)) {
311 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
312 atomic_dec(&rq->engine->gt->rps.num_waiters);
316 * We only loosely track inflight requests across preemption,
317 * and so we may find ourselves attempting to retire a _completed_
318 * request that we have removed from the HW and put back on a run
321 * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
322 * after removing the breadcrumb and signaling it, so that we do not
323 * inadvertently attach the breadcrumb to a completed request.
325 if (!list_empty(&rq->sched.link))
326 remove_from_engine(rq);
327 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
329 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
331 intel_context_exit(rq->context);
332 intel_context_unpin(rq->context);
334 free_capture_list(rq);
335 i915_sched_node_fini(&rq->sched);
336 i915_request_put(rq);
341 void i915_request_retire_upto(struct i915_request *rq)
343 struct intel_timeline * const tl = i915_request_timeline(rq);
344 struct i915_request *tmp;
348 GEM_BUG_ON(!i915_request_completed(rq));
351 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
352 } while (i915_request_retire(tmp) && tmp != rq);
355 static struct i915_request * const *
356 __engine_active(struct intel_engine_cs *engine)
358 return READ_ONCE(engine->execlists.active);
361 static bool __request_in_flight(const struct i915_request *signal)
363 struct i915_request * const *port, *rq;
364 bool inflight = false;
366 if (!i915_request_is_ready(signal))
370 * Even if we have unwound the request, it may still be on
371 * the GPU (preempt-to-busy). If that request is inside an
372 * unpreemptible critical section, it will not be removed. Some
373 * GPU functions may even be stuck waiting for the paired request
374 * (__await_execution) to be submitted and cannot be preempted
375 * until the bond is executing.
377 * As we know that there are always preemption points between
378 * requests, we know that only the currently executing request
379 * may be still active even though we have cleared the flag.
380 * However, we can't rely on our tracking of ELSP[0] to know
381 * which request is currently active and so maybe stuck, as
382 * the tracking maybe an event behind. Instead assume that
383 * if the context is still inflight, then it is still active
384 * even if the active flag has been cleared.
386 * To further complicate matters, if there a pending promotion, the HW
387 * may either perform a context switch to the second inflight execlists,
388 * or it may switch to the pending set of execlists. In the case of the
389 * latter, it may send the ACK and we process the event copying the
390 * pending[] over top of inflight[], _overwriting_ our *active. Since
391 * this implies the HW is arbitrating and not struck in *active, we do
392 * not worry about complete accuracy, but we do require no read/write
393 * tearing of the pointer [the read of the pointer must be valid, even
394 * as the array is being overwritten, for which we require the writes
397 * Note that the read of *execlists->active may race with the promotion
398 * of execlists->pending[] to execlists->inflight[], overwritting
399 * the value at *execlists->active. This is fine. The promotion implies
400 * that we received an ACK from the HW, and so the context is not
401 * stuck -- if we do not see ourselves in *active, the inflight status
402 * is valid. If instead we see ourselves being copied into *active,
403 * we are inflight and may signal the callback.
405 if (!intel_context_inflight(signal->context))
409 for (port = __engine_active(signal->engine);
410 (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
412 if (rq->context == signal->context) {
413 inflight = i915_seqno_passed(rq->fence.seqno,
414 signal->fence.seqno);
424 __await_execution(struct i915_request *rq,
425 struct i915_request *signal,
426 void (*hook)(struct i915_request *rq,
427 struct dma_fence *signal),
430 struct execute_cb *cb;
432 if (i915_request_is_active(signal)) {
434 hook(rq, &signal->fence);
438 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
442 cb->fence = &rq->submit;
443 i915_sw_fence_await(cb->fence);
444 init_irq_work(&cb->work, irq_execute_cb);
448 cb->signal = i915_request_get(signal);
449 cb->work.func = irq_execute_cb_hook;
453 * Register the callback first, then see if the signaler is already
454 * active. This ensures that if we race with the
455 * __notify_execute_cb from i915_request_submit() and we are not
456 * included in that list, we get a second bite of the cherry and
457 * execute it ourselves. After this point, a future
458 * i915_request_submit() will notify us.
460 * In i915_request_retire() we set the ACTIVE bit on a completed
461 * request (then flush the execute_cb). So by registering the
462 * callback first, then checking the ACTIVE bit, we serialise with
463 * the completed/retired request.
465 if (llist_add(&cb->work.llnode, &signal->execute_cb)) {
466 if (i915_request_is_active(signal) ||
467 __request_in_flight(signal))
468 __notify_execute_cb_imm(signal);
474 static bool fatal_error(int error)
477 case 0: /* not an error! */
478 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
479 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
486 void __i915_request_skip(struct i915_request *rq)
488 GEM_BUG_ON(!fatal_error(rq->fence.error));
490 if (rq->infix == rq->postfix)
494 * As this request likely depends on state from the lost
495 * context, clear out all the user operations leaving the
496 * breadcrumb at the end (so we get the fence notifications).
498 __i915_request_fill(rq, 0);
499 rq->infix = rq->postfix;
502 void i915_request_set_error_once(struct i915_request *rq, int error)
506 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
508 if (i915_request_signaled(rq))
511 old = READ_ONCE(rq->fence.error);
513 if (fatal_error(old))
515 } while (!try_cmpxchg(&rq->fence.error, &old, error));
518 bool __i915_request_submit(struct i915_request *request)
520 struct intel_engine_cs *engine = request->engine;
523 RQ_TRACE(request, "\n");
525 GEM_BUG_ON(!irqs_disabled());
526 lockdep_assert_held(&engine->active.lock);
529 * With the advent of preempt-to-busy, we frequently encounter
530 * requests that we have unsubmitted from HW, but left running
531 * until the next ack and so have completed in the meantime. On
532 * resubmission of that completed request, we can skip
533 * updating the payload, and execlists can even skip submitting
536 * We must remove the request from the caller's priority queue,
537 * and the caller must only call us when the request is in their
538 * priority queue, under the active.lock. This ensures that the
539 * request has *not* yet been retired and we can safely move
540 * the request into the engine->active.list where it will be
541 * dropped upon retiring. (Otherwise if resubmit a *retired*
542 * request, this would be a horrible use-after-free.)
544 if (i915_request_completed(request))
547 if (unlikely(intel_context_is_closed(request->context) &&
548 !intel_engine_has_heartbeat(engine)))
549 intel_context_set_banned(request->context);
551 if (unlikely(intel_context_is_banned(request->context)))
552 i915_request_set_error_once(request, -EIO);
554 if (unlikely(fatal_error(request->fence.error)))
555 __i915_request_skip(request);
558 * Are we using semaphores when the gpu is already saturated?
560 * Using semaphores incurs a cost in having the GPU poll a
561 * memory location, busywaiting for it to change. The continual
562 * memory reads can have a noticeable impact on the rest of the
563 * system with the extra bus traffic, stalling the cpu as it too
564 * tries to access memory across the bus (perf stat -e bus-cycles).
566 * If we installed a semaphore on this request and we only submit
567 * the request after the signaler completed, that indicates the
568 * system is overloaded and using semaphores at this time only
569 * increases the amount of work we are doing. If so, we disable
570 * further use of semaphores until we are idle again, whence we
571 * optimistically try again.
573 if (request->sched.semaphores &&
574 i915_sw_fence_signaled(&request->semaphore))
575 engine->saturated |= request->sched.semaphores;
577 engine->emit_fini_breadcrumb(request,
578 request->ring->vaddr + request->postfix);
580 trace_i915_request_execute(request);
585 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
586 list_move_tail(&request->sched.link, &engine->active.requests);
587 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
591 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
593 * In the future, perhaps when we have an active time-slicing scheduler,
594 * it will be interesting to unsubmit parallel execution and remove
595 * busywaits from the GPU until their master is restarted. This is
596 * quite hairy, we have to carefully rollback the fence and do a
597 * preempt-to-idle cycle on the target engine, all the while the
598 * master execute_cb may refire.
600 __notify_execute_cb_irq(request);
602 /* We may be recursing from the signal callback of another i915 fence */
603 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
604 i915_request_enable_breadcrumb(request);
609 void i915_request_submit(struct i915_request *request)
611 struct intel_engine_cs *engine = request->engine;
614 /* Will be called from irq-context when using foreign fences. */
615 spin_lock_irqsave(&engine->active.lock, flags);
617 __i915_request_submit(request);
619 spin_unlock_irqrestore(&engine->active.lock, flags);
622 void __i915_request_unsubmit(struct i915_request *request)
624 struct intel_engine_cs *engine = request->engine;
627 * Only unwind in reverse order, required so that the per-context list
628 * is kept in seqno/ring order.
630 RQ_TRACE(request, "\n");
632 GEM_BUG_ON(!irqs_disabled());
633 lockdep_assert_held(&engine->active.lock);
636 * Before we remove this breadcrumb from the signal list, we have
637 * to ensure that a concurrent dma_fence_enable_signaling() does not
638 * attach itself. We first mark the request as no longer active and
639 * make sure that is visible to other cores, and then remove the
640 * breadcrumb if attached.
642 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
643 clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
644 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
645 i915_request_cancel_breadcrumb(request);
647 /* We've already spun, don't charge on resubmitting. */
648 if (request->sched.semaphores && i915_request_started(request))
649 request->sched.semaphores = 0;
652 * We don't need to wake_up any waiters on request->execute, they
653 * will get woken by any other event or us re-adding this request
654 * to the engine timeline (__i915_request_submit()). The waiters
655 * should be quite adapt at finding that the request now has a new
656 * global_seqno to the one they went to sleep on.
660 void i915_request_unsubmit(struct i915_request *request)
662 struct intel_engine_cs *engine = request->engine;
665 /* Will be called from irq-context when using foreign fences. */
666 spin_lock_irqsave(&engine->active.lock, flags);
668 __i915_request_unsubmit(request);
670 spin_unlock_irqrestore(&engine->active.lock, flags);
673 static int __i915_sw_fence_call
674 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
676 struct i915_request *request =
677 container_of(fence, typeof(*request), submit);
681 trace_i915_request_submit(request);
683 if (unlikely(fence->error))
684 i915_request_set_error_once(request, fence->error);
687 * We need to serialize use of the submit_request() callback
688 * with its hotplugging performed during an emergency
689 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
690 * critical section in order to force i915_gem_set_wedged() to
691 * wait until the submit_request() is completed before
695 request->engine->submit_request(request);
700 i915_request_put(request);
707 static int __i915_sw_fence_call
708 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
710 struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
717 i915_request_put(rq);
724 static void retire_requests(struct intel_timeline *tl)
726 struct i915_request *rq, *rn;
728 list_for_each_entry_safe(rq, rn, &tl->requests, link)
729 if (!i915_request_retire(rq))
733 static noinline struct i915_request *
734 request_alloc_slow(struct intel_timeline *tl,
735 struct i915_request **rsvd,
738 struct i915_request *rq;
740 /* If we cannot wait, dip into our reserves */
741 if (!gfpflags_allow_blocking(gfp)) {
742 rq = xchg(rsvd, NULL);
743 if (!rq) /* Use the normal failure path for one final WARN */
749 if (list_empty(&tl->requests))
752 /* Move our oldest request to the slab-cache (if not in use!) */
753 rq = list_first_entry(&tl->requests, typeof(*rq), link);
754 i915_request_retire(rq);
756 rq = kmem_cache_alloc(global.slab_requests,
757 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
761 /* Ratelimit ourselves to prevent oom from malicious clients */
762 rq = list_last_entry(&tl->requests, typeof(*rq), link);
763 cond_synchronize_rcu(rq->rcustate);
765 /* Retire our old requests in the hope that we free some */
769 return kmem_cache_alloc(global.slab_requests, gfp);
772 static void __i915_request_ctor(void *arg)
774 struct i915_request *rq = arg;
776 spin_lock_init(&rq->lock);
777 i915_sched_node_init(&rq->sched);
778 i915_sw_fence_init(&rq->submit, submit_notify);
779 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
781 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
783 rq->capture_list = NULL;
785 init_llist_head(&rq->execute_cb);
788 struct i915_request *
789 __i915_request_create(struct intel_context *ce, gfp_t gfp)
791 struct intel_timeline *tl = ce->timeline;
792 struct i915_request *rq;
796 might_sleep_if(gfpflags_allow_blocking(gfp));
798 /* Check that the caller provided an already pinned context */
799 __intel_context_pin(ce);
802 * Beware: Dragons be flying overhead.
804 * We use RCU to look up requests in flight. The lookups may
805 * race with the request being allocated from the slab freelist.
806 * That is the request we are writing to here, may be in the process
807 * of being read by __i915_active_request_get_rcu(). As such,
808 * we have to be very careful when overwriting the contents. During
809 * the RCU lookup, we change chase the request->engine pointer,
810 * read the request->global_seqno and increment the reference count.
812 * The reference count is incremented atomically. If it is zero,
813 * the lookup knows the request is unallocated and complete. Otherwise,
814 * it is either still in use, or has been reallocated and reset
815 * with dma_fence_init(). This increment is safe for release as we
816 * check that the request we have a reference to and matches the active
819 * Before we increment the refcount, we chase the request->engine
820 * pointer. We must not call kmem_cache_zalloc() or else we set
821 * that pointer to NULL and cause a crash during the lookup. If
822 * we see the request is completed (based on the value of the
823 * old engine and seqno), the lookup is complete and reports NULL.
824 * If we decide the request is not completed (new engine or seqno),
825 * then we grab a reference and double check that it is still the
826 * active request - which it won't be and restart the lookup.
828 * Do not use kmem_cache_zalloc() here!
830 rq = kmem_cache_alloc(global.slab_requests,
831 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
833 rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
841 rq->engine = ce->engine;
843 rq->execution_mask = ce->engine->mask;
845 kref_init(&rq->fence.refcount);
848 INIT_LIST_HEAD(&rq->fence.cb_list);
850 ret = intel_timeline_get_seqno(tl, rq, &seqno);
854 rq->fence.context = tl->fence_context;
855 rq->fence.seqno = seqno;
857 RCU_INIT_POINTER(rq->timeline, tl);
858 RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
859 rq->hwsp_seqno = tl->hwsp_seqno;
860 GEM_BUG_ON(i915_request_completed(rq));
862 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
864 /* We bump the ref for the fence chain */
865 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
866 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
868 i915_sched_node_reinit(&rq->sched);
870 /* No zalloc, everything must be cleared after use */
872 GEM_BUG_ON(rq->capture_list);
873 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
876 * Reserve space in the ring buffer for all the commands required to
877 * eventually emit this request. This is to guarantee that the
878 * i915_request_add() call can't fail. Note that the reserve may need
879 * to be redone if the request is not actually submitted straight
880 * away, e.g. because a GPU scheduler has deferred it.
882 * Note that due to how we add reserved_space to intel_ring_begin()
883 * we need to double our request to ensure that if we need to wrap
884 * around inside i915_request_add() there is sufficient space at
885 * the beginning of the ring as well.
888 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
891 * Record the position of the start of the request so that
892 * should we detect the updated seqno part-way through the
893 * GPU processing the request, we never over-estimate the
894 * position of the head.
896 rq->head = rq->ring->emit;
898 ret = rq->engine->request_alloc(rq);
902 rq->infix = rq->ring->emit; /* end of header; start of user payload */
904 intel_context_mark_active(ce);
905 list_add_tail_rcu(&rq->link, &tl->requests);
910 ce->ring->emit = rq->head;
912 /* Make sure we didn't add ourselves to external state before freeing */
913 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
914 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
917 kmem_cache_free(global.slab_requests, rq);
919 intel_context_unpin(ce);
923 struct i915_request *
924 i915_request_create(struct intel_context *ce)
926 struct i915_request *rq;
927 struct intel_timeline *tl;
929 tl = intel_context_timeline_lock(ce);
933 /* Move our oldest request to the slab-cache (if not in use!) */
934 rq = list_first_entry(&tl->requests, typeof(*rq), link);
935 if (!list_is_last(&rq->link, &tl->requests))
936 i915_request_retire(rq);
938 intel_context_enter(ce);
939 rq = __i915_request_create(ce, GFP_KERNEL);
940 intel_context_exit(ce); /* active reference transferred to request */
944 /* Check that we do not interrupt ourselves with a new request */
945 rq->cookie = lockdep_pin_lock(&tl->mutex);
950 intel_context_timeline_unlock(tl);
955 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
957 struct dma_fence *fence;
960 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
963 if (i915_request_started(signal))
968 spin_lock_irq(&signal->lock);
970 struct list_head *pos = READ_ONCE(signal->link.prev);
971 struct i915_request *prev;
973 /* Confirm signal has not been retired, the link is valid */
974 if (unlikely(i915_request_started(signal)))
977 /* Is signal the earliest request on its timeline? */
978 if (pos == &rcu_dereference(signal->timeline)->requests)
982 * Peek at the request before us in the timeline. That
983 * request will only be valid before it is retired, so
984 * after acquiring a reference to it, confirm that it is
985 * still part of the signaler's timeline.
987 prev = list_entry(pos, typeof(*prev), link);
988 if (!i915_request_get_rcu(prev))
991 /* After the strong barrier, confirm prev is still attached */
992 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
993 i915_request_put(prev);
997 fence = &prev->fence;
999 spin_unlock_irq(&signal->lock);
1005 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
1006 err = i915_sw_fence_await_dma_fence(&rq->submit,
1009 dma_fence_put(fence);
1014 static intel_engine_mask_t
1015 already_busywaiting(struct i915_request *rq)
1018 * Polling a semaphore causes bus traffic, delaying other users of
1019 * both the GPU and CPU. We want to limit the impact on others,
1020 * while taking advantage of early submission to reduce GPU
1021 * latency. Therefore we restrict ourselves to not using more
1022 * than one semaphore from each source, and not using a semaphore
1023 * if we have detected the engine is saturated (i.e. would not be
1024 * submitted early and cause bus traffic reading an already passed
1027 * See the are-we-too-late? check in __i915_request_submit().
1029 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1033 __emit_semaphore_wait(struct i915_request *to,
1034 struct i915_request *from,
1037 const int has_token = INTEL_GEN(to->engine->i915) >= 12;
1042 GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8);
1043 GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1045 /* We need to pin the signaler's HWSP until we are finished reading. */
1046 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1054 cs = intel_ring_begin(to, len);
1059 * Using greater-than-or-equal here means we have to worry
1060 * about seqno wraparound. To side step that issue, we swap
1061 * the timeline HWSP upon wrapping, so that everyone listening
1062 * for the old (pre-wrap) values do not see the much smaller
1063 * (post-wrap) values than they were expecting (and so wait
1066 *cs++ = (MI_SEMAPHORE_WAIT |
1067 MI_SEMAPHORE_GLOBAL_GTT |
1069 MI_SEMAPHORE_SAD_GTE_SDD) +
1072 *cs++ = hwsp_offset;
1079 intel_ring_advance(to, cs);
1084 emit_semaphore_wait(struct i915_request *to,
1085 struct i915_request *from,
1088 const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1089 struct i915_sw_fence *wait = &to->submit;
1091 if (!intel_context_use_semaphores(to->context))
1094 if (i915_request_has_initial_breadcrumb(to))
1097 if (!rcu_access_pointer(from->hwsp_cacheline))
1101 * If this or its dependents are waiting on an external fence
1102 * that may fail catastrophically, then we want to avoid using
1103 * sempahores as they bypass the fence signaling metadata, and we
1104 * lose the fence->error propagation.
1106 if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1109 /* Just emit the first semaphore we see as request space is limited. */
1110 if (already_busywaiting(to) & mask)
1113 if (i915_request_await_start(to, from) < 0)
1116 /* Only submit our spinner after the signaler is running! */
1117 if (__await_execution(to, from, NULL, gfp))
1120 if (__emit_semaphore_wait(to, from, from->fence.seqno))
1123 to->sched.semaphores |= mask;
1124 wait = &to->semaphore;
1127 return i915_sw_fence_await_dma_fence(wait,
1132 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1133 struct dma_fence *fence)
1135 return __intel_timeline_sync_is_later(tl,
1140 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1141 const struct dma_fence *fence)
1143 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1147 __i915_request_await_execution(struct i915_request *to,
1148 struct i915_request *from,
1149 void (*hook)(struct i915_request *rq,
1150 struct dma_fence *signal))
1154 GEM_BUG_ON(intel_context_is_barrier(from->context));
1156 /* Submit both requests at the same time */
1157 err = __await_execution(to, from, hook, I915_FENCE_GFP);
1161 /* Squash repeated depenendices to the same timelines */
1162 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1167 * Wait until the start of this request.
1169 * The execution cb fires when we submit the request to HW. But in
1170 * many cases this may be long before the request itself is ready to
1171 * run (consider that we submit 2 requests for the same context, where
1172 * the request of interest is behind an indefinite spinner). So we hook
1173 * up to both to reduce our queues and keep the execution lag minimised
1174 * in the worst case, though we hope that the await_start is elided.
1176 err = i915_request_await_start(to, from);
1181 * Ensure both start together [after all semaphores in signal]
1183 * Now that we are queued to the HW at roughly the same time (thanks
1184 * to the execute cb) and are ready to run at roughly the same time
1185 * (thanks to the await start), our signaler may still be indefinitely
1186 * delayed by waiting on a semaphore from a remote engine. If our
1187 * signaler depends on a semaphore, so indirectly do we, and we do not
1188 * want to start our payload until our signaler also starts theirs.
1191 * However, there is also a second condition for which we need to wait
1192 * for the precise start of the signaler. Consider that the signaler
1193 * was submitted in a chain of requests following another context
1194 * (with just an ordinary intra-engine fence dependency between the
1195 * two). In this case the signaler is queued to HW, but not for
1196 * immediate execution, and so we must wait until it reaches the
1199 if (intel_engine_has_semaphores(to->engine) &&
1200 !i915_request_has_initial_breadcrumb(to)) {
1201 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1206 /* Couple the dependency tree for PI on this exposed to->fence */
1207 if (to->engine->schedule) {
1208 err = i915_sched_node_add_dependency(&to->sched,
1210 I915_DEPENDENCY_WEAK);
1215 return intel_timeline_sync_set_start(i915_request_timeline(to),
1219 static void mark_external(struct i915_request *rq)
1222 * The downside of using semaphores is that we lose metadata passing
1223 * along the signaling chain. This is particularly nasty when we
1224 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1225 * fatal errors we want to scrub the request before it is executed,
1226 * which means that we cannot preload the request onto HW and have
1227 * it wait upon a semaphore.
1229 rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1233 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1236 return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1237 i915_fence_context_timeout(rq->engine->i915,
1243 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1245 struct dma_fence *iter;
1248 if (!to_dma_fence_chain(fence))
1249 return __i915_request_await_external(rq, fence);
1251 dma_fence_chain_for_each(iter, fence) {
1252 struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1254 if (!dma_fence_is_i915(chain->fence)) {
1255 err = __i915_request_await_external(rq, iter);
1259 err = i915_request_await_dma_fence(rq, chain->fence);
1264 dma_fence_put(iter);
1269 i915_request_await_execution(struct i915_request *rq,
1270 struct dma_fence *fence,
1271 void (*hook)(struct i915_request *rq,
1272 struct dma_fence *signal))
1274 struct dma_fence **child = &fence;
1275 unsigned int nchild = 1;
1278 if (dma_fence_is_array(fence)) {
1279 struct dma_fence_array *array = to_dma_fence_array(fence);
1281 /* XXX Error for signal-on-any fence arrays */
1283 child = array->fences;
1284 nchild = array->num_fences;
1285 GEM_BUG_ON(!nchild);
1290 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1291 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1295 if (fence->context == rq->fence.context)
1299 * We don't squash repeated fence dependencies here as we
1300 * want to run our callback in all cases.
1303 if (dma_fence_is_i915(fence))
1304 ret = __i915_request_await_execution(rq,
1308 ret = i915_request_await_external(rq, fence);
1317 await_request_submit(struct i915_request *to, struct i915_request *from)
1320 * If we are waiting on a virtual engine, then it may be
1321 * constrained to execute on a single engine *prior* to submission.
1322 * When it is submitted, it will be first submitted to the virtual
1323 * engine and then passed to the physical engine. We cannot allow
1324 * the waiter to be submitted immediately to the physical engine
1325 * as it may then bypass the virtual request.
1327 if (to->engine == READ_ONCE(from->engine))
1328 return i915_sw_fence_await_sw_fence_gfp(&to->submit,
1332 return __i915_request_await_execution(to, from, NULL);
1336 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1340 GEM_BUG_ON(to == from);
1341 GEM_BUG_ON(to->timeline == from->timeline);
1343 if (i915_request_completed(from)) {
1344 i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1348 if (to->engine->schedule) {
1349 ret = i915_sched_node_add_dependency(&to->sched,
1351 I915_DEPENDENCY_EXTERNAL);
1356 if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
1357 ret = await_request_submit(to, from);
1359 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1367 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1369 struct dma_fence **child = &fence;
1370 unsigned int nchild = 1;
1374 * Note that if the fence-array was created in signal-on-any mode,
1375 * we should *not* decompose it into its individual fences. However,
1376 * we don't currently store which mode the fence-array is operating
1377 * in. Fortunately, the only user of signal-on-any is private to
1378 * amdgpu and we should not see any incoming fence-array from
1379 * sync-file being in signal-on-any mode.
1381 if (dma_fence_is_array(fence)) {
1382 struct dma_fence_array *array = to_dma_fence_array(fence);
1384 child = array->fences;
1385 nchild = array->num_fences;
1386 GEM_BUG_ON(!nchild);
1391 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1392 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1397 * Requests on the same timeline are explicitly ordered, along
1398 * with their dependencies, by i915_request_add() which ensures
1399 * that requests are submitted in-order through each ring.
1401 if (fence->context == rq->fence.context)
1404 /* Squash repeated waits to the same timelines */
1405 if (fence->context &&
1406 intel_timeline_sync_is_later(i915_request_timeline(rq),
1410 if (dma_fence_is_i915(fence))
1411 ret = i915_request_await_request(rq, to_request(fence));
1413 ret = i915_request_await_external(rq, fence);
1417 /* Record the latest fence used against each timeline */
1419 intel_timeline_sync_set(i915_request_timeline(rq),
1427 * i915_request_await_object - set this request to (async) wait upon a bo
1428 * @to: request we are wishing to use
1429 * @obj: object which may be in use on another ring.
1430 * @write: whether the wait is on behalf of a writer
1432 * This code is meant to abstract object synchronization with the GPU.
1433 * Conceptually we serialise writes between engines inside the GPU.
1434 * We only allow one engine to write into a buffer at any time, but
1435 * multiple readers. To ensure each has a coherent view of memory, we must:
1437 * - If there is an outstanding write request to the object, the new
1438 * request must wait for it to complete (either CPU or in hw, requests
1439 * on the same ring will be naturally ordered).
1441 * - If we are a write request (pending_write_domain is set), the new
1442 * request must wait for outstanding read requests to complete.
1444 * Returns 0 if successful, else propagates up the lower layer error.
1447 i915_request_await_object(struct i915_request *to,
1448 struct drm_i915_gem_object *obj,
1451 struct dma_fence *excl;
1455 struct dma_fence **shared;
1456 unsigned int count, i;
1458 ret = dma_resv_get_fences_rcu(obj->base.resv,
1459 &excl, &count, &shared);
1463 for (i = 0; i < count; i++) {
1464 ret = i915_request_await_dma_fence(to, shared[i]);
1468 dma_fence_put(shared[i]);
1471 for (; i < count; i++)
1472 dma_fence_put(shared[i]);
1475 excl = dma_resv_get_excl_rcu(obj->base.resv);
1480 ret = i915_request_await_dma_fence(to, excl);
1482 dma_fence_put(excl);
1488 static struct i915_request *
1489 __i915_request_add_to_timeline(struct i915_request *rq)
1491 struct intel_timeline *timeline = i915_request_timeline(rq);
1492 struct i915_request *prev;
1495 * Dependency tracking and request ordering along the timeline
1496 * is special cased so that we can eliminate redundant ordering
1497 * operations while building the request (we know that the timeline
1498 * itself is ordered, and here we guarantee it).
1500 * As we know we will need to emit tracking along the timeline,
1501 * we embed the hooks into our request struct -- at the cost of
1502 * having to have specialised no-allocation interfaces (which will
1503 * be beneficial elsewhere).
1505 * A second benefit to open-coding i915_request_await_request is
1506 * that we can apply a slight variant of the rules specialised
1507 * for timelines that jump between engines (such as virtual engines).
1508 * If we consider the case of virtual engine, we must emit a dma-fence
1509 * to prevent scheduling of the second request until the first is
1510 * complete (to maximise our greedy late load balancing) and this
1511 * precludes optimising to use semaphores serialisation of a single
1512 * timeline across engines.
1514 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1516 if (prev && !i915_request_completed(prev)) {
1518 * The requests are supposed to be kept in order. However,
1519 * we need to be wary in case the timeline->last_request
1520 * is used as a barrier for external modification to this
1523 GEM_BUG_ON(prev->context == rq->context &&
1524 i915_seqno_passed(prev->fence.seqno,
1527 if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask))
1528 i915_sw_fence_await_sw_fence(&rq->submit,
1532 __i915_sw_fence_await_dma_fence(&rq->submit,
1535 if (rq->engine->schedule)
1536 __i915_sched_node_add_dependency(&rq->sched,
1543 * Make sure that no request gazumped us - if it was allocated after
1544 * our i915_request_alloc() and called __i915_request_add() before
1545 * us, the timeline will hold its seqno which is later than ours.
1547 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1553 * NB: This function is not allowed to fail. Doing so would mean the the
1554 * request is not being tracked for completion but the work itself is
1555 * going to happen on the hardware. This would be a Bad Thing(tm).
1557 struct i915_request *__i915_request_commit(struct i915_request *rq)
1559 struct intel_engine_cs *engine = rq->engine;
1560 struct intel_ring *ring = rq->ring;
1566 * To ensure that this call will not fail, space for its emissions
1567 * should already have been reserved in the ring buffer. Let the ring
1568 * know that it is time to use that space up.
1570 GEM_BUG_ON(rq->reserved_space > ring->space);
1571 rq->reserved_space = 0;
1572 rq->emitted_jiffies = jiffies;
1575 * Record the position of the start of the breadcrumb so that
1576 * should we detect the updated seqno part-way through the
1577 * GPU processing the request, we never over-estimate the
1578 * position of the ring's HEAD.
1580 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1581 GEM_BUG_ON(IS_ERR(cs));
1582 rq->postfix = intel_ring_offset(rq, cs);
1584 return __i915_request_add_to_timeline(rq);
1587 void __i915_request_queue_bh(struct i915_request *rq)
1589 i915_sw_fence_commit(&rq->semaphore);
1590 i915_sw_fence_commit(&rq->submit);
1593 void __i915_request_queue(struct i915_request *rq,
1594 const struct i915_sched_attr *attr)
1597 * Let the backend know a new request has arrived that may need
1598 * to adjust the existing execution schedule due to a high priority
1599 * request - i.e. we may want to preempt the current request in order
1600 * to run a high priority dependency chain *before* we can execute this
1603 * This is called before the request is ready to run so that we can
1604 * decide whether to preempt the entire chain so that it is ready to
1605 * run at the earliest possible convenience.
1607 if (attr && rq->engine->schedule)
1608 rq->engine->schedule(rq, attr);
1611 __i915_request_queue_bh(rq);
1612 local_bh_enable(); /* kick tasklets */
1615 void i915_request_add(struct i915_request *rq)
1617 struct intel_timeline * const tl = i915_request_timeline(rq);
1618 struct i915_sched_attr attr = {};
1619 struct i915_gem_context *ctx;
1621 lockdep_assert_held(&tl->mutex);
1622 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1624 trace_i915_request_add(rq);
1625 __i915_request_commit(rq);
1627 /* XXX placeholder for selftests */
1629 ctx = rcu_dereference(rq->context->gem_context);
1634 __i915_request_queue(rq, &attr);
1636 mutex_unlock(&tl->mutex);
1639 static unsigned long local_clock_ns(unsigned int *cpu)
1644 * Cheaply and approximately convert from nanoseconds to microseconds.
1645 * The result and subsequent calculations are also defined in the same
1646 * approximate microseconds units. The principal source of timing
1647 * error here is from the simple truncation.
1649 * Note that local_clock() is only defined wrt to the current CPU;
1650 * the comparisons are no longer valid if we switch CPUs. Instead of
1651 * blocking preemption for the entire busywait, we can detect the CPU
1652 * switch and use that as indicator of system load and a reason to
1653 * stop busywaiting, see busywait_stop().
1662 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1664 unsigned int this_cpu;
1666 if (time_after(local_clock_ns(&this_cpu), timeout))
1669 return this_cpu != cpu;
1672 static bool __i915_spin_request(struct i915_request * const rq, int state)
1674 unsigned long timeout_ns;
1678 * Only wait for the request if we know it is likely to complete.
1680 * We don't track the timestamps around requests, nor the average
1681 * request length, so we do not have a good indicator that this
1682 * request will complete within the timeout. What we do know is the
1683 * order in which requests are executed by the context and so we can
1684 * tell if the request has been started. If the request is not even
1685 * running yet, it is a fair assumption that it will not complete
1686 * within our relatively short timeout.
1688 if (!i915_request_is_running(rq))
1692 * When waiting for high frequency requests, e.g. during synchronous
1693 * rendering split between the CPU and GPU, the finite amount of time
1694 * required to set up the irq and wait upon it limits the response
1695 * rate. By busywaiting on the request completion for a short while we
1696 * can service the high frequency waits as quick as possible. However,
1697 * if it is a slow request, we want to sleep as quickly as possible.
1698 * The tradeoff between waiting and sleeping is roughly the time it
1699 * takes to sleep on a request, on the order of a microsecond.
1702 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1703 timeout_ns += local_clock_ns(&cpu);
1705 if (dma_fence_is_signaled(&rq->fence))
1708 if (signal_pending_state(state, current))
1711 if (busywait_stop(timeout_ns, cpu))
1715 } while (!need_resched());
1720 struct request_wait {
1721 struct dma_fence_cb cb;
1722 struct task_struct *tsk;
1725 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1727 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1729 wake_up_process(fetch_and_zero(&wait->tsk));
1733 * i915_request_wait - wait until execution of request has finished
1734 * @rq: the request to wait upon
1735 * @flags: how to wait
1736 * @timeout: how long to wait in jiffies
1738 * i915_request_wait() waits for the request to be completed, for a
1739 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1742 * Returns the remaining time (in jiffies) if the request completed, which may
1743 * be zero or -ETIME if the request is unfinished after the timeout expires.
1744 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1745 * pending before the request completes.
1747 long i915_request_wait(struct i915_request *rq,
1751 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1752 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1753 struct request_wait wait;
1756 GEM_BUG_ON(timeout < 0);
1758 if (dma_fence_is_signaled(&rq->fence))
1764 trace_i915_request_wait_begin(rq, flags);
1767 * We must never wait on the GPU while holding a lock as we
1768 * may need to perform a GPU reset. So while we don't need to
1769 * serialise wait/reset with an explicit lock, we do want
1770 * lockdep to detect potential dependency cycles.
1772 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1775 * Optimistic spin before touching IRQs.
1777 * We may use a rather large value here to offset the penalty of
1778 * switching away from the active task. Frequently, the client will
1779 * wait upon an old swapbuffer to throttle itself to remain within a
1780 * frame of the gpu. If the client is running in lockstep with the gpu,
1781 * then it should not be waiting long at all, and a sleep now will incur
1782 * extra scheduler latency in producing the next frame. To try to
1783 * avoid adding the cost of enabling/disabling the interrupt to the
1784 * short wait, we first spin to see if the request would have completed
1785 * in the time taken to setup the interrupt.
1787 * We need upto 5us to enable the irq, and upto 20us to hide the
1788 * scheduler latency of a context switch, ignoring the secondary
1789 * impacts from a context switch such as cache eviction.
1791 * The scheme used for low-latency IO is called "hybrid interrupt
1792 * polling". The suggestion there is to sleep until just before you
1793 * expect to be woken by the device interrupt and then poll for its
1794 * completion. That requires having a good predictor for the request
1795 * duration, which we currently lack.
1797 if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) &&
1798 __i915_spin_request(rq, state))
1802 * This client is about to stall waiting for the GPU. In many cases
1803 * this is undesirable and limits the throughput of the system, as
1804 * many clients cannot continue processing user input/output whilst
1805 * blocked. RPS autotuning may take tens of milliseconds to respond
1806 * to the GPU load and thus incurs additional latency for the client.
1807 * We can circumvent that by promoting the GPU frequency to maximum
1808 * before we sleep. This makes the GPU throttle up much more quickly
1809 * (good for benchmarks and user experience, e.g. window animations),
1810 * but at a cost of spending more power processing the workload
1811 * (bad for battery).
1813 if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
1814 intel_rps_boost(rq);
1817 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1821 * Flush the submission tasklet, but only if it may help this request.
1823 * We sometimes experience some latency between the HW interrupts and
1824 * tasklet execution (mostly due to ksoftirqd latency, but it can also
1825 * be due to lazy CS events), so lets run the tasklet manually if there
1826 * is a chance it may submit this request. If the request is not ready
1827 * to run, as it is waiting for other fences to be signaled, flushing
1828 * the tasklet is busy work without any advantage for this client.
1830 * If the HW is being lazy, this is the last chance before we go to
1831 * sleep to catch any pending events. We will check periodically in
1832 * the heartbeat to flush the submission tasklets as a last resort
1835 if (i915_request_is_ready(rq))
1836 __intel_engine_flush_submission(rq->engine, false);
1839 set_current_state(state);
1841 if (dma_fence_is_signaled(&rq->fence))
1844 if (signal_pending_state(state, current)) {
1845 timeout = -ERESTARTSYS;
1854 timeout = io_schedule_timeout(timeout);
1856 __set_current_state(TASK_RUNNING);
1858 if (READ_ONCE(wait.tsk))
1859 dma_fence_remove_callback(&rq->fence, &wait.cb);
1860 GEM_BUG_ON(!list_empty(&wait.cb.node));
1863 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1864 trace_i915_request_wait_end(rq);
1868 static int print_sched_attr(const struct i915_sched_attr *attr,
1869 char *buf, int x, int len)
1871 if (attr->priority == I915_PRIORITY_INVALID)
1874 x += snprintf(buf + x, len - x,
1875 " prio=%d", attr->priority);
1880 static char queue_status(const struct i915_request *rq)
1882 if (i915_request_is_active(rq))
1885 if (i915_request_is_ready(rq))
1886 return intel_engine_is_virtual(rq->engine) ? 'V' : 'R';
1891 static const char *run_status(const struct i915_request *rq)
1893 if (i915_request_completed(rq))
1896 if (i915_request_started(rq))
1899 if (!i915_sw_fence_signaled(&rq->semaphore))
1905 static const char *fence_status(const struct i915_request *rq)
1907 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
1910 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
1916 void i915_request_show(struct drm_printer *m,
1917 const struct i915_request *rq,
1921 const char *name = rq->fence.ops->get_timeline_name((struct dma_fence *)&rq->fence);
1926 * The prefix is used to show the queue status, for which we use
1927 * the following flags:
1930 * - initial status upon being submitted by the user
1932 * - the request is not ready for execution as it is waiting
1933 * for external fences
1936 * - all fences the request was waiting on have been signaled,
1937 * and the request is now ready for execution and will be
1938 * in a backend queue
1940 * - a ready request may still need to wait on semaphores
1944 * - same as ready, but queued over multiple backends
1947 * - the request has been transferred from the backend queue and
1948 * submitted for execution on HW
1950 * - a completed request may still be regarded as executing, its
1951 * status may not be updated until it is retired and removed
1955 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
1957 drm_printf(m, "%s%.*s%c %llx:%lld%s%s %s @ %dms: %s\n",
1958 prefix, indent, " ",
1960 rq->fence.context, rq->fence.seqno,
1964 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1968 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1969 #include "selftests/mock_request.c"
1970 #include "selftests/i915_request.c"
1973 static void i915_global_request_shrink(void)
1975 kmem_cache_shrink(global.slab_execute_cbs);
1976 kmem_cache_shrink(global.slab_requests);
1979 static void i915_global_request_exit(void)
1981 kmem_cache_destroy(global.slab_execute_cbs);
1982 kmem_cache_destroy(global.slab_requests);
1985 static struct i915_global_request global = { {
1986 .shrink = i915_global_request_shrink,
1987 .exit = i915_global_request_exit,
1990 int __init i915_global_request_init(void)
1992 global.slab_requests =
1993 kmem_cache_create("i915_request",
1994 sizeof(struct i915_request),
1995 __alignof__(struct i915_request),
1996 SLAB_HWCACHE_ALIGN |
1997 SLAB_RECLAIM_ACCOUNT |
1998 SLAB_TYPESAFE_BY_RCU,
1999 __i915_request_ctor);
2000 if (!global.slab_requests)
2003 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
2004 SLAB_HWCACHE_ALIGN |
2005 SLAB_RECLAIM_ACCOUNT |
2006 SLAB_TYPESAFE_BY_RCU);
2007 if (!global.slab_execute_cbs)
2010 i915_global_register(&global.base);
2014 kmem_cache_destroy(global.slab_requests);