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25 #include <linux/dma-fence-array.h>
26 #include <linux/dma-fence-chain.h>
27 #include <linux/irq_work.h>
28 #include <linux/prefetch.h>
29 #include <linux/sched.h>
30 #include <linux/sched/clock.h>
31 #include <linux/sched/signal.h>
33 #include "gem/i915_gem_context.h"
34 #include "gt/intel_breadcrumbs.h"
35 #include "gt/intel_context.h"
36 #include "gt/intel_ring.h"
37 #include "gt/intel_rps.h"
39 #include "i915_active.h"
41 #include "i915_globals.h"
42 #include "i915_trace.h"
47 struct i915_sw_fence *fence;
48 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
49 struct i915_request *signal;
52 static struct i915_global_request {
53 struct i915_global base;
54 struct kmem_cache *slab_requests;
55 struct kmem_cache *slab_execute_cbs;
58 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
60 return dev_name(to_request(fence)->engine->i915->drm.dev);
63 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
65 const struct i915_gem_context *ctx;
68 * The timeline struct (as part of the ppgtt underneath a context)
69 * may be freed when the request is no longer in use by the GPU.
70 * We could extend the life of a context to beyond that of all
71 * fences, possibly keeping the hw resource around indefinitely,
72 * or we just give them a false name. Since
73 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
74 * lie seems justifiable.
76 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
79 ctx = i915_request_gem_context(to_request(fence));
81 return "[" DRIVER_NAME "]";
86 static bool i915_fence_signaled(struct dma_fence *fence)
88 return i915_request_completed(to_request(fence));
91 static bool i915_fence_enable_signaling(struct dma_fence *fence)
93 return i915_request_enable_breadcrumb(to_request(fence));
96 static signed long i915_fence_wait(struct dma_fence *fence,
100 return i915_request_wait(to_request(fence),
101 interruptible | I915_WAIT_PRIORITY,
105 struct kmem_cache *i915_request_slab_cache(void)
107 return global.slab_requests;
110 static void i915_fence_release(struct dma_fence *fence)
112 struct i915_request *rq = to_request(fence);
115 * The request is put onto a RCU freelist (i.e. the address
116 * is immediately reused), mark the fences as being freed now.
117 * Otherwise the debugobjects for the fences are only marked as
118 * freed when the slab cache itself is freed, and so we would get
119 * caught trying to reuse dead objects.
121 i915_sw_fence_fini(&rq->submit);
122 i915_sw_fence_fini(&rq->semaphore);
125 * Keep one request on each engine for reserved use under mempressure
127 * We do not hold a reference to the engine here and so have to be
128 * very careful in what rq->engine we poke. The virtual engine is
129 * referenced via the rq->context and we released that ref during
130 * i915_request_retire(), ergo we must not dereference a virtual
131 * engine here. Not that we would want to, as the only consumer of
132 * the reserved engine->request_pool is the power management parking,
133 * which must-not-fail, and that is only run on the physical engines.
135 * Since the request must have been executed to be have completed,
136 * we know that it will have been processed by the HW and will
137 * not be unsubmitted again, so rq->engine and rq->execution_mask
138 * at this point is stable. rq->execution_mask will be a single
139 * bit if the last and _only_ engine it could execution on was a
140 * physical engine, if it's multiple bits then it started on and
141 * could still be on a virtual engine. Thus if the mask is not a
142 * power-of-two we assume that rq->engine may still be a virtual
143 * engine and so a dangling invalid pointer that we cannot dereference
145 * For example, consider the flow of a bonded request through a virtual
146 * engine. The request is created with a wide engine mask (all engines
147 * that we might execute on). On processing the bond, the request mask
148 * is reduced to one or more engines. If the request is subsequently
149 * bound to a single engine, it will then be constrained to only
150 * execute on that engine and never returned to the virtual engine
151 * after timeslicing away, see __unwind_incomplete_requests(). Thus we
152 * know that if the rq->execution_mask is a single bit, rq->engine
153 * can be a physical engine with the exact corresponding mask.
155 if (is_power_of_2(rq->execution_mask) &&
156 !cmpxchg(&rq->engine->request_pool, NULL, rq))
159 kmem_cache_free(global.slab_requests, rq);
162 const struct dma_fence_ops i915_fence_ops = {
163 .get_driver_name = i915_fence_get_driver_name,
164 .get_timeline_name = i915_fence_get_timeline_name,
165 .enable_signaling = i915_fence_enable_signaling,
166 .signaled = i915_fence_signaled,
167 .wait = i915_fence_wait,
168 .release = i915_fence_release,
171 static void irq_execute_cb(struct irq_work *wrk)
173 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
175 i915_sw_fence_complete(cb->fence);
176 kmem_cache_free(global.slab_execute_cbs, cb);
179 static void irq_execute_cb_hook(struct irq_work *wrk)
181 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
183 cb->hook(container_of(cb->fence, struct i915_request, submit),
185 i915_request_put(cb->signal);
190 static void __notify_execute_cb(struct i915_request *rq)
192 struct execute_cb *cb, *cn;
194 lockdep_assert_held(&rq->lock);
196 GEM_BUG_ON(!i915_request_is_active(rq));
197 if (llist_empty(&rq->execute_cb))
200 llist_for_each_entry_safe(cb, cn, rq->execute_cb.first, work.llnode)
201 irq_work_queue(&cb->work);
204 * XXX Rollback on __i915_request_unsubmit()
206 * In the future, perhaps when we have an active time-slicing scheduler,
207 * it will be interesting to unsubmit parallel execution and remove
208 * busywaits from the GPU until their master is restarted. This is
209 * quite hairy, we have to carefully rollback the fence and do a
210 * preempt-to-idle cycle on the target engine, all the while the
211 * master execute_cb may refire.
213 init_llist_head(&rq->execute_cb);
216 static void free_capture_list(struct i915_request *request)
218 struct i915_capture_list *capture;
220 capture = fetch_and_zero(&request->capture_list);
222 struct i915_capture_list *next = capture->next;
229 static void __i915_request_fill(struct i915_request *rq, u8 val)
231 void *vaddr = rq->ring->vaddr;
235 if (rq->postfix < head) {
236 memset(vaddr + head, val, rq->ring->size - head);
239 memset(vaddr + head, val, rq->postfix - head);
242 static void remove_from_engine(struct i915_request *rq)
244 struct intel_engine_cs *engine, *locked;
247 * Virtual engines complicate acquiring the engine timeline lock,
248 * as their rq->engine pointer is not stable until under that
249 * engine lock. The simple ploy we use is to take the lock then
250 * check that the rq still belongs to the newly locked engine.
252 locked = READ_ONCE(rq->engine);
253 spin_lock_irq(&locked->active.lock);
254 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
255 spin_unlock(&locked->active.lock);
256 spin_lock(&engine->active.lock);
259 list_del_init(&rq->sched.link);
260 clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
261 clear_bit(I915_FENCE_FLAG_HOLD, &rq->fence.flags);
262 spin_unlock_irq(&locked->active.lock);
265 bool i915_request_retire(struct i915_request *rq)
267 if (!i915_request_completed(rq))
272 GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit));
273 trace_i915_request_retire(rq);
276 * We know the GPU must have read the request to have
277 * sent us the seqno + interrupt, so use the position
278 * of tail of the request to update the last known position
281 * Note this requires that we are always called in request
284 GEM_BUG_ON(!list_is_first(&rq->link,
285 &i915_request_timeline(rq)->requests));
286 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
287 /* Poison before we release our space in the ring */
288 __i915_request_fill(rq, POISON_FREE);
289 rq->ring->head = rq->postfix;
292 * We only loosely track inflight requests across preemption,
293 * and so we may find ourselves attempting to retire a _completed_
294 * request that we have removed from the HW and put back on a run
297 remove_from_engine(rq);
299 i915_request_mark_complete(rq);
300 if (!i915_request_signaled(rq)) {
301 spin_lock_irq(&rq->lock);
302 dma_fence_signal_locked(&rq->fence);
303 spin_unlock_irq(&rq->lock);
306 if (i915_request_has_waitboost(rq)) {
307 GEM_BUG_ON(!atomic_read(&rq->engine->gt->rps.num_waiters));
308 atomic_dec(&rq->engine->gt->rps.num_waiters);
312 * We only loosely track inflight requests across preemption,
313 * and so we may find ourselves attempting to retire a _completed_
314 * request that we have removed from the HW and put back on a run
317 * As we set I915_FENCE_FLAG_ACTIVE on the request, this should be
318 * after removing the breadcrumb and signaling it, so that we do not
319 * inadvertently attach the breadcrumb to a completed request.
321 remove_from_engine(rq);
322 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
323 spin_unlock_irq(&rq->lock);
325 __list_del_entry(&rq->link); /* poison neither prev/next (RCU walks) */
327 intel_context_exit(rq->context);
328 intel_context_unpin(rq->context);
330 free_capture_list(rq);
331 i915_sched_node_fini(&rq->sched);
332 i915_request_put(rq);
337 void i915_request_retire_upto(struct i915_request *rq)
339 struct intel_timeline * const tl = i915_request_timeline(rq);
340 struct i915_request *tmp;
344 GEM_BUG_ON(!i915_request_completed(rq));
347 tmp = list_first_entry(&tl->requests, typeof(*tmp), link);
348 } while (i915_request_retire(tmp) && tmp != rq);
351 static void __llist_add(struct llist_node *node, struct llist_head *head)
353 node->next = head->first;
357 static struct i915_request * const *
358 __engine_active(struct intel_engine_cs *engine)
360 return READ_ONCE(engine->execlists.active);
363 static bool __request_in_flight(const struct i915_request *signal)
365 struct i915_request * const *port, *rq;
366 bool inflight = false;
368 if (!i915_request_is_ready(signal))
372 * Even if we have unwound the request, it may still be on
373 * the GPU (preempt-to-busy). If that request is inside an
374 * unpreemptible critical section, it will not be removed. Some
375 * GPU functions may even be stuck waiting for the paired request
376 * (__await_execution) to be submitted and cannot be preempted
377 * until the bond is executing.
379 * As we know that there are always preemption points between
380 * requests, we know that only the currently executing request
381 * may be still active even though we have cleared the flag.
382 * However, we can't rely on our tracking of ELSP[0] to know
383 * which request is currently active and so maybe stuck, as
384 * the tracking maybe an event behind. Instead assume that
385 * if the context is still inflight, then it is still active
386 * even if the active flag has been cleared.
388 * To further complicate matters, if there a pending promotion, the HW
389 * may either perform a context switch to the second inflight execlists,
390 * or it may switch to the pending set of execlists. In the case of the
391 * latter, it may send the ACK and we process the event copying the
392 * pending[] over top of inflight[], _overwriting_ our *active. Since
393 * this implies the HW is arbitrating and not struck in *active, we do
394 * not worry about complete accuracy, but we do require no read/write
395 * tearing of the pointer [the read of the pointer must be valid, even
396 * as the array is being overwritten, for which we require the writes
399 * Note that the read of *execlists->active may race with the promotion
400 * of execlists->pending[] to execlists->inflight[], overwritting
401 * the value at *execlists->active. This is fine. The promotion implies
402 * that we received an ACK from the HW, and so the context is not
403 * stuck -- if we do not see ourselves in *active, the inflight status
404 * is valid. If instead we see ourselves being copied into *active,
405 * we are inflight and may signal the callback.
407 if (!intel_context_inflight(signal->context))
411 for (port = __engine_active(signal->engine);
412 (rq = READ_ONCE(*port)); /* may race with promotion of pending[] */
414 if (rq->context == signal->context) {
415 inflight = i915_seqno_passed(rq->fence.seqno,
416 signal->fence.seqno);
426 __await_execution(struct i915_request *rq,
427 struct i915_request *signal,
428 void (*hook)(struct i915_request *rq,
429 struct dma_fence *signal),
432 struct execute_cb *cb;
434 if (i915_request_is_active(signal)) {
436 hook(rq, &signal->fence);
440 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
444 cb->fence = &rq->submit;
445 i915_sw_fence_await(cb->fence);
446 init_irq_work(&cb->work, irq_execute_cb);
450 cb->signal = i915_request_get(signal);
451 cb->work.func = irq_execute_cb_hook;
454 spin_lock_irq(&signal->lock);
455 if (i915_request_is_active(signal) || __request_in_flight(signal)) {
457 hook(rq, &signal->fence);
458 i915_request_put(signal);
460 i915_sw_fence_complete(cb->fence);
461 kmem_cache_free(global.slab_execute_cbs, cb);
463 __llist_add(&cb->work.llnode, &signal->execute_cb);
465 spin_unlock_irq(&signal->lock);
470 static bool fatal_error(int error)
473 case 0: /* not an error! */
474 case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */
475 case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */
482 void __i915_request_skip(struct i915_request *rq)
484 GEM_BUG_ON(!fatal_error(rq->fence.error));
486 if (rq->infix == rq->postfix)
490 * As this request likely depends on state from the lost
491 * context, clear out all the user operations leaving the
492 * breadcrumb at the end (so we get the fence notifications).
494 __i915_request_fill(rq, 0);
495 rq->infix = rq->postfix;
498 void i915_request_set_error_once(struct i915_request *rq, int error)
502 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
504 if (i915_request_signaled(rq))
507 old = READ_ONCE(rq->fence.error);
509 if (fatal_error(old))
511 } while (!try_cmpxchg(&rq->fence.error, &old, error));
514 bool __i915_request_submit(struct i915_request *request)
516 struct intel_engine_cs *engine = request->engine;
519 RQ_TRACE(request, "\n");
521 GEM_BUG_ON(!irqs_disabled());
522 lockdep_assert_held(&engine->active.lock);
525 * With the advent of preempt-to-busy, we frequently encounter
526 * requests that we have unsubmitted from HW, but left running
527 * until the next ack and so have completed in the meantime. On
528 * resubmission of that completed request, we can skip
529 * updating the payload, and execlists can even skip submitting
532 * We must remove the request from the caller's priority queue,
533 * and the caller must only call us when the request is in their
534 * priority queue, under the active.lock. This ensures that the
535 * request has *not* yet been retired and we can safely move
536 * the request into the engine->active.list where it will be
537 * dropped upon retiring. (Otherwise if resubmit a *retired*
538 * request, this would be a horrible use-after-free.)
540 if (i915_request_completed(request))
543 if (unlikely(intel_context_is_banned(request->context)))
544 i915_request_set_error_once(request, -EIO);
545 if (unlikely(fatal_error(request->fence.error)))
546 __i915_request_skip(request);
549 * Are we using semaphores when the gpu is already saturated?
551 * Using semaphores incurs a cost in having the GPU poll a
552 * memory location, busywaiting for it to change. The continual
553 * memory reads can have a noticeable impact on the rest of the
554 * system with the extra bus traffic, stalling the cpu as it too
555 * tries to access memory across the bus (perf stat -e bus-cycles).
557 * If we installed a semaphore on this request and we only submit
558 * the request after the signaler completed, that indicates the
559 * system is overloaded and using semaphores at this time only
560 * increases the amount of work we are doing. If so, we disable
561 * further use of semaphores until we are idle again, whence we
562 * optimistically try again.
564 if (request->sched.semaphores &&
565 i915_sw_fence_signaled(&request->semaphore))
566 engine->saturated |= request->sched.semaphores;
568 engine->emit_fini_breadcrumb(request,
569 request->ring->vaddr + request->postfix);
571 trace_i915_request_execute(request);
576 if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) {
577 list_move_tail(&request->sched.link, &engine->active.requests);
578 clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags);
582 * XXX Rollback bonded-execution on __i915_request_unsubmit()?
584 * In the future, perhaps when we have an active time-slicing scheduler,
585 * it will be interesting to unsubmit parallel execution and remove
586 * busywaits from the GPU until their master is restarted. This is
587 * quite hairy, we have to carefully rollback the fence and do a
588 * preempt-to-idle cycle on the target engine, all the while the
589 * master execute_cb may refire.
591 __notify_execute_cb(request);
593 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
594 i915_request_enable_breadcrumb(request);
599 void i915_request_submit(struct i915_request *request)
601 struct intel_engine_cs *engine = request->engine;
604 /* Will be called from irq-context when using foreign fences. */
605 spin_lock_irqsave(&engine->active.lock, flags);
607 __i915_request_submit(request);
609 spin_unlock_irqrestore(&engine->active.lock, flags);
612 void __i915_request_unsubmit(struct i915_request *request)
614 struct intel_engine_cs *engine = request->engine;
617 * Only unwind in reverse order, required so that the per-context list
618 * is kept in seqno/ring order.
620 RQ_TRACE(request, "\n");
622 GEM_BUG_ON(!irqs_disabled());
623 lockdep_assert_held(&engine->active.lock);
626 * Before we remove this breadcrumb from the signal list, we have
627 * to ensure that a concurrent dma_fence_enable_signaling() does not
628 * attach itself. We first mark the request as no longer active and
629 * make sure that is visible to other cores, and then remove the
630 * breadcrumb if attached.
632 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
633 clear_bit_unlock(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
634 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
635 i915_request_cancel_breadcrumb(request);
637 /* We've already spun, don't charge on resubmitting. */
638 if (request->sched.semaphores && i915_request_started(request))
639 request->sched.semaphores = 0;
642 * We don't need to wake_up any waiters on request->execute, they
643 * will get woken by any other event or us re-adding this request
644 * to the engine timeline (__i915_request_submit()). The waiters
645 * should be quite adapt at finding that the request now has a new
646 * global_seqno to the one they went to sleep on.
650 void i915_request_unsubmit(struct i915_request *request)
652 struct intel_engine_cs *engine = request->engine;
655 /* Will be called from irq-context when using foreign fences. */
656 spin_lock_irqsave(&engine->active.lock, flags);
658 __i915_request_unsubmit(request);
660 spin_unlock_irqrestore(&engine->active.lock, flags);
663 static int __i915_sw_fence_call
664 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
666 struct i915_request *request =
667 container_of(fence, typeof(*request), submit);
671 trace_i915_request_submit(request);
673 if (unlikely(fence->error))
674 i915_request_set_error_once(request, fence->error);
677 * We need to serialize use of the submit_request() callback
678 * with its hotplugging performed during an emergency
679 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
680 * critical section in order to force i915_gem_set_wedged() to
681 * wait until the submit_request() is completed before
685 request->engine->submit_request(request);
690 i915_request_put(request);
697 static int __i915_sw_fence_call
698 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
700 struct i915_request *rq = container_of(fence, typeof(*rq), semaphore);
707 i915_request_put(rq);
714 static void retire_requests(struct intel_timeline *tl)
716 struct i915_request *rq, *rn;
718 list_for_each_entry_safe(rq, rn, &tl->requests, link)
719 if (!i915_request_retire(rq))
723 static noinline struct i915_request *
724 request_alloc_slow(struct intel_timeline *tl,
725 struct i915_request **rsvd,
728 struct i915_request *rq;
730 /* If we cannot wait, dip into our reserves */
731 if (!gfpflags_allow_blocking(gfp)) {
732 rq = xchg(rsvd, NULL);
733 if (!rq) /* Use the normal failure path for one final WARN */
739 if (list_empty(&tl->requests))
742 /* Move our oldest request to the slab-cache (if not in use!) */
743 rq = list_first_entry(&tl->requests, typeof(*rq), link);
744 i915_request_retire(rq);
746 rq = kmem_cache_alloc(global.slab_requests,
747 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
751 /* Ratelimit ourselves to prevent oom from malicious clients */
752 rq = list_last_entry(&tl->requests, typeof(*rq), link);
753 cond_synchronize_rcu(rq->rcustate);
755 /* Retire our old requests in the hope that we free some */
759 return kmem_cache_alloc(global.slab_requests, gfp);
762 static void __i915_request_ctor(void *arg)
764 struct i915_request *rq = arg;
766 spin_lock_init(&rq->lock);
767 i915_sched_node_init(&rq->sched);
768 i915_sw_fence_init(&rq->submit, submit_notify);
769 i915_sw_fence_init(&rq->semaphore, semaphore_notify);
771 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
773 rq->capture_list = NULL;
775 init_llist_head(&rq->execute_cb);
778 struct i915_request *
779 __i915_request_create(struct intel_context *ce, gfp_t gfp)
781 struct intel_timeline *tl = ce->timeline;
782 struct i915_request *rq;
786 might_sleep_if(gfpflags_allow_blocking(gfp));
788 /* Check that the caller provided an already pinned context */
789 __intel_context_pin(ce);
792 * Beware: Dragons be flying overhead.
794 * We use RCU to look up requests in flight. The lookups may
795 * race with the request being allocated from the slab freelist.
796 * That is the request we are writing to here, may be in the process
797 * of being read by __i915_active_request_get_rcu(). As such,
798 * we have to be very careful when overwriting the contents. During
799 * the RCU lookup, we change chase the request->engine pointer,
800 * read the request->global_seqno and increment the reference count.
802 * The reference count is incremented atomically. If it is zero,
803 * the lookup knows the request is unallocated and complete. Otherwise,
804 * it is either still in use, or has been reallocated and reset
805 * with dma_fence_init(). This increment is safe for release as we
806 * check that the request we have a reference to and matches the active
809 * Before we increment the refcount, we chase the request->engine
810 * pointer. We must not call kmem_cache_zalloc() or else we set
811 * that pointer to NULL and cause a crash during the lookup. If
812 * we see the request is completed (based on the value of the
813 * old engine and seqno), the lookup is complete and reports NULL.
814 * If we decide the request is not completed (new engine or seqno),
815 * then we grab a reference and double check that it is still the
816 * active request - which it won't be and restart the lookup.
818 * Do not use kmem_cache_zalloc() here!
820 rq = kmem_cache_alloc(global.slab_requests,
821 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
823 rq = request_alloc_slow(tl, &ce->engine->request_pool, gfp);
831 rq->engine = ce->engine;
833 rq->execution_mask = ce->engine->mask;
835 kref_init(&rq->fence.refcount);
838 INIT_LIST_HEAD(&rq->fence.cb_list);
840 ret = intel_timeline_get_seqno(tl, rq, &seqno);
844 rq->fence.context = tl->fence_context;
845 rq->fence.seqno = seqno;
847 RCU_INIT_POINTER(rq->timeline, tl);
848 RCU_INIT_POINTER(rq->hwsp_cacheline, tl->hwsp_cacheline);
849 rq->hwsp_seqno = tl->hwsp_seqno;
850 GEM_BUG_ON(i915_request_completed(rq));
852 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
854 /* We bump the ref for the fence chain */
855 i915_sw_fence_reinit(&i915_request_get(rq)->submit);
856 i915_sw_fence_reinit(&i915_request_get(rq)->semaphore);
858 i915_sched_node_reinit(&rq->sched);
860 /* No zalloc, everything must be cleared after use */
862 GEM_BUG_ON(rq->capture_list);
863 GEM_BUG_ON(!llist_empty(&rq->execute_cb));
866 * Reserve space in the ring buffer for all the commands required to
867 * eventually emit this request. This is to guarantee that the
868 * i915_request_add() call can't fail. Note that the reserve may need
869 * to be redone if the request is not actually submitted straight
870 * away, e.g. because a GPU scheduler has deferred it.
872 * Note that due to how we add reserved_space to intel_ring_begin()
873 * we need to double our request to ensure that if we need to wrap
874 * around inside i915_request_add() there is sufficient space at
875 * the beginning of the ring as well.
878 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
881 * Record the position of the start of the request so that
882 * should we detect the updated seqno part-way through the
883 * GPU processing the request, we never over-estimate the
884 * position of the head.
886 rq->head = rq->ring->emit;
888 ret = rq->engine->request_alloc(rq);
892 rq->infix = rq->ring->emit; /* end of header; start of user payload */
894 intel_context_mark_active(ce);
895 list_add_tail_rcu(&rq->link, &tl->requests);
900 ce->ring->emit = rq->head;
902 /* Make sure we didn't add ourselves to external state before freeing */
903 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
904 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
907 kmem_cache_free(global.slab_requests, rq);
909 intel_context_unpin(ce);
913 struct i915_request *
914 i915_request_create(struct intel_context *ce)
916 struct i915_request *rq;
917 struct intel_timeline *tl;
919 tl = intel_context_timeline_lock(ce);
923 /* Move our oldest request to the slab-cache (if not in use!) */
924 rq = list_first_entry(&tl->requests, typeof(*rq), link);
925 if (!list_is_last(&rq->link, &tl->requests))
926 i915_request_retire(rq);
928 intel_context_enter(ce);
929 rq = __i915_request_create(ce, GFP_KERNEL);
930 intel_context_exit(ce); /* active reference transferred to request */
934 /* Check that we do not interrupt ourselves with a new request */
935 rq->cookie = lockdep_pin_lock(&tl->mutex);
940 intel_context_timeline_unlock(tl);
945 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
947 struct dma_fence *fence;
950 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
953 if (i915_request_started(signal))
958 spin_lock_irq(&signal->lock);
960 struct list_head *pos = READ_ONCE(signal->link.prev);
961 struct i915_request *prev;
963 /* Confirm signal has not been retired, the link is valid */
964 if (unlikely(i915_request_started(signal)))
967 /* Is signal the earliest request on its timeline? */
968 if (pos == &rcu_dereference(signal->timeline)->requests)
972 * Peek at the request before us in the timeline. That
973 * request will only be valid before it is retired, so
974 * after acquiring a reference to it, confirm that it is
975 * still part of the signaler's timeline.
977 prev = list_entry(pos, typeof(*prev), link);
978 if (!i915_request_get_rcu(prev))
981 /* After the strong barrier, confirm prev is still attached */
982 if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
983 i915_request_put(prev);
987 fence = &prev->fence;
989 spin_unlock_irq(&signal->lock);
995 if (!intel_timeline_sync_is_later(i915_request_timeline(rq), fence))
996 err = i915_sw_fence_await_dma_fence(&rq->submit,
999 dma_fence_put(fence);
1004 static intel_engine_mask_t
1005 already_busywaiting(struct i915_request *rq)
1008 * Polling a semaphore causes bus traffic, delaying other users of
1009 * both the GPU and CPU. We want to limit the impact on others,
1010 * while taking advantage of early submission to reduce GPU
1011 * latency. Therefore we restrict ourselves to not using more
1012 * than one semaphore from each source, and not using a semaphore
1013 * if we have detected the engine is saturated (i.e. would not be
1014 * submitted early and cause bus traffic reading an already passed
1017 * See the are-we-too-late? check in __i915_request_submit().
1019 return rq->sched.semaphores | READ_ONCE(rq->engine->saturated);
1023 __emit_semaphore_wait(struct i915_request *to,
1024 struct i915_request *from,
1027 const int has_token = INTEL_GEN(to->engine->i915) >= 12;
1032 GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8);
1033 GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
1035 /* We need to pin the signaler's HWSP until we are finished reading. */
1036 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1044 cs = intel_ring_begin(to, len);
1049 * Using greater-than-or-equal here means we have to worry
1050 * about seqno wraparound. To side step that issue, we swap
1051 * the timeline HWSP upon wrapping, so that everyone listening
1052 * for the old (pre-wrap) values do not see the much smaller
1053 * (post-wrap) values than they were expecting (and so wait
1056 *cs++ = (MI_SEMAPHORE_WAIT |
1057 MI_SEMAPHORE_GLOBAL_GTT |
1059 MI_SEMAPHORE_SAD_GTE_SDD) +
1062 *cs++ = hwsp_offset;
1069 intel_ring_advance(to, cs);
1074 emit_semaphore_wait(struct i915_request *to,
1075 struct i915_request *from,
1078 const intel_engine_mask_t mask = READ_ONCE(from->engine)->mask;
1079 struct i915_sw_fence *wait = &to->submit;
1081 if (!intel_context_use_semaphores(to->context))
1084 if (i915_request_has_initial_breadcrumb(to))
1087 if (!rcu_access_pointer(from->hwsp_cacheline))
1091 * If this or its dependents are waiting on an external fence
1092 * that may fail catastrophically, then we want to avoid using
1093 * sempahores as they bypass the fence signaling metadata, and we
1094 * lose the fence->error propagation.
1096 if (from->sched.flags & I915_SCHED_HAS_EXTERNAL_CHAIN)
1099 /* Just emit the first semaphore we see as request space is limited. */
1100 if (already_busywaiting(to) & mask)
1103 if (i915_request_await_start(to, from) < 0)
1106 /* Only submit our spinner after the signaler is running! */
1107 if (__await_execution(to, from, NULL, gfp))
1110 if (__emit_semaphore_wait(to, from, from->fence.seqno))
1113 to->sched.semaphores |= mask;
1114 wait = &to->semaphore;
1117 return i915_sw_fence_await_dma_fence(wait,
1122 static bool intel_timeline_sync_has_start(struct intel_timeline *tl,
1123 struct dma_fence *fence)
1125 return __intel_timeline_sync_is_later(tl,
1130 static int intel_timeline_sync_set_start(struct intel_timeline *tl,
1131 const struct dma_fence *fence)
1133 return __intel_timeline_sync_set(tl, fence->context, fence->seqno - 1);
1137 __i915_request_await_execution(struct i915_request *to,
1138 struct i915_request *from,
1139 void (*hook)(struct i915_request *rq,
1140 struct dma_fence *signal))
1144 GEM_BUG_ON(intel_context_is_barrier(from->context));
1146 /* Submit both requests at the same time */
1147 err = __await_execution(to, from, hook, I915_FENCE_GFP);
1151 /* Squash repeated depenendices to the same timelines */
1152 if (intel_timeline_sync_has_start(i915_request_timeline(to),
1157 * Wait until the start of this request.
1159 * The execution cb fires when we submit the request to HW. But in
1160 * many cases this may be long before the request itself is ready to
1161 * run (consider that we submit 2 requests for the same context, where
1162 * the request of interest is behind an indefinite spinner). So we hook
1163 * up to both to reduce our queues and keep the execution lag minimised
1164 * in the worst case, though we hope that the await_start is elided.
1166 err = i915_request_await_start(to, from);
1171 * Ensure both start together [after all semaphores in signal]
1173 * Now that we are queued to the HW at roughly the same time (thanks
1174 * to the execute cb) and are ready to run at roughly the same time
1175 * (thanks to the await start), our signaler may still be indefinitely
1176 * delayed by waiting on a semaphore from a remote engine. If our
1177 * signaler depends on a semaphore, so indirectly do we, and we do not
1178 * want to start our payload until our signaler also starts theirs.
1181 * However, there is also a second condition for which we need to wait
1182 * for the precise start of the signaler. Consider that the signaler
1183 * was submitted in a chain of requests following another context
1184 * (with just an ordinary intra-engine fence dependency between the
1185 * two). In this case the signaler is queued to HW, but not for
1186 * immediate execution, and so we must wait until it reaches the
1189 if (intel_engine_has_semaphores(to->engine) &&
1190 !i915_request_has_initial_breadcrumb(to)) {
1191 err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
1196 /* Couple the dependency tree for PI on this exposed to->fence */
1197 if (to->engine->schedule) {
1198 err = i915_sched_node_add_dependency(&to->sched,
1200 I915_DEPENDENCY_WEAK);
1205 return intel_timeline_sync_set_start(i915_request_timeline(to),
1209 static void mark_external(struct i915_request *rq)
1212 * The downside of using semaphores is that we lose metadata passing
1213 * along the signaling chain. This is particularly nasty when we
1214 * need to pass along a fatal error such as EFAULT or EDEADLK. For
1215 * fatal errors we want to scrub the request before it is executed,
1216 * which means that we cannot preload the request onto HW and have
1217 * it wait upon a semaphore.
1219 rq->sched.flags |= I915_SCHED_HAS_EXTERNAL_CHAIN;
1223 __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1226 return i915_sw_fence_await_dma_fence(&rq->submit, fence,
1227 i915_fence_context_timeout(rq->engine->i915,
1233 i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
1235 struct dma_fence *iter;
1238 if (!to_dma_fence_chain(fence))
1239 return __i915_request_await_external(rq, fence);
1241 dma_fence_chain_for_each(iter, fence) {
1242 struct dma_fence_chain *chain = to_dma_fence_chain(iter);
1244 if (!dma_fence_is_i915(chain->fence)) {
1245 err = __i915_request_await_external(rq, iter);
1249 err = i915_request_await_dma_fence(rq, chain->fence);
1254 dma_fence_put(iter);
1259 i915_request_await_execution(struct i915_request *rq,
1260 struct dma_fence *fence,
1261 void (*hook)(struct i915_request *rq,
1262 struct dma_fence *signal))
1264 struct dma_fence **child = &fence;
1265 unsigned int nchild = 1;
1268 if (dma_fence_is_array(fence)) {
1269 struct dma_fence_array *array = to_dma_fence_array(fence);
1271 /* XXX Error for signal-on-any fence arrays */
1273 child = array->fences;
1274 nchild = array->num_fences;
1275 GEM_BUG_ON(!nchild);
1280 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1281 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1285 if (fence->context == rq->fence.context)
1289 * We don't squash repeated fence dependencies here as we
1290 * want to run our callback in all cases.
1293 if (dma_fence_is_i915(fence))
1294 ret = __i915_request_await_execution(rq,
1298 ret = i915_request_await_external(rq, fence);
1307 await_request_submit(struct i915_request *to, struct i915_request *from)
1310 * If we are waiting on a virtual engine, then it may be
1311 * constrained to execute on a single engine *prior* to submission.
1312 * When it is submitted, it will be first submitted to the virtual
1313 * engine and then passed to the physical engine. We cannot allow
1314 * the waiter to be submitted immediately to the physical engine
1315 * as it may then bypass the virtual request.
1317 if (to->engine == READ_ONCE(from->engine))
1318 return i915_sw_fence_await_sw_fence_gfp(&to->submit,
1322 return __i915_request_await_execution(to, from, NULL);
1326 i915_request_await_request(struct i915_request *to, struct i915_request *from)
1330 GEM_BUG_ON(to == from);
1331 GEM_BUG_ON(to->timeline == from->timeline);
1333 if (i915_request_completed(from)) {
1334 i915_sw_fence_set_error_once(&to->submit, from->fence.error);
1338 if (to->engine->schedule) {
1339 ret = i915_sched_node_add_dependency(&to->sched,
1341 I915_DEPENDENCY_EXTERNAL);
1346 if (is_power_of_2(to->execution_mask | READ_ONCE(from->execution_mask)))
1347 ret = await_request_submit(to, from);
1349 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
1357 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
1359 struct dma_fence **child = &fence;
1360 unsigned int nchild = 1;
1364 * Note that if the fence-array was created in signal-on-any mode,
1365 * we should *not* decompose it into its individual fences. However,
1366 * we don't currently store which mode the fence-array is operating
1367 * in. Fortunately, the only user of signal-on-any is private to
1368 * amdgpu and we should not see any incoming fence-array from
1369 * sync-file being in signal-on-any mode.
1371 if (dma_fence_is_array(fence)) {
1372 struct dma_fence_array *array = to_dma_fence_array(fence);
1374 child = array->fences;
1375 nchild = array->num_fences;
1376 GEM_BUG_ON(!nchild);
1381 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
1382 i915_sw_fence_set_error_once(&rq->submit, fence->error);
1387 * Requests on the same timeline are explicitly ordered, along
1388 * with their dependencies, by i915_request_add() which ensures
1389 * that requests are submitted in-order through each ring.
1391 if (fence->context == rq->fence.context)
1394 /* Squash repeated waits to the same timelines */
1395 if (fence->context &&
1396 intel_timeline_sync_is_later(i915_request_timeline(rq),
1400 if (dma_fence_is_i915(fence))
1401 ret = i915_request_await_request(rq, to_request(fence));
1403 ret = i915_request_await_external(rq, fence);
1407 /* Record the latest fence used against each timeline */
1409 intel_timeline_sync_set(i915_request_timeline(rq),
1417 * i915_request_await_object - set this request to (async) wait upon a bo
1418 * @to: request we are wishing to use
1419 * @obj: object which may be in use on another ring.
1420 * @write: whether the wait is on behalf of a writer
1422 * This code is meant to abstract object synchronization with the GPU.
1423 * Conceptually we serialise writes between engines inside the GPU.
1424 * We only allow one engine to write into a buffer at any time, but
1425 * multiple readers. To ensure each has a coherent view of memory, we must:
1427 * - If there is an outstanding write request to the object, the new
1428 * request must wait for it to complete (either CPU or in hw, requests
1429 * on the same ring will be naturally ordered).
1431 * - If we are a write request (pending_write_domain is set), the new
1432 * request must wait for outstanding read requests to complete.
1434 * Returns 0 if successful, else propagates up the lower layer error.
1437 i915_request_await_object(struct i915_request *to,
1438 struct drm_i915_gem_object *obj,
1441 struct dma_fence *excl;
1445 struct dma_fence **shared;
1446 unsigned int count, i;
1448 ret = dma_resv_get_fences_rcu(obj->base.resv,
1449 &excl, &count, &shared);
1453 for (i = 0; i < count; i++) {
1454 ret = i915_request_await_dma_fence(to, shared[i]);
1458 dma_fence_put(shared[i]);
1461 for (; i < count; i++)
1462 dma_fence_put(shared[i]);
1465 excl = dma_resv_get_excl_rcu(obj->base.resv);
1470 ret = i915_request_await_dma_fence(to, excl);
1472 dma_fence_put(excl);
1478 static struct i915_request *
1479 __i915_request_add_to_timeline(struct i915_request *rq)
1481 struct intel_timeline *timeline = i915_request_timeline(rq);
1482 struct i915_request *prev;
1485 * Dependency tracking and request ordering along the timeline
1486 * is special cased so that we can eliminate redundant ordering
1487 * operations while building the request (we know that the timeline
1488 * itself is ordered, and here we guarantee it).
1490 * As we know we will need to emit tracking along the timeline,
1491 * we embed the hooks into our request struct -- at the cost of
1492 * having to have specialised no-allocation interfaces (which will
1493 * be beneficial elsewhere).
1495 * A second benefit to open-coding i915_request_await_request is
1496 * that we can apply a slight variant of the rules specialised
1497 * for timelines that jump between engines (such as virtual engines).
1498 * If we consider the case of virtual engine, we must emit a dma-fence
1499 * to prevent scheduling of the second request until the first is
1500 * complete (to maximise our greedy late load balancing) and this
1501 * precludes optimising to use semaphores serialisation of a single
1502 * timeline across engines.
1504 prev = to_request(__i915_active_fence_set(&timeline->last_request,
1506 if (prev && !i915_request_completed(prev)) {
1508 * The requests are supposed to be kept in order. However,
1509 * we need to be wary in case the timeline->last_request
1510 * is used as a barrier for external modification to this
1513 GEM_BUG_ON(prev->context == rq->context &&
1514 i915_seqno_passed(prev->fence.seqno,
1517 if (is_power_of_2(READ_ONCE(prev->engine)->mask | rq->engine->mask))
1518 i915_sw_fence_await_sw_fence(&rq->submit,
1522 __i915_sw_fence_await_dma_fence(&rq->submit,
1525 if (rq->engine->schedule)
1526 __i915_sched_node_add_dependency(&rq->sched,
1533 * Make sure that no request gazumped us - if it was allocated after
1534 * our i915_request_alloc() and called __i915_request_add() before
1535 * us, the timeline will hold its seqno which is later than ours.
1537 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1543 * NB: This function is not allowed to fail. Doing so would mean the the
1544 * request is not being tracked for completion but the work itself is
1545 * going to happen on the hardware. This would be a Bad Thing(tm).
1547 struct i915_request *__i915_request_commit(struct i915_request *rq)
1549 struct intel_engine_cs *engine = rq->engine;
1550 struct intel_ring *ring = rq->ring;
1556 * To ensure that this call will not fail, space for its emissions
1557 * should already have been reserved in the ring buffer. Let the ring
1558 * know that it is time to use that space up.
1560 GEM_BUG_ON(rq->reserved_space > ring->space);
1561 rq->reserved_space = 0;
1562 rq->emitted_jiffies = jiffies;
1565 * Record the position of the start of the breadcrumb so that
1566 * should we detect the updated seqno part-way through the
1567 * GPU processing the request, we never over-estimate the
1568 * position of the ring's HEAD.
1570 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1571 GEM_BUG_ON(IS_ERR(cs));
1572 rq->postfix = intel_ring_offset(rq, cs);
1574 return __i915_request_add_to_timeline(rq);
1577 void __i915_request_queue(struct i915_request *rq,
1578 const struct i915_sched_attr *attr)
1581 * Let the backend know a new request has arrived that may need
1582 * to adjust the existing execution schedule due to a high priority
1583 * request - i.e. we may want to preempt the current request in order
1584 * to run a high priority dependency chain *before* we can execute this
1587 * This is called before the request is ready to run so that we can
1588 * decide whether to preempt the entire chain so that it is ready to
1589 * run at the earliest possible convenience.
1591 if (attr && rq->engine->schedule)
1592 rq->engine->schedule(rq, attr);
1593 i915_sw_fence_commit(&rq->semaphore);
1594 i915_sw_fence_commit(&rq->submit);
1597 void i915_request_add(struct i915_request *rq)
1599 struct intel_timeline * const tl = i915_request_timeline(rq);
1600 struct i915_sched_attr attr = {};
1601 struct i915_gem_context *ctx;
1603 lockdep_assert_held(&tl->mutex);
1604 lockdep_unpin_lock(&tl->mutex, rq->cookie);
1606 trace_i915_request_add(rq);
1607 __i915_request_commit(rq);
1609 /* XXX placeholder for selftests */
1611 ctx = rcu_dereference(rq->context->gem_context);
1616 __i915_request_queue(rq, &attr);
1618 mutex_unlock(&tl->mutex);
1621 static unsigned long local_clock_ns(unsigned int *cpu)
1626 * Cheaply and approximately convert from nanoseconds to microseconds.
1627 * The result and subsequent calculations are also defined in the same
1628 * approximate microseconds units. The principal source of timing
1629 * error here is from the simple truncation.
1631 * Note that local_clock() is only defined wrt to the current CPU;
1632 * the comparisons are no longer valid if we switch CPUs. Instead of
1633 * blocking preemption for the entire busywait, we can detect the CPU
1634 * switch and use that as indicator of system load and a reason to
1635 * stop busywaiting, see busywait_stop().
1644 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1646 unsigned int this_cpu;
1648 if (time_after(local_clock_ns(&this_cpu), timeout))
1651 return this_cpu != cpu;
1654 static bool __i915_spin_request(struct i915_request * const rq, int state)
1656 unsigned long timeout_ns;
1660 * Only wait for the request if we know it is likely to complete.
1662 * We don't track the timestamps around requests, nor the average
1663 * request length, so we do not have a good indicator that this
1664 * request will complete within the timeout. What we do know is the
1665 * order in which requests are executed by the context and so we can
1666 * tell if the request has been started. If the request is not even
1667 * running yet, it is a fair assumption that it will not complete
1668 * within our relatively short timeout.
1670 if (!i915_request_is_running(rq))
1674 * When waiting for high frequency requests, e.g. during synchronous
1675 * rendering split between the CPU and GPU, the finite amount of time
1676 * required to set up the irq and wait upon it limits the response
1677 * rate. By busywaiting on the request completion for a short while we
1678 * can service the high frequency waits as quick as possible. However,
1679 * if it is a slow request, we want to sleep as quickly as possible.
1680 * The tradeoff between waiting and sleeping is roughly the time it
1681 * takes to sleep on a request, on the order of a microsecond.
1684 timeout_ns = READ_ONCE(rq->engine->props.max_busywait_duration_ns);
1685 timeout_ns += local_clock_ns(&cpu);
1687 if (dma_fence_is_signaled(&rq->fence))
1690 if (signal_pending_state(state, current))
1693 if (busywait_stop(timeout_ns, cpu))
1697 } while (!need_resched());
1702 struct request_wait {
1703 struct dma_fence_cb cb;
1704 struct task_struct *tsk;
1707 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1709 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1711 wake_up_process(fetch_and_zero(&wait->tsk));
1715 * i915_request_wait - wait until execution of request has finished
1716 * @rq: the request to wait upon
1717 * @flags: how to wait
1718 * @timeout: how long to wait in jiffies
1720 * i915_request_wait() waits for the request to be completed, for a
1721 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1724 * Returns the remaining time (in jiffies) if the request completed, which may
1725 * be zero or -ETIME if the request is unfinished after the timeout expires.
1726 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1727 * pending before the request completes.
1729 long i915_request_wait(struct i915_request *rq,
1733 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1734 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1735 struct request_wait wait;
1738 GEM_BUG_ON(timeout < 0);
1740 if (dma_fence_is_signaled(&rq->fence))
1746 trace_i915_request_wait_begin(rq, flags);
1749 * We must never wait on the GPU while holding a lock as we
1750 * may need to perform a GPU reset. So while we don't need to
1751 * serialise wait/reset with an explicit lock, we do want
1752 * lockdep to detect potential dependency cycles.
1754 mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
1757 * Optimistic spin before touching IRQs.
1759 * We may use a rather large value here to offset the penalty of
1760 * switching away from the active task. Frequently, the client will
1761 * wait upon an old swapbuffer to throttle itself to remain within a
1762 * frame of the gpu. If the client is running in lockstep with the gpu,
1763 * then it should not be waiting long at all, and a sleep now will incur
1764 * extra scheduler latency in producing the next frame. To try to
1765 * avoid adding the cost of enabling/disabling the interrupt to the
1766 * short wait, we first spin to see if the request would have completed
1767 * in the time taken to setup the interrupt.
1769 * We need upto 5us to enable the irq, and upto 20us to hide the
1770 * scheduler latency of a context switch, ignoring the secondary
1771 * impacts from a context switch such as cache eviction.
1773 * The scheme used for low-latency IO is called "hybrid interrupt
1774 * polling". The suggestion there is to sleep until just before you
1775 * expect to be woken by the device interrupt and then poll for its
1776 * completion. That requires having a good predictor for the request
1777 * duration, which we currently lack.
1779 if (IS_ACTIVE(CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT) &&
1780 __i915_spin_request(rq, state))
1784 * This client is about to stall waiting for the GPU. In many cases
1785 * this is undesirable and limits the throughput of the system, as
1786 * many clients cannot continue processing user input/output whilst
1787 * blocked. RPS autotuning may take tens of milliseconds to respond
1788 * to the GPU load and thus incurs additional latency for the client.
1789 * We can circumvent that by promoting the GPU frequency to maximum
1790 * before we sleep. This makes the GPU throttle up much more quickly
1791 * (good for benchmarks and user experience, e.g. window animations),
1792 * but at a cost of spending more power processing the workload
1793 * (bad for battery).
1795 if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
1796 intel_rps_boost(rq);
1799 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1803 * Flush the submission tasklet, but only if it may help this request.
1805 * We sometimes experience some latency between the HW interrupts and
1806 * tasklet execution (mostly due to ksoftirqd latency, but it can also
1807 * be due to lazy CS events), so lets run the tasklet manually if there
1808 * is a chance it may submit this request. If the request is not ready
1809 * to run, as it is waiting for other fences to be signaled, flushing
1810 * the tasklet is busy work without any advantage for this client.
1812 * If the HW is being lazy, this is the last chance before we go to
1813 * sleep to catch any pending events. We will check periodically in
1814 * the heartbeat to flush the submission tasklets as a last resort
1817 if (i915_request_is_ready(rq))
1818 intel_engine_flush_submission(rq->engine);
1821 set_current_state(state);
1823 if (dma_fence_is_signaled(&rq->fence))
1826 if (signal_pending_state(state, current)) {
1827 timeout = -ERESTARTSYS;
1836 timeout = io_schedule_timeout(timeout);
1838 __set_current_state(TASK_RUNNING);
1840 if (READ_ONCE(wait.tsk))
1841 dma_fence_remove_callback(&rq->fence, &wait.cb);
1842 GEM_BUG_ON(!list_empty(&wait.cb.node));
1845 mutex_release(&rq->engine->gt->reset.mutex.dep_map, _THIS_IP_);
1846 trace_i915_request_wait_end(rq);
1850 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1851 #include "selftests/mock_request.c"
1852 #include "selftests/i915_request.c"
1855 static void i915_global_request_shrink(void)
1857 kmem_cache_shrink(global.slab_execute_cbs);
1858 kmem_cache_shrink(global.slab_requests);
1861 static void i915_global_request_exit(void)
1863 kmem_cache_destroy(global.slab_execute_cbs);
1864 kmem_cache_destroy(global.slab_requests);
1867 static struct i915_global_request global = { {
1868 .shrink = i915_global_request_shrink,
1869 .exit = i915_global_request_exit,
1872 int __init i915_global_request_init(void)
1874 global.slab_requests =
1875 kmem_cache_create("i915_request",
1876 sizeof(struct i915_request),
1877 __alignof__(struct i915_request),
1878 SLAB_HWCACHE_ALIGN |
1879 SLAB_RECLAIM_ACCOUNT |
1880 SLAB_TYPESAFE_BY_RCU,
1881 __i915_request_ctor);
1882 if (!global.slab_requests)
1885 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1886 SLAB_HWCACHE_ALIGN |
1887 SLAB_RECLAIM_ACCOUNT |
1888 SLAB_TYPESAFE_BY_RCU);
1889 if (!global.slab_execute_cbs)
1892 i915_global_register(&global.base);
1896 kmem_cache_destroy(global.slab_requests);