2 * Copyright © 2008-2015 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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25 #include <linux/dma-fence-array.h>
26 #include <linux/irq_work.h>
27 #include <linux/prefetch.h>
28 #include <linux/sched.h>
29 #include <linux/sched/clock.h>
30 #include <linux/sched/signal.h>
32 #include "i915_active.h"
34 #include "i915_globals.h"
38 struct list_head link;
40 struct i915_sw_fence *fence;
41 void (*hook)(struct i915_request *rq, struct dma_fence *signal);
42 struct i915_request *signal;
45 static struct i915_global_request {
46 struct i915_global base;
47 struct kmem_cache *slab_requests;
48 struct kmem_cache *slab_dependencies;
49 struct kmem_cache *slab_execute_cbs;
52 static const char *i915_fence_get_driver_name(struct dma_fence *fence)
57 static const char *i915_fence_get_timeline_name(struct dma_fence *fence)
60 * The timeline struct (as part of the ppgtt underneath a context)
61 * may be freed when the request is no longer in use by the GPU.
62 * We could extend the life of a context to beyond that of all
63 * fences, possibly keeping the hw resource around indefinitely,
64 * or we just give them a false name. Since
65 * dma_fence_ops.get_timeline_name is a debug feature, the occasional
66 * lie seems justifiable.
68 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
71 return to_request(fence)->gem_context->name ?: "[i915]";
74 static bool i915_fence_signaled(struct dma_fence *fence)
76 return i915_request_completed(to_request(fence));
79 static bool i915_fence_enable_signaling(struct dma_fence *fence)
81 return i915_request_enable_breadcrumb(to_request(fence));
84 static signed long i915_fence_wait(struct dma_fence *fence,
88 return i915_request_wait(to_request(fence),
89 interruptible | I915_WAIT_PRIORITY,
93 static void i915_fence_release(struct dma_fence *fence)
95 struct i915_request *rq = to_request(fence);
98 * The request is put onto a RCU freelist (i.e. the address
99 * is immediately reused), mark the fences as being freed now.
100 * Otherwise the debugobjects for the fences are only marked as
101 * freed when the slab cache itself is freed, and so we would get
102 * caught trying to reuse dead objects.
104 i915_sw_fence_fini(&rq->submit);
105 i915_sw_fence_fini(&rq->semaphore);
107 kmem_cache_free(global.slab_requests, rq);
110 const struct dma_fence_ops i915_fence_ops = {
111 .get_driver_name = i915_fence_get_driver_name,
112 .get_timeline_name = i915_fence_get_timeline_name,
113 .enable_signaling = i915_fence_enable_signaling,
114 .signaled = i915_fence_signaled,
115 .wait = i915_fence_wait,
116 .release = i915_fence_release,
120 i915_request_remove_from_client(struct i915_request *request)
122 struct drm_i915_file_private *file_priv;
124 file_priv = request->file_priv;
128 spin_lock(&file_priv->mm.lock);
129 if (request->file_priv) {
130 list_del(&request->client_link);
131 request->file_priv = NULL;
133 spin_unlock(&file_priv->mm.lock);
136 static void advance_ring(struct i915_request *request)
138 struct intel_ring *ring = request->ring;
142 * We know the GPU must have read the request to have
143 * sent us the seqno + interrupt, so use the position
144 * of tail of the request to update the last known position
147 * Note this requires that we are always called in request
150 GEM_BUG_ON(!list_is_first(&request->ring_link, &ring->request_list));
151 if (list_is_last(&request->ring_link, &ring->request_list)) {
153 * We may race here with execlists resubmitting this request
154 * as we retire it. The resubmission will move the ring->tail
155 * forwards (to request->wa_tail). We either read the
156 * current value that was written to hw, or the value that
157 * is just about to be. Either works, if we miss the last two
158 * noops - they are safe to be replayed on a reset.
160 tail = READ_ONCE(request->tail);
161 list_del(&ring->active_link);
163 tail = request->postfix;
165 list_del_init(&request->ring_link);
170 static void free_capture_list(struct i915_request *request)
172 struct i915_capture_list *capture;
174 capture = request->capture_list;
176 struct i915_capture_list *next = capture->next;
183 static void __retire_engine_request(struct intel_engine_cs *engine,
184 struct i915_request *rq)
186 GEM_TRACE("%s(%s) fence %llx:%lld, current %d\n",
187 __func__, engine->name,
188 rq->fence.context, rq->fence.seqno,
191 GEM_BUG_ON(!i915_request_completed(rq));
195 spin_lock(&engine->timeline.lock);
196 GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests));
197 list_del_init(&rq->link);
198 spin_unlock(&engine->timeline.lock);
200 spin_lock(&rq->lock);
201 i915_request_mark_complete(rq);
202 if (!i915_request_signaled(rq))
203 dma_fence_signal_locked(&rq->fence);
204 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
205 i915_request_cancel_breadcrumb(rq);
207 GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
208 atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
210 spin_unlock(&rq->lock);
215 * The backing object for the context is done after switching to the
216 * *next* context. Therefore we cannot retire the previous context until
217 * the next context has already started running. However, since we
218 * cannot take the required locks at i915_request_submit() we
219 * defer the unpinning of the active context to now, retirement of
220 * the subsequent request.
222 if (engine->last_retired_context)
223 intel_context_unpin(engine->last_retired_context);
224 engine->last_retired_context = rq->hw_context;
227 static void __retire_engine_upto(struct intel_engine_cs *engine,
228 struct i915_request *rq)
230 struct i915_request *tmp;
232 if (list_empty(&rq->link))
236 tmp = list_first_entry(&engine->timeline.requests,
239 GEM_BUG_ON(tmp->engine != engine);
240 __retire_engine_request(engine, tmp);
244 static void i915_request_retire(struct i915_request *request)
246 struct i915_active_request *active, *next;
248 GEM_TRACE("%s fence %llx:%lld, current %d\n",
249 request->engine->name,
250 request->fence.context, request->fence.seqno,
251 hwsp_seqno(request));
253 lockdep_assert_held(&request->i915->drm.struct_mutex);
254 GEM_BUG_ON(!i915_sw_fence_signaled(&request->submit));
255 GEM_BUG_ON(!i915_request_completed(request));
257 trace_i915_request_retire(request);
259 advance_ring(request);
260 free_capture_list(request);
263 * Walk through the active list, calling retire on each. This allows
264 * objects to track their GPU activity and mark themselves as idle
265 * when their *last* active request is completed (updating state
266 * tracking lists for eviction, active references for GEM, etc).
268 * As the ->retire() may free the node, we decouple it first and
269 * pass along the auxiliary information (to avoid dereferencing
270 * the node after the callback).
272 list_for_each_entry_safe(active, next, &request->active_list, link) {
274 * In microbenchmarks or focusing upon time inside the kernel,
275 * we may spend an inordinate amount of time simply handling
276 * the retirement of requests and processing their callbacks.
277 * Of which, this loop itself is particularly hot due to the
278 * cache misses when jumping around the list of
279 * i915_active_request. So we try to keep this loop as
280 * streamlined as possible and also prefetch the next
281 * i915_active_request to try and hide the likely cache miss.
285 INIT_LIST_HEAD(&active->link);
286 RCU_INIT_POINTER(active->request, NULL);
288 active->retire(active, request);
291 i915_request_remove_from_client(request);
293 __retire_engine_upto(request->engine, request);
295 intel_context_exit(request->hw_context);
296 intel_context_unpin(request->hw_context);
298 i915_sched_node_fini(&request->sched);
299 i915_request_put(request);
302 void i915_request_retire_upto(struct i915_request *rq)
304 struct intel_ring *ring = rq->ring;
305 struct i915_request *tmp;
307 GEM_TRACE("%s fence %llx:%lld, current %d\n",
309 rq->fence.context, rq->fence.seqno,
312 lockdep_assert_held(&rq->i915->drm.struct_mutex);
313 GEM_BUG_ON(!i915_request_completed(rq));
315 if (list_empty(&rq->ring_link))
319 tmp = list_first_entry(&ring->request_list,
320 typeof(*tmp), ring_link);
322 i915_request_retire(tmp);
326 static void irq_execute_cb(struct irq_work *wrk)
328 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
330 i915_sw_fence_complete(cb->fence);
331 kmem_cache_free(global.slab_execute_cbs, cb);
334 static void irq_execute_cb_hook(struct irq_work *wrk)
336 struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
338 cb->hook(container_of(cb->fence, struct i915_request, submit),
340 i915_request_put(cb->signal);
345 static void __notify_execute_cb(struct i915_request *rq)
347 struct execute_cb *cb;
349 lockdep_assert_held(&rq->lock);
351 if (list_empty(&rq->execute_cb))
354 list_for_each_entry(cb, &rq->execute_cb, link)
355 irq_work_queue(&cb->work);
358 * XXX Rollback on __i915_request_unsubmit()
360 * In the future, perhaps when we have an active time-slicing scheduler,
361 * it will be interesting to unsubmit parallel execution and remove
362 * busywaits from the GPU until their master is restarted. This is
363 * quite hairy, we have to carefully rollback the fence and do a
364 * preempt-to-idle cycle on the target engine, all the while the
365 * master execute_cb may refire.
367 INIT_LIST_HEAD(&rq->execute_cb);
371 __i915_request_await_execution(struct i915_request *rq,
372 struct i915_request *signal,
373 void (*hook)(struct i915_request *rq,
374 struct dma_fence *signal),
377 struct execute_cb *cb;
379 if (i915_request_is_active(signal)) {
381 hook(rq, &signal->fence);
385 cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
389 cb->fence = &rq->submit;
390 i915_sw_fence_await(cb->fence);
391 init_irq_work(&cb->work, irq_execute_cb);
395 cb->signal = i915_request_get(signal);
396 cb->work.func = irq_execute_cb_hook;
399 spin_lock_irq(&signal->lock);
400 if (i915_request_is_active(signal)) {
402 hook(rq, &signal->fence);
403 i915_request_put(signal);
405 i915_sw_fence_complete(cb->fence);
406 kmem_cache_free(global.slab_execute_cbs, cb);
408 list_add_tail(&cb->link, &signal->execute_cb);
410 spin_unlock_irq(&signal->lock);
415 static void move_to_timeline(struct i915_request *request,
416 struct i915_timeline *timeline)
418 GEM_BUG_ON(request->timeline == &request->engine->timeline);
419 lockdep_assert_held(&request->engine->timeline.lock);
421 spin_lock(&request->timeline->lock);
422 list_move_tail(&request->link, &timeline->requests);
423 spin_unlock(&request->timeline->lock);
426 void __i915_request_submit(struct i915_request *request)
428 struct intel_engine_cs *engine = request->engine;
430 GEM_TRACE("%s fence %llx:%lld -> current %d\n",
432 request->fence.context, request->fence.seqno,
433 hwsp_seqno(request));
435 GEM_BUG_ON(!irqs_disabled());
436 lockdep_assert_held(&engine->timeline.lock);
438 if (i915_gem_context_is_banned(request->gem_context))
439 i915_request_skip(request, -EIO);
442 * Are we using semaphores when the gpu is already saturated?
444 * Using semaphores incurs a cost in having the GPU poll a
445 * memory location, busywaiting for it to change. The continual
446 * memory reads can have a noticeable impact on the rest of the
447 * system with the extra bus traffic, stalling the cpu as it too
448 * tries to access memory across the bus (perf stat -e bus-cycles).
450 * If we installed a semaphore on this request and we only submit
451 * the request after the signaler completed, that indicates the
452 * system is overloaded and using semaphores at this time only
453 * increases the amount of work we are doing. If so, we disable
454 * further use of semaphores until we are idle again, whence we
455 * optimistically try again.
457 if (request->sched.semaphores &&
458 i915_sw_fence_signaled(&request->semaphore))
459 request->hw_context->saturated |= request->sched.semaphores;
461 /* We may be recursing from the signal callback of another i915 fence */
462 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
464 GEM_BUG_ON(test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
465 set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
467 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) &&
468 !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) &&
469 !i915_request_enable_breadcrumb(request))
470 intel_engine_queue_breadcrumbs(engine);
472 __notify_execute_cb(request);
474 spin_unlock(&request->lock);
476 engine->emit_fini_breadcrumb(request,
477 request->ring->vaddr + request->postfix);
479 /* Transfer from per-context onto the global per-engine timeline */
480 move_to_timeline(request, &engine->timeline);
484 trace_i915_request_execute(request);
487 void i915_request_submit(struct i915_request *request)
489 struct intel_engine_cs *engine = request->engine;
492 /* Will be called from irq-context when using foreign fences. */
493 spin_lock_irqsave(&engine->timeline.lock, flags);
495 __i915_request_submit(request);
497 spin_unlock_irqrestore(&engine->timeline.lock, flags);
500 void __i915_request_unsubmit(struct i915_request *request)
502 struct intel_engine_cs *engine = request->engine;
504 GEM_TRACE("%s fence %llx:%lld, current %d\n",
506 request->fence.context, request->fence.seqno,
507 hwsp_seqno(request));
509 GEM_BUG_ON(!irqs_disabled());
510 lockdep_assert_held(&engine->timeline.lock);
513 * Only unwind in reverse order, required so that the per-context list
514 * is kept in seqno/ring order.
517 /* We may be recursing from the signal callback of another i915 fence */
518 spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING);
520 if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags))
521 i915_request_cancel_breadcrumb(request);
523 GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags));
524 clear_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags);
526 spin_unlock(&request->lock);
528 /* Transfer back from the global per-engine timeline to per-context */
529 move_to_timeline(request, request->timeline);
531 /* We've already spun, don't charge on resubmitting. */
532 if (request->sched.semaphores && i915_request_started(request)) {
533 request->sched.attr.priority |= I915_PRIORITY_NOSEMAPHORE;
534 request->sched.semaphores = 0;
538 * We don't need to wake_up any waiters on request->execute, they
539 * will get woken by any other event or us re-adding this request
540 * to the engine timeline (__i915_request_submit()). The waiters
541 * should be quite adapt at finding that the request now has a new
542 * global_seqno to the one they went to sleep on.
546 void i915_request_unsubmit(struct i915_request *request)
548 struct intel_engine_cs *engine = request->engine;
551 /* Will be called from irq-context when using foreign fences. */
552 spin_lock_irqsave(&engine->timeline.lock, flags);
554 __i915_request_unsubmit(request);
556 spin_unlock_irqrestore(&engine->timeline.lock, flags);
559 static int __i915_sw_fence_call
560 submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
562 struct i915_request *request =
563 container_of(fence, typeof(*request), submit);
567 trace_i915_request_submit(request);
569 * We need to serialize use of the submit_request() callback
570 * with its hotplugging performed during an emergency
571 * i915_gem_set_wedged(). We use the RCU mechanism to mark the
572 * critical section in order to force i915_gem_set_wedged() to
573 * wait until the submit_request() is completed before
577 request->engine->submit_request(request);
582 i915_request_put(request);
589 static int __i915_sw_fence_call
590 semaphore_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
592 struct i915_request *request =
593 container_of(fence, typeof(*request), semaphore);
597 i915_schedule_bump_priority(request, I915_PRIORITY_NOSEMAPHORE);
601 i915_request_put(request);
608 static void ring_retire_requests(struct intel_ring *ring)
610 struct i915_request *rq, *rn;
612 list_for_each_entry_safe(rq, rn, &ring->request_list, ring_link) {
613 if (!i915_request_completed(rq))
616 i915_request_retire(rq);
620 static noinline struct i915_request *
621 request_alloc_slow(struct intel_context *ce, gfp_t gfp)
623 struct intel_ring *ring = ce->ring;
624 struct i915_request *rq;
626 if (list_empty(&ring->request_list))
629 if (!gfpflags_allow_blocking(gfp))
632 /* Ratelimit ourselves to prevent oom from malicious clients */
633 rq = list_last_entry(&ring->request_list, typeof(*rq), ring_link);
634 cond_synchronize_rcu(rq->rcustate);
636 /* Retire our old requests in the hope that we free some */
637 ring_retire_requests(ring);
640 return kmem_cache_alloc(global.slab_requests, gfp);
643 struct i915_request *
644 __i915_request_create(struct intel_context *ce, gfp_t gfp)
646 struct i915_timeline *tl = ce->ring->timeline;
647 struct i915_request *rq;
651 might_sleep_if(gfpflags_allow_blocking(gfp));
653 /* Check that the caller provided an already pinned context */
654 __intel_context_pin(ce);
657 * Beware: Dragons be flying overhead.
659 * We use RCU to look up requests in flight. The lookups may
660 * race with the request being allocated from the slab freelist.
661 * That is the request we are writing to here, may be in the process
662 * of being read by __i915_active_request_get_rcu(). As such,
663 * we have to be very careful when overwriting the contents. During
664 * the RCU lookup, we change chase the request->engine pointer,
665 * read the request->global_seqno and increment the reference count.
667 * The reference count is incremented atomically. If it is zero,
668 * the lookup knows the request is unallocated and complete. Otherwise,
669 * it is either still in use, or has been reallocated and reset
670 * with dma_fence_init(). This increment is safe for release as we
671 * check that the request we have a reference to and matches the active
674 * Before we increment the refcount, we chase the request->engine
675 * pointer. We must not call kmem_cache_zalloc() or else we set
676 * that pointer to NULL and cause a crash during the lookup. If
677 * we see the request is completed (based on the value of the
678 * old engine and seqno), the lookup is complete and reports NULL.
679 * If we decide the request is not completed (new engine or seqno),
680 * then we grab a reference and double check that it is still the
681 * active request - which it won't be and restart the lookup.
683 * Do not use kmem_cache_zalloc() here!
685 rq = kmem_cache_alloc(global.slab_requests,
686 gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
688 rq = request_alloc_slow(ce, gfp);
695 ret = i915_timeline_get_seqno(tl, rq, &seqno);
699 rq->i915 = ce->engine->i915;
701 rq->gem_context = ce->gem_context;
702 rq->engine = ce->engine;
705 GEM_BUG_ON(rq->timeline == &ce->engine->timeline);
706 rq->hwsp_seqno = tl->hwsp_seqno;
707 rq->hwsp_cacheline = tl->hwsp_cacheline;
708 rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
710 spin_lock_init(&rq->lock);
711 dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
712 tl->fence_context, seqno);
714 /* We bump the ref for the fence chain */
715 i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
716 i915_sw_fence_init(&i915_request_get(rq)->semaphore, semaphore_notify);
718 i915_sched_node_init(&rq->sched);
720 /* No zalloc, must clear what we need by hand */
721 rq->file_priv = NULL;
723 rq->capture_list = NULL;
724 rq->waitboost = false;
725 rq->execution_mask = ALL_ENGINES;
727 INIT_LIST_HEAD(&rq->active_list);
728 INIT_LIST_HEAD(&rq->execute_cb);
731 * Reserve space in the ring buffer for all the commands required to
732 * eventually emit this request. This is to guarantee that the
733 * i915_request_add() call can't fail. Note that the reserve may need
734 * to be redone if the request is not actually submitted straight
735 * away, e.g. because a GPU scheduler has deferred it.
737 * Note that due to how we add reserved_space to intel_ring_begin()
738 * we need to double our request to ensure that if we need to wrap
739 * around inside i915_request_add() there is sufficient space at
740 * the beginning of the ring as well.
743 2 * rq->engine->emit_fini_breadcrumb_dw * sizeof(u32);
746 * Record the position of the start of the request so that
747 * should we detect the updated seqno part-way through the
748 * GPU processing the request, we never over-estimate the
749 * position of the head.
751 rq->head = rq->ring->emit;
753 ret = rq->engine->request_alloc(rq);
757 rq->infix = rq->ring->emit; /* end of header; start of user payload */
759 /* Keep a second pin for the dual retirement along engine and ring */
760 __intel_context_pin(ce);
762 intel_context_mark_active(ce);
766 ce->ring->emit = rq->head;
768 /* Make sure we didn't add ourselves to external state before freeing */
769 GEM_BUG_ON(!list_empty(&rq->active_list));
770 GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
771 GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
774 kmem_cache_free(global.slab_requests, rq);
776 intel_context_unpin(ce);
780 struct i915_request *
781 i915_request_create(struct intel_context *ce)
783 struct i915_request *rq;
785 intel_context_timeline_lock(ce);
787 /* Move our oldest request to the slab-cache (if not in use!) */
788 rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
789 if (!list_is_last(&rq->ring_link, &ce->ring->request_list) &&
790 i915_request_completed(rq))
791 i915_request_retire(rq);
793 intel_context_enter(ce);
794 rq = __i915_request_create(ce, GFP_KERNEL);
795 intel_context_exit(ce); /* active reference transferred to request */
799 /* Check that we do not interrupt ourselves with a new request */
800 rq->cookie = lockdep_pin_lock(&ce->ring->timeline->mutex);
805 intel_context_timeline_unlock(ce);
810 i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
812 if (list_is_first(&signal->ring_link, &signal->ring->request_list))
815 signal = list_prev_entry(signal, ring_link);
816 if (i915_timeline_sync_is_later(rq->timeline, &signal->fence))
819 return i915_sw_fence_await_dma_fence(&rq->submit,
824 static intel_engine_mask_t
825 already_busywaiting(struct i915_request *rq)
828 * Polling a semaphore causes bus traffic, delaying other users of
829 * both the GPU and CPU. We want to limit the impact on others,
830 * while taking advantage of early submission to reduce GPU
831 * latency. Therefore we restrict ourselves to not using more
832 * than one semaphore from each source, and not using a semaphore
833 * if we have detected the engine is saturated (i.e. would not be
834 * submitted early and cause bus traffic reading an already passed
837 * See the are-we-too-late? check in __i915_request_submit().
839 return rq->sched.semaphores | rq->hw_context->saturated;
843 emit_semaphore_wait(struct i915_request *to,
844 struct i915_request *from,
851 GEM_BUG_ON(!from->timeline->has_initial_breadcrumb);
852 GEM_BUG_ON(INTEL_GEN(to->i915) < 8);
854 /* Just emit the first semaphore we see as request space is limited. */
855 if (already_busywaiting(to) & from->engine->mask)
856 return i915_sw_fence_await_dma_fence(&to->submit,
860 err = i915_request_await_start(to, from);
864 /* Only submit our spinner after the signaler is running! */
865 err = __i915_request_await_execution(to, from, NULL, gfp);
869 /* We need to pin the signaler's HWSP until we are finished reading. */
870 err = i915_timeline_read_hwsp(from, to, &hwsp_offset);
874 cs = intel_ring_begin(to, 4);
879 * Using greater-than-or-equal here means we have to worry
880 * about seqno wraparound. To side step that issue, we swap
881 * the timeline HWSP upon wrapping, so that everyone listening
882 * for the old (pre-wrap) values do not see the much smaller
883 * (post-wrap) values than they were expecting (and so wait
886 *cs++ = MI_SEMAPHORE_WAIT |
887 MI_SEMAPHORE_GLOBAL_GTT |
889 MI_SEMAPHORE_SAD_GTE_SDD;
890 *cs++ = from->fence.seqno;
894 intel_ring_advance(to, cs);
895 to->sched.semaphores |= from->engine->mask;
896 to->sched.flags |= I915_SCHED_HAS_SEMAPHORE_CHAIN;
901 i915_request_await_request(struct i915_request *to, struct i915_request *from)
905 GEM_BUG_ON(to == from);
906 GEM_BUG_ON(to->timeline == from->timeline);
908 if (i915_request_completed(from))
911 if (to->engine->schedule) {
912 ret = i915_sched_node_add_dependency(&to->sched, &from->sched);
917 if (to->engine == from->engine) {
918 ret = i915_sw_fence_await_sw_fence_gfp(&to->submit,
921 } else if (intel_engine_has_semaphores(to->engine) &&
922 to->gem_context->sched.priority >= I915_PRIORITY_NORMAL) {
923 ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
925 ret = i915_sw_fence_await_dma_fence(&to->submit,
932 if (to->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN) {
933 ret = i915_sw_fence_await_dma_fence(&to->semaphore,
944 i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence)
946 struct dma_fence **child = &fence;
947 unsigned int nchild = 1;
951 * Note that if the fence-array was created in signal-on-any mode,
952 * we should *not* decompose it into its individual fences. However,
953 * we don't currently store which mode the fence-array is operating
954 * in. Fortunately, the only user of signal-on-any is private to
955 * amdgpu and we should not see any incoming fence-array from
956 * sync-file being in signal-on-any mode.
958 if (dma_fence_is_array(fence)) {
959 struct dma_fence_array *array = to_dma_fence_array(fence);
961 child = array->fences;
962 nchild = array->num_fences;
968 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
972 * Requests on the same timeline are explicitly ordered, along
973 * with their dependencies, by i915_request_add() which ensures
974 * that requests are submitted in-order through each ring.
976 if (fence->context == rq->fence.context)
979 /* Squash repeated waits to the same timelines */
980 if (fence->context != rq->i915->mm.unordered_timeline &&
981 i915_timeline_sync_is_later(rq->timeline, fence))
984 if (dma_fence_is_i915(fence))
985 ret = i915_request_await_request(rq, to_request(fence));
987 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
993 /* Record the latest fence used against each timeline */
994 if (fence->context != rq->i915->mm.unordered_timeline)
995 i915_timeline_sync_set(rq->timeline, fence);
1002 i915_request_await_execution(struct i915_request *rq,
1003 struct dma_fence *fence,
1004 void (*hook)(struct i915_request *rq,
1005 struct dma_fence *signal))
1007 struct dma_fence **child = &fence;
1008 unsigned int nchild = 1;
1011 if (dma_fence_is_array(fence)) {
1012 struct dma_fence_array *array = to_dma_fence_array(fence);
1014 /* XXX Error for signal-on-any fence arrays */
1016 child = array->fences;
1017 nchild = array->num_fences;
1018 GEM_BUG_ON(!nchild);
1023 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
1027 * We don't squash repeated fence dependencies here as we
1028 * want to run our callback in all cases.
1031 if (dma_fence_is_i915(fence))
1032 ret = __i915_request_await_execution(rq,
1037 ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
1048 * i915_request_await_object - set this request to (async) wait upon a bo
1049 * @to: request we are wishing to use
1050 * @obj: object which may be in use on another ring.
1051 * @write: whether the wait is on behalf of a writer
1053 * This code is meant to abstract object synchronization with the GPU.
1054 * Conceptually we serialise writes between engines inside the GPU.
1055 * We only allow one engine to write into a buffer at any time, but
1056 * multiple readers. To ensure each has a coherent view of memory, we must:
1058 * - If there is an outstanding write request to the object, the new
1059 * request must wait for it to complete (either CPU or in hw, requests
1060 * on the same ring will be naturally ordered).
1062 * - If we are a write request (pending_write_domain is set), the new
1063 * request must wait for outstanding read requests to complete.
1065 * Returns 0 if successful, else propagates up the lower layer error.
1068 i915_request_await_object(struct i915_request *to,
1069 struct drm_i915_gem_object *obj,
1072 struct dma_fence *excl;
1076 struct dma_fence **shared;
1077 unsigned int count, i;
1079 ret = reservation_object_get_fences_rcu(obj->resv,
1080 &excl, &count, &shared);
1084 for (i = 0; i < count; i++) {
1085 ret = i915_request_await_dma_fence(to, shared[i]);
1089 dma_fence_put(shared[i]);
1092 for (; i < count; i++)
1093 dma_fence_put(shared[i]);
1096 excl = reservation_object_get_excl_rcu(obj->resv);
1101 ret = i915_request_await_dma_fence(to, excl);
1103 dma_fence_put(excl);
1109 void i915_request_skip(struct i915_request *rq, int error)
1111 void *vaddr = rq->ring->vaddr;
1114 GEM_BUG_ON(!IS_ERR_VALUE((long)error));
1115 dma_fence_set_error(&rq->fence, error);
1118 * As this request likely depends on state from the lost
1119 * context, clear out all the user operations leaving the
1120 * breadcrumb at the end (so we get the fence notifications).
1123 if (rq->postfix < head) {
1124 memset(vaddr + head, 0, rq->ring->size - head);
1127 memset(vaddr + head, 0, rq->postfix - head);
1130 static struct i915_request *
1131 __i915_request_add_to_timeline(struct i915_request *rq)
1133 struct i915_timeline *timeline = rq->timeline;
1134 struct i915_request *prev;
1137 * Dependency tracking and request ordering along the timeline
1138 * is special cased so that we can eliminate redundant ordering
1139 * operations while building the request (we know that the timeline
1140 * itself is ordered, and here we guarantee it).
1142 * As we know we will need to emit tracking along the timeline,
1143 * we embed the hooks into our request struct -- at the cost of
1144 * having to have specialised no-allocation interfaces (which will
1145 * be beneficial elsewhere).
1147 * A second benefit to open-coding i915_request_await_request is
1148 * that we can apply a slight variant of the rules specialised
1149 * for timelines that jump between engines (such as virtual engines).
1150 * If we consider the case of virtual engine, we must emit a dma-fence
1151 * to prevent scheduling of the second request until the first is
1152 * complete (to maximise our greedy late load balancing) and this
1153 * precludes optimising to use semaphores serialisation of a single
1154 * timeline across engines.
1156 prev = rcu_dereference_protected(timeline->last_request.request, 1);
1157 if (prev && !i915_request_completed(prev)) {
1158 if (is_power_of_2(prev->engine->mask | rq->engine->mask))
1159 i915_sw_fence_await_sw_fence(&rq->submit,
1163 __i915_sw_fence_await_dma_fence(&rq->submit,
1166 if (rq->engine->schedule)
1167 __i915_sched_node_add_dependency(&rq->sched,
1173 spin_lock_irq(&timeline->lock);
1174 list_add_tail(&rq->link, &timeline->requests);
1175 spin_unlock_irq(&timeline->lock);
1178 * Make sure that no request gazumped us - if it was allocated after
1179 * our i915_request_alloc() and called __i915_request_add() before
1180 * us, the timeline will hold its seqno which is later than ours.
1182 GEM_BUG_ON(timeline->seqno != rq->fence.seqno);
1183 __i915_active_request_set(&timeline->last_request, rq);
1189 * NB: This function is not allowed to fail. Doing so would mean the the
1190 * request is not being tracked for completion but the work itself is
1191 * going to happen on the hardware. This would be a Bad Thing(tm).
1193 struct i915_request *__i915_request_commit(struct i915_request *rq)
1195 struct intel_engine_cs *engine = rq->engine;
1196 struct intel_ring *ring = rq->ring;
1197 struct i915_request *prev;
1200 GEM_TRACE("%s fence %llx:%lld\n",
1201 engine->name, rq->fence.context, rq->fence.seqno);
1204 * To ensure that this call will not fail, space for its emissions
1205 * should already have been reserved in the ring buffer. Let the ring
1206 * know that it is time to use that space up.
1208 GEM_BUG_ON(rq->reserved_space > ring->space);
1209 rq->reserved_space = 0;
1212 * Record the position of the start of the breadcrumb so that
1213 * should we detect the updated seqno part-way through the
1214 * GPU processing the request, we never over-estimate the
1215 * position of the ring's HEAD.
1217 cs = intel_ring_begin(rq, engine->emit_fini_breadcrumb_dw);
1218 GEM_BUG_ON(IS_ERR(cs));
1219 rq->postfix = intel_ring_offset(rq, cs);
1221 prev = __i915_request_add_to_timeline(rq);
1223 list_add_tail(&rq->ring_link, &ring->request_list);
1224 if (list_is_first(&rq->ring_link, &ring->request_list))
1225 list_add(&ring->active_link, &rq->i915->gt.active_rings);
1226 rq->emitted_jiffies = jiffies;
1229 * Let the backend know a new request has arrived that may need
1230 * to adjust the existing execution schedule due to a high priority
1231 * request - i.e. we may want to preempt the current request in order
1232 * to run a high priority dependency chain *before* we can execute this
1235 * This is called before the request is ready to run so that we can
1236 * decide whether to preempt the entire chain so that it is ready to
1237 * run at the earliest possible convenience.
1240 i915_sw_fence_commit(&rq->semaphore);
1241 rcu_read_lock(); /* RCU serialisation for set-wedged protection */
1242 if (engine->schedule) {
1243 struct i915_sched_attr attr = rq->gem_context->sched;
1246 * Boost actual workloads past semaphores!
1248 * With semaphores we spin on one engine waiting for another,
1249 * simply to reduce the latency of starting our work when
1250 * the signaler completes. However, if there is any other
1251 * work that we could be doing on this engine instead, that
1252 * is better utilisation and will reduce the overall duration
1253 * of the current work. To avoid PI boosting a semaphore
1254 * far in the distance past over useful work, we keep a history
1255 * of any semaphore use along our dependency chain.
1257 if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN))
1258 attr.priority |= I915_PRIORITY_NOSEMAPHORE;
1261 * Boost priorities to new clients (new request flows).
1263 * Allow interactive/synchronous clients to jump ahead of
1264 * the bulk clients. (FQ_CODEL)
1266 if (list_empty(&rq->sched.signalers_list))
1267 attr.priority |= I915_PRIORITY_WAIT;
1269 engine->schedule(rq, &attr);
1272 i915_sw_fence_commit(&rq->submit);
1273 local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
1278 void i915_request_add(struct i915_request *rq)
1280 struct i915_request *prev;
1282 lockdep_assert_held(&rq->timeline->mutex);
1283 lockdep_unpin_lock(&rq->timeline->mutex, rq->cookie);
1285 trace_i915_request_add(rq);
1287 prev = __i915_request_commit(rq);
1290 * In typical scenarios, we do not expect the previous request on
1291 * the timeline to be still tracked by timeline->last_request if it
1292 * has been completed. If the completed request is still here, that
1293 * implies that request retirement is a long way behind submission,
1294 * suggesting that we haven't been retiring frequently enough from
1295 * the combination of retire-before-alloc, waiters and the background
1296 * retirement worker. So if the last request on this timeline was
1297 * already completed, do a catch up pass, flushing the retirement queue
1298 * up to this client. Since we have now moved the heaviest operations
1299 * during retirement onto secondary workers, such as freeing objects
1300 * or contexts, retiring a bunch of requests is mostly list management
1301 * (and cache misses), and so we should not be overly penalizing this
1302 * client by performing excess work, though we may still performing
1303 * work on behalf of others -- but instead we should benefit from
1304 * improved resource management. (Well, that's the theory at least.)
1306 if (prev && i915_request_completed(prev))
1307 i915_request_retire_upto(prev);
1309 mutex_unlock(&rq->timeline->mutex);
1312 static unsigned long local_clock_us(unsigned int *cpu)
1317 * Cheaply and approximately convert from nanoseconds to microseconds.
1318 * The result and subsequent calculations are also defined in the same
1319 * approximate microseconds units. The principal source of timing
1320 * error here is from the simple truncation.
1322 * Note that local_clock() is only defined wrt to the current CPU;
1323 * the comparisons are no longer valid if we switch CPUs. Instead of
1324 * blocking preemption for the entire busywait, we can detect the CPU
1325 * switch and use that as indicator of system load and a reason to
1326 * stop busywaiting, see busywait_stop().
1329 t = local_clock() >> 10;
1335 static bool busywait_stop(unsigned long timeout, unsigned int cpu)
1337 unsigned int this_cpu;
1339 if (time_after(local_clock_us(&this_cpu), timeout))
1342 return this_cpu != cpu;
1345 static bool __i915_spin_request(const struct i915_request * const rq,
1346 int state, unsigned long timeout_us)
1351 * Only wait for the request if we know it is likely to complete.
1353 * We don't track the timestamps around requests, nor the average
1354 * request length, so we do not have a good indicator that this
1355 * request will complete within the timeout. What we do know is the
1356 * order in which requests are executed by the context and so we can
1357 * tell if the request has been started. If the request is not even
1358 * running yet, it is a fair assumption that it will not complete
1359 * within our relatively short timeout.
1361 if (!i915_request_is_running(rq))
1365 * When waiting for high frequency requests, e.g. during synchronous
1366 * rendering split between the CPU and GPU, the finite amount of time
1367 * required to set up the irq and wait upon it limits the response
1368 * rate. By busywaiting on the request completion for a short while we
1369 * can service the high frequency waits as quick as possible. However,
1370 * if it is a slow request, we want to sleep as quickly as possible.
1371 * The tradeoff between waiting and sleeping is roughly the time it
1372 * takes to sleep on a request, on the order of a microsecond.
1375 timeout_us += local_clock_us(&cpu);
1377 if (i915_request_completed(rq))
1380 if (signal_pending_state(state, current))
1383 if (busywait_stop(timeout_us, cpu))
1387 } while (!need_resched());
1392 struct request_wait {
1393 struct dma_fence_cb cb;
1394 struct task_struct *tsk;
1397 static void request_wait_wake(struct dma_fence *fence, struct dma_fence_cb *cb)
1399 struct request_wait *wait = container_of(cb, typeof(*wait), cb);
1401 wake_up_process(wait->tsk);
1405 * i915_request_wait - wait until execution of request has finished
1406 * @rq: the request to wait upon
1407 * @flags: how to wait
1408 * @timeout: how long to wait in jiffies
1410 * i915_request_wait() waits for the request to be completed, for a
1411 * maximum of @timeout jiffies (with MAX_SCHEDULE_TIMEOUT implying an
1414 * If the caller holds the struct_mutex, the caller must pass I915_WAIT_LOCKED
1415 * in via the flags, and vice versa if the struct_mutex is not held, the caller
1416 * must not specify that the wait is locked.
1418 * Returns the remaining time (in jiffies) if the request completed, which may
1419 * be zero or -ETIME if the request is unfinished after the timeout expires.
1420 * May return -EINTR is called with I915_WAIT_INTERRUPTIBLE and a signal is
1421 * pending before the request completes.
1423 long i915_request_wait(struct i915_request *rq,
1427 const int state = flags & I915_WAIT_INTERRUPTIBLE ?
1428 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1429 struct request_wait wait;
1432 GEM_BUG_ON(timeout < 0);
1434 if (i915_request_completed(rq))
1440 trace_i915_request_wait_begin(rq, flags);
1443 * Optimistic spin before touching IRQs.
1445 * We may use a rather large value here to offset the penalty of
1446 * switching away from the active task. Frequently, the client will
1447 * wait upon an old swapbuffer to throttle itself to remain within a
1448 * frame of the gpu. If the client is running in lockstep with the gpu,
1449 * then it should not be waiting long at all, and a sleep now will incur
1450 * extra scheduler latency in producing the next frame. To try to
1451 * avoid adding the cost of enabling/disabling the interrupt to the
1452 * short wait, we first spin to see if the request would have completed
1453 * in the time taken to setup the interrupt.
1455 * We need upto 5us to enable the irq, and upto 20us to hide the
1456 * scheduler latency of a context switch, ignoring the secondary
1457 * impacts from a context switch such as cache eviction.
1459 * The scheme used for low-latency IO is called "hybrid interrupt
1460 * polling". The suggestion there is to sleep until just before you
1461 * expect to be woken by the device interrupt and then poll for its
1462 * completion. That requires having a good predictor for the request
1463 * duration, which we currently lack.
1465 if (CONFIG_DRM_I915_SPIN_REQUEST &&
1466 __i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST))
1470 * This client is about to stall waiting for the GPU. In many cases
1471 * this is undesirable and limits the throughput of the system, as
1472 * many clients cannot continue processing user input/output whilst
1473 * blocked. RPS autotuning may take tens of milliseconds to respond
1474 * to the GPU load and thus incurs additional latency for the client.
1475 * We can circumvent that by promoting the GPU frequency to maximum
1476 * before we sleep. This makes the GPU throttle up much more quickly
1477 * (good for benchmarks and user experience, e.g. window animations),
1478 * but at a cost of spending more power processing the workload
1479 * (bad for battery).
1481 if (flags & I915_WAIT_PRIORITY) {
1482 if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6)
1484 i915_schedule_bump_priority(rq, I915_PRIORITY_WAIT);
1488 if (dma_fence_add_callback(&rq->fence, &wait.cb, request_wait_wake))
1492 set_current_state(state);
1494 if (i915_request_completed(rq))
1497 if (signal_pending_state(state, current)) {
1498 timeout = -ERESTARTSYS;
1507 timeout = io_schedule_timeout(timeout);
1509 __set_current_state(TASK_RUNNING);
1511 dma_fence_remove_callback(&rq->fence, &wait.cb);
1514 trace_i915_request_wait_end(rq);
1518 bool i915_retire_requests(struct drm_i915_private *i915)
1520 struct intel_ring *ring, *tmp;
1522 lockdep_assert_held(&i915->drm.struct_mutex);
1524 list_for_each_entry_safe(ring, tmp,
1525 &i915->gt.active_rings, active_link) {
1526 intel_ring_get(ring); /* last rq holds reference! */
1527 ring_retire_requests(ring);
1528 intel_ring_put(ring);
1531 return !list_empty(&i915->gt.active_rings);
1534 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1535 #include "selftests/mock_request.c"
1536 #include "selftests/i915_request.c"
1539 static void i915_global_request_shrink(void)
1541 kmem_cache_shrink(global.slab_dependencies);
1542 kmem_cache_shrink(global.slab_execute_cbs);
1543 kmem_cache_shrink(global.slab_requests);
1546 static void i915_global_request_exit(void)
1548 kmem_cache_destroy(global.slab_dependencies);
1549 kmem_cache_destroy(global.slab_execute_cbs);
1550 kmem_cache_destroy(global.slab_requests);
1553 static struct i915_global_request global = { {
1554 .shrink = i915_global_request_shrink,
1555 .exit = i915_global_request_exit,
1558 int __init i915_global_request_init(void)
1560 global.slab_requests = KMEM_CACHE(i915_request,
1561 SLAB_HWCACHE_ALIGN |
1562 SLAB_RECLAIM_ACCOUNT |
1563 SLAB_TYPESAFE_BY_RCU);
1564 if (!global.slab_requests)
1567 global.slab_execute_cbs = KMEM_CACHE(execute_cb,
1568 SLAB_HWCACHE_ALIGN |
1569 SLAB_RECLAIM_ACCOUNT |
1570 SLAB_TYPESAFE_BY_RCU);
1571 if (!global.slab_execute_cbs)
1574 global.slab_dependencies = KMEM_CACHE(i915_dependency,
1575 SLAB_HWCACHE_ALIGN |
1576 SLAB_RECLAIM_ACCOUNT);
1577 if (!global.slab_dependencies)
1578 goto err_execute_cbs;
1580 i915_global_register(&global.base);
1584 kmem_cache_destroy(global.slab_execute_cbs);
1586 kmem_cache_destroy(global.slab_requests);