1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * DOC: The i915 register macro definition style guide
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
37 * Keep helper macros near the top. For example, _PIPE() and friends.
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
51 * For single registers, define the register offset first, followed by register
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
123 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
125 #define INVALID_MMIO_REG _MMIO(0)
127 static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
132 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
137 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
142 #define VLV_DISPLAY_BASE 0x180000
143 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
144 #define BXT_MIPI_BASE 0x60000
146 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
149 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
150 * numbers, pick the 0-based __index'th value.
152 * Always prefer this over _PICK() if the numbers are evenly spaced.
154 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
157 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
159 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
161 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
164 * Named helper wrappers around _PICK_EVEN() and _PICK().
166 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
167 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
168 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
169 #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
170 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
172 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
173 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
174 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
175 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
176 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
178 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
180 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
181 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
182 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
185 * Device info offset array based helpers for groups of registers with unevenly
186 * spaced base offsets.
188 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
189 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
190 DISPLAY_MMIO_BASE(dev_priv))
191 #define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
192 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
193 DISPLAY_MMIO_BASE(dev_priv))
194 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
195 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
196 DISPLAY_MMIO_BASE(dev_priv))
198 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
199 #define _MASKED_FIELD(mask, value) ({ \
200 if (__builtin_constant_p(mask)) \
201 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
202 if (__builtin_constant_p(value)) \
203 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
204 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
205 BUILD_BUG_ON_MSG((value) & ~(mask), \
206 "Incorrect value for mask"); \
207 __MASKED_FIELD(mask, value); })
208 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
209 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
224 #define RENDER_CLASS 0
225 #define VIDEO_DECODE_CLASS 1
226 #define VIDEO_ENHANCEMENT_CLASS 2
227 #define COPY_ENGINE_CLASS 3
228 #define OTHER_CLASS 4
229 #define MAX_ENGINE_CLASS 4
231 #define OTHER_GTPM_INSTANCE 1
232 #define MAX_ENGINE_INSTANCE 3
234 /* PCI config space */
236 #define MCHBAR_I915 0x44
237 #define MCHBAR_I965 0x48
238 #define MCHBAR_SIZE (4 * 4096)
241 #define DEVEN_MCHBAR_EN (1 << 28)
243 /* BSM in include/drm/i915_drm.h */
245 #define HPLLCC 0xc0 /* 85x only */
246 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
247 #define GC_CLOCK_133_200 (0 << 0)
248 #define GC_CLOCK_100_200 (1 << 0)
249 #define GC_CLOCK_100_133 (2 << 0)
250 #define GC_CLOCK_133_266 (3 << 0)
251 #define GC_CLOCK_133_200_2 (4 << 0)
252 #define GC_CLOCK_133_266_2 (5 << 0)
253 #define GC_CLOCK_166_266 (6 << 0)
254 #define GC_CLOCK_166_250 (7 << 0)
256 #define I915_GDRST 0xc0 /* PCI config register */
257 #define GRDOM_FULL (0 << 2)
258 #define GRDOM_RENDER (1 << 2)
259 #define GRDOM_MEDIA (3 << 2)
260 #define GRDOM_MASK (3 << 2)
261 #define GRDOM_RESET_STATUS (1 << 1)
262 #define GRDOM_RESET_ENABLE (1 << 0)
264 /* BSpec only has register offset, PCI device and bit found empirically */
265 #define I830_CLOCK_GATE 0xc8 /* device 0 */
266 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
268 #define GCDGMBUS 0xcc
271 #define GCFGC 0xf0 /* 915+ only */
272 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
273 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
274 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
275 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
276 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
277 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
278 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
279 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
280 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
281 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
282 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
283 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
284 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
285 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
286 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
287 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
288 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
289 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
290 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
291 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
292 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
293 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
294 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
295 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
296 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
297 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
298 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
299 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
300 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
306 #define SWSCI_SCISEL (1 << 15)
307 #define SWSCI_GSSCIE (1 << 0)
309 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
312 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
313 #define ILK_GRDOM_FULL (0 << 1)
314 #define ILK_GRDOM_RENDER (1 << 1)
315 #define ILK_GRDOM_MEDIA (3 << 1)
316 #define ILK_GRDOM_MASK (3 << 1)
317 #define ILK_GRDOM_RESET_ENABLE (1 << 0)
319 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
320 #define GEN6_MBC_SNPCR_SHIFT 21
321 #define GEN6_MBC_SNPCR_MASK (3 << 21)
322 #define GEN6_MBC_SNPCR_MAX (0 << 21)
323 #define GEN6_MBC_SNPCR_MED (1 << 21)
324 #define GEN6_MBC_SNPCR_LOW (2 << 21)
325 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
327 #define VLV_G3DCTL _MMIO(0x9024)
328 #define VLV_GSCKGCTL _MMIO(0x9028)
330 #define GEN6_MBCTL _MMIO(0x0907c)
331 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
332 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
333 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
334 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
335 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
337 #define GEN6_GDRST _MMIO(0x941c)
338 #define GEN6_GRDOM_FULL (1 << 0)
339 #define GEN6_GRDOM_RENDER (1 << 1)
340 #define GEN6_GRDOM_MEDIA (1 << 2)
341 #define GEN6_GRDOM_BLT (1 << 3)
342 #define GEN6_GRDOM_VECS (1 << 4)
343 #define GEN9_GRDOM_GUC (1 << 5)
344 #define GEN8_GRDOM_MEDIA2 (1 << 7)
345 /* GEN11 changed all bit defs except for FULL & RENDER */
346 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
347 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
348 #define GEN11_GRDOM_BLT (1 << 2)
349 #define GEN11_GRDOM_GUC (1 << 3)
350 #define GEN11_GRDOM_MEDIA (1 << 5)
351 #define GEN11_GRDOM_MEDIA2 (1 << 6)
352 #define GEN11_GRDOM_MEDIA3 (1 << 7)
353 #define GEN11_GRDOM_MEDIA4 (1 << 8)
354 #define GEN11_GRDOM_VECS (1 << 13)
355 #define GEN11_GRDOM_VECS2 (1 << 14)
356 #define GEN11_GRDOM_SFC0 (1 << 17)
357 #define GEN11_GRDOM_SFC1 (1 << 18)
359 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
360 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
362 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
363 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
364 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
365 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
366 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
368 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
369 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
370 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
371 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
372 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
373 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
375 #define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
376 #define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
377 #define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
378 #define PP_DIR_DCLV_2G 0xffffffff
380 #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
381 #define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
383 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
384 #define GEN8_RPCS_ENABLE (1 << 31)
385 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
386 #define GEN8_RPCS_S_CNT_SHIFT 15
387 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
388 #define GEN11_RPCS_S_CNT_SHIFT 12
389 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
390 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
391 #define GEN8_RPCS_SS_CNT_SHIFT 8
392 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
393 #define GEN8_RPCS_EU_MAX_SHIFT 4
394 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
395 #define GEN8_RPCS_EU_MIN_SHIFT 0
396 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
398 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
400 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
401 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
402 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
403 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
405 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
406 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
407 #define HSW_RCS_INHIBIT (1 << 8)
409 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
410 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
411 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
412 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
413 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
414 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
415 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
416 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
417 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
418 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
420 #define GAM_ECOCHK _MMIO(0x4090)
421 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
422 #define ECOCHK_SNB_BIT (1 << 10)
423 #define ECOCHK_DIS_TLB (1 << 8)
424 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
425 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
426 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
427 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
428 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
429 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
430 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
431 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
433 #define GAC_ECO_BITS _MMIO(0x14090)
434 #define ECOBITS_SNB_BIT (1 << 13)
435 #define ECOBITS_PPGTT_CACHE64B (3 << 8)
436 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
438 #define GAB_CTL _MMIO(0x24000)
439 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
441 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
442 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
443 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
444 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
445 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
446 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
447 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
448 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
449 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
450 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
451 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
452 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
453 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
454 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
455 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
456 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
457 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
458 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
462 #define VGA_ST01_MDA 0x3ba
463 #define VGA_ST01_CGA 0x3da
465 #define _VGA_MSR_WRITE _MMIO(0x3c2)
466 #define VGA_MSR_WRITE 0x3c2
467 #define VGA_MSR_READ 0x3cc
468 #define VGA_MSR_MEM_EN (1 << 1)
469 #define VGA_MSR_CGA_MODE (1 << 0)
471 #define VGA_SR_INDEX 0x3c4
473 #define VGA_SR_DATA 0x3c5
475 #define VGA_AR_INDEX 0x3c0
476 #define VGA_AR_VID_EN (1 << 5)
477 #define VGA_AR_DATA_WRITE 0x3c0
478 #define VGA_AR_DATA_READ 0x3c1
480 #define VGA_GR_INDEX 0x3ce
481 #define VGA_GR_DATA 0x3cf
483 #define VGA_GR_MEM_READ_MODE_SHIFT 3
484 #define VGA_GR_MEM_READ_MODE_PLANE 1
486 #define VGA_GR_MEM_MODE_MASK 0xc
487 #define VGA_GR_MEM_MODE_SHIFT 2
488 #define VGA_GR_MEM_A0000_AFFFF 0
489 #define VGA_GR_MEM_A0000_BFFFF 1
490 #define VGA_GR_MEM_B0000_B7FFF 2
491 #define VGA_GR_MEM_B0000_BFFFF 3
493 #define VGA_DACMASK 0x3c6
494 #define VGA_DACRX 0x3c7
495 #define VGA_DACWX 0x3c8
496 #define VGA_DACDATA 0x3c9
498 #define VGA_CR_INDEX_MDA 0x3b4
499 #define VGA_CR_DATA_MDA 0x3b5
500 #define VGA_CR_INDEX_CGA 0x3d4
501 #define VGA_CR_DATA_CGA 0x3d5
503 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
504 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
505 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
506 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
508 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
509 #define LOWER_SLICE_ENABLED (1 << 0)
510 #define LOWER_SLICE_DISABLED (0 << 0)
513 * Registers used only by the command parser
515 #define BCS_SWCTRL _MMIO(0x22200)
517 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
518 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
519 #define HS_INVOCATION_COUNT _MMIO(0x2300)
520 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
521 #define DS_INVOCATION_COUNT _MMIO(0x2308)
522 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
523 #define IA_VERTICES_COUNT _MMIO(0x2310)
524 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
525 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
526 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
527 #define VS_INVOCATION_COUNT _MMIO(0x2320)
528 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
529 #define GS_INVOCATION_COUNT _MMIO(0x2328)
530 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
531 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
532 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
533 #define CL_INVOCATION_COUNT _MMIO(0x2338)
534 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
535 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
536 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
537 #define PS_INVOCATION_COUNT _MMIO(0x2348)
538 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
539 #define PS_DEPTH_COUNT _MMIO(0x2350)
540 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
542 /* There are the 4 64-bit counter registers, one for each stream output */
543 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
544 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
546 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
547 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
549 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
550 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
551 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
552 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
553 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
554 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
556 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
557 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
558 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
560 /* There are the 16 64-bit CS General Purpose Registers */
561 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
562 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
564 #define GEN7_OACONTROL _MMIO(0x2360)
565 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
566 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
567 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
568 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
569 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
570 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
571 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
572 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
573 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
574 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
575 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
576 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
577 #define GEN7_OACONTROL_FORMAT_SHIFT 2
578 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
579 #define GEN7_OACONTROL_ENABLE (1 << 0)
581 #define GEN8_OACTXID _MMIO(0x2364)
583 #define GEN8_OA_DEBUG _MMIO(0x2B04)
584 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
585 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
586 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
587 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
589 #define GEN8_OACONTROL _MMIO(0x2B00)
590 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
591 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
592 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
593 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
594 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
595 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
596 #define GEN8_OA_COUNTER_ENABLE (1 << 0)
598 #define GEN8_OACTXCONTROL _MMIO(0x2360)
599 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
600 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
601 #define GEN8_OA_TIMER_ENABLE (1 << 1)
602 #define GEN8_OA_COUNTER_RESUME (1 << 0)
604 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
605 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
606 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
607 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
608 #define GEN7_OABUFFER_RESUME (1 << 0)
610 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
611 #define GEN8_OABUFFER _MMIO(0x2b14)
612 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
614 #define GEN7_OASTATUS1 _MMIO(0x2364)
615 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
616 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
617 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
618 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
620 #define GEN7_OASTATUS2 _MMIO(0x2368)
621 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
622 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
624 #define GEN8_OASTATUS _MMIO(0x2b08)
625 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
626 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
627 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
628 #define GEN8_OASTATUS_REPORT_LOST (1 << 0)
630 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
631 #define GEN8_OAHEADPTR_MASK 0xffffffc0
632 #define GEN8_OATAILPTR _MMIO(0x2B10)
633 #define GEN8_OATAILPTR_MASK 0xffffffc0
635 #define OABUFFER_SIZE_128K (0 << 3)
636 #define OABUFFER_SIZE_256K (1 << 3)
637 #define OABUFFER_SIZE_512K (2 << 3)
638 #define OABUFFER_SIZE_1M (3 << 3)
639 #define OABUFFER_SIZE_2M (4 << 3)
640 #define OABUFFER_SIZE_4M (5 << 3)
641 #define OABUFFER_SIZE_8M (6 << 3)
642 #define OABUFFER_SIZE_16M (7 << 3)
645 * Flexible, Aggregate EU Counter Registers.
646 * Note: these aren't contiguous
648 #define EU_PERF_CNTL0 _MMIO(0xe458)
649 #define EU_PERF_CNTL1 _MMIO(0xe558)
650 #define EU_PERF_CNTL2 _MMIO(0xe658)
651 #define EU_PERF_CNTL3 _MMIO(0xe758)
652 #define EU_PERF_CNTL4 _MMIO(0xe45c)
653 #define EU_PERF_CNTL5 _MMIO(0xe55c)
654 #define EU_PERF_CNTL6 _MMIO(0xe65c)
660 #define OASTARTTRIG1 _MMIO(0x2710)
661 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
662 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
664 #define OASTARTTRIG2 _MMIO(0x2714)
665 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
666 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
667 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
668 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
669 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
670 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
671 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
672 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
673 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
674 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
675 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
676 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
677 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
678 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
679 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
680 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
681 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
682 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
683 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
684 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
685 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
686 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
687 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
688 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
689 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
690 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
691 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
692 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
693 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
695 #define OASTARTTRIG3 _MMIO(0x2718)
696 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
697 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
698 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
699 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
700 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
701 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
702 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
703 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
704 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
706 #define OASTARTTRIG4 _MMIO(0x271c)
707 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
708 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
709 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
710 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
711 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
712 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
713 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
714 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
715 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
717 #define OASTARTTRIG5 _MMIO(0x2720)
718 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
719 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
721 #define OASTARTTRIG6 _MMIO(0x2724)
722 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
723 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
724 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
725 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
726 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
727 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
728 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
729 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
730 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
731 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
732 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
733 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
734 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
735 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
736 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
737 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
738 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
739 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
740 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
741 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
742 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
743 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
744 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
745 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
746 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
747 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
748 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
749 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
750 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
752 #define OASTARTTRIG7 _MMIO(0x2728)
753 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
754 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
755 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
756 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
757 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
758 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
759 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
760 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
761 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
763 #define OASTARTTRIG8 _MMIO(0x272c)
764 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
765 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
766 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
767 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
768 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
769 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
770 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
771 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
772 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
774 #define OAREPORTTRIG1 _MMIO(0x2740)
775 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
776 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
778 #define OAREPORTTRIG2 _MMIO(0x2744)
779 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
780 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
781 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
782 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
783 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
784 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
785 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
786 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
787 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
788 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
789 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
790 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
791 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
792 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
793 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
794 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
795 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
796 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
797 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
798 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
799 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
800 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
801 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
802 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
803 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
805 #define OAREPORTTRIG3 _MMIO(0x2748)
806 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
807 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
808 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
809 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
810 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
811 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
812 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
813 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
814 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
816 #define OAREPORTTRIG4 _MMIO(0x274c)
817 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
818 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
819 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
820 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
821 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
822 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
823 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
824 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
825 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
827 #define OAREPORTTRIG5 _MMIO(0x2750)
828 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
829 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
831 #define OAREPORTTRIG6 _MMIO(0x2754)
832 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
833 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
834 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
835 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
836 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
837 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
838 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
839 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
840 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
841 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
842 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
843 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
844 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
845 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
846 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
847 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
848 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
849 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
850 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
851 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
852 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
853 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
854 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
855 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
856 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
858 #define OAREPORTTRIG7 _MMIO(0x2758)
859 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
860 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
861 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
862 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
863 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
864 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
865 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
866 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
867 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
869 #define OAREPORTTRIG8 _MMIO(0x275c)
870 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
871 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
872 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
873 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
874 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
875 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
876 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
877 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
878 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
881 #define OACEC_COMPARE_LESS_OR_EQUAL 6
882 #define OACEC_COMPARE_NOT_EQUAL 5
883 #define OACEC_COMPARE_LESS_THAN 4
884 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
885 #define OACEC_COMPARE_EQUAL 2
886 #define OACEC_COMPARE_GREATER_THAN 1
887 #define OACEC_COMPARE_ANY_EQUAL 0
889 #define OACEC_COMPARE_VALUE_MASK 0xffff
890 #define OACEC_COMPARE_VALUE_SHIFT 3
892 #define OACEC_SELECT_NOA (0 << 19)
893 #define OACEC_SELECT_PREV (1 << 19)
894 #define OACEC_SELECT_BOOLEAN (2 << 19)
897 #define OACEC_MASK_MASK 0xffff
898 #define OACEC_CONSIDERATIONS_MASK 0xffff
899 #define OACEC_CONSIDERATIONS_SHIFT 16
901 #define OACEC0_0 _MMIO(0x2770)
902 #define OACEC0_1 _MMIO(0x2774)
903 #define OACEC1_0 _MMIO(0x2778)
904 #define OACEC1_1 _MMIO(0x277c)
905 #define OACEC2_0 _MMIO(0x2780)
906 #define OACEC2_1 _MMIO(0x2784)
907 #define OACEC3_0 _MMIO(0x2788)
908 #define OACEC3_1 _MMIO(0x278c)
909 #define OACEC4_0 _MMIO(0x2790)
910 #define OACEC4_1 _MMIO(0x2794)
911 #define OACEC5_0 _MMIO(0x2798)
912 #define OACEC5_1 _MMIO(0x279c)
913 #define OACEC6_0 _MMIO(0x27a0)
914 #define OACEC6_1 _MMIO(0x27a4)
915 #define OACEC7_0 _MMIO(0x27a8)
916 #define OACEC7_1 _MMIO(0x27ac)
918 /* OA perf counters */
919 #define OA_PERFCNT1_LO _MMIO(0x91B8)
920 #define OA_PERFCNT1_HI _MMIO(0x91BC)
921 #define OA_PERFCNT2_LO _MMIO(0x91C0)
922 #define OA_PERFCNT2_HI _MMIO(0x91C4)
923 #define OA_PERFCNT3_LO _MMIO(0x91C8)
924 #define OA_PERFCNT3_HI _MMIO(0x91CC)
925 #define OA_PERFCNT4_LO _MMIO(0x91D8)
926 #define OA_PERFCNT4_HI _MMIO(0x91DC)
928 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
929 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
931 /* RPM unit config (Gen8+) */
932 #define RPM_CONFIG0 _MMIO(0x0D00)
933 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
934 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
935 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
936 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
937 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
938 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
939 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
940 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
941 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
942 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
943 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
944 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
946 #define RPM_CONFIG1 _MMIO(0x0D04)
947 #define GEN10_GT_NOA_ENABLE (1 << 9)
949 /* GPM unit config (Gen9+) */
950 #define CTC_MODE _MMIO(0xA26C)
951 #define CTC_SOURCE_PARAMETER_MASK 1
952 #define CTC_SOURCE_CRYSTAL_CLOCK 0
953 #define CTC_SOURCE_DIVIDE_LOGIC 1
954 #define CTC_SHIFT_PARAMETER_SHIFT 1
955 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
957 /* RCP unit config (Gen8+) */
958 #define RCP_CONFIG _MMIO(0x0D08)
961 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
962 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
963 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
964 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
965 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
966 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
967 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
968 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
969 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
970 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
972 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
975 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
977 #define MICRO_BP0_0 _MMIO(0x9800)
978 #define MICRO_BP0_2 _MMIO(0x9804)
979 #define MICRO_BP0_1 _MMIO(0x9808)
981 #define MICRO_BP1_0 _MMIO(0x980C)
982 #define MICRO_BP1_2 _MMIO(0x9810)
983 #define MICRO_BP1_1 _MMIO(0x9814)
985 #define MICRO_BP2_0 _MMIO(0x9818)
986 #define MICRO_BP2_2 _MMIO(0x981C)
987 #define MICRO_BP2_1 _MMIO(0x9820)
989 #define MICRO_BP3_0 _MMIO(0x9824)
990 #define MICRO_BP3_2 _MMIO(0x9828)
991 #define MICRO_BP3_1 _MMIO(0x982C)
993 #define MICRO_BP_TRIGGER _MMIO(0x9830)
994 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
995 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
996 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
998 #define GDT_CHICKEN_BITS _MMIO(0x9840)
999 #define GT_NOA_ENABLE 0x00000080
1001 #define NOA_DATA _MMIO(0x986C)
1002 #define NOA_WRITE _MMIO(0x9888)
1004 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1005 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1006 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1011 #define DEBUG_RESET_I830 _MMIO(0x6070)
1012 #define DEBUG_RESET_FULL (1 << 7)
1013 #define DEBUG_RESET_RENDER (1 << 8)
1014 #define DEBUG_RESET_DISPLAY (1 << 9)
1019 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1020 #define IOSF_DEVFN_SHIFT 24
1021 #define IOSF_OPCODE_SHIFT 16
1022 #define IOSF_PORT_SHIFT 8
1023 #define IOSF_BYTE_ENABLES_SHIFT 4
1024 #define IOSF_BAR_SHIFT 1
1025 #define IOSF_SB_BUSY (1 << 0)
1026 #define IOSF_PORT_BUNIT 0x03
1027 #define IOSF_PORT_PUNIT 0x04
1028 #define IOSF_PORT_NC 0x11
1029 #define IOSF_PORT_DPIO 0x12
1030 #define IOSF_PORT_GPIO_NC 0x13
1031 #define IOSF_PORT_CCK 0x14
1032 #define IOSF_PORT_DPIO_2 0x1a
1033 #define IOSF_PORT_FLISDSI 0x1b
1034 #define IOSF_PORT_GPIO_SC 0x48
1035 #define IOSF_PORT_GPIO_SUS 0xa8
1036 #define IOSF_PORT_CCU 0xa9
1037 #define CHV_IOSF_PORT_GPIO_N 0x13
1038 #define CHV_IOSF_PORT_GPIO_SE 0x48
1039 #define CHV_IOSF_PORT_GPIO_E 0xa8
1040 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1041 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1042 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1044 /* See configdb bunit SB addr map */
1045 #define BUNIT_REG_BISOC 0x11
1047 #define PUNIT_REG_DSPFREQ 0x36
1048 #define DSPFREQSTAT_SHIFT_CHV 24
1049 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1050 #define DSPFREQGUAR_SHIFT_CHV 8
1051 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1052 #define DSPFREQSTAT_SHIFT 30
1053 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1054 #define DSPFREQGUAR_SHIFT 14
1055 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1056 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1057 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1058 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1059 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1060 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1061 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1062 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1063 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1064 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1065 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1066 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1067 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1068 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1069 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1070 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1073 * i915_power_well_id:
1075 * IDs used to look up power wells. Power wells accessed directly bypassing
1076 * the power domains framework must be assigned a unique ID. The rest of power
1077 * wells must be assigned DISP_PW_ID_NONE.
1079 enum i915_power_well_id {
1083 BXT_DISP_PW_DPIO_CMN_A,
1084 VLV_DISP_PW_DPIO_CMN_BC,
1085 GLK_DISP_PW_DPIO_CMN_C,
1086 CHV_DISP_PW_DPIO_CMN_D,
1088 SKL_DISP_PW_MISC_IO,
1093 #define PUNIT_REG_PWRGT_CTRL 0x60
1094 #define PUNIT_REG_PWRGT_STATUS 0x61
1095 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1096 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1097 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1098 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1099 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1101 #define PUNIT_PWGT_IDX_RENDER 0
1102 #define PUNIT_PWGT_IDX_MEDIA 1
1103 #define PUNIT_PWGT_IDX_DISP2D 3
1104 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1105 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1106 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1107 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1108 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1109 #define PUNIT_PWGT_IDX_DPIO_RX0 10
1110 #define PUNIT_PWGT_IDX_DPIO_RX1 11
1111 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1113 #define PUNIT_REG_GPU_LFM 0xd3
1114 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1115 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1116 #define GPLLENABLE (1 << 4)
1117 #define GENFREQSTATUS (1 << 0)
1118 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1119 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1121 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1122 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1124 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1125 #define FB_GFX_FREQ_FUSE_MASK 0xff
1126 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1127 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1128 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1130 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1131 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1133 #define PUNIT_REG_DDR_SETUP2 0x139
1134 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1135 #define FORCE_DDR_LOW_FREQ (1 << 1)
1136 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1138 #define PUNIT_GPU_STATUS_REG 0xdb
1139 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1140 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1141 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1142 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1144 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1145 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1146 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1148 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1149 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1150 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1151 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1152 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1153 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1154 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1155 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1156 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1157 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1159 #define VLV_TURBO_SOC_OVERRIDE 0x04
1160 #define VLV_OVERRIDE_EN 1
1161 #define VLV_SOC_TDP_EN (1 << 1)
1162 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1163 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1165 /* vlv2 north clock has */
1166 #define CCK_FUSE_REG 0x8
1167 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1168 #define CCK_REG_DSI_PLL_FUSE 0x44
1169 #define CCK_REG_DSI_PLL_CONTROL 0x48
1170 #define DSI_PLL_VCO_EN (1 << 31)
1171 #define DSI_PLL_LDO_GATE (1 << 30)
1172 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1173 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1174 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1175 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1176 #define DSI_PLL_MUX_MASK (3 << 9)
1177 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1178 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1179 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1180 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1181 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1182 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1183 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1184 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1185 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1186 #define DSI_PLL_LOCK (1 << 0)
1187 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1188 #define DSI_PLL_LFSR (1 << 31)
1189 #define DSI_PLL_FRACTION_EN (1 << 30)
1190 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1191 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1192 #define DSI_PLL_USYNC_CNT_SHIFT 18
1193 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1194 #define DSI_PLL_N1_DIV_SHIFT 16
1195 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1196 #define DSI_PLL_M1_DIV_SHIFT 0
1197 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1198 #define CCK_CZ_CLOCK_CONTROL 0x62
1199 #define CCK_GPLL_CLOCK_CONTROL 0x67
1200 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1201 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1202 #define CCK_TRUNK_FORCE_ON (1 << 17)
1203 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1204 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1205 #define CCK_FREQUENCY_STATUS_SHIFT 8
1206 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1208 /* DPIO registers */
1209 #define DPIO_DEVFN 0
1211 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1212 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1213 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1214 #define DPIO_SFR_BYPASS (1 << 1)
1215 #define DPIO_CMNRST (1 << 0)
1217 #define DPIO_PHY(pipe) ((pipe) >> 1)
1218 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1221 * Per pipe/PLL DPIO regs
1223 #define _VLV_PLL_DW3_CH0 0x800c
1224 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1225 #define DPIO_POST_DIV_DAC 0
1226 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1227 #define DPIO_POST_DIV_LVDS1 2
1228 #define DPIO_POST_DIV_LVDS2 3
1229 #define DPIO_K_SHIFT (24) /* 4 bits */
1230 #define DPIO_P1_SHIFT (21) /* 3 bits */
1231 #define DPIO_P2_SHIFT (16) /* 5 bits */
1232 #define DPIO_N_SHIFT (12) /* 4 bits */
1233 #define DPIO_ENABLE_CALIBRATION (1 << 11)
1234 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1235 #define DPIO_M2DIV_MASK 0xff
1236 #define _VLV_PLL_DW3_CH1 0x802c
1237 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1239 #define _VLV_PLL_DW5_CH0 0x8014
1240 #define DPIO_REFSEL_OVERRIDE 27
1241 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1242 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1243 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1244 #define DPIO_PLL_REFCLK_SEL_MASK 3
1245 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1246 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1247 #define _VLV_PLL_DW5_CH1 0x8034
1248 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1250 #define _VLV_PLL_DW7_CH0 0x801c
1251 #define _VLV_PLL_DW7_CH1 0x803c
1252 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1254 #define _VLV_PLL_DW8_CH0 0x8040
1255 #define _VLV_PLL_DW8_CH1 0x8060
1256 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1258 #define VLV_PLL_DW9_BCAST 0xc044
1259 #define _VLV_PLL_DW9_CH0 0x8044
1260 #define _VLV_PLL_DW9_CH1 0x8064
1261 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1263 #define _VLV_PLL_DW10_CH0 0x8048
1264 #define _VLV_PLL_DW10_CH1 0x8068
1265 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1267 #define _VLV_PLL_DW11_CH0 0x804c
1268 #define _VLV_PLL_DW11_CH1 0x806c
1269 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1271 /* Spec for ref block start counts at DW10 */
1272 #define VLV_REF_DW13 0x80ac
1274 #define VLV_CMN_DW0 0x8100
1277 * Per DDI channel DPIO regs
1280 #define _VLV_PCS_DW0_CH0 0x8200
1281 #define _VLV_PCS_DW0_CH1 0x8400
1282 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1283 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1284 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1285 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1286 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1288 #define _VLV_PCS01_DW0_CH0 0x200
1289 #define _VLV_PCS23_DW0_CH0 0x400
1290 #define _VLV_PCS01_DW0_CH1 0x2600
1291 #define _VLV_PCS23_DW0_CH1 0x2800
1292 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1293 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1295 #define _VLV_PCS_DW1_CH0 0x8204
1296 #define _VLV_PCS_DW1_CH1 0x8404
1297 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1298 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1299 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1300 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1301 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1302 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1304 #define _VLV_PCS01_DW1_CH0 0x204
1305 #define _VLV_PCS23_DW1_CH0 0x404
1306 #define _VLV_PCS01_DW1_CH1 0x2604
1307 #define _VLV_PCS23_DW1_CH1 0x2804
1308 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1309 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1311 #define _VLV_PCS_DW8_CH0 0x8220
1312 #define _VLV_PCS_DW8_CH1 0x8420
1313 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1314 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1315 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1317 #define _VLV_PCS01_DW8_CH0 0x0220
1318 #define _VLV_PCS23_DW8_CH0 0x0420
1319 #define _VLV_PCS01_DW8_CH1 0x2620
1320 #define _VLV_PCS23_DW8_CH1 0x2820
1321 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1322 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1324 #define _VLV_PCS_DW9_CH0 0x8224
1325 #define _VLV_PCS_DW9_CH1 0x8424
1326 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1327 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1328 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1329 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1330 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1331 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1332 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1334 #define _VLV_PCS01_DW9_CH0 0x224
1335 #define _VLV_PCS23_DW9_CH0 0x424
1336 #define _VLV_PCS01_DW9_CH1 0x2624
1337 #define _VLV_PCS23_DW9_CH1 0x2824
1338 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1339 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1341 #define _CHV_PCS_DW10_CH0 0x8228
1342 #define _CHV_PCS_DW10_CH1 0x8428
1343 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1344 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1345 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1346 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1347 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1348 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1349 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1350 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1351 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1353 #define _VLV_PCS01_DW10_CH0 0x0228
1354 #define _VLV_PCS23_DW10_CH0 0x0428
1355 #define _VLV_PCS01_DW10_CH1 0x2628
1356 #define _VLV_PCS23_DW10_CH1 0x2828
1357 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1358 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1360 #define _VLV_PCS_DW11_CH0 0x822c
1361 #define _VLV_PCS_DW11_CH1 0x842c
1362 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1363 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1364 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1365 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1366 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1368 #define _VLV_PCS01_DW11_CH0 0x022c
1369 #define _VLV_PCS23_DW11_CH0 0x042c
1370 #define _VLV_PCS01_DW11_CH1 0x262c
1371 #define _VLV_PCS23_DW11_CH1 0x282c
1372 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1373 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1375 #define _VLV_PCS01_DW12_CH0 0x0230
1376 #define _VLV_PCS23_DW12_CH0 0x0430
1377 #define _VLV_PCS01_DW12_CH1 0x2630
1378 #define _VLV_PCS23_DW12_CH1 0x2830
1379 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1380 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1382 #define _VLV_PCS_DW12_CH0 0x8230
1383 #define _VLV_PCS_DW12_CH1 0x8430
1384 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1385 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1386 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1387 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1388 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1389 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1391 #define _VLV_PCS_DW14_CH0 0x8238
1392 #define _VLV_PCS_DW14_CH1 0x8438
1393 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1395 #define _VLV_PCS_DW23_CH0 0x825c
1396 #define _VLV_PCS_DW23_CH1 0x845c
1397 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1399 #define _VLV_TX_DW2_CH0 0x8288
1400 #define _VLV_TX_DW2_CH1 0x8488
1401 #define DPIO_SWING_MARGIN000_SHIFT 16
1402 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1403 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1404 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1406 #define _VLV_TX_DW3_CH0 0x828c
1407 #define _VLV_TX_DW3_CH1 0x848c
1408 /* The following bit for CHV phy */
1409 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1410 #define DPIO_SWING_MARGIN101_SHIFT 16
1411 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1412 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1414 #define _VLV_TX_DW4_CH0 0x8290
1415 #define _VLV_TX_DW4_CH1 0x8490
1416 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1417 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1418 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1419 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1420 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1422 #define _VLV_TX3_DW4_CH0 0x690
1423 #define _VLV_TX3_DW4_CH1 0x2a90
1424 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1426 #define _VLV_TX_DW5_CH0 0x8294
1427 #define _VLV_TX_DW5_CH1 0x8494
1428 #define DPIO_TX_OCALINIT_EN (1 << 31)
1429 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1431 #define _VLV_TX_DW11_CH0 0x82ac
1432 #define _VLV_TX_DW11_CH1 0x84ac
1433 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1435 #define _VLV_TX_DW14_CH0 0x82b8
1436 #define _VLV_TX_DW14_CH1 0x84b8
1437 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1439 /* CHV dpPhy registers */
1440 #define _CHV_PLL_DW0_CH0 0x8000
1441 #define _CHV_PLL_DW0_CH1 0x8180
1442 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1444 #define _CHV_PLL_DW1_CH0 0x8004
1445 #define _CHV_PLL_DW1_CH1 0x8184
1446 #define DPIO_CHV_N_DIV_SHIFT 8
1447 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1448 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1450 #define _CHV_PLL_DW2_CH0 0x8008
1451 #define _CHV_PLL_DW2_CH1 0x8188
1452 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1454 #define _CHV_PLL_DW3_CH0 0x800c
1455 #define _CHV_PLL_DW3_CH1 0x818c
1456 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1457 #define DPIO_CHV_FIRST_MOD (0 << 8)
1458 #define DPIO_CHV_SECOND_MOD (1 << 8)
1459 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1460 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1461 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1463 #define _CHV_PLL_DW6_CH0 0x8018
1464 #define _CHV_PLL_DW6_CH1 0x8198
1465 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1466 #define DPIO_CHV_INT_COEFF_SHIFT 8
1467 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1468 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1470 #define _CHV_PLL_DW8_CH0 0x8020
1471 #define _CHV_PLL_DW8_CH1 0x81A0
1472 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1473 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1474 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1476 #define _CHV_PLL_DW9_CH0 0x8024
1477 #define _CHV_PLL_DW9_CH1 0x81A4
1478 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1479 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1480 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1481 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1483 #define _CHV_CMN_DW0_CH0 0x8100
1484 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1485 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1486 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1487 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1489 #define _CHV_CMN_DW5_CH0 0x8114
1490 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1491 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1492 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1493 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1494 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1495 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1496 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1497 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1499 #define _CHV_CMN_DW13_CH0 0x8134
1500 #define _CHV_CMN_DW0_CH1 0x8080
1501 #define DPIO_CHV_S1_DIV_SHIFT 21
1502 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1503 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1504 #define DPIO_CHV_K_DIV_SHIFT 4
1505 #define DPIO_PLL_FREQLOCK (1 << 1)
1506 #define DPIO_PLL_LOCK (1 << 0)
1507 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1509 #define _CHV_CMN_DW14_CH0 0x8138
1510 #define _CHV_CMN_DW1_CH1 0x8084
1511 #define DPIO_AFC_RECAL (1 << 14)
1512 #define DPIO_DCLKP_EN (1 << 13)
1513 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1514 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1515 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1516 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1517 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1518 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1519 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1520 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1521 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1523 #define _CHV_CMN_DW19_CH0 0x814c
1524 #define _CHV_CMN_DW6_CH1 0x8098
1525 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1526 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1527 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1528 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1530 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1532 #define CHV_CMN_DW28 0x8170
1533 #define DPIO_CL1POWERDOWNEN (1 << 23)
1534 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1535 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1536 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1537 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1538 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1540 #define CHV_CMN_DW30 0x8178
1541 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1542 #define DPIO_LRC_BYPASS (1 << 3)
1544 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1545 (lane) * 0x200 + (offset))
1547 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1548 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1549 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1550 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1551 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1552 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1553 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1554 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1555 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1556 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1557 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1558 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1559 #define DPIO_FRC_LATENCY_SHFIT 8
1560 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1561 #define DPIO_UPAR_SHIFT 30
1563 /* BXT PHY registers */
1564 #define _BXT_PHY0_BASE 0x6C000
1565 #define _BXT_PHY1_BASE 0x162000
1566 #define _BXT_PHY2_BASE 0x163000
1567 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1571 #define _BXT_PHY(phy, reg) \
1572 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1574 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1575 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1576 (reg_ch1) - _BXT_PHY0_BASE))
1577 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1578 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1580 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1581 #define MIPIO_RST_CTRL (1 << 2)
1583 #define _BXT_PHY_CTL_DDI_A 0x64C00
1584 #define _BXT_PHY_CTL_DDI_B 0x64C10
1585 #define _BXT_PHY_CTL_DDI_C 0x64C20
1586 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1587 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1588 #define BXT_PHY_LANE_ENABLED (1 << 8)
1589 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1592 #define _PHY_CTL_FAMILY_EDP 0x64C80
1593 #define _PHY_CTL_FAMILY_DDI 0x64C90
1594 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1595 #define COMMON_RESET_DIS (1 << 31)
1596 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1597 _PHY_CTL_FAMILY_EDP, \
1598 _PHY_CTL_FAMILY_DDI_C)
1600 /* BXT PHY PLL registers */
1601 #define _PORT_PLL_A 0x46074
1602 #define _PORT_PLL_B 0x46078
1603 #define _PORT_PLL_C 0x4607c
1604 #define PORT_PLL_ENABLE (1 << 31)
1605 #define PORT_PLL_LOCK (1 << 30)
1606 #define PORT_PLL_REF_SEL (1 << 27)
1607 #define PORT_PLL_POWER_ENABLE (1 << 26)
1608 #define PORT_PLL_POWER_STATE (1 << 25)
1609 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1611 #define _PORT_PLL_EBB_0_A 0x162034
1612 #define _PORT_PLL_EBB_0_B 0x6C034
1613 #define _PORT_PLL_EBB_0_C 0x6C340
1614 #define PORT_PLL_P1_SHIFT 13
1615 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1616 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1617 #define PORT_PLL_P2_SHIFT 8
1618 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1619 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1620 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1621 _PORT_PLL_EBB_0_B, \
1624 #define _PORT_PLL_EBB_4_A 0x162038
1625 #define _PORT_PLL_EBB_4_B 0x6C038
1626 #define _PORT_PLL_EBB_4_C 0x6C344
1627 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1628 #define PORT_PLL_RECALIBRATE (1 << 14)
1629 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1630 _PORT_PLL_EBB_4_B, \
1633 #define _PORT_PLL_0_A 0x162100
1634 #define _PORT_PLL_0_B 0x6C100
1635 #define _PORT_PLL_0_C 0x6C380
1637 #define PORT_PLL_M2_MASK 0xFF
1639 #define PORT_PLL_N_SHIFT 8
1640 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1641 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1643 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1645 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1647 #define PORT_PLL_PROP_COEFF_MASK 0xF
1648 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1649 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1650 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1651 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1653 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1655 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1656 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1658 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1659 #define PORT_PLL_DCO_AMP_DEFAULT 15
1660 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1661 #define PORT_PLL_DCO_AMP(x) ((x) << 10)
1662 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1665 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1668 /* BXT PHY common lane registers */
1669 #define _PORT_CL1CM_DW0_A 0x162000
1670 #define _PORT_CL1CM_DW0_BC 0x6C000
1671 #define PHY_POWER_GOOD (1 << 16)
1672 #define PHY_RESERVED (1 << 7)
1673 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1675 #define _PORT_CL1CM_DW9_A 0x162024
1676 #define _PORT_CL1CM_DW9_BC 0x6C024
1677 #define IREF0RC_OFFSET_SHIFT 8
1678 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1679 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1681 #define _PORT_CL1CM_DW10_A 0x162028
1682 #define _PORT_CL1CM_DW10_BC 0x6C028
1683 #define IREF1RC_OFFSET_SHIFT 8
1684 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1685 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1687 #define _PORT_CL1CM_DW28_A 0x162070
1688 #define _PORT_CL1CM_DW28_BC 0x6C070
1689 #define OCL1_POWER_DOWN_EN (1 << 23)
1690 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1691 #define SUS_CLK_CONFIG 0x3
1692 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1694 #define _PORT_CL1CM_DW30_A 0x162078
1695 #define _PORT_CL1CM_DW30_BC 0x6C078
1696 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1697 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1700 * CNL/ICL Port/COMBO-PHY Registers
1702 #define _ICL_COMBOPHY_A 0x162000
1703 #define _ICL_COMBOPHY_B 0x6C000
1704 #define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
1707 /* CNL/ICL Port CL_DW registers */
1708 #define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
1711 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1712 #define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
1713 #define CL_POWER_DOWN_ENABLE (1 << 4)
1714 #define SUS_CLOCK_CONFIG (3 << 0)
1716 #define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
1717 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1718 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1719 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1720 #define PWR_UP_ALL_LANES (0x0 << 4)
1721 #define PWR_DOWN_LN_3_2_1 (0xe << 4)
1722 #define PWR_DOWN_LN_3_2 (0xc << 4)
1723 #define PWR_DOWN_LN_3 (0x8 << 4)
1724 #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1725 #define PWR_DOWN_LN_1_0 (0x3 << 4)
1726 #define PWR_DOWN_LN_1 (0x2 << 4)
1727 #define PWR_DOWN_LN_3_1 (0xa << 4)
1728 #define PWR_DOWN_LN_3_1_0 (0xb << 4)
1729 #define PWR_DOWN_LN_MASK (0xf << 4)
1730 #define PWR_DOWN_LN_SHIFT 4
1732 #define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
1733 #define ICL_LANE_ENABLE_AUX (1 << 0)
1735 /* CNL/ICL Port COMP_DW registers */
1736 #define _ICL_PORT_COMP 0x100
1737 #define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
1738 _ICL_PORT_COMP + 4 * (dw))
1740 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1741 #define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
1742 #define COMP_INIT (1 << 31)
1744 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1745 #define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
1747 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1748 #define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
1749 #define PROCESS_INFO_DOT_0 (0 << 26)
1750 #define PROCESS_INFO_DOT_1 (1 << 26)
1751 #define PROCESS_INFO_DOT_4 (2 << 26)
1752 #define PROCESS_INFO_MASK (7 << 26)
1753 #define PROCESS_INFO_SHIFT 26
1754 #define VOLTAGE_INFO_0_85V (0 << 24)
1755 #define VOLTAGE_INFO_0_95V (1 << 24)
1756 #define VOLTAGE_INFO_1_05V (2 << 24)
1757 #define VOLTAGE_INFO_MASK (3 << 24)
1758 #define VOLTAGE_INFO_SHIFT 24
1760 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1761 #define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
1763 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1764 #define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
1766 /* CNL/ICL Port PCS registers */
1767 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1768 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1769 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1770 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1771 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1772 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1773 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1774 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1775 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1776 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1777 #define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
1778 _CNL_PORT_PCS_DW1_GRP_AE, \
1779 _CNL_PORT_PCS_DW1_GRP_B, \
1780 _CNL_PORT_PCS_DW1_GRP_C, \
1781 _CNL_PORT_PCS_DW1_GRP_D, \
1782 _CNL_PORT_PCS_DW1_GRP_AE, \
1783 _CNL_PORT_PCS_DW1_GRP_F))
1784 #define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
1785 _CNL_PORT_PCS_DW1_LN0_AE, \
1786 _CNL_PORT_PCS_DW1_LN0_B, \
1787 _CNL_PORT_PCS_DW1_LN0_C, \
1788 _CNL_PORT_PCS_DW1_LN0_D, \
1789 _CNL_PORT_PCS_DW1_LN0_AE, \
1790 _CNL_PORT_PCS_DW1_LN0_F))
1792 #define _ICL_PORT_PCS_AUX 0x300
1793 #define _ICL_PORT_PCS_GRP 0x600
1794 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1795 #define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1796 _ICL_PORT_PCS_AUX + 4 * (dw))
1797 #define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1798 _ICL_PORT_PCS_GRP + 4 * (dw))
1799 #define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1800 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1801 #define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
1802 #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
1803 #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
1804 #define COMMON_KEEPER_EN (1 << 26)
1806 /* CNL/ICL Port TX registers */
1807 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1808 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1809 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1810 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1811 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1812 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1813 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1814 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1815 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1816 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
1817 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
1818 _CNL_PORT_TX_AE_GRP_OFFSET, \
1819 _CNL_PORT_TX_B_GRP_OFFSET, \
1820 _CNL_PORT_TX_B_GRP_OFFSET, \
1821 _CNL_PORT_TX_D_GRP_OFFSET, \
1822 _CNL_PORT_TX_AE_GRP_OFFSET, \
1823 _CNL_PORT_TX_F_GRP_OFFSET) + \
1825 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
1826 _CNL_PORT_TX_AE_LN0_OFFSET, \
1827 _CNL_PORT_TX_B_LN0_OFFSET, \
1828 _CNL_PORT_TX_B_LN0_OFFSET, \
1829 _CNL_PORT_TX_D_LN0_OFFSET, \
1830 _CNL_PORT_TX_AE_LN0_OFFSET, \
1831 _CNL_PORT_TX_F_LN0_OFFSET) + \
1834 #define _ICL_PORT_TX_AUX 0x380
1835 #define _ICL_PORT_TX_GRP 0x680
1836 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
1838 #define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1839 _ICL_PORT_TX_AUX + 4 * (dw))
1840 #define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1841 _ICL_PORT_TX_GRP + 4 * (dw))
1842 #define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1843 _ICL_PORT_TX_LN(ln) + 4 * (dw))
1845 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1846 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1847 #define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
1848 #define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
1849 #define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
1850 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
1851 #define SWING_SEL_UPPER_MASK (1 << 15)
1852 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
1853 #define SWING_SEL_LOWER_MASK (0x7 << 11)
1854 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
1855 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
1856 #define RCOMP_SCALAR(x) ((x) << 0)
1857 #define RCOMP_SCALAR_MASK (0xFF << 0)
1859 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
1860 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
1861 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
1862 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
1863 #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
1864 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
1865 _CNL_PORT_TX_DW4_LN0_AE)))
1866 #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
1867 #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
1868 #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
1869 #define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
1870 #define LOADGEN_SELECT (1 << 31)
1871 #define POST_CURSOR_1(x) ((x) << 12)
1872 #define POST_CURSOR_1_MASK (0x3F << 12)
1873 #define POST_CURSOR_2(x) ((x) << 6)
1874 #define POST_CURSOR_2_MASK (0x3F << 6)
1875 #define CURSOR_COEFF(x) ((x) << 0)
1876 #define CURSOR_COEFF_MASK (0x3F << 0)
1878 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1879 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1880 #define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
1881 #define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
1882 #define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
1883 #define TX_TRAINING_EN (1 << 31)
1884 #define TAP2_DISABLE (1 << 30)
1885 #define TAP3_DISABLE (1 << 29)
1886 #define SCALING_MODE_SEL(x) ((x) << 18)
1887 #define SCALING_MODE_SEL_MASK (0x7 << 18)
1888 #define RTERM_SELECT(x) ((x) << 3)
1889 #define RTERM_SELECT_MASK (0x7 << 3)
1891 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
1892 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
1893 #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
1894 #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
1895 #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
1896 #define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
1897 #define N_SCALAR(x) ((x) << 24)
1898 #define N_SCALAR_MASK (0x7F << 24)
1900 #define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
1901 _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
1903 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
1904 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
1905 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
1906 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
1907 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
1908 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
1909 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
1910 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
1911 #define MG_TX1_LINK_PARAMS(port, ln) \
1912 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
1913 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
1914 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
1916 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
1917 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
1918 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
1919 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
1920 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
1921 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
1922 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
1923 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
1924 #define MG_TX2_LINK_PARAMS(port, ln) \
1925 MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
1926 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
1927 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
1928 #define CRI_USE_FS32 (1 << 5)
1930 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
1931 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
1932 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
1933 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
1934 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
1935 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
1936 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
1937 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
1938 #define MG_TX1_PISO_READLOAD(port, ln) \
1939 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
1940 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
1941 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
1943 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
1944 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
1945 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
1946 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
1947 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
1948 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
1949 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
1950 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
1951 #define MG_TX2_PISO_READLOAD(port, ln) \
1952 MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
1953 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
1954 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
1955 #define CRI_CALCINIT (1 << 1)
1957 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
1958 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
1959 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
1960 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
1961 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
1962 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
1963 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
1964 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
1965 #define MG_TX1_SWINGCTRL(port, ln) \
1966 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
1967 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
1968 MG_TX_SWINGCTRL_TX1LN1_PORT1)
1970 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
1971 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
1972 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
1973 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
1974 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
1975 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
1976 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
1977 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
1978 #define MG_TX2_SWINGCTRL(port, ln) \
1979 MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
1980 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
1981 MG_TX_SWINGCTRL_TX2LN1_PORT1)
1982 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
1983 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
1985 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
1986 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
1987 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
1988 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
1989 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
1990 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
1991 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
1992 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
1993 #define MG_TX1_DRVCTRL(port, ln) \
1994 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
1995 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
1996 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
1998 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
1999 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2000 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2001 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2002 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2003 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2004 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2005 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2006 #define MG_TX2_DRVCTRL(port, ln) \
2007 MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2008 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2009 MG_TX_DRVCTRL_TX2LN1_PORT1)
2010 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2011 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2012 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2013 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2014 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2015 #define CRI_LOADGEN_SEL(x) ((x) << 12)
2016 #define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2018 #define MG_CLKHUB_LN0_PORT1 0x16839C
2019 #define MG_CLKHUB_LN1_PORT1 0x16879C
2020 #define MG_CLKHUB_LN0_PORT2 0x16939C
2021 #define MG_CLKHUB_LN1_PORT2 0x16979C
2022 #define MG_CLKHUB_LN0_PORT3 0x16A39C
2023 #define MG_CLKHUB_LN1_PORT3 0x16A79C
2024 #define MG_CLKHUB_LN0_PORT4 0x16B39C
2025 #define MG_CLKHUB_LN1_PORT4 0x16B79C
2026 #define MG_CLKHUB(port, ln) \
2027 MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
2028 MG_CLKHUB_LN0_PORT2, \
2029 MG_CLKHUB_LN1_PORT1)
2030 #define CFG_LOW_RATE_LKREN_EN (1 << 11)
2032 #define MG_TX_DCC_TX1LN0_PORT1 0x168110
2033 #define MG_TX_DCC_TX1LN1_PORT1 0x168510
2034 #define MG_TX_DCC_TX1LN0_PORT2 0x169110
2035 #define MG_TX_DCC_TX1LN1_PORT2 0x169510
2036 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2037 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2038 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2039 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2040 #define MG_TX1_DCC(port, ln) \
2041 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
2042 MG_TX_DCC_TX1LN0_PORT2, \
2043 MG_TX_DCC_TX1LN1_PORT1)
2044 #define MG_TX_DCC_TX2LN0_PORT1 0x168090
2045 #define MG_TX_DCC_TX2LN1_PORT1 0x168490
2046 #define MG_TX_DCC_TX2LN0_PORT2 0x169090
2047 #define MG_TX_DCC_TX2LN1_PORT2 0x169490
2048 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2049 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2050 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2051 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2052 #define MG_TX2_DCC(port, ln) \
2053 MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
2054 MG_TX_DCC_TX2LN0_PORT2, \
2055 MG_TX_DCC_TX2LN1_PORT1)
2056 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2057 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2058 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2060 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2061 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2062 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2063 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2064 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2065 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2066 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2067 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2068 #define MG_DP_MODE(port, ln) \
2069 MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
2070 MG_DP_MODE_LN0_ACU_PORT2, \
2071 MG_DP_MODE_LN1_ACU_PORT1)
2072 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2073 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2074 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5)
2075 #define MG_DP_MODE_CFG_TRPWR_GATING (1 << 4)
2076 #define MG_DP_MODE_CFG_CLNPWR_GATING (1 << 3)
2077 #define MG_DP_MODE_CFG_DIGPWR_GATING (1 << 2)
2078 #define MG_DP_MODE_CFG_GAONPWR_GATING (1 << 1)
2080 #define MG_MISC_SUS0_PORT1 0x168814
2081 #define MG_MISC_SUS0_PORT2 0x169814
2082 #define MG_MISC_SUS0_PORT3 0x16A814
2083 #define MG_MISC_SUS0_PORT4 0x16B814
2084 #define MG_MISC_SUS0(tc_port) \
2085 _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
2086 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK (3 << 14)
2087 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14)
2088 #define MG_MISC_SUS0_CFG_TR2PWR_GATING (1 << 12)
2089 #define MG_MISC_SUS0_CFG_CL2PWR_GATING (1 << 11)
2090 #define MG_MISC_SUS0_CFG_GAONPWR_GATING (1 << 10)
2091 #define MG_MISC_SUS0_CFG_TRPWR_GATING (1 << 7)
2092 #define MG_MISC_SUS0_CFG_CL1PWR_GATING (1 << 6)
2093 #define MG_MISC_SUS0_CFG_DGPWR_GATING (1 << 5)
2095 /* The spec defines this only for BXT PHY0, but lets assume that this
2096 * would exist for PHY1 too if it had a second channel.
2098 #define _PORT_CL2CM_DW6_A 0x162358
2099 #define _PORT_CL2CM_DW6_BC 0x6C358
2100 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2101 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2103 #define FIA1_BASE 0x163000
2105 /* ICL PHY DFLEX registers */
2106 #define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
2107 #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2108 #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2109 #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2110 #define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2111 #define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2112 #define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2114 /* BXT PHY Ref registers */
2115 #define _PORT_REF_DW3_A 0x16218C
2116 #define _PORT_REF_DW3_BC 0x6C18C
2117 #define GRC_DONE (1 << 22)
2118 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2120 #define _PORT_REF_DW6_A 0x162198
2121 #define _PORT_REF_DW6_BC 0x6C198
2122 #define GRC_CODE_SHIFT 24
2123 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2124 #define GRC_CODE_FAST_SHIFT 16
2125 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2126 #define GRC_CODE_SLOW_SHIFT 8
2127 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2128 #define GRC_CODE_NOM_MASK 0xFF
2129 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2131 #define _PORT_REF_DW8_A 0x1621A0
2132 #define _PORT_REF_DW8_BC 0x6C1A0
2133 #define GRC_DIS (1 << 15)
2134 #define GRC_RDY_OVRD (1 << 1)
2135 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2137 /* BXT PHY PCS registers */
2138 #define _PORT_PCS_DW10_LN01_A 0x162428
2139 #define _PORT_PCS_DW10_LN01_B 0x6C428
2140 #define _PORT_PCS_DW10_LN01_C 0x6C828
2141 #define _PORT_PCS_DW10_GRP_A 0x162C28
2142 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2143 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2144 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2145 _PORT_PCS_DW10_LN01_B, \
2146 _PORT_PCS_DW10_LN01_C)
2147 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2148 _PORT_PCS_DW10_GRP_B, \
2149 _PORT_PCS_DW10_GRP_C)
2151 #define TX2_SWING_CALC_INIT (1 << 31)
2152 #define TX1_SWING_CALC_INIT (1 << 30)
2154 #define _PORT_PCS_DW12_LN01_A 0x162430
2155 #define _PORT_PCS_DW12_LN01_B 0x6C430
2156 #define _PORT_PCS_DW12_LN01_C 0x6C830
2157 #define _PORT_PCS_DW12_LN23_A 0x162630
2158 #define _PORT_PCS_DW12_LN23_B 0x6C630
2159 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2160 #define _PORT_PCS_DW12_GRP_A 0x162c30
2161 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2162 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2163 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2164 #define LANE_STAGGER_MASK 0x1F
2165 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2166 _PORT_PCS_DW12_LN01_B, \
2167 _PORT_PCS_DW12_LN01_C)
2168 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2169 _PORT_PCS_DW12_LN23_B, \
2170 _PORT_PCS_DW12_LN23_C)
2171 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2172 _PORT_PCS_DW12_GRP_B, \
2173 _PORT_PCS_DW12_GRP_C)
2175 /* BXT PHY TX registers */
2176 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2177 ((lane) & 1) * 0x80)
2179 #define _PORT_TX_DW2_LN0_A 0x162508
2180 #define _PORT_TX_DW2_LN0_B 0x6C508
2181 #define _PORT_TX_DW2_LN0_C 0x6C908
2182 #define _PORT_TX_DW2_GRP_A 0x162D08
2183 #define _PORT_TX_DW2_GRP_B 0x6CD08
2184 #define _PORT_TX_DW2_GRP_C 0x6CF08
2185 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2186 _PORT_TX_DW2_LN0_B, \
2188 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2189 _PORT_TX_DW2_GRP_B, \
2191 #define MARGIN_000_SHIFT 16
2192 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2193 #define UNIQ_TRANS_SCALE_SHIFT 8
2194 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2196 #define _PORT_TX_DW3_LN0_A 0x16250C
2197 #define _PORT_TX_DW3_LN0_B 0x6C50C
2198 #define _PORT_TX_DW3_LN0_C 0x6C90C
2199 #define _PORT_TX_DW3_GRP_A 0x162D0C
2200 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2201 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2202 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2203 _PORT_TX_DW3_LN0_B, \
2205 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2206 _PORT_TX_DW3_GRP_B, \
2208 #define SCALE_DCOMP_METHOD (1 << 26)
2209 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2211 #define _PORT_TX_DW4_LN0_A 0x162510
2212 #define _PORT_TX_DW4_LN0_B 0x6C510
2213 #define _PORT_TX_DW4_LN0_C 0x6C910
2214 #define _PORT_TX_DW4_GRP_A 0x162D10
2215 #define _PORT_TX_DW4_GRP_B 0x6CD10
2216 #define _PORT_TX_DW4_GRP_C 0x6CF10
2217 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2218 _PORT_TX_DW4_LN0_B, \
2220 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2221 _PORT_TX_DW4_GRP_B, \
2223 #define DEEMPH_SHIFT 24
2224 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2226 #define _PORT_TX_DW5_LN0_A 0x162514
2227 #define _PORT_TX_DW5_LN0_B 0x6C514
2228 #define _PORT_TX_DW5_LN0_C 0x6C914
2229 #define _PORT_TX_DW5_GRP_A 0x162D14
2230 #define _PORT_TX_DW5_GRP_B 0x6CD14
2231 #define _PORT_TX_DW5_GRP_C 0x6CF14
2232 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2233 _PORT_TX_DW5_LN0_B, \
2235 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2236 _PORT_TX_DW5_GRP_B, \
2238 #define DCC_DELAY_RANGE_1 (1 << 9)
2239 #define DCC_DELAY_RANGE_2 (1 << 8)
2241 #define _PORT_TX_DW14_LN0_A 0x162538
2242 #define _PORT_TX_DW14_LN0_B 0x6C538
2243 #define _PORT_TX_DW14_LN0_C 0x6C938
2244 #define LATENCY_OPTIM_SHIFT 30
2245 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2246 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2247 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2248 _PORT_TX_DW14_LN0_C) + \
2249 _BXT_LANE_OFFSET(lane))
2251 /* UAIMI scratch pad register 1 */
2252 #define UAIMI_SPR1 _MMIO(0x4F074)
2253 /* SKL VccIO mask */
2254 #define SKL_VCCIO_MASK 0x1
2255 /* SKL balance leg register */
2256 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2257 /* I_boost values */
2258 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2259 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2260 /* Balance leg disable bits */
2261 #define BALANCE_LEG_DISABLE_SHIFT 23
2262 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2266 * [0-7] @ 0x2000 gen2,gen3
2267 * [8-15] @ 0x3000 945,g33,pnv
2269 * [0-15] @ 0x3000 gen4,gen5
2271 * [0-15] @ 0x100000 gen6,vlv,chv
2272 * [0-31] @ 0x100000 gen7+
2274 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2275 #define I830_FENCE_START_MASK 0x07f80000
2276 #define I830_FENCE_TILING_Y_SHIFT 12
2277 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2278 #define I830_FENCE_PITCH_SHIFT 4
2279 #define I830_FENCE_REG_VALID (1 << 0)
2280 #define I915_FENCE_MAX_PITCH_VAL 4
2281 #define I830_FENCE_MAX_PITCH_VAL 6
2282 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2284 #define I915_FENCE_START_MASK 0x0ff00000
2285 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2287 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2288 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2289 #define I965_FENCE_PITCH_SHIFT 2
2290 #define I965_FENCE_TILING_Y_SHIFT 1
2291 #define I965_FENCE_REG_VALID (1 << 0)
2292 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2294 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2295 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2296 #define GEN6_FENCE_PITCH_SHIFT 32
2297 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2300 /* control register for cpu gtt access */
2301 #define TILECTL _MMIO(0x101000)
2302 #define TILECTL_SWZCTL (1 << 0)
2303 #define TILECTL_TLBPF (1 << 1)
2304 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2305 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2308 * Instruction and interrupt control regs
2310 #define PGTBL_CTL _MMIO(0x02020)
2311 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2312 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2313 #define PGTBL_ER _MMIO(0x02024)
2314 #define PRB0_BASE (0x2030 - 0x30)
2315 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2316 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2317 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2318 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2319 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2320 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2321 #define RENDER_RING_BASE 0x02000
2322 #define BSD_RING_BASE 0x04000
2323 #define GEN6_BSD_RING_BASE 0x12000
2324 #define GEN8_BSD2_RING_BASE 0x1c000
2325 #define GEN11_BSD_RING_BASE 0x1c0000
2326 #define GEN11_BSD2_RING_BASE 0x1c4000
2327 #define GEN11_BSD3_RING_BASE 0x1d0000
2328 #define GEN11_BSD4_RING_BASE 0x1d4000
2329 #define VEBOX_RING_BASE 0x1a000
2330 #define GEN11_VEBOX_RING_BASE 0x1c8000
2331 #define GEN11_VEBOX2_RING_BASE 0x1d8000
2332 #define BLT_RING_BASE 0x22000
2333 #define RING_TAIL(base) _MMIO((base) + 0x30)
2334 #define RING_HEAD(base) _MMIO((base) + 0x34)
2335 #define RING_START(base) _MMIO((base) + 0x38)
2336 #define RING_CTL(base) _MMIO((base) + 0x3c)
2337 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2338 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
2339 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
2340 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
2341 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2342 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2343 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2344 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2345 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2346 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2347 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2348 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2349 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2350 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2351 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2352 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2353 #define GEN6_NOSYNC INVALID_MMIO_REG
2354 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2355 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2356 #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2357 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2358 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2359 #define RESET_CTL_REQUEST_RESET (1 << 0)
2360 #define RESET_CTL_READY_TO_RESET (1 << 1)
2361 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2363 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2364 #define GTT_CACHE_EN_ALL 0xF0007FFF
2365 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2366 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2367 #define ARB_MODE _MMIO(0x4030)
2368 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
2369 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
2370 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2371 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2372 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2373 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2374 #define GEN7_LRA_LIMITS_REG_NUM 13
2375 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2376 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2378 #define GAMTARBMODE _MMIO(0x04a08)
2379 #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2380 #define ARB_MODE_SWIZZLE_BDW (1 << 1)
2381 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2382 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2383 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2384 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2385 #define RING_FAULT_GTTSEL_MASK (1 << 11)
2386 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2387 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2388 #define RING_FAULT_VALID (1 << 0)
2389 #define DONE_REG _MMIO(0x40b0)
2390 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2391 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2392 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2393 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2394 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2395 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2396 #define RING_ACTHD(base) _MMIO((base) + 0x74)
2397 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2398 #define RING_NOPID(base) _MMIO((base) + 0x94)
2399 #define RING_IMR(base) _MMIO((base) + 0xa8)
2400 #define RING_HWSTAM(base) _MMIO((base) + 0x98)
2401 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2402 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2403 #define TAIL_ADDR 0x001FFFF8
2404 #define HEAD_WRAP_COUNT 0xFFE00000
2405 #define HEAD_WRAP_ONE 0x00200000
2406 #define HEAD_ADDR 0x001FFFFC
2407 #define RING_NR_PAGES 0x001FF000
2408 #define RING_REPORT_MASK 0x00000006
2409 #define RING_REPORT_64K 0x00000002
2410 #define RING_REPORT_128K 0x00000004
2411 #define RING_NO_REPORT 0x00000000
2412 #define RING_VALID_MASK 0x00000001
2413 #define RING_VALID 0x00000001
2414 #define RING_INVALID 0x00000000
2415 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2416 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2417 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2419 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2420 #define RING_MAX_NONPRIV_SLOTS 12
2422 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2424 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2425 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2427 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2428 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2429 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2431 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2432 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2433 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2434 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2437 #define PRB0_TAIL _MMIO(0x2030)
2438 #define PRB0_HEAD _MMIO(0x2034)
2439 #define PRB0_START _MMIO(0x2038)
2440 #define PRB0_CTL _MMIO(0x203c)
2441 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2442 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2443 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2444 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2446 #define IPEIR_I965 _MMIO(0x2064)
2447 #define IPEHR_I965 _MMIO(0x2068)
2448 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2449 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2450 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2451 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2452 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2453 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2454 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2455 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2456 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2457 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2458 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2459 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2460 #define RING_IPEIR(base) _MMIO((base) + 0x64)
2461 #define RING_IPEHR(base) _MMIO((base) + 0x68)
2463 * On GEN4, only the render ring INSTDONE exists and has a different
2464 * layout than the GEN7+ version.
2465 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2467 #define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2468 #define RING_INSTPS(base) _MMIO((base) + 0x70)
2469 #define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2470 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2471 #define RING_INSTPM(base) _MMIO((base) + 0xc0)
2472 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2473 #define INSTPS _MMIO(0x2070) /* 965+ only */
2474 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2475 #define ACTHD_I965 _MMIO(0x2074)
2476 #define HWS_PGA _MMIO(0x2080)
2477 #define HWS_ADDRESS_MASK 0xfffff000
2478 #define HWS_START_ADDRESS_SHIFT 4
2479 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2480 #define PWRCTX_EN (1 << 0)
2481 #define IPEIR _MMIO(0x2088)
2482 #define IPEHR _MMIO(0x208c)
2483 #define GEN2_INSTDONE _MMIO(0x2090)
2484 #define NOPID _MMIO(0x2094)
2485 #define HWSTAM _MMIO(0x2098)
2486 #define DMA_FADD_I8XX _MMIO(0x20d0)
2487 #define RING_BBSTATE(base) _MMIO((base) + 0x110)
2488 #define RING_BB_PPGTT (1 << 5)
2489 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2490 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2491 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2492 #define RING_BBADDR(base) _MMIO((base) + 0x140)
2493 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2494 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2495 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2496 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2497 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2499 #define ERROR_GEN6 _MMIO(0x40a0)
2500 #define GEN7_ERR_INT _MMIO(0x44040)
2501 #define ERR_INT_POISON (1 << 31)
2502 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2503 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2504 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2505 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2506 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2507 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2508 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2509 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2510 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2512 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2513 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2514 #define FAULT_VA_HIGH_BITS (0xf << 0)
2515 #define FAULT_GTT_SEL (1 << 4)
2517 #define FPGA_DBG _MMIO(0x42300)
2518 #define FPGA_DBG_RM_NOCLAIM (1 << 31)
2520 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2521 #define CLAIM_ER_CLR (1 << 31)
2522 #define CLAIM_ER_OVERFLOW (1 << 16)
2523 #define CLAIM_ER_CTR_MASK 0xffff
2525 #define DERRMR _MMIO(0x44050)
2526 /* Note that HBLANK events are reserved on bdw+ */
2527 #define DERRMR_PIPEA_SCANLINE (1 << 0)
2528 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2529 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2530 #define DERRMR_PIPEA_VBLANK (1 << 3)
2531 #define DERRMR_PIPEA_HBLANK (1 << 5)
2532 #define DERRMR_PIPEB_SCANLINE (1 << 8)
2533 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2534 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2535 #define DERRMR_PIPEB_VBLANK (1 << 11)
2536 #define DERRMR_PIPEB_HBLANK (1 << 13)
2537 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2538 #define DERRMR_PIPEC_SCANLINE (1 << 14)
2539 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2540 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2541 #define DERRMR_PIPEC_VBLANK (1 << 21)
2542 #define DERRMR_PIPEC_HBLANK (1 << 22)
2545 /* GM45+ chicken bits -- debug workaround bits that may be required
2546 * for various sorts of correct behavior. The top 16 bits of each are
2547 * the enables for writing to the corresponding low bit.
2549 #define _3D_CHICKEN _MMIO(0x2084)
2550 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2551 #define _3D_CHICKEN2 _MMIO(0x208c)
2553 #define FF_SLICE_CHICKEN _MMIO(0x2088)
2554 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2556 /* Disables pipelining of read flushes past the SF-WIZ interface.
2557 * Required on all Ironlake steppings according to the B-Spec, but the
2558 * particular danger of not doing so is not specified.
2560 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2561 #define _3D_CHICKEN3 _MMIO(0x2090)
2562 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2563 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2564 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2565 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2566 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2567 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2569 #define MI_MODE _MMIO(0x209c)
2570 # define VS_TIMER_DISPATCH (1 << 6)
2571 # define MI_FLUSH_ENABLE (1 << 12)
2572 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2573 # define MODE_IDLE (1 << 9)
2574 # define STOP_RING (1 << 8)
2576 #define GEN6_GT_MODE _MMIO(0x20d0)
2577 #define GEN7_GT_MODE _MMIO(0x7008)
2578 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2579 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2580 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2581 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2582 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2583 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2584 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2585 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2587 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2588 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2589 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2590 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2592 /* WaClearTdlStateAckDirtyBits */
2593 #define GEN8_STATE_ACK _MMIO(0x20F0)
2594 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2595 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2596 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2597 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2598 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2599 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2600 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2601 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2602 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2604 #define GFX_MODE _MMIO(0x2520)
2605 #define GFX_MODE_GEN7 _MMIO(0x229c)
2606 #define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
2607 #define GFX_RUN_LIST_ENABLE (1 << 15)
2608 #define GFX_INTERRUPT_STEERING (1 << 14)
2609 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2610 #define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2611 #define GFX_REPLAY_MODE (1 << 11)
2612 #define GFX_PSMI_GRANULARITY (1 << 10)
2613 #define GFX_PPGTT_ENABLE (1 << 9)
2614 #define GEN8_GFX_PPGTT_48B (1 << 7)
2616 #define GFX_FORWARD_VBLANK_MASK (3 << 5)
2617 #define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2618 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2619 #define GFX_FORWARD_VBLANK_COND (2 << 5)
2621 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2623 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2624 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2625 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2626 #define IER _MMIO(0x20a0)
2627 #define IIR _MMIO(0x20a4)
2628 #define IMR _MMIO(0x20a8)
2629 #define ISR _MMIO(0x20ac)
2630 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2631 #define GINT_DIS (1 << 22)
2632 #define GCFG_DIS (1 << 8)
2633 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2634 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2635 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2636 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2637 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2638 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2639 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2640 #define VLV_PCBR_ADDR_SHIFT 12
2642 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2643 #define EIR _MMIO(0x20b0)
2644 #define EMR _MMIO(0x20b4)
2645 #define ESR _MMIO(0x20b8)
2646 #define GM45_ERROR_PAGE_TABLE (1 << 5)
2647 #define GM45_ERROR_MEM_PRIV (1 << 4)
2648 #define I915_ERROR_PAGE_TABLE (1 << 4)
2649 #define GM45_ERROR_CP_PRIV (1 << 3)
2650 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
2651 #define I915_ERROR_INSTRUCTION (1 << 0)
2652 #define INSTPM _MMIO(0x20c0)
2653 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2654 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2655 will not assert AGPBUSY# and will only
2656 be delivered when out of C3. */
2657 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2658 #define INSTPM_TLB_INVALIDATE (1 << 9)
2659 #define INSTPM_SYNC_FLUSH (1 << 5)
2660 #define ACTHD _MMIO(0x20c8)
2661 #define MEM_MODE _MMIO(0x20cc)
2662 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2663 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2664 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2665 #define FW_BLC _MMIO(0x20d8)
2666 #define FW_BLC2 _MMIO(0x20dc)
2667 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2668 #define FW_BLC_SELF_EN_MASK (1 << 31)
2669 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
2670 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
2671 #define MM_BURST_LENGTH 0x00700000
2672 #define MM_FIFO_WATERMARK 0x0001F000
2673 #define LM_BURST_LENGTH 0x00000700
2674 #define LM_FIFO_WATERMARK 0x0000001F
2675 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2677 #define MBUS_ABOX_CTL _MMIO(0x45038)
2678 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2679 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2680 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2681 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2682 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2683 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2684 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2685 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2687 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2688 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2689 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2690 _PIPEB_MBUS_DBOX_CTL)
2691 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2692 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2693 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2694 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2695 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2696 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2698 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2699 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2700 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2702 /* Make render/texture TLB fetches lower priorty than associated data
2703 * fetches. This is not turned on by default
2705 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2707 /* Isoch request wait on GTT enable (Display A/B/C streams).
2708 * Make isoch requests stall on the TLB update. May cause
2709 * display underruns (test mode only)
2711 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2713 /* Block grant count for isoch requests when block count is
2714 * set to a finite value.
2716 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2717 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2718 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2719 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2720 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2722 /* Enable render writes to complete in C2/C3/C4 power states.
2723 * If this isn't enabled, render writes are prevented in low
2724 * power states. That seems bad to me.
2726 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2728 /* This acknowledges an async flip immediately instead
2729 * of waiting for 2TLB fetches.
2731 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2733 /* Enables non-sequential data reads through arbiter
2735 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2737 /* Disable FSB snooping of cacheable write cycles from binner/render
2740 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2742 /* Arbiter time slice for non-isoch streams */
2743 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2744 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2745 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2746 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2747 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2748 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2749 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2750 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2751 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2753 /* Low priority grace period page size */
2754 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2755 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2757 /* Disable display A/B trickle feed */
2758 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2760 /* Set display plane priority */
2761 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2762 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2764 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2765 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2766 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2768 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2769 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
2770 #define CM0_IZ_OPT_DISABLE (1 << 6)
2771 #define CM0_ZR_OPT_DISABLE (1 << 5)
2772 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
2773 #define CM0_DEPTH_EVICT_DISABLE (1 << 4)
2774 #define CM0_COLOR_EVICT_DISABLE (1 << 3)
2775 #define CM0_DEPTH_WRITE_DISABLE (1 << 1)
2776 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
2777 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2778 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2779 #define GFX_FLSH_CNTL_EN (1 << 0)
2780 #define ECOSKPD _MMIO(0x21d0)
2781 #define ECO_GATING_CX_ONLY (1 << 3)
2782 #define ECO_FLIP_DONE (1 << 0)
2784 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2785 #define RC_OP_FLUSH_ENABLE (1 << 0)
2786 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
2787 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2788 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
2789 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
2790 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
2792 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2793 #define GEN6_BLITTER_LOCK_SHIFT 16
2794 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
2796 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2797 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2798 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2799 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
2801 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2802 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2804 #define GEN10_CACHE_MODE_SS _MMIO(0xe420)
2805 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
2807 /* Fuse readout registers for GT */
2808 #define HSW_PAVP_FUSE1 _MMIO(0x911C)
2809 #define HSW_F1_EU_DIS_SHIFT 16
2810 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2811 #define HSW_F1_EU_DIS_10EUS 0
2812 #define HSW_F1_EU_DIS_8EUS 1
2813 #define HSW_F1_EU_DIS_6EUS 2
2815 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2816 #define CHV_FGT_DISABLE_SS0 (1 << 10)
2817 #define CHV_FGT_DISABLE_SS1 (1 << 11)
2818 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2819 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2820 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2821 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2822 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2823 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2824 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2825 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2827 #define GEN8_FUSE2 _MMIO(0x9120)
2828 #define GEN8_F2_SS_DIS_SHIFT 21
2829 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2830 #define GEN8_F2_S_ENA_SHIFT 25
2831 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2833 #define GEN9_F2_SS_DIS_SHIFT 20
2834 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2836 #define GEN10_F2_S_ENA_SHIFT 22
2837 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2838 #define GEN10_F2_SS_DIS_SHIFT 18
2839 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2841 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
2842 #define GEN10_L3BANK_PAIR_COUNT 4
2843 #define GEN10_L3BANK_MASK 0x0F
2845 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
2846 #define GEN8_EU_DIS0_S0_MASK 0xffffff
2847 #define GEN8_EU_DIS0_S1_SHIFT 24
2848 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2850 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
2851 #define GEN8_EU_DIS1_S1_MASK 0xffff
2852 #define GEN8_EU_DIS1_S2_SHIFT 16
2853 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2855 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
2856 #define GEN8_EU_DIS2_S2_MASK 0xff
2858 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
2860 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
2861 #define GEN10_EU_DIS_SS_MASK 0xff
2863 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
2864 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff
2865 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
2866 #define GEN11_GT_VEBOX_DISABLE_MASK (0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
2868 #define GEN11_EU_DISABLE _MMIO(0x9134)
2869 #define GEN11_EU_DIS_MASK 0xFF
2871 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
2872 #define GEN11_GT_S_ENA_MASK 0xFF
2874 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
2876 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2877 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2878 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2879 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2880 #define GEN6_BSD_GO_INDICATOR (1 << 4)
2882 /* On modern GEN architectures interrupt control consists of two sets
2883 * of registers. The first set pertains to the ring generating the
2884 * interrupt. The second control is for the functional block generating the
2885 * interrupt. These are PM, GT, DE, etc.
2887 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2888 * GT interrupt bits, so we don't need to duplicate the defines.
2890 * These defines should cover us well from SNB->HSW with minor exceptions
2891 * it can also work on ILK.
2893 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2894 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2895 #define GT_BLT_USER_INTERRUPT (1 << 22)
2896 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2897 #define GT_BSD_USER_INTERRUPT (1 << 12)
2898 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2899 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2900 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2901 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2902 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2903 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2904 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2905 #define GT_RENDER_USER_INTERRUPT (1 << 0)
2907 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2908 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2910 #define GT_PARITY_ERROR(dev_priv) \
2911 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2912 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2914 /* These are all the "old" interrupts */
2915 #define ILK_BSD_USER_INTERRUPT (1 << 5)
2917 #define I915_PM_INTERRUPT (1 << 31)
2918 #define I915_ISP_INTERRUPT (1 << 22)
2919 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
2920 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
2921 #define I915_MIPIC_INTERRUPT (1 << 19)
2922 #define I915_MIPIA_INTERRUPT (1 << 18)
2923 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
2924 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
2925 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
2926 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
2927 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
2928 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
2929 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
2930 #define I915_HWB_OOM_INTERRUPT (1 << 13)
2931 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
2932 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
2933 #define I915_MISC_INTERRUPT (1 << 11)
2934 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
2935 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
2936 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
2937 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
2938 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
2939 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
2940 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
2941 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
2942 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
2943 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
2944 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
2945 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
2946 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
2947 #define I915_DEBUG_INTERRUPT (1 << 2)
2948 #define I915_WINVALID_INTERRUPT (1 << 1)
2949 #define I915_USER_INTERRUPT (1 << 1)
2950 #define I915_ASLE_INTERRUPT (1 << 0)
2951 #define I915_BSD_USER_INTERRUPT (1 << 25)
2953 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2954 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2956 /* DisplayPort Audio w/ LPE */
2957 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2958 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2960 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2961 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2962 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2963 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2964 _VLV_AUD_PORT_EN_B_DBG, \
2965 _VLV_AUD_PORT_EN_C_DBG, \
2966 _VLV_AUD_PORT_EN_D_DBG)
2967 #define VLV_AMP_MUTE (1 << 1)
2969 #define GEN6_BSD_RNCID _MMIO(0x12198)
2971 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2972 #define GEN7_FF_SCHED_MASK 0x0077070
2973 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2974 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
2975 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
2976 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
2977 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
2978 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2979 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
2980 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
2981 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
2982 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
2983 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
2984 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
2985 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
2986 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
2989 * Framebuffer compression (915+ only)
2992 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2993 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2994 #define FBC_CONTROL _MMIO(0x3208)
2995 #define FBC_CTL_EN (1 << 31)
2996 #define FBC_CTL_PERIODIC (1 << 30)
2997 #define FBC_CTL_INTERVAL_SHIFT (16)
2998 #define FBC_CTL_UNCOMPRESSIBLE (1 << 14)
2999 #define FBC_CTL_C3_IDLE (1 << 13)
3000 #define FBC_CTL_STRIDE_SHIFT (5)
3001 #define FBC_CTL_FENCENO_SHIFT (0)
3002 #define FBC_COMMAND _MMIO(0x320c)
3003 #define FBC_CMD_COMPRESS (1 << 0)
3004 #define FBC_STATUS _MMIO(0x3210)
3005 #define FBC_STAT_COMPRESSING (1 << 31)
3006 #define FBC_STAT_COMPRESSED (1 << 30)
3007 #define FBC_STAT_MODIFIED (1 << 29)
3008 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
3009 #define FBC_CONTROL2 _MMIO(0x3214)
3010 #define FBC_CTL_FENCE_DBL (0 << 4)
3011 #define FBC_CTL_IDLE_IMM (0 << 2)
3012 #define FBC_CTL_IDLE_FULL (1 << 2)
3013 #define FBC_CTL_IDLE_LINE (2 << 2)
3014 #define FBC_CTL_IDLE_DEBUG (3 << 2)
3015 #define FBC_CTL_CPU_FENCE (1 << 1)
3016 #define FBC_CTL_PLANE(plane) ((plane) << 0)
3017 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3018 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3020 #define FBC_LL_SIZE (1536)
3022 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
3023 #define FBC_LLC_FULLY_OPEN (1 << 30)
3025 /* Framebuffer compression for GM45+ */
3026 #define DPFC_CB_BASE _MMIO(0x3200)
3027 #define DPFC_CONTROL _MMIO(0x3208)
3028 #define DPFC_CTL_EN (1 << 31)
3029 #define DPFC_CTL_PLANE(plane) ((plane) << 30)
3030 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3031 #define DPFC_CTL_FENCE_EN (1 << 29)
3032 #define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3033 #define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3034 #define DPFC_SR_EN (1 << 10)
3035 #define DPFC_CTL_LIMIT_1X (0 << 6)
3036 #define DPFC_CTL_LIMIT_2X (1 << 6)
3037 #define DPFC_CTL_LIMIT_4X (2 << 6)
3038 #define DPFC_RECOMP_CTL _MMIO(0x320c)
3039 #define DPFC_RECOMP_STALL_EN (1 << 27)
3040 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
3041 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3042 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3043 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3044 #define DPFC_STATUS _MMIO(0x3210)
3045 #define DPFC_INVAL_SEG_SHIFT (16)
3046 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
3047 #define DPFC_COMP_SEG_SHIFT (0)
3048 #define DPFC_COMP_SEG_MASK (0x000007ff)
3049 #define DPFC_STATUS2 _MMIO(0x3214)
3050 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3051 #define DPFC_CHICKEN _MMIO(0x3224)
3052 #define DPFC_HT_MODIFY (1 << 31)
3054 /* Framebuffer compression for Ironlake */
3055 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3056 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3057 #define FBC_CTL_FALSE_COLOR (1 << 10)
3058 /* The bit 28-8 is reserved */
3059 #define DPFC_RESERVED (0x1FFFFF00)
3060 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3061 #define ILK_DPFC_STATUS _MMIO(0x43210)
3062 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3063 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3064 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3065 #define BDW_FBC_COMP_SEG_MASK 0xfff
3066 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3067 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3068 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3069 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3070 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3071 #define ILK_FBC_RT_VALID (1 << 0)
3072 #define SNB_FBC_FRONT_BUFFER (1 << 1)
3074 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3075 #define ILK_FBCQ_DIS (1 << 22)
3076 #define ILK_PABSTRETCH_DIS (1 << 21)
3080 * Framebuffer compression for Sandybridge
3082 * The following two registers are of type GTTMMADR
3084 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3085 #define SNB_CPU_FENCE_ENABLE (1 << 29)
3086 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3088 /* Framebuffer compression for Ivybridge */
3089 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3091 #define IPS_CTL _MMIO(0x43408)
3092 #define IPS_ENABLE (1 << 31)
3094 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3095 #define FBC_REND_NUKE (1 << 2)
3096 #define FBC_REND_CACHE_CLEAN (1 << 1)
3101 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3104 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3105 # define GPIO_CLOCK_DIR_IN (0 << 1)
3106 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3107 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3108 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3109 # define GPIO_CLOCK_VAL_IN (1 << 4)
3110 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3111 # define GPIO_DATA_DIR_MASK (1 << 8)
3112 # define GPIO_DATA_DIR_IN (0 << 9)
3113 # define GPIO_DATA_DIR_OUT (1 << 9)
3114 # define GPIO_DATA_VAL_MASK (1 << 10)
3115 # define GPIO_DATA_VAL_OUT (1 << 11)
3116 # define GPIO_DATA_VAL_IN (1 << 12)
3117 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3119 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3120 #define GMBUS_AKSV_SELECT (1 << 11)
3121 #define GMBUS_RATE_100KHZ (0 << 8)
3122 #define GMBUS_RATE_50KHZ (1 << 8)
3123 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3124 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3125 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3126 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3127 #define GMBUS_PIN_DISABLED 0
3128 #define GMBUS_PIN_SSC 1
3129 #define GMBUS_PIN_VGADDC 2
3130 #define GMBUS_PIN_PANEL 3
3131 #define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3132 #define GMBUS_PIN_DPC 4 /* HDMIC */
3133 #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3134 #define GMBUS_PIN_DPD 6 /* HDMID */
3135 #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3136 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3137 #define GMBUS_PIN_2_BXT 2
3138 #define GMBUS_PIN_3_BXT 3
3139 #define GMBUS_PIN_4_CNP 4
3140 #define GMBUS_PIN_9_TC1_ICP 9
3141 #define GMBUS_PIN_10_TC2_ICP 10
3142 #define GMBUS_PIN_11_TC3_ICP 11
3143 #define GMBUS_PIN_12_TC4_ICP 12
3145 #define GMBUS_NUM_PINS 13 /* including 0 */
3146 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3147 #define GMBUS_SW_CLR_INT (1 << 31)
3148 #define GMBUS_SW_RDY (1 << 30)
3149 #define GMBUS_ENT (1 << 29) /* enable timeout */
3150 #define GMBUS_CYCLE_NONE (0 << 25)
3151 #define GMBUS_CYCLE_WAIT (1 << 25)
3152 #define GMBUS_CYCLE_INDEX (2 << 25)
3153 #define GMBUS_CYCLE_STOP (4 << 25)
3154 #define GMBUS_BYTE_COUNT_SHIFT 16
3155 #define GMBUS_BYTE_COUNT_MAX 256U
3156 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3157 #define GMBUS_SLAVE_INDEX_SHIFT 8
3158 #define GMBUS_SLAVE_ADDR_SHIFT 1
3159 #define GMBUS_SLAVE_READ (1 << 0)
3160 #define GMBUS_SLAVE_WRITE (0 << 0)
3161 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3162 #define GMBUS_INUSE (1 << 15)
3163 #define GMBUS_HW_WAIT_PHASE (1 << 14)
3164 #define GMBUS_STALL_TIMEOUT (1 << 13)
3165 #define GMBUS_INT (1 << 12)
3166 #define GMBUS_HW_RDY (1 << 11)
3167 #define GMBUS_SATOER (1 << 10)
3168 #define GMBUS_ACTIVE (1 << 9)
3169 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3170 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3171 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3172 #define GMBUS_NAK_EN (1 << 3)
3173 #define GMBUS_IDLE_EN (1 << 2)
3174 #define GMBUS_HW_WAIT_EN (1 << 1)
3175 #define GMBUS_HW_RDY_EN (1 << 0)
3176 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3177 #define GMBUS_2BYTE_INDEX_EN (1 << 31)
3180 * Clock control & power management
3182 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3183 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3184 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3185 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3187 #define VGA0 _MMIO(0x6000)
3188 #define VGA1 _MMIO(0x6004)
3189 #define VGA_PD _MMIO(0x6010)
3190 #define VGA0_PD_P2_DIV_4 (1 << 7)
3191 #define VGA0_PD_P1_DIV_2 (1 << 5)
3192 #define VGA0_PD_P1_SHIFT 0
3193 #define VGA0_PD_P1_MASK (0x1f << 0)
3194 #define VGA1_PD_P2_DIV_4 (1 << 15)
3195 #define VGA1_PD_P1_DIV_2 (1 << 13)
3196 #define VGA1_PD_P1_SHIFT 8
3197 #define VGA1_PD_P1_MASK (0x1f << 8)
3198 #define DPLL_VCO_ENABLE (1 << 31)
3199 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3200 #define DPLL_DVO_2X_MODE (1 << 30)
3201 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3202 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3203 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3204 #define DPLL_VGA_MODE_DIS (1 << 28)
3205 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3206 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3207 #define DPLL_MODE_MASK (3 << 26)
3208 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3209 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3210 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3211 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3212 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3213 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3214 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3215 #define DPLL_LOCK_VLV (1 << 15)
3216 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3217 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3218 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
3219 #define DPLL_PORTC_READY_MASK (0xf << 4)
3220 #define DPLL_PORTB_READY_MASK (0xf)
3222 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3224 /* Additional CHV pll/phy registers */
3225 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3226 #define DPLL_PORTD_READY_MASK (0xf)
3227 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3228 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3229 #define PHY_LDO_DELAY_0NS 0x0
3230 #define PHY_LDO_DELAY_200NS 0x1
3231 #define PHY_LDO_DELAY_600NS 0x2
3232 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3233 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3234 #define PHY_CH_SU_PSR 0x1
3235 #define PHY_CH_DEEP_PSR 0x7
3236 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3237 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3238 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3239 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3240 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3241 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3244 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3245 * this field (only one bit may be set).
3247 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3248 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3249 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3250 /* i830, required in DVO non-gang */
3251 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3252 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3253 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3254 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3255 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3256 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3257 #define PLL_REF_INPUT_MASK (3 << 13)
3258 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3260 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3261 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3262 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3263 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3264 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3267 * Parallel to Serial Load Pulse phase selection.
3268 * Selects the phase for the 10X DPLL clock for the PCIe
3269 * digital display port. The range is 4 to 13; 10 or more
3270 * is just a flip delay. The default is 6
3272 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3273 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3275 * SDVO multiplier for 945G/GM. Not used on 965.
3277 #define SDVO_MULTIPLIER_MASK 0x000000ff
3278 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3279 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3281 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3282 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3283 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3284 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3287 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3289 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3291 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3292 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3293 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3294 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3295 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3297 * SDVO/UDI pixel multiplier.
3299 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3300 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3301 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3302 * dummy bytes in the datastream at an increased clock rate, with both sides of
3303 * the link knowing how many bytes are fill.
3305 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3306 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3307 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3308 * through an SDVO command.
3310 * This register field has values of multiplication factor minus 1, with
3311 * a maximum multiplier of 5 for SDVO.
3313 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3314 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3316 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3317 * This best be set to the default value (3) or the CRT won't work. No,
3318 * I don't entirely understand what this does...
3320 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3321 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3323 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3325 #define _FPA0 0x6040
3326 #define _FPA1 0x6044
3327 #define _FPB0 0x6048
3328 #define _FPB1 0x604c
3329 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3330 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3331 #define FP_N_DIV_MASK 0x003f0000
3332 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3333 #define FP_N_DIV_SHIFT 16
3334 #define FP_M1_DIV_MASK 0x00003f00
3335 #define FP_M1_DIV_SHIFT 8
3336 #define FP_M2_DIV_MASK 0x0000003f
3337 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3338 #define FP_M2_DIV_SHIFT 0
3339 #define DPLL_TEST _MMIO(0x606c)
3340 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3341 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3342 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3343 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3344 #define DPLLB_TEST_N_BYPASS (1 << 19)
3345 #define DPLLB_TEST_M_BYPASS (1 << 18)
3346 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3347 #define DPLLA_TEST_N_BYPASS (1 << 3)
3348 #define DPLLA_TEST_M_BYPASS (1 << 2)
3349 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3350 #define D_STATE _MMIO(0x6104)
3351 #define DSTATE_GFX_RESET_I830 (1 << 6)
3352 #define DSTATE_PLL_D3_OFF (1 << 3)
3353 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
3354 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
3355 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3356 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3357 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3358 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3359 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3360 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3361 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3362 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3363 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3364 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3365 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3366 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3367 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3368 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3369 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3370 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3371 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3372 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3373 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3374 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3375 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3376 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3377 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3378 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3379 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3380 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3381 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3382 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3383 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3384 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3386 * This bit must be set on the 830 to prevent hangs when turning off the
3389 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3390 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3391 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3392 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3393 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3395 #define RENCLK_GATE_D1 _MMIO(0x6204)
3396 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3397 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3398 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3399 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3400 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3401 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3402 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3403 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3404 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3405 /* This bit must be unset on 855,865 */
3406 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3407 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3408 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3409 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3410 /* This bit must be set on 855,865. */
3411 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3412 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3413 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3414 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3415 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3416 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3417 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3418 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3419 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3420 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3421 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3422 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3423 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3424 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3425 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3426 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3427 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3428 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3430 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3431 /* This bit must always be set on 965G/965GM */
3432 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3433 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3434 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3435 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3436 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3437 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3438 /* This bit must always be set on 965G */
3439 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3440 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3441 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3442 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3443 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3444 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3445 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3446 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3447 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3448 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3449 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3450 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3451 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3452 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3453 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3454 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3455 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3456 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3457 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3459 #define RENCLK_GATE_D2 _MMIO(0x6208)
3460 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3461 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3462 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3464 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3465 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3467 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3468 #define DEUC _MMIO(0x6214) /* CRL only */
3470 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3471 #define FW_CSPWRDWNEN (1 << 15)
3473 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3475 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3476 #define CDCLK_FREQ_SHIFT 4
3477 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3478 #define CZCLK_FREQ_MASK 0xf
3480 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3481 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3482 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3483 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3484 #define PFI_CREDIT_RESEND (1 << 27)
3485 #define VGA_FAST_MODE_DISABLE (1 << 14)
3487 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3492 #define _PALETTE_A 0xa000
3493 #define _PALETTE_B 0xa800
3494 #define _CHV_PALETTE_C 0xc000
3495 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3496 _PICK((pipe), _PALETTE_A, \
3497 _PALETTE_B, _CHV_PALETTE_C) + \
3500 /* MCH MMIO space */
3505 * This mirrors the MCHBAR MMIO space whose location is determined by
3506 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3507 * every way. It is not accessible from the CP register read instructions.
3509 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3512 #define MCHBAR_MIRROR_BASE 0x10000
3514 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3516 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3517 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3518 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3519 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3520 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3522 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3523 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3525 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3526 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3527 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3528 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3529 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3530 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3531 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3532 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3533 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3534 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3536 /* Pineview MCH register contains DDR3 setting */
3537 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3538 #define CSHRDDR3CTL_DDR3 (1 << 2)
3540 /* 965 MCH register controlling DRAM channel configuration */
3541 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3542 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3544 /* snb MCH registers for reading the DRAM channel configuration */
3545 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3546 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3547 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3548 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3549 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3550 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3551 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3552 #define MAD_DIMM_ECC_ON (0x3 << 24)
3553 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3554 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3555 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3556 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3557 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3558 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3559 #define MAD_DIMM_A_SELECT (0x1 << 16)
3560 /* DIMM sizes are in multiples of 256mb. */
3561 #define MAD_DIMM_B_SIZE_SHIFT 8
3562 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3563 #define MAD_DIMM_A_SIZE_SHIFT 0
3564 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3566 /* snb MCH registers for priority tuning */
3567 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3568 #define MCH_SSKPD_WM0_MASK 0x3f
3569 #define MCH_SSKPD_WM0_VAL 0xc
3571 #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3573 /* Clocking configuration register */
3574 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3575 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3576 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3577 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3578 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3579 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3580 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3581 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3583 * Note that on at least on ELK the below value is reported for both
3584 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3585 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3587 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3588 #define CLKCFG_FSB_MASK (7 << 0)
3589 #define CLKCFG_MEM_533 (1 << 4)
3590 #define CLKCFG_MEM_667 (2 << 4)
3591 #define CLKCFG_MEM_800 (3 << 4)
3592 #define CLKCFG_MEM_MASK (7 << 4)
3594 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3595 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3597 #define TSC1 _MMIO(0x11001)
3598 #define TSE (1 << 0)
3599 #define TR1 _MMIO(0x11006)
3600 #define TSFS _MMIO(0x11020)
3601 #define TSFS_SLOPE_MASK 0x0000ff00
3602 #define TSFS_SLOPE_SHIFT 8
3603 #define TSFS_INTR_MASK 0x000000ff
3605 #define CRSTANDVID _MMIO(0x11100)
3606 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3607 #define PXVFREQ_PX_MASK 0x7f000000
3608 #define PXVFREQ_PX_SHIFT 24
3609 #define VIDFREQ_BASE _MMIO(0x11110)
3610 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3611 #define VIDFREQ2 _MMIO(0x11114)
3612 #define VIDFREQ3 _MMIO(0x11118)
3613 #define VIDFREQ4 _MMIO(0x1111c)
3614 #define VIDFREQ_P0_MASK 0x1f000000
3615 #define VIDFREQ_P0_SHIFT 24
3616 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3617 #define VIDFREQ_P0_CSCLK_SHIFT 20
3618 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3619 #define VIDFREQ_P0_CRCLK_SHIFT 16
3620 #define VIDFREQ_P1_MASK 0x00001f00
3621 #define VIDFREQ_P1_SHIFT 8
3622 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3623 #define VIDFREQ_P1_CSCLK_SHIFT 4
3624 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3625 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3626 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3627 #define INTTOEXT_MAP3_SHIFT 24
3628 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3629 #define INTTOEXT_MAP2_SHIFT 16
3630 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3631 #define INTTOEXT_MAP1_SHIFT 8
3632 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3633 #define INTTOEXT_MAP0_SHIFT 0
3634 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3635 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3636 #define MEMCTL_CMD_MASK 0xe000
3637 #define MEMCTL_CMD_SHIFT 13
3638 #define MEMCTL_CMD_RCLK_OFF 0
3639 #define MEMCTL_CMD_RCLK_ON 1
3640 #define MEMCTL_CMD_CHFREQ 2
3641 #define MEMCTL_CMD_CHVID 3
3642 #define MEMCTL_CMD_VMMOFF 4
3643 #define MEMCTL_CMD_VMMON 5
3644 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
3645 when command complete */
3646 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3647 #define MEMCTL_FREQ_SHIFT 8
3648 #define MEMCTL_SFCAVM (1 << 7)
3649 #define MEMCTL_TGT_VID_MASK 0x007f
3650 #define MEMIHYST _MMIO(0x1117c)
3651 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3652 #define MEMINT_RSEXIT_EN (1 << 8)
3653 #define MEMINT_CX_SUPR_EN (1 << 7)
3654 #define MEMINT_CONT_BUSY_EN (1 << 6)
3655 #define MEMINT_AVG_BUSY_EN (1 << 5)
3656 #define MEMINT_EVAL_CHG_EN (1 << 4)
3657 #define MEMINT_MON_IDLE_EN (1 << 3)
3658 #define MEMINT_UP_EVAL_EN (1 << 2)
3659 #define MEMINT_DOWN_EVAL_EN (1 << 1)
3660 #define MEMINT_SW_CMD_EN (1 << 0)
3661 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3662 #define MEM_RSEXIT_MASK 0xc000
3663 #define MEM_RSEXIT_SHIFT 14
3664 #define MEM_CONT_BUSY_MASK 0x3000
3665 #define MEM_CONT_BUSY_SHIFT 12
3666 #define MEM_AVG_BUSY_MASK 0x0c00
3667 #define MEM_AVG_BUSY_SHIFT 10
3668 #define MEM_EVAL_CHG_MASK 0x0300
3669 #define MEM_EVAL_BUSY_SHIFT 8
3670 #define MEM_MON_IDLE_MASK 0x00c0
3671 #define MEM_MON_IDLE_SHIFT 6
3672 #define MEM_UP_EVAL_MASK 0x0030
3673 #define MEM_UP_EVAL_SHIFT 4
3674 #define MEM_DOWN_EVAL_MASK 0x000c
3675 #define MEM_DOWN_EVAL_SHIFT 2
3676 #define MEM_SW_CMD_MASK 0x0003
3677 #define MEM_INT_STEER_GFX 0
3678 #define MEM_INT_STEER_CMR 1
3679 #define MEM_INT_STEER_SMI 2
3680 #define MEM_INT_STEER_SCI 3
3681 #define MEMINTRSTS _MMIO(0x11184)
3682 #define MEMINT_RSEXIT (1 << 7)
3683 #define MEMINT_CONT_BUSY (1 << 6)
3684 #define MEMINT_AVG_BUSY (1 << 5)
3685 #define MEMINT_EVAL_CHG (1 << 4)
3686 #define MEMINT_MON_IDLE (1 << 3)
3687 #define MEMINT_UP_EVAL (1 << 2)
3688 #define MEMINT_DOWN_EVAL (1 << 1)
3689 #define MEMINT_SW_CMD (1 << 0)
3690 #define MEMMODECTL _MMIO(0x11190)
3691 #define MEMMODE_BOOST_EN (1 << 31)
3692 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3693 #define MEMMODE_BOOST_FREQ_SHIFT 24
3694 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3695 #define MEMMODE_IDLE_MODE_SHIFT 16
3696 #define MEMMODE_IDLE_MODE_EVAL 0
3697 #define MEMMODE_IDLE_MODE_CONT 1
3698 #define MEMMODE_HWIDLE_EN (1 << 15)
3699 #define MEMMODE_SWMODE_EN (1 << 14)
3700 #define MEMMODE_RCLK_GATE (1 << 13)
3701 #define MEMMODE_HW_UPDATE (1 << 12)
3702 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3703 #define MEMMODE_FSTART_SHIFT 8
3704 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3705 #define MEMMODE_FMAX_SHIFT 4
3706 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3707 #define RCBMAXAVG _MMIO(0x1119c)
3708 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3709 #define SWMEMCMD_RENDER_OFF (0 << 13)
3710 #define SWMEMCMD_RENDER_ON (1 << 13)
3711 #define SWMEMCMD_SWFREQ (2 << 13)
3712 #define SWMEMCMD_TARVID (3 << 13)
3713 #define SWMEMCMD_VRM_OFF (4 << 13)
3714 #define SWMEMCMD_VRM_ON (5 << 13)
3715 #define CMDSTS (1 << 12)
3716 #define SFCAVM (1 << 11)
3717 #define SWFREQ_MASK 0x0380 /* P0-7 */
3718 #define SWFREQ_SHIFT 7
3719 #define TARVID_MASK 0x001f
3720 #define MEMSTAT_CTG _MMIO(0x111a0)
3721 #define RCBMINAVG _MMIO(0x111a0)
3722 #define RCUPEI _MMIO(0x111b0)
3723 #define RCDNEI _MMIO(0x111b4)
3724 #define RSTDBYCTL _MMIO(0x111b8)
3725 #define RS1EN (1 << 31)
3726 #define RS2EN (1 << 30)
3727 #define RS3EN (1 << 29)
3728 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
3729 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
3730 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
3731 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
3732 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3733 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3734 #define RSX_STATUS_MASK (7 << 20)
3735 #define RSX_STATUS_ON (0 << 20)
3736 #define RSX_STATUS_RC1 (1 << 20)
3737 #define RSX_STATUS_RC1E (2 << 20)
3738 #define RSX_STATUS_RS1 (3 << 20)
3739 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
3740 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
3741 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
3742 #define RSX_STATUS_RSVD2 (7 << 20)
3743 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
3744 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
3745 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3746 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
3747 #define RS1CONTSAV_MASK (3 << 14)
3748 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
3749 #define RS1CONTSAV_RSVD (1 << 14)
3750 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
3751 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
3752 #define NORMSLEXLAT_MASK (3 << 12)
3753 #define SLOW_RS123 (0 << 12)
3754 #define SLOW_RS23 (1 << 12)
3755 #define SLOW_RS3 (2 << 12)
3756 #define NORMAL_RS123 (3 << 12)
3757 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
3758 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3759 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3760 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
3761 #define RS_CSTATE_MASK (3 << 4)
3762 #define RS_CSTATE_C367_RS1 (0 << 4)
3763 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3764 #define RS_CSTATE_RSVD (2 << 4)
3765 #define RS_CSTATE_C367_RS2 (3 << 4)
3766 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
3767 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
3768 #define VIDCTL _MMIO(0x111c0)
3769 #define VIDSTS _MMIO(0x111c8)
3770 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3771 #define MEMSTAT_ILK _MMIO(0x111f8)
3772 #define MEMSTAT_VID_MASK 0x7f00
3773 #define MEMSTAT_VID_SHIFT 8
3774 #define MEMSTAT_PSTATE_MASK 0x00f8
3775 #define MEMSTAT_PSTATE_SHIFT 3
3776 #define MEMSTAT_MON_ACTV (1 << 2)
3777 #define MEMSTAT_SRC_CTL_MASK 0x0003
3778 #define MEMSTAT_SRC_CTL_CORE 0
3779 #define MEMSTAT_SRC_CTL_TRB 1
3780 #define MEMSTAT_SRC_CTL_THM 2
3781 #define MEMSTAT_SRC_CTL_STDBY 3
3782 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
3783 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
3784 #define PMMISC _MMIO(0x11214)
3785 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
3786 #define SDEW _MMIO(0x1124c)
3787 #define CSIEW0 _MMIO(0x11250)
3788 #define CSIEW1 _MMIO(0x11254)
3789 #define CSIEW2 _MMIO(0x11258)
3790 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3791 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3792 #define MCHAFE _MMIO(0x112c0)
3793 #define CSIEC _MMIO(0x112e0)
3794 #define DMIEC _MMIO(0x112e4)
3795 #define DDREC _MMIO(0x112e8)
3796 #define PEG0EC _MMIO(0x112ec)
3797 #define PEG1EC _MMIO(0x112f0)
3798 #define GFXEC _MMIO(0x112f4)
3799 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
3800 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
3801 #define ECR _MMIO(0x11600)
3802 #define ECR_GPFE (1 << 31)
3803 #define ECR_IMONE (1 << 30)
3804 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3805 #define OGW0 _MMIO(0x11608)
3806 #define OGW1 _MMIO(0x1160c)
3807 #define EG0 _MMIO(0x11610)
3808 #define EG1 _MMIO(0x11614)
3809 #define EG2 _MMIO(0x11618)
3810 #define EG3 _MMIO(0x1161c)
3811 #define EG4 _MMIO(0x11620)
3812 #define EG5 _MMIO(0x11624)
3813 #define EG6 _MMIO(0x11628)
3814 #define EG7 _MMIO(0x1162c)
3815 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3816 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3817 #define LCFUSE02 _MMIO(0x116c0)
3818 #define LCFUSE_HIV_MASK 0x000000ff
3819 #define CSIPLL0 _MMIO(0x12c10)
3820 #define DDRMPLL1 _MMIO(0X12c20)
3821 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3823 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3824 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3826 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3827 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3828 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3829 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3830 #define BXT_RP_STATE_CAP _MMIO(0x138170)
3833 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3834 * 8300) freezing up around GPU hangs. Looks as if even
3835 * scheduling/timer interrupts start misbehaving if the RPS
3836 * EI/thresholds are "bad", leading to a very sluggish or even
3839 #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3840 #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3841 #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3842 #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3843 (IS_GEN9_LP(dev_priv) ? \
3844 INTERVAL_0_833_US(us) : \
3845 INTERVAL_1_33_US(us)) : \
3846 INTERVAL_1_28_US(us))
3848 #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3849 #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3850 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3851 #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3852 (IS_GEN9_LP(dev_priv) ? \
3853 INTERVAL_0_833_TO_US(interval) : \
3854 INTERVAL_1_33_TO_US(interval)) : \
3855 INTERVAL_1_28_TO_US(interval))
3858 * Logical Context regs
3860 #define CCID _MMIO(0x2180)
3861 #define CCID_EN BIT(0)
3862 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
3863 #define CCID_EXTENDED_STATE_SAVE BIT(3)
3865 * Notes on SNB/IVB/VLV context size:
3866 * - Power context is saved elsewhere (LLC or stolen)
3867 * - Ring/execlist context is saved on SNB, not on IVB
3868 * - Extended context size already includes render context size
3869 * - We always need to follow the extended context size.
3870 * SNB BSpec has comments indicating that we should use the
3871 * render context size instead if execlists are disabled, but
3872 * based on empirical testing that's just nonsense.
3873 * - Pipelined/VF state is saved on SNB/IVB respectively
3874 * - GT1 size just indicates how much of render context
3875 * doesn't need saving on GT1
3877 #define CXT_SIZE _MMIO(0x21a0)
3878 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3879 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3880 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3881 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3882 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3883 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3884 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3885 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3886 #define GEN7_CXT_SIZE _MMIO(0x21a8)
3887 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3888 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3889 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3890 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3891 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3892 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3893 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3894 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3897 INTEL_ADVANCED_CONTEXT = 0,
3898 INTEL_LEGACY_32B_CONTEXT,
3899 INTEL_ADVANCED_AD_CONTEXT,
3900 INTEL_LEGACY_64B_CONTEXT
3905 FAULT_AND_HALT, /* Debug only */
3907 FAULT_AND_CONTINUE /* Unsupported */
3910 #define GEN8_CTX_VALID (1 << 0)
3911 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
3912 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
3913 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
3914 #define GEN8_CTX_PRIVILEGE (1 << 8)
3915 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3917 #define GEN8_CTX_ID_SHIFT 32
3918 #define GEN8_CTX_ID_WIDTH 21
3919 #define GEN11_SW_CTX_ID_SHIFT 37
3920 #define GEN11_SW_CTX_ID_WIDTH 11
3921 #define GEN11_ENGINE_CLASS_SHIFT 61
3922 #define GEN11_ENGINE_CLASS_WIDTH 3
3923 #define GEN11_ENGINE_INSTANCE_SHIFT 48
3924 #define GEN11_ENGINE_INSTANCE_WIDTH 6
3926 #define CHV_CLK_CTL1 _MMIO(0x101100)
3927 #define VLV_CLK_CTL2 _MMIO(0x101104)
3928 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3934 #define OVADD _MMIO(0x30000)
3935 #define DOVSTA _MMIO(0x30008)
3936 #define OC_BUF (0x3 << 20)
3937 #define OGAMC5 _MMIO(0x30010)
3938 #define OGAMC4 _MMIO(0x30014)
3939 #define OGAMC3 _MMIO(0x30018)
3940 #define OGAMC2 _MMIO(0x3001c)
3941 #define OGAMC1 _MMIO(0x30020)
3942 #define OGAMC0 _MMIO(0x30024)
3945 * GEN9 clock gating regs
3947 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3948 #define DARBF_GATING_DIS (1 << 27)
3949 #define PWM2_GATING_DIS (1 << 14)
3950 #define PWM1_GATING_DIS (1 << 13)
3952 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3953 #define BXT_GMBUS_GATING_DIS (1 << 14)
3955 #define _CLKGATE_DIS_PSL_A 0x46520
3956 #define _CLKGATE_DIS_PSL_B 0x46524
3957 #define _CLKGATE_DIS_PSL_C 0x46528
3958 #define DUPS1_GATING_DIS (1 << 15)
3959 #define DUPS2_GATING_DIS (1 << 19)
3960 #define DUPS3_GATING_DIS (1 << 23)
3961 #define DPF_GATING_DIS (1 << 10)
3962 #define DPF_RAM_GATING_DIS (1 << 9)
3963 #define DPFR_GATING_DIS (1 << 8)
3965 #define CLKGATE_DIS_PSL(pipe) \
3966 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3969 * GEN10 clock gating regs
3971 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3972 #define SARBUNIT_CLKGATE_DIS (1 << 5)
3973 #define RCCUNIT_CLKGATE_DIS (1 << 7)
3974 #define MSCUNIT_CLKGATE_DIS (1 << 10)
3976 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
3977 #define GWUNIT_CLKGATE_DIS (1 << 16)
3979 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3980 #define VFUNIT_CLKGATE_DIS (1 << 20)
3982 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
3983 #define CGPSF_CLKGATE_DIS (1 << 3)
3986 * Display engine regs
3989 /* Pipe A CRC regs */
3990 #define _PIPE_CRC_CTL_A 0x60050
3991 #define PIPE_CRC_ENABLE (1 << 31)
3992 /* ivb+ source selection */
3993 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3994 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3995 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3996 /* ilk+ source selection */
3997 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3998 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3999 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
4000 /* embedded DP port on the north display block, reserved on ivb */
4001 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
4002 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
4003 /* vlv source selection */
4004 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
4005 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
4006 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
4007 /* with DP port the pipe source is invalid */
4008 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
4009 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
4010 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
4011 /* gen3+ source selection */
4012 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4013 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4014 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4015 /* with DP/TV port the pipe source is invalid */
4016 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4017 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4018 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4019 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4020 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4021 /* gen2 doesn't have source selection bits */
4022 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4024 #define _PIPE_CRC_RES_1_A_IVB 0x60064
4025 #define _PIPE_CRC_RES_2_A_IVB 0x60068
4026 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
4027 #define _PIPE_CRC_RES_4_A_IVB 0x60070
4028 #define _PIPE_CRC_RES_5_A_IVB 0x60074
4030 #define _PIPE_CRC_RES_RED_A 0x60060
4031 #define _PIPE_CRC_RES_GREEN_A 0x60064
4032 #define _PIPE_CRC_RES_BLUE_A 0x60068
4033 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4034 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4036 /* Pipe B CRC regs */
4037 #define _PIPE_CRC_RES_1_B_IVB 0x61064
4038 #define _PIPE_CRC_RES_2_B_IVB 0x61068
4039 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
4040 #define _PIPE_CRC_RES_4_B_IVB 0x61070
4041 #define _PIPE_CRC_RES_5_B_IVB 0x61074
4043 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4044 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4045 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4046 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4047 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4048 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4050 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4051 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4052 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4053 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4054 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4056 /* Pipe A timing regs */
4057 #define _HTOTAL_A 0x60000
4058 #define _HBLANK_A 0x60004
4059 #define _HSYNC_A 0x60008
4060 #define _VTOTAL_A 0x6000c
4061 #define _VBLANK_A 0x60010
4062 #define _VSYNC_A 0x60014
4063 #define _PIPEASRC 0x6001c
4064 #define _BCLRPAT_A 0x60020
4065 #define _VSYNCSHIFT_A 0x60028
4066 #define _PIPE_MULT_A 0x6002c
4068 /* Pipe B timing regs */
4069 #define _HTOTAL_B 0x61000
4070 #define _HBLANK_B 0x61004
4071 #define _HSYNC_B 0x61008
4072 #define _VTOTAL_B 0x6100c
4073 #define _VBLANK_B 0x61010
4074 #define _VSYNC_B 0x61014
4075 #define _PIPEBSRC 0x6101c
4076 #define _BCLRPAT_B 0x61020
4077 #define _VSYNCSHIFT_B 0x61028
4078 #define _PIPE_MULT_B 0x6102c
4080 /* DSI 0 timing regs */
4081 #define _HTOTAL_DSI0 0x6b000
4082 #define _HSYNC_DSI0 0x6b008
4083 #define _VTOTAL_DSI0 0x6b00c
4084 #define _VSYNC_DSI0 0x6b014
4085 #define _VSYNCSHIFT_DSI0 0x6b028
4087 /* DSI 1 timing regs */
4088 #define _HTOTAL_DSI1 0x6b800
4089 #define _HSYNC_DSI1 0x6b808
4090 #define _VTOTAL_DSI1 0x6b80c
4091 #define _VSYNC_DSI1 0x6b814
4092 #define _VSYNCSHIFT_DSI1 0x6b828
4094 #define TRANSCODER_A_OFFSET 0x60000
4095 #define TRANSCODER_B_OFFSET 0x61000
4096 #define TRANSCODER_C_OFFSET 0x62000
4097 #define CHV_TRANSCODER_C_OFFSET 0x63000
4098 #define TRANSCODER_EDP_OFFSET 0x6f000
4099 #define TRANSCODER_DSI0_OFFSET 0x6b000
4100 #define TRANSCODER_DSI1_OFFSET 0x6b800
4102 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4103 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4104 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4105 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4106 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4107 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4108 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4109 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4110 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4111 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4113 /* VLV eDP PSR registers */
4114 #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4115 #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4116 #define VLV_EDP_PSR_ENABLE (1 << 0)
4117 #define VLV_EDP_PSR_RESET (1 << 1)
4118 #define VLV_EDP_PSR_MODE_MASK (7 << 2)
4119 #define VLV_EDP_PSR_MODE_HW_TIMER (1 << 3)
4120 #define VLV_EDP_PSR_MODE_SW_TIMER (1 << 2)
4121 #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1 << 7)
4122 #define VLV_EDP_PSR_ACTIVE_ENTRY (1 << 8)
4123 #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1 << 9)
4124 #define VLV_EDP_PSR_DBL_FRAME (1 << 10)
4125 #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff << 16)
4126 #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4127 #define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4129 #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4130 #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4131 #define VLV_EDP_PSR_SDP_FREQ_MASK (3 << 30)
4132 #define VLV_EDP_PSR_SDP_FREQ_ONCE (1 << 31)
4133 #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1 << 30)
4134 #define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4136 #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4137 #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4138 #define VLV_EDP_PSR_LAST_STATE_MASK (7 << 3)
4139 #define VLV_EDP_PSR_CURR_STATE_MASK 7
4140 #define VLV_EDP_PSR_DISABLED (0 << 0)
4141 #define VLV_EDP_PSR_INACTIVE (1 << 0)
4142 #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2 << 0)
4143 #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3 << 0)
4144 #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4 << 0)
4145 #define VLV_EDP_PSR_EXIT (5 << 0)
4146 #define VLV_EDP_PSR_IN_TRANS (1 << 7)
4147 #define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4149 /* HSW+ eDP PSR registers */
4150 #define HSW_EDP_PSR_BASE 0x64800
4151 #define BDW_EDP_PSR_BASE 0x6f800
4152 #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4153 #define EDP_PSR_ENABLE (1 << 31)
4154 #define BDW_PSR_SINGLE_FRAME (1 << 30)
4155 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4156 #define EDP_PSR_LINK_STANDBY (1 << 27)
4157 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4158 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4159 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4160 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4161 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4162 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4163 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4164 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
4165 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
4166 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
4167 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4168 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4169 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4170 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4171 #define EDP_PSR_TP1_TIME_500us (0 << 4)
4172 #define EDP_PSR_TP1_TIME_100us (1 << 4)
4173 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
4174 #define EDP_PSR_TP1_TIME_0us (3 << 4)
4175 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4177 /* Bspec claims those aren't shifted but stay at 0x64800 */
4178 #define EDP_PSR_IMR _MMIO(0x64834)
4179 #define EDP_PSR_IIR _MMIO(0x64838)
4180 #define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
4181 #define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
4182 #define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
4183 #define EDP_PSR_TRANSCODER_C_SHIFT 24
4184 #define EDP_PSR_TRANSCODER_B_SHIFT 16
4185 #define EDP_PSR_TRANSCODER_A_SHIFT 8
4186 #define EDP_PSR_TRANSCODER_EDP_SHIFT 0
4188 #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4189 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4190 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4191 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4192 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4193 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4195 #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4197 #define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4198 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4199 #define EDP_PSR_STATUS_STATE_SHIFT 29
4200 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4201 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4202 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4203 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4204 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4205 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4206 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4207 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4208 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4209 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4210 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4211 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4212 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4213 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4214 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4215 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4216 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4217 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4218 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4219 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4220 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4222 #define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4223 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4225 #define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
4226 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4227 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4228 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4229 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4230 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4231 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4233 #define EDP_PSR2_CTL _MMIO(0x6f900)
4234 #define EDP_PSR2_ENABLE (1 << 31)
4235 #define EDP_SU_TRACK_ENABLE (1 << 30)
4236 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4237 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4238 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4239 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4240 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
4241 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
4242 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4243 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
4244 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4245 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4246 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4247 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4248 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
4249 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
4251 #define _PSR_EVENT_TRANS_A 0x60848
4252 #define _PSR_EVENT_TRANS_B 0x61848
4253 #define _PSR_EVENT_TRANS_C 0x62848
4254 #define _PSR_EVENT_TRANS_D 0x63848
4255 #define _PSR_EVENT_TRANS_EDP 0x6F848
4256 #define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
4257 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4258 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
4259 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4260 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4261 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4262 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4263 #define PSR_EVENT_MEMORY_UP (1 << 10)
4264 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4265 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4266 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4267 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4268 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
4269 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4270 #define PSR_EVENT_VBI_ENABLE (1 << 2)
4271 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4272 #define PSR_EVENT_PSR_DISABLE (1 << 0)
4274 #define EDP_PSR2_STATUS _MMIO(0x6f940)
4275 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4276 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4278 #define _PSR2_SU_STATUS_0 0x6F914
4279 #define _PSR2_SU_STATUS_1 0x6F918
4280 #define _PSR2_SU_STATUS_2 0x6F91C
4281 #define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
4282 #define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
4283 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4284 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4285 #define PSR2_SU_STATUS_FRAMES 8
4287 /* VGA port control */
4288 #define ADPA _MMIO(0x61100)
4289 #define PCH_ADPA _MMIO(0xe1100)
4290 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4292 #define ADPA_DAC_ENABLE (1 << 31)
4293 #define ADPA_DAC_DISABLE 0
4294 #define ADPA_PIPE_SEL_SHIFT 30
4295 #define ADPA_PIPE_SEL_MASK (1 << 30)
4296 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4297 #define ADPA_PIPE_SEL_SHIFT_CPT 29
4298 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4299 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4300 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4301 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4302 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4303 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4304 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4305 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4306 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4307 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4308 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4309 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4310 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4311 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4312 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4313 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4314 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4315 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4316 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4317 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4318 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4319 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4320 #define ADPA_SETS_HVPOLARITY 0
4321 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4322 #define ADPA_VSYNC_CNTL_ENABLE 0
4323 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4324 #define ADPA_HSYNC_CNTL_ENABLE 0
4325 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4326 #define ADPA_VSYNC_ACTIVE_LOW 0
4327 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4328 #define ADPA_HSYNC_ACTIVE_LOW 0
4329 #define ADPA_DPMS_MASK (~(3 << 10))
4330 #define ADPA_DPMS_ON (0 << 10)
4331 #define ADPA_DPMS_SUSPEND (1 << 10)
4332 #define ADPA_DPMS_STANDBY (2 << 10)
4333 #define ADPA_DPMS_OFF (3 << 10)
4336 /* Hotplug control (945+ only) */
4337 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4338 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4339 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4340 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4341 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4342 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4343 #define TV_HOTPLUG_INT_EN (1 << 18)
4344 #define CRT_HOTPLUG_INT_EN (1 << 9)
4345 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4346 PORTC_HOTPLUG_INT_EN | \
4347 PORTD_HOTPLUG_INT_EN | \
4348 SDVOC_HOTPLUG_INT_EN | \
4349 SDVOB_HOTPLUG_INT_EN | \
4351 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4352 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4353 /* must use period 64 on GM45 according to docs */
4354 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4355 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4356 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4357 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4358 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4359 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4360 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4361 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4362 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4363 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4364 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4365 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4367 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4369 * HDMI/DP bits are g4x+
4371 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4372 * Please check the detailed lore in the commit message for for experimental
4375 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4376 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4377 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4378 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4379 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4380 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4381 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4382 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4383 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4384 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4385 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4386 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4387 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4388 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4389 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4390 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4391 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4392 /* CRT/TV common between gen3+ */
4393 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4394 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4395 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4396 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4397 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4398 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4399 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4400 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4401 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4402 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4404 /* SDVO is different across gen3/4 */
4405 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4406 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4408 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4409 * since reality corrobates that they're the same as on gen3. But keep these
4410 * bits here (and the comment!) to help any other lost wanderers back onto the
4413 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4414 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4415 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4416 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4417 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4418 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4419 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4420 PORTB_HOTPLUG_INT_STATUS | \
4421 PORTC_HOTPLUG_INT_STATUS | \
4422 PORTD_HOTPLUG_INT_STATUS)
4424 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4425 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4426 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4427 PORTB_HOTPLUG_INT_STATUS | \
4428 PORTC_HOTPLUG_INT_STATUS | \
4429 PORTD_HOTPLUG_INT_STATUS)
4431 /* SDVO and HDMI port control.
4432 * The same register may be used for SDVO or HDMI */
4433 #define _GEN3_SDVOB 0x61140
4434 #define _GEN3_SDVOC 0x61160
4435 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4436 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4437 #define GEN4_HDMIB GEN3_SDVOB
4438 #define GEN4_HDMIC GEN3_SDVOC
4439 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4440 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4441 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4442 #define PCH_SDVOB _MMIO(0xe1140)
4443 #define PCH_HDMIB PCH_SDVOB
4444 #define PCH_HDMIC _MMIO(0xe1150)
4445 #define PCH_HDMID _MMIO(0xe1160)
4447 #define PORT_DFT_I9XX _MMIO(0x61150)
4448 #define DC_BALANCE_RESET (1 << 25)
4449 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4450 #define DC_BALANCE_RESET_VLV (1 << 31)
4451 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4452 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4453 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4454 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4456 /* Gen 3 SDVO bits: */
4457 #define SDVO_ENABLE (1 << 31)
4458 #define SDVO_PIPE_SEL_SHIFT 30
4459 #define SDVO_PIPE_SEL_MASK (1 << 30)
4460 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4461 #define SDVO_STALL_SELECT (1 << 29)
4462 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4464 * 915G/GM SDVO pixel multiplier.
4465 * Programmed value is multiplier - 1, up to 5x.
4466 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4468 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4469 #define SDVO_PORT_MULTIPLY_SHIFT 23
4470 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4471 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4472 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4473 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4474 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4475 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4476 #define SDVO_DETECTED (1 << 2)
4477 /* Bits to be preserved when writing */
4478 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4479 SDVO_INTERRUPT_ENABLE)
4480 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4482 /* Gen 4 SDVO/HDMI bits: */
4483 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4484 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4485 #define SDVO_ENCODING_SDVO (0 << 10)
4486 #define SDVO_ENCODING_HDMI (2 << 10)
4487 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4488 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4489 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4490 #define SDVO_AUDIO_ENABLE (1 << 6)
4491 /* VSYNC/HSYNC bits new with 965, default is to be set */
4492 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4493 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4495 /* Gen 5 (IBX) SDVO/HDMI bits: */
4496 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4497 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4499 /* Gen 6 (CPT) SDVO/HDMI bits: */
4500 #define SDVO_PIPE_SEL_SHIFT_CPT 29
4501 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4502 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4504 /* CHV SDVO/HDMI bits: */
4505 #define SDVO_PIPE_SEL_SHIFT_CHV 24
4506 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4507 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4510 /* DVO port control */
4511 #define _DVOA 0x61120
4512 #define DVOA _MMIO(_DVOA)
4513 #define _DVOB 0x61140
4514 #define DVOB _MMIO(_DVOB)
4515 #define _DVOC 0x61160
4516 #define DVOC _MMIO(_DVOC)
4517 #define DVO_ENABLE (1 << 31)
4518 #define DVO_PIPE_SEL_SHIFT 30
4519 #define DVO_PIPE_SEL_MASK (1 << 30)
4520 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4521 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4522 #define DVO_PIPE_STALL (1 << 28)
4523 #define DVO_PIPE_STALL_TV (2 << 28)
4524 #define DVO_PIPE_STALL_MASK (3 << 28)
4525 #define DVO_USE_VGA_SYNC (1 << 15)
4526 #define DVO_DATA_ORDER_I740 (0 << 14)
4527 #define DVO_DATA_ORDER_FP (1 << 14)
4528 #define DVO_VSYNC_DISABLE (1 << 11)
4529 #define DVO_HSYNC_DISABLE (1 << 10)
4530 #define DVO_VSYNC_TRISTATE (1 << 9)
4531 #define DVO_HSYNC_TRISTATE (1 << 8)
4532 #define DVO_BORDER_ENABLE (1 << 7)
4533 #define DVO_DATA_ORDER_GBRG (1 << 6)
4534 #define DVO_DATA_ORDER_RGGB (0 << 6)
4535 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4536 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4537 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4538 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4539 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4540 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4541 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4542 #define DVO_PRESERVE_MASK (0x7 << 24)
4543 #define DVOA_SRCDIM _MMIO(0x61124)
4544 #define DVOB_SRCDIM _MMIO(0x61144)
4545 #define DVOC_SRCDIM _MMIO(0x61164)
4546 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4547 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4549 /* LVDS port control */
4550 #define LVDS _MMIO(0x61180)
4552 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4553 * the DPLL semantics change when the LVDS is assigned to that pipe.
4555 #define LVDS_PORT_EN (1 << 31)
4556 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4557 #define LVDS_PIPE_SEL_SHIFT 30
4558 #define LVDS_PIPE_SEL_MASK (1 << 30)
4559 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
4560 #define LVDS_PIPE_SEL_SHIFT_CPT 29
4561 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
4562 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4563 /* LVDS dithering flag on 965/g4x platform */
4564 #define LVDS_ENABLE_DITHER (1 << 25)
4565 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4566 #define LVDS_VSYNC_POLARITY (1 << 21)
4567 #define LVDS_HSYNC_POLARITY (1 << 20)
4569 /* Enable border for unscaled (or aspect-scaled) display */
4570 #define LVDS_BORDER_ENABLE (1 << 15)
4572 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4575 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4576 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4577 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4579 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4580 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4583 #define LVDS_A3_POWER_MASK (3 << 6)
4584 #define LVDS_A3_POWER_DOWN (0 << 6)
4585 #define LVDS_A3_POWER_UP (3 << 6)
4587 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4590 #define LVDS_CLKB_POWER_MASK (3 << 4)
4591 #define LVDS_CLKB_POWER_DOWN (0 << 4)
4592 #define LVDS_CLKB_POWER_UP (3 << 4)
4594 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4595 * setting for whether we are in dual-channel mode. The B3 pair will
4596 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4598 #define LVDS_B0B3_POWER_MASK (3 << 2)
4599 #define LVDS_B0B3_POWER_DOWN (0 << 2)
4600 #define LVDS_B0B3_POWER_UP (3 << 2)
4602 /* Video Data Island Packet control */
4603 #define VIDEO_DIP_DATA _MMIO(0x61178)
4604 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4605 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4606 * of the infoframe structure specified by CEA-861. */
4607 #define VIDEO_DIP_DATA_SIZE 32
4608 #define VIDEO_DIP_VSC_DATA_SIZE 36
4609 #define VIDEO_DIP_PPS_DATA_SIZE 132
4610 #define VIDEO_DIP_CTL _MMIO(0x61170)
4612 #define VIDEO_DIP_ENABLE (1 << 31)
4613 #define VIDEO_DIP_PORT(port) ((port) << 29)
4614 #define VIDEO_DIP_PORT_MASK (3 << 29)
4615 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
4616 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
4617 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4618 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4619 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
4620 #define VIDEO_DIP_SELECT_AVI (0 << 19)
4621 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4622 #define VIDEO_DIP_SELECT_SPD (3 << 19)
4623 #define VIDEO_DIP_SELECT_MASK (3 << 19)
4624 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
4625 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4626 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4627 #define VIDEO_DIP_FREQ_MASK (3 << 16)
4628 /* HSW and later: */
4629 #define DRM_DIP_ENABLE (1 << 28)
4630 #define PSR_VSC_BIT_7_SET (1 << 27)
4631 #define VSC_SELECT_MASK (0x3 << 25)
4632 #define VSC_SELECT_SHIFT 25
4633 #define VSC_DIP_HW_HEA_DATA (0 << 25)
4634 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4635 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4636 #define VSC_DIP_SW_HEA_DATA (3 << 25)
4637 #define VDIP_ENABLE_PPS (1 << 24)
4638 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4639 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4640 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4641 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4642 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4643 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4645 /* Panel power sequencing */
4646 #define PPS_BASE 0x61200
4647 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4648 #define PCH_PPS_BASE 0xC7200
4650 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4651 PPS_BASE + (reg) + \
4654 #define _PP_STATUS 0x61200
4655 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4656 #define PP_ON (1 << 31)
4658 #define _PP_CONTROL_1 0xc7204
4659 #define _PP_CONTROL_2 0xc7304
4660 #define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
4662 #define POWER_CYCLE_DELAY_MASK (0x1f << 4)
4663 #define POWER_CYCLE_DELAY_SHIFT 4
4664 #define VDD_OVERRIDE_FORCE (1 << 3)
4665 #define BACKLIGHT_ENABLE (1 << 2)
4666 #define PWR_DOWN_ON_RESET (1 << 1)
4667 #define PWR_STATE_TARGET (1 << 0)
4669 * Indicates that all dependencies of the panel are on:
4673 * - LVDS/DVOB/DVOC on
4675 #define PP_READY (1 << 30)
4676 #define PP_SEQUENCE_NONE (0 << 28)
4677 #define PP_SEQUENCE_POWER_UP (1 << 28)
4678 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
4679 #define PP_SEQUENCE_MASK (3 << 28)
4680 #define PP_SEQUENCE_SHIFT 28
4681 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4682 #define PP_SEQUENCE_STATE_MASK 0x0000000f
4683 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4684 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4685 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4686 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4687 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4688 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4689 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4690 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4691 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
4693 #define _PP_CONTROL 0x61204
4694 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4695 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4696 #define PANEL_UNLOCK_MASK (0xffff << 16)
4697 #define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4698 #define BXT_POWER_CYCLE_DELAY_SHIFT 4
4699 #define EDP_FORCE_VDD (1 << 3)
4700 #define EDP_BLC_ENABLE (1 << 2)
4701 #define PANEL_POWER_RESET (1 << 1)
4702 #define PANEL_POWER_ON (1 << 0)
4704 #define _PP_ON_DELAYS 0x61208
4705 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4706 #define PANEL_PORT_SELECT_SHIFT 30
4707 #define PANEL_PORT_SELECT_MASK (3 << 30)
4708 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4709 #define PANEL_PORT_SELECT_DPA (1 << 30)
4710 #define PANEL_PORT_SELECT_DPC (2 << 30)
4711 #define PANEL_PORT_SELECT_DPD (3 << 30)
4712 #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4713 #define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4714 #define PANEL_POWER_UP_DELAY_SHIFT 16
4715 #define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4716 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4718 #define _PP_OFF_DELAYS 0x6120C
4719 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4720 #define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4721 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4722 #define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4723 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4725 #define _PP_DIVISOR 0x61210
4726 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4727 #define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4728 #define PP_REFERENCE_DIVIDER_SHIFT 8
4729 #define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4730 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4733 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
4734 #define PFIT_ENABLE (1 << 31)
4735 #define PFIT_PIPE_MASK (3 << 29)
4736 #define PFIT_PIPE_SHIFT 29
4737 #define VERT_INTERP_DISABLE (0 << 10)
4738 #define VERT_INTERP_BILINEAR (1 << 10)
4739 #define VERT_INTERP_MASK (3 << 10)
4740 #define VERT_AUTO_SCALE (1 << 9)
4741 #define HORIZ_INTERP_DISABLE (0 << 6)
4742 #define HORIZ_INTERP_BILINEAR (1 << 6)
4743 #define HORIZ_INTERP_MASK (3 << 6)
4744 #define HORIZ_AUTO_SCALE (1 << 5)
4745 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4746 #define PFIT_FILTER_FUZZY (0 << 24)
4747 #define PFIT_SCALING_AUTO (0 << 26)
4748 #define PFIT_SCALING_PROGRAMMED (1 << 26)
4749 #define PFIT_SCALING_PILLAR (2 << 26)
4750 #define PFIT_SCALING_LETTER (3 << 26)
4751 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
4753 #define PFIT_VERT_SCALE_SHIFT 20
4754 #define PFIT_VERT_SCALE_MASK 0xfff00000
4755 #define PFIT_HORIZ_SCALE_SHIFT 4
4756 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4758 #define PFIT_VERT_SCALE_SHIFT_965 16
4759 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4760 #define PFIT_HORIZ_SCALE_SHIFT_965 0
4761 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4763 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
4765 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
4766 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
4767 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4768 _VLV_BLC_PWM_CTL2_B)
4770 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4771 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
4772 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4775 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4776 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
4777 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4778 _VLV_BLC_HIST_CTL_B)
4780 /* Backlight control */
4781 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
4782 #define BLM_PWM_ENABLE (1 << 31)
4783 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4784 #define BLM_PIPE_SELECT (1 << 29)
4785 #define BLM_PIPE_SELECT_IVB (3 << 29)
4786 #define BLM_PIPE_A (0 << 29)
4787 #define BLM_PIPE_B (1 << 29)
4788 #define BLM_PIPE_C (2 << 29) /* ivb + */
4789 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4790 #define BLM_TRANSCODER_B BLM_PIPE_B
4791 #define BLM_TRANSCODER_C BLM_PIPE_C
4792 #define BLM_TRANSCODER_EDP (3 << 29)
4793 #define BLM_PIPE(pipe) ((pipe) << 29)
4794 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4795 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4796 #define BLM_PHASE_IN_ENABLE (1 << 25)
4797 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4798 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4799 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4800 #define BLM_PHASE_IN_COUNT_SHIFT (8)
4801 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4802 #define BLM_PHASE_IN_INCR_SHIFT (0)
4803 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4804 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
4806 * This is the most significant 15 bits of the number of backlight cycles in a
4807 * complete cycle of the modulated backlight control.
4809 * The actual value is this field multiplied by two.
4811 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4812 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4813 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4815 * This is the number of cycles out of the backlight modulation cycle for which
4816 * the backlight is on.
4818 * This field must be no greater than the number of cycles in the complete
4819 * backlight modulation cycle.
4821 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4822 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4823 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4824 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4826 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
4827 #define BLM_HISTOGRAM_ENABLE (1 << 31)
4829 /* New registers for PCH-split platforms. Safe where new bits show up, the
4830 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4831 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4832 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
4834 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4836 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4837 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4838 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4839 #define BLM_PCH_PWM_ENABLE (1 << 31)
4840 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4841 #define BLM_PCH_POLARITY (1 << 29)
4842 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4844 #define UTIL_PIN_CTL _MMIO(0x48400)
4845 #define UTIL_PIN_ENABLE (1 << 31)
4847 #define UTIL_PIN_PIPE(x) ((x) << 29)
4848 #define UTIL_PIN_PIPE_MASK (3 << 29)
4849 #define UTIL_PIN_MODE_PWM (1 << 24)
4850 #define UTIL_PIN_MODE_MASK (0xf << 24)
4851 #define UTIL_PIN_POLARITY (1 << 22)
4853 /* BXT backlight register definition. */
4854 #define _BXT_BLC_PWM_CTL1 0xC8250
4855 #define BXT_BLC_PWM_ENABLE (1 << 31)
4856 #define BXT_BLC_PWM_POLARITY (1 << 29)
4857 #define _BXT_BLC_PWM_FREQ1 0xC8254
4858 #define _BXT_BLC_PWM_DUTY1 0xC8258
4860 #define _BXT_BLC_PWM_CTL2 0xC8350
4861 #define _BXT_BLC_PWM_FREQ2 0xC8354
4862 #define _BXT_BLC_PWM_DUTY2 0xC8358
4864 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4865 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4866 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4867 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4868 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4869 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4871 #define PCH_GTC_CTL _MMIO(0xe7000)
4872 #define PCH_GTC_ENABLE (1 << 31)
4874 /* TV port control */
4875 #define TV_CTL _MMIO(0x68000)
4876 /* Enables the TV encoder */
4877 # define TV_ENC_ENABLE (1 << 31)
4878 /* Sources the TV encoder input from pipe B instead of A. */
4879 # define TV_ENC_PIPE_SEL_SHIFT 30
4880 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
4881 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
4882 /* Outputs composite video (DAC A only) */
4883 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4884 /* Outputs SVideo video (DAC B/C) */
4885 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4886 /* Outputs Component video (DAC A/B/C) */
4887 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4888 /* Outputs Composite and SVideo (DAC A/B/C) */
4889 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4890 # define TV_TRILEVEL_SYNC (1 << 21)
4891 /* Enables slow sync generation (945GM only) */
4892 # define TV_SLOW_SYNC (1 << 20)
4893 /* Selects 4x oversampling for 480i and 576p */
4894 # define TV_OVERSAMPLE_4X (0 << 18)
4895 /* Selects 2x oversampling for 720p and 1080i */
4896 # define TV_OVERSAMPLE_2X (1 << 18)
4897 /* Selects no oversampling for 1080p */
4898 # define TV_OVERSAMPLE_NONE (2 << 18)
4899 /* Selects 8x oversampling */
4900 # define TV_OVERSAMPLE_8X (3 << 18)
4901 # define TV_OVERSAMPLE_MASK (3 << 18)
4902 /* Selects progressive mode rather than interlaced */
4903 # define TV_PROGRESSIVE (1 << 17)
4904 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4905 # define TV_PAL_BURST (1 << 16)
4906 /* Field for setting delay of Y compared to C */
4907 # define TV_YC_SKEW_MASK (7 << 12)
4908 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4909 # define TV_ENC_SDP_FIX (1 << 11)
4911 * Enables a fix for the 915GM only.
4913 * Not sure what it does.
4915 # define TV_ENC_C0_FIX (1 << 10)
4916 /* Bits that must be preserved by software */
4917 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4918 # define TV_FUSE_STATE_MASK (3 << 4)
4919 /* Read-only state that reports all features enabled */
4920 # define TV_FUSE_STATE_ENABLED (0 << 4)
4921 /* Read-only state that reports that Macrovision is disabled in hardware*/
4922 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4923 /* Read-only state that reports that TV-out is disabled in hardware. */
4924 # define TV_FUSE_STATE_DISABLED (2 << 4)
4925 /* Normal operation */
4926 # define TV_TEST_MODE_NORMAL (0 << 0)
4927 /* Encoder test pattern 1 - combo pattern */
4928 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
4929 /* Encoder test pattern 2 - full screen vertical 75% color bars */
4930 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
4931 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
4932 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
4933 /* Encoder test pattern 4 - random noise */
4934 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
4935 /* Encoder test pattern 5 - linear color ramps */
4936 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
4938 * This test mode forces the DACs to 50% of full output.
4940 * This is used for load detection in combination with TVDAC_SENSE_MASK
4942 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4943 # define TV_TEST_MODE_MASK (7 << 0)
4945 #define TV_DAC _MMIO(0x68004)
4946 # define TV_DAC_SAVE 0x00ffff00
4948 * Reports that DAC state change logic has reported change (RO).
4950 * This gets cleared when TV_DAC_STATE_EN is cleared
4952 # define TVDAC_STATE_CHG (1 << 31)
4953 # define TVDAC_SENSE_MASK (7 << 28)
4954 /* Reports that DAC A voltage is above the detect threshold */
4955 # define TVDAC_A_SENSE (1 << 30)
4956 /* Reports that DAC B voltage is above the detect threshold */
4957 # define TVDAC_B_SENSE (1 << 29)
4958 /* Reports that DAC C voltage is above the detect threshold */
4959 # define TVDAC_C_SENSE (1 << 28)
4961 * Enables DAC state detection logic, for load-based TV detection.
4963 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4964 * to off, for load detection to work.
4966 # define TVDAC_STATE_CHG_EN (1 << 27)
4967 /* Sets the DAC A sense value to high */
4968 # define TVDAC_A_SENSE_CTL (1 << 26)
4969 /* Sets the DAC B sense value to high */
4970 # define TVDAC_B_SENSE_CTL (1 << 25)
4971 /* Sets the DAC C sense value to high */
4972 # define TVDAC_C_SENSE_CTL (1 << 24)
4973 /* Overrides the ENC_ENABLE and DAC voltage levels */
4974 # define DAC_CTL_OVERRIDE (1 << 7)
4975 /* Sets the slew rate. Must be preserved in software */
4976 # define ENC_TVDAC_SLEW_FAST (1 << 6)
4977 # define DAC_A_1_3_V (0 << 4)
4978 # define DAC_A_1_1_V (1 << 4)
4979 # define DAC_A_0_7_V (2 << 4)
4980 # define DAC_A_MASK (3 << 4)
4981 # define DAC_B_1_3_V (0 << 2)
4982 # define DAC_B_1_1_V (1 << 2)
4983 # define DAC_B_0_7_V (2 << 2)
4984 # define DAC_B_MASK (3 << 2)
4985 # define DAC_C_1_3_V (0 << 0)
4986 # define DAC_C_1_1_V (1 << 0)
4987 # define DAC_C_0_7_V (2 << 0)
4988 # define DAC_C_MASK (3 << 0)
4991 * CSC coefficients are stored in a floating point format with 9 bits of
4992 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4993 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4994 * -1 (0x3) being the only legal negative value.
4996 #define TV_CSC_Y _MMIO(0x68010)
4997 # define TV_RY_MASK 0x07ff0000
4998 # define TV_RY_SHIFT 16
4999 # define TV_GY_MASK 0x00000fff
5000 # define TV_GY_SHIFT 0
5002 #define TV_CSC_Y2 _MMIO(0x68014)
5003 # define TV_BY_MASK 0x07ff0000
5004 # define TV_BY_SHIFT 16
5006 * Y attenuation for component video.
5008 * Stored in 1.9 fixed point.
5010 # define TV_AY_MASK 0x000003ff
5011 # define TV_AY_SHIFT 0
5013 #define TV_CSC_U _MMIO(0x68018)
5014 # define TV_RU_MASK 0x07ff0000
5015 # define TV_RU_SHIFT 16
5016 # define TV_GU_MASK 0x000007ff
5017 # define TV_GU_SHIFT 0
5019 #define TV_CSC_U2 _MMIO(0x6801c)
5020 # define TV_BU_MASK 0x07ff0000
5021 # define TV_BU_SHIFT 16
5023 * U attenuation for component video.
5025 * Stored in 1.9 fixed point.
5027 # define TV_AU_MASK 0x000003ff
5028 # define TV_AU_SHIFT 0
5030 #define TV_CSC_V _MMIO(0x68020)
5031 # define TV_RV_MASK 0x0fff0000
5032 # define TV_RV_SHIFT 16
5033 # define TV_GV_MASK 0x000007ff
5034 # define TV_GV_SHIFT 0
5036 #define TV_CSC_V2 _MMIO(0x68024)
5037 # define TV_BV_MASK 0x07ff0000
5038 # define TV_BV_SHIFT 16
5040 * V attenuation for component video.
5042 * Stored in 1.9 fixed point.
5044 # define TV_AV_MASK 0x000007ff
5045 # define TV_AV_SHIFT 0
5047 #define TV_CLR_KNOBS _MMIO(0x68028)
5048 /* 2s-complement brightness adjustment */
5049 # define TV_BRIGHTNESS_MASK 0xff000000
5050 # define TV_BRIGHTNESS_SHIFT 24
5051 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5052 # define TV_CONTRAST_MASK 0x00ff0000
5053 # define TV_CONTRAST_SHIFT 16
5054 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5055 # define TV_SATURATION_MASK 0x0000ff00
5056 # define TV_SATURATION_SHIFT 8
5057 /* Hue adjustment, as an integer phase angle in degrees */
5058 # define TV_HUE_MASK 0x000000ff
5059 # define TV_HUE_SHIFT 0
5061 #define TV_CLR_LEVEL _MMIO(0x6802c)
5062 /* Controls the DAC level for black */
5063 # define TV_BLACK_LEVEL_MASK 0x01ff0000
5064 # define TV_BLACK_LEVEL_SHIFT 16
5065 /* Controls the DAC level for blanking */
5066 # define TV_BLANK_LEVEL_MASK 0x000001ff
5067 # define TV_BLANK_LEVEL_SHIFT 0
5069 #define TV_H_CTL_1 _MMIO(0x68030)
5070 /* Number of pixels in the hsync. */
5071 # define TV_HSYNC_END_MASK 0x1fff0000
5072 # define TV_HSYNC_END_SHIFT 16
5073 /* Total number of pixels minus one in the line (display and blanking). */
5074 # define TV_HTOTAL_MASK 0x00001fff
5075 # define TV_HTOTAL_SHIFT 0
5077 #define TV_H_CTL_2 _MMIO(0x68034)
5078 /* Enables the colorburst (needed for non-component color) */
5079 # define TV_BURST_ENA (1 << 31)
5080 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5081 # define TV_HBURST_START_SHIFT 16
5082 # define TV_HBURST_START_MASK 0x1fff0000
5083 /* Length of the colorburst */
5084 # define TV_HBURST_LEN_SHIFT 0
5085 # define TV_HBURST_LEN_MASK 0x0001fff
5087 #define TV_H_CTL_3 _MMIO(0x68038)
5088 /* End of hblank, measured in pixels minus one from start of hsync */
5089 # define TV_HBLANK_END_SHIFT 16
5090 # define TV_HBLANK_END_MASK 0x1fff0000
5091 /* Start of hblank, measured in pixels minus one from start of hsync */
5092 # define TV_HBLANK_START_SHIFT 0
5093 # define TV_HBLANK_START_MASK 0x0001fff
5095 #define TV_V_CTL_1 _MMIO(0x6803c)
5097 # define TV_NBR_END_SHIFT 16
5098 # define TV_NBR_END_MASK 0x07ff0000
5100 # define TV_VI_END_F1_SHIFT 8
5101 # define TV_VI_END_F1_MASK 0x00003f00
5103 # define TV_VI_END_F2_SHIFT 0
5104 # define TV_VI_END_F2_MASK 0x0000003f
5106 #define TV_V_CTL_2 _MMIO(0x68040)
5107 /* Length of vsync, in half lines */
5108 # define TV_VSYNC_LEN_MASK 0x07ff0000
5109 # define TV_VSYNC_LEN_SHIFT 16
5110 /* Offset of the start of vsync in field 1, measured in one less than the
5111 * number of half lines.
5113 # define TV_VSYNC_START_F1_MASK 0x00007f00
5114 # define TV_VSYNC_START_F1_SHIFT 8
5116 * Offset of the start of vsync in field 2, measured in one less than the
5117 * number of half lines.
5119 # define TV_VSYNC_START_F2_MASK 0x0000007f
5120 # define TV_VSYNC_START_F2_SHIFT 0
5122 #define TV_V_CTL_3 _MMIO(0x68044)
5123 /* Enables generation of the equalization signal */
5124 # define TV_EQUAL_ENA (1 << 31)
5125 /* Length of vsync, in half lines */
5126 # define TV_VEQ_LEN_MASK 0x007f0000
5127 # define TV_VEQ_LEN_SHIFT 16
5128 /* Offset of the start of equalization in field 1, measured in one less than
5129 * the number of half lines.
5131 # define TV_VEQ_START_F1_MASK 0x0007f00
5132 # define TV_VEQ_START_F1_SHIFT 8
5134 * Offset of the start of equalization in field 2, measured in one less than
5135 * the number of half lines.
5137 # define TV_VEQ_START_F2_MASK 0x000007f
5138 # define TV_VEQ_START_F2_SHIFT 0
5140 #define TV_V_CTL_4 _MMIO(0x68048)
5142 * Offset to start of vertical colorburst, measured in one less than the
5143 * number of lines from vertical start.
5145 # define TV_VBURST_START_F1_MASK 0x003f0000
5146 # define TV_VBURST_START_F1_SHIFT 16
5148 * Offset to the end of vertical colorburst, measured in one less than the
5149 * number of lines from the start of NBR.
5151 # define TV_VBURST_END_F1_MASK 0x000000ff
5152 # define TV_VBURST_END_F1_SHIFT 0
5154 #define TV_V_CTL_5 _MMIO(0x6804c)
5156 * Offset to start of vertical colorburst, measured in one less than the
5157 * number of lines from vertical start.
5159 # define TV_VBURST_START_F2_MASK 0x003f0000
5160 # define TV_VBURST_START_F2_SHIFT 16
5162 * Offset to the end of vertical colorburst, measured in one less than the
5163 * number of lines from the start of NBR.
5165 # define TV_VBURST_END_F2_MASK 0x000000ff
5166 # define TV_VBURST_END_F2_SHIFT 0
5168 #define TV_V_CTL_6 _MMIO(0x68050)
5170 * Offset to start of vertical colorburst, measured in one less than the
5171 * number of lines from vertical start.
5173 # define TV_VBURST_START_F3_MASK 0x003f0000
5174 # define TV_VBURST_START_F3_SHIFT 16
5176 * Offset to the end of vertical colorburst, measured in one less than the
5177 * number of lines from the start of NBR.
5179 # define TV_VBURST_END_F3_MASK 0x000000ff
5180 # define TV_VBURST_END_F3_SHIFT 0
5182 #define TV_V_CTL_7 _MMIO(0x68054)
5184 * Offset to start of vertical colorburst, measured in one less than the
5185 * number of lines from vertical start.
5187 # define TV_VBURST_START_F4_MASK 0x003f0000
5188 # define TV_VBURST_START_F4_SHIFT 16
5190 * Offset to the end of vertical colorburst, measured in one less than the
5191 * number of lines from the start of NBR.
5193 # define TV_VBURST_END_F4_MASK 0x000000ff
5194 # define TV_VBURST_END_F4_SHIFT 0
5196 #define TV_SC_CTL_1 _MMIO(0x68060)
5197 /* Turns on the first subcarrier phase generation DDA */
5198 # define TV_SC_DDA1_EN (1 << 31)
5199 /* Turns on the first subcarrier phase generation DDA */
5200 # define TV_SC_DDA2_EN (1 << 30)
5201 /* Turns on the first subcarrier phase generation DDA */
5202 # define TV_SC_DDA3_EN (1 << 29)
5203 /* Sets the subcarrier DDA to reset frequency every other field */
5204 # define TV_SC_RESET_EVERY_2 (0 << 24)
5205 /* Sets the subcarrier DDA to reset frequency every fourth field */
5206 # define TV_SC_RESET_EVERY_4 (1 << 24)
5207 /* Sets the subcarrier DDA to reset frequency every eighth field */
5208 # define TV_SC_RESET_EVERY_8 (2 << 24)
5209 /* Sets the subcarrier DDA to never reset the frequency */
5210 # define TV_SC_RESET_NEVER (3 << 24)
5211 /* Sets the peak amplitude of the colorburst.*/
5212 # define TV_BURST_LEVEL_MASK 0x00ff0000
5213 # define TV_BURST_LEVEL_SHIFT 16
5214 /* Sets the increment of the first subcarrier phase generation DDA */
5215 # define TV_SCDDA1_INC_MASK 0x00000fff
5216 # define TV_SCDDA1_INC_SHIFT 0
5218 #define TV_SC_CTL_2 _MMIO(0x68064)
5219 /* Sets the rollover for the second subcarrier phase generation DDA */
5220 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5221 # define TV_SCDDA2_SIZE_SHIFT 16
5222 /* Sets the increent of the second subcarrier phase generation DDA */
5223 # define TV_SCDDA2_INC_MASK 0x00007fff
5224 # define TV_SCDDA2_INC_SHIFT 0
5226 #define TV_SC_CTL_3 _MMIO(0x68068)
5227 /* Sets the rollover for the third subcarrier phase generation DDA */
5228 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5229 # define TV_SCDDA3_SIZE_SHIFT 16
5230 /* Sets the increent of the third subcarrier phase generation DDA */
5231 # define TV_SCDDA3_INC_MASK 0x00007fff
5232 # define TV_SCDDA3_INC_SHIFT 0
5234 #define TV_WIN_POS _MMIO(0x68070)
5235 /* X coordinate of the display from the start of horizontal active */
5236 # define TV_XPOS_MASK 0x1fff0000
5237 # define TV_XPOS_SHIFT 16
5238 /* Y coordinate of the display from the start of vertical active (NBR) */
5239 # define TV_YPOS_MASK 0x00000fff
5240 # define TV_YPOS_SHIFT 0
5242 #define TV_WIN_SIZE _MMIO(0x68074)
5243 /* Horizontal size of the display window, measured in pixels*/
5244 # define TV_XSIZE_MASK 0x1fff0000
5245 # define TV_XSIZE_SHIFT 16
5247 * Vertical size of the display window, measured in pixels.
5249 * Must be even for interlaced modes.
5251 # define TV_YSIZE_MASK 0x00000fff
5252 # define TV_YSIZE_SHIFT 0
5254 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5256 * Enables automatic scaling calculation.
5258 * If set, the rest of the registers are ignored, and the calculated values can
5259 * be read back from the register.
5261 # define TV_AUTO_SCALE (1 << 31)
5263 * Disables the vertical filter.
5265 * This is required on modes more than 1024 pixels wide */
5266 # define TV_V_FILTER_BYPASS (1 << 29)
5267 /* Enables adaptive vertical filtering */
5268 # define TV_VADAPT (1 << 28)
5269 # define TV_VADAPT_MODE_MASK (3 << 26)
5270 /* Selects the least adaptive vertical filtering mode */
5271 # define TV_VADAPT_MODE_LEAST (0 << 26)
5272 /* Selects the moderately adaptive vertical filtering mode */
5273 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5274 /* Selects the most adaptive vertical filtering mode */
5275 # define TV_VADAPT_MODE_MOST (3 << 26)
5277 * Sets the horizontal scaling factor.
5279 * This should be the fractional part of the horizontal scaling factor divided
5280 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5282 * (src width - 1) / ((oversample * dest width) - 1)
5284 # define TV_HSCALE_FRAC_MASK 0x00003fff
5285 # define TV_HSCALE_FRAC_SHIFT 0
5287 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5289 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5291 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5293 # define TV_VSCALE_INT_MASK 0x00038000
5294 # define TV_VSCALE_INT_SHIFT 15
5296 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5298 * \sa TV_VSCALE_INT_MASK
5300 # define TV_VSCALE_FRAC_MASK 0x00007fff
5301 # define TV_VSCALE_FRAC_SHIFT 0
5303 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5305 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5307 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5309 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5311 # define TV_VSCALE_IP_INT_MASK 0x00038000
5312 # define TV_VSCALE_IP_INT_SHIFT 15
5314 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5316 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5318 * \sa TV_VSCALE_IP_INT_MASK
5320 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5321 # define TV_VSCALE_IP_FRAC_SHIFT 0
5323 #define TV_CC_CONTROL _MMIO(0x68090)
5324 # define TV_CC_ENABLE (1 << 31)
5326 * Specifies which field to send the CC data in.
5328 * CC data is usually sent in field 0.
5330 # define TV_CC_FID_MASK (1 << 27)
5331 # define TV_CC_FID_SHIFT 27
5332 /* Sets the horizontal position of the CC data. Usually 135. */
5333 # define TV_CC_HOFF_MASK 0x03ff0000
5334 # define TV_CC_HOFF_SHIFT 16
5335 /* Sets the vertical position of the CC data. Usually 21 */
5336 # define TV_CC_LINE_MASK 0x0000003f
5337 # define TV_CC_LINE_SHIFT 0
5339 #define TV_CC_DATA _MMIO(0x68094)
5340 # define TV_CC_RDY (1 << 31)
5341 /* Second word of CC data to be transmitted. */
5342 # define TV_CC_DATA_2_MASK 0x007f0000
5343 # define TV_CC_DATA_2_SHIFT 16
5344 /* First word of CC data to be transmitted. */
5345 # define TV_CC_DATA_1_MASK 0x0000007f
5346 # define TV_CC_DATA_1_SHIFT 0
5348 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5349 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5350 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5351 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5354 #define DP_A _MMIO(0x64000) /* eDP */
5355 #define DP_B _MMIO(0x64100)
5356 #define DP_C _MMIO(0x64200)
5357 #define DP_D _MMIO(0x64300)
5359 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5360 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5361 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5363 #define DP_PORT_EN (1 << 31)
5364 #define DP_PIPE_SEL_SHIFT 30
5365 #define DP_PIPE_SEL_MASK (1 << 30)
5366 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
5367 #define DP_PIPE_SEL_SHIFT_IVB 29
5368 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
5369 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5370 #define DP_PIPE_SEL_SHIFT_CHV 16
5371 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
5372 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5374 /* Link training mode - select a suitable mode for each stage */
5375 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5376 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5377 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5378 #define DP_LINK_TRAIN_OFF (3 << 28)
5379 #define DP_LINK_TRAIN_MASK (3 << 28)
5380 #define DP_LINK_TRAIN_SHIFT 28
5382 /* CPT Link training mode */
5383 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5384 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5385 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5386 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5387 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5388 #define DP_LINK_TRAIN_SHIFT_CPT 8
5390 /* Signal voltages. These are mostly controlled by the other end */
5391 #define DP_VOLTAGE_0_4 (0 << 25)
5392 #define DP_VOLTAGE_0_6 (1 << 25)
5393 #define DP_VOLTAGE_0_8 (2 << 25)
5394 #define DP_VOLTAGE_1_2 (3 << 25)
5395 #define DP_VOLTAGE_MASK (7 << 25)
5396 #define DP_VOLTAGE_SHIFT 25
5398 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5401 #define DP_PRE_EMPHASIS_0 (0 << 22)
5402 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5403 #define DP_PRE_EMPHASIS_6 (2 << 22)
5404 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5405 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5406 #define DP_PRE_EMPHASIS_SHIFT 22
5408 /* How many wires to use. I guess 3 was too hard */
5409 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5410 #define DP_PORT_WIDTH_MASK (7 << 19)
5411 #define DP_PORT_WIDTH_SHIFT 19
5413 /* Mystic DPCD version 1.1 special mode */
5414 #define DP_ENHANCED_FRAMING (1 << 18)
5417 #define DP_PLL_FREQ_270MHZ (0 << 16)
5418 #define DP_PLL_FREQ_162MHZ (1 << 16)
5419 #define DP_PLL_FREQ_MASK (3 << 16)
5421 /* locked once port is enabled */
5422 #define DP_PORT_REVERSAL (1 << 15)
5425 #define DP_PLL_ENABLE (1 << 14)
5427 /* sends the clock on lane 15 of the PEG for debug */
5428 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5430 #define DP_SCRAMBLING_DISABLE (1 << 12)
5431 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5433 /* limit RGB values to avoid confusing TVs */
5434 #define DP_COLOR_RANGE_16_235 (1 << 8)
5436 /* Turn on the audio link */
5437 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5439 /* vs and hs sync polarity */
5440 #define DP_SYNC_VS_HIGH (1 << 4)
5441 #define DP_SYNC_HS_HIGH (1 << 3)
5444 #define DP_DETECTED (1 << 2)
5446 /* The aux channel provides a way to talk to the
5447 * signal sink for DDC etc. Max packet size supported
5448 * is 20 bytes in each direction, hence the 5 fixed
5451 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5452 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5453 #define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018)
5454 #define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c)
5455 #define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020)
5456 #define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024)
5458 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5459 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5460 #define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118)
5461 #define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c)
5462 #define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120)
5463 #define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124)
5465 #define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210)
5466 #define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214)
5467 #define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218)
5468 #define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c)
5469 #define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220)
5470 #define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224)
5472 #define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310)
5473 #define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314)
5474 #define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318)
5475 #define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c)
5476 #define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320)
5477 #define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324)
5479 #define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410)
5480 #define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414)
5481 #define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418)
5482 #define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c)
5483 #define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420)
5484 #define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424)
5486 #define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510)
5487 #define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514)
5488 #define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518)
5489 #define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c)
5490 #define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520)
5491 #define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524)
5493 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5494 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5496 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5497 #define DP_AUX_CH_CTL_DONE (1 << 30)
5498 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5499 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5500 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5501 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5502 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5503 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5504 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5505 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5506 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5507 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5508 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5509 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5510 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5511 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5512 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5513 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5514 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5515 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5516 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5517 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5518 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5519 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5520 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5521 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5522 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5523 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5526 * Computing GMCH M and N values for the Display Port link
5528 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5530 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5532 * The GMCH value is used internally
5534 * bytes_per_pixel is the number of bytes coming out of the plane,
5535 * which is after the LUTs, so we want the bytes for our color format.
5536 * For our current usage, this is always 3, one byte for R, G and B.
5538 #define _PIPEA_DATA_M_G4X 0x70050
5539 #define _PIPEB_DATA_M_G4X 0x71050
5541 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5542 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5543 #define TU_SIZE_SHIFT 25
5544 #define TU_SIZE_MASK (0x3f << 25)
5546 #define DATA_LINK_M_N_MASK (0xffffff)
5547 #define DATA_LINK_N_MAX (0x800000)
5549 #define _PIPEA_DATA_N_G4X 0x70054
5550 #define _PIPEB_DATA_N_G4X 0x71054
5551 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5554 * Computing Link M and N values for the Display Port link
5556 * Link M / N = pixel_clock / ls_clk
5558 * (the DP spec calls pixel_clock the 'strm_clk')
5560 * The Link value is transmitted in the Main Stream
5561 * Attributes and VB-ID.
5564 #define _PIPEA_LINK_M_G4X 0x70060
5565 #define _PIPEB_LINK_M_G4X 0x71060
5566 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5568 #define _PIPEA_LINK_N_G4X 0x70064
5569 #define _PIPEB_LINK_N_G4X 0x71064
5570 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5572 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5573 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5574 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5575 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5577 /* Display & cursor control */
5580 #define _PIPEADSL 0x70000
5581 #define DSL_LINEMASK_GEN2 0x00000fff
5582 #define DSL_LINEMASK_GEN3 0x00001fff
5583 #define _PIPEACONF 0x70008
5584 #define PIPECONF_ENABLE (1 << 31)
5585 #define PIPECONF_DISABLE 0
5586 #define PIPECONF_DOUBLE_WIDE (1 << 30)
5587 #define I965_PIPECONF_ACTIVE (1 << 30)
5588 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5589 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
5590 #define PIPECONF_SINGLE_WIDE 0
5591 #define PIPECONF_PIPE_UNLOCKED 0
5592 #define PIPECONF_PIPE_LOCKED (1 << 25)
5593 #define PIPECONF_PALETTE 0
5594 #define PIPECONF_GAMMA (1 << 24)
5595 #define PIPECONF_FORCE_BORDER (1 << 25)
5596 #define PIPECONF_INTERLACE_MASK (7 << 21)
5597 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5598 /* Note that pre-gen3 does not support interlaced display directly. Panel
5599 * fitting must be disabled on pre-ilk for interlaced. */
5600 #define PIPECONF_PROGRESSIVE (0 << 21)
5601 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5602 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5603 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5604 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5605 /* Ironlake and later have a complete new set of values for interlaced. PFIT
5606 * means panel fitter required, PF means progressive fetch, DBL means power
5607 * saving pixel doubling. */
5608 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5609 #define PIPECONF_INTERLACED_ILK (3 << 21)
5610 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5611 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5612 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5613 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5614 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
5615 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5616 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5617 #define PIPECONF_BPC_MASK (0x7 << 5)
5618 #define PIPECONF_8BPC (0 << 5)
5619 #define PIPECONF_10BPC (1 << 5)
5620 #define PIPECONF_6BPC (2 << 5)
5621 #define PIPECONF_12BPC (3 << 5)
5622 #define PIPECONF_DITHER_EN (1 << 4)
5623 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5624 #define PIPECONF_DITHER_TYPE_SP (0 << 2)
5625 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
5626 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
5627 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
5628 #define _PIPEASTAT 0x70024
5629 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
5630 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
5631 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
5632 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
5633 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
5634 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
5635 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
5636 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
5637 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
5638 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
5639 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
5640 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
5641 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
5642 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
5643 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
5644 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
5645 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
5646 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
5647 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
5648 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
5649 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
5650 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
5651 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
5652 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
5653 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
5654 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
5655 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
5656 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
5657 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
5658 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
5659 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
5660 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
5661 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
5662 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
5663 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
5664 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
5665 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
5666 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
5667 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
5668 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
5669 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
5670 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
5671 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
5672 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
5673 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
5674 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
5676 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5677 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5679 #define PIPE_A_OFFSET 0x70000
5680 #define PIPE_B_OFFSET 0x71000
5681 #define PIPE_C_OFFSET 0x72000
5682 #define CHV_PIPE_C_OFFSET 0x74000
5684 * There's actually no pipe EDP. Some pipe registers have
5685 * simply shifted from the pipe to the transcoder, while
5686 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5687 * to access such registers in transcoder EDP.
5689 #define PIPE_EDP_OFFSET 0x7f000
5691 /* ICL DSI 0 and 1 */
5692 #define PIPE_DSI0_OFFSET 0x7b000
5693 #define PIPE_DSI1_OFFSET 0x7b800
5695 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5696 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5697 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5698 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5699 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5701 #define _PIPE_MISC_A 0x70030
5702 #define _PIPE_MISC_B 0x71030
5703 #define PIPEMISC_YUV420_ENABLE (1 << 27)
5704 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
5705 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
5706 #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
5707 #define PIPEMISC_DITHER_8_BPC (0 << 5)
5708 #define PIPEMISC_DITHER_10_BPC (1 << 5)
5709 #define PIPEMISC_DITHER_6_BPC (2 << 5)
5710 #define PIPEMISC_DITHER_12_BPC (3 << 5)
5711 #define PIPEMISC_DITHER_ENABLE (1 << 4)
5712 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
5713 #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
5714 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5716 /* Skylake+ pipe bottom (background) color */
5717 #define _SKL_BOTTOM_COLOR_A 0x70034
5718 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
5719 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
5720 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
5722 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5723 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
5724 #define PIPEB_HLINE_INT_EN (1 << 28)
5725 #define PIPEB_VBLANK_INT_EN (1 << 27)
5726 #define SPRITED_FLIP_DONE_INT_EN (1 << 26)
5727 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
5728 #define PLANEB_FLIP_DONE_INT_EN (1 << 24)
5729 #define PIPE_PSR_INT_EN (1 << 22)
5730 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
5731 #define PIPEA_HLINE_INT_EN (1 << 20)
5732 #define PIPEA_VBLANK_INT_EN (1 << 19)
5733 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
5734 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
5735 #define PLANEA_FLIPDONE_INT_EN (1 << 16)
5736 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
5737 #define PIPEC_HLINE_INT_EN (1 << 12)
5738 #define PIPEC_VBLANK_INT_EN (1 << 11)
5739 #define SPRITEF_FLIPDONE_INT_EN (1 << 10)
5740 #define SPRITEE_FLIPDONE_INT_EN (1 << 9)
5741 #define PLANEC_FLIPDONE_INT_EN (1 << 8)
5743 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5744 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
5745 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
5746 #define PLANEC_INVALID_GTT_INT_EN (1 << 25)
5747 #define CURSORC_INVALID_GTT_INT_EN (1 << 24)
5748 #define CURSORB_INVALID_GTT_INT_EN (1 << 23)
5749 #define CURSORA_INVALID_GTT_INT_EN (1 << 22)
5750 #define SPRITED_INVALID_GTT_INT_EN (1 << 21)
5751 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
5752 #define PLANEB_INVALID_GTT_INT_EN (1 << 19)
5753 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
5754 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
5755 #define PLANEA_INVALID_GTT_INT_EN (1 << 16)
5756 #define DPINVGTT_EN_MASK 0xff0000
5757 #define DPINVGTT_EN_MASK_CHV 0xfff0000
5758 #define SPRITEF_INVALID_GTT_STATUS (1 << 11)
5759 #define SPRITEE_INVALID_GTT_STATUS (1 << 10)
5760 #define PLANEC_INVALID_GTT_STATUS (1 << 9)
5761 #define CURSORC_INVALID_GTT_STATUS (1 << 8)
5762 #define CURSORB_INVALID_GTT_STATUS (1 << 7)
5763 #define CURSORA_INVALID_GTT_STATUS (1 << 6)
5764 #define SPRITED_INVALID_GTT_STATUS (1 << 5)
5765 #define SPRITEC_INVALID_GTT_STATUS (1 << 4)
5766 #define PLANEB_INVALID_GTT_STATUS (1 << 3)
5767 #define SPRITEB_INVALID_GTT_STATUS (1 << 2)
5768 #define SPRITEA_INVALID_GTT_STATUS (1 << 1)
5769 #define PLANEA_INVALID_GTT_STATUS (1 << 0)
5770 #define DPINVGTT_STATUS_MASK 0xff
5771 #define DPINVGTT_STATUS_MASK_CHV 0xfff
5773 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
5774 #define DSPARB_CSTART_MASK (0x7f << 7)
5775 #define DSPARB_CSTART_SHIFT 7
5776 #define DSPARB_BSTART_MASK (0x7f)
5777 #define DSPARB_BSTART_SHIFT 0
5778 #define DSPARB_BEND_SHIFT 9 /* on 855 */
5779 #define DSPARB_AEND_SHIFT 0
5780 #define DSPARB_SPRITEA_SHIFT_VLV 0
5781 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5782 #define DSPARB_SPRITEB_SHIFT_VLV 8
5783 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5784 #define DSPARB_SPRITEC_SHIFT_VLV 16
5785 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5786 #define DSPARB_SPRITED_SHIFT_VLV 24
5787 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5788 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5789 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5790 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5791 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5792 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5793 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5794 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5795 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
5796 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5797 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5798 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5799 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5800 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5801 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5802 #define DSPARB_SPRITEE_SHIFT_VLV 0
5803 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5804 #define DSPARB_SPRITEF_SHIFT_VLV 8
5805 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5807 /* pnv/gen4/g4x/vlv/chv */
5808 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
5809 #define DSPFW_SR_SHIFT 23
5810 #define DSPFW_SR_MASK (0x1ff << 23)
5811 #define DSPFW_CURSORB_SHIFT 16
5812 #define DSPFW_CURSORB_MASK (0x3f << 16)
5813 #define DSPFW_PLANEB_SHIFT 8
5814 #define DSPFW_PLANEB_MASK (0x7f << 8)
5815 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
5816 #define DSPFW_PLANEA_SHIFT 0
5817 #define DSPFW_PLANEA_MASK (0x7f << 0)
5818 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
5819 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
5820 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
5821 #define DSPFW_FBC_SR_SHIFT 28
5822 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
5823 #define DSPFW_FBC_HPLL_SR_SHIFT 24
5824 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
5825 #define DSPFW_SPRITEB_SHIFT (16)
5826 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
5827 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
5828 #define DSPFW_CURSORA_SHIFT 8
5829 #define DSPFW_CURSORA_MASK (0x3f << 8)
5830 #define DSPFW_PLANEC_OLD_SHIFT 0
5831 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
5832 #define DSPFW_SPRITEA_SHIFT 0
5833 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
5834 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
5835 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
5836 #define DSPFW_HPLL_SR_EN (1 << 31)
5837 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
5838 #define DSPFW_CURSOR_SR_SHIFT 24
5839 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
5840 #define DSPFW_HPLL_CURSOR_SHIFT 16
5841 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
5842 #define DSPFW_HPLL_SR_SHIFT 0
5843 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
5846 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5847 #define DSPFW_SPRITEB_WM1_SHIFT 16
5848 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
5849 #define DSPFW_CURSORA_WM1_SHIFT 8
5850 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
5851 #define DSPFW_SPRITEA_WM1_SHIFT 0
5852 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
5853 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5854 #define DSPFW_PLANEB_WM1_SHIFT 24
5855 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
5856 #define DSPFW_PLANEA_WM1_SHIFT 16
5857 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
5858 #define DSPFW_CURSORB_WM1_SHIFT 8
5859 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
5860 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
5861 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
5862 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5863 #define DSPFW_SR_WM1_SHIFT 0
5864 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
5865 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5866 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5867 #define DSPFW_SPRITED_WM1_SHIFT 24
5868 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
5869 #define DSPFW_SPRITED_SHIFT 16
5870 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
5871 #define DSPFW_SPRITEC_WM1_SHIFT 8
5872 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
5873 #define DSPFW_SPRITEC_SHIFT 0
5874 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
5875 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5876 #define DSPFW_SPRITEF_WM1_SHIFT 24
5877 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
5878 #define DSPFW_SPRITEF_SHIFT 16
5879 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
5880 #define DSPFW_SPRITEE_WM1_SHIFT 8
5881 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
5882 #define DSPFW_SPRITEE_SHIFT 0
5883 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
5884 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5885 #define DSPFW_PLANEC_WM1_SHIFT 24
5886 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
5887 #define DSPFW_PLANEC_SHIFT 16
5888 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
5889 #define DSPFW_CURSORC_WM1_SHIFT 8
5890 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
5891 #define DSPFW_CURSORC_SHIFT 0
5892 #define DSPFW_CURSORC_MASK (0x3f << 0)
5894 /* vlv/chv high order bits */
5895 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5896 #define DSPFW_SR_HI_SHIFT 24
5897 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5898 #define DSPFW_SPRITEF_HI_SHIFT 23
5899 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
5900 #define DSPFW_SPRITEE_HI_SHIFT 22
5901 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
5902 #define DSPFW_PLANEC_HI_SHIFT 21
5903 #define DSPFW_PLANEC_HI_MASK (1 << 21)
5904 #define DSPFW_SPRITED_HI_SHIFT 20
5905 #define DSPFW_SPRITED_HI_MASK (1 << 20)
5906 #define DSPFW_SPRITEC_HI_SHIFT 16
5907 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
5908 #define DSPFW_PLANEB_HI_SHIFT 12
5909 #define DSPFW_PLANEB_HI_MASK (1 << 12)
5910 #define DSPFW_SPRITEB_HI_SHIFT 8
5911 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
5912 #define DSPFW_SPRITEA_HI_SHIFT 4
5913 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
5914 #define DSPFW_PLANEA_HI_SHIFT 0
5915 #define DSPFW_PLANEA_HI_MASK (1 << 0)
5916 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5917 #define DSPFW_SR_WM1_HI_SHIFT 24
5918 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
5919 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5920 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
5921 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5922 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
5923 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
5924 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
5925 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
5926 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
5927 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5928 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
5929 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
5930 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
5931 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5932 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
5933 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5934 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
5935 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
5936 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
5938 /* drain latency register values*/
5939 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5940 #define DDL_CURSOR_SHIFT 24
5941 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
5942 #define DDL_PLANE_SHIFT 0
5943 #define DDL_PRECISION_HIGH (1 << 7)
5944 #define DDL_PRECISION_LOW (0 << 7)
5945 #define DRAIN_LATENCY_MASK 0x7f
5947 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5948 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
5949 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
5951 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5952 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
5954 /* FIFO watermark sizes etc */
5955 #define G4X_FIFO_LINE_SIZE 64
5956 #define I915_FIFO_LINE_SIZE 64
5957 #define I830_FIFO_LINE_SIZE 32
5959 #define VALLEYVIEW_FIFO_SIZE 255
5960 #define G4X_FIFO_SIZE 127
5961 #define I965_FIFO_SIZE 512
5962 #define I945_FIFO_SIZE 127
5963 #define I915_FIFO_SIZE 95
5964 #define I855GM_FIFO_SIZE 127 /* In cachelines */
5965 #define I830_FIFO_SIZE 95
5967 #define VALLEYVIEW_MAX_WM 0xff
5968 #define G4X_MAX_WM 0x3f
5969 #define I915_MAX_WM 0x3f
5971 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5972 #define PINEVIEW_FIFO_LINE_SIZE 64
5973 #define PINEVIEW_MAX_WM 0x1ff
5974 #define PINEVIEW_DFT_WM 0x3f
5975 #define PINEVIEW_DFT_HPLLOFF_WM 0
5976 #define PINEVIEW_GUARD_WM 10
5977 #define PINEVIEW_CURSOR_FIFO 64
5978 #define PINEVIEW_CURSOR_MAX_WM 0x3f
5979 #define PINEVIEW_CURSOR_DFT_WM 0
5980 #define PINEVIEW_CURSOR_GUARD_WM 5
5982 #define VALLEYVIEW_CURSOR_MAX_WM 64
5983 #define I965_CURSOR_FIFO 64
5984 #define I965_CURSOR_MAX_WM 32
5985 #define I965_CURSOR_DFT_WM 8
5987 /* Watermark register definitions for SKL */
5988 #define _CUR_WM_A_0 0x70140
5989 #define _CUR_WM_B_0 0x71140
5990 #define _PLANE_WM_1_A_0 0x70240
5991 #define _PLANE_WM_1_B_0 0x71240
5992 #define _PLANE_WM_2_A_0 0x70340
5993 #define _PLANE_WM_2_B_0 0x71340
5994 #define _PLANE_WM_TRANS_1_A_0 0x70268
5995 #define _PLANE_WM_TRANS_1_B_0 0x71268
5996 #define _PLANE_WM_TRANS_2_A_0 0x70368
5997 #define _PLANE_WM_TRANS_2_B_0 0x71368
5998 #define _CUR_WM_TRANS_A_0 0x70168
5999 #define _CUR_WM_TRANS_B_0 0x71168
6000 #define PLANE_WM_EN (1 << 31)
6001 #define PLANE_WM_LINES_SHIFT 14
6002 #define PLANE_WM_LINES_MASK 0x1f
6003 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
6005 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6006 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6007 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6009 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6010 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6011 #define _PLANE_WM_BASE(pipe, plane) \
6012 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6013 #define PLANE_WM(pipe, plane, level) \
6014 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6015 #define _PLANE_WM_TRANS_1(pipe) \
6016 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6017 #define _PLANE_WM_TRANS_2(pipe) \
6018 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6019 #define PLANE_WM_TRANS(pipe, plane) \
6020 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6022 /* define the Watermark register on Ironlake */
6023 #define WM0_PIPEA_ILK _MMIO(0x45100)
6024 #define WM0_PIPE_PLANE_MASK (0xffff << 16)
6025 #define WM0_PIPE_PLANE_SHIFT 16
6026 #define WM0_PIPE_SPRITE_MASK (0xff << 8)
6027 #define WM0_PIPE_SPRITE_SHIFT 8
6028 #define WM0_PIPE_CURSOR_MASK (0xff)
6030 #define WM0_PIPEB_ILK _MMIO(0x45104)
6031 #define WM0_PIPEC_IVB _MMIO(0x45200)
6032 #define WM1_LP_ILK _MMIO(0x45108)
6033 #define WM1_LP_SR_EN (1 << 31)
6034 #define WM1_LP_LATENCY_SHIFT 24
6035 #define WM1_LP_LATENCY_MASK (0x7f << 24)
6036 #define WM1_LP_FBC_MASK (0xf << 20)
6037 #define WM1_LP_FBC_SHIFT 20
6038 #define WM1_LP_FBC_SHIFT_BDW 19
6039 #define WM1_LP_SR_MASK (0x7ff << 8)
6040 #define WM1_LP_SR_SHIFT 8
6041 #define WM1_LP_CURSOR_MASK (0xff)
6042 #define WM2_LP_ILK _MMIO(0x4510c)
6043 #define WM2_LP_EN (1 << 31)
6044 #define WM3_LP_ILK _MMIO(0x45110)
6045 #define WM3_LP_EN (1 << 31)
6046 #define WM1S_LP_ILK _MMIO(0x45120)
6047 #define WM2S_LP_IVB _MMIO(0x45124)
6048 #define WM3S_LP_IVB _MMIO(0x45128)
6049 #define WM1S_LP_EN (1 << 31)
6051 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6052 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6053 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6055 /* Memory latency timer register */
6056 #define MLTR_ILK _MMIO(0x11222)
6057 #define MLTR_WM1_SHIFT 0
6058 #define MLTR_WM2_SHIFT 8
6059 /* the unit of memory self-refresh latency time is 0.5us */
6060 #define ILK_SRLT_MASK 0x3f
6063 /* the address where we get all kinds of latency value */
6064 #define SSKPD _MMIO(0x5d10)
6065 #define SSKPD_WM_MASK 0x3f
6066 #define SSKPD_WM0_SHIFT 0
6067 #define SSKPD_WM1_SHIFT 8
6068 #define SSKPD_WM2_SHIFT 16
6069 #define SSKPD_WM3_SHIFT 24
6072 * The two pipe frame counter registers are not synchronized, so
6073 * reading a stable value is somewhat tricky. The following code
6077 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6078 * PIPE_FRAME_HIGH_SHIFT;
6079 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6080 * PIPE_FRAME_LOW_SHIFT);
6081 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6082 * PIPE_FRAME_HIGH_SHIFT);
6083 * } while (high1 != high2);
6084 * frame = (high1 << 8) | low1;
6086 #define _PIPEAFRAMEHIGH 0x70040
6087 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
6088 #define PIPE_FRAME_HIGH_SHIFT 0
6089 #define _PIPEAFRAMEPIXEL 0x70044
6090 #define PIPE_FRAME_LOW_MASK 0xff000000
6091 #define PIPE_FRAME_LOW_SHIFT 24
6092 #define PIPE_PIXEL_MASK 0x00ffffff
6093 #define PIPE_PIXEL_SHIFT 0
6094 /* GM45+ just has to be different */
6095 #define _PIPEA_FRMCOUNT_G4X 0x70040
6096 #define _PIPEA_FLIPCOUNT_G4X 0x70044
6097 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6098 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6100 /* Cursor A & B regs */
6101 #define _CURACNTR 0x70080
6102 /* Old style CUR*CNTR flags (desktop 8xx) */
6103 #define CURSOR_ENABLE 0x80000000
6104 #define CURSOR_GAMMA_ENABLE 0x40000000
6105 #define CURSOR_STRIDE_SHIFT 28
6106 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6107 #define CURSOR_FORMAT_SHIFT 24
6108 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6109 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6110 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6111 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6112 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6113 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6114 /* New style CUR*CNTR flags */
6115 #define MCURSOR_MODE 0x27
6116 #define MCURSOR_MODE_DISABLE 0x00
6117 #define MCURSOR_MODE_128_32B_AX 0x02
6118 #define MCURSOR_MODE_256_32B_AX 0x03
6119 #define MCURSOR_MODE_64_32B_AX 0x07
6120 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6121 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6122 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6123 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6124 #define MCURSOR_PIPE_SELECT_SHIFT 28
6125 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6126 #define MCURSOR_GAMMA_ENABLE (1 << 26)
6127 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
6128 #define MCURSOR_ROTATE_180 (1 << 15)
6129 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6130 #define _CURABASE 0x70084
6131 #define _CURAPOS 0x70088
6132 #define CURSOR_POS_MASK 0x007FF
6133 #define CURSOR_POS_SIGN 0x8000
6134 #define CURSOR_X_SHIFT 0
6135 #define CURSOR_Y_SHIFT 16
6136 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
6137 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6138 #define CUR_FBC_CTL_EN (1 << 31)
6139 #define _CURASURFLIVE 0x700ac /* g4x+ */
6140 #define _CURBCNTR 0x700c0
6141 #define _CURBBASE 0x700c4
6142 #define _CURBPOS 0x700c8
6144 #define _CURBCNTR_IVB 0x71080
6145 #define _CURBBASE_IVB 0x71084
6146 #define _CURBPOS_IVB 0x71088
6148 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6149 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6150 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6151 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6152 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6154 #define CURSOR_A_OFFSET 0x70080
6155 #define CURSOR_B_OFFSET 0x700c0
6156 #define CHV_CURSOR_C_OFFSET 0x700e0
6157 #define IVB_CURSOR_B_OFFSET 0x71080
6158 #define IVB_CURSOR_C_OFFSET 0x72080
6160 /* Display A control */
6161 #define _DSPACNTR 0x70180
6162 #define DISPLAY_PLANE_ENABLE (1 << 31)
6163 #define DISPLAY_PLANE_DISABLE 0
6164 #define DISPPLANE_GAMMA_ENABLE (1 << 30)
6165 #define DISPPLANE_GAMMA_DISABLE 0
6166 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6167 #define DISPPLANE_YUV422 (0x0 << 26)
6168 #define DISPPLANE_8BPP (0x2 << 26)
6169 #define DISPPLANE_BGRA555 (0x3 << 26)
6170 #define DISPPLANE_BGRX555 (0x4 << 26)
6171 #define DISPPLANE_BGRX565 (0x5 << 26)
6172 #define DISPPLANE_BGRX888 (0x6 << 26)
6173 #define DISPPLANE_BGRA888 (0x7 << 26)
6174 #define DISPPLANE_RGBX101010 (0x8 << 26)
6175 #define DISPPLANE_RGBA101010 (0x9 << 26)
6176 #define DISPPLANE_BGRX101010 (0xa << 26)
6177 #define DISPPLANE_RGBX161616 (0xc << 26)
6178 #define DISPPLANE_RGBX888 (0xe << 26)
6179 #define DISPPLANE_RGBA888 (0xf << 26)
6180 #define DISPPLANE_STEREO_ENABLE (1 << 25)
6181 #define DISPPLANE_STEREO_DISABLE 0
6182 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
6183 #define DISPPLANE_SEL_PIPE_SHIFT 24
6184 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6185 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6186 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6187 #define DISPPLANE_SRC_KEY_DISABLE 0
6188 #define DISPPLANE_LINE_DOUBLE (1 << 20)
6189 #define DISPPLANE_NO_LINE_DOUBLE 0
6190 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6191 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6192 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6193 #define DISPPLANE_ROTATE_180 (1 << 15)
6194 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6195 #define DISPPLANE_TILED (1 << 10)
6196 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
6197 #define _DSPAADDR 0x70184
6198 #define _DSPASTRIDE 0x70188
6199 #define _DSPAPOS 0x7018C /* reserved */
6200 #define _DSPASIZE 0x70190
6201 #define _DSPASURF 0x7019C /* 965+ only */
6202 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6203 #define _DSPAOFFSET 0x701A4 /* HSW */
6204 #define _DSPASURFLIVE 0x701AC
6206 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6207 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6208 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6209 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6210 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6211 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6212 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6213 #define DSPLINOFF(plane) DSPADDR(plane)
6214 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6215 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6217 /* CHV pipe B blender and primary plane */
6218 #define _CHV_BLEND_A 0x60a00
6219 #define CHV_BLEND_LEGACY (0 << 30)
6220 #define CHV_BLEND_ANDROID (1 << 30)
6221 #define CHV_BLEND_MPO (2 << 30)
6222 #define CHV_BLEND_MASK (3 << 30)
6223 #define _CHV_CANVAS_A 0x60a04
6224 #define _PRIMPOS_A 0x60a08
6225 #define _PRIMSIZE_A 0x60a0c
6226 #define _PRIMCNSTALPHA_A 0x60a10
6227 #define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6229 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6230 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6231 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6232 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6233 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6235 /* Display/Sprite base address macros */
6236 #define DISP_BASEADDR_MASK (0xfffff000)
6237 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6238 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6251 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6252 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6253 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6254 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6257 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6258 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6259 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6260 #define _PIPEBFRAMEHIGH 0x71040
6261 #define _PIPEBFRAMEPIXEL 0x71044
6262 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6263 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6266 /* Display B control */
6267 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6268 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6269 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6270 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6271 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6272 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6273 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6274 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6275 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6276 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6277 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6278 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6279 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6281 /* ICL DSI 0 and 1 */
6282 #define _PIPEDSI0CONF 0x7b008
6283 #define _PIPEDSI1CONF 0x7b808
6285 /* Sprite A control */
6286 #define _DVSACNTR 0x72180
6287 #define DVS_ENABLE (1 << 31)
6288 #define DVS_GAMMA_ENABLE (1 << 30)
6289 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6290 #define DVS_PIXFORMAT_MASK (3 << 25)
6291 #define DVS_FORMAT_YUV422 (0 << 25)
6292 #define DVS_FORMAT_RGBX101010 (1 << 25)
6293 #define DVS_FORMAT_RGBX888 (2 << 25)
6294 #define DVS_FORMAT_RGBX161616 (3 << 25)
6295 #define DVS_PIPE_CSC_ENABLE (1 << 24)
6296 #define DVS_SOURCE_KEY (1 << 22)
6297 #define DVS_RGB_ORDER_XBGR (1 << 20)
6298 #define DVS_YUV_FORMAT_BT709 (1 << 18)
6299 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6300 #define DVS_YUV_ORDER_YUYV (0 << 16)
6301 #define DVS_YUV_ORDER_UYVY (1 << 16)
6302 #define DVS_YUV_ORDER_YVYU (2 << 16)
6303 #define DVS_YUV_ORDER_VYUY (3 << 16)
6304 #define DVS_ROTATE_180 (1 << 15)
6305 #define DVS_DEST_KEY (1 << 2)
6306 #define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6307 #define DVS_TILED (1 << 10)
6308 #define _DVSALINOFF 0x72184
6309 #define _DVSASTRIDE 0x72188
6310 #define _DVSAPOS 0x7218c
6311 #define _DVSASIZE 0x72190
6312 #define _DVSAKEYVAL 0x72194
6313 #define _DVSAKEYMSK 0x72198
6314 #define _DVSASURF 0x7219c
6315 #define _DVSAKEYMAXVAL 0x721a0
6316 #define _DVSATILEOFF 0x721a4
6317 #define _DVSASURFLIVE 0x721ac
6318 #define _DVSASCALE 0x72204
6319 #define DVS_SCALE_ENABLE (1 << 31)
6320 #define DVS_FILTER_MASK (3 << 29)
6321 #define DVS_FILTER_MEDIUM (0 << 29)
6322 #define DVS_FILTER_ENHANCING (1 << 29)
6323 #define DVS_FILTER_SOFTENING (2 << 29)
6324 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6325 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6326 #define _DVSAGAMC 0x72300
6328 #define _DVSBCNTR 0x73180
6329 #define _DVSBLINOFF 0x73184
6330 #define _DVSBSTRIDE 0x73188
6331 #define _DVSBPOS 0x7318c
6332 #define _DVSBSIZE 0x73190
6333 #define _DVSBKEYVAL 0x73194
6334 #define _DVSBKEYMSK 0x73198
6335 #define _DVSBSURF 0x7319c
6336 #define _DVSBKEYMAXVAL 0x731a0
6337 #define _DVSBTILEOFF 0x731a4
6338 #define _DVSBSURFLIVE 0x731ac
6339 #define _DVSBSCALE 0x73204
6340 #define _DVSBGAMC 0x73300
6342 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6343 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6344 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6345 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6346 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6347 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6348 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6349 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6350 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6351 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6352 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6353 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6355 #define _SPRA_CTL 0x70280
6356 #define SPRITE_ENABLE (1 << 31)
6357 #define SPRITE_GAMMA_ENABLE (1 << 30)
6358 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6359 #define SPRITE_PIXFORMAT_MASK (7 << 25)
6360 #define SPRITE_FORMAT_YUV422 (0 << 25)
6361 #define SPRITE_FORMAT_RGBX101010 (1 << 25)
6362 #define SPRITE_FORMAT_RGBX888 (2 << 25)
6363 #define SPRITE_FORMAT_RGBX161616 (3 << 25)
6364 #define SPRITE_FORMAT_YUV444 (4 << 25)
6365 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
6366 #define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6367 #define SPRITE_SOURCE_KEY (1 << 22)
6368 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
6369 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6370 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
6371 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6372 #define SPRITE_YUV_ORDER_YUYV (0 << 16)
6373 #define SPRITE_YUV_ORDER_UYVY (1 << 16)
6374 #define SPRITE_YUV_ORDER_YVYU (2 << 16)
6375 #define SPRITE_YUV_ORDER_VYUY (3 << 16)
6376 #define SPRITE_ROTATE_180 (1 << 15)
6377 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6378 #define SPRITE_INT_GAMMA_ENABLE (1 << 13)
6379 #define SPRITE_TILED (1 << 10)
6380 #define SPRITE_DEST_KEY (1 << 2)
6381 #define _SPRA_LINOFF 0x70284
6382 #define _SPRA_STRIDE 0x70288
6383 #define _SPRA_POS 0x7028c
6384 #define _SPRA_SIZE 0x70290
6385 #define _SPRA_KEYVAL 0x70294
6386 #define _SPRA_KEYMSK 0x70298
6387 #define _SPRA_SURF 0x7029c
6388 #define _SPRA_KEYMAX 0x702a0
6389 #define _SPRA_TILEOFF 0x702a4
6390 #define _SPRA_OFFSET 0x702a4
6391 #define _SPRA_SURFLIVE 0x702ac
6392 #define _SPRA_SCALE 0x70304
6393 #define SPRITE_SCALE_ENABLE (1 << 31)
6394 #define SPRITE_FILTER_MASK (3 << 29)
6395 #define SPRITE_FILTER_MEDIUM (0 << 29)
6396 #define SPRITE_FILTER_ENHANCING (1 << 29)
6397 #define SPRITE_FILTER_SOFTENING (2 << 29)
6398 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6399 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6400 #define _SPRA_GAMC 0x70400
6402 #define _SPRB_CTL 0x71280
6403 #define _SPRB_LINOFF 0x71284
6404 #define _SPRB_STRIDE 0x71288
6405 #define _SPRB_POS 0x7128c
6406 #define _SPRB_SIZE 0x71290
6407 #define _SPRB_KEYVAL 0x71294
6408 #define _SPRB_KEYMSK 0x71298
6409 #define _SPRB_SURF 0x7129c
6410 #define _SPRB_KEYMAX 0x712a0
6411 #define _SPRB_TILEOFF 0x712a4
6412 #define _SPRB_OFFSET 0x712a4
6413 #define _SPRB_SURFLIVE 0x712ac
6414 #define _SPRB_SCALE 0x71304
6415 #define _SPRB_GAMC 0x71400
6417 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6418 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6419 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6420 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6421 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6422 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6423 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6424 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6425 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6426 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6427 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6428 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6429 #define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6430 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6432 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6433 #define SP_ENABLE (1 << 31)
6434 #define SP_GAMMA_ENABLE (1 << 30)
6435 #define SP_PIXFORMAT_MASK (0xf << 26)
6436 #define SP_FORMAT_YUV422 (0 << 26)
6437 #define SP_FORMAT_BGR565 (5 << 26)
6438 #define SP_FORMAT_BGRX8888 (6 << 26)
6439 #define SP_FORMAT_BGRA8888 (7 << 26)
6440 #define SP_FORMAT_RGBX1010102 (8 << 26)
6441 #define SP_FORMAT_RGBA1010102 (9 << 26)
6442 #define SP_FORMAT_RGBX8888 (0xe << 26)
6443 #define SP_FORMAT_RGBA8888 (0xf << 26)
6444 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
6445 #define SP_SOURCE_KEY (1 << 22)
6446 #define SP_YUV_FORMAT_BT709 (1 << 18)
6447 #define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6448 #define SP_YUV_ORDER_YUYV (0 << 16)
6449 #define SP_YUV_ORDER_UYVY (1 << 16)
6450 #define SP_YUV_ORDER_YVYU (2 << 16)
6451 #define SP_YUV_ORDER_VYUY (3 << 16)
6452 #define SP_ROTATE_180 (1 << 15)
6453 #define SP_TILED (1 << 10)
6454 #define SP_MIRROR (1 << 8) /* CHV pipe B */
6455 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6456 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6457 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6458 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6459 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6460 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6461 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6462 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6463 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6464 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6465 #define SP_CONST_ALPHA_ENABLE (1 << 31)
6466 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6467 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6468 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6469 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6470 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6471 #define SP_SH_COS(x) (x) /* u3.7 */
6472 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6474 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6475 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6476 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6477 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6478 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6479 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6480 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6481 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6482 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6483 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6484 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6485 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6486 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6487 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6489 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6490 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6492 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6493 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6494 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6495 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6496 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6497 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6498 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6499 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6500 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6501 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6502 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6503 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6504 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6505 #define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6508 * CHV pipe B sprite CSC
6510 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6511 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6512 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6514 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6515 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6517 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6518 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6519 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6520 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6521 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6523 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6524 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6525 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6526 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6527 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6528 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6529 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6531 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6532 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6533 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6534 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6535 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6537 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6538 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6539 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6540 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6541 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6543 /* Skylake plane registers */
6545 #define _PLANE_CTL_1_A 0x70180
6546 #define _PLANE_CTL_2_A 0x70280
6547 #define _PLANE_CTL_3_A 0x70380
6548 #define PLANE_CTL_ENABLE (1 << 31)
6549 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6550 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6552 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6553 * expanded to include bit 23 as well. However, the shift-24 based values
6554 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6556 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6557 #define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6558 #define PLANE_CTL_FORMAT_NV12 (1 << 24)
6559 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
6560 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
6561 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
6562 #define PLANE_CTL_FORMAT_AYUV (8 << 24)
6563 #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
6564 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
6565 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6566 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6567 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6568 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
6569 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
6570 #define PLANE_CTL_ORDER_BGRX (0 << 20)
6571 #define PLANE_CTL_ORDER_RGBX (1 << 20)
6572 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
6573 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6574 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6575 #define PLANE_CTL_YUV422_YUYV (0 << 16)
6576 #define PLANE_CTL_YUV422_UYVY (1 << 16)
6577 #define PLANE_CTL_YUV422_YVYU (2 << 16)
6578 #define PLANE_CTL_YUV422_VYUY (3 << 16)
6579 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
6580 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6581 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6582 #define PLANE_CTL_TILED_MASK (0x7 << 10)
6583 #define PLANE_CTL_TILED_LINEAR (0 << 10)
6584 #define PLANE_CTL_TILED_X (1 << 10)
6585 #define PLANE_CTL_TILED_Y (4 << 10)
6586 #define PLANE_CTL_TILED_YF (5 << 10)
6587 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
6588 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6589 #define PLANE_CTL_ALPHA_DISABLE (0 << 4)
6590 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
6591 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
6592 #define PLANE_CTL_ROTATE_MASK 0x3
6593 #define PLANE_CTL_ROTATE_0 0x0
6594 #define PLANE_CTL_ROTATE_90 0x1
6595 #define PLANE_CTL_ROTATE_180 0x2
6596 #define PLANE_CTL_ROTATE_270 0x3
6597 #define _PLANE_STRIDE_1_A 0x70188
6598 #define _PLANE_STRIDE_2_A 0x70288
6599 #define _PLANE_STRIDE_3_A 0x70388
6600 #define _PLANE_POS_1_A 0x7018c
6601 #define _PLANE_POS_2_A 0x7028c
6602 #define _PLANE_POS_3_A 0x7038c
6603 #define _PLANE_SIZE_1_A 0x70190
6604 #define _PLANE_SIZE_2_A 0x70290
6605 #define _PLANE_SIZE_3_A 0x70390
6606 #define _PLANE_SURF_1_A 0x7019c
6607 #define _PLANE_SURF_2_A 0x7029c
6608 #define _PLANE_SURF_3_A 0x7039c
6609 #define _PLANE_OFFSET_1_A 0x701a4
6610 #define _PLANE_OFFSET_2_A 0x702a4
6611 #define _PLANE_OFFSET_3_A 0x703a4
6612 #define _PLANE_KEYVAL_1_A 0x70194
6613 #define _PLANE_KEYVAL_2_A 0x70294
6614 #define _PLANE_KEYMSK_1_A 0x70198
6615 #define _PLANE_KEYMSK_2_A 0x70298
6616 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
6617 #define _PLANE_KEYMAX_1_A 0x701a0
6618 #define _PLANE_KEYMAX_2_A 0x702a0
6619 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
6620 #define _PLANE_AUX_DIST_1_A 0x701c0
6621 #define _PLANE_AUX_DIST_2_A 0x702c0
6622 #define _PLANE_AUX_OFFSET_1_A 0x701c4
6623 #define _PLANE_AUX_OFFSET_2_A 0x702c4
6624 #define _PLANE_CUS_CTL_1_A 0x701c8
6625 #define _PLANE_CUS_CTL_2_A 0x702c8
6626 #define PLANE_CUS_ENABLE (1 << 31)
6627 #define PLANE_CUS_PLANE_6 (0 << 30)
6628 #define PLANE_CUS_PLANE_7 (1 << 30)
6629 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
6630 #define PLANE_CUS_HPHASE_0 (0 << 16)
6631 #define PLANE_CUS_HPHASE_0_25 (1 << 16)
6632 #define PLANE_CUS_HPHASE_0_5 (2 << 16)
6633 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
6634 #define PLANE_CUS_VPHASE_0 (0 << 12)
6635 #define PLANE_CUS_VPHASE_0_25 (1 << 12)
6636 #define PLANE_CUS_VPHASE_0_5 (2 << 12)
6637 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6638 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6639 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6640 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6641 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6642 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
6643 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
6644 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6645 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6646 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6647 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6648 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6649 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6650 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6651 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6652 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6653 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6654 #define _PLANE_BUF_CFG_1_A 0x7027c
6655 #define _PLANE_BUF_CFG_2_A 0x7037c
6656 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
6657 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
6659 /* Input CSC Register Definitions */
6660 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
6661 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
6663 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
6664 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
6666 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
6667 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
6668 _PLANE_INPUT_CSC_RY_GY_1_B)
6669 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
6670 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
6671 _PLANE_INPUT_CSC_RY_GY_2_B)
6673 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
6674 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
6675 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
6677 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
6678 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
6680 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
6681 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
6683 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
6684 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
6685 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
6686 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
6687 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
6688 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
6689 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
6690 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
6691 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
6693 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
6694 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
6696 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
6697 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
6699 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
6700 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
6701 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
6702 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
6703 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
6704 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
6705 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
6706 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
6707 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
6709 #define _PLANE_CTL_1_B 0x71180
6710 #define _PLANE_CTL_2_B 0x71280
6711 #define _PLANE_CTL_3_B 0x71380
6712 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6713 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6714 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6715 #define PLANE_CTL(pipe, plane) \
6716 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6718 #define _PLANE_STRIDE_1_B 0x71188
6719 #define _PLANE_STRIDE_2_B 0x71288
6720 #define _PLANE_STRIDE_3_B 0x71388
6721 #define _PLANE_STRIDE_1(pipe) \
6722 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6723 #define _PLANE_STRIDE_2(pipe) \
6724 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6725 #define _PLANE_STRIDE_3(pipe) \
6726 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6727 #define PLANE_STRIDE(pipe, plane) \
6728 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6730 #define _PLANE_POS_1_B 0x7118c
6731 #define _PLANE_POS_2_B 0x7128c
6732 #define _PLANE_POS_3_B 0x7138c
6733 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6734 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6735 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6736 #define PLANE_POS(pipe, plane) \
6737 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6739 #define _PLANE_SIZE_1_B 0x71190
6740 #define _PLANE_SIZE_2_B 0x71290
6741 #define _PLANE_SIZE_3_B 0x71390
6742 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6743 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6744 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6745 #define PLANE_SIZE(pipe, plane) \
6746 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6748 #define _PLANE_SURF_1_B 0x7119c
6749 #define _PLANE_SURF_2_B 0x7129c
6750 #define _PLANE_SURF_3_B 0x7139c
6751 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6752 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6753 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6754 #define PLANE_SURF(pipe, plane) \
6755 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6757 #define _PLANE_OFFSET_1_B 0x711a4
6758 #define _PLANE_OFFSET_2_B 0x712a4
6759 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6760 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6761 #define PLANE_OFFSET(pipe, plane) \
6762 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6764 #define _PLANE_KEYVAL_1_B 0x71194
6765 #define _PLANE_KEYVAL_2_B 0x71294
6766 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6767 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6768 #define PLANE_KEYVAL(pipe, plane) \
6769 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6771 #define _PLANE_KEYMSK_1_B 0x71198
6772 #define _PLANE_KEYMSK_2_B 0x71298
6773 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6774 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6775 #define PLANE_KEYMSK(pipe, plane) \
6776 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6778 #define _PLANE_KEYMAX_1_B 0x711a0
6779 #define _PLANE_KEYMAX_2_B 0x712a0
6780 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6781 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6782 #define PLANE_KEYMAX(pipe, plane) \
6783 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6785 #define _PLANE_BUF_CFG_1_B 0x7127c
6786 #define _PLANE_BUF_CFG_2_B 0x7137c
6787 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
6788 #define DDB_ENTRY_END_SHIFT 16
6789 #define _PLANE_BUF_CFG_1(pipe) \
6790 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6791 #define _PLANE_BUF_CFG_2(pipe) \
6792 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6793 #define PLANE_BUF_CFG(pipe, plane) \
6794 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6796 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
6797 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
6798 #define _PLANE_NV12_BUF_CFG_1(pipe) \
6799 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6800 #define _PLANE_NV12_BUF_CFG_2(pipe) \
6801 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6802 #define PLANE_NV12_BUF_CFG(pipe, plane) \
6803 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6805 #define _PLANE_AUX_DIST_1_B 0x711c0
6806 #define _PLANE_AUX_DIST_2_B 0x712c0
6807 #define _PLANE_AUX_DIST_1(pipe) \
6808 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6809 #define _PLANE_AUX_DIST_2(pipe) \
6810 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6811 #define PLANE_AUX_DIST(pipe, plane) \
6812 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6814 #define _PLANE_AUX_OFFSET_1_B 0x711c4
6815 #define _PLANE_AUX_OFFSET_2_B 0x712c4
6816 #define _PLANE_AUX_OFFSET_1(pipe) \
6817 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6818 #define _PLANE_AUX_OFFSET_2(pipe) \
6819 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6820 #define PLANE_AUX_OFFSET(pipe, plane) \
6821 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6823 #define _PLANE_CUS_CTL_1_B 0x711c8
6824 #define _PLANE_CUS_CTL_2_B 0x712c8
6825 #define _PLANE_CUS_CTL_1(pipe) \
6826 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
6827 #define _PLANE_CUS_CTL_2(pipe) \
6828 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
6829 #define PLANE_CUS_CTL(pipe, plane) \
6830 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
6832 #define _PLANE_COLOR_CTL_1_B 0x711CC
6833 #define _PLANE_COLOR_CTL_2_B 0x712CC
6834 #define _PLANE_COLOR_CTL_3_B 0x713CC
6835 #define _PLANE_COLOR_CTL_1(pipe) \
6836 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6837 #define _PLANE_COLOR_CTL_2(pipe) \
6838 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6839 #define PLANE_COLOR_CTL(pipe, plane) \
6840 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6842 #/* SKL new cursor registers */
6843 #define _CUR_BUF_CFG_A 0x7017c
6844 #define _CUR_BUF_CFG_B 0x7117c
6845 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6848 #define VGACNTRL _MMIO(0x71400)
6849 # define VGA_DISP_DISABLE (1 << 31)
6850 # define VGA_2X_MODE (1 << 30)
6851 # define VGA_PIPE_B_SELECT (1 << 29)
6853 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6857 #define CPU_VGACNTRL _MMIO(0x41000)
6859 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6860 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6861 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6862 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6863 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6864 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6865 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6866 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6867 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6868 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6869 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6871 /* refresh rate hardware control */
6872 #define RR_HW_CTL _MMIO(0x45300)
6873 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6874 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6876 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
6877 #define FDI_PLL_FB_CLOCK_MASK 0xff
6878 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
6879 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
6880 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6881 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6882 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6884 #define PCH_3DCGDIS0 _MMIO(0x46020)
6885 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6886 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6888 #define PCH_3DCGDIS1 _MMIO(0x46024)
6889 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6891 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6892 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
6893 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6894 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6897 #define _PIPEA_DATA_M1 0x60030
6898 #define PIPE_DATA_M1_OFFSET 0
6899 #define _PIPEA_DATA_N1 0x60034
6900 #define PIPE_DATA_N1_OFFSET 0
6902 #define _PIPEA_DATA_M2 0x60038
6903 #define PIPE_DATA_M2_OFFSET 0
6904 #define _PIPEA_DATA_N2 0x6003c
6905 #define PIPE_DATA_N2_OFFSET 0
6907 #define _PIPEA_LINK_M1 0x60040
6908 #define PIPE_LINK_M1_OFFSET 0
6909 #define _PIPEA_LINK_N1 0x60044
6910 #define PIPE_LINK_N1_OFFSET 0
6912 #define _PIPEA_LINK_M2 0x60048
6913 #define PIPE_LINK_M2_OFFSET 0
6914 #define _PIPEA_LINK_N2 0x6004c
6915 #define PIPE_LINK_N2_OFFSET 0
6917 /* PIPEB timing regs are same start from 0x61000 */
6919 #define _PIPEB_DATA_M1 0x61030
6920 #define _PIPEB_DATA_N1 0x61034
6921 #define _PIPEB_DATA_M2 0x61038
6922 #define _PIPEB_DATA_N2 0x6103c
6923 #define _PIPEB_LINK_M1 0x61040
6924 #define _PIPEB_LINK_N1 0x61044
6925 #define _PIPEB_LINK_M2 0x61048
6926 #define _PIPEB_LINK_N2 0x6104c
6928 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6929 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6930 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6931 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6932 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6933 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6934 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6935 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6937 /* CPU panel fitter */
6938 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6939 #define _PFA_CTL_1 0x68080
6940 #define _PFB_CTL_1 0x68880
6941 #define PF_ENABLE (1 << 31)
6942 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
6943 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
6944 #define PF_FILTER_MASK (3 << 23)
6945 #define PF_FILTER_PROGRAMMED (0 << 23)
6946 #define PF_FILTER_MED_3x3 (1 << 23)
6947 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
6948 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
6949 #define _PFA_WIN_SZ 0x68074
6950 #define _PFB_WIN_SZ 0x68874
6951 #define _PFA_WIN_POS 0x68070
6952 #define _PFB_WIN_POS 0x68870
6953 #define _PFA_VSCALE 0x68084
6954 #define _PFB_VSCALE 0x68884
6955 #define _PFA_HSCALE 0x68090
6956 #define _PFB_HSCALE 0x68890
6958 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6959 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6960 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6961 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6962 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6964 #define _PSA_CTL 0x68180
6965 #define _PSB_CTL 0x68980
6966 #define PS_ENABLE (1 << 31)
6967 #define _PSA_WIN_SZ 0x68174
6968 #define _PSB_WIN_SZ 0x68974
6969 #define _PSA_WIN_POS 0x68170
6970 #define _PSB_WIN_POS 0x68970
6972 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6973 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6974 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6979 #define _PS_1A_CTRL 0x68180
6980 #define _PS_2A_CTRL 0x68280
6981 #define _PS_1B_CTRL 0x68980
6982 #define _PS_2B_CTRL 0x68A80
6983 #define _PS_1C_CTRL 0x69180
6984 #define PS_SCALER_EN (1 << 31)
6985 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
6986 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
6987 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
6988 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
6989 #define PS_SCALER_MODE_PLANAR (1 << 29)
6990 #define PS_SCALER_MODE_NORMAL (0 << 29)
6991 #define PS_PLANE_SEL_MASK (7 << 25)
6992 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6993 #define PS_FILTER_MASK (3 << 23)
6994 #define PS_FILTER_MEDIUM (0 << 23)
6995 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
6996 #define PS_FILTER_BILINEAR (3 << 23)
6997 #define PS_VERT3TAP (1 << 21)
6998 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6999 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7000 #define PS_PWRUP_PROGRESS (1 << 17)
7001 #define PS_V_FILTER_BYPASS (1 << 8)
7002 #define PS_VADAPT_EN (1 << 7)
7003 #define PS_VADAPT_MODE_MASK (3 << 5)
7004 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7005 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7006 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
7007 #define PS_PLANE_Y_SEL_MASK (7 << 5)
7008 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7010 #define _PS_PWR_GATE_1A 0x68160
7011 #define _PS_PWR_GATE_2A 0x68260
7012 #define _PS_PWR_GATE_1B 0x68960
7013 #define _PS_PWR_GATE_2B 0x68A60
7014 #define _PS_PWR_GATE_1C 0x69160
7015 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7016 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7017 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7018 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7019 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7020 #define PS_PWR_GATE_SLPEN_8 0
7021 #define PS_PWR_GATE_SLPEN_16 1
7022 #define PS_PWR_GATE_SLPEN_24 2
7023 #define PS_PWR_GATE_SLPEN_32 3
7025 #define _PS_WIN_POS_1A 0x68170
7026 #define _PS_WIN_POS_2A 0x68270
7027 #define _PS_WIN_POS_1B 0x68970
7028 #define _PS_WIN_POS_2B 0x68A70
7029 #define _PS_WIN_POS_1C 0x69170
7031 #define _PS_WIN_SZ_1A 0x68174
7032 #define _PS_WIN_SZ_2A 0x68274
7033 #define _PS_WIN_SZ_1B 0x68974
7034 #define _PS_WIN_SZ_2B 0x68A74
7035 #define _PS_WIN_SZ_1C 0x69174
7037 #define _PS_VSCALE_1A 0x68184
7038 #define _PS_VSCALE_2A 0x68284
7039 #define _PS_VSCALE_1B 0x68984
7040 #define _PS_VSCALE_2B 0x68A84
7041 #define _PS_VSCALE_1C 0x69184
7043 #define _PS_HSCALE_1A 0x68190
7044 #define _PS_HSCALE_2A 0x68290
7045 #define _PS_HSCALE_1B 0x68990
7046 #define _PS_HSCALE_2B 0x68A90
7047 #define _PS_HSCALE_1C 0x69190
7049 #define _PS_VPHASE_1A 0x68188
7050 #define _PS_VPHASE_2A 0x68288
7051 #define _PS_VPHASE_1B 0x68988
7052 #define _PS_VPHASE_2B 0x68A88
7053 #define _PS_VPHASE_1C 0x69188
7054 #define PS_Y_PHASE(x) ((x) << 16)
7055 #define PS_UV_RGB_PHASE(x) ((x) << 0)
7056 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7057 #define PS_PHASE_TRIP (1 << 0)
7059 #define _PS_HPHASE_1A 0x68194
7060 #define _PS_HPHASE_2A 0x68294
7061 #define _PS_HPHASE_1B 0x68994
7062 #define _PS_HPHASE_2B 0x68A94
7063 #define _PS_HPHASE_1C 0x69194
7065 #define _PS_ECC_STAT_1A 0x681D0
7066 #define _PS_ECC_STAT_2A 0x682D0
7067 #define _PS_ECC_STAT_1B 0x689D0
7068 #define _PS_ECC_STAT_2B 0x68AD0
7069 #define _PS_ECC_STAT_1C 0x691D0
7071 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7072 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
7073 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7074 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7075 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
7076 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7077 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7078 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
7079 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7080 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7081 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
7082 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7083 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7084 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
7085 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7086 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7087 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
7088 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7089 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7090 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
7091 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7092 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7093 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
7094 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7095 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7096 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
7097 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
7098 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7100 /* legacy palette */
7101 #define _LGC_PALETTE_A 0x4a000
7102 #define _LGC_PALETTE_B 0x4a800
7103 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7105 #define _GAMMA_MODE_A 0x4a480
7106 #define _GAMMA_MODE_B 0x4ac80
7107 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7108 #define GAMMA_MODE_MODE_MASK (3 << 0)
7109 #define GAMMA_MODE_MODE_8BIT (0 << 0)
7110 #define GAMMA_MODE_MODE_10BIT (1 << 0)
7111 #define GAMMA_MODE_MODE_12BIT (2 << 0)
7112 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
7115 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
7116 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
7117 #define CSR_HTP_ADDR_SKL 0x00500034
7118 #define CSR_SSP_BASE _MMIO(0x8F074)
7119 #define CSR_HTP_SKL _MMIO(0x8F004)
7120 #define CSR_LAST_WRITE _MMIO(0x8F034)
7121 #define CSR_LAST_WRITE_VALUE 0xc003b400
7122 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7123 #define CSR_MMIO_START_RANGE 0x80000
7124 #define CSR_MMIO_END_RANGE 0x8FFFF
7125 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
7126 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
7127 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
7130 #define DE_MASTER_IRQ_CONTROL (1 << 31)
7131 #define DE_SPRITEB_FLIP_DONE (1 << 29)
7132 #define DE_SPRITEA_FLIP_DONE (1 << 28)
7133 #define DE_PLANEB_FLIP_DONE (1 << 27)
7134 #define DE_PLANEA_FLIP_DONE (1 << 26)
7135 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7136 #define DE_PCU_EVENT (1 << 25)
7137 #define DE_GTT_FAULT (1 << 24)
7138 #define DE_POISON (1 << 23)
7139 #define DE_PERFORM_COUNTER (1 << 22)
7140 #define DE_PCH_EVENT (1 << 21)
7141 #define DE_AUX_CHANNEL_A (1 << 20)
7142 #define DE_DP_A_HOTPLUG (1 << 19)
7143 #define DE_GSE (1 << 18)
7144 #define DE_PIPEB_VBLANK (1 << 15)
7145 #define DE_PIPEB_EVEN_FIELD (1 << 14)
7146 #define DE_PIPEB_ODD_FIELD (1 << 13)
7147 #define DE_PIPEB_LINE_COMPARE (1 << 12)
7148 #define DE_PIPEB_VSYNC (1 << 11)
7149 #define DE_PIPEB_CRC_DONE (1 << 10)
7150 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7151 #define DE_PIPEA_VBLANK (1 << 7)
7152 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7153 #define DE_PIPEA_EVEN_FIELD (1 << 6)
7154 #define DE_PIPEA_ODD_FIELD (1 << 5)
7155 #define DE_PIPEA_LINE_COMPARE (1 << 4)
7156 #define DE_PIPEA_VSYNC (1 << 3)
7157 #define DE_PIPEA_CRC_DONE (1 << 2)
7158 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7159 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7160 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7162 /* More Ivybridge lolz */
7163 #define DE_ERR_INT_IVB (1 << 30)
7164 #define DE_GSE_IVB (1 << 29)
7165 #define DE_PCH_EVENT_IVB (1 << 28)
7166 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
7167 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
7168 #define DE_EDP_PSR_INT_HSW (1 << 19)
7169 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7170 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7171 #define DE_PIPEC_VBLANK_IVB (1 << 10)
7172 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7173 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7174 #define DE_PIPEB_VBLANK_IVB (1 << 5)
7175 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7176 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7177 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7178 #define DE_PIPEA_VBLANK_IVB (1 << 0)
7179 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7181 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
7182 #define MASTER_INTERRUPT_ENABLE (1 << 31)
7184 #define DEISR _MMIO(0x44000)
7185 #define DEIMR _MMIO(0x44004)
7186 #define DEIIR _MMIO(0x44008)
7187 #define DEIER _MMIO(0x4400c)
7189 #define GTISR _MMIO(0x44010)
7190 #define GTIMR _MMIO(0x44014)
7191 #define GTIIR _MMIO(0x44018)
7192 #define GTIER _MMIO(0x4401c)
7194 #define GEN8_MASTER_IRQ _MMIO(0x44200)
7195 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7196 #define GEN8_PCU_IRQ (1 << 30)
7197 #define GEN8_DE_PCH_IRQ (1 << 23)
7198 #define GEN8_DE_MISC_IRQ (1 << 22)
7199 #define GEN8_DE_PORT_IRQ (1 << 20)
7200 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
7201 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
7202 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
7203 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7204 #define GEN8_GT_VECS_IRQ (1 << 6)
7205 #define GEN8_GT_GUC_IRQ (1 << 5)
7206 #define GEN8_GT_PM_IRQ (1 << 4)
7207 #define GEN8_GT_VCS2_IRQ (1 << 3)
7208 #define GEN8_GT_VCS1_IRQ (1 << 2)
7209 #define GEN8_GT_BCS_IRQ (1 << 1)
7210 #define GEN8_GT_RCS_IRQ (1 << 0)
7212 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7213 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7214 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7215 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7217 #define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
7218 #define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
7219 #define GEN9_GUC_DISPLAY_EVENT (1 << 29)
7220 #define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
7221 #define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
7222 #define GEN9_GUC_DB_RING_EVENT (1 << 26)
7223 #define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
7224 #define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
7225 #define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
7227 #define GEN8_RCS_IRQ_SHIFT 0
7228 #define GEN8_BCS_IRQ_SHIFT 16
7229 #define GEN8_VCS1_IRQ_SHIFT 0
7230 #define GEN8_VCS2_IRQ_SHIFT 16
7231 #define GEN8_VECS_IRQ_SHIFT 0
7232 #define GEN8_WD_IRQ_SHIFT 16
7234 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7235 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7236 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7237 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7238 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7239 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7240 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7241 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7242 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7243 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7244 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7245 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7246 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7247 #define GEN8_PIPE_VSYNC (1 << 1)
7248 #define GEN8_PIPE_VBLANK (1 << 0)
7249 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7250 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7251 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7252 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7253 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7254 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7255 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7256 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7257 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7258 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7259 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7260 (GEN8_PIPE_CURSOR_FAULT | \
7261 GEN8_PIPE_SPRITE_FAULT | \
7262 GEN8_PIPE_PRIMARY_FAULT)
7263 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7264 (GEN9_PIPE_CURSOR_FAULT | \
7265 GEN9_PIPE_PLANE4_FAULT | \
7266 GEN9_PIPE_PLANE3_FAULT | \
7267 GEN9_PIPE_PLANE2_FAULT | \
7268 GEN9_PIPE_PLANE1_FAULT)
7270 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7271 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7272 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7273 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7274 #define ICL_AUX_CHANNEL_E (1 << 29)
7275 #define CNL_AUX_CHANNEL_F (1 << 28)
7276 #define GEN9_AUX_CHANNEL_D (1 << 27)
7277 #define GEN9_AUX_CHANNEL_C (1 << 26)
7278 #define GEN9_AUX_CHANNEL_B (1 << 25)
7279 #define BXT_DE_PORT_HP_DDIC (1 << 5)
7280 #define BXT_DE_PORT_HP_DDIB (1 << 4)
7281 #define BXT_DE_PORT_HP_DDIA (1 << 3)
7282 #define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7283 BXT_DE_PORT_HP_DDIB | \
7284 BXT_DE_PORT_HP_DDIC)
7285 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7286 #define BXT_DE_PORT_GMBUS (1 << 1)
7287 #define GEN8_AUX_CHANNEL_A (1 << 0)
7289 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7290 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7291 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7292 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7293 #define GEN8_DE_MISC_GSE (1 << 27)
7294 #define GEN8_DE_EDP_PSR (1 << 19)
7296 #define GEN8_PCU_ISR _MMIO(0x444e0)
7297 #define GEN8_PCU_IMR _MMIO(0x444e4)
7298 #define GEN8_PCU_IIR _MMIO(0x444e8)
7299 #define GEN8_PCU_IER _MMIO(0x444ec)
7301 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7302 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7303 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7304 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
7305 #define GEN11_GU_MISC_GSE (1 << 27)
7307 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7308 #define GEN11_MASTER_IRQ (1 << 31)
7309 #define GEN11_PCU_IRQ (1 << 30)
7310 #define GEN11_GU_MISC_IRQ (1 << 29)
7311 #define GEN11_DISPLAY_IRQ (1 << 16)
7312 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7313 #define GEN11_GT_DW1_IRQ (1 << 1)
7314 #define GEN11_GT_DW0_IRQ (1 << 0)
7316 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7317 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7318 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7319 #define GEN11_DE_PCH_IRQ (1 << 23)
7320 #define GEN11_DE_MISC_IRQ (1 << 22)
7321 #define GEN11_DE_HPD_IRQ (1 << 21)
7322 #define GEN11_DE_PORT_IRQ (1 << 20)
7323 #define GEN11_DE_PIPE_C (1 << 18)
7324 #define GEN11_DE_PIPE_B (1 << 17)
7325 #define GEN11_DE_PIPE_A (1 << 16)
7327 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
7328 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
7329 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
7330 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
7331 #define GEN11_TC4_HOTPLUG (1 << 19)
7332 #define GEN11_TC3_HOTPLUG (1 << 18)
7333 #define GEN11_TC2_HOTPLUG (1 << 17)
7334 #define GEN11_TC1_HOTPLUG (1 << 16)
7335 #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
7336 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
7337 GEN11_TC3_HOTPLUG | \
7338 GEN11_TC2_HOTPLUG | \
7340 #define GEN11_TBT4_HOTPLUG (1 << 3)
7341 #define GEN11_TBT3_HOTPLUG (1 << 2)
7342 #define GEN11_TBT2_HOTPLUG (1 << 1)
7343 #define GEN11_TBT1_HOTPLUG (1 << 0)
7344 #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
7345 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
7346 GEN11_TBT3_HOTPLUG | \
7347 GEN11_TBT2_HOTPLUG | \
7350 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7351 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7352 #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)
7353 #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7354 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7355 #define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)
7357 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7358 #define GEN11_CSME (31)
7359 #define GEN11_GUNIT (28)
7360 #define GEN11_GUC (25)
7361 #define GEN11_WDPERF (20)
7362 #define GEN11_KCR (19)
7363 #define GEN11_GTPM (16)
7364 #define GEN11_BCS (15)
7365 #define GEN11_RCS0 (0)
7367 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7368 #define GEN11_VECS(x) (31 - (x))
7369 #define GEN11_VCS(x) (x)
7371 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7373 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7374 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7375 #define GEN11_INTR_DATA_VALID (1 << 31)
7376 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7377 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7378 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7380 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7382 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7383 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7385 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7387 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7388 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7389 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7390 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7391 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7392 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7394 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7395 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7396 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7397 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7398 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7399 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7400 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7401 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7402 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7404 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7405 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7406 #define ILK_ELPIN_409_SELECT (1 << 25)
7407 #define ILK_DPARB_GATE (1 << 22)
7408 #define ILK_VSDPFD_FULL (1 << 21)
7409 #define FUSE_STRAP _MMIO(0x42014)
7410 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7411 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7412 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7413 #define IVB_PIPE_C_DISABLE (1 << 28)
7414 #define ILK_HDCP_DISABLE (1 << 25)
7415 #define ILK_eDP_A_DISABLE (1 << 24)
7416 #define HSW_CDCLK_LIMIT (1 << 24)
7417 #define ILK_DESKTOP (1 << 23)
7419 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7420 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7421 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7422 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7423 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7424 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7426 #define IVB_CHICKEN3 _MMIO(0x4200c)
7427 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7428 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7430 #define CHICKEN_PAR1_1 _MMIO(0x42080)
7431 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7432 #define DPA_MASK_VBLANK_SRD (1 << 15)
7433 #define FORCE_ARB_IDLE_PLANES (1 << 14)
7434 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7436 #define CHICKEN_PAR2_1 _MMIO(0x42090)
7437 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7439 #define CHICKEN_MISC_2 _MMIO(0x42084)
7440 #define CNL_COMP_PWR_DOWN (1 << 23)
7441 #define GLK_CL2_PWR_DOWN (1 << 12)
7442 #define GLK_CL1_PWR_DOWN (1 << 11)
7443 #define GLK_CL0_PWR_DOWN (1 << 10)
7445 #define CHICKEN_MISC_4 _MMIO(0x4208c)
7446 #define FBC_STRIDE_OVERRIDE (1 << 13)
7447 #define FBC_STRIDE_MASK 0x1FFF
7449 #define _CHICKEN_PIPESL_1_A 0x420b0
7450 #define _CHICKEN_PIPESL_1_B 0x420b4
7451 #define HSW_FBCQ_DIS (1 << 22)
7452 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7453 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7455 #define CHICKEN_TRANS_A _MMIO(0x420c0)
7456 #define CHICKEN_TRANS_B _MMIO(0x420c4)
7457 #define CHICKEN_TRANS_C _MMIO(0x420c8)
7458 #define CHICKEN_TRANS_EDP _MMIO(0x420cc)
7459 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
7460 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
7461 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
7462 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
7463 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
7464 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
7465 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
7467 #define DISP_ARB_CTL _MMIO(0x45000)
7468 #define DISP_FBC_MEMORY_WAKE (1 << 31)
7469 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
7470 #define DISP_FBC_WM_DIS (1 << 15)
7471 #define DISP_ARB_CTL2 _MMIO(0x45004)
7472 #define DISP_DATA_PARTITION_5_6 (1 << 6)
7473 #define DISP_IPC_ENABLE (1 << 3)
7474 #define DBUF_CTL _MMIO(0x45008)
7475 #define DBUF_CTL_S1 _MMIO(0x45008)
7476 #define DBUF_CTL_S2 _MMIO(0x44FE8)
7477 #define DBUF_POWER_REQUEST (1 << 31)
7478 #define DBUF_POWER_STATE (1 << 30)
7479 #define GEN7_MSG_CTL _MMIO(0x45010)
7480 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
7481 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
7482 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7483 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
7485 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7486 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7487 #define MASK_WAKEMEM (1 << 13)
7488 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7490 #define SKL_DFSM _MMIO(0x51000)
7491 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7492 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7493 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7494 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7495 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7496 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7497 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7498 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7500 #define SKL_DSSM _MMIO(0x51004)
7501 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7502 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7503 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7504 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7505 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7507 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7508 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
7510 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7511 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
7512 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
7514 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7515 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7516 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7517 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
7518 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7519 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7520 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7521 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7522 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7525 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7526 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
7527 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
7529 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7530 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
7531 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
7532 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
7533 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
7535 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
7536 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
7538 #define HIZ_CHICKEN _MMIO(0x7018)
7539 # define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
7540 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
7542 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7543 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
7545 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7546 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
7548 #define GEN7_SARCHKMD _MMIO(0xB000)
7549 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
7550 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
7552 #define GEN7_L3SQCREG1 _MMIO(0xB010)
7553 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7555 #define GEN8_L3SQCREG1 _MMIO(0xB100)
7557 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7558 * Using the formula in BSpec leads to a hang, while the formula here works
7559 * fine and matches the formulas for all other platforms. A BSpec change
7560 * request has been filed to clarify this.
7562 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7563 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7564 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7566 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7567 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7568 #define GEN7_L3AGDIS (1 << 19)
7569 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
7570 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
7572 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7573 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7574 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
7575 #define GEN11_I2M_WRITE_DISABLE (1 << 28)
7577 #define GEN7_L3SQCREG4 _MMIO(0xb034)
7578 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
7580 #define GEN8_L3SQCREG4 _MMIO(0xb118)
7581 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
7582 #define GEN8_LQSC_RO_PERF_DIS (1 << 27)
7583 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
7586 #define HDC_CHICKEN0 _MMIO(0x7300)
7587 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7588 #define ICL_HDC_MODE _MMIO(0xE5F4)
7589 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
7590 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
7591 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
7592 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
7593 #define HDC_FORCE_NON_COHERENT (1 << 4)
7594 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
7596 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7599 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7600 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7602 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7603 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7605 /* WaCatErrorRejectionIssue */
7606 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7607 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
7609 #define HSW_SCRATCH1 _MMIO(0xb038)
7610 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
7612 #define BDW_SCRATCH1 _MMIO(0xb11c)
7613 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
7616 #define _PIPEA_CHICKEN 0x70038
7617 #define _PIPEB_CHICKEN 0x71038
7618 #define _PIPEC_CHICKEN 0x72038
7619 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
7620 #define PM_FILL_MAINTAIN_DBUF_FULLNESS (1 << 0)
7621 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
7626 #define PCH_DISPLAY_BASE 0xc0000u
7628 /* south display engine interrupt: IBX */
7629 #define SDE_AUDIO_POWER_D (1 << 27)
7630 #define SDE_AUDIO_POWER_C (1 << 26)
7631 #define SDE_AUDIO_POWER_B (1 << 25)
7632 #define SDE_AUDIO_POWER_SHIFT (25)
7633 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7634 #define SDE_GMBUS (1 << 24)
7635 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7636 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7637 #define SDE_AUDIO_HDCP_MASK (3 << 22)
7638 #define SDE_AUDIO_TRANSB (1 << 21)
7639 #define SDE_AUDIO_TRANSA (1 << 20)
7640 #define SDE_AUDIO_TRANS_MASK (3 << 20)
7641 #define SDE_POISON (1 << 19)
7643 #define SDE_FDI_RXB (1 << 17)
7644 #define SDE_FDI_RXA (1 << 16)
7645 #define SDE_FDI_MASK (3 << 16)
7646 #define SDE_AUXD (1 << 15)
7647 #define SDE_AUXC (1 << 14)
7648 #define SDE_AUXB (1 << 13)
7649 #define SDE_AUX_MASK (7 << 13)
7651 #define SDE_CRT_HOTPLUG (1 << 11)
7652 #define SDE_PORTD_HOTPLUG (1 << 10)
7653 #define SDE_PORTC_HOTPLUG (1 << 9)
7654 #define SDE_PORTB_HOTPLUG (1 << 8)
7655 #define SDE_SDVOB_HOTPLUG (1 << 6)
7656 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7657 SDE_SDVOB_HOTPLUG | \
7658 SDE_PORTB_HOTPLUG | \
7659 SDE_PORTC_HOTPLUG | \
7661 #define SDE_TRANSB_CRC_DONE (1 << 5)
7662 #define SDE_TRANSB_CRC_ERR (1 << 4)
7663 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
7664 #define SDE_TRANSA_CRC_DONE (1 << 2)
7665 #define SDE_TRANSA_CRC_ERR (1 << 1)
7666 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
7667 #define SDE_TRANS_MASK (0x3f)
7669 /* south display engine interrupt: CPT - CNP */
7670 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
7671 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
7672 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
7673 #define SDE_AUDIO_POWER_SHIFT_CPT 29
7674 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7675 #define SDE_AUXD_CPT (1 << 27)
7676 #define SDE_AUXC_CPT (1 << 26)
7677 #define SDE_AUXB_CPT (1 << 25)
7678 #define SDE_AUX_MASK_CPT (7 << 25)
7679 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7680 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7681 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7682 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7683 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7684 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
7685 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7686 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7687 SDE_SDVOB_HOTPLUG_CPT | \
7688 SDE_PORTD_HOTPLUG_CPT | \
7689 SDE_PORTC_HOTPLUG_CPT | \
7690 SDE_PORTB_HOTPLUG_CPT)
7691 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7692 SDE_PORTD_HOTPLUG_CPT | \
7693 SDE_PORTC_HOTPLUG_CPT | \
7694 SDE_PORTB_HOTPLUG_CPT | \
7695 SDE_PORTA_HOTPLUG_SPT)
7696 #define SDE_GMBUS_CPT (1 << 17)
7697 #define SDE_ERROR_CPT (1 << 16)
7698 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7699 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7700 #define SDE_FDI_RXC_CPT (1 << 8)
7701 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7702 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7703 #define SDE_FDI_RXB_CPT (1 << 4)
7704 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7705 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7706 #define SDE_FDI_RXA_CPT (1 << 0)
7707 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7708 SDE_AUDIO_CP_REQ_B_CPT | \
7709 SDE_AUDIO_CP_REQ_A_CPT)
7710 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7711 SDE_AUDIO_CP_CHG_B_CPT | \
7712 SDE_AUDIO_CP_CHG_A_CPT)
7713 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7717 /* south display engine interrupt: ICP */
7718 #define SDE_TC4_HOTPLUG_ICP (1 << 27)
7719 #define SDE_TC3_HOTPLUG_ICP (1 << 26)
7720 #define SDE_TC2_HOTPLUG_ICP (1 << 25)
7721 #define SDE_TC1_HOTPLUG_ICP (1 << 24)
7722 #define SDE_GMBUS_ICP (1 << 23)
7723 #define SDE_DDIB_HOTPLUG_ICP (1 << 17)
7724 #define SDE_DDIA_HOTPLUG_ICP (1 << 16)
7725 #define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
7726 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
7727 #define SDE_DDI_MASK_ICP (SDE_DDIB_HOTPLUG_ICP | \
7728 SDE_DDIA_HOTPLUG_ICP)
7729 #define SDE_TC_MASK_ICP (SDE_TC4_HOTPLUG_ICP | \
7730 SDE_TC3_HOTPLUG_ICP | \
7731 SDE_TC2_HOTPLUG_ICP | \
7732 SDE_TC1_HOTPLUG_ICP)
7734 #define SDEISR _MMIO(0xc4000)
7735 #define SDEIMR _MMIO(0xc4004)
7736 #define SDEIIR _MMIO(0xc4008)
7737 #define SDEIER _MMIO(0xc400c)
7739 #define SERR_INT _MMIO(0xc4040)
7740 #define SERR_INT_POISON (1 << 31)
7741 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
7743 /* digital port hotplug */
7744 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7745 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7746 #define BXT_DDIA_HPD_INVERT (1 << 27)
7747 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7748 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7749 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7750 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7751 #define PORTD_HOTPLUG_ENABLE (1 << 20)
7752 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7753 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7754 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7755 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7756 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7757 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7758 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7759 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7760 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7761 #define PORTC_HOTPLUG_ENABLE (1 << 12)
7762 #define BXT_DDIC_HPD_INVERT (1 << 11)
7763 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7764 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7765 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7766 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7767 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7768 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7769 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7770 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7771 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7772 #define PORTB_HOTPLUG_ENABLE (1 << 4)
7773 #define BXT_DDIB_HPD_INVERT (1 << 3)
7774 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7775 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7776 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7777 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7778 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7779 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7780 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7781 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7782 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7783 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7784 BXT_DDIB_HPD_INVERT | \
7785 BXT_DDIC_HPD_INVERT)
7787 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7788 #define PORTE_HOTPLUG_ENABLE (1 << 4)
7789 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7790 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7791 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7792 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7794 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
7795 * functionality covered in PCH_PORT_HOTPLUG is split into
7796 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
7799 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
7800 #define ICP_DDIB_HPD_ENABLE (1 << 7)
7801 #define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
7802 #define ICP_DDIB_HPD_NO_DETECT (0 << 4)
7803 #define ICP_DDIB_HPD_SHORT_DETECT (1 << 4)
7804 #define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
7805 #define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
7806 #define ICP_DDIA_HPD_ENABLE (1 << 3)
7807 #define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
7808 #define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
7809 #define ICP_DDIA_HPD_NO_DETECT (0 << 0)
7810 #define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
7811 #define ICP_DDIA_HPD_LONG_DETECT (2 << 0)
7812 #define ICP_DDIA_HPD_SHORT_LONG_DETECT (3 << 0)
7814 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
7815 #define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)
7816 /* Icelake DSC Rate Control Range Parameter Registers */
7817 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
7818 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
7819 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
7820 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
7821 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
7822 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
7823 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
7824 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
7825 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
7826 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
7827 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
7828 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
7829 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7830 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
7831 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
7832 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7833 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
7834 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
7835 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7836 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
7837 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
7838 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7839 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
7840 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
7841 #define RC_BPG_OFFSET_SHIFT 10
7842 #define RC_MAX_QP_SHIFT 5
7843 #define RC_MIN_QP_SHIFT 0
7845 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
7846 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
7847 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
7848 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
7849 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
7850 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
7851 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
7852 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
7853 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
7854 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
7855 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
7856 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
7857 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7858 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
7859 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
7860 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7861 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
7862 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
7863 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7864 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
7865 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
7866 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7867 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
7868 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
7870 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
7871 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
7872 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
7873 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
7874 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
7875 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
7876 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
7877 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
7878 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
7879 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
7880 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
7881 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
7882 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7883 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
7884 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
7885 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7886 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
7887 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
7888 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7889 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
7890 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
7891 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7892 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
7893 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
7895 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
7896 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
7897 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
7898 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
7899 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
7900 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
7901 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
7902 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
7903 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
7904 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
7905 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
7906 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
7907 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7908 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
7909 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
7910 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7911 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
7912 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
7913 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7914 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
7915 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
7916 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7917 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
7918 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
7920 #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
7921 #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
7923 #define _PCH_DPLL_A 0xc6014
7924 #define _PCH_DPLL_B 0xc6018
7925 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7927 #define _PCH_FPA0 0xc6040
7928 #define FP_CB_TUNE (0x3 << 22)
7929 #define _PCH_FPA1 0xc6044
7930 #define _PCH_FPB0 0xc6048
7931 #define _PCH_FPB1 0xc604c
7932 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
7933 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
7935 #define PCH_DPLL_TEST _MMIO(0xc606c)
7937 #define PCH_DREF_CONTROL _MMIO(0xC6200)
7938 #define DREF_CONTROL_MASK 0x7fc3
7939 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
7940 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
7941 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
7942 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
7943 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
7944 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
7945 #define DREF_SSC_SOURCE_MASK (3 << 11)
7946 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
7947 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
7948 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
7949 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
7950 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
7951 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
7952 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
7953 #define DREF_SSC4_DOWNSPREAD (0 << 6)
7954 #define DREF_SSC4_CENTERSPREAD (1 << 6)
7955 #define DREF_SSC1_DISABLE (0 << 1)
7956 #define DREF_SSC1_ENABLE (1 << 1)
7957 #define DREF_SSC4_DISABLE (0)
7958 #define DREF_SSC4_ENABLE (1)
7960 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7961 #define FDL_TP1_TIMER_SHIFT 12
7962 #define FDL_TP1_TIMER_MASK (3 << 12)
7963 #define FDL_TP2_TIMER_SHIFT 10
7964 #define FDL_TP2_TIMER_MASK (3 << 10)
7965 #define RAWCLK_FREQ_MASK 0x3ff
7966 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7967 #define CNP_RAWCLK_DIV(div) ((div) << 16)
7968 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7969 #define CNP_RAWCLK_DEN(den) ((den) << 26)
7970 #define ICP_RAWCLK_NUM(num) ((num) << 11)
7972 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7974 #define PCH_SSC4_PARMS _MMIO(0xc6210)
7975 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7977 #define PCH_DPLL_SEL _MMIO(0xc7000)
7978 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7979 #define TRANS_DPLLA_SEL(pipe) 0
7980 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7984 #define _PCH_TRANS_HTOTAL_A 0xe0000
7985 #define TRANS_HTOTAL_SHIFT 16
7986 #define TRANS_HACTIVE_SHIFT 0
7987 #define _PCH_TRANS_HBLANK_A 0xe0004
7988 #define TRANS_HBLANK_END_SHIFT 16
7989 #define TRANS_HBLANK_START_SHIFT 0
7990 #define _PCH_TRANS_HSYNC_A 0xe0008
7991 #define TRANS_HSYNC_END_SHIFT 16
7992 #define TRANS_HSYNC_START_SHIFT 0
7993 #define _PCH_TRANS_VTOTAL_A 0xe000c
7994 #define TRANS_VTOTAL_SHIFT 16
7995 #define TRANS_VACTIVE_SHIFT 0
7996 #define _PCH_TRANS_VBLANK_A 0xe0010
7997 #define TRANS_VBLANK_END_SHIFT 16
7998 #define TRANS_VBLANK_START_SHIFT 0
7999 #define _PCH_TRANS_VSYNC_A 0xe0014
8000 #define TRANS_VSYNC_END_SHIFT 16
8001 #define TRANS_VSYNC_START_SHIFT 0
8002 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
8004 #define _PCH_TRANSA_DATA_M1 0xe0030
8005 #define _PCH_TRANSA_DATA_N1 0xe0034
8006 #define _PCH_TRANSA_DATA_M2 0xe0038
8007 #define _PCH_TRANSA_DATA_N2 0xe003c
8008 #define _PCH_TRANSA_LINK_M1 0xe0040
8009 #define _PCH_TRANSA_LINK_N1 0xe0044
8010 #define _PCH_TRANSA_LINK_M2 0xe0048
8011 #define _PCH_TRANSA_LINK_N2 0xe004c
8013 /* Per-transcoder DIP controls (PCH) */
8014 #define _VIDEO_DIP_CTL_A 0xe0200
8015 #define _VIDEO_DIP_DATA_A 0xe0208
8016 #define _VIDEO_DIP_GCP_A 0xe0210
8017 #define GCP_COLOR_INDICATION (1 << 2)
8018 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8019 #define GCP_AV_MUTE (1 << 0)
8021 #define _VIDEO_DIP_CTL_B 0xe1200
8022 #define _VIDEO_DIP_DATA_B 0xe1208
8023 #define _VIDEO_DIP_GCP_B 0xe1210
8025 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8026 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8027 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8029 /* Per-transcoder DIP controls (VLV) */
8030 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8031 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8032 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8034 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8035 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8036 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8038 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8039 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8040 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8042 #define VLV_TVIDEO_DIP_CTL(pipe) \
8043 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8044 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8045 #define VLV_TVIDEO_DIP_DATA(pipe) \
8046 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8047 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8048 #define VLV_TVIDEO_DIP_GCP(pipe) \
8049 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8050 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8052 /* Haswell DIP controls */
8054 #define _HSW_VIDEO_DIP_CTL_A 0x60200
8055 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8056 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8057 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8058 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8059 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
8060 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8061 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8062 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8063 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8064 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8065 #define _HSW_VIDEO_DIP_GCP_A 0x60210
8067 #define _HSW_VIDEO_DIP_CTL_B 0x61200
8068 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8069 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8070 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8071 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8072 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
8073 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8074 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8075 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8076 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8077 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8078 #define _HSW_VIDEO_DIP_GCP_B 0x61210
8080 /* Icelake PPS_DATA and _ECC DIP Registers.
8081 * These are available for transcoders B,C and eDP.
8082 * Adding the _A so as to reuse the _MMIO_TRANS2
8083 * definition, with which it offsets to the right location.
8086 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8087 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8088 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8089 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8091 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8092 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8093 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8094 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8095 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8096 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8097 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8098 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8100 #define _HSW_STEREO_3D_CTL_A 0x70020
8101 #define S3D_ENABLE (1 << 31)
8102 #define _HSW_STEREO_3D_CTL_B 0x71020
8104 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8106 #define _PCH_TRANS_HTOTAL_B 0xe1000
8107 #define _PCH_TRANS_HBLANK_B 0xe1004
8108 #define _PCH_TRANS_HSYNC_B 0xe1008
8109 #define _PCH_TRANS_VTOTAL_B 0xe100c
8110 #define _PCH_TRANS_VBLANK_B 0xe1010
8111 #define _PCH_TRANS_VSYNC_B 0xe1014
8112 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8114 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8115 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8116 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8117 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8118 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8119 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8120 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8122 #define _PCH_TRANSB_DATA_M1 0xe1030
8123 #define _PCH_TRANSB_DATA_N1 0xe1034
8124 #define _PCH_TRANSB_DATA_M2 0xe1038
8125 #define _PCH_TRANSB_DATA_N2 0xe103c
8126 #define _PCH_TRANSB_LINK_M1 0xe1040
8127 #define _PCH_TRANSB_LINK_N1 0xe1044
8128 #define _PCH_TRANSB_LINK_M2 0xe1048
8129 #define _PCH_TRANSB_LINK_N2 0xe104c
8131 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8132 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8133 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8134 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8135 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8136 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8137 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8138 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8140 #define _PCH_TRANSACONF 0xf0008
8141 #define _PCH_TRANSBCONF 0xf1008
8142 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8143 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8144 #define TRANS_DISABLE (0 << 31)
8145 #define TRANS_ENABLE (1 << 31)
8146 #define TRANS_STATE_MASK (1 << 30)
8147 #define TRANS_STATE_DISABLE (0 << 30)
8148 #define TRANS_STATE_ENABLE (1 << 30)
8149 #define TRANS_FSYNC_DELAY_HB1 (0 << 27)
8150 #define TRANS_FSYNC_DELAY_HB2 (1 << 27)
8151 #define TRANS_FSYNC_DELAY_HB3 (2 << 27)
8152 #define TRANS_FSYNC_DELAY_HB4 (3 << 27)
8153 #define TRANS_INTERLACE_MASK (7 << 21)
8154 #define TRANS_PROGRESSIVE (0 << 21)
8155 #define TRANS_INTERLACED (3 << 21)
8156 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8157 #define TRANS_8BPC (0 << 5)
8158 #define TRANS_10BPC (1 << 5)
8159 #define TRANS_6BPC (2 << 5)
8160 #define TRANS_12BPC (3 << 5)
8162 #define _TRANSA_CHICKEN1 0xf0060
8163 #define _TRANSB_CHICKEN1 0xf1060
8164 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8165 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8166 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8167 #define _TRANSA_CHICKEN2 0xf0064
8168 #define _TRANSB_CHICKEN2 0xf1064
8169 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8170 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8171 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8172 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8173 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8174 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8176 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
8177 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
8178 #define FDIA_PHASE_SYNC_SHIFT_EN 18
8179 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8180 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8181 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
8182 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8183 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8184 #define SPT_PWM_GRANULARITY (1 << 0)
8185 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
8186 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8187 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8188 #define LPT_PWM_GRANULARITY (1 << 5)
8189 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8191 #define _FDI_RXA_CHICKEN 0xc200c
8192 #define _FDI_RXB_CHICKEN 0xc2010
8193 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8194 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8195 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8197 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8198 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8199 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8200 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8201 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8202 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8203 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8206 #define _FDI_TXA_CTL 0x60100
8207 #define _FDI_TXB_CTL 0x61100
8208 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8209 #define FDI_TX_DISABLE (0 << 31)
8210 #define FDI_TX_ENABLE (1 << 31)
8211 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8212 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8213 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8214 #define FDI_LINK_TRAIN_NONE (3 << 28)
8215 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8216 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8217 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8218 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8219 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8220 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8221 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8222 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8223 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8224 SNB has different settings. */
8225 /* SNB A-stepping */
8226 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8227 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8228 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8229 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8230 /* SNB B-stepping */
8231 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8232 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8233 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8234 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8235 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8236 #define FDI_DP_PORT_WIDTH_SHIFT 19
8237 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8238 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8239 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8240 /* Ironlake: hardwired to 1 */
8241 #define FDI_TX_PLL_ENABLE (1 << 14)
8243 /* Ivybridge has different bits for lolz */
8244 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8245 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8246 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8247 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8249 /* both Tx and Rx */
8250 #define FDI_COMPOSITE_SYNC (1 << 11)
8251 #define FDI_LINK_TRAIN_AUTO (1 << 10)
8252 #define FDI_SCRAMBLING_ENABLE (0 << 7)
8253 #define FDI_SCRAMBLING_DISABLE (1 << 7)
8255 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8256 #define _FDI_RXA_CTL 0xf000c
8257 #define _FDI_RXB_CTL 0xf100c
8258 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8259 #define FDI_RX_ENABLE (1 << 31)
8260 /* train, dp width same as FDI_TX */
8261 #define FDI_FS_ERRC_ENABLE (1 << 27)
8262 #define FDI_FE_ERRC_ENABLE (1 << 26)
8263 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8264 #define FDI_8BPC (0 << 16)
8265 #define FDI_10BPC (1 << 16)
8266 #define FDI_6BPC (2 << 16)
8267 #define FDI_12BPC (3 << 16)
8268 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8269 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8270 #define FDI_RX_PLL_ENABLE (1 << 13)
8271 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8272 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8273 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8274 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8275 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8276 #define FDI_PCDCLK (1 << 4)
8278 #define FDI_AUTO_TRAINING (1 << 10)
8279 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8280 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8281 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8282 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8283 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8285 #define _FDI_RXA_MISC 0xf0010
8286 #define _FDI_RXB_MISC 0xf1010
8287 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8288 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8289 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8290 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8291 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8292 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8293 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8294 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8296 #define _FDI_RXA_TUSIZE1 0xf0030
8297 #define _FDI_RXA_TUSIZE2 0xf0038
8298 #define _FDI_RXB_TUSIZE1 0xf1030
8299 #define _FDI_RXB_TUSIZE2 0xf1038
8300 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8301 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8303 /* FDI_RX interrupt register format */
8304 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8305 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
8306 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
8307 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8308 #define FDI_RX_FS_CODE_ERR (1 << 6)
8309 #define FDI_RX_FE_CODE_ERR (1 << 5)
8310 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8311 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8312 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8313 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8314 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8316 #define _FDI_RXA_IIR 0xf0014
8317 #define _FDI_RXA_IMR 0xf0018
8318 #define _FDI_RXB_IIR 0xf1014
8319 #define _FDI_RXB_IMR 0xf1018
8320 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8321 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8323 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
8324 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
8326 #define PCH_LVDS _MMIO(0xe1180)
8327 #define LVDS_DETECTED (1 << 1)
8329 #define _PCH_DP_B 0xe4100
8330 #define PCH_DP_B _MMIO(_PCH_DP_B)
8331 #define _PCH_DPB_AUX_CH_CTL 0xe4110
8332 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
8333 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
8334 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
8335 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
8336 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
8338 #define _PCH_DP_C 0xe4200
8339 #define PCH_DP_C _MMIO(_PCH_DP_C)
8340 #define _PCH_DPC_AUX_CH_CTL 0xe4210
8341 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
8342 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
8343 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
8344 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
8345 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
8347 #define _PCH_DP_D 0xe4300
8348 #define PCH_DP_D _MMIO(_PCH_DP_D)
8349 #define _PCH_DPD_AUX_CH_CTL 0xe4310
8350 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
8351 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
8352 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
8353 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
8354 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
8356 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8357 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8360 #define _TRANS_DP_CTL_A 0xe0300
8361 #define _TRANS_DP_CTL_B 0xe1300
8362 #define _TRANS_DP_CTL_C 0xe2300
8363 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8364 #define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8365 #define TRANS_DP_PORT_SEL_MASK (3 << 29)
8366 #define TRANS_DP_PORT_SEL_NONE (3 << 29)
8367 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8368 #define TRANS_DP_AUDIO_ONLY (1 << 26)
8369 #define TRANS_DP_ENH_FRAMING (1 << 18)
8370 #define TRANS_DP_8BPC (0 << 9)
8371 #define TRANS_DP_10BPC (1 << 9)
8372 #define TRANS_DP_6BPC (2 << 9)
8373 #define TRANS_DP_12BPC (3 << 9)
8374 #define TRANS_DP_BPC_MASK (3 << 9)
8375 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8376 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
8377 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8378 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
8379 #define TRANS_DP_SYNC_MASK (3 << 3)
8381 /* SNB eDP training params */
8382 /* SNB A-stepping */
8383 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8384 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8385 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8386 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8387 /* SNB B-stepping */
8388 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8389 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8390 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8391 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8392 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8393 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8396 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8397 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8398 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8399 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8400 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8401 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8402 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8405 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8406 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8407 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8408 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8409 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8411 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8413 #define VLV_PMWGICZ _MMIO(0x1300a4)
8415 #define RC6_LOCATION _MMIO(0xD40)
8416 #define RC6_CTX_IN_DRAM (1 << 0)
8417 #define RC6_CTX_BASE _MMIO(0xD48)
8418 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
8419 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8420 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8421 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8422 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8423 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8424 #define IDLE_TIME_MASK 0xFFFFF
8425 #define FORCEWAKE _MMIO(0xA18C)
8426 #define FORCEWAKE_VLV _MMIO(0x1300b0)
8427 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8428 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8429 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8430 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8431 #define FORCEWAKE_ACK _MMIO(0x130090)
8432 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8433 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8434 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8435 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8437 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8438 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8439 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8440 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8441 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8442 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8443 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8444 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8445 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8446 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8447 #define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8448 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8449 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8450 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8451 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8452 #define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8453 #define FORCEWAKE_KERNEL BIT(0)
8454 #define FORCEWAKE_USER BIT(1)
8455 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8456 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
8457 #define ECOBUS _MMIO(0xa180)
8458 #define FORCEWAKE_MT_ENABLE (1 << 5)
8459 #define VLV_SPAREG2H _MMIO(0xA194)
8460 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8461 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8462 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8464 #define GTFIFODBG _MMIO(0x120000)
8465 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8466 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8467 #define GT_FIFO_SBDROPERR (1 << 6)
8468 #define GT_FIFO_BLOBDROPERR (1 << 5)
8469 #define GT_FIFO_SB_READ_ABORTERR (1 << 4)
8470 #define GT_FIFO_DROPERR (1 << 3)
8471 #define GT_FIFO_OVFERR (1 << 2)
8472 #define GT_FIFO_IAWRERR (1 << 1)
8473 #define GT_FIFO_IARDERR (1 << 0)
8475 #define GTFIFOCTL _MMIO(0x120008)
8476 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8477 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
8478 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8479 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8481 #define HSW_IDICR _MMIO(0x9008)
8482 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8483 #define HSW_EDRAM_CAP _MMIO(0x120010)
8484 #define EDRAM_ENABLED 0x1
8485 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8486 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8487 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8489 #define GEN6_UCGCTL1 _MMIO(0x9400)
8490 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8491 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8492 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8493 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8495 #define GEN6_UCGCTL2 _MMIO(0x9404)
8496 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8497 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8498 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8499 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8500 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8501 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8503 #define GEN6_UCGCTL3 _MMIO(0x9408)
8504 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8506 #define GEN7_UCGCTL4 _MMIO(0x940c)
8507 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
8508 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
8510 #define GEN6_RCGCTL1 _MMIO(0x9410)
8511 #define GEN6_RCGCTL2 _MMIO(0x9414)
8512 #define GEN6_RSTCTL _MMIO(0x9420)
8514 #define GEN8_UCGCTL6 _MMIO(0x9430)
8515 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
8516 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
8517 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
8519 #define GEN6_GFXPAUSE _MMIO(0xA000)
8520 #define GEN6_RPNSWREQ _MMIO(0xA008)
8521 #define GEN6_TURBO_DISABLE (1 << 31)
8522 #define GEN6_FREQUENCY(x) ((x) << 25)
8523 #define HSW_FREQUENCY(x) ((x) << 24)
8524 #define GEN9_FREQUENCY(x) ((x) << 23)
8525 #define GEN6_OFFSET(x) ((x) << 19)
8526 #define GEN6_AGGRESSIVE_TURBO (0 << 15)
8527 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8528 #define GEN6_RC_CONTROL _MMIO(0xA090)
8529 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
8530 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
8531 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
8532 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
8533 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
8534 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
8535 #define GEN7_RC_CTL_TO_MODE (1 << 28)
8536 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
8537 #define GEN6_RC_CTL_HW_ENABLE (1 << 31)
8538 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8539 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8540 #define GEN6_RPSTAT1 _MMIO(0xA01C)
8541 #define GEN6_CAGF_SHIFT 8
8542 #define HSW_CAGF_SHIFT 7
8543 #define GEN9_CAGF_SHIFT 23
8544 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8545 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8546 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8547 #define GEN6_RP_CONTROL _MMIO(0xA024)
8548 #define GEN6_RP_MEDIA_TURBO (1 << 11)
8549 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
8550 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
8551 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
8552 #define GEN6_RP_MEDIA_HW_MODE (1 << 9)
8553 #define GEN6_RP_MEDIA_SW_MODE (0 << 9)
8554 #define GEN6_RP_MEDIA_IS_GFX (1 << 8)
8555 #define GEN6_RP_ENABLE (1 << 7)
8556 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
8557 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
8558 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
8559 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
8560 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
8561 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8562 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8563 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8564 #define GEN6_RP_EI_MASK 0xffffff
8565 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8566 #define GEN6_RP_CUR_UP _MMIO(0xA054)
8567 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8568 #define GEN6_RP_PREV_UP _MMIO(0xA058)
8569 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8570 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8571 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8572 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8573 #define GEN6_RP_UP_EI _MMIO(0xA068)
8574 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8575 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8576 #define GEN6_RPDEUHWTC _MMIO(0xA080)
8577 #define GEN6_RPDEUC _MMIO(0xA084)
8578 #define GEN6_RPDEUCSW _MMIO(0xA088)
8579 #define GEN6_RC_STATE _MMIO(0xA094)
8580 #define RC_SW_TARGET_STATE_SHIFT 16
8581 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8582 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8583 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8584 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8585 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8586 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8587 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8588 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
8589 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8590 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8591 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8592 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8593 #define VLV_RCEDATA _MMIO(0xA0BC)
8594 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8595 #define GEN6_PMINTRMSK _MMIO(0xA168)
8596 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
8597 #define ARAT_EXPIRED_INTRMSK (1 << 9)
8598 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
8599 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
8600 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8601 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8602 #define GEN9_PG_ENABLE _MMIO(0xA210)
8603 #define GEN9_RENDER_PG_ENABLE (1 << 0)
8604 #define GEN9_MEDIA_PG_ENABLE (1 << 1)
8605 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8606 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8607 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8609 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8610 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8611 #define PIXEL_OVERLAP_CNT_SHIFT 30
8613 #define GEN6_PMISR _MMIO(0x44020)
8614 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8615 #define GEN6_PMIIR _MMIO(0x44028)
8616 #define GEN6_PMIER _MMIO(0x4402C)
8617 #define GEN6_PM_MBOX_EVENT (1 << 25)
8618 #define GEN6_PM_THERMAL_EVENT (1 << 24)
8619 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
8620 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
8621 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
8622 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
8623 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
8624 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
8625 GEN6_PM_RP_UP_THRESHOLD | \
8626 GEN6_PM_RP_DOWN_EI_EXPIRED | \
8627 GEN6_PM_RP_DOWN_THRESHOLD | \
8628 GEN6_PM_RP_DOWN_TIMEOUT)
8630 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8631 #define GEN7_GT_SCRATCH_REG_NUM 8
8633 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8634 #define VLV_GFX_CLK_STATUS_BIT (1 << 3)
8635 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
8637 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8638 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
8639 #define VLV_COUNT_RANGE_HIGH (1 << 15)
8640 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
8641 #define VLV_RENDER_RC0_COUNT_EN (1 << 4)
8642 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
8643 #define VLV_RENDER_RC6_COUNT_EN (1 << 0)
8644 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8645 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8646 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8648 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8649 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8650 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8651 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8653 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8654 #define GEN6_PCODE_READY (1 << 31)
8655 #define GEN6_PCODE_ERROR_MASK 0xFF
8656 #define GEN6_PCODE_SUCCESS 0x0
8657 #define GEN6_PCODE_ILLEGAL_CMD 0x1
8658 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8659 #define GEN6_PCODE_TIMEOUT 0x3
8660 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8661 #define GEN7_PCODE_TIMEOUT 0x2
8662 #define GEN7_PCODE_ILLEGAL_DATA 0x3
8663 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8664 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
8665 #define GEN6_PCODE_READ_RC6VIDS 0x5
8666 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8667 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8668 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8669 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
8670 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8671 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8672 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8673 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8674 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8675 #define SKL_PCODE_CDCLK_CONTROL 0x7
8676 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8677 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
8678 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8679 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8680 #define GEN6_READ_OC_PARAMS 0xc
8681 #define GEN6_PCODE_READ_D_COMP 0x10
8682 #define GEN6_PCODE_WRITE_D_COMP 0x11
8683 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8684 #define DISPLAY_IPS_CONTROL 0x19
8685 /* See also IPS_CTL */
8686 #define IPS_PCODE_CONTROL (1 << 30)
8687 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8688 #define GEN9_PCODE_SAGV_CONTROL 0x21
8689 #define GEN9_SAGV_DISABLE 0x0
8690 #define GEN9_SAGV_IS_DISABLED 0x1
8691 #define GEN9_SAGV_ENABLE 0x3
8692 #define GEN6_PCODE_DATA _MMIO(0x138128)
8693 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8694 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8695 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8697 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8698 #define GEN6_CORE_CPD_STATE_MASK (7 << 4)
8699 #define GEN6_RCn_MASK 7
8705 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8706 #define GEN8_LSLICESTAT_MASK 0x7
8708 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8709 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8710 #define CHV_SS_PG_ENABLE (1 << 1)
8711 #define CHV_EU08_PG_ENABLE (1 << 9)
8712 #define CHV_EU19_PG_ENABLE (1 << 17)
8713 #define CHV_EU210_PG_ENABLE (1 << 25)
8715 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8716 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8717 #define CHV_EU311_PG_ENABLE (1 << 1)
8719 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
8720 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8721 ((slice) % 3) * 0x4)
8722 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
8723 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
8724 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8726 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
8727 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8728 ((slice) % 3) * 0x8)
8729 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
8730 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8731 ((slice) % 3) * 0x8)
8732 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8733 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8734 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8735 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8736 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8737 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8738 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8739 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8741 #define GEN7_MISCCPCTL _MMIO(0x9424)
8742 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
8743 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
8744 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
8745 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
8747 #define GEN8_GARBCNTL _MMIO(0xB004)
8748 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
8749 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
8750 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
8751 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
8753 #define GEN11_GLBLINVL _MMIO(0xB404)
8754 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
8755 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
8757 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
8758 #define DFR_DISABLE (1 << 9)
8760 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
8761 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
8762 #define GEN11_HASH_CTRL_BIT0 (1 << 0)
8763 #define GEN11_HASH_CTRL_BIT4 (1 << 12)
8765 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
8766 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
8767 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
8769 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
8772 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8773 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
8774 #define GEN7_PARITY_ERROR_VALID (1 << 13)
8775 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
8776 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
8777 #define GEN7_PARITY_ERROR_ROW(reg) \
8778 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8779 #define GEN7_PARITY_ERROR_BANK(reg) \
8780 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8781 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
8782 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8783 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
8785 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8786 #define GEN7_L3LOG_SIZE 0x80
8788 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8789 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8790 #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
8791 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
8792 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
8793 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
8795 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8796 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
8797 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
8799 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8800 #define FLOW_CONTROL_ENABLE (1 << 15)
8801 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
8802 #define STALL_DOP_GATING_DISABLE (1 << 5)
8803 #define THROTTLE_12_5 (7 << 2)
8804 #define DISABLE_EARLY_EOT (1 << 1)
8806 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8807 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8808 #define DOP_CLOCK_GATING_DISABLE (1 << 0)
8809 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
8810 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
8812 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8813 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8815 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8816 #define GEN8_ST_PO_DISABLE (1 << 13)
8818 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8819 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
8820 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
8821 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
8822 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
8823 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
8825 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8826 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
8827 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
8828 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
8831 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
8832 #define INTEL_AUDIO_DEVCL 0x808629FB
8833 #define INTEL_AUDIO_DEVBLC 0x80862801
8834 #define INTEL_AUDIO_DEVCTG 0x80862802
8836 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8837 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8838 #define G4X_ELDV_DEVCTG (1 << 14)
8839 #define G4X_ELD_ADDR_MASK (0xf << 5)
8840 #define G4X_ELD_ACK (1 << 4)
8841 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8843 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
8844 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
8845 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8846 _IBX_HDMIW_HDMIEDID_B)
8847 #define _IBX_AUD_CNTL_ST_A 0xE20B4
8848 #define _IBX_AUD_CNTL_ST_B 0xE21B4
8849 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8851 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8852 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8853 #define IBX_ELD_ACK (1 << 4)
8854 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8855 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8856 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8858 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
8859 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
8860 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8861 #define _CPT_AUD_CNTL_ST_A 0xE50B4
8862 #define _CPT_AUD_CNTL_ST_B 0xE51B4
8863 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8864 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8866 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8867 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8868 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8869 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8870 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8871 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8872 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8874 /* These are the 4 32-bit write offset registers for each stream
8875 * output buffer. It determines the offset from the
8876 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8878 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8880 #define _IBX_AUD_CONFIG_A 0xe2000
8881 #define _IBX_AUD_CONFIG_B 0xe2100
8882 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8883 #define _CPT_AUD_CONFIG_A 0xe5000
8884 #define _CPT_AUD_CONFIG_B 0xe5100
8885 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8886 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8887 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8888 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8890 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8891 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8892 #define AUD_CONFIG_UPPER_N_SHIFT 20
8893 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8894 #define AUD_CONFIG_LOWER_N_SHIFT 4
8895 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8896 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8897 #define AUD_CONFIG_N(n) \
8898 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8899 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8900 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8901 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8902 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8903 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8904 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8905 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8906 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8907 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8908 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8909 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8910 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8911 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8912 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8915 #define _HSW_AUD_CONFIG_A 0x65000
8916 #define _HSW_AUD_CONFIG_B 0x65100
8917 #define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8919 #define _HSW_AUD_MISC_CTRL_A 0x65010
8920 #define _HSW_AUD_MISC_CTRL_B 0x65110
8921 #define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8923 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8924 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8925 #define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8926 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8927 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8928 #define AUD_CONFIG_M_MASK 0xfffff
8930 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8931 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8932 #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8934 /* Audio Digital Converter */
8935 #define _HSW_AUD_DIG_CNVT_1 0x65080
8936 #define _HSW_AUD_DIG_CNVT_2 0x65180
8937 #define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8938 #define DIP_PORT_SEL_MASK 0x3
8940 #define _HSW_AUD_EDID_DATA_A 0x65050
8941 #define _HSW_AUD_EDID_DATA_B 0x65150
8942 #define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8944 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8945 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8946 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8947 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8948 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8949 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8951 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8952 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8955 * HSW - ICL power wells
8957 * Platforms have up to 3 power well control register sets, each set
8958 * controlling up to 16 power wells via a request/status HW flag tuple:
8959 * - main (HSW_PWR_WELL_CTL[1-4])
8960 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
8961 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
8962 * Each control register set consists of up to 4 registers used by different
8963 * sources that can request a power well to be enabled:
8964 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
8965 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
8966 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
8967 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
8969 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
8970 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
8971 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
8972 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
8973 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
8974 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
8976 /* HSW/BDW power well */
8977 #define HSW_PW_CTL_IDX_GLOBAL 15
8979 /* SKL/BXT/GLK/CNL power wells */
8980 #define SKL_PW_CTL_IDX_PW_2 15
8981 #define SKL_PW_CTL_IDX_PW_1 14
8982 #define CNL_PW_CTL_IDX_AUX_F 12
8983 #define CNL_PW_CTL_IDX_AUX_D 11
8984 #define GLK_PW_CTL_IDX_AUX_C 10
8985 #define GLK_PW_CTL_IDX_AUX_B 9
8986 #define GLK_PW_CTL_IDX_AUX_A 8
8987 #define CNL_PW_CTL_IDX_DDI_F 6
8988 #define SKL_PW_CTL_IDX_DDI_D 4
8989 #define SKL_PW_CTL_IDX_DDI_C 3
8990 #define SKL_PW_CTL_IDX_DDI_B 2
8991 #define SKL_PW_CTL_IDX_DDI_A_E 1
8992 #define GLK_PW_CTL_IDX_DDI_A 1
8993 #define SKL_PW_CTL_IDX_MISC_IO 0
8995 /* ICL - power wells */
8996 #define ICL_PW_CTL_IDX_PW_4 3
8997 #define ICL_PW_CTL_IDX_PW_3 2
8998 #define ICL_PW_CTL_IDX_PW_2 1
8999 #define ICL_PW_CTL_IDX_PW_1 0
9001 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
9002 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
9003 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
9004 #define ICL_PW_CTL_IDX_AUX_TBT4 11
9005 #define ICL_PW_CTL_IDX_AUX_TBT3 10
9006 #define ICL_PW_CTL_IDX_AUX_TBT2 9
9007 #define ICL_PW_CTL_IDX_AUX_TBT1 8
9008 #define ICL_PW_CTL_IDX_AUX_F 5
9009 #define ICL_PW_CTL_IDX_AUX_E 4
9010 #define ICL_PW_CTL_IDX_AUX_D 3
9011 #define ICL_PW_CTL_IDX_AUX_C 2
9012 #define ICL_PW_CTL_IDX_AUX_B 1
9013 #define ICL_PW_CTL_IDX_AUX_A 0
9015 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
9016 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
9017 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
9018 #define ICL_PW_CTL_IDX_DDI_F 5
9019 #define ICL_PW_CTL_IDX_DDI_E 4
9020 #define ICL_PW_CTL_IDX_DDI_D 3
9021 #define ICL_PW_CTL_IDX_DDI_C 2
9022 #define ICL_PW_CTL_IDX_DDI_B 1
9023 #define ICL_PW_CTL_IDX_DDI_A 0
9025 /* HSW - power well misc debug registers */
9026 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
9027 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
9028 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
9029 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
9030 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
9032 /* SKL Fuse Status */
9033 enum skl_power_gate {
9041 #define SKL_FUSE_STATUS _MMIO(0x42000)
9042 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
9044 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9045 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9047 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
9048 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9050 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9051 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9053 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
9054 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9055 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9057 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9058 #define _CNL_AUX_ANAOVRD1_B 0x162250
9059 #define _CNL_AUX_ANAOVRD1_C 0x162210
9060 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
9061 #define _CNL_AUX_ANAOVRD1_F 0x162A90
9062 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9063 _CNL_AUX_ANAOVRD1_B, \
9064 _CNL_AUX_ANAOVRD1_C, \
9065 _CNL_AUX_ANAOVRD1_D, \
9066 _CNL_AUX_ANAOVRD1_F))
9067 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
9068 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
9070 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9071 #define _ICL_AUX_ANAOVRD1_A 0x162398
9072 #define _ICL_AUX_ANAOVRD1_B 0x6C398
9073 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9074 _ICL_AUX_ANAOVRD1_A, \
9075 _ICL_AUX_ANAOVRD1_B))
9076 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9077 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9079 /* HDCP Key Registers */
9080 #define HDCP_KEY_CONF _MMIO(0x66c00)
9081 #define HDCP_AKSV_SEND_TRIGGER BIT(31)
9082 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
9083 #define HDCP_KEY_LOAD_TRIGGER BIT(8)
9084 #define HDCP_KEY_STATUS _MMIO(0x66c04)
9085 #define HDCP_FUSE_IN_PROGRESS BIT(7)
9086 #define HDCP_FUSE_ERROR BIT(6)
9087 #define HDCP_FUSE_DONE BIT(5)
9088 #define HDCP_KEY_LOAD_STATUS BIT(1)
9089 #define HDCP_KEY_LOAD_DONE BIT(0)
9090 #define HDCP_AKSV_LO _MMIO(0x66c10)
9091 #define HDCP_AKSV_HI _MMIO(0x66c14)
9093 /* HDCP Repeater Registers */
9094 #define HDCP_REP_CTL _MMIO(0x66d00)
9095 #define HDCP_DDIB_REP_PRESENT BIT(30)
9096 #define HDCP_DDIA_REP_PRESENT BIT(29)
9097 #define HDCP_DDIC_REP_PRESENT BIT(28)
9098 #define HDCP_DDID_REP_PRESENT BIT(27)
9099 #define HDCP_DDIF_REP_PRESENT BIT(26)
9100 #define HDCP_DDIE_REP_PRESENT BIT(25)
9101 #define HDCP_DDIB_SHA1_M0 (1 << 20)
9102 #define HDCP_DDIA_SHA1_M0 (2 << 20)
9103 #define HDCP_DDIC_SHA1_M0 (3 << 20)
9104 #define HDCP_DDID_SHA1_M0 (4 << 20)
9105 #define HDCP_DDIF_SHA1_M0 (5 << 20)
9106 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
9107 #define HDCP_SHA1_BUSY BIT(16)
9108 #define HDCP_SHA1_READY BIT(17)
9109 #define HDCP_SHA1_COMPLETE BIT(18)
9110 #define HDCP_SHA1_V_MATCH BIT(19)
9111 #define HDCP_SHA1_TEXT_32 (1 << 1)
9112 #define HDCP_SHA1_COMPLETE_HASH (2 << 1)
9113 #define HDCP_SHA1_TEXT_24 (4 << 1)
9114 #define HDCP_SHA1_TEXT_16 (5 << 1)
9115 #define HDCP_SHA1_TEXT_8 (6 << 1)
9116 #define HDCP_SHA1_TEXT_0 (7 << 1)
9117 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
9118 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
9119 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
9120 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
9121 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
9122 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
9123 #define HDCP_SHA_TEXT _MMIO(0x66d18)
9125 /* HDCP Auth Registers */
9126 #define _PORTA_HDCP_AUTHENC 0x66800
9127 #define _PORTB_HDCP_AUTHENC 0x66500
9128 #define _PORTC_HDCP_AUTHENC 0x66600
9129 #define _PORTD_HDCP_AUTHENC 0x66700
9130 #define _PORTE_HDCP_AUTHENC 0x66A00
9131 #define _PORTF_HDCP_AUTHENC 0x66900
9132 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
9133 _PORTA_HDCP_AUTHENC, \
9134 _PORTB_HDCP_AUTHENC, \
9135 _PORTC_HDCP_AUTHENC, \
9136 _PORTD_HDCP_AUTHENC, \
9137 _PORTE_HDCP_AUTHENC, \
9138 _PORTF_HDCP_AUTHENC) + (x))
9139 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
9140 #define HDCP_CONF_CAPTURE_AN BIT(0)
9141 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
9142 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
9143 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
9144 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9145 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9146 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9147 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9148 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9149 #define HDCP_STATUS_STREAM_A_ENC BIT(31)
9150 #define HDCP_STATUS_STREAM_B_ENC BIT(30)
9151 #define HDCP_STATUS_STREAM_C_ENC BIT(29)
9152 #define HDCP_STATUS_STREAM_D_ENC BIT(28)
9153 #define HDCP_STATUS_AUTH BIT(21)
9154 #define HDCP_STATUS_ENC BIT(20)
9155 #define HDCP_STATUS_RI_MATCH BIT(19)
9156 #define HDCP_STATUS_R0_READY BIT(18)
9157 #define HDCP_STATUS_AN_READY BIT(17)
9158 #define HDCP_STATUS_CIPHER BIT(16)
9159 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9161 /* HDCP2.2 Registers */
9162 #define _PORTA_HDCP2_BASE 0x66800
9163 #define _PORTB_HDCP2_BASE 0x66500
9164 #define _PORTC_HDCP2_BASE 0x66600
9165 #define _PORTD_HDCP2_BASE 0x66700
9166 #define _PORTE_HDCP2_BASE 0x66A00
9167 #define _PORTF_HDCP2_BASE 0x66900
9168 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
9169 _PORTA_HDCP2_BASE, \
9170 _PORTB_HDCP2_BASE, \
9171 _PORTC_HDCP2_BASE, \
9172 _PORTD_HDCP2_BASE, \
9173 _PORTE_HDCP2_BASE, \
9174 _PORTF_HDCP2_BASE) + (x))
9176 #define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
9177 #define AUTH_LINK_AUTHENTICATED BIT(31)
9178 #define AUTH_LINK_TYPE BIT(30)
9179 #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
9180 #define AUTH_CLR_KEYS BIT(18)
9182 #define HDCP2_CTL_DDI(port) _PORT_HDCP2_BASE(port, 0xB0)
9183 #define CTL_LINK_ENCRYPTION_REQ BIT(31)
9185 #define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
9186 #define STREAM_ENCRYPTION_STATUS_A BIT(31)
9187 #define STREAM_ENCRYPTION_STATUS_B BIT(30)
9188 #define STREAM_ENCRYPTION_STATUS_C BIT(29)
9189 #define LINK_TYPE_STATUS BIT(22)
9190 #define LINK_AUTH_STATUS BIT(21)
9191 #define LINK_ENCRYPTION_STATUS BIT(20)
9193 /* Per-pipe DDI Function Control */
9194 #define _TRANS_DDI_FUNC_CTL_A 0x60400
9195 #define _TRANS_DDI_FUNC_CTL_B 0x61400
9196 #define _TRANS_DDI_FUNC_CTL_C 0x62400
9197 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9198 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
9199 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9200 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9202 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
9203 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9204 #define TRANS_DDI_PORT_MASK (7 << 28)
9205 #define TRANS_DDI_PORT_SHIFT 28
9206 #define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
9207 #define TRANS_DDI_PORT_NONE (0 << 28)
9208 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9209 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9210 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9211 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9212 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9213 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9214 #define TRANS_DDI_BPC_MASK (7 << 20)
9215 #define TRANS_DDI_BPC_8 (0 << 20)
9216 #define TRANS_DDI_BPC_10 (1 << 20)
9217 #define TRANS_DDI_BPC_6 (2 << 20)
9218 #define TRANS_DDI_BPC_12 (3 << 20)
9219 #define TRANS_DDI_PVSYNC (1 << 17)
9220 #define TRANS_DDI_PHSYNC (1 << 16)
9221 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9222 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9223 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9224 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9225 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9226 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9227 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9228 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9229 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9230 #define TRANS_DDI_BFI_ENABLE (1 << 4)
9231 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9232 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9233 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9234 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9235 | TRANS_DDI_HDMI_SCRAMBLING)
9237 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
9238 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
9239 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
9240 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
9241 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
9242 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
9243 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
9244 _TRANS_DDI_FUNC_CTL2_A)
9245 #define PORT_SYNC_MODE_ENABLE (1 << 4)
9246 #define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
9247 #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
9248 #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
9250 /* DisplayPort Transport Control */
9251 #define _DP_TP_CTL_A 0x64040
9252 #define _DP_TP_CTL_B 0x64140
9253 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9254 #define DP_TP_CTL_ENABLE (1 << 31)
9255 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
9256 #define DP_TP_CTL_MODE_SST (0 << 27)
9257 #define DP_TP_CTL_MODE_MST (1 << 27)
9258 #define DP_TP_CTL_FORCE_ACT (1 << 25)
9259 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9260 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9261 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9262 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9263 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9264 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9265 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9266 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
9267 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
9268 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
9270 /* DisplayPort Transport Status */
9271 #define _DP_TP_STATUS_A 0x64044
9272 #define _DP_TP_STATUS_B 0x64144
9273 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
9274 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
9275 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
9276 #define DP_TP_STATUS_ACT_SENT (1 << 24)
9277 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
9278 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
9279 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
9280 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
9281 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
9283 /* DDI Buffer Control */
9284 #define _DDI_BUF_CTL_A 0x64000
9285 #define _DDI_BUF_CTL_B 0x64100
9286 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
9287 #define DDI_BUF_CTL_ENABLE (1 << 31)
9288 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
9289 #define DDI_BUF_EMP_MASK (0xf << 24)
9290 #define DDI_BUF_PORT_REVERSAL (1 << 16)
9291 #define DDI_BUF_IS_IDLE (1 << 7)
9292 #define DDI_A_4_LANES (1 << 4)
9293 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
9294 #define DDI_PORT_WIDTH_MASK (7 << 1)
9295 #define DDI_PORT_WIDTH_SHIFT 1
9296 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
9298 /* DDI Buffer Translations */
9299 #define _DDI_BUF_TRANS_A 0x64E00
9300 #define _DDI_BUF_TRANS_B 0x64E60
9301 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
9302 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
9303 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
9305 /* Sideband Interface (SBI) is programmed indirectly, via
9306 * SBI_ADDR, which contains the register offset; and SBI_DATA,
9307 * which contains the payload */
9308 #define SBI_ADDR _MMIO(0xC6000)
9309 #define SBI_DATA _MMIO(0xC6004)
9310 #define SBI_CTL_STAT _MMIO(0xC6008)
9311 #define SBI_CTL_DEST_ICLK (0x0 << 16)
9312 #define SBI_CTL_DEST_MPHY (0x1 << 16)
9313 #define SBI_CTL_OP_IORD (0x2 << 8)
9314 #define SBI_CTL_OP_IOWR (0x3 << 8)
9315 #define SBI_CTL_OP_CRRD (0x6 << 8)
9316 #define SBI_CTL_OP_CRWR (0x7 << 8)
9317 #define SBI_RESPONSE_FAIL (0x1 << 1)
9318 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
9319 #define SBI_BUSY (0x1 << 0)
9320 #define SBI_READY (0x0 << 0)
9323 #define SBI_SSCDIVINTPHASE 0x0200
9324 #define SBI_SSCDIVINTPHASE6 0x0600
9325 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
9326 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
9327 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
9328 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
9329 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
9330 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
9331 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
9332 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
9333 #define SBI_SSCDITHPHASE 0x0204
9334 #define SBI_SSCCTL 0x020c
9335 #define SBI_SSCCTL6 0x060C
9336 #define SBI_SSCCTL_PATHALT (1 << 3)
9337 #define SBI_SSCCTL_DISABLE (1 << 0)
9338 #define SBI_SSCAUXDIV6 0x0610
9339 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
9340 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
9341 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
9342 #define SBI_DBUFF0 0x2a00
9343 #define SBI_GEN0 0x1f00
9344 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
9346 /* LPT PIXCLK_GATE */
9347 #define PIXCLK_GATE _MMIO(0xC6020)
9348 #define PIXCLK_GATE_UNGATE (1 << 0)
9349 #define PIXCLK_GATE_GATE (0 << 0)
9352 #define SPLL_CTL _MMIO(0x46020)
9353 #define SPLL_PLL_ENABLE (1 << 31)
9354 #define SPLL_PLL_SSC (1 << 28)
9355 #define SPLL_PLL_NON_SSC (2 << 28)
9356 #define SPLL_PLL_LCPLL (3 << 28)
9357 #define SPLL_PLL_REF_MASK (3 << 28)
9358 #define SPLL_PLL_FREQ_810MHz (0 << 26)
9359 #define SPLL_PLL_FREQ_1350MHz (1 << 26)
9360 #define SPLL_PLL_FREQ_2700MHz (2 << 26)
9361 #define SPLL_PLL_FREQ_MASK (3 << 26)
9364 #define _WRPLL_CTL1 0x46040
9365 #define _WRPLL_CTL2 0x46060
9366 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
9367 #define WRPLL_PLL_ENABLE (1 << 31)
9368 #define WRPLL_PLL_SSC (1 << 28)
9369 #define WRPLL_PLL_NON_SSC (2 << 28)
9370 #define WRPLL_PLL_LCPLL (3 << 28)
9371 #define WRPLL_PLL_REF_MASK (3 << 28)
9372 /* WRPLL divider programming */
9373 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
9374 #define WRPLL_DIVIDER_REF_MASK (0xff)
9375 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
9376 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
9377 #define WRPLL_DIVIDER_POST_SHIFT 8
9378 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
9379 #define WRPLL_DIVIDER_FB_SHIFT 16
9380 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
9382 /* Port clock selection */
9383 #define _PORT_CLK_SEL_A 0x46100
9384 #define _PORT_CLK_SEL_B 0x46104
9385 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
9386 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
9387 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
9388 #define PORT_CLK_SEL_LCPLL_810 (2 << 29)
9389 #define PORT_CLK_SEL_SPLL (3 << 29)
9390 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
9391 #define PORT_CLK_SEL_WRPLL1 (4 << 29)
9392 #define PORT_CLK_SEL_WRPLL2 (5 << 29)
9393 #define PORT_CLK_SEL_NONE (7 << 29)
9394 #define PORT_CLK_SEL_MASK (7 << 29)
9396 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
9397 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
9398 #define DDI_CLK_SEL_NONE (0x0 << 28)
9399 #define DDI_CLK_SEL_MG (0x8 << 28)
9400 #define DDI_CLK_SEL_TBT_162 (0xC << 28)
9401 #define DDI_CLK_SEL_TBT_270 (0xD << 28)
9402 #define DDI_CLK_SEL_TBT_540 (0xE << 28)
9403 #define DDI_CLK_SEL_TBT_810 (0xF << 28)
9404 #define DDI_CLK_SEL_MASK (0xF << 28)
9406 /* Transcoder clock selection */
9407 #define _TRANS_CLK_SEL_A 0x46140
9408 #define _TRANS_CLK_SEL_B 0x46144
9409 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
9410 /* For each transcoder, we need to select the corresponding port clock */
9411 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
9412 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
9414 #define CDCLK_FREQ _MMIO(0x46200)
9416 #define _TRANSA_MSA_MISC 0x60410
9417 #define _TRANSB_MSA_MISC 0x61410
9418 #define _TRANSC_MSA_MISC 0x62410
9419 #define _TRANS_EDP_MSA_MISC 0x6f410
9420 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
9422 #define TRANS_MSA_SYNC_CLK (1 << 0)
9423 #define TRANS_MSA_SAMPLING_444 (2 << 1)
9424 #define TRANS_MSA_CLRSP_YCBCR (2 << 3)
9425 #define TRANS_MSA_6_BPC (0 << 5)
9426 #define TRANS_MSA_8_BPC (1 << 5)
9427 #define TRANS_MSA_10_BPC (2 << 5)
9428 #define TRANS_MSA_12_BPC (3 << 5)
9429 #define TRANS_MSA_16_BPC (4 << 5)
9430 #define TRANS_MSA_CEA_RANGE (1 << 3)
9433 #define LCPLL_CTL _MMIO(0x130040)
9434 #define LCPLL_PLL_DISABLE (1 << 31)
9435 #define LCPLL_PLL_LOCK (1 << 30)
9436 #define LCPLL_CLK_FREQ_MASK (3 << 26)
9437 #define LCPLL_CLK_FREQ_450 (0 << 26)
9438 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
9439 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
9440 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
9441 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
9442 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
9443 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
9444 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
9445 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
9446 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
9453 #define CDCLK_CTL _MMIO(0x46000)
9454 #define CDCLK_FREQ_SEL_MASK (3 << 26)
9455 #define CDCLK_FREQ_450_432 (0 << 26)
9456 #define CDCLK_FREQ_540 (1 << 26)
9457 #define CDCLK_FREQ_337_308 (2 << 26)
9458 #define CDCLK_FREQ_675_617 (3 << 26)
9459 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
9460 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
9461 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
9462 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
9463 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
9464 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
9465 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
9466 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
9467 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
9468 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
9469 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
9472 #define LCPLL1_CTL _MMIO(0x46010)
9473 #define LCPLL2_CTL _MMIO(0x46014)
9474 #define LCPLL_PLL_ENABLE (1 << 31)
9477 #define DPLL_CTRL1 _MMIO(0x6C058)
9478 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
9479 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
9480 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
9481 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
9482 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
9483 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
9484 #define DPLL_CTRL1_LINK_RATE_2700 0
9485 #define DPLL_CTRL1_LINK_RATE_1350 1
9486 #define DPLL_CTRL1_LINK_RATE_810 2
9487 #define DPLL_CTRL1_LINK_RATE_1620 3
9488 #define DPLL_CTRL1_LINK_RATE_1080 4
9489 #define DPLL_CTRL1_LINK_RATE_2160 5
9492 #define DPLL_CTRL2 _MMIO(0x6C05C)
9493 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
9494 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
9495 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
9496 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
9497 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
9500 #define DPLL_STATUS _MMIO(0x6C060)
9501 #define DPLL_LOCK(id) (1 << ((id) * 8))
9504 #define _DPLL1_CFGCR1 0x6C040
9505 #define _DPLL2_CFGCR1 0x6C048
9506 #define _DPLL3_CFGCR1 0x6C050
9507 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
9508 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
9509 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
9510 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
9512 #define _DPLL1_CFGCR2 0x6C044
9513 #define _DPLL2_CFGCR2 0x6C04C
9514 #define _DPLL3_CFGCR2 0x6C054
9515 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
9516 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
9517 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
9518 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
9519 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
9520 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
9521 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
9522 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
9523 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
9524 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
9525 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
9526 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
9527 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
9528 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
9529 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
9530 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
9532 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
9533 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
9538 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
9539 #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
9540 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
9542 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
9543 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
9544 21 : (tc_port) + 12))
9545 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
9547 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9548 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
9551 #define DPLL0_ENABLE 0x46010
9552 #define DPLL1_ENABLE 0x46014
9553 #define PLL_ENABLE (1 << 31)
9554 #define PLL_LOCK (1 << 30)
9555 #define PLL_POWER_ENABLE (1 << 27)
9556 #define PLL_POWER_STATE (1 << 26)
9557 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
9559 #define TBT_PLL_ENABLE _MMIO(0x46020)
9561 #define _MG_PLL1_ENABLE 0x46030
9562 #define _MG_PLL2_ENABLE 0x46034
9563 #define _MG_PLL3_ENABLE 0x46038
9564 #define _MG_PLL4_ENABLE 0x4603C
9565 /* Bits are the same as DPLL0_ENABLE */
9566 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
9569 #define _MG_REFCLKIN_CTL_PORT1 0x16892C
9570 #define _MG_REFCLKIN_CTL_PORT2 0x16992C
9571 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C
9572 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
9573 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
9574 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
9575 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
9576 _MG_REFCLKIN_CTL_PORT1, \
9577 _MG_REFCLKIN_CTL_PORT2)
9579 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
9580 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
9581 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
9582 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
9583 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
9584 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
9585 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
9586 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
9587 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
9588 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
9589 _MG_CLKTOP2_CORECLKCTL1_PORT2)
9591 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
9592 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
9593 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
9594 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
9595 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
9596 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
9597 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
9598 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
9599 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
9600 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
9601 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
9602 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
9603 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
9604 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
9605 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
9606 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
9607 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
9608 _MG_CLKTOP2_HSCLKCTL_PORT1, \
9609 _MG_CLKTOP2_HSCLKCTL_PORT2)
9611 #define _MG_PLL_DIV0_PORT1 0x168A00
9612 #define _MG_PLL_DIV0_PORT2 0x169A00
9613 #define _MG_PLL_DIV0_PORT3 0x16AA00
9614 #define _MG_PLL_DIV0_PORT4 0x16BA00
9615 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
9616 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
9617 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
9618 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
9619 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
9620 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
9621 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
9624 #define _MG_PLL_DIV1_PORT1 0x168A04
9625 #define _MG_PLL_DIV1_PORT2 0x169A04
9626 #define _MG_PLL_DIV1_PORT3 0x16AA04
9627 #define _MG_PLL_DIV1_PORT4 0x16BA04
9628 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
9629 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
9630 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
9631 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
9632 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
9633 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
9634 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
9635 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
9636 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
9639 #define _MG_PLL_LF_PORT1 0x168A08
9640 #define _MG_PLL_LF_PORT2 0x169A08
9641 #define _MG_PLL_LF_PORT3 0x16AA08
9642 #define _MG_PLL_LF_PORT4 0x16BA08
9643 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
9644 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
9645 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
9646 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
9647 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
9648 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
9649 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
9652 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
9653 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
9654 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
9655 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
9656 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
9657 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
9658 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
9659 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
9660 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
9661 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
9662 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
9663 _MG_PLL_FRAC_LOCK_PORT1, \
9664 _MG_PLL_FRAC_LOCK_PORT2)
9666 #define _MG_PLL_SSC_PORT1 0x168A10
9667 #define _MG_PLL_SSC_PORT2 0x169A10
9668 #define _MG_PLL_SSC_PORT3 0x16AA10
9669 #define _MG_PLL_SSC_PORT4 0x16BA10
9670 #define MG_PLL_SSC_EN (1 << 28)
9671 #define MG_PLL_SSC_TYPE(x) ((x) << 26)
9672 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
9673 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
9674 #define MG_PLL_SSC_FLLEN (1 << 9)
9675 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
9676 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
9679 #define _MG_PLL_BIAS_PORT1 0x168A14
9680 #define _MG_PLL_BIAS_PORT2 0x169A14
9681 #define _MG_PLL_BIAS_PORT3 0x16AA14
9682 #define _MG_PLL_BIAS_PORT4 0x16BA14
9683 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
9684 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
9685 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
9686 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
9687 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
9688 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
9689 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
9690 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
9691 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
9692 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
9693 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
9694 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
9695 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
9696 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
9699 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
9700 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
9701 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
9702 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
9703 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
9704 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
9705 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
9706 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
9707 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
9708 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
9709 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
9710 _MG_PLL_TDC_COLDST_BIAS_PORT2)
9712 #define _CNL_DPLL0_CFGCR0 0x6C000
9713 #define _CNL_DPLL1_CFGCR0 0x6C080
9714 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
9715 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
9716 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
9717 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
9718 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
9719 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
9720 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
9721 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
9722 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
9723 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
9724 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
9725 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
9726 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9727 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9728 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9729 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9730 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9732 #define _CNL_DPLL0_CFGCR1 0x6C004
9733 #define _CNL_DPLL1_CFGCR1 0x6C084
9734 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9735 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9736 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9737 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
9738 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9739 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9740 #define DPLL_CFGCR1_KDIV_SHIFT (6)
9741 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9742 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
9743 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
9744 #define DPLL_CFGCR1_KDIV_4 (4 << 6)
9745 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9746 #define DPLL_CFGCR1_PDIV_SHIFT (2)
9747 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9748 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
9749 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
9750 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
9751 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
9752 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9753 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
9754 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9756 #define _ICL_DPLL0_CFGCR0 0x164000
9757 #define _ICL_DPLL1_CFGCR0 0x164080
9758 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
9761 #define _ICL_DPLL0_CFGCR1 0x164004
9762 #define _ICL_DPLL1_CFGCR1 0x164084
9763 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
9766 /* BXT display engine PLL */
9767 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
9768 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
9769 #define BXT_DE_PLL_RATIO_MASK 0xff
9771 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
9772 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
9773 #define BXT_DE_PLL_LOCK (1 << 30)
9774 #define CNL_CDCLK_PLL_RATIO(x) (x)
9775 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
9778 #define DC_STATE_EN _MMIO(0x45504)
9779 #define DC_STATE_DISABLE 0
9780 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
9781 #define DC_STATE_EN_DC9 (1 << 3)
9782 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
9783 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9785 #define DC_STATE_DEBUG _MMIO(0x45520)
9786 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
9787 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
9789 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
9790 #define BXT_REQ_DATA_MASK 0x3F
9791 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
9792 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
9793 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
9795 #define BXT_D_CR_DRP0_DUNIT8 0x1000
9796 #define BXT_D_CR_DRP0_DUNIT9 0x1200
9797 #define BXT_D_CR_DRP0_DUNIT_START 8
9798 #define BXT_D_CR_DRP0_DUNIT_END 11
9799 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
9800 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
9801 BXT_D_CR_DRP0_DUNIT9))
9802 #define BXT_DRAM_RANK_MASK 0x3
9803 #define BXT_DRAM_RANK_SINGLE 0x1
9804 #define BXT_DRAM_RANK_DUAL 0x3
9805 #define BXT_DRAM_WIDTH_MASK (0x3 << 4)
9806 #define BXT_DRAM_WIDTH_SHIFT 4
9807 #define BXT_DRAM_WIDTH_X8 (0x0 << 4)
9808 #define BXT_DRAM_WIDTH_X16 (0x1 << 4)
9809 #define BXT_DRAM_WIDTH_X32 (0x2 << 4)
9810 #define BXT_DRAM_WIDTH_X64 (0x3 << 4)
9811 #define BXT_DRAM_SIZE_MASK (0x7 << 6)
9812 #define BXT_DRAM_SIZE_SHIFT 6
9813 #define BXT_DRAM_SIZE_4GB (0x0 << 6)
9814 #define BXT_DRAM_SIZE_6GB (0x1 << 6)
9815 #define BXT_DRAM_SIZE_8GB (0x2 << 6)
9816 #define BXT_DRAM_SIZE_12GB (0x3 << 6)
9817 #define BXT_DRAM_SIZE_16GB (0x4 << 6)
9819 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
9820 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
9821 #define SKL_REQ_DATA_MASK (0xF << 0)
9823 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
9824 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
9825 #define SKL_DRAM_S_SHIFT 16
9826 #define SKL_DRAM_SIZE_MASK 0x3F
9827 #define SKL_DRAM_WIDTH_MASK (0x3 << 8)
9828 #define SKL_DRAM_WIDTH_SHIFT 8
9829 #define SKL_DRAM_WIDTH_X8 (0x0 << 8)
9830 #define SKL_DRAM_WIDTH_X16 (0x1 << 8)
9831 #define SKL_DRAM_WIDTH_X32 (0x2 << 8)
9832 #define SKL_DRAM_RANK_MASK (0x1 << 10)
9833 #define SKL_DRAM_RANK_SHIFT 10
9834 #define SKL_DRAM_RANK_SINGLE (0x0 << 10)
9835 #define SKL_DRAM_RANK_DUAL (0x1 << 10)
9837 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9838 * since on HSW we can't write to it using I915_WRITE. */
9839 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9840 #define D_COMP_BDW _MMIO(0x138144)
9841 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
9842 #define D_COMP_COMP_FORCE (1 << 8)
9843 #define D_COMP_COMP_DISABLE (1 << 0)
9845 /* Pipe WM_LINETIME - watermark line time */
9846 #define _PIPE_WM_LINETIME_A 0x45270
9847 #define _PIPE_WM_LINETIME_B 0x45274
9848 #define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9849 #define PIPE_WM_LINETIME_MASK (0x1ff)
9850 #define PIPE_WM_LINETIME_TIME(x) ((x))
9851 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff << 16)
9852 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x) << 16)
9855 #define SFUSE_STRAP _MMIO(0xc2014)
9856 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
9857 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
9858 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
9859 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
9860 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
9861 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
9862 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
9863 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
9865 #define WM_MISC _MMIO(0x45260)
9866 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
9868 #define WM_DBG _MMIO(0x45280)
9869 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
9870 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
9871 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
9874 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
9875 #define _PIPE_A_CSC_COEFF_BY 0x49014
9876 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
9877 #define _PIPE_A_CSC_COEFF_BU 0x4901c
9878 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9879 #define _PIPE_A_CSC_COEFF_BV 0x49024
9880 #define _PIPE_A_CSC_MODE 0x49028
9881 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9882 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9883 #define CSC_MODE_YUV_TO_RGB (1 << 0)
9884 #define _PIPE_A_CSC_PREOFF_HI 0x49030
9885 #define _PIPE_A_CSC_PREOFF_ME 0x49034
9886 #define _PIPE_A_CSC_PREOFF_LO 0x49038
9887 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
9888 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
9889 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
9891 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
9892 #define _PIPE_B_CSC_COEFF_BY 0x49114
9893 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
9894 #define _PIPE_B_CSC_COEFF_BU 0x4911c
9895 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
9896 #define _PIPE_B_CSC_COEFF_BV 0x49124
9897 #define _PIPE_B_CSC_MODE 0x49128
9898 #define _PIPE_B_CSC_PREOFF_HI 0x49130
9899 #define _PIPE_B_CSC_PREOFF_ME 0x49134
9900 #define _PIPE_B_CSC_PREOFF_LO 0x49138
9901 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
9902 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
9903 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
9905 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9906 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9907 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9908 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9909 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9910 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9911 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9912 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9913 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9914 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9915 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9916 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9917 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9919 /* pipe degamma/gamma LUTs on IVB+ */
9920 #define _PAL_PREC_INDEX_A 0x4A400
9921 #define _PAL_PREC_INDEX_B 0x4AC00
9922 #define _PAL_PREC_INDEX_C 0x4B400
9923 #define PAL_PREC_10_12_BIT (0 << 31)
9924 #define PAL_PREC_SPLIT_MODE (1 << 31)
9925 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
9926 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
9927 #define _PAL_PREC_DATA_A 0x4A404
9928 #define _PAL_PREC_DATA_B 0x4AC04
9929 #define _PAL_PREC_DATA_C 0x4B404
9930 #define _PAL_PREC_GC_MAX_A 0x4A410
9931 #define _PAL_PREC_GC_MAX_B 0x4AC10
9932 #define _PAL_PREC_GC_MAX_C 0x4B410
9933 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9934 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9935 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
9936 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
9937 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
9938 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
9940 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9941 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9942 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9943 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9945 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
9946 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
9947 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
9948 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
9949 #define _PRE_CSC_GAMC_DATA_A 0x4A488
9950 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
9951 #define _PRE_CSC_GAMC_DATA_C 0x4B488
9953 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9954 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9956 /* pipe CSC & degamma/gamma LUTs on CHV */
9957 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9958 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9959 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9960 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9961 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9962 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9963 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9964 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9965 #define CGM_PIPE_MODE_GAMMA (1 << 2)
9966 #define CGM_PIPE_MODE_CSC (1 << 1)
9967 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9969 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9970 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9971 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9972 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9973 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9974 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9975 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9976 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9978 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9979 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9980 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9981 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9982 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9983 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9984 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9985 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9987 /* MIPI DSI registers */
9989 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9990 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9993 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
9996 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9997 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9998 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9999 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
10001 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090
10002 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890
10003 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10004 _ICL_DSI_ESC_CLK_DIV0, \
10005 _ICL_DSI_ESC_CLK_DIV1)
10006 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190
10007 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
10008 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
10009 _ICL_DPHY_ESC_CLK_DIV0, \
10010 _ICL_DPHY_ESC_CLK_DIV1)
10011 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
10012 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
10013 #define ICL_ESC_CLK_DIV_MASK 0x1ff
10014 #define ICL_ESC_CLK_DIV_SHIFT 0
10015 #define DSI_MAX_ESC_CLK 20000 /* in KHz */
10017 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
10018 #define GEN4_TIMESTAMP _MMIO(0x2358)
10019 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
10020 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
10022 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
10023 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
10024 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
10025 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
10026 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
10028 #define _PIPE_FRMTMSTMP_A 0x70048
10029 #define PIPE_FRMTMSTMP(pipe) \
10030 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
10032 /* BXT MIPI clock controls */
10033 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
10035 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
10036 #define BXT_MIPI1_DIV_SHIFT 26
10037 #define BXT_MIPI2_DIV_SHIFT 10
10038 #define BXT_MIPI_DIV_SHIFT(port) \
10039 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
10040 BXT_MIPI2_DIV_SHIFT)
10042 /* TX control divider to select actual TX clock output from (8x/var) */
10043 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
10044 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
10045 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
10046 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
10047 BXT_MIPI2_TX_ESCLK_SHIFT)
10048 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
10049 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
10050 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
10051 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
10052 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
10053 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
10054 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
10055 /* RX upper control divider to select actual RX clock output from 8x */
10056 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
10057 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
10058 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
10059 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
10060 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
10061 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
10062 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
10063 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
10064 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
10065 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
10066 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
10067 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
10068 /* 8/3X divider to select the actual 8/3X clock output from 8x */
10069 #define BXT_MIPI1_8X_BY3_SHIFT 19
10070 #define BXT_MIPI2_8X_BY3_SHIFT 3
10071 #define BXT_MIPI_8X_BY3_SHIFT(port) \
10072 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
10073 BXT_MIPI2_8X_BY3_SHIFT)
10074 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
10075 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
10076 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
10077 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
10078 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
10079 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
10080 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
10081 /* RX lower control divider to select actual RX clock output from 8x */
10082 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
10083 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
10084 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
10085 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
10086 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
10087 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
10088 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
10089 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
10090 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
10091 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
10092 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
10093 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
10095 #define RX_DIVIDER_BIT_1_2 0x3
10096 #define RX_DIVIDER_BIT_3_4 0xC
10098 /* BXT MIPI mode configure */
10099 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
10100 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
10101 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
10102 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
10104 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
10105 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
10106 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
10107 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
10109 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
10110 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
10111 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
10112 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
10114 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
10115 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
10116 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10117 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
10118 #define BXT_DSIC_16X_BY1 (0 << 10)
10119 #define BXT_DSIC_16X_BY2 (1 << 10)
10120 #define BXT_DSIC_16X_BY3 (2 << 10)
10121 #define BXT_DSIC_16X_BY4 (3 << 10)
10122 #define BXT_DSIC_16X_MASK (3 << 10)
10123 #define BXT_DSIA_16X_BY1 (0 << 8)
10124 #define BXT_DSIA_16X_BY2 (1 << 8)
10125 #define BXT_DSIA_16X_BY3 (2 << 8)
10126 #define BXT_DSIA_16X_BY4 (3 << 8)
10127 #define BXT_DSIA_16X_MASK (3 << 8)
10128 #define BXT_DSI_FREQ_SEL_SHIFT 8
10129 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
10131 #define BXT_DSI_PLL_RATIO_MAX 0x7D
10132 #define BXT_DSI_PLL_RATIO_MIN 0x22
10133 #define GLK_DSI_PLL_RATIO_MAX 0x6F
10134 #define GLK_DSI_PLL_RATIO_MIN 0x22
10135 #define BXT_DSI_PLL_RATIO_MASK 0xFF
10136 #define BXT_REF_CLOCK_KHZ 19200
10138 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
10139 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
10140 #define BXT_DSI_PLL_LOCKED (1 << 30)
10142 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
10143 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
10144 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
10146 /* BXT port control */
10147 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
10148 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
10149 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
10151 /* ICL DSI MODE control */
10152 #define _ICL_DSI_IO_MODECTL_0 0x6B094
10153 #define _ICL_DSI_IO_MODECTL_1 0x6B894
10154 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
10155 _ICL_DSI_IO_MODECTL_0, \
10156 _ICL_DSI_IO_MODECTL_1)
10157 #define COMBO_PHY_MODE_DSI (1 << 0)
10159 /* Display Stream Splitter Control */
10160 #define DSS_CTL1 _MMIO(0x67400)
10161 #define SPLITTER_ENABLE (1 << 31)
10162 #define JOINER_ENABLE (1 << 30)
10163 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
10164 #define DUAL_LINK_MODE_FRONTBACK (0 << 24)
10165 #define OVERLAP_PIXELS_MASK (0xf << 16)
10166 #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
10167 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10168 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10169 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
10171 #define DSS_CTL2 _MMIO(0x67404)
10172 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
10173 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
10174 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
10175 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
10177 #define _ICL_PIPE_DSS_CTL1_PB 0x78200
10178 #define _ICL_PIPE_DSS_CTL1_PC 0x78400
10179 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10180 _ICL_PIPE_DSS_CTL1_PB, \
10181 _ICL_PIPE_DSS_CTL1_PC)
10182 #define BIG_JOINER_ENABLE (1 << 29)
10183 #define MASTER_BIG_JOINER_ENABLE (1 << 28)
10184 #define VGA_CENTERING_ENABLE (1 << 27)
10186 #define _ICL_PIPE_DSS_CTL2_PB 0x78204
10187 #define _ICL_PIPE_DSS_CTL2_PC 0x78404
10188 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10189 _ICL_PIPE_DSS_CTL2_PB, \
10190 _ICL_PIPE_DSS_CTL2_PC)
10192 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
10193 #define STAP_SELECT (1 << 0)
10195 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
10196 #define HS_IO_CTRL_SELECT (1 << 0)
10198 #define DPI_ENABLE (1 << 31) /* A + C */
10199 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
10200 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
10201 #define DUAL_LINK_MODE_SHIFT 26
10202 #define DUAL_LINK_MODE_MASK (1 << 26)
10203 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
10204 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
10205 #define DITHERING_ENABLE (1 << 25) /* A + C */
10206 #define FLOPPED_HSTX (1 << 23)
10207 #define DE_INVERT (1 << 19) /* XXX */
10208 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
10209 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
10210 #define AFE_LATCHOUT (1 << 17)
10211 #define LP_OUTPUT_HOLD (1 << 16)
10212 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
10213 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
10214 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
10215 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
10216 #define CSB_SHIFT 9
10217 #define CSB_MASK (3 << 9)
10218 #define CSB_20MHZ (0 << 9)
10219 #define CSB_10MHZ (1 << 9)
10220 #define CSB_40MHZ (2 << 9)
10221 #define BANDGAP_MASK (1 << 8)
10222 #define BANDGAP_PNW_CIRCUIT (0 << 8)
10223 #define BANDGAP_LNC_CIRCUIT (1 << 8)
10224 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
10225 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
10226 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
10227 #define TEARING_EFFECT_SHIFT 2 /* A + C */
10228 #define TEARING_EFFECT_MASK (3 << 2)
10229 #define TEARING_EFFECT_OFF (0 << 2)
10230 #define TEARING_EFFECT_DSI (1 << 2)
10231 #define TEARING_EFFECT_GPIO (2 << 2)
10232 #define LANE_CONFIGURATION_SHIFT 0
10233 #define LANE_CONFIGURATION_MASK (3 << 0)
10234 #define LANE_CONFIGURATION_4LANE (0 << 0)
10235 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
10236 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
10238 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10239 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10240 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
10241 #define TEARING_EFFECT_DELAY_SHIFT 0
10242 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
10244 /* XXX: all bits reserved */
10245 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
10247 /* MIPI DSI Controller and D-PHY registers */
10249 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
10250 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
10251 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
10252 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
10253 #define ULPS_STATE_MASK (3 << 1)
10254 #define ULPS_STATE_ENTER (2 << 1)
10255 #define ULPS_STATE_EXIT (1 << 1)
10256 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
10257 #define DEVICE_READY (1 << 0)
10259 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
10260 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
10261 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
10262 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
10263 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
10264 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
10265 #define TEARING_EFFECT (1 << 31)
10266 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
10267 #define GEN_READ_DATA_AVAIL (1 << 29)
10268 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
10269 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
10270 #define RX_PROT_VIOLATION (1 << 26)
10271 #define RX_INVALID_TX_LENGTH (1 << 25)
10272 #define ACK_WITH_NO_ERROR (1 << 24)
10273 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
10274 #define LP_RX_TIMEOUT (1 << 22)
10275 #define HS_TX_TIMEOUT (1 << 21)
10276 #define DPI_FIFO_UNDERRUN (1 << 20)
10277 #define LOW_CONTENTION (1 << 19)
10278 #define HIGH_CONTENTION (1 << 18)
10279 #define TXDSI_VC_ID_INVALID (1 << 17)
10280 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
10281 #define TXCHECKSUM_ERROR (1 << 15)
10282 #define TXECC_MULTIBIT_ERROR (1 << 14)
10283 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
10284 #define TXFALSE_CONTROL_ERROR (1 << 12)
10285 #define RXDSI_VC_ID_INVALID (1 << 11)
10286 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
10287 #define RXCHECKSUM_ERROR (1 << 9)
10288 #define RXECC_MULTIBIT_ERROR (1 << 8)
10289 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
10290 #define RXFALSE_CONTROL_ERROR (1 << 6)
10291 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
10292 #define RX_LP_TX_SYNC_ERROR (1 << 4)
10293 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
10294 #define RXEOT_SYNC_ERROR (1 << 2)
10295 #define RXSOT_SYNC_ERROR (1 << 1)
10296 #define RXSOT_ERROR (1 << 0)
10298 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
10299 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
10300 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
10301 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
10302 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
10303 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
10304 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
10305 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
10306 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
10307 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
10308 #define VID_MODE_FORMAT_MASK (0xf << 7)
10309 #define VID_MODE_NOT_SUPPORTED (0 << 7)
10310 #define VID_MODE_FORMAT_RGB565 (1 << 7)
10311 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
10312 #define VID_MODE_FORMAT_RGB666 (3 << 7)
10313 #define VID_MODE_FORMAT_RGB888 (4 << 7)
10314 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
10315 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
10316 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
10317 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
10318 #define DATA_LANES_PRG_REG_SHIFT 0
10319 #define DATA_LANES_PRG_REG_MASK (7 << 0)
10321 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
10322 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
10323 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
10324 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
10326 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
10327 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
10328 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
10329 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
10331 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
10332 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
10333 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
10334 #define TURN_AROUND_TIMEOUT_MASK 0x3f
10336 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
10337 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
10338 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
10339 #define DEVICE_RESET_TIMER_MASK 0xffff
10341 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
10342 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
10343 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
10344 #define VERTICAL_ADDRESS_SHIFT 16
10345 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
10346 #define HORIZONTAL_ADDRESS_SHIFT 0
10347 #define HORIZONTAL_ADDRESS_MASK 0xffff
10349 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
10350 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
10351 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
10352 #define DBI_FIFO_EMPTY_HALF (0 << 0)
10353 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
10354 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
10356 /* regs below are bits 15:0 */
10357 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
10358 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
10359 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
10361 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
10362 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
10363 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
10365 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
10366 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
10367 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
10369 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
10370 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
10371 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
10373 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
10374 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
10375 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
10377 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
10378 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
10379 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
10381 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
10382 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
10383 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
10385 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
10386 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
10387 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
10389 /* regs above are bits 15:0 */
10391 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
10392 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
10393 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
10394 #define DPI_LP_MODE (1 << 6)
10395 #define BACKLIGHT_OFF (1 << 5)
10396 #define BACKLIGHT_ON (1 << 4)
10397 #define COLOR_MODE_OFF (1 << 3)
10398 #define COLOR_MODE_ON (1 << 2)
10399 #define TURN_ON (1 << 1)
10400 #define SHUTDOWN (1 << 0)
10402 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
10403 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
10404 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
10405 #define COMMAND_BYTE_SHIFT 0
10406 #define COMMAND_BYTE_MASK (0x3f << 0)
10408 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
10409 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
10410 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
10411 #define MASTER_INIT_TIMER_SHIFT 0
10412 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
10414 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
10415 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
10416 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
10417 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
10418 #define MAX_RETURN_PKT_SIZE_SHIFT 0
10419 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
10421 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
10422 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
10423 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
10424 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
10425 #define DISABLE_VIDEO_BTA (1 << 3)
10426 #define IP_TG_CONFIG (1 << 2)
10427 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
10428 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
10429 #define VIDEO_MODE_BURST (3 << 0)
10431 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
10432 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
10433 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
10434 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
10435 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
10436 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
10437 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
10438 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
10439 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
10440 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
10441 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
10442 #define CLOCKSTOP (1 << 1)
10443 #define EOT_DISABLE (1 << 0)
10445 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
10446 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
10447 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
10448 #define LP_BYTECLK_SHIFT 0
10449 #define LP_BYTECLK_MASK (0xffff << 0)
10451 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
10452 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
10453 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
10455 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
10456 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
10457 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
10460 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
10461 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
10462 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
10465 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
10466 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
10467 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
10469 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
10470 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
10471 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
10472 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
10473 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
10474 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
10475 #define LONG_PACKET_WORD_COUNT_SHIFT 8
10476 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
10477 #define SHORT_PACKET_PARAM_SHIFT 8
10478 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
10479 #define VIRTUAL_CHANNEL_SHIFT 6
10480 #define VIRTUAL_CHANNEL_MASK (3 << 6)
10481 #define DATA_TYPE_SHIFT 0
10482 #define DATA_TYPE_MASK (0x3f << 0)
10483 /* data type values, see include/video/mipi_display.h */
10485 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
10486 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
10487 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
10488 #define DPI_FIFO_EMPTY (1 << 28)
10489 #define DBI_FIFO_EMPTY (1 << 27)
10490 #define LP_CTRL_FIFO_EMPTY (1 << 26)
10491 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
10492 #define LP_CTRL_FIFO_FULL (1 << 24)
10493 #define HS_CTRL_FIFO_EMPTY (1 << 18)
10494 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
10495 #define HS_CTRL_FIFO_FULL (1 << 16)
10496 #define LP_DATA_FIFO_EMPTY (1 << 10)
10497 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
10498 #define LP_DATA_FIFO_FULL (1 << 8)
10499 #define HS_DATA_FIFO_EMPTY (1 << 2)
10500 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
10501 #define HS_DATA_FIFO_FULL (1 << 0)
10503 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
10504 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
10505 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
10506 #define DBI_HS_LP_MODE_MASK (1 << 0)
10507 #define DBI_LP_MODE (1 << 0)
10508 #define DBI_HS_MODE (0 << 0)
10510 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
10511 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
10512 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
10513 #define EXIT_ZERO_COUNT_SHIFT 24
10514 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
10515 #define TRAIL_COUNT_SHIFT 16
10516 #define TRAIL_COUNT_MASK (0x1f << 16)
10517 #define CLK_ZERO_COUNT_SHIFT 8
10518 #define CLK_ZERO_COUNT_MASK (0xff << 8)
10519 #define PREPARE_COUNT_SHIFT 0
10520 #define PREPARE_COUNT_MASK (0x3f << 0)
10522 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088
10523 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888
10524 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
10525 _ICL_DSI_T_INIT_MASTER_0,\
10526 _ICL_DSI_T_INIT_MASTER_1)
10528 #define _DPHY_CLK_TIMING_PARAM_0 0x162180
10529 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180
10530 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10531 _DPHY_CLK_TIMING_PARAM_0,\
10532 _DPHY_CLK_TIMING_PARAM_1)
10533 #define _DSI_CLK_TIMING_PARAM_0 0x6b080
10534 #define _DSI_CLK_TIMING_PARAM_1 0x6b880
10535 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
10536 _DSI_CLK_TIMING_PARAM_0,\
10537 _DSI_CLK_TIMING_PARAM_1)
10538 #define CLK_PREPARE_OVERRIDE (1 << 31)
10539 #define CLK_PREPARE(x) ((x) << 28)
10540 #define CLK_PREPARE_MASK (0x7 << 28)
10541 #define CLK_PREPARE_SHIFT 28
10542 #define CLK_ZERO_OVERRIDE (1 << 27)
10543 #define CLK_ZERO(x) ((x) << 20)
10544 #define CLK_ZERO_MASK (0xf << 20)
10545 #define CLK_ZERO_SHIFT 20
10546 #define CLK_PRE_OVERRIDE (1 << 19)
10547 #define CLK_PRE(x) ((x) << 16)
10548 #define CLK_PRE_MASK (0x3 << 16)
10549 #define CLK_PRE_SHIFT 16
10550 #define CLK_POST_OVERRIDE (1 << 15)
10551 #define CLK_POST(x) ((x) << 8)
10552 #define CLK_POST_MASK (0x7 << 8)
10553 #define CLK_POST_SHIFT 8
10554 #define CLK_TRAIL_OVERRIDE (1 << 7)
10555 #define CLK_TRAIL(x) ((x) << 0)
10556 #define CLK_TRAIL_MASK (0xf << 0)
10557 #define CLK_TRAIL_SHIFT 0
10559 #define _DPHY_DATA_TIMING_PARAM_0 0x162184
10560 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184
10561 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10562 _DPHY_DATA_TIMING_PARAM_0,\
10563 _DPHY_DATA_TIMING_PARAM_1)
10564 #define _DSI_DATA_TIMING_PARAM_0 0x6B084
10565 #define _DSI_DATA_TIMING_PARAM_1 0x6B884
10566 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
10567 _DSI_DATA_TIMING_PARAM_0,\
10568 _DSI_DATA_TIMING_PARAM_1)
10569 #define HS_PREPARE_OVERRIDE (1 << 31)
10570 #define HS_PREPARE(x) ((x) << 24)
10571 #define HS_PREPARE_MASK (0x7 << 24)
10572 #define HS_PREPARE_SHIFT 24
10573 #define HS_ZERO_OVERRIDE (1 << 23)
10574 #define HS_ZERO(x) ((x) << 16)
10575 #define HS_ZERO_MASK (0xf << 16)
10576 #define HS_ZERO_SHIFT 16
10577 #define HS_TRAIL_OVERRIDE (1 << 15)
10578 #define HS_TRAIL(x) ((x) << 8)
10579 #define HS_TRAIL_MASK (0x7 << 8)
10580 #define HS_TRAIL_SHIFT 8
10581 #define HS_EXIT_OVERRIDE (1 << 7)
10582 #define HS_EXIT(x) ((x) << 0)
10583 #define HS_EXIT_MASK (0x7 << 0)
10584 #define HS_EXIT_SHIFT 0
10586 #define _DPHY_TA_TIMING_PARAM_0 0x162188
10587 #define _DPHY_TA_TIMING_PARAM_1 0x6c188
10588 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10589 _DPHY_TA_TIMING_PARAM_0,\
10590 _DPHY_TA_TIMING_PARAM_1)
10591 #define _DSI_TA_TIMING_PARAM_0 0x6b098
10592 #define _DSI_TA_TIMING_PARAM_1 0x6b898
10593 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
10594 _DSI_TA_TIMING_PARAM_0,\
10595 _DSI_TA_TIMING_PARAM_1)
10596 #define TA_SURE_OVERRIDE (1 << 31)
10597 #define TA_SURE(x) ((x) << 16)
10598 #define TA_SURE_MASK (0x1f << 16)
10599 #define TA_SURE_SHIFT 16
10600 #define TA_GO_OVERRIDE (1 << 15)
10601 #define TA_GO(x) ((x) << 8)
10602 #define TA_GO_MASK (0xf << 8)
10603 #define TA_GO_SHIFT 8
10604 #define TA_GET_OVERRIDE (1 << 7)
10605 #define TA_GET(x) ((x) << 0)
10606 #define TA_GET_MASK (0xf << 0)
10607 #define TA_GET_SHIFT 0
10609 /* DSI transcoder configuration */
10610 #define _DSI_TRANS_FUNC_CONF_0 0x6b030
10611 #define _DSI_TRANS_FUNC_CONF_1 0x6b830
10612 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
10613 _DSI_TRANS_FUNC_CONF_0,\
10614 _DSI_TRANS_FUNC_CONF_1)
10615 #define OP_MODE_MASK (0x3 << 28)
10616 #define OP_MODE_SHIFT 28
10617 #define CMD_MODE_NO_GATE (0x0 << 28)
10618 #define CMD_MODE_TE_GATE (0x1 << 28)
10619 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
10620 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
10621 #define LINK_READY (1 << 20)
10622 #define PIX_FMT_MASK (0x3 << 16)
10623 #define PIX_FMT_SHIFT 16
10624 #define PIX_FMT_RGB565 (0x0 << 16)
10625 #define PIX_FMT_RGB666_PACKED (0x1 << 16)
10626 #define PIX_FMT_RGB666_LOOSE (0x2 << 16)
10627 #define PIX_FMT_RGB888 (0x3 << 16)
10628 #define PIX_FMT_RGB101010 (0x4 << 16)
10629 #define PIX_FMT_RGB121212 (0x5 << 16)
10630 #define PIX_FMT_COMPRESSED (0x6 << 16)
10631 #define BGR_TRANSMISSION (1 << 15)
10632 #define PIX_VIRT_CHAN(x) ((x) << 12)
10633 #define PIX_VIRT_CHAN_MASK (0x3 << 12)
10634 #define PIX_VIRT_CHAN_SHIFT 12
10635 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
10636 #define PIX_BUF_THRESHOLD_SHIFT 10
10637 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
10638 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
10639 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
10640 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
10641 #define CONTINUOUS_CLK_MASK (0x3 << 8)
10642 #define CONTINUOUS_CLK_SHIFT 8
10643 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
10644 #define CLK_HS_OR_LP (0x2 << 8)
10645 #define CLK_HS_CONTINUOUS (0x3 << 8)
10646 #define LINK_CALIBRATION_MASK (0x3 << 4)
10647 #define LINK_CALIBRATION_SHIFT 4
10648 #define CALIBRATION_DISABLED (0x0 << 4)
10649 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
10650 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
10651 #define S3D_ORIENTATION_LANDSCAPE (1 << 1)
10652 #define EOTP_DISABLED (1 << 0)
10654 #define _DSI_CMD_RXCTL_0 0x6b0d4
10655 #define _DSI_CMD_RXCTL_1 0x6b8d4
10656 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
10659 #define READ_UNLOADS_DW (1 << 16)
10660 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
10661 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
10662 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
10663 #define RECEIVED_RESET_TRIGGER (1 << 12)
10664 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
10665 #define RECEIVED_CRC_WAS_LOST (1 << 10)
10666 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
10667 #define NUMBER_RX_PLOAD_DW_SHIFT 0
10669 #define _DSI_CMD_TXCTL_0 0x6b0d0
10670 #define _DSI_CMD_TXCTL_1 0x6b8d0
10671 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
10674 #define KEEP_LINK_IN_HS (1 << 24)
10675 #define FREE_HEADER_CREDIT_MASK (0x1f << 8)
10676 #define FREE_HEADER_CREDIT_SHIFT 0x8
10677 #define FREE_PLOAD_CREDIT_MASK (0xff << 0)
10678 #define FREE_PLOAD_CREDIT_SHIFT 0
10679 #define MAX_HEADER_CREDIT 0x10
10680 #define MAX_PLOAD_CREDIT 0x40
10682 #define _DSI_CMD_TXHDR_0 0x6b100
10683 #define _DSI_CMD_TXHDR_1 0x6b900
10684 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
10687 #define PAYLOAD_PRESENT (1 << 31)
10688 #define LP_DATA_TRANSFER (1 << 30)
10689 #define VBLANK_FENCE (1 << 29)
10690 #define PARAM_WC_MASK (0xffff << 8)
10691 #define PARAM_WC_LOWER_SHIFT 8
10692 #define PARAM_WC_UPPER_SHIFT 16
10693 #define VC_MASK (0x3 << 6)
10695 #define DT_MASK (0x3f << 0)
10698 #define _DSI_CMD_TXPYLD_0 0x6b104
10699 #define _DSI_CMD_TXPYLD_1 0x6b904
10700 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
10701 _DSI_CMD_TXPYLD_0,\
10704 #define _DSI_LP_MSG_0 0x6b0d8
10705 #define _DSI_LP_MSG_1 0x6b8d8
10706 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
10709 #define LPTX_IN_PROGRESS (1 << 17)
10710 #define LINK_IN_ULPS (1 << 16)
10711 #define LINK_ULPS_TYPE_LP11 (1 << 8)
10712 #define LINK_ENTER_ULPS (1 << 0)
10714 /* DSI timeout registers */
10715 #define _DSI_HSTX_TO_0 0x6b044
10716 #define _DSI_HSTX_TO_1 0x6b844
10717 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
10720 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
10721 #define HSTX_TIMEOUT_VALUE_SHIFT 16
10722 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
10723 #define HSTX_TIMED_OUT (1 << 0)
10725 #define _DSI_LPRX_HOST_TO_0 0x6b048
10726 #define _DSI_LPRX_HOST_TO_1 0x6b848
10727 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
10728 _DSI_LPRX_HOST_TO_0,\
10729 _DSI_LPRX_HOST_TO_1)
10730 #define LPRX_TIMED_OUT (1 << 16)
10731 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
10732 #define LPRX_TIMEOUT_VALUE_SHIFT 0
10733 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
10735 #define _DSI_PWAIT_TO_0 0x6b040
10736 #define _DSI_PWAIT_TO_1 0x6b840
10737 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
10740 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
10741 #define PRESET_TIMEOUT_VALUE_SHIFT 16
10742 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
10743 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
10744 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
10745 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
10747 #define _DSI_TA_TO_0 0x6b04c
10748 #define _DSI_TA_TO_1 0x6b84c
10749 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \
10752 #define TA_TIMED_OUT (1 << 16)
10753 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
10754 #define TA_TIMEOUT_VALUE_SHIFT 0
10755 #define TA_TIMEOUT_VALUE(x) ((x) << 0)
10758 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
10759 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
10760 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
10762 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
10763 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
10764 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
10765 #define LP_HS_SSW_CNT_SHIFT 16
10766 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
10767 #define HS_LP_PWR_SW_CNT_SHIFT 0
10768 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
10770 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
10771 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
10772 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
10773 #define STOP_STATE_STALL_COUNTER_SHIFT 0
10774 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
10776 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
10777 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
10778 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
10779 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
10780 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
10781 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
10782 #define RX_CONTENTION_DETECTED (1 << 0)
10784 /* XXX: only pipe A ?!? */
10785 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
10786 #define DBI_TYPEC_ENABLE (1 << 31)
10787 #define DBI_TYPEC_WIP (1 << 30)
10788 #define DBI_TYPEC_OPTION_SHIFT 28
10789 #define DBI_TYPEC_OPTION_MASK (3 << 28)
10790 #define DBI_TYPEC_FREQ_SHIFT 24
10791 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
10792 #define DBI_TYPEC_OVERRIDE (1 << 8)
10793 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
10794 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
10797 /* MIPI adapter registers */
10799 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
10800 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
10801 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
10802 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
10803 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
10804 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
10805 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
10806 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
10807 #define READ_REQUEST_PRIORITY_SHIFT 3
10808 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
10809 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
10810 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
10811 #define RGB_FLIP_TO_BGR (1 << 2)
10813 #define BXT_PIPE_SELECT_SHIFT 7
10814 #define BXT_PIPE_SELECT_MASK (7 << 7)
10815 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
10816 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
10817 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
10818 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
10819 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
10820 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
10821 #define GLK_LP_WAKE (1 << 22)
10822 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
10823 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
10824 #define GLK_FIREWALL_ENABLE (1 << 16)
10825 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
10826 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
10827 #define BXT_DSC_ENABLE (1 << 3)
10828 #define BXT_RGB_FLIP (1 << 2)
10829 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
10830 #define GLK_MIPIIO_ENABLE (1 << 0)
10832 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
10833 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
10834 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
10835 #define DATA_MEM_ADDRESS_SHIFT 5
10836 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
10837 #define DATA_VALID (1 << 0)
10839 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
10840 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
10841 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
10842 #define DATA_LENGTH_SHIFT 0
10843 #define DATA_LENGTH_MASK (0xfffff << 0)
10845 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
10846 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
10847 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
10848 #define COMMAND_MEM_ADDRESS_SHIFT 5
10849 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
10850 #define AUTO_PWG_ENABLE (1 << 2)
10851 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
10852 #define COMMAND_VALID (1 << 0)
10854 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
10855 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
10856 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
10857 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
10858 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
10860 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
10861 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
10862 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
10864 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
10865 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
10866 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
10867 #define READ_DATA_VALID(n) (1 << (n))
10869 /* MOCS (Memory Object Control State) registers */
10870 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
10872 #define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
10873 #define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
10874 #define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
10875 #define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
10876 #define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
10877 /* Media decoder 2 MOCS registers */
10878 #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4)
10880 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
10881 #define PMFLUSHDONE_LNICRSDROP (1 << 20)
10882 #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
10883 #define PMFLUSHDONE_LNEBLK (1 << 22)
10886 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
10887 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
10888 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
10889 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
10890 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
10892 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
10893 #define MMCD_PCLA (1 << 31)
10894 #define MMCD_HOTSPOT_EN (1 << 27)
10896 #define _ICL_PHY_MISC_A 0x64C00
10897 #define _ICL_PHY_MISC_B 0x64C04
10898 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
10900 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
10902 /* Icelake Display Stream Compression Registers */
10903 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
10904 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
10905 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
10906 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
10907 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
10908 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
10909 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10910 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
10911 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
10912 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10913 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
10914 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
10915 #define DSC_VBR_ENABLE (1 << 19)
10916 #define DSC_422_ENABLE (1 << 18)
10917 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
10918 #define DSC_BLOCK_PREDICTION (1 << 16)
10919 #define DSC_LINE_BUF_DEPTH_SHIFT 12
10920 #define DSC_BPC_SHIFT 8
10921 #define DSC_VER_MIN_SHIFT 4
10922 #define DSC_VER_MAJ (0x1 << 0)
10924 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
10925 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
10926 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
10927 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
10928 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
10929 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
10930 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10931 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
10932 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
10933 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10934 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
10935 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
10936 #define DSC_BPP(bpp) ((bpp) << 0)
10938 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
10939 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
10940 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
10941 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
10942 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
10943 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
10944 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10945 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
10946 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
10947 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10948 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
10949 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
10950 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
10951 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
10953 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
10954 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
10955 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
10956 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
10957 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
10958 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
10959 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10960 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
10961 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
10962 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10963 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
10964 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
10965 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
10966 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
10968 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
10969 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
10970 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
10971 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
10972 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
10973 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
10974 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10975 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
10976 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
10977 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10978 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
10979 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
10980 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
10981 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
10983 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
10984 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
10985 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
10986 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
10987 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
10988 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
10989 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10990 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
10991 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
10992 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
10993 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
10994 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
10995 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
10996 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
10998 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
10999 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
11000 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
11001 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
11002 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
11003 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
11004 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11005 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
11006 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
11007 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11008 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
11009 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
11010 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
11011 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
11012 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
11013 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
11015 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
11016 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
11017 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
11018 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
11019 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
11020 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
11021 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11022 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
11023 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
11024 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11025 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
11026 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
11027 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
11028 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
11030 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
11031 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
11032 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
11033 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
11034 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
11035 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
11036 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11037 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
11038 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
11039 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11040 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
11041 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
11042 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
11043 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
11045 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
11046 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
11047 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
11048 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
11049 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
11050 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
11051 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11052 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
11053 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
11054 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11055 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
11056 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
11057 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
11058 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
11060 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
11061 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
11062 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
11063 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
11064 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
11065 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
11066 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11067 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
11068 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
11069 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11070 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
11071 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
11072 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
11073 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
11074 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
11075 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
11077 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
11078 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
11079 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
11080 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
11081 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
11082 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
11083 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11084 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
11085 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
11086 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11087 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
11088 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
11090 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
11091 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
11092 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
11093 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
11094 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
11095 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
11096 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11097 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
11098 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
11099 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11100 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
11101 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
11103 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
11104 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
11105 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
11106 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
11107 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
11108 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
11109 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11110 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
11111 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
11112 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11113 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
11114 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
11116 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
11117 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
11118 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
11119 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
11120 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
11121 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
11122 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11123 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
11124 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
11125 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11126 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
11127 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
11129 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
11130 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
11131 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
11132 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
11133 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
11134 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
11135 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11136 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
11137 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
11138 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11139 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
11140 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
11142 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
11143 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
11144 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
11145 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
11146 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
11147 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
11148 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11149 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
11150 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
11151 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11152 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
11153 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
11154 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
11155 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
11156 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
11158 /* Icelake Rate Control Buffer Threshold Registers */
11159 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
11160 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
11161 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
11162 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
11163 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
11164 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
11165 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
11166 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
11167 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
11168 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
11169 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
11170 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
11171 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11172 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
11173 _ICL_DSC0_RC_BUF_THRESH_0_PC)
11174 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11175 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
11176 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
11177 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11178 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
11179 _ICL_DSC1_RC_BUF_THRESH_0_PC)
11180 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11181 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
11182 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
11184 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
11185 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
11186 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
11187 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
11188 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
11189 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
11190 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
11191 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
11192 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
11193 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
11194 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
11195 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
11196 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11197 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
11198 _ICL_DSC0_RC_BUF_THRESH_1_PC)
11199 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11200 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
11201 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
11202 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11203 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
11204 _ICL_DSC1_RC_BUF_THRESH_1_PC)
11205 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11206 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
11207 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
11209 #define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
11210 #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
11211 #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
11212 #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
11213 #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
11214 #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
11216 #define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
11217 #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
11219 #define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
11220 #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
11222 #endif /* _I915_REG_H_ */