1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "i915_reg_defs.h"
29 #include "display/intel_display_reg_defs.h"
32 * DOC: The i915 register macro definition style guide
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
40 * Keep helper macros near the top. For example, _PIPE() and friends.
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
54 * For single registers, define the register offset first, followed by register
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
120 #define DEPRESENT REG_BIT(9)
122 #define GU_CNTL _MMIO(0x101010)
123 #define LMEM_INIT REG_BIT(7)
124 #define DRIVERFLR REG_BIT(31)
125 #define GU_DEBUG _MMIO(0x101018)
126 #define DRIVERFLR_STATUS REG_BIT(31)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
131 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
132 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
133 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
134 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
135 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
136 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
137 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
138 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
139 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
140 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
141 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
142 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
143 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
147 #define _VGA_MSR_WRITE _MMIO(0x3c2)
149 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
156 #define DEBUG_RESET_I830 _MMIO(0x6070)
157 #define DEBUG_RESET_FULL (1 << 7)
158 #define DEBUG_RESET_RENDER (1 << 8)
159 #define DEBUG_RESET_DISPLAY (1 << 9)
164 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
165 #define IOSF_DEVFN_SHIFT 24
166 #define IOSF_OPCODE_SHIFT 16
167 #define IOSF_PORT_SHIFT 8
168 #define IOSF_BYTE_ENABLES_SHIFT 4
169 #define IOSF_BAR_SHIFT 1
170 #define IOSF_SB_BUSY (1 << 0)
171 #define IOSF_PORT_BUNIT 0x03
172 #define IOSF_PORT_PUNIT 0x04
173 #define IOSF_PORT_NC 0x11
174 #define IOSF_PORT_DPIO 0x12
175 #define IOSF_PORT_GPIO_NC 0x13
176 #define IOSF_PORT_CCK 0x14
177 #define IOSF_PORT_DPIO_2 0x1a
178 #define IOSF_PORT_FLISDSI 0x1b
179 #define IOSF_PORT_GPIO_SC 0x48
180 #define IOSF_PORT_GPIO_SUS 0xa8
181 #define IOSF_PORT_CCU 0xa9
182 #define CHV_IOSF_PORT_GPIO_N 0x13
183 #define CHV_IOSF_PORT_GPIO_SE 0x48
184 #define CHV_IOSF_PORT_GPIO_E 0xa8
185 #define CHV_IOSF_PORT_GPIO_SW 0xb2
186 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
192 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
193 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
194 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
195 #define DPIO_SFR_BYPASS (1 << 1)
196 #define DPIO_CMNRST (1 << 0)
198 #define DPIO_PHY(pipe) ((pipe) >> 1)
201 * Per pipe/PLL DPIO regs
203 #define _VLV_PLL_DW3_CH0 0x800c
204 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
205 #define DPIO_POST_DIV_DAC 0
206 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
207 #define DPIO_POST_DIV_LVDS1 2
208 #define DPIO_POST_DIV_LVDS2 3
209 #define DPIO_K_SHIFT (24) /* 4 bits */
210 #define DPIO_P1_SHIFT (21) /* 3 bits */
211 #define DPIO_P2_SHIFT (16) /* 5 bits */
212 #define DPIO_N_SHIFT (12) /* 4 bits */
213 #define DPIO_ENABLE_CALIBRATION (1 << 11)
214 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
215 #define DPIO_M2DIV_MASK 0xff
216 #define _VLV_PLL_DW3_CH1 0x802c
217 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
219 #define _VLV_PLL_DW5_CH0 0x8014
220 #define DPIO_REFSEL_OVERRIDE 27
221 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
222 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
223 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
224 #define DPIO_PLL_REFCLK_SEL_MASK 3
225 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
226 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
227 #define _VLV_PLL_DW5_CH1 0x8034
228 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
230 #define _VLV_PLL_DW7_CH0 0x801c
231 #define _VLV_PLL_DW7_CH1 0x803c
232 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
234 #define _VLV_PLL_DW8_CH0 0x8040
235 #define _VLV_PLL_DW8_CH1 0x8060
236 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
238 #define VLV_PLL_DW9_BCAST 0xc044
239 #define _VLV_PLL_DW9_CH0 0x8044
240 #define _VLV_PLL_DW9_CH1 0x8064
241 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
243 #define _VLV_PLL_DW10_CH0 0x8048
244 #define _VLV_PLL_DW10_CH1 0x8068
245 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
247 #define _VLV_PLL_DW11_CH0 0x804c
248 #define _VLV_PLL_DW11_CH1 0x806c
249 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
251 /* Spec for ref block start counts at DW10 */
252 #define VLV_REF_DW13 0x80ac
254 #define VLV_CMN_DW0 0x8100
257 * Per DDI channel DPIO regs
260 #define _VLV_PCS_DW0_CH0 0x8200
261 #define _VLV_PCS_DW0_CH1 0x8400
262 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
263 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
264 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
265 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
266 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
268 #define _VLV_PCS01_DW0_CH0 0x200
269 #define _VLV_PCS23_DW0_CH0 0x400
270 #define _VLV_PCS01_DW0_CH1 0x2600
271 #define _VLV_PCS23_DW0_CH1 0x2800
272 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
273 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
275 #define _VLV_PCS_DW1_CH0 0x8204
276 #define _VLV_PCS_DW1_CH1 0x8404
277 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
278 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
279 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
280 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
281 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
282 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
284 #define _VLV_PCS01_DW1_CH0 0x204
285 #define _VLV_PCS23_DW1_CH0 0x404
286 #define _VLV_PCS01_DW1_CH1 0x2604
287 #define _VLV_PCS23_DW1_CH1 0x2804
288 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
289 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
291 #define _VLV_PCS_DW8_CH0 0x8220
292 #define _VLV_PCS_DW8_CH1 0x8420
293 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
294 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
295 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
297 #define _VLV_PCS01_DW8_CH0 0x0220
298 #define _VLV_PCS23_DW8_CH0 0x0420
299 #define _VLV_PCS01_DW8_CH1 0x2620
300 #define _VLV_PCS23_DW8_CH1 0x2820
301 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
302 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
304 #define _VLV_PCS_DW9_CH0 0x8224
305 #define _VLV_PCS_DW9_CH1 0x8424
306 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
307 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
308 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
309 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
310 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
311 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
312 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
314 #define _VLV_PCS01_DW9_CH0 0x224
315 #define _VLV_PCS23_DW9_CH0 0x424
316 #define _VLV_PCS01_DW9_CH1 0x2624
317 #define _VLV_PCS23_DW9_CH1 0x2824
318 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
319 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
321 #define _CHV_PCS_DW10_CH0 0x8228
322 #define _CHV_PCS_DW10_CH1 0x8428
323 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
324 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
325 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
326 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
327 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
328 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
329 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
330 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
331 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
333 #define _VLV_PCS01_DW10_CH0 0x0228
334 #define _VLV_PCS23_DW10_CH0 0x0428
335 #define _VLV_PCS01_DW10_CH1 0x2628
336 #define _VLV_PCS23_DW10_CH1 0x2828
337 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
338 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
340 #define _VLV_PCS_DW11_CH0 0x822c
341 #define _VLV_PCS_DW11_CH1 0x842c
342 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
343 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
344 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
345 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
346 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
348 #define _VLV_PCS01_DW11_CH0 0x022c
349 #define _VLV_PCS23_DW11_CH0 0x042c
350 #define _VLV_PCS01_DW11_CH1 0x262c
351 #define _VLV_PCS23_DW11_CH1 0x282c
352 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
353 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
355 #define _VLV_PCS01_DW12_CH0 0x0230
356 #define _VLV_PCS23_DW12_CH0 0x0430
357 #define _VLV_PCS01_DW12_CH1 0x2630
358 #define _VLV_PCS23_DW12_CH1 0x2830
359 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
360 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
362 #define _VLV_PCS_DW12_CH0 0x8230
363 #define _VLV_PCS_DW12_CH1 0x8430
364 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
365 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
366 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
367 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
368 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
369 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
371 #define _VLV_PCS_DW14_CH0 0x8238
372 #define _VLV_PCS_DW14_CH1 0x8438
373 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
375 #define _VLV_PCS_DW23_CH0 0x825c
376 #define _VLV_PCS_DW23_CH1 0x845c
377 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
379 #define _VLV_TX_DW2_CH0 0x8288
380 #define _VLV_TX_DW2_CH1 0x8488
381 #define DPIO_SWING_MARGIN000_SHIFT 16
382 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
383 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
384 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
386 #define _VLV_TX_DW3_CH0 0x828c
387 #define _VLV_TX_DW3_CH1 0x848c
388 /* The following bit for CHV phy */
389 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
390 #define DPIO_SWING_MARGIN101_SHIFT 16
391 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
392 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
394 #define _VLV_TX_DW4_CH0 0x8290
395 #define _VLV_TX_DW4_CH1 0x8490
396 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
397 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
398 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
399 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
400 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
402 #define _VLV_TX3_DW4_CH0 0x690
403 #define _VLV_TX3_DW4_CH1 0x2a90
404 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
406 #define _VLV_TX_DW5_CH0 0x8294
407 #define _VLV_TX_DW5_CH1 0x8494
408 #define DPIO_TX_OCALINIT_EN (1 << 31)
409 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
411 #define _VLV_TX_DW11_CH0 0x82ac
412 #define _VLV_TX_DW11_CH1 0x84ac
413 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
415 #define _VLV_TX_DW14_CH0 0x82b8
416 #define _VLV_TX_DW14_CH1 0x84b8
417 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
419 /* CHV dpPhy registers */
420 #define _CHV_PLL_DW0_CH0 0x8000
421 #define _CHV_PLL_DW0_CH1 0x8180
422 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
424 #define _CHV_PLL_DW1_CH0 0x8004
425 #define _CHV_PLL_DW1_CH1 0x8184
426 #define DPIO_CHV_N_DIV_SHIFT 8
427 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
428 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
430 #define _CHV_PLL_DW2_CH0 0x8008
431 #define _CHV_PLL_DW2_CH1 0x8188
432 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
434 #define _CHV_PLL_DW3_CH0 0x800c
435 #define _CHV_PLL_DW3_CH1 0x818c
436 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
437 #define DPIO_CHV_FIRST_MOD (0 << 8)
438 #define DPIO_CHV_SECOND_MOD (1 << 8)
439 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
440 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
441 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
443 #define _CHV_PLL_DW6_CH0 0x8018
444 #define _CHV_PLL_DW6_CH1 0x8198
445 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
446 #define DPIO_CHV_INT_COEFF_SHIFT 8
447 #define DPIO_CHV_PROP_COEFF_SHIFT 0
448 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
450 #define _CHV_PLL_DW8_CH0 0x8020
451 #define _CHV_PLL_DW8_CH1 0x81A0
452 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
453 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
454 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
456 #define _CHV_PLL_DW9_CH0 0x8024
457 #define _CHV_PLL_DW9_CH1 0x81A4
458 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
459 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
460 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
461 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
463 #define _CHV_CMN_DW0_CH0 0x8100
464 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
465 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
466 #define DPIO_ALLDL_POWERDOWN (1 << 1)
467 #define DPIO_ANYDL_POWERDOWN (1 << 0)
469 #define _CHV_CMN_DW5_CH0 0x8114
470 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
471 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
472 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
473 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
474 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
475 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
476 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
477 #define CHV_BUFLEFTENA1_MASK (3 << 22)
479 #define _CHV_CMN_DW13_CH0 0x8134
480 #define _CHV_CMN_DW0_CH1 0x8080
481 #define DPIO_CHV_S1_DIV_SHIFT 21
482 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
483 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
484 #define DPIO_CHV_K_DIV_SHIFT 4
485 #define DPIO_PLL_FREQLOCK (1 << 1)
486 #define DPIO_PLL_LOCK (1 << 0)
487 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
489 #define _CHV_CMN_DW14_CH0 0x8138
490 #define _CHV_CMN_DW1_CH1 0x8084
491 #define DPIO_AFC_RECAL (1 << 14)
492 #define DPIO_DCLKP_EN (1 << 13)
493 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
494 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
495 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
496 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
497 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
498 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
499 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
500 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
501 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
503 #define _CHV_CMN_DW19_CH0 0x814c
504 #define _CHV_CMN_DW6_CH1 0x8098
505 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
506 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
507 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
508 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
510 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
512 #define CHV_CMN_DW28 0x8170
513 #define DPIO_CL1POWERDOWNEN (1 << 23)
514 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
515 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
516 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
517 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
518 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
520 #define CHV_CMN_DW30 0x8178
521 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
522 #define DPIO_LRC_BYPASS (1 << 3)
524 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
525 (lane) * 0x200 + (offset))
527 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
528 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
529 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
530 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
531 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
532 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
533 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
534 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
535 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
536 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
537 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
538 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
539 #define DPIO_FRC_LATENCY_SHFIT 8
540 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
541 #define DPIO_UPAR_SHIFT 30
543 /* BXT PHY registers */
544 #define _BXT_PHY0_BASE 0x6C000
545 #define _BXT_PHY1_BASE 0x162000
546 #define _BXT_PHY2_BASE 0x163000
547 #define BXT_PHY_BASE(phy) \
548 _PICK_EVEN_2RANGES(phy, 1, \
549 _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
550 _BXT_PHY1_BASE, _BXT_PHY2_BASE)
552 #define _BXT_PHY(phy, reg) \
553 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
555 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
556 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
557 (reg_ch1) - _BXT_PHY0_BASE))
558 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
559 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
561 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
562 #define MIPIO_RST_CTRL (1 << 2)
564 #define _BXT_PHY_CTL_DDI_A 0x64C00
565 #define _BXT_PHY_CTL_DDI_B 0x64C10
566 #define _BXT_PHY_CTL_DDI_C 0x64C20
567 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
568 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
569 #define BXT_PHY_LANE_ENABLED (1 << 8)
570 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
573 #define _PHY_CTL_FAMILY_DDI 0x64C90
574 #define _PHY_CTL_FAMILY_EDP 0x64C80
575 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
576 #define COMMON_RESET_DIS (1 << 31)
577 #define BXT_PHY_CTL_FAMILY(phy) \
578 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
579 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
580 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
582 /* BXT PHY PLL registers */
583 #define _PORT_PLL_A 0x46074
584 #define _PORT_PLL_B 0x46078
585 #define _PORT_PLL_C 0x4607c
586 #define PORT_PLL_ENABLE REG_BIT(31)
587 #define PORT_PLL_LOCK REG_BIT(30)
588 #define PORT_PLL_REF_SEL REG_BIT(27)
589 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
590 #define PORT_PLL_POWER_STATE REG_BIT(25)
591 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
593 #define _PORT_PLL_EBB_0_A 0x162034
594 #define _PORT_PLL_EBB_0_B 0x6C034
595 #define _PORT_PLL_EBB_0_C 0x6C340
596 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
597 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
598 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
599 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
600 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
604 #define _PORT_PLL_EBB_4_A 0x162038
605 #define _PORT_PLL_EBB_4_B 0x6C038
606 #define _PORT_PLL_EBB_4_C 0x6C344
607 #define PORT_PLL_RECALIBRATE REG_BIT(14)
608 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
609 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
613 #define _PORT_PLL_0_A 0x162100
614 #define _PORT_PLL_0_B 0x6C100
615 #define _PORT_PLL_0_C 0x6C380
617 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
618 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
620 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
621 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
623 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
624 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
626 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
628 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
629 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
630 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
631 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
632 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
633 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
635 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
636 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
638 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
639 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
641 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
642 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
643 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
644 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
647 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
650 /* BXT PHY common lane registers */
651 #define _PORT_CL1CM_DW0_A 0x162000
652 #define _PORT_CL1CM_DW0_BC 0x6C000
653 #define PHY_POWER_GOOD (1 << 16)
654 #define PHY_RESERVED (1 << 7)
655 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
657 #define _PORT_CL1CM_DW9_A 0x162024
658 #define _PORT_CL1CM_DW9_BC 0x6C024
659 #define IREF0RC_OFFSET_SHIFT 8
660 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
661 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
663 #define _PORT_CL1CM_DW10_A 0x162028
664 #define _PORT_CL1CM_DW10_BC 0x6C028
665 #define IREF1RC_OFFSET_SHIFT 8
666 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
667 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
669 #define _PORT_CL1CM_DW28_A 0x162070
670 #define _PORT_CL1CM_DW28_BC 0x6C070
671 #define OCL1_POWER_DOWN_EN (1 << 23)
672 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
673 #define SUS_CLK_CONFIG 0x3
674 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
676 #define _PORT_CL1CM_DW30_A 0x162078
677 #define _PORT_CL1CM_DW30_BC 0x6C078
678 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
679 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
681 /* The spec defines this only for BXT PHY0, but lets assume that this
682 * would exist for PHY1 too if it had a second channel.
684 #define _PORT_CL2CM_DW6_A 0x162358
685 #define _PORT_CL2CM_DW6_BC 0x6C358
686 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
687 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
689 /* BXT PHY Ref registers */
690 #define _PORT_REF_DW3_A 0x16218C
691 #define _PORT_REF_DW3_BC 0x6C18C
692 #define GRC_DONE (1 << 22)
693 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
695 #define _PORT_REF_DW6_A 0x162198
696 #define _PORT_REF_DW6_BC 0x6C198
697 #define GRC_CODE_SHIFT 24
698 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
699 #define GRC_CODE_FAST_SHIFT 16
700 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
701 #define GRC_CODE_SLOW_SHIFT 8
702 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
703 #define GRC_CODE_NOM_MASK 0xFF
704 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
706 #define _PORT_REF_DW8_A 0x1621A0
707 #define _PORT_REF_DW8_BC 0x6C1A0
708 #define GRC_DIS (1 << 15)
709 #define GRC_RDY_OVRD (1 << 1)
710 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
712 /* BXT PHY PCS registers */
713 #define _PORT_PCS_DW10_LN01_A 0x162428
714 #define _PORT_PCS_DW10_LN01_B 0x6C428
715 #define _PORT_PCS_DW10_LN01_C 0x6C828
716 #define _PORT_PCS_DW10_GRP_A 0x162C28
717 #define _PORT_PCS_DW10_GRP_B 0x6CC28
718 #define _PORT_PCS_DW10_GRP_C 0x6CE28
719 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
720 _PORT_PCS_DW10_LN01_B, \
721 _PORT_PCS_DW10_LN01_C)
722 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
723 _PORT_PCS_DW10_GRP_B, \
724 _PORT_PCS_DW10_GRP_C)
726 #define TX2_SWING_CALC_INIT (1 << 31)
727 #define TX1_SWING_CALC_INIT (1 << 30)
729 #define _PORT_PCS_DW12_LN01_A 0x162430
730 #define _PORT_PCS_DW12_LN01_B 0x6C430
731 #define _PORT_PCS_DW12_LN01_C 0x6C830
732 #define _PORT_PCS_DW12_LN23_A 0x162630
733 #define _PORT_PCS_DW12_LN23_B 0x6C630
734 #define _PORT_PCS_DW12_LN23_C 0x6CA30
735 #define _PORT_PCS_DW12_GRP_A 0x162c30
736 #define _PORT_PCS_DW12_GRP_B 0x6CC30
737 #define _PORT_PCS_DW12_GRP_C 0x6CE30
738 #define LANESTAGGER_STRAP_OVRD (1 << 6)
739 #define LANE_STAGGER_MASK 0x1F
740 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
741 _PORT_PCS_DW12_LN01_B, \
742 _PORT_PCS_DW12_LN01_C)
743 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
744 _PORT_PCS_DW12_LN23_B, \
745 _PORT_PCS_DW12_LN23_C)
746 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
747 _PORT_PCS_DW12_GRP_B, \
748 _PORT_PCS_DW12_GRP_C)
750 /* BXT PHY TX registers */
751 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
754 #define _PORT_TX_DW2_LN0_A 0x162508
755 #define _PORT_TX_DW2_LN0_B 0x6C508
756 #define _PORT_TX_DW2_LN0_C 0x6C908
757 #define _PORT_TX_DW2_GRP_A 0x162D08
758 #define _PORT_TX_DW2_GRP_B 0x6CD08
759 #define _PORT_TX_DW2_GRP_C 0x6CF08
760 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
761 _PORT_TX_DW2_LN0_B, \
763 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
764 _PORT_TX_DW2_GRP_B, \
766 #define MARGIN_000_SHIFT 16
767 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
768 #define UNIQ_TRANS_SCALE_SHIFT 8
769 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
771 #define _PORT_TX_DW3_LN0_A 0x16250C
772 #define _PORT_TX_DW3_LN0_B 0x6C50C
773 #define _PORT_TX_DW3_LN0_C 0x6C90C
774 #define _PORT_TX_DW3_GRP_A 0x162D0C
775 #define _PORT_TX_DW3_GRP_B 0x6CD0C
776 #define _PORT_TX_DW3_GRP_C 0x6CF0C
777 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
778 _PORT_TX_DW3_LN0_B, \
780 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
781 _PORT_TX_DW3_GRP_B, \
783 #define SCALE_DCOMP_METHOD (1 << 26)
784 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
786 #define _PORT_TX_DW4_LN0_A 0x162510
787 #define _PORT_TX_DW4_LN0_B 0x6C510
788 #define _PORT_TX_DW4_LN0_C 0x6C910
789 #define _PORT_TX_DW4_GRP_A 0x162D10
790 #define _PORT_TX_DW4_GRP_B 0x6CD10
791 #define _PORT_TX_DW4_GRP_C 0x6CF10
792 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
793 _PORT_TX_DW4_LN0_B, \
795 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
796 _PORT_TX_DW4_GRP_B, \
798 #define DEEMPH_SHIFT 24
799 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
801 #define _PORT_TX_DW5_LN0_A 0x162514
802 #define _PORT_TX_DW5_LN0_B 0x6C514
803 #define _PORT_TX_DW5_LN0_C 0x6C914
804 #define _PORT_TX_DW5_GRP_A 0x162D14
805 #define _PORT_TX_DW5_GRP_B 0x6CD14
806 #define _PORT_TX_DW5_GRP_C 0x6CF14
807 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
808 _PORT_TX_DW5_LN0_B, \
810 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
811 _PORT_TX_DW5_GRP_B, \
813 #define DCC_DELAY_RANGE_1 (1 << 9)
814 #define DCC_DELAY_RANGE_2 (1 << 8)
816 #define _PORT_TX_DW14_LN0_A 0x162538
817 #define _PORT_TX_DW14_LN0_B 0x6C538
818 #define _PORT_TX_DW14_LN0_C 0x6C938
819 #define LATENCY_OPTIM_SHIFT 30
820 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
821 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
822 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
823 _PORT_TX_DW14_LN0_C) + \
824 _BXT_LANE_OFFSET(lane))
826 /* UAIMI scratch pad register 1 */
827 #define UAIMI_SPR1 _MMIO(0x4F074)
829 #define SKL_VCCIO_MASK 0x1
830 /* SKL balance leg register */
831 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
833 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
834 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
835 /* Balance leg disable bits */
836 #define BALANCE_LEG_DISABLE_SHIFT 23
837 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
841 * [0-7] @ 0x2000 gen2,gen3
842 * [8-15] @ 0x3000 945,g33,pnv
844 * [0-15] @ 0x3000 gen4,gen5
846 * [0-15] @ 0x100000 gen6,vlv,chv
847 * [0-31] @ 0x100000 gen7+
849 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
850 #define I830_FENCE_START_MASK 0x07f80000
851 #define I830_FENCE_TILING_Y_SHIFT 12
852 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
853 #define I830_FENCE_PITCH_SHIFT 4
854 #define I830_FENCE_REG_VALID (1 << 0)
855 #define I915_FENCE_MAX_PITCH_VAL 4
856 #define I830_FENCE_MAX_PITCH_VAL 6
857 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
859 #define I915_FENCE_START_MASK 0x0ff00000
860 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
862 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
863 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
864 #define I965_FENCE_PITCH_SHIFT 2
865 #define I965_FENCE_TILING_Y_SHIFT 1
866 #define I965_FENCE_REG_VALID (1 << 0)
867 #define I965_FENCE_MAX_PITCH_VAL 0x0400
869 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
870 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
871 #define GEN6_FENCE_PITCH_SHIFT 32
872 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
875 /* control register for cpu gtt access */
876 #define TILECTL _MMIO(0x101000)
877 #define TILECTL_SWZCTL (1 << 0)
878 #define TILECTL_TLBPF (1 << 1)
879 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
880 #define TILECTL_BACKSNOOP_DIS (1 << 3)
883 * Instruction and interrupt control regs
885 #define PGTBL_CTL _MMIO(0x02020)
886 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
887 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
888 #define PGTBL_ER _MMIO(0x02024)
889 #define PRB0_BASE (0x2030 - 0x30)
890 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
891 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
892 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
893 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
894 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
895 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
896 #define RENDER_RING_BASE 0x02000
897 #define BSD_RING_BASE 0x04000
898 #define GEN6_BSD_RING_BASE 0x12000
899 #define GEN8_BSD2_RING_BASE 0x1c000
900 #define GEN11_BSD_RING_BASE 0x1c0000
901 #define GEN11_BSD2_RING_BASE 0x1c4000
902 #define GEN11_BSD3_RING_BASE 0x1d0000
903 #define GEN11_BSD4_RING_BASE 0x1d4000
904 #define XEHP_BSD5_RING_BASE 0x1e0000
905 #define XEHP_BSD6_RING_BASE 0x1e4000
906 #define XEHP_BSD7_RING_BASE 0x1f0000
907 #define XEHP_BSD8_RING_BASE 0x1f4000
908 #define VEBOX_RING_BASE 0x1a000
909 #define GEN11_VEBOX_RING_BASE 0x1c8000
910 #define GEN11_VEBOX2_RING_BASE 0x1d8000
911 #define XEHP_VEBOX3_RING_BASE 0x1e8000
912 #define XEHP_VEBOX4_RING_BASE 0x1f8000
913 #define MTL_GSC_RING_BASE 0x11a000
914 #define GEN12_COMPUTE0_RING_BASE 0x1a000
915 #define GEN12_COMPUTE1_RING_BASE 0x1c000
916 #define GEN12_COMPUTE2_RING_BASE 0x1e000
917 #define GEN12_COMPUTE3_RING_BASE 0x26000
918 #define BLT_RING_BASE 0x22000
919 #define XEHPC_BCS1_RING_BASE 0x3e0000
920 #define XEHPC_BCS2_RING_BASE 0x3e2000
921 #define XEHPC_BCS3_RING_BASE 0x3e4000
922 #define XEHPC_BCS4_RING_BASE 0x3e6000
923 #define XEHPC_BCS5_RING_BASE 0x3e8000
924 #define XEHPC_BCS6_RING_BASE 0x3ea000
925 #define XEHPC_BCS7_RING_BASE 0x3ec000
926 #define XEHPC_BCS8_RING_BASE 0x3ee000
927 #define DG1_GSC_HECI1_BASE 0x00258000
928 #define DG1_GSC_HECI2_BASE 0x00259000
929 #define DG2_GSC_HECI1_BASE 0x00373000
930 #define DG2_GSC_HECI2_BASE 0x00374000
931 #define MTL_GSC_HECI1_BASE 0x00116000
932 #define MTL_GSC_HECI2_BASE 0x00117000
934 #define HECI_H_CSR(base) _MMIO((base) + 0x4)
935 #define HECI_H_CSR_IE REG_BIT(0)
936 #define HECI_H_CSR_IS REG_BIT(1)
937 #define HECI_H_CSR_IG REG_BIT(2)
938 #define HECI_H_CSR_RDY REG_BIT(3)
939 #define HECI_H_CSR_RST REG_BIT(4)
941 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
942 #define HECI_H_GS1_ER_PREP REG_BIT(0)
944 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
945 #define GTT_CACHE_EN_ALL 0xF0007FFF
946 #define GEN7_WR_WATERMARK _MMIO(0x4028)
947 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
948 #define ARB_MODE _MMIO(0x4030)
949 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
950 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
951 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
952 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
953 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
954 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
955 #define GEN7_LRA_LIMITS_REG_NUM 13
956 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
957 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
959 #define GEN7_ERR_INT _MMIO(0x44040)
960 #define ERR_INT_POISON (1 << 31)
961 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
962 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
963 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
964 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
965 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
966 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
967 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
968 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
969 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
971 #define FPGA_DBG _MMIO(0x42300)
972 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
974 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
975 #define CLAIM_ER_CLR REG_BIT(31)
976 #define CLAIM_ER_OVERFLOW REG_BIT(16)
977 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
979 #define DERRMR _MMIO(0x44050)
980 /* Note that HBLANK events are reserved on bdw+ */
981 #define DERRMR_PIPEA_SCANLINE (1 << 0)
982 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
983 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
984 #define DERRMR_PIPEA_VBLANK (1 << 3)
985 #define DERRMR_PIPEA_HBLANK (1 << 5)
986 #define DERRMR_PIPEB_SCANLINE (1 << 8)
987 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
988 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
989 #define DERRMR_PIPEB_VBLANK (1 << 11)
990 #define DERRMR_PIPEB_HBLANK (1 << 13)
991 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
992 #define DERRMR_PIPEC_SCANLINE (1 << 14)
993 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
994 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
995 #define DERRMR_PIPEC_VBLANK (1 << 21)
996 #define DERRMR_PIPEC_HBLANK (1 << 22)
998 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
999 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1000 #define SCPD0 _MMIO(0x209c) /* 915+ only */
1001 #define SCPD_FBC_IGNORE_3D (1 << 6)
1002 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
1003 #define GEN2_IER _MMIO(0x20a0)
1004 #define GEN2_IIR _MMIO(0x20a4)
1005 #define GEN2_IMR _MMIO(0x20a8)
1006 #define GEN2_ISR _MMIO(0x20ac)
1007 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1008 #define GINT_DIS (1 << 22)
1009 #define GCFG_DIS (1 << 8)
1010 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1011 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1012 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1013 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1014 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1015 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1016 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1017 #define VLV_PCBR_ADDR_SHIFT 12
1019 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1020 #define EIR _MMIO(0x20b0)
1021 #define EMR _MMIO(0x20b4)
1022 #define ESR _MMIO(0x20b8)
1023 #define GM45_ERROR_PAGE_TABLE (1 << 5)
1024 #define GM45_ERROR_MEM_PRIV (1 << 4)
1025 #define I915_ERROR_PAGE_TABLE (1 << 4)
1026 #define GM45_ERROR_CP_PRIV (1 << 3)
1027 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
1028 #define I915_ERROR_INSTRUCTION (1 << 0)
1029 #define INSTPM _MMIO(0x20c0)
1030 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
1031 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
1032 will not assert AGPBUSY# and will only
1033 be delivered when out of C3. */
1034 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
1035 #define INSTPM_TLB_INVALIDATE (1 << 9)
1036 #define INSTPM_SYNC_FLUSH (1 << 5)
1037 #define MEM_MODE _MMIO(0x20cc)
1038 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
1039 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
1040 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
1041 #define FW_BLC _MMIO(0x20d8)
1042 #define FW_BLC2 _MMIO(0x20dc)
1043 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1044 #define FW_BLC_SELF_EN_MASK (1 << 31)
1045 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
1046 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
1047 #define MM_BURST_LENGTH 0x00700000
1048 #define MM_FIFO_WATERMARK 0x0001F000
1049 #define LM_BURST_LENGTH 0x00000700
1050 #define LM_FIFO_WATERMARK 0x0000001F
1051 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1053 #define _MBUS_ABOX0_CTL 0x45038
1054 #define _MBUS_ABOX1_CTL 0x45048
1055 #define _MBUS_ABOX2_CTL 0x4504C
1056 #define MBUS_ABOX_CTL(x) \
1057 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
1058 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
1059 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
1061 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
1062 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
1063 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
1064 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
1065 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
1066 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
1067 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
1068 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
1070 /* Make render/texture TLB fetches lower priorty than associated data
1071 * fetches. This is not turned on by default
1073 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1075 /* Isoch request wait on GTT enable (Display A/B/C streams).
1076 * Make isoch requests stall on the TLB update. May cause
1077 * display underruns (test mode only)
1079 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1081 /* Block grant count for isoch requests when block count is
1082 * set to a finite value.
1084 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1085 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1086 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1087 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1088 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1090 /* Enable render writes to complete in C2/C3/C4 power states.
1091 * If this isn't enabled, render writes are prevented in low
1092 * power states. That seems bad to me.
1094 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1096 /* This acknowledges an async flip immediately instead
1097 * of waiting for 2TLB fetches.
1099 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1101 /* Enables non-sequential data reads through arbiter
1103 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1105 /* Disable FSB snooping of cacheable write cycles from binner/render
1108 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1110 /* Arbiter time slice for non-isoch streams */
1111 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
1112 #define MI_ARB_TIME_SLICE_1 (0 << 5)
1113 #define MI_ARB_TIME_SLICE_2 (1 << 5)
1114 #define MI_ARB_TIME_SLICE_4 (2 << 5)
1115 #define MI_ARB_TIME_SLICE_6 (3 << 5)
1116 #define MI_ARB_TIME_SLICE_8 (4 << 5)
1117 #define MI_ARB_TIME_SLICE_10 (5 << 5)
1118 #define MI_ARB_TIME_SLICE_14 (6 << 5)
1119 #define MI_ARB_TIME_SLICE_16 (7 << 5)
1121 /* Low priority grace period page size */
1122 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1123 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1125 /* Disable display A/B trickle feed */
1126 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1128 /* Set display plane priority */
1129 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1130 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1132 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
1133 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1134 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1136 /* On modern GEN architectures interrupt control consists of two sets
1137 * of registers. The first set pertains to the ring generating the
1138 * interrupt. The second control is for the functional block generating the
1139 * interrupt. These are PM, GT, DE, etc.
1141 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1142 * GT interrupt bits, so we don't need to duplicate the defines.
1144 * These defines should cover us well from SNB->HSW with minor exceptions
1145 * it can also work on ILK.
1147 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1148 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1149 #define GT_BLT_USER_INTERRUPT (1 << 22)
1150 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1151 #define GT_BSD_USER_INTERRUPT (1 << 12)
1152 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1153 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1154 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1155 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1156 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1157 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1158 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1159 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1160 #define GT_RENDER_USER_INTERRUPT (1 << 0)
1162 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1163 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1165 #define GT_PARITY_ERROR(dev_priv) \
1166 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1167 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1169 /* These are all the "old" interrupts */
1170 #define ILK_BSD_USER_INTERRUPT (1 << 5)
1172 #define I915_PM_INTERRUPT (1 << 31)
1173 #define I915_ISP_INTERRUPT (1 << 22)
1174 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
1175 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
1176 #define I915_MIPIC_INTERRUPT (1 << 19)
1177 #define I915_MIPIA_INTERRUPT (1 << 18)
1178 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
1179 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
1180 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
1181 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
1182 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
1183 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1184 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
1185 #define I915_HWB_OOM_INTERRUPT (1 << 13)
1186 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
1187 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
1188 #define I915_MISC_INTERRUPT (1 << 11)
1189 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
1190 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
1191 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
1192 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
1193 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
1194 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
1195 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
1196 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
1197 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
1198 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
1199 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
1200 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
1201 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
1202 #define I915_DEBUG_INTERRUPT (1 << 2)
1203 #define I915_WINVALID_INTERRUPT (1 << 1)
1204 #define I915_USER_INTERRUPT (1 << 1)
1205 #define I915_ASLE_INTERRUPT (1 << 0)
1206 #define I915_BSD_USER_INTERRUPT (1 << 25)
1208 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
1209 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
1211 /* DisplayPort Audio w/ LPE */
1212 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
1213 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
1215 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
1216 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
1217 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
1218 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1219 _VLV_AUD_PORT_EN_B_DBG, \
1220 _VLV_AUD_PORT_EN_C_DBG, \
1221 _VLV_AUD_PORT_EN_D_DBG)
1222 #define VLV_AMP_MUTE (1 << 1)
1224 #define GEN6_BSD_RNCID _MMIO(0x12198)
1226 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
1227 #define GEN7_FF_SCHED_MASK 0x0077070
1228 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1229 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
1230 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
1231 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
1232 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
1233 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
1234 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1235 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
1236 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
1237 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
1238 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
1239 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
1240 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
1241 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
1242 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
1245 * Framebuffer compression (915+ only)
1248 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
1249 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
1250 #define FBC_CONTROL _MMIO(0x3208)
1251 #define FBC_CTL_EN REG_BIT(31)
1252 #define FBC_CTL_PERIODIC REG_BIT(30)
1253 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
1254 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
1255 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1256 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1257 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1258 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
1259 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
1260 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1261 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
1262 #define FBC_COMMAND _MMIO(0x320c)
1263 #define FBC_CMD_COMPRESS REG_BIT(0)
1264 #define FBC_STATUS _MMIO(0x3210)
1265 #define FBC_STAT_COMPRESSING REG_BIT(31)
1266 #define FBC_STAT_COMPRESSED REG_BIT(30)
1267 #define FBC_STAT_MODIFIED REG_BIT(29)
1268 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
1269 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
1270 #define FBC_CTL_FENCE_DBL REG_BIT(4)
1271 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
1272 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1273 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
1274 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
1275 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
1276 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1277 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
1278 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
1279 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
1280 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
1281 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
1282 #define FBC_MOD_NUM_VALID REG_BIT(0)
1283 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
1284 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
1285 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
1286 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
1287 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
1288 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
1290 #define FBC_LL_SIZE (1536)
1292 /* Framebuffer compression for GM45+ */
1293 #define DPFC_CB_BASE _MMIO(0x3200)
1294 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1295 #define DPFC_CONTROL _MMIO(0x3208)
1296 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1297 #define DPFC_CTL_EN REG_BIT(31)
1298 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1299 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
1300 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1301 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
1302 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
1303 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1304 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1305 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1306 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1307 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1308 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
1309 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1310 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
1311 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
1312 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1313 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
1314 #define DPFC_RECOMP_CTL _MMIO(0x320c)
1315 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1316 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
1317 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
1318 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
1319 #define DPFC_STATUS _MMIO(0x3210)
1320 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1321 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
1322 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
1323 #define DPFC_STATUS2 _MMIO(0x3214)
1324 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1325 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
1326 #define DPFC_FENCE_YOFF _MMIO(0x3218)
1327 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1328 #define DPFC_CHICKEN _MMIO(0x3224)
1329 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1330 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1331 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1332 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1333 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1334 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1336 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1337 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
1338 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
1339 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
1341 #define ILK_FBC_RT_BASE _MMIO(0x2128)
1342 #define ILK_FBC_RT_VALID REG_BIT(0)
1343 #define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1345 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
1346 #define ILK_FBCQ_DIS REG_BIT(22)
1347 #define ILK_PABSTRETCH_DIS REG_BIT(21)
1348 #define ILK_SABSTRETCH_DIS REG_BIT(20)
1349 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
1350 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1351 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
1352 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
1353 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
1354 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
1355 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1356 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
1357 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
1358 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
1362 * Framebuffer compression for Sandybridge
1364 * The following two registers are of type GTTMMADR
1366 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
1367 #define SNB_DPFC_FENCE_EN REG_BIT(29)
1368 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
1369 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
1370 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
1372 /* Framebuffer compression for Ivybridge */
1373 #define IVB_FBC_RT_BASE _MMIO(0x7020)
1374 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
1376 #define IPS_CTL _MMIO(0x43408)
1377 #define IPS_ENABLE REG_BIT(31)
1378 #define IPS_FALSE_COLOR REG_BIT(4)
1380 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1381 #define FBC_REND_NUKE REG_BIT(2)
1382 #define FBC_REND_CACHE_CLEAN REG_BIT(1)
1385 * Clock control & power management
1387 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1388 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1389 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1390 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1392 #define VGA0 _MMIO(0x6000)
1393 #define VGA1 _MMIO(0x6004)
1394 #define VGA_PD _MMIO(0x6010)
1395 #define VGA0_PD_P2_DIV_4 (1 << 7)
1396 #define VGA0_PD_P1_DIV_2 (1 << 5)
1397 #define VGA0_PD_P1_SHIFT 0
1398 #define VGA0_PD_P1_MASK (0x1f << 0)
1399 #define VGA1_PD_P2_DIV_4 (1 << 15)
1400 #define VGA1_PD_P1_DIV_2 (1 << 13)
1401 #define VGA1_PD_P1_SHIFT 8
1402 #define VGA1_PD_P1_MASK (0x1f << 8)
1403 #define DPLL_VCO_ENABLE (1 << 31)
1404 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1405 #define DPLL_DVO_2X_MODE (1 << 30)
1406 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1407 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1408 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
1409 #define DPLL_VGA_MODE_DIS (1 << 28)
1410 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1411 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1412 #define DPLL_MODE_MASK (3 << 26)
1413 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1414 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1415 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1416 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1417 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1418 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1419 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1420 #define DPLL_LOCK_VLV (1 << 15)
1421 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
1422 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
1423 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
1424 #define DPLL_PORTC_READY_MASK (0xf << 4)
1425 #define DPLL_PORTB_READY_MASK (0xf)
1427 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1429 /* Additional CHV pll/phy registers */
1430 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
1431 #define DPLL_PORTD_READY_MASK (0xf)
1432 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1433 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
1434 #define PHY_LDO_DELAY_0NS 0x0
1435 #define PHY_LDO_DELAY_200NS 0x1
1436 #define PHY_LDO_DELAY_600NS 0x2
1437 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
1438 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
1439 #define PHY_CH_SU_PSR 0x1
1440 #define PHY_CH_DEEP_PSR 0x7
1441 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
1442 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1443 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1444 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
1445 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1446 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
1449 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1450 * this field (only one bit may be set).
1452 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1453 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1454 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1455 /* i830, required in DVO non-gang */
1456 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1457 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1458 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1459 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1460 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1461 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1462 #define PLL_REF_INPUT_MASK (3 << 13)
1463 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1465 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1466 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1467 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1468 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1469 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1472 * Parallel to Serial Load Pulse phase selection.
1473 * Selects the phase for the 10X DPLL clock for the PCIe
1474 * digital display port. The range is 4 to 13; 10 or more
1475 * is just a flip delay. The default is 6
1477 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1478 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1480 * SDVO multiplier for 945G/GM. Not used on 965.
1482 #define SDVO_MULTIPLIER_MASK 0x000000ff
1483 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1484 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1486 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1487 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1488 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1489 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1492 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1494 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1496 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1497 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1498 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1499 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1500 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1502 * SDVO/UDI pixel multiplier.
1504 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1505 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1506 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1507 * dummy bytes in the datastream at an increased clock rate, with both sides of
1508 * the link knowing how many bytes are fill.
1510 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1511 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1512 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1513 * through an SDVO command.
1515 * This register field has values of multiplication factor minus 1, with
1516 * a maximum multiplier of 5 for SDVO.
1518 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1519 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1521 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1522 * This best be set to the default value (3) or the CRT won't work. No,
1523 * I don't entirely understand what this does...
1525 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1526 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1528 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
1530 #define _FPA0 0x6040
1531 #define _FPA1 0x6044
1532 #define _FPB0 0x6048
1533 #define _FPB1 0x604c
1534 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
1535 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
1536 #define FP_N_DIV_MASK 0x003f0000
1537 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1538 #define FP_N_DIV_SHIFT 16
1539 #define FP_M1_DIV_MASK 0x00003f00
1540 #define FP_M1_DIV_SHIFT 8
1541 #define FP_M2_DIV_MASK 0x0000003f
1542 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1543 #define FP_M2_DIV_SHIFT 0
1544 #define DPLL_TEST _MMIO(0x606c)
1545 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1546 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1547 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1548 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1549 #define DPLLB_TEST_N_BYPASS (1 << 19)
1550 #define DPLLB_TEST_M_BYPASS (1 << 18)
1551 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1552 #define DPLLA_TEST_N_BYPASS (1 << 3)
1553 #define DPLLA_TEST_M_BYPASS (1 << 2)
1554 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1555 #define D_STATE _MMIO(0x6104)
1556 #define DSTATE_GFX_RESET_I830 (1 << 6)
1557 #define DSTATE_PLL_D3_OFF (1 << 3)
1558 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
1559 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
1560 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1561 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1562 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1563 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1564 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1565 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1566 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1567 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1568 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
1569 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1570 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1571 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1572 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1573 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1574 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1575 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1576 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1577 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1578 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1579 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1580 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1581 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1582 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1583 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1584 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1585 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1586 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1587 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1588 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1589 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1591 * This bit must be set on the 830 to prevent hangs when turning off the
1594 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1595 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1596 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1597 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1598 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1600 #define RENCLK_GATE_D1 _MMIO(0x6204)
1601 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1602 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1603 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1604 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1605 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1606 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1607 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1608 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1609 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1610 /* This bit must be unset on 855,865 */
1611 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1612 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1613 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1614 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1615 /* This bit must be set on 855,865. */
1616 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1617 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1618 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1619 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1620 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1621 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1622 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1623 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1624 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1625 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1626 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1627 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1628 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1629 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1630 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1631 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1632 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1633 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1635 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1636 /* This bit must always be set on 965G/965GM */
1637 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1638 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1639 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1640 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1641 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1642 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1643 /* This bit must always be set on 965G */
1644 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1645 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1646 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1647 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1648 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1649 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1650 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1651 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1652 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1653 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1654 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1655 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1656 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1657 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1658 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1659 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1660 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1661 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1662 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1664 #define RENCLK_GATE_D2 _MMIO(0x6208)
1665 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1666 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1667 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1669 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
1670 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1672 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
1673 #define DEUC _MMIO(0x6214) /* CRL only */
1675 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1676 #define FW_CSPWRDWNEN (1 << 15)
1678 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1680 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1681 #define CDCLK_FREQ_SHIFT 4
1682 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1683 #define CZCLK_FREQ_MASK 0xf
1685 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1686 #define PFI_CREDIT_63 (9 << 28) /* chv only */
1687 #define PFI_CREDIT_31 (8 << 28) /* chv only */
1688 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1689 #define PFI_CREDIT_RESEND (1 << 27)
1690 #define VGA_FAST_MODE_DISABLE (1 << 14)
1692 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
1697 #define _PALETTE_A 0xa000
1698 #define _PALETTE_B 0xa800
1699 #define _CHV_PALETTE_C 0xc000
1700 /* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
1701 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
1702 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
1703 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
1704 /* pre-i965 10bit interpolated mode ldw */
1705 #define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
1706 #define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
1707 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
1708 /* pre-i965 10bit interpolated mode udw */
1709 #define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
1710 #define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
1711 #define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
1712 #define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
1713 #define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
1714 #define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
1715 #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
1716 #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
1717 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
1718 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
1719 _PICK_EVEN_2RANGES(pipe, 2, \
1720 _PALETTE_A, _PALETTE_B, \
1721 _CHV_PALETTE_C, _CHV_PALETTE_C) + \
1724 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
1726 #define BXT_RP_STATE_CAP _MMIO(0x138170)
1727 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
1728 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
1729 #define PVC_RP_STATE_CAP _MMIO(0x281014)
1731 #define MTL_RP_STATE_CAP _MMIO(0x138000)
1732 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
1733 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
1734 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
1736 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
1737 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
1738 #define MTL_RPE_MASK REG_GENMASK(8, 0)
1740 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1741 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1742 #define PROCHOT_MASK REG_BIT(0)
1743 #define THERMAL_LIMIT_MASK REG_BIT(1)
1744 #define RATL_MASK REG_BIT(5)
1745 #define VR_THERMALERT_MASK REG_BIT(6)
1746 #define VR_TDC_MASK REG_BIT(7)
1747 #define POWER_LIMIT_4_MASK REG_BIT(8)
1748 #define POWER_LIMIT_1_MASK REG_BIT(10)
1749 #define POWER_LIMIT_2_MASK REG_BIT(11)
1750 #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1751 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1753 #define CHV_CLK_CTL1 _MMIO(0x101100)
1754 #define VLV_CLK_CTL2 _MMIO(0x101104)
1755 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1761 #define OVADD _MMIO(0x30000)
1762 #define DOVSTA _MMIO(0x30008)
1763 #define OC_BUF (0x3 << 20)
1764 #define OGAMC5 _MMIO(0x30010)
1765 #define OGAMC4 _MMIO(0x30014)
1766 #define OGAMC3 _MMIO(0x30018)
1767 #define OGAMC2 _MMIO(0x3001c)
1768 #define OGAMC1 _MMIO(0x30020)
1769 #define OGAMC0 _MMIO(0x30024)
1772 * GEN9 clock gating regs
1774 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1775 #define DARBF_GATING_DIS REG_BIT(27)
1776 #define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
1777 #define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
1778 #define PWM2_GATING_DIS REG_BIT(14)
1779 #define PWM1_GATING_DIS REG_BIT(13)
1781 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1782 #define TGL_VRH_GATING_DIS REG_BIT(31)
1783 #define DPT_GATING_DIS REG_BIT(22)
1785 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1786 #define BXT_GMBUS_GATING_DIS (1 << 14)
1788 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1789 #define DPCE_GATING_DIS REG_BIT(17)
1791 #define _CLKGATE_DIS_PSL_A 0x46520
1792 #define _CLKGATE_DIS_PSL_B 0x46524
1793 #define _CLKGATE_DIS_PSL_C 0x46528
1794 #define DUPS1_GATING_DIS (1 << 15)
1795 #define DUPS2_GATING_DIS (1 << 19)
1796 #define DUPS3_GATING_DIS (1 << 23)
1797 #define CURSOR_GATING_DIS REG_BIT(28)
1798 #define DPF_GATING_DIS (1 << 10)
1799 #define DPF_RAM_GATING_DIS (1 << 9)
1800 #define DPFR_GATING_DIS (1 << 8)
1802 #define CLKGATE_DIS_PSL(pipe) \
1803 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1805 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1806 #define _CLKGATE_DIS_PSL_EXT_B 0x46550
1807 #define PIPEDMC_GATING_DIS REG_BIT(12)
1809 #define CLKGATE_DIS_PSL_EXT(pipe) \
1810 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1812 /* DDI Buffer Control */
1813 #define _DDI_CLK_VALFREQ_A 0x64030
1814 #define _DDI_CLK_VALFREQ_B 0x64130
1815 #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
1818 * Display engine regs
1821 /* Pipe A CRC regs */
1822 #define _PIPE_CRC_CTL_A 0x60050
1823 #define PIPE_CRC_ENABLE REG_BIT(31)
1824 /* skl+ source selection */
1825 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
1826 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1827 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
1828 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
1829 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
1830 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
1831 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
1832 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
1833 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
1834 /* ivb+ source selection */
1835 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
1836 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1837 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
1838 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
1839 /* ilk+ source selection */
1840 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
1841 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1842 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
1843 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
1844 /* embedded DP port on the north display block */
1845 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
1846 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
1847 /* vlv source selection */
1848 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
1849 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1850 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
1851 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
1852 /* with DP port the pipe source is invalid */
1853 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
1854 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
1855 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
1856 /* gen3+ source selection */
1857 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
1858 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1859 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
1860 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
1861 /* with DP/TV port the pipe source is invalid */
1862 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
1863 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
1864 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
1865 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
1866 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
1867 /* gen2 doesn't have source selection bits */
1868 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
1870 #define _PIPE_CRC_RES_1_A_IVB 0x60064
1871 #define _PIPE_CRC_RES_2_A_IVB 0x60068
1872 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
1873 #define _PIPE_CRC_RES_4_A_IVB 0x60070
1874 #define _PIPE_CRC_RES_5_A_IVB 0x60074
1876 #define _PIPE_CRC_RES_RED_A 0x60060
1877 #define _PIPE_CRC_RES_GREEN_A 0x60064
1878 #define _PIPE_CRC_RES_BLUE_A 0x60068
1879 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1880 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1882 /* Pipe B CRC regs */
1883 #define _PIPE_CRC_RES_1_B_IVB 0x61064
1884 #define _PIPE_CRC_RES_2_B_IVB 0x61068
1885 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
1886 #define _PIPE_CRC_RES_4_B_IVB 0x61070
1887 #define _PIPE_CRC_RES_5_B_IVB 0x61074
1889 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
1890 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
1891 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
1892 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
1893 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
1894 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
1896 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
1897 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
1898 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
1899 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1900 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1902 /* Pipe/transcoder A timing regs */
1903 #define _TRANS_HTOTAL_A 0x60000
1904 #define HTOTAL_MASK REG_GENMASK(31, 16)
1905 #define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
1906 #define HACTIVE_MASK REG_GENMASK(15, 0)
1907 #define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
1908 #define _TRANS_HBLANK_A 0x60004
1909 #define HBLANK_END_MASK REG_GENMASK(31, 16)
1910 #define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
1911 #define HBLANK_START_MASK REG_GENMASK(15, 0)
1912 #define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
1913 #define _TRANS_HSYNC_A 0x60008
1914 #define HSYNC_END_MASK REG_GENMASK(31, 16)
1915 #define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
1916 #define HSYNC_START_MASK REG_GENMASK(15, 0)
1917 #define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
1918 #define _TRANS_VTOTAL_A 0x6000c
1919 #define VTOTAL_MASK REG_GENMASK(31, 16)
1920 #define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
1921 #define VACTIVE_MASK REG_GENMASK(15, 0)
1922 #define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
1923 #define _TRANS_VBLANK_A 0x60010
1924 #define VBLANK_END_MASK REG_GENMASK(31, 16)
1925 #define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
1926 #define VBLANK_START_MASK REG_GENMASK(15, 0)
1927 #define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
1928 #define _TRANS_VSYNC_A 0x60014
1929 #define VSYNC_END_MASK REG_GENMASK(31, 16)
1930 #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
1931 #define VSYNC_START_MASK REG_GENMASK(15, 0)
1932 #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
1933 #define _TRANS_EXITLINE_A 0x60018
1934 #define _PIPEASRC 0x6001c
1935 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1936 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1937 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1938 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1939 #define _BCLRPAT_A 0x60020
1940 #define _TRANS_VSYNCSHIFT_A 0x60028
1941 #define _TRANS_MULT_A 0x6002c
1943 /* Pipe/transcoder B timing regs */
1944 #define _TRANS_HTOTAL_B 0x61000
1945 #define _TRANS_HBLANK_B 0x61004
1946 #define _TRANS_HSYNC_B 0x61008
1947 #define _TRANS_VTOTAL_B 0x6100c
1948 #define _TRANS_VBLANK_B 0x61010
1949 #define _TRANS_VSYNC_B 0x61014
1950 #define _PIPEBSRC 0x6101c
1951 #define _BCLRPAT_B 0x61020
1952 #define _TRANS_VSYNCSHIFT_B 0x61028
1953 #define _TRANS_MULT_B 0x6102c
1955 /* DSI 0 timing regs */
1956 #define _TRANS_HTOTAL_DSI0 0x6b000
1957 #define _TRANS_HSYNC_DSI0 0x6b008
1958 #define _TRANS_VTOTAL_DSI0 0x6b00c
1959 #define _TRANS_VSYNC_DSI0 0x6b014
1960 #define _TRANS_VSYNCSHIFT_DSI0 0x6b028
1962 /* DSI 1 timing regs */
1963 #define _TRANS_HTOTAL_DSI1 0x6b800
1964 #define _TRANS_HSYNC_DSI1 0x6b808
1965 #define _TRANS_VTOTAL_DSI1 0x6b80c
1966 #define _TRANS_VSYNC_DSI1 0x6b814
1967 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828
1969 #define TRANSCODER_A_OFFSET 0x60000
1970 #define TRANSCODER_B_OFFSET 0x61000
1971 #define TRANSCODER_C_OFFSET 0x62000
1972 #define CHV_TRANSCODER_C_OFFSET 0x63000
1973 #define TRANSCODER_D_OFFSET 0x63000
1974 #define TRANSCODER_EDP_OFFSET 0x6f000
1975 #define TRANSCODER_DSI0_OFFSET 0x6b000
1976 #define TRANSCODER_DSI1_OFFSET 0x6b800
1978 #define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
1979 #define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
1980 #define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
1981 #define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A)
1982 #define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A)
1983 #define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A)
1984 #define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A)
1985 #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A)
1986 #define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC)
1987 #define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A)
1990 #define _TRANS_VRR_CTL_A 0x60420
1991 #define _TRANS_VRR_CTL_B 0x61420
1992 #define _TRANS_VRR_CTL_C 0x62420
1993 #define _TRANS_VRR_CTL_D 0x63420
1994 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
1995 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
1996 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
1997 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
1998 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
1999 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
2000 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
2001 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
2002 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
2004 #define _TRANS_VRR_VMAX_A 0x60424
2005 #define _TRANS_VRR_VMAX_B 0x61424
2006 #define _TRANS_VRR_VMAX_C 0x62424
2007 #define _TRANS_VRR_VMAX_D 0x63424
2008 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
2009 #define VRR_VMAX_MASK REG_GENMASK(19, 0)
2011 #define _TRANS_VRR_VMIN_A 0x60434
2012 #define _TRANS_VRR_VMIN_B 0x61434
2013 #define _TRANS_VRR_VMIN_C 0x62434
2014 #define _TRANS_VRR_VMIN_D 0x63434
2015 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
2016 #define VRR_VMIN_MASK REG_GENMASK(15, 0)
2018 #define _TRANS_VRR_VMAXSHIFT_A 0x60428
2019 #define _TRANS_VRR_VMAXSHIFT_B 0x61428
2020 #define _TRANS_VRR_VMAXSHIFT_C 0x62428
2021 #define _TRANS_VRR_VMAXSHIFT_D 0x63428
2022 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
2023 _TRANS_VRR_VMAXSHIFT_A)
2024 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
2025 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
2026 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
2028 #define _TRANS_VRR_STATUS_A 0x6042C
2029 #define _TRANS_VRR_STATUS_B 0x6142C
2030 #define _TRANS_VRR_STATUS_C 0x6242C
2031 #define _TRANS_VRR_STATUS_D 0x6342C
2032 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
2033 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2034 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2035 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2036 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2037 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2038 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2039 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
2040 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2041 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
2042 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
2043 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
2044 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
2045 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
2046 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
2048 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480
2049 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480
2050 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480
2051 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480
2052 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
2053 _TRANS_VRR_VTOTAL_PREV_A)
2054 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2055 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2056 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2057 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
2059 #define _TRANS_VRR_FLIPLINE_A 0x60438
2060 #define _TRANS_VRR_FLIPLINE_B 0x61438
2061 #define _TRANS_VRR_FLIPLINE_C 0x62438
2062 #define _TRANS_VRR_FLIPLINE_D 0x63438
2063 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
2064 _TRANS_VRR_FLIPLINE_A)
2065 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
2067 #define _TRANS_VRR_STATUS2_A 0x6043C
2068 #define _TRANS_VRR_STATUS2_B 0x6143C
2069 #define _TRANS_VRR_STATUS2_C 0x6243C
2070 #define _TRANS_VRR_STATUS2_D 0x6343C
2071 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
2072 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
2074 #define _TRANS_PUSH_A 0x60A70
2075 #define _TRANS_PUSH_B 0x61A70
2076 #define _TRANS_PUSH_C 0x62A70
2077 #define _TRANS_PUSH_D 0x63A70
2078 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
2079 #define TRANS_PUSH_EN REG_BIT(31)
2080 #define TRANS_PUSH_SEND REG_BIT(30)
2082 /* VGA port control */
2083 #define ADPA _MMIO(0x61100)
2084 #define PCH_ADPA _MMIO(0xe1100)
2085 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
2087 #define ADPA_DAC_ENABLE (1 << 31)
2088 #define ADPA_DAC_DISABLE 0
2089 #define ADPA_PIPE_SEL_SHIFT 30
2090 #define ADPA_PIPE_SEL_MASK (1 << 30)
2091 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
2092 #define ADPA_PIPE_SEL_SHIFT_CPT 29
2093 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
2094 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2095 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2096 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
2097 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
2098 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
2099 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
2100 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
2101 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
2102 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
2103 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
2104 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
2105 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
2106 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
2107 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
2108 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
2109 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
2110 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
2111 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
2112 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
2113 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
2114 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
2115 #define ADPA_SETS_HVPOLARITY 0
2116 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
2117 #define ADPA_VSYNC_CNTL_ENABLE 0
2118 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
2119 #define ADPA_HSYNC_CNTL_ENABLE 0
2120 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
2121 #define ADPA_VSYNC_ACTIVE_LOW 0
2122 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
2123 #define ADPA_HSYNC_ACTIVE_LOW 0
2124 #define ADPA_DPMS_MASK (~(3 << 10))
2125 #define ADPA_DPMS_ON (0 << 10)
2126 #define ADPA_DPMS_SUSPEND (1 << 10)
2127 #define ADPA_DPMS_STANDBY (2 << 10)
2128 #define ADPA_DPMS_OFF (3 << 10)
2131 /* Hotplug control (945+ only) */
2132 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2133 #define PORTB_HOTPLUG_INT_EN (1 << 29)
2134 #define PORTC_HOTPLUG_INT_EN (1 << 28)
2135 #define PORTD_HOTPLUG_INT_EN (1 << 27)
2136 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
2137 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
2138 #define TV_HOTPLUG_INT_EN (1 << 18)
2139 #define CRT_HOTPLUG_INT_EN (1 << 9)
2140 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2141 PORTC_HOTPLUG_INT_EN | \
2142 PORTD_HOTPLUG_INT_EN | \
2143 SDVOC_HOTPLUG_INT_EN | \
2144 SDVOB_HOTPLUG_INT_EN | \
2146 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2147 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2148 /* must use period 64 on GM45 according to docs */
2149 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2150 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2151 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2152 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2153 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2154 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2155 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2156 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2157 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2158 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2159 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2160 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2162 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2163 /* HDMI/DP bits are g4x+ */
2164 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2165 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2166 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2167 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2168 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2169 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2170 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2171 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2172 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2173 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2174 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2175 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2176 /* CRT/TV common between gen3+ */
2177 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
2178 #define TV_HOTPLUG_INT_STATUS (1 << 10)
2179 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2180 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2181 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2182 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2183 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2184 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2185 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2186 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2188 /* SDVO is different across gen3/4 */
2189 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2190 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2192 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2193 * since reality corrobates that they're the same as on gen3. But keep these
2194 * bits here (and the comment!) to help any other lost wanderers back onto the
2197 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2198 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2199 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2200 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2201 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2202 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2203 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2204 PORTB_HOTPLUG_INT_STATUS | \
2205 PORTC_HOTPLUG_INT_STATUS | \
2206 PORTD_HOTPLUG_INT_STATUS)
2208 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2209 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2210 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2211 PORTB_HOTPLUG_INT_STATUS | \
2212 PORTC_HOTPLUG_INT_STATUS | \
2213 PORTD_HOTPLUG_INT_STATUS)
2215 /* SDVO and HDMI port control.
2216 * The same register may be used for SDVO or HDMI */
2217 #define _GEN3_SDVOB 0x61140
2218 #define _GEN3_SDVOC 0x61160
2219 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
2220 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
2221 #define GEN4_HDMIB GEN3_SDVOB
2222 #define GEN4_HDMIC GEN3_SDVOC
2223 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
2224 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
2225 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
2226 #define PCH_SDVOB _MMIO(0xe1140)
2227 #define PCH_HDMIB PCH_SDVOB
2228 #define PCH_HDMIC _MMIO(0xe1150)
2229 #define PCH_HDMID _MMIO(0xe1160)
2231 #define PORT_DFT_I9XX _MMIO(0x61150)
2232 #define DC_BALANCE_RESET (1 << 25)
2233 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2234 #define DC_BALANCE_RESET_VLV (1 << 31)
2235 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2236 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2237 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2238 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2240 /* Gen 3 SDVO bits: */
2241 #define SDVO_ENABLE (1 << 31)
2242 #define SDVO_PIPE_SEL_SHIFT 30
2243 #define SDVO_PIPE_SEL_MASK (1 << 30)
2244 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2245 #define SDVO_STALL_SELECT (1 << 29)
2246 #define SDVO_INTERRUPT_ENABLE (1 << 26)
2248 * 915G/GM SDVO pixel multiplier.
2249 * Programmed value is multiplier - 1, up to 5x.
2250 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2252 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2253 #define SDVO_PORT_MULTIPLY_SHIFT 23
2254 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2255 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2256 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2257 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2258 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2259 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2260 #define SDVO_DETECTED (1 << 2)
2261 /* Bits to be preserved when writing */
2262 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2263 SDVO_INTERRUPT_ENABLE)
2264 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2266 /* Gen 4 SDVO/HDMI bits: */
2267 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2268 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
2269 #define SDVO_ENCODING_SDVO (0 << 10)
2270 #define SDVO_ENCODING_HDMI (2 << 10)
2271 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2272 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2273 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2274 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
2275 /* VSYNC/HSYNC bits new with 965, default is to be set */
2276 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2277 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2279 /* Gen 5 (IBX) SDVO/HDMI bits: */
2280 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2281 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2283 /* Gen 6 (CPT) SDVO/HDMI bits: */
2284 #define SDVO_PIPE_SEL_SHIFT_CPT 29
2285 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2286 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2288 /* CHV SDVO/HDMI bits: */
2289 #define SDVO_PIPE_SEL_SHIFT_CHV 24
2290 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2291 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2293 /* Video Data Island Packet control */
2294 #define VIDEO_DIP_DATA _MMIO(0x61178)
2295 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
2296 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2297 * of the infoframe structure specified by CEA-861. */
2298 #define VIDEO_DIP_DATA_SIZE 32
2299 #define VIDEO_DIP_GMP_DATA_SIZE 36
2300 #define VIDEO_DIP_VSC_DATA_SIZE 36
2301 #define VIDEO_DIP_PPS_DATA_SIZE 132
2302 #define VIDEO_DIP_CTL _MMIO(0x61170)
2304 #define VIDEO_DIP_ENABLE (1 << 31)
2305 #define VIDEO_DIP_PORT(port) ((port) << 29)
2306 #define VIDEO_DIP_PORT_MASK (3 << 29)
2307 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
2308 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2309 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2310 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
2311 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2312 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2313 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2314 #define VIDEO_DIP_SELECT_GAMUT (2 << 19)
2315 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2316 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2317 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2318 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2319 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2320 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2321 /* HSW and later: */
2322 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
2323 #define PSR_VSC_BIT_7_SET (1 << 27)
2324 #define VSC_SELECT_MASK (0x3 << 25)
2325 #define VSC_SELECT_SHIFT 25
2326 #define VSC_DIP_HW_HEA_DATA (0 << 25)
2327 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
2328 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
2329 #define VSC_DIP_SW_HEA_DATA (3 << 25)
2330 #define VDIP_ENABLE_PPS (1 << 24)
2331 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2332 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2333 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2334 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2335 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2336 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2339 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2340 #define PFIT_ENABLE REG_BIT(31)
2341 #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
2342 #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
2343 #define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
2344 #define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
2345 #define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
2346 #define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
2347 #define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
2348 #define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
2349 #define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
2350 #define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
2351 #define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
2352 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
2353 #define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
2354 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
2355 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
2356 #define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
2357 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
2358 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
2360 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2361 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
2362 #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
2363 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
2364 #define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
2365 #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
2366 #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
2368 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2370 #define PCH_GTC_CTL _MMIO(0xe7000)
2371 #define PCH_GTC_ENABLE (1 << 31)
2374 #define DP_A _MMIO(0x64000) /* eDP */
2375 #define DP_B _MMIO(0x64100)
2376 #define DP_C _MMIO(0x64200)
2377 #define DP_D _MMIO(0x64300)
2379 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
2380 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
2381 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
2383 #define DP_PORT_EN (1 << 31)
2384 #define DP_PIPE_SEL_SHIFT 30
2385 #define DP_PIPE_SEL_MASK (1 << 30)
2386 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
2387 #define DP_PIPE_SEL_SHIFT_IVB 29
2388 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
2389 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
2390 #define DP_PIPE_SEL_SHIFT_CHV 16
2391 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
2392 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
2394 /* Link training mode - select a suitable mode for each stage */
2395 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2396 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2397 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2398 #define DP_LINK_TRAIN_OFF (3 << 28)
2399 #define DP_LINK_TRAIN_MASK (3 << 28)
2400 #define DP_LINK_TRAIN_SHIFT 28
2402 /* CPT Link training mode */
2403 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2404 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2405 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2406 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2407 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2408 #define DP_LINK_TRAIN_SHIFT_CPT 8
2410 /* Signal voltages. These are mostly controlled by the other end */
2411 #define DP_VOLTAGE_0_4 (0 << 25)
2412 #define DP_VOLTAGE_0_6 (1 << 25)
2413 #define DP_VOLTAGE_0_8 (2 << 25)
2414 #define DP_VOLTAGE_1_2 (3 << 25)
2415 #define DP_VOLTAGE_MASK (7 << 25)
2416 #define DP_VOLTAGE_SHIFT 25
2418 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2421 #define DP_PRE_EMPHASIS_0 (0 << 22)
2422 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2423 #define DP_PRE_EMPHASIS_6 (2 << 22)
2424 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2425 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2426 #define DP_PRE_EMPHASIS_SHIFT 22
2428 /* How many wires to use. I guess 3 was too hard */
2429 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
2430 #define DP_PORT_WIDTH_MASK (7 << 19)
2431 #define DP_PORT_WIDTH_SHIFT 19
2433 /* Mystic DPCD version 1.1 special mode */
2434 #define DP_ENHANCED_FRAMING (1 << 18)
2437 #define DP_PLL_FREQ_270MHZ (0 << 16)
2438 #define DP_PLL_FREQ_162MHZ (1 << 16)
2439 #define DP_PLL_FREQ_MASK (3 << 16)
2441 /* locked once port is enabled */
2442 #define DP_PORT_REVERSAL (1 << 15)
2445 #define DP_PLL_ENABLE (1 << 14)
2447 /* sends the clock on lane 15 of the PEG for debug */
2448 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2450 #define DP_SCRAMBLING_DISABLE (1 << 12)
2451 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2453 /* limit RGB values to avoid confusing TVs */
2454 #define DP_COLOR_RANGE_16_235 (1 << 8)
2456 /* Turn on the audio link */
2457 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2459 /* vs and hs sync polarity */
2460 #define DP_SYNC_VS_HIGH (1 << 4)
2461 #define DP_SYNC_HS_HIGH (1 << 3)
2464 #define DP_DETECTED (1 << 2)
2467 * Computing GMCH M and N values for the Display Port link
2469 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2471 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2473 * The GMCH value is used internally
2475 * bytes_per_pixel is the number of bytes coming out of the plane,
2476 * which is after the LUTs, so we want the bytes for our color format.
2477 * For our current usage, this is always 3, one byte for R, G and B.
2479 #define _PIPEA_DATA_M_G4X 0x70050
2480 #define _PIPEB_DATA_M_G4X 0x71050
2482 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2483 #define TU_SIZE_MASK REG_GENMASK(30, 25)
2484 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
2486 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
2487 #define DATA_LINK_N_MAX (0x800000)
2489 #define _PIPEA_DATA_N_G4X 0x70054
2490 #define _PIPEB_DATA_N_G4X 0x71054
2493 * Computing Link M and N values for the Display Port link
2495 * Link M / N = pixel_clock / ls_clk
2497 * (the DP spec calls pixel_clock the 'strm_clk')
2499 * The Link value is transmitted in the Main Stream
2500 * Attributes and VB-ID.
2503 #define _PIPEA_LINK_M_G4X 0x70060
2504 #define _PIPEB_LINK_M_G4X 0x71060
2505 #define _PIPEA_LINK_N_G4X 0x70064
2506 #define _PIPEB_LINK_N_G4X 0x71064
2508 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
2509 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
2510 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
2511 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2513 /* Display & cursor control */
2516 #define _PIPEADSL 0x70000
2517 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
2518 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
2519 #define _TRANSACONF 0x70008
2520 #define TRANSCONF_ENABLE REG_BIT(31)
2521 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
2522 #define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
2523 #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
2524 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
2525 #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
2526 #define TRANSCONF_PIPE_LOCKED REG_BIT(25)
2527 #define TRANSCONF_FORCE_BORDER REG_BIT(25)
2528 #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
2529 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
2530 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
2531 #define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
2532 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
2533 #define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
2534 #define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
2535 #define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
2536 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
2537 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
2538 #define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
2539 #define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
2540 #define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
2542 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
2543 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
2545 #define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
2546 #define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
2547 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
2548 #define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
2549 #define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
2550 #define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
2551 #define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
2552 #define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
2553 #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
2554 #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
2555 #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
2556 #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
2557 #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
2558 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
2559 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
2560 #define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
2561 #define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
2562 #define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
2563 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
2564 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
2565 #define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
2566 #define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
2567 #define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
2568 #define TRANSCONF_DITHER_EN REG_BIT(4)
2569 #define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
2570 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
2571 #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
2572 #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
2573 #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
2574 #define _PIPEASTAT 0x70024
2575 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
2576 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
2577 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
2578 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
2579 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
2580 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
2581 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
2582 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
2583 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
2584 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
2585 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
2586 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
2587 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
2588 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
2589 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
2590 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
2591 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
2592 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
2593 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
2594 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
2595 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
2596 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
2597 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
2598 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
2599 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
2600 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
2601 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
2602 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
2603 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
2604 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
2605 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
2606 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
2607 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
2608 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
2609 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
2610 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
2611 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
2612 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
2613 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
2614 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
2615 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
2616 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
2617 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
2618 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
2619 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
2620 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
2622 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
2623 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
2625 #define PIPE_A_OFFSET 0x70000
2626 #define PIPE_B_OFFSET 0x71000
2627 #define PIPE_C_OFFSET 0x72000
2628 #define PIPE_D_OFFSET 0x73000
2629 #define CHV_PIPE_C_OFFSET 0x74000
2631 * There's actually no pipe EDP. Some pipe registers have
2632 * simply shifted from the pipe to the transcoder, while
2633 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
2634 * to access such registers in transcoder EDP.
2636 #define PIPE_EDP_OFFSET 0x7f000
2638 /* ICL DSI 0 and 1 */
2639 #define PIPE_DSI0_OFFSET 0x7b000
2640 #define PIPE_DSI1_OFFSET 0x7b800
2642 #define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
2643 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
2644 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
2645 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
2646 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
2648 #define _PIPEAGCMAX 0x70010
2649 #define _PIPEBGCMAX 0x71010
2650 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
2652 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
2653 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
2654 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
2656 #define _PIPE_MISC_A 0x70030
2657 #define _PIPE_MISC_B 0x71030
2658 #define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
2659 #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
2660 #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
2661 #define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
2662 #define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
2663 #define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
2664 #define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
2665 #define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
2666 #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
2667 #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
2669 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
2670 * valid values of: 6, 8, 10 BPC.
2671 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
2674 #define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
2675 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
2676 #define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
2677 #define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
2678 #define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
2679 #define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
2680 #define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
2681 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
2682 #define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
2683 #define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
2684 #define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
2685 #define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
2687 #define _PIPE_MISC2_A 0x7002C
2688 #define _PIPE_MISC2_B 0x7102C
2689 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
2690 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
2691 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
2692 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
2693 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
2694 #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
2696 /* Skylake+ pipe bottom (background) color */
2697 #define _SKL_BOTTOM_COLOR_A 0x70034
2698 #define _SKL_BOTTOM_COLOR_B 0x71034
2699 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
2700 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
2701 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
2703 #define _ICL_PIPE_A_STATUS 0x70058
2704 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
2705 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
2706 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
2707 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
2708 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
2710 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
2711 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
2712 #define PIPEB_HLINE_INT_EN REG_BIT(28)
2713 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
2714 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
2715 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
2716 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
2717 #define PIPE_PSR_INT_EN REG_BIT(22)
2718 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
2719 #define PIPEA_HLINE_INT_EN REG_BIT(20)
2720 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
2721 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
2722 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
2723 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
2724 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
2725 #define PIPEC_HLINE_INT_EN REG_BIT(12)
2726 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
2727 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
2728 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
2729 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
2731 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
2732 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
2733 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
2734 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
2735 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
2736 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
2737 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
2738 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
2739 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
2740 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
2741 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
2742 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
2743 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
2744 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
2745 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
2746 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
2747 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
2748 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
2749 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
2750 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
2751 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
2752 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
2753 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
2754 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
2755 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
2756 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
2757 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
2758 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
2759 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
2761 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
2762 #define DSPARB_CSTART_MASK (0x7f << 7)
2763 #define DSPARB_CSTART_SHIFT 7
2764 #define DSPARB_BSTART_MASK (0x7f)
2765 #define DSPARB_BSTART_SHIFT 0
2766 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2767 #define DSPARB_AEND_SHIFT 0
2768 #define DSPARB_SPRITEA_SHIFT_VLV 0
2769 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
2770 #define DSPARB_SPRITEB_SHIFT_VLV 8
2771 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
2772 #define DSPARB_SPRITEC_SHIFT_VLV 16
2773 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
2774 #define DSPARB_SPRITED_SHIFT_VLV 24
2775 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
2776 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
2777 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
2778 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
2779 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
2780 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
2781 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
2782 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
2783 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
2784 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
2785 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
2786 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
2787 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
2788 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
2789 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
2790 #define DSPARB_SPRITEE_SHIFT_VLV 0
2791 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
2792 #define DSPARB_SPRITEF_SHIFT_VLV 8
2793 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
2795 /* pnv/gen4/g4x/vlv/chv */
2796 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
2797 #define DSPFW_SR_SHIFT 23
2798 #define DSPFW_SR_MASK (0x1ff << 23)
2799 #define DSPFW_CURSORB_SHIFT 16
2800 #define DSPFW_CURSORB_MASK (0x3f << 16)
2801 #define DSPFW_PLANEB_SHIFT 8
2802 #define DSPFW_PLANEB_MASK (0x7f << 8)
2803 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
2804 #define DSPFW_PLANEA_SHIFT 0
2805 #define DSPFW_PLANEA_MASK (0x7f << 0)
2806 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
2807 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
2808 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
2809 #define DSPFW_FBC_SR_SHIFT 28
2810 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
2811 #define DSPFW_FBC_HPLL_SR_SHIFT 24
2812 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
2813 #define DSPFW_SPRITEB_SHIFT (16)
2814 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
2815 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
2816 #define DSPFW_CURSORA_SHIFT 8
2817 #define DSPFW_CURSORA_MASK (0x3f << 8)
2818 #define DSPFW_PLANEC_OLD_SHIFT 0
2819 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
2820 #define DSPFW_SPRITEA_SHIFT 0
2821 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
2822 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
2823 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
2824 #define DSPFW_HPLL_SR_EN (1 << 31)
2825 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
2826 #define DSPFW_CURSOR_SR_SHIFT 24
2827 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
2828 #define DSPFW_HPLL_CURSOR_SHIFT 16
2829 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
2830 #define DSPFW_HPLL_SR_SHIFT 0
2831 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
2834 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
2835 #define DSPFW_SPRITEB_WM1_SHIFT 16
2836 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
2837 #define DSPFW_CURSORA_WM1_SHIFT 8
2838 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
2839 #define DSPFW_SPRITEA_WM1_SHIFT 0
2840 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
2841 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
2842 #define DSPFW_PLANEB_WM1_SHIFT 24
2843 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
2844 #define DSPFW_PLANEA_WM1_SHIFT 16
2845 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
2846 #define DSPFW_CURSORB_WM1_SHIFT 8
2847 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
2848 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
2849 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
2850 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
2851 #define DSPFW_SR_WM1_SHIFT 0
2852 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
2853 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
2854 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
2855 #define DSPFW_SPRITED_WM1_SHIFT 24
2856 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
2857 #define DSPFW_SPRITED_SHIFT 16
2858 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
2859 #define DSPFW_SPRITEC_WM1_SHIFT 8
2860 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
2861 #define DSPFW_SPRITEC_SHIFT 0
2862 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
2863 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
2864 #define DSPFW_SPRITEF_WM1_SHIFT 24
2865 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
2866 #define DSPFW_SPRITEF_SHIFT 16
2867 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
2868 #define DSPFW_SPRITEE_WM1_SHIFT 8
2869 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
2870 #define DSPFW_SPRITEE_SHIFT 0
2871 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
2872 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
2873 #define DSPFW_PLANEC_WM1_SHIFT 24
2874 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
2875 #define DSPFW_PLANEC_SHIFT 16
2876 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
2877 #define DSPFW_CURSORC_WM1_SHIFT 8
2878 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
2879 #define DSPFW_CURSORC_SHIFT 0
2880 #define DSPFW_CURSORC_MASK (0x3f << 0)
2882 /* vlv/chv high order bits */
2883 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
2884 #define DSPFW_SR_HI_SHIFT 24
2885 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
2886 #define DSPFW_SPRITEF_HI_SHIFT 23
2887 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
2888 #define DSPFW_SPRITEE_HI_SHIFT 22
2889 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
2890 #define DSPFW_PLANEC_HI_SHIFT 21
2891 #define DSPFW_PLANEC_HI_MASK (1 << 21)
2892 #define DSPFW_SPRITED_HI_SHIFT 20
2893 #define DSPFW_SPRITED_HI_MASK (1 << 20)
2894 #define DSPFW_SPRITEC_HI_SHIFT 16
2895 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
2896 #define DSPFW_PLANEB_HI_SHIFT 12
2897 #define DSPFW_PLANEB_HI_MASK (1 << 12)
2898 #define DSPFW_SPRITEB_HI_SHIFT 8
2899 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
2900 #define DSPFW_SPRITEA_HI_SHIFT 4
2901 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
2902 #define DSPFW_PLANEA_HI_SHIFT 0
2903 #define DSPFW_PLANEA_HI_MASK (1 << 0)
2904 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
2905 #define DSPFW_SR_WM1_HI_SHIFT 24
2906 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
2907 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
2908 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
2909 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
2910 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
2911 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
2912 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
2913 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
2914 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
2915 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
2916 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
2917 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
2918 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
2919 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
2920 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
2921 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
2922 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
2923 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
2924 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
2926 /* drain latency register values*/
2927 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
2928 #define DDL_CURSOR_SHIFT 24
2929 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
2930 #define DDL_PLANE_SHIFT 0
2931 #define DDL_PRECISION_HIGH (1 << 7)
2932 #define DDL_PRECISION_LOW (0 << 7)
2933 #define DRAIN_LATENCY_MASK 0x7f
2935 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
2936 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
2937 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
2939 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
2940 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
2942 /* FIFO watermark sizes etc */
2943 #define G4X_FIFO_LINE_SIZE 64
2944 #define I915_FIFO_LINE_SIZE 64
2945 #define I830_FIFO_LINE_SIZE 32
2947 #define VALLEYVIEW_FIFO_SIZE 255
2948 #define G4X_FIFO_SIZE 127
2949 #define I965_FIFO_SIZE 512
2950 #define I945_FIFO_SIZE 127
2951 #define I915_FIFO_SIZE 95
2952 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2953 #define I830_FIFO_SIZE 95
2955 #define VALLEYVIEW_MAX_WM 0xff
2956 #define G4X_MAX_WM 0x3f
2957 #define I915_MAX_WM 0x3f
2959 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2960 #define PINEVIEW_FIFO_LINE_SIZE 64
2961 #define PINEVIEW_MAX_WM 0x1ff
2962 #define PINEVIEW_DFT_WM 0x3f
2963 #define PINEVIEW_DFT_HPLLOFF_WM 0
2964 #define PINEVIEW_GUARD_WM 10
2965 #define PINEVIEW_CURSOR_FIFO 64
2966 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2967 #define PINEVIEW_CURSOR_DFT_WM 0
2968 #define PINEVIEW_CURSOR_GUARD_WM 5
2970 #define VALLEYVIEW_CURSOR_MAX_WM 64
2971 #define I965_CURSOR_FIFO 64
2972 #define I965_CURSOR_MAX_WM 32
2973 #define I965_CURSOR_DFT_WM 8
2975 /* define the Watermark register on Ironlake */
2976 #define _WM0_PIPEA_ILK 0x45100
2977 #define _WM0_PIPEB_ILK 0x45104
2978 #define _WM0_PIPEC_IVB 0x45200
2979 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
2980 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
2981 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
2982 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
2983 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2984 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
2985 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
2986 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
2987 #define WM1_LP_ILK _MMIO(0x45108)
2988 #define WM2_LP_ILK _MMIO(0x4510c)
2989 #define WM3_LP_ILK _MMIO(0x45110)
2990 #define WM_LP_ENABLE REG_BIT(31)
2991 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
2992 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
2993 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
2994 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
2995 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2996 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
2997 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
2998 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
2999 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
3000 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
3001 #define WM1S_LP_ILK _MMIO(0x45120)
3002 #define WM2S_LP_IVB _MMIO(0x45124)
3003 #define WM3S_LP_IVB _MMIO(0x45128)
3004 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
3005 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
3006 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
3009 * The two pipe frame counter registers are not synchronized, so
3010 * reading a stable value is somewhat tricky. The following code
3014 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3015 * PIPE_FRAME_HIGH_SHIFT;
3016 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3017 * PIPE_FRAME_LOW_SHIFT);
3018 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3019 * PIPE_FRAME_HIGH_SHIFT);
3020 * } while (high1 != high2);
3021 * frame = (high1 << 8) | low1;
3023 #define _PIPEAFRAMEHIGH 0x70040
3024 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
3025 #define PIPE_FRAME_HIGH_SHIFT 0
3026 #define _PIPEAFRAMEPIXEL 0x70044
3027 #define PIPE_FRAME_LOW_MASK 0xff000000
3028 #define PIPE_FRAME_LOW_SHIFT 24
3029 #define PIPE_PIXEL_MASK 0x00ffffff
3030 #define PIPE_PIXEL_SHIFT 0
3031 /* GM45+ just has to be different */
3032 #define _PIPEA_FRMCOUNT_G4X 0x70040
3033 #define _PIPEA_FLIPCOUNT_G4X 0x70044
3034 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
3035 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
3037 /* Cursor A & B regs */
3038 #define _CURACNTR 0x70080
3039 /* Old style CUR*CNTR flags (desktop 8xx) */
3040 #define CURSOR_ENABLE REG_BIT(31)
3041 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
3042 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
3043 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
3044 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
3045 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
3046 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
3047 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
3048 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
3049 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
3050 /* New style CUR*CNTR flags */
3051 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
3052 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
3053 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
3054 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
3055 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
3056 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
3057 #define MCURSOR_ROTATE_180 REG_BIT(15)
3058 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
3059 #define MCURSOR_MODE_MASK 0x27
3060 #define MCURSOR_MODE_DISABLE 0x00
3061 #define MCURSOR_MODE_128_32B_AX 0x02
3062 #define MCURSOR_MODE_256_32B_AX 0x03
3063 #define MCURSOR_MODE_64_32B_AX 0x07
3064 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
3065 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
3066 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
3067 #define _CURABASE 0x70084
3068 #define _CURAPOS 0x70088
3069 #define CURSOR_POS_Y_SIGN REG_BIT(31)
3070 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
3071 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
3072 #define CURSOR_POS_X_SIGN REG_BIT(15)
3073 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
3074 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
3075 #define _CURASIZE 0x700a0 /* 845/865 */
3076 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
3077 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
3078 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
3079 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
3080 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
3081 #define CUR_FBC_EN REG_BIT(31)
3082 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
3083 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
3084 #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
3085 #define _CURASURFLIVE 0x700ac /* g4x+ */
3086 #define _CURBCNTR 0x700c0
3087 #define _CURBBASE 0x700c4
3088 #define _CURBPOS 0x700c8
3090 #define _CURBCNTR_IVB 0x71080
3091 #define _CURBBASE_IVB 0x71084
3092 #define _CURBPOS_IVB 0x71088
3094 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
3095 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
3096 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
3097 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
3098 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
3099 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
3100 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
3102 #define CURSOR_A_OFFSET 0x70080
3103 #define CURSOR_B_OFFSET 0x700c0
3104 #define CHV_CURSOR_C_OFFSET 0x700e0
3105 #define IVB_CURSOR_B_OFFSET 0x71080
3106 #define IVB_CURSOR_C_OFFSET 0x72080
3107 #define TGL_CURSOR_D_OFFSET 0x73080
3109 /* Display A control */
3110 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
3111 #define _DSPACNTR 0x70180
3112 #define DISP_ENABLE REG_BIT(31)
3113 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
3114 #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
3115 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
3116 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
3117 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
3118 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
3119 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
3120 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
3121 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
3122 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
3123 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
3124 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
3125 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
3126 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
3127 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
3128 #define DISP_STEREO_ENABLE REG_BIT(25)
3129 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
3130 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
3131 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
3132 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
3133 #define DISP_LINE_DOUBLE REG_BIT(20)
3134 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
3135 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
3136 #define DISP_ROTATE_180 REG_BIT(15)
3137 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
3138 #define DISP_TILED REG_BIT(10)
3139 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
3140 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
3141 #define _DSPAADDR 0x70184
3142 #define _DSPASTRIDE 0x70188
3143 #define _DSPAPOS 0x7018C /* reserved */
3144 #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
3145 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
3146 #define DISP_POS_X_MASK REG_GENMASK(15, 0)
3147 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
3148 #define _DSPASIZE 0x70190
3149 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
3150 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
3151 #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
3152 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
3153 #define _DSPASURF 0x7019C /* 965+ only */
3154 #define DISP_ADDR_MASK REG_GENMASK(31, 12)
3155 #define _DSPATILEOFF 0x701A4 /* 965+ only */
3156 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
3157 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
3158 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
3159 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
3160 #define _DSPAOFFSET 0x701A4 /* HSW */
3161 #define _DSPASURFLIVE 0x701AC
3162 #define _DSPAGAMC 0x701E0
3164 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
3165 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
3166 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
3167 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
3168 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
3169 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
3170 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
3171 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
3172 #define DSPLINOFF(plane) DSPADDR(plane)
3173 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
3174 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
3175 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
3177 /* CHV pipe B blender and primary plane */
3178 #define _CHV_BLEND_A 0x60a00
3179 #define CHV_BLEND_MASK REG_GENMASK(31, 30)
3180 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
3181 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
3182 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
3183 #define _CHV_CANVAS_A 0x60a04
3184 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
3185 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
3186 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
3187 #define _PRIMPOS_A 0x60a08
3188 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
3189 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
3190 #define PRIM_POS_X_MASK REG_GENMASK(15, 0)
3191 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
3192 #define _PRIMSIZE_A 0x60a0c
3193 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
3194 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
3195 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
3196 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
3197 #define _PRIMCNSTALPHA_A 0x60a10
3198 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
3199 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
3200 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
3202 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
3203 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
3204 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
3205 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
3206 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
3208 /* Display/Sprite base address macros */
3209 #define DISP_BASEADDR_MASK (0xfffff000)
3210 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
3211 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
3224 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
3225 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
3226 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
3227 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
3230 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
3231 #define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
3232 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
3233 #define _PIPEBFRAMEHIGH 0x71040
3234 #define _PIPEBFRAMEPIXEL 0x71044
3235 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
3236 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
3239 /* Display B control */
3240 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
3241 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
3242 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
3243 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
3244 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
3245 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
3246 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
3247 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
3248 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3249 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3250 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
3252 /* ICL DSI 0 and 1 */
3253 #define _PIPEDSI0CONF 0x7b008
3254 #define _PIPEDSI1CONF 0x7b808
3256 /* Sprite A control */
3257 #define _DVSACNTR 0x72180
3258 #define DVS_ENABLE REG_BIT(31)
3259 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
3260 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
3261 #define DVS_FORMAT_MASK REG_GENMASK(26, 25)
3262 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
3263 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
3264 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
3265 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
3266 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
3267 #define DVS_SOURCE_KEY REG_BIT(22)
3268 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
3269 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
3270 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
3271 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
3272 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
3273 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
3274 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
3275 #define DVS_ROTATE_180 REG_BIT(15)
3276 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
3277 #define DVS_TILED REG_BIT(10)
3278 #define DVS_DEST_KEY REG_BIT(2)
3279 #define _DVSALINOFF 0x72184
3280 #define _DVSASTRIDE 0x72188
3281 #define _DVSAPOS 0x7218c
3282 #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
3283 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
3284 #define DVS_POS_X_MASK REG_GENMASK(15, 0)
3285 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
3286 #define _DVSASIZE 0x72190
3287 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
3288 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
3289 #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
3290 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
3291 #define _DVSAKEYVAL 0x72194
3292 #define _DVSAKEYMSK 0x72198
3293 #define _DVSASURF 0x7219c
3294 #define DVS_ADDR_MASK REG_GENMASK(31, 12)
3295 #define _DVSAKEYMAXVAL 0x721a0
3296 #define _DVSATILEOFF 0x721a4
3297 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
3298 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
3299 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
3300 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
3301 #define _DVSASURFLIVE 0x721ac
3302 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
3303 #define _DVSASCALE 0x72204
3304 #define DVS_SCALE_ENABLE REG_BIT(31)
3305 #define DVS_FILTER_MASK REG_GENMASK(30, 29)
3306 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
3307 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
3308 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
3309 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
3310 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
3311 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
3312 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
3313 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
3314 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
3315 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
3316 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
3318 #define _DVSBCNTR 0x73180
3319 #define _DVSBLINOFF 0x73184
3320 #define _DVSBSTRIDE 0x73188
3321 #define _DVSBPOS 0x7318c
3322 #define _DVSBSIZE 0x73190
3323 #define _DVSBKEYVAL 0x73194
3324 #define _DVSBKEYMSK 0x73198
3325 #define _DVSBSURF 0x7319c
3326 #define _DVSBKEYMAXVAL 0x731a0
3327 #define _DVSBTILEOFF 0x731a4
3328 #define _DVSBSURFLIVE 0x731ac
3329 #define _DVSBGAMC_G4X 0x731e0 /* g4x */
3330 #define _DVSBSCALE 0x73204
3331 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
3332 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
3334 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3335 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3336 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3337 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
3338 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
3339 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3340 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3341 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3342 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3343 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3344 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3345 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3346 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
3347 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
3348 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
3350 #define _SPRA_CTL 0x70280
3351 #define SPRITE_ENABLE REG_BIT(31)
3352 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
3353 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3354 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
3355 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
3356 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
3357 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
3358 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
3359 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
3360 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
3361 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
3362 #define SPRITE_SOURCE_KEY REG_BIT(22)
3363 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
3364 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
3365 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
3366 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
3367 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
3368 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
3369 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
3370 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
3371 #define SPRITE_ROTATE_180 REG_BIT(15)
3372 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
3373 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
3374 #define SPRITE_TILED REG_BIT(10)
3375 #define SPRITE_DEST_KEY REG_BIT(2)
3376 #define _SPRA_LINOFF 0x70284
3377 #define _SPRA_STRIDE 0x70288
3378 #define _SPRA_POS 0x7028c
3379 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
3380 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
3381 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
3382 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
3383 #define _SPRA_SIZE 0x70290
3384 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
3385 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
3386 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
3387 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
3388 #define _SPRA_KEYVAL 0x70294
3389 #define _SPRA_KEYMSK 0x70298
3390 #define _SPRA_SURF 0x7029c
3391 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
3392 #define _SPRA_KEYMAX 0x702a0
3393 #define _SPRA_TILEOFF 0x702a4
3394 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
3395 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
3396 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
3397 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
3398 #define _SPRA_OFFSET 0x702a4
3399 #define _SPRA_SURFLIVE 0x702ac
3400 #define _SPRA_SCALE 0x70304
3401 #define SPRITE_SCALE_ENABLE REG_BIT(31)
3402 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
3403 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
3404 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
3405 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
3406 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
3407 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
3408 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
3409 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
3410 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
3411 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
3412 #define _SPRA_GAMC 0x70400
3413 #define _SPRA_GAMC16 0x70440
3414 #define _SPRA_GAMC17 0x7044c
3416 #define _SPRB_CTL 0x71280
3417 #define _SPRB_LINOFF 0x71284
3418 #define _SPRB_STRIDE 0x71288
3419 #define _SPRB_POS 0x7128c
3420 #define _SPRB_SIZE 0x71290
3421 #define _SPRB_KEYVAL 0x71294
3422 #define _SPRB_KEYMSK 0x71298
3423 #define _SPRB_SURF 0x7129c
3424 #define _SPRB_KEYMAX 0x712a0
3425 #define _SPRB_TILEOFF 0x712a4
3426 #define _SPRB_OFFSET 0x712a4
3427 #define _SPRB_SURFLIVE 0x712ac
3428 #define _SPRB_SCALE 0x71304
3429 #define _SPRB_GAMC 0x71400
3430 #define _SPRB_GAMC16 0x71440
3431 #define _SPRB_GAMC17 0x7144c
3433 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3434 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3435 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3436 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
3437 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3438 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3439 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3440 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3441 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3442 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3443 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3444 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3445 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
3446 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
3447 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
3448 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3450 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3451 #define SP_ENABLE REG_BIT(31)
3452 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
3453 #define SP_FORMAT_MASK REG_GENMASK(29, 26)
3454 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
3455 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
3456 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
3457 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
3458 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
3459 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
3460 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
3461 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
3462 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
3463 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
3464 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
3465 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
3466 #define SP_SOURCE_KEY REG_BIT(22)
3467 #define SP_YUV_FORMAT_BT709 REG_BIT(18)
3468 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
3469 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
3470 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
3471 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
3472 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
3473 #define SP_ROTATE_180 REG_BIT(15)
3474 #define SP_TILED REG_BIT(10)
3475 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
3476 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3477 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3478 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3479 #define SP_POS_Y_MASK REG_GENMASK(31, 16)
3480 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
3481 #define SP_POS_X_MASK REG_GENMASK(15, 0)
3482 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
3483 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3484 #define SP_HEIGHT_MASK REG_GENMASK(31, 16)
3485 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
3486 #define SP_WIDTH_MASK REG_GENMASK(15, 0)
3487 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
3488 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3489 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3490 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3491 #define SP_ADDR_MASK REG_GENMASK(31, 12)
3492 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3493 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3494 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
3495 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
3496 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
3497 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
3498 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3499 #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
3500 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
3501 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
3502 #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
3503 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
3504 #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
3505 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
3506 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
3507 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
3508 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
3509 #define SP_SH_SIN_MASK REG_GENMASK(26, 16)
3510 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
3511 #define SP_SH_COS_MASK REG_GENMASK(9, 0)
3512 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
3513 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
3515 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3516 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3517 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3518 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3519 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3520 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3521 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3522 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3523 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3524 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3525 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3526 #define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
3527 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
3528 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
3529 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
3531 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
3532 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
3533 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
3534 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
3536 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
3537 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
3538 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
3539 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
3540 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
3541 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
3542 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
3543 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
3544 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3545 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
3546 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
3547 #define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
3548 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
3549 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
3550 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
3553 * CHV pipe B sprite CSC
3555 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
3556 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
3557 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
3559 #define _MMIO_CHV_SPCSC(plane_id, reg) \
3560 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
3562 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
3563 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
3564 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
3565 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
3566 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
3567 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
3568 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
3570 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
3571 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
3572 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
3573 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
3574 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
3575 #define SPCSC_C1_MASK REG_GENMASK(30, 16)
3576 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
3577 #define SPCSC_C0_MASK REG_GENMASK(14, 0)
3578 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
3580 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
3581 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
3582 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
3583 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
3584 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
3585 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
3586 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
3588 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
3589 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
3590 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
3591 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
3592 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
3593 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
3594 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
3596 /* Skylake plane registers */
3598 #define _PLANE_CTL_1_A 0x70180
3599 #define _PLANE_CTL_2_A 0x70280
3600 #define _PLANE_CTL_3_A 0x70380
3601 #define PLANE_CTL_ENABLE REG_BIT(31)
3602 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
3603 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
3604 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
3605 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3607 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
3608 * expanded to include bit 23 as well. However, the shift-24 based values
3609 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
3611 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
3612 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
3613 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
3614 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
3615 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
3616 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
3617 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
3618 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
3619 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
3620 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
3621 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
3622 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
3623 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
3624 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
3625 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
3626 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
3627 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
3628 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
3629 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
3630 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
3631 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
3632 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
3633 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
3634 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
3635 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
3636 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
3637 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
3638 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
3639 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
3640 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
3641 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
3642 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
3643 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
3644 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
3645 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
3646 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
3647 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
3648 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
3649 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
3650 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
3651 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
3652 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
3653 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
3654 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
3655 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
3656 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
3657 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
3658 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
3659 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
3660 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
3661 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
3662 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
3663 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
3664 #define _PLANE_STRIDE_1_A 0x70188
3665 #define _PLANE_STRIDE_2_A 0x70288
3666 #define _PLANE_STRIDE_3_A 0x70388
3667 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
3668 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
3669 #define _PLANE_POS_1_A 0x7018c
3670 #define _PLANE_POS_2_A 0x7028c
3671 #define _PLANE_POS_3_A 0x7038c
3672 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
3673 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
3674 #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
3675 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
3676 #define _PLANE_SIZE_1_A 0x70190
3677 #define _PLANE_SIZE_2_A 0x70290
3678 #define _PLANE_SIZE_3_A 0x70390
3679 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
3680 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
3681 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
3682 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
3683 #define _PLANE_SURF_1_A 0x7019c
3684 #define _PLANE_SURF_2_A 0x7029c
3685 #define _PLANE_SURF_3_A 0x7039c
3686 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
3687 #define PLANE_SURF_DECRYPT REG_BIT(2)
3688 #define _PLANE_OFFSET_1_A 0x701a4
3689 #define _PLANE_OFFSET_2_A 0x702a4
3690 #define _PLANE_OFFSET_3_A 0x703a4
3691 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
3692 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
3693 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
3694 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
3695 #define _PLANE_KEYVAL_1_A 0x70194
3696 #define _PLANE_KEYVAL_2_A 0x70294
3697 #define _PLANE_KEYMSK_1_A 0x70198
3698 #define _PLANE_KEYMSK_2_A 0x70298
3699 #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
3700 #define _PLANE_KEYMAX_1_A 0x701a0
3701 #define _PLANE_KEYMAX_2_A 0x702a0
3702 #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
3703 #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
3704 #define _PLANE_SURFLIVE_1_A 0x701ac
3705 #define _PLANE_SURFLIVE_2_A 0x702ac
3706 #define _PLANE_CC_VAL_1_A 0x701b4
3707 #define _PLANE_CC_VAL_2_A 0x702b4
3708 #define _PLANE_AUX_DIST_1_A 0x701c0
3709 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
3710 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
3711 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
3712 #define _PLANE_AUX_DIST_2_A 0x702c0
3713 #define _PLANE_AUX_OFFSET_1_A 0x701c4
3714 #define _PLANE_AUX_OFFSET_2_A 0x702c4
3715 #define _PLANE_CUS_CTL_1_A 0x701c8
3716 #define _PLANE_CUS_CTL_2_A 0x702c8
3717 #define PLANE_CUS_ENABLE REG_BIT(31)
3718 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
3719 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3720 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
3721 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3722 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
3723 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
3724 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
3725 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
3726 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
3727 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
3728 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
3729 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
3730 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
3731 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
3732 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
3733 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
3734 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
3735 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
3736 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
3737 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3738 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
3739 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
3740 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
3741 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
3742 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
3743 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
3744 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
3745 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
3746 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
3747 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
3748 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
3749 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
3750 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
3751 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
3752 #define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
3753 #define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
3754 #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
3755 #define _PLANE_BUF_CFG_1_A 0x7027c
3756 #define _PLANE_BUF_CFG_2_A 0x7037c
3757 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
3758 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
3759 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
3760 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
3761 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
3762 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
3763 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
3765 #define _PLANE_CC_VAL_1_B 0x711b4
3766 #define _PLANE_CC_VAL_2_B 0x712b4
3767 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
3768 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
3769 #define PLANE_CC_VAL(pipe, plane, dw) \
3770 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
3772 /* Input CSC Register Definitions */
3773 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
3774 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
3776 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
3777 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
3779 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
3780 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
3781 _PLANE_INPUT_CSC_RY_GY_1_B)
3782 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
3783 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
3784 _PLANE_INPUT_CSC_RY_GY_2_B)
3786 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
3787 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
3788 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
3790 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
3791 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
3793 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
3794 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
3796 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
3797 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
3798 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
3799 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
3800 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
3801 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
3802 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
3803 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
3804 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
3806 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
3807 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
3809 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
3810 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
3812 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
3813 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
3814 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
3815 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
3816 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
3817 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
3818 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
3819 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
3820 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
3822 #define _PLANE_CTL_1_B 0x71180
3823 #define _PLANE_CTL_2_B 0x71280
3824 #define _PLANE_CTL_3_B 0x71380
3825 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
3826 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
3827 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
3828 #define PLANE_CTL(pipe, plane) \
3829 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
3831 #define _PLANE_STRIDE_1_B 0x71188
3832 #define _PLANE_STRIDE_2_B 0x71288
3833 #define _PLANE_STRIDE_3_B 0x71388
3834 #define _PLANE_STRIDE_1(pipe) \
3835 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
3836 #define _PLANE_STRIDE_2(pipe) \
3837 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
3838 #define _PLANE_STRIDE_3(pipe) \
3839 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
3840 #define PLANE_STRIDE(pipe, plane) \
3841 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
3843 #define _PLANE_POS_1_B 0x7118c
3844 #define _PLANE_POS_2_B 0x7128c
3845 #define _PLANE_POS_3_B 0x7138c
3846 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
3847 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
3848 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
3849 #define PLANE_POS(pipe, plane) \
3850 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
3852 #define _PLANE_SIZE_1_B 0x71190
3853 #define _PLANE_SIZE_2_B 0x71290
3854 #define _PLANE_SIZE_3_B 0x71390
3855 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
3856 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
3857 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
3858 #define PLANE_SIZE(pipe, plane) \
3859 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
3861 #define _PLANE_SURF_1_B 0x7119c
3862 #define _PLANE_SURF_2_B 0x7129c
3863 #define _PLANE_SURF_3_B 0x7139c
3864 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
3865 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
3866 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
3867 #define PLANE_SURF(pipe, plane) \
3868 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
3870 #define _PLANE_OFFSET_1_B 0x711a4
3871 #define _PLANE_OFFSET_2_B 0x712a4
3872 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
3873 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
3874 #define PLANE_OFFSET(pipe, plane) \
3875 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
3877 #define _PLANE_KEYVAL_1_B 0x71194
3878 #define _PLANE_KEYVAL_2_B 0x71294
3879 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
3880 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
3881 #define PLANE_KEYVAL(pipe, plane) \
3882 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
3884 #define _PLANE_KEYMSK_1_B 0x71198
3885 #define _PLANE_KEYMSK_2_B 0x71298
3886 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
3887 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
3888 #define PLANE_KEYMSK(pipe, plane) \
3889 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
3891 #define _PLANE_KEYMAX_1_B 0x711a0
3892 #define _PLANE_KEYMAX_2_B 0x712a0
3893 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
3894 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
3895 #define PLANE_KEYMAX(pipe, plane) \
3896 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
3898 #define _PLANE_SURFLIVE_1_B 0x711ac
3899 #define _PLANE_SURFLIVE_2_B 0x712ac
3900 #define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
3901 #define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
3902 #define PLANE_SURFLIVE(pipe, plane) \
3903 _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
3905 #define _PLANE_CHICKEN_1_B 0x7126c
3906 #define _PLANE_CHICKEN_2_B 0x7136c
3907 #define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
3908 #define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
3909 #define PLANE_CHICKEN(pipe, plane) \
3910 _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
3912 #define _PLANE_AUX_DIST_1_B 0x711c0
3913 #define _PLANE_AUX_DIST_2_B 0x712c0
3914 #define _PLANE_AUX_DIST_1(pipe) \
3915 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
3916 #define _PLANE_AUX_DIST_2(pipe) \
3917 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
3918 #define PLANE_AUX_DIST(pipe, plane) \
3919 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
3921 #define _PLANE_AUX_OFFSET_1_B 0x711c4
3922 #define _PLANE_AUX_OFFSET_2_B 0x712c4
3923 #define _PLANE_AUX_OFFSET_1(pipe) \
3924 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
3925 #define _PLANE_AUX_OFFSET_2(pipe) \
3926 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
3927 #define PLANE_AUX_OFFSET(pipe, plane) \
3928 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
3930 #define _PLANE_CUS_CTL_1_B 0x711c8
3931 #define _PLANE_CUS_CTL_2_B 0x712c8
3932 #define _PLANE_CUS_CTL_1(pipe) \
3933 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
3934 #define _PLANE_CUS_CTL_2(pipe) \
3935 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
3936 #define PLANE_CUS_CTL(pipe, plane) \
3937 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
3939 #define _PLANE_COLOR_CTL_1_B 0x711CC
3940 #define _PLANE_COLOR_CTL_2_B 0x712CC
3941 #define _PLANE_COLOR_CTL_3_B 0x713CC
3942 #define _PLANE_COLOR_CTL_1(pipe) \
3943 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
3944 #define _PLANE_COLOR_CTL_2(pipe) \
3945 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
3946 #define PLANE_COLOR_CTL(pipe, plane) \
3947 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
3950 #define VGACNTRL _MMIO(0x71400)
3951 # define VGA_DISP_DISABLE (1 << 31)
3952 # define VGA_2X_MODE (1 << 30)
3953 # define VGA_PIPE_B_SELECT (1 << 29)
3955 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
3959 #define CPU_VGACNTRL _MMIO(0x41000)
3961 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
3962 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3963 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
3964 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
3965 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
3966 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
3967 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
3968 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
3969 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
3970 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
3971 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
3973 /* refresh rate hardware control */
3974 #define RR_HW_CTL _MMIO(0x45300)
3975 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3976 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3978 #define PCH_3DCGDIS0 _MMIO(0x46020)
3979 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3980 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3982 #define PCH_3DCGDIS1 _MMIO(0x46024)
3983 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3985 #define _PIPEA_DATA_M1 0x60030
3986 #define _PIPEA_DATA_N1 0x60034
3987 #define _PIPEA_DATA_M2 0x60038
3988 #define _PIPEA_DATA_N2 0x6003c
3989 #define _PIPEA_LINK_M1 0x60040
3990 #define _PIPEA_LINK_N1 0x60044
3991 #define _PIPEA_LINK_M2 0x60048
3992 #define _PIPEA_LINK_N2 0x6004c
3994 /* PIPEB timing regs are same start from 0x61000 */
3996 #define _PIPEB_DATA_M1 0x61030
3997 #define _PIPEB_DATA_N1 0x61034
3998 #define _PIPEB_DATA_M2 0x61038
3999 #define _PIPEB_DATA_N2 0x6103c
4000 #define _PIPEB_LINK_M1 0x61040
4001 #define _PIPEB_LINK_N1 0x61044
4002 #define _PIPEB_LINK_M2 0x61048
4003 #define _PIPEB_LINK_N2 0x6104c
4005 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
4006 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
4007 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
4008 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
4009 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
4010 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
4011 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
4012 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
4014 /* CPU panel fitter */
4015 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4016 #define _PFA_CTL_1 0x68080
4017 #define _PFB_CTL_1 0x68880
4018 #define PF_ENABLE REG_BIT(31)
4019 #define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
4020 #define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
4021 #define PF_FILTER_MASK REG_GENMASK(24, 23)
4022 #define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
4023 #define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
4024 #define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
4025 #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
4026 #define _PFA_WIN_SZ 0x68074
4027 #define _PFB_WIN_SZ 0x68874
4028 #define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
4029 #define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
4030 #define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
4031 #define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
4032 #define _PFA_WIN_POS 0x68070
4033 #define _PFB_WIN_POS 0x68870
4034 #define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
4035 #define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
4036 #define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
4037 #define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
4038 #define _PFA_VSCALE 0x68084
4039 #define _PFB_VSCALE 0x68884
4040 #define _PFA_HSCALE 0x68090
4041 #define _PFB_HSCALE 0x68890
4043 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4044 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4045 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4046 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4047 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4052 #define _PS_1A_CTRL 0x68180
4053 #define _PS_2A_CTRL 0x68280
4054 #define _PS_1B_CTRL 0x68980
4055 #define _PS_2B_CTRL 0x68A80
4056 #define _PS_1C_CTRL 0x69180
4057 #define PS_SCALER_EN REG_BIT(31)
4058 #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
4059 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
4060 #define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
4061 #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
4062 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
4063 #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
4064 #define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
4065 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
4066 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
4067 #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
4068 #define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
4069 #define PS_BINDING_MASK REG_GENMASK(27, 25)
4070 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
4071 #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
4072 #define PS_FILTER_MASK REG_GENMASK(24, 23)
4073 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
4074 #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
4075 #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
4076 #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
4077 #define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
4078 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
4079 #define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
4080 #define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
4081 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
4082 #define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
4083 #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
4084 #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
4085 #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
4086 #define PS_PWRUP_PROGRESS REG_BIT(17)
4087 #define PS_V_FILTER_BYPASS REG_BIT(8)
4088 #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
4089 #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
4090 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
4091 #define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
4092 #define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
4093 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
4094 #define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
4095 #define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
4096 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
4097 #define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
4098 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
4099 #define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
4100 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
4101 #define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
4102 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
4104 #define _PS_PWR_GATE_1A 0x68160
4105 #define _PS_PWR_GATE_2A 0x68260
4106 #define _PS_PWR_GATE_1B 0x68960
4107 #define _PS_PWR_GATE_2B 0x68A60
4108 #define _PS_PWR_GATE_1C 0x69160
4109 #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
4110 #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
4111 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
4112 #define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
4113 #define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
4114 #define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
4115 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
4116 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
4117 #define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
4118 #define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
4119 #define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
4121 #define _PS_WIN_POS_1A 0x68170
4122 #define _PS_WIN_POS_2A 0x68270
4123 #define _PS_WIN_POS_1B 0x68970
4124 #define _PS_WIN_POS_2B 0x68A70
4125 #define _PS_WIN_POS_1C 0x69170
4126 #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
4127 #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
4128 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
4129 #define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
4131 #define _PS_WIN_SZ_1A 0x68174
4132 #define _PS_WIN_SZ_2A 0x68274
4133 #define _PS_WIN_SZ_1B 0x68974
4134 #define _PS_WIN_SZ_2B 0x68A74
4135 #define _PS_WIN_SZ_1C 0x69174
4136 #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
4137 #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
4138 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
4139 #define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
4141 #define _PS_VSCALE_1A 0x68184
4142 #define _PS_VSCALE_2A 0x68284
4143 #define _PS_VSCALE_1B 0x68984
4144 #define _PS_VSCALE_2B 0x68A84
4145 #define _PS_VSCALE_1C 0x69184
4147 #define _PS_HSCALE_1A 0x68190
4148 #define _PS_HSCALE_2A 0x68290
4149 #define _PS_HSCALE_1B 0x68990
4150 #define _PS_HSCALE_2B 0x68A90
4151 #define _PS_HSCALE_1C 0x69190
4153 #define _PS_VPHASE_1A 0x68188
4154 #define _PS_VPHASE_2A 0x68288
4155 #define _PS_VPHASE_1B 0x68988
4156 #define _PS_VPHASE_2B 0x68A88
4157 #define _PS_VPHASE_1C 0x69188
4158 #define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
4159 #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
4160 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
4161 #define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
4162 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
4163 #define PS_PHASE_TRIP (1 << 0)
4165 #define _PS_HPHASE_1A 0x68194
4166 #define _PS_HPHASE_2A 0x68294
4167 #define _PS_HPHASE_1B 0x68994
4168 #define _PS_HPHASE_2B 0x68A94
4169 #define _PS_HPHASE_1C 0x69194
4171 #define _PS_ECC_STAT_1A 0x681D0
4172 #define _PS_ECC_STAT_2A 0x682D0
4173 #define _PS_ECC_STAT_1B 0x689D0
4174 #define _PS_ECC_STAT_2B 0x68AD0
4175 #define _PS_ECC_STAT_1C 0x691D0
4177 #define _PS_COEF_SET0_INDEX_1A 0x68198
4178 #define _PS_COEF_SET0_INDEX_2A 0x68298
4179 #define _PS_COEF_SET0_INDEX_1B 0x68998
4180 #define _PS_COEF_SET0_INDEX_2B 0x68A98
4181 #define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
4183 #define _PS_COEF_SET0_DATA_1A 0x6819C
4184 #define _PS_COEF_SET0_DATA_2A 0x6829C
4185 #define _PS_COEF_SET0_DATA_1B 0x6899C
4186 #define _PS_COEF_SET0_DATA_2B 0x68A9C
4188 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
4189 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
4190 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
4191 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
4192 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
4193 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
4194 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
4195 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
4196 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
4197 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
4198 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
4199 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
4200 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
4201 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
4202 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
4203 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
4204 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
4205 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
4206 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
4207 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
4208 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
4209 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
4210 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
4211 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
4212 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
4213 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
4214 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
4215 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
4216 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4217 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
4218 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
4220 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4221 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
4222 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
4223 /* legacy palette */
4224 #define _LGC_PALETTE_A 0x4a000
4225 #define _LGC_PALETTE_B 0x4a800
4226 /* see PALETTE_* for the bits */
4227 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
4229 /* ilk/snb precision palette */
4230 #define _PREC_PALETTE_A 0x4b000
4231 #define _PREC_PALETTE_B 0x4c000
4233 #define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20)
4234 #define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10)
4235 #define PREC_PALETTE_10_BLUE_MASK REG_GENMASK(9, 0)
4236 /* 12.4 interpolated mode ldw */
4237 #define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24)
4238 #define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14)
4239 #define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4)
4240 /* 12.4 interpolated mode udw */
4241 #define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20)
4242 #define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10)
4243 #define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0)
4244 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
4246 #define _PREC_PIPEAGCMAX 0x4d000
4247 #define _PREC_PIPEBGCMAX 0x4d010
4248 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */
4250 #define _GAMMA_MODE_A 0x4a480
4251 #define _GAMMA_MODE_B 0x4ac80
4252 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4253 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
4254 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
4255 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
4256 #define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0)
4257 #define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
4258 #define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)
4259 #define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)
4260 #define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
4261 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
4263 /* Display Internal Timeout Register */
4264 #define RM_TIMEOUT _MMIO(0x42060)
4265 #define MMIO_TIMEOUT_US(us) ((us) << 0)
4268 #define DE_MASTER_IRQ_CONTROL (1 << 31)
4269 #define DE_SPRITEB_FLIP_DONE (1 << 29)
4270 #define DE_SPRITEA_FLIP_DONE (1 << 28)
4271 #define DE_PLANEB_FLIP_DONE (1 << 27)
4272 #define DE_PLANEA_FLIP_DONE (1 << 26)
4273 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
4274 #define DE_PCU_EVENT (1 << 25)
4275 #define DE_GTT_FAULT (1 << 24)
4276 #define DE_POISON (1 << 23)
4277 #define DE_PERFORM_COUNTER (1 << 22)
4278 #define DE_PCH_EVENT (1 << 21)
4279 #define DE_AUX_CHANNEL_A (1 << 20)
4280 #define DE_DP_A_HOTPLUG (1 << 19)
4281 #define DE_GSE (1 << 18)
4282 #define DE_PIPEB_VBLANK (1 << 15)
4283 #define DE_PIPEB_EVEN_FIELD (1 << 14)
4284 #define DE_PIPEB_ODD_FIELD (1 << 13)
4285 #define DE_PIPEB_LINE_COMPARE (1 << 12)
4286 #define DE_PIPEB_VSYNC (1 << 11)
4287 #define DE_PIPEB_CRC_DONE (1 << 10)
4288 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4289 #define DE_PIPEA_VBLANK (1 << 7)
4290 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
4291 #define DE_PIPEA_EVEN_FIELD (1 << 6)
4292 #define DE_PIPEA_ODD_FIELD (1 << 5)
4293 #define DE_PIPEA_LINE_COMPARE (1 << 4)
4294 #define DE_PIPEA_VSYNC (1 << 3)
4295 #define DE_PIPEA_CRC_DONE (1 << 2)
4296 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
4297 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
4298 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
4300 /* More Ivybridge lolz */
4301 #define DE_ERR_INT_IVB (1 << 30)
4302 #define DE_GSE_IVB (1 << 29)
4303 #define DE_PCH_EVENT_IVB (1 << 28)
4304 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
4305 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
4306 #define DE_EDP_PSR_INT_HSW (1 << 19)
4307 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
4308 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
4309 #define DE_PIPEC_VBLANK_IVB (1 << 10)
4310 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
4311 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
4312 #define DE_PIPEB_VBLANK_IVB (1 << 5)
4313 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
4314 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
4315 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
4316 #define DE_PIPEA_VBLANK_IVB (1 << 0)
4317 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
4319 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
4320 #define MASTER_INTERRUPT_ENABLE (1 << 31)
4322 #define DEISR _MMIO(0x44000)
4323 #define DEIMR _MMIO(0x44004)
4324 #define DEIIR _MMIO(0x44008)
4325 #define DEIER _MMIO(0x4400c)
4327 #define GTISR _MMIO(0x44010)
4328 #define GTIMR _MMIO(0x44014)
4329 #define GTIIR _MMIO(0x44018)
4330 #define GTIER _MMIO(0x4401c)
4332 #define GEN8_MASTER_IRQ _MMIO(0x44200)
4333 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
4334 #define GEN8_PCU_IRQ (1 << 30)
4335 #define GEN8_DE_PCH_IRQ (1 << 23)
4336 #define GEN8_DE_MISC_IRQ (1 << 22)
4337 #define GEN8_DE_PORT_IRQ (1 << 20)
4338 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
4339 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
4340 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
4341 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
4342 #define GEN8_GT_VECS_IRQ (1 << 6)
4343 #define GEN8_GT_GUC_IRQ (1 << 5)
4344 #define GEN8_GT_PM_IRQ (1 << 4)
4345 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
4346 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
4347 #define GEN8_GT_BCS_IRQ (1 << 1)
4348 #define GEN8_GT_RCS_IRQ (1 << 0)
4350 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
4352 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
4353 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
4354 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
4355 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
4357 #define GEN8_RCS_IRQ_SHIFT 0
4358 #define GEN8_BCS_IRQ_SHIFT 16
4359 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
4360 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
4361 #define GEN8_VECS_IRQ_SHIFT 0
4362 #define GEN8_WD_IRQ_SHIFT 16
4364 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
4365 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
4366 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
4367 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
4368 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
4369 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4370 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4371 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
4372 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
4373 #define GEN12_PIPE_VBLANK_UNMOD (1 << 19)
4374 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4375 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4376 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4377 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4378 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
4379 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4380 #define GEN8_PIPE_VSYNC (1 << 1)
4381 #define GEN8_PIPE_VBLANK (1 << 0)
4382 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
4383 #define GEN11_PIPE_PLANE7_FAULT (1 << 22)
4384 #define GEN11_PIPE_PLANE6_FAULT (1 << 21)
4385 #define GEN11_PIPE_PLANE5_FAULT (1 << 20)
4386 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
4387 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
4388 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
4389 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
4390 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
4391 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
4392 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
4393 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
4394 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
4395 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4396 (GEN8_PIPE_CURSOR_FAULT | \
4397 GEN8_PIPE_SPRITE_FAULT | \
4398 GEN8_PIPE_PRIMARY_FAULT)
4399 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
4400 (GEN9_PIPE_CURSOR_FAULT | \
4401 GEN9_PIPE_PLANE4_FAULT | \
4402 GEN9_PIPE_PLANE3_FAULT | \
4403 GEN9_PIPE_PLANE2_FAULT | \
4404 GEN9_PIPE_PLANE1_FAULT)
4405 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
4406 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
4407 GEN11_PIPE_PLANE7_FAULT | \
4408 GEN11_PIPE_PLANE6_FAULT | \
4409 GEN11_PIPE_PLANE5_FAULT)
4410 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
4411 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
4412 GEN11_PIPE_PLANE5_FAULT)
4414 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
4415 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
4417 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
4418 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
4419 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
4420 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
4421 #define DSI1_NON_TE (1 << 31)
4422 #define DSI0_NON_TE (1 << 30)
4423 #define ICL_AUX_CHANNEL_E (1 << 29)
4424 #define ICL_AUX_CHANNEL_F (1 << 28)
4425 #define GEN9_AUX_CHANNEL_D (1 << 27)
4426 #define GEN9_AUX_CHANNEL_C (1 << 26)
4427 #define GEN9_AUX_CHANNEL_B (1 << 25)
4428 #define DSI1_TE (1 << 24)
4429 #define DSI0_TE (1 << 23)
4430 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
4431 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
4432 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
4433 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
4434 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
4435 #define BXT_DE_PORT_GMBUS (1 << 1)
4436 #define GEN8_AUX_CHANNEL_A (1 << 0)
4437 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
4438 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
4439 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
4440 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
4441 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
4442 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
4443 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
4444 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
4445 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
4446 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
4447 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
4449 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
4450 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
4451 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
4452 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
4453 #define GEN8_DE_MISC_GSE (1 << 27)
4454 #define GEN8_DE_EDP_PSR (1 << 19)
4456 #define GEN8_PCU_ISR _MMIO(0x444e0)
4457 #define GEN8_PCU_IMR _MMIO(0x444e4)
4458 #define GEN8_PCU_IIR _MMIO(0x444e8)
4459 #define GEN8_PCU_IER _MMIO(0x444ec)
4461 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
4462 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
4463 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
4464 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
4465 #define GEN11_GU_MISC_GSE (1 << 27)
4467 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
4468 #define GEN11_MASTER_IRQ (1 << 31)
4469 #define GEN11_PCU_IRQ (1 << 30)
4470 #define GEN11_GU_MISC_IRQ (1 << 29)
4471 #define GEN11_DISPLAY_IRQ (1 << 16)
4472 #define GEN11_GT_DW_IRQ(x) (1 << (x))
4473 #define GEN11_GT_DW1_IRQ (1 << 1)
4474 #define GEN11_GT_DW0_IRQ (1 << 0)
4476 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
4477 #define DG1_MSTR_IRQ REG_BIT(31)
4478 #define DG1_MSTR_TILE(t) REG_BIT(t)
4480 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
4481 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
4482 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
4483 #define GEN11_DE_PCH_IRQ (1 << 23)
4484 #define GEN11_DE_MISC_IRQ (1 << 22)
4485 #define GEN11_DE_HPD_IRQ (1 << 21)
4486 #define GEN11_DE_PORT_IRQ (1 << 20)
4487 #define GEN11_DE_PIPE_C (1 << 18)
4488 #define GEN11_DE_PIPE_B (1 << 17)
4489 #define GEN11_DE_PIPE_A (1 << 16)
4491 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
4492 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
4493 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
4494 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
4495 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
4496 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
4497 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
4498 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
4499 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
4500 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
4501 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
4502 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
4503 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
4504 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
4505 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
4506 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
4507 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
4508 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
4510 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
4511 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
4512 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
4513 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
4514 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
4515 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
4517 #define PICAINTERRUPT_ISR _MMIO(0x16FE50)
4518 #define PICAINTERRUPT_IMR _MMIO(0x16FE54)
4519 #define PICAINTERRUPT_IIR _MMIO(0x16FE58)
4520 #define PICAINTERRUPT_IER _MMIO(0x16FE5C)
4522 #define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
4523 #define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
4525 #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
4526 #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
4528 #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
4529 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
4531 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
4532 #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
4533 #define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
4534 #define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
4535 #define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
4536 #define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
4537 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
4539 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
4540 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
4541 #define ILK_ELPIN_409_SELECT REG_BIT(25)
4542 #define ILK_DPARB_GATE REG_BIT(22)
4543 #define ILK_VSDPFD_FULL REG_BIT(21)
4545 #define FUSE_STRAP _MMIO(0x42014)
4546 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
4547 #define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
4548 #define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
4549 #define IVB_PIPE_C_DISABLE REG_BIT(28)
4550 #define ILK_HDCP_DISABLE REG_BIT(25)
4551 #define ILK_eDP_A_DISABLE REG_BIT(24)
4552 #define HSW_CDCLK_LIMIT REG_BIT(24)
4553 #define ILK_DESKTOP REG_BIT(23)
4554 #define HSW_CPU_SSC_ENABLE REG_BIT(21)
4556 #define FUSE_STRAP3 _MMIO(0x42020)
4557 #define HSW_REF_CLK_SELECT REG_BIT(1)
4559 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
4560 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
4561 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
4562 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
4563 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
4564 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
4566 #define IVB_CHICKEN3 _MMIO(0x4200c)
4567 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
4568 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
4570 #define CHICKEN_PAR1_1 _MMIO(0x42080)
4571 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
4572 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
4573 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
4574 #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
4575 #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
4576 #define FORCE_ARB_IDLE_PLANES REG_BIT(14)
4577 #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
4578 #define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
4580 #define CHICKEN_PAR2_1 _MMIO(0x42090)
4581 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
4583 #define CHICKEN_MISC_2 _MMIO(0x42084)
4584 #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
4585 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
4586 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
4587 #define GLK_CL2_PWR_DOWN REG_BIT(12)
4588 #define GLK_CL1_PWR_DOWN REG_BIT(11)
4589 #define GLK_CL0_PWR_DOWN REG_BIT(10)
4591 #define CHICKEN_MISC_4 _MMIO(0x4208c)
4592 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
4593 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
4594 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
4596 #define _CHICKEN_PIPESL_1_A 0x420b0
4597 #define _CHICKEN_PIPESL_1_B 0x420b4
4598 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4599 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
4600 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
4601 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
4602 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
4603 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
4604 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
4605 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
4606 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
4607 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
4608 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
4609 #define HSW_FBCQ_DIS REG_BIT(22)
4610 #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
4611 #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
4612 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
4613 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
4614 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
4615 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
4616 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
4617 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
4619 #define _CHICKEN_TRANS_A 0x420c0
4620 #define _CHICKEN_TRANS_B 0x420c4
4621 #define _CHICKEN_TRANS_C 0x420c8
4622 #define _CHICKEN_TRANS_EDP 0x420cc
4623 #define _CHICKEN_TRANS_D 0x420d8
4624 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
4625 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
4626 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
4627 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
4628 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
4629 [TRANSCODER_D] = _CHICKEN_TRANS_D))
4630 #define _MTL_CHICKEN_TRANS_A 0x604e0
4631 #define _MTL_CHICKEN_TRANS_B 0x614e0
4632 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
4633 _MTL_CHICKEN_TRANS_A, \
4634 _MTL_CHICKEN_TRANS_B)
4635 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */
4636 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
4637 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
4638 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
4639 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
4640 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
4641 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
4642 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
4643 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
4644 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
4645 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
4646 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
4647 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
4649 #define DISP_ARB_CTL _MMIO(0x45000)
4650 #define DISP_FBC_MEMORY_WAKE REG_BIT(31)
4651 #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
4652 #define DISP_FBC_WM_DIS REG_BIT(15)
4654 #define DISP_ARB_CTL2 _MMIO(0x45004)
4655 #define DISP_DATA_PARTITION_5_6 REG_BIT(6)
4656 #define DISP_IPC_ENABLE REG_BIT(3)
4658 #define GEN7_MSG_CTL _MMIO(0x45010)
4659 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
4660 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
4662 #define _BW_BUDDY0_CTL 0x45130
4663 #define _BW_BUDDY1_CTL 0x45140
4664 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
4667 #define BW_BUDDY_DISABLE REG_BIT(31)
4668 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
4669 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
4671 #define _BW_BUDDY0_PAGE_MASK 0x45134
4672 #define _BW_BUDDY1_PAGE_MASK 0x45144
4673 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
4674 _BW_BUDDY0_PAGE_MASK, \
4675 _BW_BUDDY1_PAGE_MASK))
4677 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
4678 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
4679 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
4681 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
4682 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
4683 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
4684 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
4685 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
4686 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
4687 #define ICL_DELAY_PMRSP REG_BIT(22)
4688 #define DISABLE_FLR_SRC REG_BIT(15)
4689 #define MASK_WAKEMEM REG_BIT(13)
4690 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
4692 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
4693 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
4694 #define DCPR_MASK_LPMODE REG_BIT(26)
4695 #define DCPR_SEND_RESP_IMM REG_BIT(25)
4696 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
4698 #define SKL_DFSM _MMIO(0x51000)
4699 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
4700 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
4701 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
4702 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
4703 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
4704 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
4705 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
4706 #define ICL_DFSM_DMC_DISABLE (1 << 23)
4707 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
4708 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
4709 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
4710 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
4711 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
4713 #define SKL_DSSM _MMIO(0x51004)
4714 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
4715 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
4716 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
4717 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
4719 #define GMD_ID_DISPLAY _MMIO(0x510a0)
4720 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
4721 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
4722 #define GMD_ID_STEP REG_GENMASK(5, 0)
4725 #define _PIPEA_CHICKEN 0x70038
4726 #define _PIPEB_CHICKEN 0x71038
4727 #define _PIPEC_CHICKEN 0x72038
4728 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
4730 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
4731 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
4732 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
4733 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
4734 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
4738 #define PCH_DISPLAY_BASE 0xc0000u
4740 /* south display engine interrupt: IBX */
4741 #define SDE_AUDIO_POWER_D (1 << 27)
4742 #define SDE_AUDIO_POWER_C (1 << 26)
4743 #define SDE_AUDIO_POWER_B (1 << 25)
4744 #define SDE_AUDIO_POWER_SHIFT (25)
4745 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4746 #define SDE_GMBUS (1 << 24)
4747 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4748 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4749 #define SDE_AUDIO_HDCP_MASK (3 << 22)
4750 #define SDE_AUDIO_TRANSB (1 << 21)
4751 #define SDE_AUDIO_TRANSA (1 << 20)
4752 #define SDE_AUDIO_TRANS_MASK (3 << 20)
4753 #define SDE_POISON (1 << 19)
4755 #define SDE_FDI_RXB (1 << 17)
4756 #define SDE_FDI_RXA (1 << 16)
4757 #define SDE_FDI_MASK (3 << 16)
4758 #define SDE_AUXD (1 << 15)
4759 #define SDE_AUXC (1 << 14)
4760 #define SDE_AUXB (1 << 13)
4761 #define SDE_AUX_MASK (7 << 13)
4763 #define SDE_CRT_HOTPLUG (1 << 11)
4764 #define SDE_PORTD_HOTPLUG (1 << 10)
4765 #define SDE_PORTC_HOTPLUG (1 << 9)
4766 #define SDE_PORTB_HOTPLUG (1 << 8)
4767 #define SDE_SDVOB_HOTPLUG (1 << 6)
4768 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4769 SDE_SDVOB_HOTPLUG | \
4770 SDE_PORTB_HOTPLUG | \
4771 SDE_PORTC_HOTPLUG | \
4773 #define SDE_TRANSB_CRC_DONE (1 << 5)
4774 #define SDE_TRANSB_CRC_ERR (1 << 4)
4775 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
4776 #define SDE_TRANSA_CRC_DONE (1 << 2)
4777 #define SDE_TRANSA_CRC_ERR (1 << 1)
4778 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
4779 #define SDE_TRANS_MASK (0x3f)
4781 /* south display engine interrupt: CPT - CNP */
4782 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
4783 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
4784 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
4785 #define SDE_AUDIO_POWER_SHIFT_CPT 29
4786 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4787 #define SDE_AUXD_CPT (1 << 27)
4788 #define SDE_AUXC_CPT (1 << 26)
4789 #define SDE_AUXB_CPT (1 << 25)
4790 #define SDE_AUX_MASK_CPT (7 << 25)
4791 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
4792 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
4793 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4794 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4795 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
4796 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
4797 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
4798 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
4799 SDE_SDVOB_HOTPLUG_CPT | \
4800 SDE_PORTD_HOTPLUG_CPT | \
4801 SDE_PORTC_HOTPLUG_CPT | \
4802 SDE_PORTB_HOTPLUG_CPT)
4803 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
4804 SDE_PORTD_HOTPLUG_CPT | \
4805 SDE_PORTC_HOTPLUG_CPT | \
4806 SDE_PORTB_HOTPLUG_CPT | \
4807 SDE_PORTA_HOTPLUG_SPT)
4808 #define SDE_GMBUS_CPT (1 << 17)
4809 #define SDE_ERROR_CPT (1 << 16)
4810 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4811 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4812 #define SDE_FDI_RXC_CPT (1 << 8)
4813 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4814 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4815 #define SDE_FDI_RXB_CPT (1 << 4)
4816 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4817 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4818 #define SDE_FDI_RXA_CPT (1 << 0)
4819 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4820 SDE_AUDIO_CP_REQ_B_CPT | \
4821 SDE_AUDIO_CP_REQ_A_CPT)
4822 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4823 SDE_AUDIO_CP_CHG_B_CPT | \
4824 SDE_AUDIO_CP_CHG_A_CPT)
4825 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4829 /* south display engine interrupt: ICP/TGP/MTP */
4830 #define SDE_PICAINTERRUPT REG_BIT(31)
4831 #define SDE_GMBUS_ICP (1 << 23)
4832 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
4833 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
4834 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
4835 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
4836 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
4837 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
4838 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
4839 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
4840 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
4841 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
4842 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
4843 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
4844 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
4846 #define SDEISR _MMIO(0xc4000)
4847 #define SDEIMR _MMIO(0xc4004)
4848 #define SDEIIR _MMIO(0xc4008)
4849 #define SDEIER _MMIO(0xc400c)
4851 #define SERR_INT _MMIO(0xc4040)
4852 #define SERR_INT_POISON (1 << 31)
4853 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
4855 /* digital port hotplug */
4856 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
4857 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
4858 #define BXT_DDIA_HPD_INVERT (1 << 27)
4859 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
4860 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
4861 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
4862 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
4863 #define PORTD_HOTPLUG_ENABLE (1 << 20)
4864 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
4865 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
4866 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
4867 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
4868 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
4869 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
4870 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4871 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4872 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
4873 #define PORTC_HOTPLUG_ENABLE (1 << 12)
4874 #define BXT_DDIC_HPD_INVERT (1 << 11)
4875 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
4876 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
4877 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
4878 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
4879 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
4880 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
4881 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4882 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4883 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
4884 #define PORTB_HOTPLUG_ENABLE (1 << 4)
4885 #define BXT_DDIB_HPD_INVERT (1 << 3)
4886 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
4887 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
4888 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
4889 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
4890 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
4891 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
4892 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4893 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4894 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
4895 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
4896 BXT_DDIB_HPD_INVERT | \
4897 BXT_DDIC_HPD_INVERT)
4899 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
4900 #define PORTE_HOTPLUG_ENABLE (1 << 4)
4901 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
4902 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
4903 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
4904 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
4906 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
4907 * functionality covered in PCH_PORT_HOTPLUG is split into
4908 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
4911 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
4912 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
4913 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
4914 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4915 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
4916 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
4917 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
4918 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4920 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
4921 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
4922 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
4923 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
4925 #define SHPD_FILTER_CNT _MMIO(0xc4038)
4926 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
4928 #define _PCH_DPLL_A 0xc6014
4929 #define _PCH_DPLL_B 0xc6018
4930 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4932 #define _PCH_FPA0 0xc6040
4933 #define FP_CB_TUNE (0x3 << 22)
4934 #define _PCH_FPA1 0xc6044
4935 #define _PCH_FPB0 0xc6048
4936 #define _PCH_FPB1 0xc604c
4937 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
4938 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
4940 #define PCH_DPLL_TEST _MMIO(0xc606c)
4942 #define PCH_DREF_CONTROL _MMIO(0xC6200)
4943 #define DREF_CONTROL_MASK 0x7fc3
4944 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
4945 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
4946 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
4947 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
4948 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
4949 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
4950 #define DREF_SSC_SOURCE_MASK (3 << 11)
4951 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
4952 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
4953 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
4954 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
4955 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
4956 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
4957 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
4958 #define DREF_SSC4_DOWNSPREAD (0 << 6)
4959 #define DREF_SSC4_CENTERSPREAD (1 << 6)
4960 #define DREF_SSC1_DISABLE (0 << 1)
4961 #define DREF_SSC1_ENABLE (1 << 1)
4962 #define DREF_SSC4_DISABLE (0)
4963 #define DREF_SSC4_ENABLE (1)
4965 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
4966 #define FDL_TP1_TIMER_SHIFT 12
4967 #define FDL_TP1_TIMER_MASK (3 << 12)
4968 #define FDL_TP2_TIMER_SHIFT 10
4969 #define FDL_TP2_TIMER_MASK (3 << 10)
4970 #define RAWCLK_FREQ_MASK 0x3ff
4971 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
4972 #define CNP_RAWCLK_DIV(div) ((div) << 16)
4973 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
4974 #define CNP_RAWCLK_DEN(den) ((den) << 26)
4975 #define ICP_RAWCLK_NUM(num) ((num) << 11)
4977 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
4979 #define PCH_SSC4_PARMS _MMIO(0xc6210)
4980 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
4982 #define PCH_DPLL_SEL _MMIO(0xc7000)
4983 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
4984 #define TRANS_DPLLA_SEL(pipe) 0
4985 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
4989 #define _PCH_TRANS_HTOTAL_A 0xe0000
4990 #define TRANS_HTOTAL_SHIFT 16
4991 #define TRANS_HACTIVE_SHIFT 0
4992 #define _PCH_TRANS_HBLANK_A 0xe0004
4993 #define TRANS_HBLANK_END_SHIFT 16
4994 #define TRANS_HBLANK_START_SHIFT 0
4995 #define _PCH_TRANS_HSYNC_A 0xe0008
4996 #define TRANS_HSYNC_END_SHIFT 16
4997 #define TRANS_HSYNC_START_SHIFT 0
4998 #define _PCH_TRANS_VTOTAL_A 0xe000c
4999 #define TRANS_VTOTAL_SHIFT 16
5000 #define TRANS_VACTIVE_SHIFT 0
5001 #define _PCH_TRANS_VBLANK_A 0xe0010
5002 #define TRANS_VBLANK_END_SHIFT 16
5003 #define TRANS_VBLANK_START_SHIFT 0
5004 #define _PCH_TRANS_VSYNC_A 0xe0014
5005 #define TRANS_VSYNC_END_SHIFT 16
5006 #define TRANS_VSYNC_START_SHIFT 0
5007 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
5009 #define _PCH_TRANSA_DATA_M1 0xe0030
5010 #define _PCH_TRANSA_DATA_N1 0xe0034
5011 #define _PCH_TRANSA_DATA_M2 0xe0038
5012 #define _PCH_TRANSA_DATA_N2 0xe003c
5013 #define _PCH_TRANSA_LINK_M1 0xe0040
5014 #define _PCH_TRANSA_LINK_N1 0xe0044
5015 #define _PCH_TRANSA_LINK_M2 0xe0048
5016 #define _PCH_TRANSA_LINK_N2 0xe004c
5018 /* Per-transcoder DIP controls (PCH) */
5019 #define _VIDEO_DIP_CTL_A 0xe0200
5020 #define _VIDEO_DIP_DATA_A 0xe0208
5021 #define _VIDEO_DIP_GCP_A 0xe0210
5022 #define GCP_COLOR_INDICATION (1 << 2)
5023 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
5024 #define GCP_AV_MUTE (1 << 0)
5026 #define _VIDEO_DIP_CTL_B 0xe1200
5027 #define _VIDEO_DIP_DATA_B 0xe1208
5028 #define _VIDEO_DIP_GCP_B 0xe1210
5030 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5031 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5032 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5034 /* Per-transcoder DIP controls (VLV) */
5035 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5036 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5037 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
5039 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5040 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5041 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
5043 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5044 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5045 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5047 #define VLV_TVIDEO_DIP_CTL(pipe) \
5048 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
5049 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
5050 #define VLV_TVIDEO_DIP_DATA(pipe) \
5051 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
5052 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
5053 #define VLV_TVIDEO_DIP_GCP(pipe) \
5054 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5055 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
5057 /* Haswell DIP controls */
5059 #define _HSW_VIDEO_DIP_CTL_A 0x60200
5060 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5061 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
5062 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5063 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5064 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5065 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
5066 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5067 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
5068 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5069 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5070 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5071 #define _HSW_VIDEO_DIP_GCP_A 0x60210
5073 #define _HSW_VIDEO_DIP_CTL_B 0x61200
5074 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5075 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
5076 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5077 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5078 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5079 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
5080 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5081 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
5082 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5083 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5084 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5085 #define _HSW_VIDEO_DIP_GCP_B 0x61210
5087 /* Icelake PPS_DATA and _ECC DIP Registers.
5088 * These are available for transcoders B,C and eDP.
5089 * Adding the _A so as to reuse the _MMIO_TRANS2
5090 * definition, with which it offsets to the right location.
5093 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
5094 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
5095 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
5096 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
5098 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
5099 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
5100 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
5101 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
5102 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
5103 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
5104 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
5105 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
5106 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
5107 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
5109 #define _HSW_STEREO_3D_CTL_A 0x70020
5110 #define S3D_ENABLE (1 << 31)
5111 #define _HSW_STEREO_3D_CTL_B 0x71020
5113 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
5115 #define _PCH_TRANS_HTOTAL_B 0xe1000
5116 #define _PCH_TRANS_HBLANK_B 0xe1004
5117 #define _PCH_TRANS_HSYNC_B 0xe1008
5118 #define _PCH_TRANS_VTOTAL_B 0xe100c
5119 #define _PCH_TRANS_VBLANK_B 0xe1010
5120 #define _PCH_TRANS_VSYNC_B 0xe1014
5121 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
5123 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5124 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5125 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5126 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5127 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5128 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5129 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
5131 #define _PCH_TRANSB_DATA_M1 0xe1030
5132 #define _PCH_TRANSB_DATA_N1 0xe1034
5133 #define _PCH_TRANSB_DATA_M2 0xe1038
5134 #define _PCH_TRANSB_DATA_N2 0xe103c
5135 #define _PCH_TRANSB_LINK_M1 0xe1040
5136 #define _PCH_TRANSB_LINK_N1 0xe1044
5137 #define _PCH_TRANSB_LINK_M2 0xe1048
5138 #define _PCH_TRANSB_LINK_N2 0xe104c
5140 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5141 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5142 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5143 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5144 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5145 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5146 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5147 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
5149 #define _PCH_TRANSACONF 0xf0008
5150 #define _PCH_TRANSBCONF 0xf1008
5151 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5152 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
5153 #define TRANS_ENABLE REG_BIT(31)
5154 #define TRANS_STATE_ENABLE REG_BIT(30)
5155 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
5156 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
5157 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
5158 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
5159 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
5160 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
5161 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
5162 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
5163 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
5164 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
5165 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
5167 #define _TRANSA_CHICKEN1 0xf0060
5168 #define _TRANSB_CHICKEN1 0xf1060
5169 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5170 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
5171 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
5173 #define _TRANSA_CHICKEN2 0xf0064
5174 #define _TRANSB_CHICKEN2 0xf1064
5175 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
5176 #define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
5177 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
5178 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
5179 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
5180 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
5181 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
5183 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
5184 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
5185 #define FDIA_PHASE_SYNC_SHIFT_EN 18
5186 #define INVERT_DDIE_HPD REG_BIT(28)
5187 #define INVERT_DDID_HPD_MTP REG_BIT(27)
5188 #define INVERT_TC4_HPD REG_BIT(26)
5189 #define INVERT_TC3_HPD REG_BIT(25)
5190 #define INVERT_TC2_HPD REG_BIT(24)
5191 #define INVERT_TC1_HPD REG_BIT(23)
5192 #define INVERT_DDID_HPD (1 << 18)
5193 #define INVERT_DDIC_HPD (1 << 17)
5194 #define INVERT_DDIB_HPD (1 << 16)
5195 #define INVERT_DDIA_HPD (1 << 15)
5196 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5197 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5198 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
5199 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
5200 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
5201 #define SBCLK_RUN_REFCLK_DIS (1 << 7)
5202 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
5203 #define SPT_PWM_GRANULARITY (1 << 0)
5204 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
5205 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
5206 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
5207 #define LPT_PWM_GRANULARITY (1 << 5)
5208 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
5210 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
5211 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
5212 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
5213 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
5214 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
5215 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
5216 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
5217 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
5219 #define _PCH_DP_B 0xe4100
5220 #define PCH_DP_B _MMIO(_PCH_DP_B)
5221 #define _PCH_DPB_AUX_CH_CTL 0xe4110
5222 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
5223 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
5224 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
5225 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
5226 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
5228 #define _PCH_DP_C 0xe4200
5229 #define PCH_DP_C _MMIO(_PCH_DP_C)
5230 #define _PCH_DPC_AUX_CH_CTL 0xe4210
5231 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
5232 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
5233 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
5234 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
5235 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
5237 #define _PCH_DP_D 0xe4300
5238 #define PCH_DP_D _MMIO(_PCH_DP_D)
5239 #define _PCH_DPD_AUX_CH_CTL 0xe4310
5240 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
5241 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
5242 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
5243 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
5244 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
5246 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
5247 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5250 #define _TRANS_DP_CTL_A 0xe0300
5251 #define _TRANS_DP_CTL_B 0xe1300
5252 #define _TRANS_DP_CTL_C 0xe2300
5253 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
5254 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
5255 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
5256 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
5257 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
5258 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
5259 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
5260 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
5261 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
5262 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
5263 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
5264 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
5265 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
5266 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
5268 #define _TRANS_DP2_CTL_A 0x600a0
5269 #define _TRANS_DP2_CTL_B 0x610a0
5270 #define _TRANS_DP2_CTL_C 0x620a0
5271 #define _TRANS_DP2_CTL_D 0x630a0
5272 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
5273 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
5274 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
5275 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
5277 #define _TRANS_DP2_VFREQHIGH_A 0x600a4
5278 #define _TRANS_DP2_VFREQHIGH_B 0x610a4
5279 #define _TRANS_DP2_VFREQHIGH_C 0x620a4
5280 #define _TRANS_DP2_VFREQHIGH_D 0x630a4
5281 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
5282 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
5283 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
5285 #define _TRANS_DP2_VFREQLOW_A 0x600a8
5286 #define _TRANS_DP2_VFREQLOW_B 0x610a8
5287 #define _TRANS_DP2_VFREQLOW_C 0x620a8
5288 #define _TRANS_DP2_VFREQLOW_D 0x630a8
5289 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
5291 /* SNB eDP training params */
5292 /* SNB A-stepping */
5293 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
5294 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
5295 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
5296 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
5297 /* SNB B-stepping */
5298 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
5299 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
5300 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
5301 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
5302 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
5303 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
5306 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
5307 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
5308 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
5309 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
5310 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
5311 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
5312 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
5315 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
5316 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
5317 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
5318 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
5319 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
5321 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
5323 #define VLV_PMWGICZ _MMIO(0x1300a4)
5325 #define HSW_EDRAM_CAP _MMIO(0x120010)
5326 #define EDRAM_ENABLED 0x1
5327 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
5328 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
5329 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
5331 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
5332 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
5333 #define PIXEL_OVERLAP_CNT_SHIFT 30
5335 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
5336 #define GEN6_PCODE_READY (1 << 31)
5337 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
5338 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
5339 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
5340 #define GEN6_PCODE_ERROR_MASK 0xFF
5341 #define GEN6_PCODE_SUCCESS 0x0
5342 #define GEN6_PCODE_ILLEGAL_CMD 0x1
5343 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
5344 #define GEN6_PCODE_TIMEOUT 0x3
5345 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
5346 #define GEN7_PCODE_TIMEOUT 0x2
5347 #define GEN7_PCODE_ILLEGAL_DATA 0x3
5348 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
5349 #define GEN11_PCODE_LOCKED 0x6
5350 #define GEN11_PCODE_REJECTED 0x11
5351 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
5352 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
5353 #define GEN6_PCODE_READ_RC6VIDS 0x5
5354 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5355 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
5356 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
5357 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
5358 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
5359 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
5360 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
5361 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
5362 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
5363 #define SKL_PCODE_CDCLK_CONTROL 0x7
5364 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
5365 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
5366 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5367 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
5368 #define GEN6_READ_OC_PARAMS 0xc
5369 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
5370 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
5371 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
5372 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
5373 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
5374 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
5375 #define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
5376 #define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
5377 #define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
5378 #define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
5379 #define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
5380 #define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
5381 #define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
5382 #define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
5383 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
5384 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
5385 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
5386 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
5387 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
5388 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
5389 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
5390 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
5391 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
5392 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
5393 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
5394 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
5395 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
5396 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
5397 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
5398 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
5399 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
5400 #define GEN6_PCODE_READ_D_COMP 0x10
5401 #define GEN6_PCODE_WRITE_D_COMP 0x11
5402 #define ICL_PCODE_EXIT_TCCOLD 0x12
5403 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
5404 #define DISPLAY_IPS_CONTROL 0x19
5405 #define TGL_PCODE_TCCOLD 0x26
5406 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
5407 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
5408 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
5409 /* See also IPS_CTL */
5410 #define IPS_PCODE_CONTROL (1 << 30)
5411 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
5412 #define GEN9_PCODE_SAGV_CONTROL 0x21
5413 #define GEN9_SAGV_DISABLE 0x0
5414 #define GEN9_SAGV_IS_DISABLED 0x1
5415 #define GEN9_SAGV_ENABLE 0x3
5416 #define DG1_PCODE_STATUS 0x7E
5417 #define DG1_UNCORE_GET_INIT_STATUS 0x0
5418 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
5419 #define PCODE_POWER_SETUP 0x7C
5420 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
5421 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
5422 #define POWER_SETUP_I1_WATTS REG_BIT(31)
5423 #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
5424 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
5425 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
5426 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
5427 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
5428 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
5429 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
5430 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
5431 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */
5432 #define PCODE_MBOX_DOMAIN_NONE 0x0
5433 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
5434 #define GEN6_PCODE_DATA _MMIO(0x138128)
5435 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
5436 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
5437 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
5440 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
5441 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
5442 #define GEN7_PARITY_ERROR_VALID (1 << 13)
5443 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
5444 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
5445 #define GEN7_PARITY_ERROR_ROW(reg) \
5446 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5447 #define GEN7_PARITY_ERROR_BANK(reg) \
5448 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5449 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
5450 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5451 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
5453 /* These are the 4 32-bit write offset registers for each stream
5454 * output buffer. It determines the offset from the
5455 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5457 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
5460 * HSW - ICL power wells
5462 * Platforms have up to 3 power well control register sets, each set
5463 * controlling up to 16 power wells via a request/status HW flag tuple:
5464 * - main (HSW_PWR_WELL_CTL[1-4])
5465 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
5466 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
5467 * Each control register set consists of up to 4 registers used by different
5468 * sources that can request a power well to be enabled:
5469 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
5470 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
5471 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
5472 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
5474 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
5475 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
5476 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
5477 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
5478 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
5479 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
5481 /* HSW/BDW power well */
5482 #define HSW_PW_CTL_IDX_GLOBAL 15
5484 /* SKL/BXT/GLK power wells */
5485 #define SKL_PW_CTL_IDX_PW_2 15
5486 #define SKL_PW_CTL_IDX_PW_1 14
5487 #define GLK_PW_CTL_IDX_AUX_C 10
5488 #define GLK_PW_CTL_IDX_AUX_B 9
5489 #define GLK_PW_CTL_IDX_AUX_A 8
5490 #define SKL_PW_CTL_IDX_DDI_D 4
5491 #define SKL_PW_CTL_IDX_DDI_C 3
5492 #define SKL_PW_CTL_IDX_DDI_B 2
5493 #define SKL_PW_CTL_IDX_DDI_A_E 1
5494 #define GLK_PW_CTL_IDX_DDI_A 1
5495 #define SKL_PW_CTL_IDX_MISC_IO 0
5497 /* ICL/TGL - power wells */
5498 #define TGL_PW_CTL_IDX_PW_5 4
5499 #define ICL_PW_CTL_IDX_PW_4 3
5500 #define ICL_PW_CTL_IDX_PW_3 2
5501 #define ICL_PW_CTL_IDX_PW_2 1
5502 #define ICL_PW_CTL_IDX_PW_1 0
5504 /* XE_LPD - power wells */
5505 #define XELPD_PW_CTL_IDX_PW_D 8
5506 #define XELPD_PW_CTL_IDX_PW_C 7
5507 #define XELPD_PW_CTL_IDX_PW_B 6
5508 #define XELPD_PW_CTL_IDX_PW_A 5
5510 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
5511 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
5512 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
5513 #define TGL_PW_CTL_IDX_AUX_TBT6 14
5514 #define TGL_PW_CTL_IDX_AUX_TBT5 13
5515 #define TGL_PW_CTL_IDX_AUX_TBT4 12
5516 #define ICL_PW_CTL_IDX_AUX_TBT4 11
5517 #define TGL_PW_CTL_IDX_AUX_TBT3 11
5518 #define ICL_PW_CTL_IDX_AUX_TBT3 10
5519 #define TGL_PW_CTL_IDX_AUX_TBT2 10
5520 #define ICL_PW_CTL_IDX_AUX_TBT2 9
5521 #define TGL_PW_CTL_IDX_AUX_TBT1 9
5522 #define ICL_PW_CTL_IDX_AUX_TBT1 8
5523 #define TGL_PW_CTL_IDX_AUX_TC6 8
5524 #define XELPD_PW_CTL_IDX_AUX_E 8
5525 #define TGL_PW_CTL_IDX_AUX_TC5 7
5526 #define XELPD_PW_CTL_IDX_AUX_D 7
5527 #define TGL_PW_CTL_IDX_AUX_TC4 6
5528 #define ICL_PW_CTL_IDX_AUX_F 5
5529 #define TGL_PW_CTL_IDX_AUX_TC3 5
5530 #define ICL_PW_CTL_IDX_AUX_E 4
5531 #define TGL_PW_CTL_IDX_AUX_TC2 4
5532 #define ICL_PW_CTL_IDX_AUX_D 3
5533 #define TGL_PW_CTL_IDX_AUX_TC1 3
5534 #define ICL_PW_CTL_IDX_AUX_C 2
5535 #define ICL_PW_CTL_IDX_AUX_B 1
5536 #define ICL_PW_CTL_IDX_AUX_A 0
5538 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
5539 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
5540 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
5541 #define XELPD_PW_CTL_IDX_DDI_E 8
5542 #define TGL_PW_CTL_IDX_DDI_TC6 8
5543 #define XELPD_PW_CTL_IDX_DDI_D 7
5544 #define TGL_PW_CTL_IDX_DDI_TC5 7
5545 #define TGL_PW_CTL_IDX_DDI_TC4 6
5546 #define ICL_PW_CTL_IDX_DDI_F 5
5547 #define TGL_PW_CTL_IDX_DDI_TC3 5
5548 #define ICL_PW_CTL_IDX_DDI_E 4
5549 #define TGL_PW_CTL_IDX_DDI_TC2 4
5550 #define ICL_PW_CTL_IDX_DDI_D 3
5551 #define TGL_PW_CTL_IDX_DDI_TC1 3
5552 #define ICL_PW_CTL_IDX_DDI_C 2
5553 #define ICL_PW_CTL_IDX_DDI_B 1
5554 #define ICL_PW_CTL_IDX_DDI_A 0
5556 /* HSW - power well misc debug registers */
5557 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
5558 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
5559 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
5560 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
5561 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
5563 /* SKL Fuse Status */
5564 enum skl_power_gate {
5572 #define SKL_FUSE_STATUS _MMIO(0x42000)
5573 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
5575 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
5576 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
5578 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
5579 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
5581 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
5582 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
5584 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
5585 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
5586 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
5588 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
5589 #define _ICL_AUX_ANAOVRD1_A 0x162398
5590 #define _ICL_AUX_ANAOVRD1_B 0x6C398
5591 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
5592 _ICL_AUX_ANAOVRD1_A, \
5593 _ICL_AUX_ANAOVRD1_B))
5594 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
5595 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
5597 /* Per-pipe DDI Function Control */
5598 #define _TRANS_DDI_FUNC_CTL_A 0x60400
5599 #define _TRANS_DDI_FUNC_CTL_B 0x61400
5600 #define _TRANS_DDI_FUNC_CTL_C 0x62400
5601 #define _TRANS_DDI_FUNC_CTL_D 0x63400
5602 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
5603 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
5604 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
5605 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
5607 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
5608 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
5609 #define TRANS_DDI_PORT_SHIFT 28
5610 #define TGL_TRANS_DDI_PORT_SHIFT 27
5611 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
5612 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
5613 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
5614 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
5615 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
5616 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
5617 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
5618 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
5619 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
5620 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
5621 #define TRANS_DDI_BPC_MASK (7 << 20)
5622 #define TRANS_DDI_BPC_8 (0 << 20)
5623 #define TRANS_DDI_BPC_10 (1 << 20)
5624 #define TRANS_DDI_BPC_6 (2 << 20)
5625 #define TRANS_DDI_BPC_12 (3 << 20)
5626 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
5627 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
5628 #define TRANS_DDI_PVSYNC (1 << 17)
5629 #define TRANS_DDI_PHSYNC (1 << 16)
5630 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
5631 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
5632 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
5633 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
5634 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
5635 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
5636 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
5637 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
5638 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
5639 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
5640 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
5641 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
5642 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
5643 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
5644 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
5645 #define TRANS_DDI_BFI_ENABLE (1 << 4)
5646 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
5647 #define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
5648 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
5649 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
5650 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
5651 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
5652 | TRANS_DDI_HDMI_SCRAMBLING)
5654 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
5655 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
5656 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
5657 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
5658 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
5659 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
5660 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
5661 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
5662 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
5663 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
5665 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
5666 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
5668 /* DisplayPort Transport Control */
5669 #define _DP_TP_CTL_A 0x64040
5670 #define _DP_TP_CTL_B 0x64140
5671 #define _TGL_DP_TP_CTL_A 0x60540
5672 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
5673 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
5674 #define DP_TP_CTL_ENABLE (1 << 31)
5675 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
5676 #define DP_TP_CTL_MODE_SST (0 << 27)
5677 #define DP_TP_CTL_MODE_MST (1 << 27)
5678 #define DP_TP_CTL_FORCE_ACT (1 << 25)
5679 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
5680 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
5681 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
5682 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
5683 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
5684 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
5685 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
5686 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
5687 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
5688 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
5690 /* DisplayPort Transport Status */
5691 #define _DP_TP_STATUS_A 0x64044
5692 #define _DP_TP_STATUS_B 0x64144
5693 #define _TGL_DP_TP_STATUS_A 0x60544
5694 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
5695 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
5696 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
5697 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
5698 #define DP_TP_STATUS_ACT_SENT (1 << 24)
5699 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
5700 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
5701 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
5702 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
5703 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
5705 /* DDI Buffer Control */
5706 #define _DDI_BUF_CTL_A 0x64000
5707 #define _DDI_BUF_CTL_B 0x64100
5708 /* Known as DDI_CTL_DE in MTL+ */
5709 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
5710 #define DDI_BUF_CTL_ENABLE (1 << 31)
5711 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
5712 #define DDI_BUF_EMP_MASK (0xf << 24)
5713 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
5714 #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
5715 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
5716 #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
5717 #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
5718 #define DDI_BUF_PORT_REVERSAL (1 << 16)
5719 #define DDI_BUF_IS_IDLE (1 << 7)
5720 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
5721 #define DDI_A_4_LANES (1 << 4)
5722 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
5723 #define DDI_PORT_WIDTH_MASK (7 << 1)
5724 #define DDI_PORT_WIDTH_SHIFT 1
5725 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
5727 /* DDI Buffer Translations */
5728 #define _DDI_BUF_TRANS_A 0x64E00
5729 #define _DDI_BUF_TRANS_B 0x64E60
5730 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
5731 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
5732 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
5734 /* DDI DP Compliance Control */
5735 #define _DDI_DP_COMP_CTL_A 0x605F0
5736 #define _DDI_DP_COMP_CTL_B 0x615F0
5737 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
5738 #define DDI_DP_COMP_CTL_ENABLE (1 << 31)
5739 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
5740 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
5741 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
5742 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
5743 #define DDI_DP_COMP_CTL_HBR2 (4 << 28)
5744 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
5745 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
5747 /* DDI DP Compliance Pattern */
5748 #define _DDI_DP_COMP_PAT_A 0x605F4
5749 #define _DDI_DP_COMP_PAT_B 0x615F4
5750 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
5752 /* Sideband Interface (SBI) is programmed indirectly, via
5753 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5754 * which contains the payload */
5755 #define SBI_ADDR _MMIO(0xC6000)
5756 #define SBI_DATA _MMIO(0xC6004)
5757 #define SBI_CTL_STAT _MMIO(0xC6008)
5758 #define SBI_CTL_DEST_ICLK (0x0 << 16)
5759 #define SBI_CTL_DEST_MPHY (0x1 << 16)
5760 #define SBI_CTL_OP_IORD (0x2 << 8)
5761 #define SBI_CTL_OP_IOWR (0x3 << 8)
5762 #define SBI_CTL_OP_CRRD (0x6 << 8)
5763 #define SBI_CTL_OP_CRWR (0x7 << 8)
5764 #define SBI_RESPONSE_FAIL (0x1 << 1)
5765 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
5766 #define SBI_BUSY (0x1 << 0)
5767 #define SBI_READY (0x0 << 0)
5770 #define SBI_SSCDIVINTPHASE 0x0200
5771 #define SBI_SSCDIVINTPHASE6 0x0600
5772 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
5773 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
5774 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
5775 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
5776 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
5777 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
5778 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
5779 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
5780 #define SBI_SSCDITHPHASE 0x0204
5781 #define SBI_SSCCTL 0x020c
5782 #define SBI_SSCCTL6 0x060C
5783 #define SBI_SSCCTL_PATHALT (1 << 3)
5784 #define SBI_SSCCTL_DISABLE (1 << 0)
5785 #define SBI_SSCAUXDIV6 0x0610
5786 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
5787 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
5788 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
5789 #define SBI_DBUFF0 0x2a00
5790 #define SBI_GEN0 0x1f00
5791 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
5793 /* LPT PIXCLK_GATE */
5794 #define PIXCLK_GATE _MMIO(0xC6020)
5795 #define PIXCLK_GATE_UNGATE (1 << 0)
5796 #define PIXCLK_GATE_GATE (0 << 0)
5799 #define SPLL_CTL _MMIO(0x46020)
5800 #define SPLL_PLL_ENABLE (1 << 31)
5801 #define SPLL_REF_BCLK (0 << 28)
5802 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
5803 #define SPLL_REF_NON_SSC_HSW (2 << 28)
5804 #define SPLL_REF_PCH_SSC_BDW (2 << 28)
5805 #define SPLL_REF_LCPLL (3 << 28)
5806 #define SPLL_REF_MASK (3 << 28)
5807 #define SPLL_FREQ_810MHz (0 << 26)
5808 #define SPLL_FREQ_1350MHz (1 << 26)
5809 #define SPLL_FREQ_2700MHz (2 << 26)
5810 #define SPLL_FREQ_MASK (3 << 26)
5813 #define _WRPLL_CTL1 0x46040
5814 #define _WRPLL_CTL2 0x46060
5815 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
5816 #define WRPLL_PLL_ENABLE (1 << 31)
5817 #define WRPLL_REF_BCLK (0 << 28)
5818 #define WRPLL_REF_PCH_SSC (1 << 28)
5819 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
5820 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
5821 #define WRPLL_REF_LCPLL (3 << 28)
5822 #define WRPLL_REF_MASK (3 << 28)
5823 /* WRPLL divider programming */
5824 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
5825 #define WRPLL_DIVIDER_REF_MASK (0xff)
5826 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
5827 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
5828 #define WRPLL_DIVIDER_POST_SHIFT 8
5829 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
5830 #define WRPLL_DIVIDER_FB_SHIFT 16
5831 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
5833 /* Port clock selection */
5834 #define _PORT_CLK_SEL_A 0x46100
5835 #define _PORT_CLK_SEL_B 0x46104
5836 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
5837 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
5838 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
5839 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
5840 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
5841 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
5842 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
5843 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
5844 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
5845 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
5847 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
5848 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
5849 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
5850 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
5851 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
5852 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
5853 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
5854 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
5855 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
5857 /* Transcoder clock selection */
5858 #define _TRANS_CLK_SEL_A 0x46140
5859 #define _TRANS_CLK_SEL_B 0x46144
5860 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
5861 /* For each transcoder, we need to select the corresponding port clock */
5862 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
5863 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
5864 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
5865 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
5868 #define CDCLK_FREQ _MMIO(0x46200)
5870 #define _TRANSA_MSA_MISC 0x60410
5871 #define _TRANSB_MSA_MISC 0x61410
5872 #define _TRANSC_MSA_MISC 0x62410
5873 #define _TRANS_EDP_MSA_MISC 0x6f410
5874 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
5875 /* See DP_MSA_MISC_* for the bit definitions */
5877 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
5878 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
5879 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
5880 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
5881 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
5882 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
5883 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
5886 #define LCPLL_CTL _MMIO(0x130040)
5887 #define LCPLL_PLL_DISABLE (1 << 31)
5888 #define LCPLL_PLL_LOCK (1 << 30)
5889 #define LCPLL_REF_NON_SSC (0 << 28)
5890 #define LCPLL_REF_BCLK (2 << 28)
5891 #define LCPLL_REF_PCH_SSC (3 << 28)
5892 #define LCPLL_REF_MASK (3 << 28)
5893 #define LCPLL_CLK_FREQ_MASK (3 << 26)
5894 #define LCPLL_CLK_FREQ_450 (0 << 26)
5895 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
5896 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
5897 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
5898 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
5899 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
5900 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
5901 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
5902 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
5903 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
5910 #define CDCLK_CTL _MMIO(0x46000)
5911 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
5912 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
5913 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
5914 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
5915 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
5916 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
5917 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
5918 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
5919 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
5920 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
5921 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
5922 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
5923 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
5924 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
5925 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
5926 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
5927 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
5928 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
5929 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
5931 /* CDCLK_SQUASH_CTL */
5932 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
5933 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
5934 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
5935 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
5936 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
5937 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
5940 #define LCPLL1_CTL _MMIO(0x46010)
5941 #define LCPLL2_CTL _MMIO(0x46014)
5942 #define LCPLL_PLL_ENABLE (1 << 31)
5945 #define DPLL_CTRL1 _MMIO(0x6C058)
5946 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
5947 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
5948 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
5949 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
5950 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
5951 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
5952 #define DPLL_CTRL1_LINK_RATE_2700 0
5953 #define DPLL_CTRL1_LINK_RATE_1350 1
5954 #define DPLL_CTRL1_LINK_RATE_810 2
5955 #define DPLL_CTRL1_LINK_RATE_1620 3
5956 #define DPLL_CTRL1_LINK_RATE_1080 4
5957 #define DPLL_CTRL1_LINK_RATE_2160 5
5960 #define DPLL_CTRL2 _MMIO(0x6C05C)
5961 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
5962 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
5963 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
5964 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
5965 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
5968 #define DPLL_STATUS _MMIO(0x6C060)
5969 #define DPLL_LOCK(id) (1 << ((id) * 8))
5972 #define _DPLL1_CFGCR1 0x6C040
5973 #define _DPLL2_CFGCR1 0x6C048
5974 #define _DPLL3_CFGCR1 0x6C050
5975 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
5976 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
5977 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
5978 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
5980 #define _DPLL1_CFGCR2 0x6C044
5981 #define _DPLL2_CFGCR2 0x6C04C
5982 #define _DPLL3_CFGCR2 0x6C054
5983 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
5984 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
5985 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
5986 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
5987 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
5988 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
5989 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
5990 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
5991 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
5992 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
5993 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
5994 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
5995 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
5996 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
5997 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
5998 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
5999 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
6001 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
6002 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
6005 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
6006 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
6007 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
6008 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
6010 (tc_port) - TC_PORT_4 + 21))
6011 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
6012 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6013 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6014 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
6015 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
6016 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6017 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
6018 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6022 * First registers controls the first A and B, while the second register
6023 * controls the phy C and D. The bits on these registers are the
6024 * same, but refer to different phys
6026 #define _DG1_DPCLKA_CFGCR0 0x164280
6027 #define _DG1_DPCLKA1_CFGCR0 0x16C280
6028 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
6029 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
6030 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
6031 _DG1_DPCLKA_CFGCR0, \
6032 _DG1_DPCLKA1_CFGCR0)
6033 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
6034 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
6035 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6036 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6039 #define _ADLS_DPCLKA_CFGCR0 0x164280
6040 #define _ADLS_DPCLKA_CFGCR1 0x1642BC
6041 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
6042 _ADLS_DPCLKA_CFGCR0, \
6043 _ADLS_DPCLKA_CFGCR1)
6044 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
6045 /* ADLS DPCLKA_CFGCR0 DDI mask */
6046 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
6047 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
6048 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
6049 /* ADLS DPCLKA_CFGCR1 DDI mask */
6050 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
6051 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
6052 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
6053 ADLS_DPCLKA_DDIA_SEL_MASK, \
6054 ADLS_DPCLKA_DDIB_SEL_MASK, \
6055 ADLS_DPCLKA_DDII_SEL_MASK, \
6056 ADLS_DPCLKA_DDIJ_SEL_MASK, \
6057 ADLS_DPCLKA_DDIK_SEL_MASK)
6060 #define _DPLL0_ENABLE 0x46010
6061 #define _DPLL1_ENABLE 0x46014
6062 #define _ADLS_DPLL2_ENABLE 0x46018
6063 #define _ADLS_DPLL3_ENABLE 0x46030
6064 #define PLL_ENABLE REG_BIT(31)
6065 #define PLL_LOCK REG_BIT(30)
6066 #define PLL_POWER_ENABLE REG_BIT(27)
6067 #define PLL_POWER_STATE REG_BIT(26)
6068 #define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
6069 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6070 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
6072 #define _DG2_PLL3_ENABLE 0x4601C
6074 #define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
6075 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6076 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
6078 #define TBT_PLL_ENABLE _MMIO(0x46020)
6080 #define _MG_PLL1_ENABLE 0x46030
6081 #define _MG_PLL2_ENABLE 0x46034
6082 #define _MG_PLL3_ENABLE 0x46038
6083 #define _MG_PLL4_ENABLE 0x4603C
6084 /* Bits are the same as _DPLL0_ENABLE */
6085 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
6089 #define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6090 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6091 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
6093 /* ADL-P Type C PLL */
6094 #define PORTTC1_PLL_ENABLE 0x46038
6095 #define PORTTC2_PLL_ENABLE 0x46040
6097 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
6098 PORTTC1_PLL_ENABLE, \
6101 #define _ICL_DPLL0_CFGCR0 0x164000
6102 #define _ICL_DPLL1_CFGCR0 0x164080
6103 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
6105 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
6106 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
6107 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
6108 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
6109 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
6110 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
6111 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
6112 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
6113 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
6114 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
6115 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
6116 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
6117 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
6118 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
6119 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
6120 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
6122 #define _ICL_DPLL0_CFGCR1 0x164004
6123 #define _ICL_DPLL1_CFGCR1 0x164084
6124 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
6126 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
6127 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
6128 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
6129 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
6130 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
6131 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
6132 #define DPLL_CFGCR1_KDIV_SHIFT (6)
6133 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
6134 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
6135 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
6136 #define DPLL_CFGCR1_KDIV_3 (4 << 6)
6137 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
6138 #define DPLL_CFGCR1_PDIV_SHIFT (2)
6139 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
6140 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
6141 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
6142 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
6143 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
6144 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
6145 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
6146 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
6148 #define _TGL_DPLL0_CFGCR0 0x164284
6149 #define _TGL_DPLL1_CFGCR0 0x16428C
6150 #define _TGL_TBTPLL_CFGCR0 0x16429C
6151 #define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6152 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6153 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
6154 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
6157 #define _TGL_DPLL0_DIV0 0x164B00
6158 #define _TGL_DPLL1_DIV0 0x164C00
6159 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
6160 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
6161 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
6163 #define _TGL_DPLL0_CFGCR1 0x164288
6164 #define _TGL_DPLL1_CFGCR1 0x164290
6165 #define _TGL_TBTPLL_CFGCR1 0x1642A0
6166 #define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6167 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6168 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
6169 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
6172 #define _DG1_DPLL2_CFGCR0 0x16C284
6173 #define _DG1_DPLL3_CFGCR0 0x16C28C
6174 #define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6175 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6176 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
6178 #define _DG1_DPLL2_CFGCR1 0x16C288
6179 #define _DG1_DPLL3_CFGCR1 0x16C290
6180 #define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6181 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6182 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
6184 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
6185 #define _ADLS_DPLL4_CFGCR0 0x164294
6186 #define _ADLS_DPLL3_CFGCR0 0x1642C0
6187 #define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6188 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6189 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
6191 #define _ADLS_DPLL4_CFGCR1 0x164298
6192 #define _ADLS_DPLL3_CFGCR1 0x1642C4
6193 #define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6194 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6195 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
6197 /* BXT display engine PLL */
6198 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
6199 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
6200 #define BXT_DE_PLL_RATIO_MASK 0xff
6202 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
6203 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
6204 #define BXT_DE_PLL_LOCK (1 << 30)
6205 #define BXT_DE_PLL_FREQ_REQ (1 << 23)
6206 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
6207 #define ICL_CDCLK_PLL_RATIO(x) (x)
6208 #define ICL_CDCLK_PLL_RATIO_MASK 0xff
6211 #define DC_STATE_EN _MMIO(0x45504)
6212 #define DC_STATE_DISABLE 0
6213 #define DC_STATE_EN_DC3CO REG_BIT(30)
6214 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
6215 #define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
6216 #define HOLD_PHY_PG1_LATCH REG_BIT(20)
6217 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
6218 #define DC_STATE_EN_DC9 (1 << 3)
6219 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
6220 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
6222 #define DC_STATE_DEBUG _MMIO(0x45520)
6223 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
6224 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
6226 #define D_COMP_BDW _MMIO(0x138144)
6228 /* Pipe WM_LINETIME - watermark line time */
6229 #define _WM_LINETIME_A 0x45270
6230 #define _WM_LINETIME_B 0x45274
6231 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
6232 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
6233 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
6234 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
6235 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
6238 #define SFUSE_STRAP _MMIO(0xc2014)
6239 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
6240 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
6241 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
6242 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
6243 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
6244 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
6245 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
6246 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
6248 #define WM_MISC _MMIO(0x45260)
6249 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6251 #define WM_DBG _MMIO(0x45280)
6252 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
6253 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
6254 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
6257 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
6258 #define _PIPE_A_CSC_COEFF_BY 0x49014
6259 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
6260 #define _PIPE_A_CSC_COEFF_BU 0x4901c
6261 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
6262 #define _PIPE_A_CSC_COEFF_BV 0x49024
6264 #define _PIPE_A_CSC_MODE 0x49028
6265 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */
6266 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
6267 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
6268 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
6269 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
6271 #define _PIPE_A_CSC_PREOFF_HI 0x49030
6272 #define _PIPE_A_CSC_PREOFF_ME 0x49034
6273 #define _PIPE_A_CSC_PREOFF_LO 0x49038
6274 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
6275 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
6276 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
6278 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
6279 #define _PIPE_B_CSC_COEFF_BY 0x49114
6280 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
6281 #define _PIPE_B_CSC_COEFF_BU 0x4911c
6282 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
6283 #define _PIPE_B_CSC_COEFF_BV 0x49124
6284 #define _PIPE_B_CSC_MODE 0x49128
6285 #define _PIPE_B_CSC_PREOFF_HI 0x49130
6286 #define _PIPE_B_CSC_PREOFF_ME 0x49134
6287 #define _PIPE_B_CSC_PREOFF_LO 0x49138
6288 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
6289 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
6290 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
6292 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
6293 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
6294 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
6295 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
6296 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
6297 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
6298 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
6299 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
6300 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
6301 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
6302 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
6303 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
6304 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
6306 /* Pipe Output CSC */
6307 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
6308 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
6309 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
6310 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
6311 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
6312 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
6313 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
6314 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
6315 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
6316 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
6317 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
6318 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
6320 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
6321 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
6322 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
6323 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
6324 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
6325 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
6326 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
6327 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
6328 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
6329 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
6330 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
6331 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
6333 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
6334 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
6335 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
6336 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
6337 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
6338 _PIPE_B_OUTPUT_CSC_COEFF_BY)
6339 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
6340 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
6341 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
6342 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
6343 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
6344 _PIPE_B_OUTPUT_CSC_COEFF_BU)
6345 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
6346 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
6347 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
6348 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
6349 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
6350 _PIPE_B_OUTPUT_CSC_COEFF_BV)
6351 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
6352 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
6353 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
6354 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
6355 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
6356 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
6357 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
6358 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
6359 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
6360 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
6361 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
6362 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
6363 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
6364 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
6365 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
6366 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
6367 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
6368 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
6370 /* pipe degamma/gamma LUTs on IVB+ */
6371 #define _PAL_PREC_INDEX_A 0x4A400
6372 #define _PAL_PREC_INDEX_B 0x4AC00
6373 #define _PAL_PREC_INDEX_C 0x4B400
6374 #define PAL_PREC_SPLIT_MODE REG_BIT(31)
6375 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
6376 #define PAL_PREC_INDEX_VALUE_MASK REG_GENMASK(9, 0)
6377 #define PAL_PREC_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_INDEX_VALUE_MASK, (x))
6378 #define _PAL_PREC_DATA_A 0x4A404
6379 #define _PAL_PREC_DATA_B 0x4AC04
6380 #define _PAL_PREC_DATA_C 0x4B404
6381 /* see PREC_PALETTE_* for the bits */
6382 #define _PAL_PREC_GC_MAX_A 0x4A410
6383 #define _PAL_PREC_GC_MAX_B 0x4AC10
6384 #define _PAL_PREC_GC_MAX_C 0x4B410
6385 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
6386 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
6387 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
6388 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
6389 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
6390 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
6392 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
6393 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
6394 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
6395 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
6396 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */
6398 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
6399 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
6400 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
6401 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
6402 #define PRE_CSC_GAMC_INDEX_VALUE_MASK REG_GENMASK(7, 0)
6403 #define PRE_CSC_GAMC_INDEX_VALUE(x) REG_FIELD_PREP(PRE_CSC_GAMC_INDEX_VALUE_MASK, (x))
6404 #define _PRE_CSC_GAMC_DATA_A 0x4A488
6405 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
6406 #define _PRE_CSC_GAMC_DATA_C 0x4B488
6408 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
6409 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
6411 /* ICL Multi segmented gamma */
6412 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
6413 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
6414 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
6415 #define PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK REG_GENMASK(4, 0)
6416 #define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x))
6418 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
6419 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
6420 /* see PREC_PALETTE_12P4_* for the bits */
6422 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
6423 _PAL_PREC_MULTI_SEG_INDEX_A, \
6424 _PAL_PREC_MULTI_SEG_INDEX_B)
6425 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
6426 _PAL_PREC_MULTI_SEG_DATA_A, \
6427 _PAL_PREC_MULTI_SEG_DATA_B)
6429 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
6431 /* Plane CSC Registers */
6432 #define _PLANE_CSC_RY_GY_1_A 0x70210
6433 #define _PLANE_CSC_RY_GY_2_A 0x70310
6435 #define _PLANE_CSC_RY_GY_1_B 0x71210
6436 #define _PLANE_CSC_RY_GY_2_B 0x71310
6438 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
6439 _PLANE_CSC_RY_GY_1_B)
6440 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
6441 _PLANE_CSC_RY_GY_2_B)
6442 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
6443 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
6444 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
6446 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
6447 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
6449 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
6450 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
6452 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
6453 _PLANE_CSC_PREOFF_HI_1_B)
6454 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
6455 _PLANE_CSC_PREOFF_HI_2_B)
6456 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
6457 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
6460 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
6461 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
6463 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
6464 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
6466 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
6467 _PLANE_CSC_POSTOFF_HI_1_B)
6468 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
6469 _PLANE_CSC_POSTOFF_HI_2_B)
6470 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
6471 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
6474 /* pipe CSC & degamma/gamma LUTs on CHV */
6475 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
6476 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
6477 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
6478 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
6479 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
6480 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
6481 /* cgm degamma ldw */
6482 #define CGM_PIPE_DEGAMMA_GREEN_LDW_MASK REG_GENMASK(29, 16)
6483 #define CGM_PIPE_DEGAMMA_BLUE_LDW_MASK REG_GENMASK(13, 0)
6484 /* cgm degamma udw */
6485 #define CGM_PIPE_DEGAMMA_RED_UDW_MASK REG_GENMASK(13, 0)
6486 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
6488 #define CGM_PIPE_GAMMA_GREEN_LDW_MASK REG_GENMASK(25, 16)
6489 #define CGM_PIPE_GAMMA_BLUE_LDW_MASK REG_GENMASK(9, 0)
6491 #define CGM_PIPE_GAMMA_RED_UDW_MASK REG_GENMASK(9, 0)
6492 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
6493 #define CGM_PIPE_MODE_GAMMA (1 << 2)
6494 #define CGM_PIPE_MODE_CSC (1 << 1)
6495 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
6497 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
6498 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
6499 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
6500 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
6501 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
6502 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
6503 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
6504 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
6506 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
6507 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
6508 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
6509 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
6510 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
6511 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
6512 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
6513 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
6515 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
6516 #define GEN4_TIMESTAMP _MMIO(0x2358)
6517 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
6518 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
6520 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
6521 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
6522 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
6523 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
6524 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
6526 /* g4x+, except vlv/chv! */
6527 #define _PIPE_FRMTMSTMP_A 0x70048
6528 #define _PIPE_FRMTMSTMP_B 0x71048
6529 #define PIPE_FRMTMSTMP(pipe) \
6530 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
6532 /* g4x+, except vlv/chv! */
6533 #define _PIPE_FLIPTMSTMP_A 0x7004C
6534 #define _PIPE_FLIPTMSTMP_B 0x7104C
6535 #define PIPE_FLIPTMSTMP(pipe) \
6536 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
6539 #define _PIPE_FLIPDONETMSTMP_A 0x70054
6540 #define _PIPE_FLIPDONETMSTMP_B 0x71054
6541 #define PIPE_FLIPDONETIMSTMP(pipe) \
6542 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
6544 #define _VLV_PIPE_MSA_MISC_A 0x70048
6545 #define VLV_PIPE_MSA_MISC(pipe) \
6546 _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
6547 #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
6548 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
6550 #define GGC _MMIO(0x108040)
6551 #define GMS_MASK REG_GENMASK(15, 8)
6552 #define GGMS_MASK REG_GENMASK(7, 6)
6554 #define GEN12_GSMBASE _MMIO(0x108100)
6555 #define GEN12_DSMBASE _MMIO(0x1080C0)
6556 #define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
6558 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
6559 #define SGSI_SIDECLK_DIS REG_BIT(17)
6560 #define SGGI_DIS REG_BIT(15)
6561 #define SGR_DIS REG_BIT(13)
6563 #define _ICL_PHY_MISC_A 0x64C00
6564 #define _ICL_PHY_MISC_B 0x64C04
6565 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
6566 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
6567 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
6569 #define ICL_PHY_MISC_MUX_DDID (1 << 28)
6570 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
6571 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
6573 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
6574 #define MODULAR_FIA_MASK (1 << 4)
6575 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
6576 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
6577 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
6578 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
6579 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
6581 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
6582 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
6584 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
6585 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
6587 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
6588 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
6589 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
6590 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
6592 #define _TCSS_DDI_STATUS_1 0x161500
6593 #define _TCSS_DDI_STATUS_2 0x161504
6594 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
6595 _TCSS_DDI_STATUS_1, \
6596 _TCSS_DDI_STATUS_2))
6597 #define TCSS_DDI_STATUS_READY REG_BIT(2)
6598 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
6599 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
6601 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
6602 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
6603 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
6604 #define SPI_STATIC_REGIONS _MMIO(0x102090)
6605 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
6606 #define OROM_OFFSET _MMIO(0x1020c0)
6607 #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
6609 #define CLKREQ_POLICY _MMIO(0x101038)
6610 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
6612 #define CLKGATE_DIS_MISC _MMIO(0x46534)
6613 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
6615 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
6616 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
6617 #define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
6618 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
6620 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
6621 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
6622 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
6623 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
6625 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
6626 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
6627 #define MTL_TRCD_MASK REG_GENMASK(31, 24)
6628 #define MTL_TRP_MASK REG_GENMASK(23, 16)
6629 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
6631 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
6632 #define MTL_TRAS_MASK REG_GENMASK(16, 8)
6633 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
6635 #define MTL_MEDIA_GSI_BASE 0x380000
6637 #endif /* _I915_REG_H_ */