2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
10 #include <linux/hrtimer.h>
11 #include <linux/perf_event.h>
12 #include <linux/spinlock_types.h>
13 #include <uapi/drm/i915_drm.h>
15 struct drm_i915_private;
18 * Non-engine events that we need to track enabled-disabled transition and
21 enum i915_pmu_tracked_events {
22 __I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,
23 __I915_PMU_REQUESTED_FREQUENCY_ENABLED,
24 __I915_PMU_RC6_RESIDENCY_ENABLED,
25 __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
29 * Slots used from the sampling timer (non-engine events) with some extras for
33 __I915_SAMPLE_FREQ_ACT = 0,
34 __I915_SAMPLE_FREQ_REQ,
36 __I915_SAMPLE_RC6_LAST_REPORTED,
37 __I915_NUM_PMU_SAMPLERS
41 * How many different events we track in the global PMU mask.
43 * It is also used to know to needed number of event reference counters.
45 #define I915_PMU_MASK_BITS \
46 (I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
48 #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
50 struct i915_pmu_sample {
56 * @cpuhp: Struct used for CPU hotplug handling.
59 struct hlist_node node;
67 * @closed: i915 is unregistering.
71 * @name: Name as registered with perf core.
75 * @lock: Lock protecting enable mask and ref count handling.
79 * @timer: Timer for internal i915 PMU sampling.
83 * @enable: Bitmask of specific enabled events.
85 * For some events we need to track their state and do some internal
88 * Each engine event sampler type and event listed in enum
89 * i915_pmu_tracked_events gets a bit in this field.
91 * Low bits are engine samplers and other events continue from there.
98 * Timestmap of the previous timer invocation.
103 * @enable_count: Reference counts for the enabled events.
105 * Array indices are mapped in the same way as bits in the @enable field
106 * and they are used to control sampling on/off when multiple clients
107 * are using the PMU API.
109 unsigned int enable_count[I915_PMU_MASK_BITS];
111 * @timer_enabled: Should the internal sampling timer be running.
115 * @sample: Current and previous (raw) counters for sampling events.
117 * These counters are updated from the i915 PMU sampling timer.
119 * Only global counters are held here, while the per-engine ones are in
120 * struct intel_engine_cs.
122 struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
124 * @sleep_last: Last time GT parked for RC6 estimation.
128 * @irq_count: Number of interrupts
130 * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
131 * 4e9 interrupts are a lot and postprocessing can really deal with an
132 * occasional wraparound easily. It's 32bit after all.
134 unsigned long irq_count;
136 * @events_attr_group: Device events attribute group.
138 struct attribute_group events_attr_group;
140 * @i915_attr: Memory block holding device attributes.
144 * @pmu_attr: Memory block holding device attributes.
149 #ifdef CONFIG_PERF_EVENTS
150 void i915_pmu_init(void);
151 void i915_pmu_exit(void);
152 void i915_pmu_register(struct drm_i915_private *i915);
153 void i915_pmu_unregister(struct drm_i915_private *i915);
154 void i915_pmu_gt_parked(struct drm_i915_private *i915);
155 void i915_pmu_gt_unparked(struct drm_i915_private *i915);
157 static inline void i915_pmu_init(void) {}
158 static inline void i915_pmu_exit(void) {}
159 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
160 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
161 static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
162 static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}