2 * Copyright © 2015-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Robert Bragg <robert@sixbynine.org>
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/sizes.h>
196 #include <linux/uuid.h>
198 #include "gem/i915_gem_context.h"
199 #include "gt/intel_engine_pm.h"
200 #include "gt/intel_engine_user.h"
201 #include "gt/intel_gt.h"
202 #include "gt/intel_lrc_reg.h"
203 #include "gt/intel_ring.h"
205 #include "i915_drv.h"
206 #include "i915_perf.h"
208 /* HW requires this to be a power of two, between 128k and 16M, though driver
209 * is currently generally designed assuming the largest 16M size is used such
210 * that the overflow cases are unlikely in normal operation.
212 #define OA_BUFFER_SIZE SZ_16M
214 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
217 * DOC: OA Tail Pointer Race
219 * There's a HW race condition between OA unit tail pointer register updates and
220 * writes to memory whereby the tail pointer can sometimes get ahead of what's
221 * been written out to the OA buffer so far (in terms of what's visible to the
224 * Although this can be observed explicitly while copying reports to userspace
225 * by checking for a zeroed report-id field in tail reports, we want to account
226 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
227 * redundant read() attempts.
229 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
230 * in the OA buffer, starting from the tail reported by the HW until we find a
231 * report with its first 2 dwords not 0 meaning its previous report is
232 * completely in memory and ready to be read. Those dwords are also set to 0
233 * once read and the whole buffer is cleared upon OA buffer initialization. The
234 * first dword is the reason for this report while the second is the timestamp,
235 * making the chances of having those 2 fields at 0 fairly unlikely. A more
236 * detailed explanation is available in oa_buffer_check_unlocked().
238 * Most of the implementation details for this workaround are in
239 * oa_buffer_check_unlocked() and _append_oa_reports()
241 * Note for posterity: previously the driver used to define an effective tail
242 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
243 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
244 * This was flawed considering that the OA unit may also automatically generate
245 * non-periodic reports (such as on context switch) or the OA unit may be
246 * enabled without any periodic sampling.
248 #define OA_TAIL_MARGIN_NSEC 100000ULL
249 #define INVALID_TAIL_PTR 0xffffffff
251 /* The default frequency for checking whether the OA unit has written new
252 * reports to the circular OA buffer...
254 #define DEFAULT_POLL_FREQUENCY_HZ 200
255 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
257 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
258 static u32 i915_perf_stream_paranoid = true;
260 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
261 * of the 64bit timestamp bits to trigger reports from) but there's currently
262 * no known use case for sampling as infrequently as once per 47 thousand years.
264 * Since the timestamps included in OA reports are only 32bits it seems
265 * reasonable to limit the OA exponent where it's still possible to account for
266 * overflow in OA report timestamps.
268 #define OA_EXPONENT_MAX 31
270 #define INVALID_CTX_ID 0xffffffff
272 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
273 #define OAREPORT_REASON_MASK 0x3f
274 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
275 #define OAREPORT_REASON_SHIFT 19
276 #define OAREPORT_REASON_TIMER (1<<0)
277 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
278 #define OAREPORT_REASON_CLK_RATIO (1<<5)
281 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
283 * The highest sampling frequency we can theoretically program the OA unit
284 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
286 * Initialized just before we register the sysctl parameter.
288 static int oa_sample_rate_hard_limit;
290 /* Theoretically we can program the OA unit to sample every 160ns but don't
291 * allow that by default unless root...
293 * The default threshold of 100000Hz is based on perf's similar
294 * kernel.perf_event_max_sample_rate sysctl parameter.
296 static u32 i915_oa_max_sample_rate = 100000;
298 /* XXX: beware if future OA HW adds new report formats that the current
299 * code assumes all reports have a power-of-two size and ~(size - 1) can
300 * be used as a mask to align the OA tail pointer.
302 static const struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
303 [I915_OA_FORMAT_A13] = { 0, 64 },
304 [I915_OA_FORMAT_A29] = { 1, 128 },
305 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
306 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
307 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
308 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
309 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
310 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
313 static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
314 [I915_OA_FORMAT_A12] = { 0, 64 },
315 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
316 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
317 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
320 static const struct i915_oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
321 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
324 #define SAMPLE_OA_REPORT (1<<0)
327 * struct perf_open_properties - for validated properties given to open a stream
328 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
329 * @single_context: Whether a single or all gpu contexts should be monitored
330 * @hold_preemption: Whether the preemption is disabled for the filtered
332 * @ctx_handle: A gem ctx handle for use with @single_context
333 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
334 * @oa_format: An OA unit HW report format
335 * @oa_periodic: Whether to enable periodic OA unit sampling
336 * @oa_period_exponent: The OA unit sampling period is derived from this
337 * @engine: The engine (typically rcs0) being monitored by the OA unit
338 * @has_sseu: Whether @sseu was specified by userspace
339 * @sseu: internal SSEU configuration computed either from the userspace
340 * specified configuration in the opening parameters or a default value
341 * (see get_default_sseu_config())
342 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
345 * As read_properties_unlocked() enumerates and validates the properties given
346 * to open a stream of metrics the configuration is built up in the structure
347 * which starts out zero initialized.
349 struct perf_open_properties {
352 u64 single_context:1;
353 u64 hold_preemption:1;
356 /* OA sampling state */
360 int oa_period_exponent;
362 struct intel_engine_cs *engine;
365 struct intel_sseu sseu;
370 struct i915_oa_config_bo {
371 struct llist_node node;
373 struct i915_oa_config *oa_config;
374 struct i915_vma *vma;
377 static struct ctl_table_header *sysctl_header;
379 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
381 void i915_oa_config_release(struct kref *ref)
383 struct i915_oa_config *oa_config =
384 container_of(ref, typeof(*oa_config), ref);
386 kfree(oa_config->flex_regs);
387 kfree(oa_config->b_counter_regs);
388 kfree(oa_config->mux_regs);
390 kfree_rcu(oa_config, rcu);
393 struct i915_oa_config *
394 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
396 struct i915_oa_config *oa_config;
399 oa_config = idr_find(&perf->metrics_idr, metrics_set);
401 oa_config = i915_oa_config_get(oa_config);
407 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
409 i915_oa_config_put(oa_bo->oa_config);
410 i915_vma_put(oa_bo->vma);
414 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
416 struct intel_uncore *uncore = stream->uncore;
418 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
419 GEN12_OAG_OATAILPTR_MASK;
422 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
424 struct intel_uncore *uncore = stream->uncore;
426 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
429 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
431 struct intel_uncore *uncore = stream->uncore;
432 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
434 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
438 * oa_buffer_check_unlocked - check for data and update tail ptr state
439 * @stream: i915 stream instance
441 * This is either called via fops (for blocking reads in user ctx) or the poll
442 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
443 * if there is data available for userspace to read.
445 * This function is central to providing a workaround for the OA unit tail
446 * pointer having a race with respect to what data is visible to the CPU.
447 * It is responsible for reading tail pointers from the hardware and giving
448 * the pointers time to 'age' before they are made available for reading.
449 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
451 * Besides returning true when there is data available to read() this function
452 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
455 * Note: It's safe to read OA config state here unlocked, assuming that this is
456 * only called while the stream is enabled, while the global OA configuration
459 * Returns: %true if the OA buffer contains data, else %false
461 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
463 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
464 int report_size = stream->oa_buffer.format_size;
470 /* We have to consider the (unlikely) possibility that read() errors
471 * could result in an OA buffer reset which might reset the head and
474 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
476 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
478 /* The tail pointer increases in 64 byte increments,
479 * not in report_size steps...
481 hw_tail &= ~(report_size - 1);
483 now = ktime_get_mono_fast_ns();
485 if (hw_tail == stream->oa_buffer.aging_tail &&
486 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
487 /* If the HW tail hasn't move since the last check and the HW
488 * tail has been aging for long enough, declare it the new
491 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
493 u32 head, tail, aged_tail;
495 /* NB: The head we observe here might effectively be a little
496 * out of date. If a read() is in progress, the head could be
497 * anywhere between this head and stream->oa_buffer.tail.
499 head = stream->oa_buffer.head - gtt_offset;
500 aged_tail = stream->oa_buffer.tail - gtt_offset;
502 hw_tail -= gtt_offset;
505 /* Walk the stream backward until we find a report with dword 0
506 * & 1 not at 0. Since the circular buffer pointers progress by
507 * increments of 64 bytes and that reports can be up to 256
508 * bytes long, we can't tell whether a report has fully landed
509 * in memory before the first 2 dwords of the following report
510 * have effectively landed.
512 * This is assuming that the writes of the OA unit land in
513 * memory in the order they were written to.
514 * If not : (╯°□°)╯︵ ┻━┻
516 while (OA_TAKEN(tail, aged_tail) >= report_size) {
517 u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
519 if (report32[0] != 0 || report32[1] != 0)
522 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
525 if (OA_TAKEN(hw_tail, tail) > report_size &&
526 __ratelimit(&stream->perf->tail_pointer_race))
527 DRM_NOTE("unlanded report(s) head=0x%x "
528 "tail=0x%x hw_tail=0x%x\n",
529 head, tail, hw_tail);
531 stream->oa_buffer.tail = gtt_offset + tail;
532 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
533 stream->oa_buffer.aging_timestamp = now;
536 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
537 stream->oa_buffer.head - gtt_offset) >= report_size;
539 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
545 * append_oa_status - Appends a status record to a userspace read() buffer.
546 * @stream: An i915-perf stream opened for OA metrics
547 * @buf: destination buffer given by userspace
548 * @count: the number of bytes userspace wants to read
549 * @offset: (inout): the current position for writing into @buf
550 * @type: The kind of status to report to userspace
552 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
553 * into the userspace read() buffer.
555 * The @buf @offset will only be updated on success.
557 * Returns: 0 on success, negative error code on failure.
559 static int append_oa_status(struct i915_perf_stream *stream,
563 enum drm_i915_perf_record_type type)
565 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
567 if ((count - *offset) < header.size)
570 if (copy_to_user(buf + *offset, &header, sizeof(header)))
573 (*offset) += header.size;
579 * append_oa_sample - Copies single OA report into userspace read() buffer.
580 * @stream: An i915-perf stream opened for OA metrics
581 * @buf: destination buffer given by userspace
582 * @count: the number of bytes userspace wants to read
583 * @offset: (inout): the current position for writing into @buf
584 * @report: A single OA report to (optionally) include as part of the sample
586 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
587 * properties when opening a stream, tracked as `stream->sample_flags`. This
588 * function copies the requested components of a single sample to the given
591 * The @buf @offset will only be updated on success.
593 * Returns: 0 on success, negative error code on failure.
595 static int append_oa_sample(struct i915_perf_stream *stream,
601 int report_size = stream->oa_buffer.format_size;
602 struct drm_i915_perf_record_header header;
603 u32 sample_flags = stream->sample_flags;
605 header.type = DRM_I915_PERF_RECORD_SAMPLE;
607 header.size = stream->sample_size;
609 if ((count - *offset) < header.size)
613 if (copy_to_user(buf, &header, sizeof(header)))
615 buf += sizeof(header);
617 if (sample_flags & SAMPLE_OA_REPORT) {
618 if (copy_to_user(buf, report, report_size))
622 (*offset) += header.size;
628 * Copies all buffered OA reports into userspace read() buffer.
629 * @stream: An i915-perf stream opened for OA metrics
630 * @buf: destination buffer given by userspace
631 * @count: the number of bytes userspace wants to read
632 * @offset: (inout): the current position for writing into @buf
634 * Notably any error condition resulting in a short read (-%ENOSPC or
635 * -%EFAULT) will be returned even though one or more records may
636 * have been successfully copied. In this case it's up to the caller
637 * to decide if the error should be squashed before returning to
640 * Note: reports are consumed from the head, and appended to the
641 * tail, so the tail chases the head?... If you think that's mad
642 * and back-to-front you're not alone, but this follows the
643 * Gen PRM naming convention.
645 * Returns: 0 on success, negative error code on failure.
647 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
652 struct intel_uncore *uncore = stream->uncore;
653 int report_size = stream->oa_buffer.format_size;
654 u8 *oa_buf_base = stream->oa_buffer.vaddr;
655 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
656 u32 mask = (OA_BUFFER_SIZE - 1);
657 size_t start_offset = *offset;
663 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
666 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
668 head = stream->oa_buffer.head;
669 tail = stream->oa_buffer.tail;
671 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
674 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
675 * while indexing relative to oa_buf_base.
681 * An out of bounds or misaligned head or tail pointer implies a driver
682 * bug since we validate + align the tail pointers we read from the
683 * hardware and we are in full control of the head pointer which should
684 * only be incremented by multiples of the report size (notably also
685 * all a power of two).
687 if (drm_WARN_ONCE(&uncore->i915->drm,
688 head > OA_BUFFER_SIZE || head % report_size ||
689 tail > OA_BUFFER_SIZE || tail % report_size,
690 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
696 (taken = OA_TAKEN(tail, head));
697 head = (head + report_size) & mask) {
698 u8 *report = oa_buf_base + head;
699 u32 *report32 = (void *)report;
704 * All the report sizes factor neatly into the buffer
705 * size so we never expect to see a report split
706 * between the beginning and end of the buffer.
708 * Given the initial alignment check a misalignment
709 * here would imply a driver bug that would result
712 if (drm_WARN_ON(&uncore->i915->drm,
713 (OA_BUFFER_SIZE - head) < report_size)) {
714 drm_err(&uncore->i915->drm,
715 "Spurious OA head ptr: non-integral report offset\n");
720 * The reason field includes flags identifying what
721 * triggered this specific report (mostly timer
722 * triggered or e.g. due to a context switch).
724 * This field is never expected to be zero so we can
725 * check that the report isn't invalid before copying
728 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
729 (IS_GEN(stream->perf->i915, 12) ?
730 OAREPORT_REASON_MASK_EXTENDED :
731 OAREPORT_REASON_MASK));
733 if (__ratelimit(&stream->perf->spurious_report_rs))
734 DRM_NOTE("Skipping spurious, invalid OA report\n");
738 ctx_id = report32[2] & stream->specific_ctx_id_mask;
741 * Squash whatever is in the CTX_ID field if it's marked as
742 * invalid to be sure we avoid false-positive, single-context
745 * Note: that we don't clear the valid_ctx_bit so userspace can
746 * understand that the ID has been squashed by the kernel.
748 if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
749 INTEL_GEN(stream->perf->i915) <= 11)
750 ctx_id = report32[2] = INVALID_CTX_ID;
753 * NB: For Gen 8 the OA unit no longer supports clock gating
754 * off for a specific context and the kernel can't securely
755 * stop the counters from updating as system-wide / global
758 * Automatic reports now include a context ID so reports can be
759 * filtered on the cpu but it's not worth trying to
760 * automatically subtract/hide counter progress for other
761 * contexts while filtering since we can't stop userspace
762 * issuing MI_REPORT_PERF_COUNT commands which would still
763 * provide a side-band view of the real values.
765 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
766 * to normalize counters for a single filtered context then it
767 * needs be forwarded bookend context-switch reports so that it
768 * can track switches in between MI_REPORT_PERF_COUNT commands
769 * and can itself subtract/ignore the progress of counters
770 * associated with other contexts. Note that the hardware
771 * automatically triggers reports when switching to a new
772 * context which are tagged with the ID of the newly active
773 * context. To avoid the complexity (and likely fragility) of
774 * reading ahead while parsing reports to try and minimize
775 * forwarding redundant context switch reports (i.e. between
776 * other, unrelated contexts) we simply elect to forward them
779 * We don't rely solely on the reason field to identify context
780 * switches since it's not-uncommon for periodic samples to
781 * identify a switch before any 'context switch' report.
783 if (!stream->perf->exclusive_stream->ctx ||
784 stream->specific_ctx_id == ctx_id ||
785 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
786 reason & OAREPORT_REASON_CTX_SWITCH) {
789 * While filtering for a single context we avoid
790 * leaking the IDs of other contexts.
792 if (stream->perf->exclusive_stream->ctx &&
793 stream->specific_ctx_id != ctx_id) {
794 report32[2] = INVALID_CTX_ID;
797 ret = append_oa_sample(stream, buf, count, offset,
802 stream->oa_buffer.last_ctx_id = ctx_id;
806 * Clear out the first 2 dword as a mean to detect unlanded
813 if (start_offset != *offset) {
814 i915_reg_t oaheadptr;
816 oaheadptr = IS_GEN(stream->perf->i915, 12) ?
817 GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
819 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
822 * We removed the gtt_offset for the copy loop above, indexing
823 * relative to oa_buf_base so put back here...
826 intel_uncore_write(uncore, oaheadptr,
827 head & GEN12_OAG_OAHEADPTR_MASK);
828 stream->oa_buffer.head = head;
830 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
837 * gen8_oa_read - copy status records then buffered OA reports
838 * @stream: An i915-perf stream opened for OA metrics
839 * @buf: destination buffer given by userspace
840 * @count: the number of bytes userspace wants to read
841 * @offset: (inout): the current position for writing into @buf
843 * Checks OA unit status registers and if necessary appends corresponding
844 * status records for userspace (such as for a buffer full condition) and then
845 * initiate appending any buffered OA reports.
847 * Updates @offset according to the number of bytes successfully copied into
848 * the userspace buffer.
850 * NB: some data may be successfully copied to the userspace buffer
851 * even if an error is returned, and this is reflected in the
854 * Returns: zero on success or a negative error code
856 static int gen8_oa_read(struct i915_perf_stream *stream,
861 struct intel_uncore *uncore = stream->uncore;
863 i915_reg_t oastatus_reg;
866 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
869 oastatus_reg = IS_GEN(stream->perf->i915, 12) ?
870 GEN12_OAG_OASTATUS : GEN8_OASTATUS;
872 oastatus = intel_uncore_read(uncore, oastatus_reg);
875 * We treat OABUFFER_OVERFLOW as a significant error:
877 * Although theoretically we could handle this more gracefully
878 * sometimes, some Gens don't correctly suppress certain
879 * automatically triggered reports in this condition and so we
880 * have to assume that old reports are now being trampled
883 * Considering how we don't currently give userspace control
884 * over the OA buffer size and always configure a large 16MB
885 * buffer, then a buffer overflow does anyway likely indicate
886 * that something has gone quite badly wrong.
888 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
889 ret = append_oa_status(stream, buf, count, offset,
890 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
894 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
895 stream->period_exponent);
897 stream->perf->ops.oa_disable(stream);
898 stream->perf->ops.oa_enable(stream);
901 * Note: .oa_enable() is expected to re-init the oabuffer and
902 * reset GEN8_OASTATUS for us
904 oastatus = intel_uncore_read(uncore, oastatus_reg);
907 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
908 ret = append_oa_status(stream, buf, count, offset,
909 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
912 intel_uncore_write(uncore, oastatus_reg,
913 oastatus & ~GEN8_OASTATUS_REPORT_LOST);
916 return gen8_append_oa_reports(stream, buf, count, offset);
920 * Copies all buffered OA reports into userspace read() buffer.
921 * @stream: An i915-perf stream opened for OA metrics
922 * @buf: destination buffer given by userspace
923 * @count: the number of bytes userspace wants to read
924 * @offset: (inout): the current position for writing into @buf
926 * Notably any error condition resulting in a short read (-%ENOSPC or
927 * -%EFAULT) will be returned even though one or more records may
928 * have been successfully copied. In this case it's up to the caller
929 * to decide if the error should be squashed before returning to
932 * Note: reports are consumed from the head, and appended to the
933 * tail, so the tail chases the head?... If you think that's mad
934 * and back-to-front you're not alone, but this follows the
935 * Gen PRM naming convention.
937 * Returns: 0 on success, negative error code on failure.
939 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
944 struct intel_uncore *uncore = stream->uncore;
945 int report_size = stream->oa_buffer.format_size;
946 u8 *oa_buf_base = stream->oa_buffer.vaddr;
947 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
948 u32 mask = (OA_BUFFER_SIZE - 1);
949 size_t start_offset = *offset;
955 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
958 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
960 head = stream->oa_buffer.head;
961 tail = stream->oa_buffer.tail;
963 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
965 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
966 * while indexing relative to oa_buf_base.
971 /* An out of bounds or misaligned head or tail pointer implies a driver
972 * bug since we validate + align the tail pointers we read from the
973 * hardware and we are in full control of the head pointer which should
974 * only be incremented by multiples of the report size (notably also
975 * all a power of two).
977 if (drm_WARN_ONCE(&uncore->i915->drm,
978 head > OA_BUFFER_SIZE || head % report_size ||
979 tail > OA_BUFFER_SIZE || tail % report_size,
980 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
986 (taken = OA_TAKEN(tail, head));
987 head = (head + report_size) & mask) {
988 u8 *report = oa_buf_base + head;
989 u32 *report32 = (void *)report;
991 /* All the report sizes factor neatly into the buffer
992 * size so we never expect to see a report split
993 * between the beginning and end of the buffer.
995 * Given the initial alignment check a misalignment
996 * here would imply a driver bug that would result
999 if (drm_WARN_ON(&uncore->i915->drm,
1000 (OA_BUFFER_SIZE - head) < report_size)) {
1001 drm_err(&uncore->i915->drm,
1002 "Spurious OA head ptr: non-integral report offset\n");
1006 /* The report-ID field for periodic samples includes
1007 * some undocumented flags related to what triggered
1008 * the report and is never expected to be zero so we
1009 * can check that the report isn't invalid before
1010 * copying it to userspace...
1012 if (report32[0] == 0) {
1013 if (__ratelimit(&stream->perf->spurious_report_rs))
1014 DRM_NOTE("Skipping spurious, invalid OA report\n");
1018 ret = append_oa_sample(stream, buf, count, offset, report);
1022 /* Clear out the first 2 dwords as a mean to detect unlanded
1029 if (start_offset != *offset) {
1030 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1032 /* We removed the gtt_offset for the copy loop above, indexing
1033 * relative to oa_buf_base so put back here...
1037 intel_uncore_write(uncore, GEN7_OASTATUS2,
1038 (head & GEN7_OASTATUS2_HEAD_MASK) |
1039 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1040 stream->oa_buffer.head = head;
1042 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1049 * gen7_oa_read - copy status records then buffered OA reports
1050 * @stream: An i915-perf stream opened for OA metrics
1051 * @buf: destination buffer given by userspace
1052 * @count: the number of bytes userspace wants to read
1053 * @offset: (inout): the current position for writing into @buf
1055 * Checks Gen 7 specific OA unit status registers and if necessary appends
1056 * corresponding status records for userspace (such as for a buffer full
1057 * condition) and then initiate appending any buffered OA reports.
1059 * Updates @offset according to the number of bytes successfully copied into
1060 * the userspace buffer.
1062 * Returns: zero on success or a negative error code
1064 static int gen7_oa_read(struct i915_perf_stream *stream,
1069 struct intel_uncore *uncore = stream->uncore;
1073 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1076 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1078 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1079 * bits while the OA unit is enabled (while the tail pointer
1080 * may be updated asynchronously) so we ignore status bits
1081 * that have already been reported to userspace.
1083 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1085 /* We treat OABUFFER_OVERFLOW as a significant error:
1087 * - The status can be interpreted to mean that the buffer is
1088 * currently full (with a higher precedence than OA_TAKEN()
1089 * which will start to report a near-empty buffer after an
1090 * overflow) but it's awkward that we can't clear the status
1091 * on Haswell, so without a reset we won't be able to catch
1094 * - Since it also implies the HW has started overwriting old
1095 * reports it may also affect our sanity checks for invalid
1096 * reports when copying to userspace that assume new reports
1097 * are being written to cleared memory.
1099 * - In the future we may want to introduce a flight recorder
1100 * mode where the driver will automatically maintain a safe
1101 * guard band between head/tail, avoiding this overflow
1102 * condition, but we avoid the added driver complexity for
1105 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1106 ret = append_oa_status(stream, buf, count, offset,
1107 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1111 DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
1112 stream->period_exponent);
1114 stream->perf->ops.oa_disable(stream);
1115 stream->perf->ops.oa_enable(stream);
1117 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1120 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1121 ret = append_oa_status(stream, buf, count, offset,
1122 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1125 stream->perf->gen7_latched_oastatus1 |=
1126 GEN7_OASTATUS1_REPORT_LOST;
1129 return gen7_append_oa_reports(stream, buf, count, offset);
1133 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1134 * @stream: An i915-perf stream opened for OA metrics
1136 * Called when userspace tries to read() from a blocking stream FD opened
1137 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1138 * OA buffer and wakes us.
1140 * Note: it's acceptable to have this return with some false positives
1141 * since any subsequent read handling will return -EAGAIN if there isn't
1142 * really data ready for userspace yet.
1144 * Returns: zero on success or a negative error code
1146 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1148 /* We would wait indefinitely if periodic sampling is not enabled */
1149 if (!stream->periodic)
1152 return wait_event_interruptible(stream->poll_wq,
1153 oa_buffer_check_unlocked(stream));
1157 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1158 * @stream: An i915-perf stream opened for OA metrics
1159 * @file: An i915 perf stream file
1160 * @wait: poll() state table
1162 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1163 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1164 * when it sees data ready to read in the circular OA buffer.
1166 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1170 poll_wait(file, &stream->poll_wq, wait);
1174 * i915_oa_read - just calls through to &i915_oa_ops->read
1175 * @stream: An i915-perf stream opened for OA metrics
1176 * @buf: destination buffer given by userspace
1177 * @count: the number of bytes userspace wants to read
1178 * @offset: (inout): the current position for writing into @buf
1180 * Updates @offset according to the number of bytes successfully copied into
1181 * the userspace buffer.
1183 * Returns: zero on success or a negative error code
1185 static int i915_oa_read(struct i915_perf_stream *stream,
1190 return stream->perf->ops.read(stream, buf, count, offset);
1193 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1195 struct i915_gem_engines_iter it;
1196 struct i915_gem_context *ctx = stream->ctx;
1197 struct intel_context *ce;
1200 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1201 if (ce->engine != stream->engine) /* first match! */
1205 * As the ID is the gtt offset of the context's vma we
1206 * pin the vma to ensure the ID remains fixed.
1208 err = intel_context_pin(ce);
1210 stream->pinned_ctx = ce;
1214 i915_gem_context_unlock_engines(ctx);
1216 return stream->pinned_ctx;
1220 * oa_get_render_ctx_id - determine and hold ctx hw id
1221 * @stream: An i915-perf stream opened for OA metrics
1223 * Determine the render context hw id, and ensure it remains fixed for the
1224 * lifetime of the stream. This ensures that we don't have to worry about
1225 * updating the context ID in OACONTROL on the fly.
1227 * Returns: zero on success or a negative error code
1229 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1231 struct intel_context *ce;
1233 ce = oa_pin_context(stream);
1237 switch (INTEL_GEN(ce->engine->i915)) {
1240 * On Haswell we don't do any post processing of the reports
1241 * and don't need to use the mask.
1243 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1244 stream->specific_ctx_id_mask = 0;
1251 if (intel_engine_in_execlists_submission_mode(ce->engine)) {
1252 stream->specific_ctx_id_mask =
1253 (1U << GEN8_CTX_ID_WIDTH) - 1;
1254 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1257 * When using GuC, the context descriptor we write in
1258 * i915 is read by GuC and rewritten before it's
1259 * actually written into the hardware. The LRCA is
1260 * what is put into the context id field of the
1261 * context descriptor by GuC. Because it's aligned to
1262 * a page, the lower 12bits are always at 0 and
1263 * dropped by GuC. They won't be part of the context
1264 * ID in the OA reports, so squash those lower bits.
1266 stream->specific_ctx_id =
1267 lower_32_bits(ce->lrc_desc) >> 12;
1270 * GuC uses the top bit to signal proxy submission, so
1273 stream->specific_ctx_id_mask =
1274 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1280 stream->specific_ctx_id_mask =
1281 ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1283 * Pick an unused context id
1284 * 0 - (NUM_CONTEXT_TAG - 1) are used by other contexts
1285 * GEN12_MAX_CONTEXT_HW_ID (0x7ff) is used by idle context
1287 stream->specific_ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1288 BUILD_BUG_ON((GEN12_MAX_CONTEXT_HW_ID - 1) < NUM_CONTEXT_TAG);
1293 MISSING_CASE(INTEL_GEN(ce->engine->i915));
1296 ce->tag = stream->specific_ctx_id;
1298 drm_dbg(&stream->perf->i915->drm,
1299 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1300 stream->specific_ctx_id,
1301 stream->specific_ctx_id_mask);
1307 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1308 * @stream: An i915-perf stream opened for OA metrics
1310 * In case anything needed doing to ensure the context HW ID would remain valid
1311 * for the lifetime of the stream, then that can be undone here.
1313 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1315 struct intel_context *ce;
1317 ce = fetch_and_zero(&stream->pinned_ctx);
1319 ce->tag = 0; /* recomputed on next submission after parking */
1320 intel_context_unpin(ce);
1323 stream->specific_ctx_id = INVALID_CTX_ID;
1324 stream->specific_ctx_id_mask = 0;
1328 free_oa_buffer(struct i915_perf_stream *stream)
1330 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1331 I915_VMA_RELEASE_MAP);
1333 stream->oa_buffer.vaddr = NULL;
1337 free_oa_configs(struct i915_perf_stream *stream)
1339 struct i915_oa_config_bo *oa_bo, *tmp;
1341 i915_oa_config_put(stream->oa_config);
1342 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1343 free_oa_config_bo(oa_bo);
1347 free_noa_wait(struct i915_perf_stream *stream)
1349 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1352 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1354 struct i915_perf *perf = stream->perf;
1356 BUG_ON(stream != perf->exclusive_stream);
1359 * Unset exclusive_stream first, it will be checked while disabling
1360 * the metric set on gen8+.
1362 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1364 WRITE_ONCE(perf->exclusive_stream, NULL);
1365 perf->ops.disable_metric_set(stream);
1367 free_oa_buffer(stream);
1369 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1370 intel_engine_pm_put(stream->engine);
1373 oa_put_render_ctx_id(stream);
1375 free_oa_configs(stream);
1376 free_noa_wait(stream);
1378 if (perf->spurious_report_rs.missed) {
1379 DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
1380 perf->spurious_report_rs.missed);
1384 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1386 struct intel_uncore *uncore = stream->uncore;
1387 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1388 unsigned long flags;
1390 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1392 /* Pre-DevBDW: OABUFFER must be set with counters off,
1393 * before OASTATUS1, but after OASTATUS2
1395 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1396 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1397 stream->oa_buffer.head = gtt_offset;
1399 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1401 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1402 gtt_offset | OABUFFER_SIZE_16M);
1404 /* Mark that we need updated tail pointers to read from... */
1405 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1406 stream->oa_buffer.tail = gtt_offset;
1408 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1410 /* On Haswell we have to track which OASTATUS1 flags we've
1411 * already seen since they can't be cleared while periodic
1412 * sampling is enabled.
1414 stream->perf->gen7_latched_oastatus1 = 0;
1416 /* NB: although the OA buffer will initially be allocated
1417 * zeroed via shmfs (and so this memset is redundant when
1418 * first allocating), we may re-init the OA buffer, either
1419 * when re-enabling a stream or in error/reset paths.
1421 * The reason we clear the buffer for each re-init is for the
1422 * sanity check in gen7_append_oa_reports() that looks at the
1423 * report-id field to make sure it's non-zero which relies on
1424 * the assumption that new reports are being written to zeroed
1427 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1430 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1432 struct intel_uncore *uncore = stream->uncore;
1433 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1434 unsigned long flags;
1436 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1438 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1439 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1440 stream->oa_buffer.head = gtt_offset;
1442 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1447 * "This MMIO must be set before the OATAILPTR
1448 * register and after the OAHEADPTR register. This is
1449 * to enable proper functionality of the overflow
1452 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1453 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1454 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1456 /* Mark that we need updated tail pointers to read from... */
1457 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1458 stream->oa_buffer.tail = gtt_offset;
1461 * Reset state used to recognise context switches, affecting which
1462 * reports we will forward to userspace while filtering for a single
1465 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1467 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1470 * NB: although the OA buffer will initially be allocated
1471 * zeroed via shmfs (and so this memset is redundant when
1472 * first allocating), we may re-init the OA buffer, either
1473 * when re-enabling a stream or in error/reset paths.
1475 * The reason we clear the buffer for each re-init is for the
1476 * sanity check in gen8_append_oa_reports() that looks at the
1477 * reason field to make sure it's non-zero which relies on
1478 * the assumption that new reports are being written to zeroed
1481 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1484 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1486 struct intel_uncore *uncore = stream->uncore;
1487 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1488 unsigned long flags;
1490 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1492 intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
1493 intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
1494 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1495 stream->oa_buffer.head = gtt_offset;
1500 * "This MMIO must be set before the OATAILPTR
1501 * register and after the OAHEADPTR register. This is
1502 * to enable proper functionality of the overflow
1505 intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
1506 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1507 intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
1508 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1510 /* Mark that we need updated tail pointers to read from... */
1511 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1512 stream->oa_buffer.tail = gtt_offset;
1515 * Reset state used to recognise context switches, affecting which
1516 * reports we will forward to userspace while filtering for a single
1519 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1521 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1524 * NB: although the OA buffer will initially be allocated
1525 * zeroed via shmfs (and so this memset is redundant when
1526 * first allocating), we may re-init the OA buffer, either
1527 * when re-enabling a stream or in error/reset paths.
1529 * The reason we clear the buffer for each re-init is for the
1530 * sanity check in gen8_append_oa_reports() that looks at the
1531 * reason field to make sure it's non-zero which relies on
1532 * the assumption that new reports are being written to zeroed
1535 memset(stream->oa_buffer.vaddr, 0,
1536 stream->oa_buffer.vma->size);
1539 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1541 struct drm_i915_private *i915 = stream->perf->i915;
1542 struct drm_i915_gem_object *bo;
1543 struct i915_vma *vma;
1546 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1549 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1550 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1552 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1554 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1558 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1560 /* PreHSW required 512K alignment, HSW requires 16M */
1561 vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
1566 stream->oa_buffer.vma = vma;
1568 stream->oa_buffer.vaddr =
1569 i915_gem_object_pin_map(bo, I915_MAP_WB);
1570 if (IS_ERR(stream->oa_buffer.vaddr)) {
1571 ret = PTR_ERR(stream->oa_buffer.vaddr);
1578 __i915_vma_unpin(vma);
1581 i915_gem_object_put(bo);
1583 stream->oa_buffer.vaddr = NULL;
1584 stream->oa_buffer.vma = NULL;
1589 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1590 bool save, i915_reg_t reg, u32 offset,
1596 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1597 if (INTEL_GEN(stream->perf->i915) >= 8)
1600 for (d = 0; d < dword_count; d++) {
1602 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1603 *cs++ = intel_gt_scratch_offset(stream->engine->gt,
1611 static int alloc_noa_wait(struct i915_perf_stream *stream)
1613 struct drm_i915_private *i915 = stream->perf->i915;
1614 struct drm_i915_gem_object *bo;
1615 struct i915_vma *vma;
1616 const u64 delay_ticks = 0xffffffffffffffff -
1618 atomic64_read(&stream->perf->noa_programming_delay) *
1619 RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
1621 const u32 base = stream->engine->mmio_base;
1622 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1623 u32 *batch, *ts0, *cs, *jump;
1634 bo = i915_gem_object_create_internal(i915, 4096);
1637 "Failed to allocate NOA wait batchbuffer\n");
1642 * We pin in GGTT because we jump into this buffer now because
1643 * multiple OA config BOs will have a jump to this address and it
1644 * needs to be fixed during the lifetime of the i915/perf stream.
1646 vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 0, PIN_HIGH);
1652 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1653 if (IS_ERR(batch)) {
1654 ret = PTR_ERR(batch);
1658 /* Save registers. */
1659 for (i = 0; i < N_CS_GPR; i++)
1660 cs = save_restore_register(
1661 stream, cs, true /* save */, CS_GPR(i),
1662 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1663 cs = save_restore_register(
1664 stream, cs, true /* save */, MI_PREDICATE_RESULT_1,
1665 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1667 /* First timestamp snapshot location. */
1671 * Initial snapshot of the timestamp register to implement the wait.
1672 * We work with 32b values, so clear out the top 32b bits of the
1673 * register because the ALU works 64bits.
1675 *cs++ = MI_LOAD_REGISTER_IMM(1);
1676 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1678 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1679 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1680 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1683 * This is the location we're going to jump back into until the
1684 * required amount of time has passed.
1689 * Take another snapshot of the timestamp register. Take care to clear
1690 * up the top 32bits of CS_GPR(1) as we're using it for other
1693 *cs++ = MI_LOAD_REGISTER_IMM(1);
1694 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1696 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1697 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1698 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1701 * Do a diff between the 2 timestamps and store the result back into
1705 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
1706 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
1707 *cs++ = MI_MATH_SUB;
1708 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
1709 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1712 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
1713 * timestamp have rolled over the 32bits) into the predicate register
1714 * to be used for the predicated jump.
1716 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1717 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1718 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1720 /* Restart from the beginning if we had timestamps roll over. */
1721 *cs++ = (INTEL_GEN(i915) < 8 ?
1722 MI_BATCH_BUFFER_START :
1723 MI_BATCH_BUFFER_START_GEN8) |
1725 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
1729 * Now add the diff between to previous timestamps and add it to :
1730 * (((1 * << 64) - 1) - delay_ns)
1732 * When the Carry Flag contains 1 this means the elapsed time is
1733 * longer than the expected delay, and we can exit the wait loop.
1735 *cs++ = MI_LOAD_REGISTER_IMM(2);
1736 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
1737 *cs++ = lower_32_bits(delay_ticks);
1738 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
1739 *cs++ = upper_32_bits(delay_ticks);
1742 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
1743 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
1744 *cs++ = MI_MATH_ADD;
1745 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1747 *cs++ = MI_ARB_CHECK;
1750 * Transfer the result into the predicate register to be used for the
1753 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1754 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1755 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
1757 /* Predicate the jump. */
1758 *cs++ = (INTEL_GEN(i915) < 8 ?
1759 MI_BATCH_BUFFER_START :
1760 MI_BATCH_BUFFER_START_GEN8) |
1762 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
1765 /* Restore registers. */
1766 for (i = 0; i < N_CS_GPR; i++)
1767 cs = save_restore_register(
1768 stream, cs, false /* restore */, CS_GPR(i),
1769 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1770 cs = save_restore_register(
1771 stream, cs, false /* restore */, MI_PREDICATE_RESULT_1,
1772 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1774 /* And return to the ring. */
1775 *cs++ = MI_BATCH_BUFFER_END;
1777 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
1779 i915_gem_object_flush_map(bo);
1780 i915_gem_object_unpin_map(bo);
1782 stream->noa_wait = vma;
1786 i915_vma_unpin_and_release(&vma, 0);
1788 i915_gem_object_put(bo);
1792 static u32 *write_cs_mi_lri(u32 *cs,
1793 const struct i915_oa_reg *reg_data,
1798 for (i = 0; i < n_regs; i++) {
1799 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
1800 u32 n_lri = min_t(u32,
1802 MI_LOAD_REGISTER_IMM_MAX_REGS);
1804 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
1806 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
1807 *cs++ = reg_data[i].value;
1813 static int num_lri_dwords(int num_regs)
1818 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
1819 count += num_regs * 2;
1825 static struct i915_oa_config_bo *
1826 alloc_oa_config_buffer(struct i915_perf_stream *stream,
1827 struct i915_oa_config *oa_config)
1829 struct drm_i915_gem_object *obj;
1830 struct i915_oa_config_bo *oa_bo;
1831 size_t config_length = 0;
1835 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
1837 return ERR_PTR(-ENOMEM);
1839 config_length += num_lri_dwords(oa_config->mux_regs_len);
1840 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
1841 config_length += num_lri_dwords(oa_config->flex_regs_len);
1842 config_length += 3; /* MI_BATCH_BUFFER_START */
1843 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
1845 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
1851 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
1857 cs = write_cs_mi_lri(cs,
1858 oa_config->mux_regs,
1859 oa_config->mux_regs_len);
1860 cs = write_cs_mi_lri(cs,
1861 oa_config->b_counter_regs,
1862 oa_config->b_counter_regs_len);
1863 cs = write_cs_mi_lri(cs,
1864 oa_config->flex_regs,
1865 oa_config->flex_regs_len);
1867 /* Jump into the active wait. */
1868 *cs++ = (INTEL_GEN(stream->perf->i915) < 8 ?
1869 MI_BATCH_BUFFER_START :
1870 MI_BATCH_BUFFER_START_GEN8);
1871 *cs++ = i915_ggtt_offset(stream->noa_wait);
1874 i915_gem_object_flush_map(obj);
1875 i915_gem_object_unpin_map(obj);
1877 oa_bo->vma = i915_vma_instance(obj,
1878 &stream->engine->gt->ggtt->vm,
1880 if (IS_ERR(oa_bo->vma)) {
1881 err = PTR_ERR(oa_bo->vma);
1885 oa_bo->oa_config = i915_oa_config_get(oa_config);
1886 llist_add(&oa_bo->node, &stream->oa_config_bos);
1891 i915_gem_object_put(obj);
1894 return ERR_PTR(err);
1897 static struct i915_vma *
1898 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
1900 struct i915_oa_config_bo *oa_bo;
1903 * Look for the buffer in the already allocated BOs attached
1906 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
1907 if (oa_bo->oa_config == oa_config &&
1908 memcmp(oa_bo->oa_config->uuid,
1910 sizeof(oa_config->uuid)) == 0)
1914 oa_bo = alloc_oa_config_buffer(stream, oa_config);
1916 return ERR_CAST(oa_bo);
1919 return i915_vma_get(oa_bo->vma);
1923 emit_oa_config(struct i915_perf_stream *stream,
1924 struct i915_oa_config *oa_config,
1925 struct intel_context *ce,
1926 struct i915_active *active)
1928 struct i915_request *rq;
1929 struct i915_vma *vma;
1932 vma = get_oa_vma(stream, oa_config);
1934 return PTR_ERR(vma);
1936 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1940 intel_engine_pm_get(ce->engine);
1941 rq = i915_request_create(ce);
1942 intel_engine_pm_put(ce->engine);
1948 if (!IS_ERR_OR_NULL(active)) {
1949 /* After all individual context modifications */
1950 err = i915_request_await_active(rq, active,
1951 I915_ACTIVE_AWAIT_ACTIVE);
1953 goto err_add_request;
1955 err = i915_active_add_request(active, rq);
1957 goto err_add_request;
1961 err = i915_request_await_object(rq, vma->obj, 0);
1963 err = i915_vma_move_to_active(vma, rq, 0);
1964 i915_vma_unlock(vma);
1966 goto err_add_request;
1968 err = rq->engine->emit_bb_start(rq,
1970 I915_DISPATCH_SECURE);
1972 goto err_add_request;
1975 i915_request_add(rq);
1977 i915_vma_unpin(vma);
1983 static struct intel_context *oa_context(struct i915_perf_stream *stream)
1985 return stream->pinned_ctx ?: stream->engine->kernel_context;
1989 hsw_enable_metric_set(struct i915_perf_stream *stream,
1990 struct i915_active *active)
1992 struct intel_uncore *uncore = stream->uncore;
1997 * OA unit is using “crclk” for its functionality. When trunk
1998 * level clock gating takes place, OA clock would be gated,
1999 * unable to count the events from non-render clock domain.
2000 * Render clock gating must be disabled when OA is enabled to
2001 * count the events from non-render domain. Unit level clock
2002 * gating for RCS should also be disabled.
2004 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2005 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2006 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2007 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2009 return emit_oa_config(stream,
2010 stream->oa_config, oa_context(stream),
2014 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2016 struct intel_uncore *uncore = stream->uncore;
2018 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2019 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2020 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2021 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2023 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2026 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2029 u32 mmio = i915_mmio_reg_offset(reg);
2033 * This arbitrary default will select the 'EU FPU0 Pipeline
2034 * Active' event. In the future it's anticipated that there
2035 * will be an explicit 'No Event' we can select, but not yet...
2040 for (i = 0; i < oa_config->flex_regs_len; i++) {
2041 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2042 return oa_config->flex_regs[i].value;
2048 * NB: It must always remain pointer safe to run this even if the OA unit
2049 * has been disabled.
2051 * It's fine to put out-of-date values into these per-context registers
2052 * in the case that the OA unit has been disabled.
2055 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2056 const struct i915_perf_stream *stream)
2058 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2059 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2060 /* The MMIO offsets for Flex EU registers aren't contiguous */
2061 i915_reg_t flex_regs[] = {
2070 u32 *reg_state = ce->lrc_reg_state;
2073 reg_state[ctx_oactxctrl + 1] =
2074 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2075 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2076 GEN8_OA_COUNTER_RESUME;
2078 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2079 reg_state[ctx_flexeu0 + i * 2 + 1] =
2080 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2090 gen8_store_flex(struct i915_request *rq,
2091 struct intel_context *ce,
2092 const struct flex *flex, unsigned int count)
2097 cs = intel_ring_begin(rq, 4 * count);
2101 offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
2103 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2104 *cs++ = offset + flex->offset * sizeof(u32);
2106 *cs++ = flex->value;
2107 } while (flex++, --count);
2109 intel_ring_advance(rq, cs);
2115 gen8_load_flex(struct i915_request *rq,
2116 struct intel_context *ce,
2117 const struct flex *flex, unsigned int count)
2121 GEM_BUG_ON(!count || count > 63);
2123 cs = intel_ring_begin(rq, 2 * count + 2);
2127 *cs++ = MI_LOAD_REGISTER_IMM(count);
2129 *cs++ = i915_mmio_reg_offset(flex->reg);
2130 *cs++ = flex->value;
2131 } while (flex++, --count);
2134 intel_ring_advance(rq, cs);
2139 static int gen8_modify_context(struct intel_context *ce,
2140 const struct flex *flex, unsigned int count)
2142 struct i915_request *rq;
2145 rq = intel_engine_create_kernel_request(ce->engine);
2149 /* Serialise with the remote context */
2150 err = intel_context_prepare_remote_request(ce, rq);
2152 err = gen8_store_flex(rq, ce, flex, count);
2154 i915_request_add(rq);
2159 gen8_modify_self(struct intel_context *ce,
2160 const struct flex *flex, unsigned int count,
2161 struct i915_active *active)
2163 struct i915_request *rq;
2166 intel_engine_pm_get(ce->engine);
2167 rq = i915_request_create(ce);
2168 intel_engine_pm_put(ce->engine);
2172 if (!IS_ERR_OR_NULL(active)) {
2173 err = i915_active_add_request(active, rq);
2175 goto err_add_request;
2178 err = gen8_load_flex(rq, ce, flex, count);
2180 goto err_add_request;
2183 i915_request_add(rq);
2187 static int gen8_configure_context(struct i915_gem_context *ctx,
2188 struct flex *flex, unsigned int count)
2190 struct i915_gem_engines_iter it;
2191 struct intel_context *ce;
2194 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2195 GEM_BUG_ON(ce == ce->engine->kernel_context);
2197 if (ce->engine->class != RENDER_CLASS)
2200 /* Otherwise OA settings will be set upon first use */
2201 if (!intel_context_pin_if_active(ce))
2204 flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
2205 err = gen8_modify_context(ce, flex, count);
2207 intel_context_unpin(ce);
2211 i915_gem_context_unlock_engines(ctx);
2216 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2217 struct i915_active *active)
2220 struct intel_context *ce = stream->pinned_ctx;
2221 u32 format = stream->oa_buffer.format;
2222 struct flex regs_context[] = {
2225 stream->perf->ctx_oactxctrl_offset + 1,
2226 active ? GEN8_OA_COUNTER_RESUME : 0,
2229 /* Offsets in regs_lri are not used since this configuration is only
2230 * applied using LRI. Initialize the correct offsets for posterity.
2232 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2233 struct flex regs_lri[] = {
2235 GEN12_OAR_OACONTROL,
2236 GEN12_OAR_OACONTROL_OFFSET + 1,
2237 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2238 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2241 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2242 CTX_CONTEXT_CONTROL,
2243 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2245 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2250 /* Modify the context image of pinned context with regs_context*/
2251 err = intel_context_lock_pinned(ce);
2255 err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
2256 intel_context_unlock_pinned(ce);
2260 /* Apply regs_lri using LRI with pinned context */
2261 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2265 * Manages updating the per-context aspects of the OA stream
2266 * configuration across all contexts.
2268 * The awkward consideration here is that OACTXCONTROL controls the
2269 * exponent for periodic sampling which is primarily used for system
2270 * wide profiling where we'd like a consistent sampling period even in
2271 * the face of context switches.
2273 * Our approach of updating the register state context (as opposed to
2274 * say using a workaround batch buffer) ensures that the hardware
2275 * won't automatically reload an out-of-date timer exponent even
2276 * transiently before a WA BB could be parsed.
2278 * This function needs to:
2279 * - Ensure the currently running context's per-context OA state is
2281 * - Ensure that all existing contexts will have the correct per-context
2282 * OA state if they are scheduled for use.
2283 * - Ensure any new contexts will be initialized with the correct
2284 * per-context OA state.
2286 * Note: it's only the RCS/Render context that has any OA state.
2287 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2290 oa_configure_all_contexts(struct i915_perf_stream *stream,
2293 struct i915_active *active)
2295 struct drm_i915_private *i915 = stream->perf->i915;
2296 struct intel_engine_cs *engine;
2297 struct i915_gem_context *ctx, *cn;
2300 lockdep_assert_held(&stream->perf->lock);
2303 * The OA register config is setup through the context image. This image
2304 * might be written to by the GPU on context switch (in particular on
2305 * lite-restore). This means we can't safely update a context's image,
2306 * if this context is scheduled/submitted to run on the GPU.
2308 * We could emit the OA register config through the batch buffer but
2309 * this might leave small interval of time where the OA unit is
2310 * configured at an invalid sampling period.
2312 * Note that since we emit all requests from a single ring, there
2313 * is still an implicit global barrier here that may cause a high
2314 * priority context to wait for an otherwise independent low priority
2315 * context. Contexts idle at the time of reconfiguration are not
2316 * trapped behind the barrier.
2318 spin_lock(&i915->gem.contexts.lock);
2319 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2320 if (!kref_get_unless_zero(&ctx->ref))
2323 spin_unlock(&i915->gem.contexts.lock);
2325 err = gen8_configure_context(ctx, regs, num_regs);
2327 i915_gem_context_put(ctx);
2331 spin_lock(&i915->gem.contexts.lock);
2332 list_safe_reset_next(ctx, cn, link);
2333 i915_gem_context_put(ctx);
2335 spin_unlock(&i915->gem.contexts.lock);
2338 * After updating all other contexts, we need to modify ourselves.
2339 * If we don't modify the kernel_context, we do not get events while
2342 for_each_uabi_engine(engine, i915) {
2343 struct intel_context *ce = engine->kernel_context;
2345 if (engine->class != RENDER_CLASS)
2348 regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
2350 err = gen8_modify_self(ce, regs, num_regs, active);
2359 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2360 const struct i915_oa_config *oa_config,
2361 struct i915_active *active)
2363 struct flex regs[] = {
2365 GEN8_R_PWR_CLK_STATE,
2366 CTX_R_PWR_CLK_STATE,
2370 return oa_configure_all_contexts(stream,
2371 regs, ARRAY_SIZE(regs),
2376 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2377 const struct i915_oa_config *oa_config,
2378 struct i915_active *active)
2380 /* The MMIO offsets for Flex EU registers aren't contiguous */
2381 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2382 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2383 struct flex regs[] = {
2385 GEN8_R_PWR_CLK_STATE,
2386 CTX_R_PWR_CLK_STATE,
2390 stream->perf->ctx_oactxctrl_offset + 1,
2392 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2393 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2394 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2395 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2396 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2397 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2398 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2404 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2405 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2406 GEN8_OA_COUNTER_RESUME;
2408 for (i = 2; i < ARRAY_SIZE(regs); i++)
2409 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2411 return oa_configure_all_contexts(stream,
2412 regs, ARRAY_SIZE(regs),
2417 gen8_enable_metric_set(struct i915_perf_stream *stream,
2418 struct i915_active *active)
2420 struct intel_uncore *uncore = stream->uncore;
2421 struct i915_oa_config *oa_config = stream->oa_config;
2425 * We disable slice/unslice clock ratio change reports on SKL since
2426 * they are too noisy. The HW generates a lot of redundant reports
2427 * where the ratio hasn't really changed causing a lot of redundant
2428 * work to processes and increasing the chances we'll hit buffer
2431 * Although we don't currently use the 'disable overrun' OABUFFER
2432 * feature it's worth noting that clock ratio reports have to be
2433 * disabled before considering to use that feature since the HW doesn't
2434 * correctly block these reports.
2436 * Currently none of the high-level metrics we have depend on knowing
2437 * this ratio to normalize.
2439 * Note: This register is not power context saved and restored, but
2440 * that's OK considering that we disable RC6 while the OA unit is
2443 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2444 * be read back from automatically triggered reports, as part of the
2447 if (IS_GEN_RANGE(stream->perf->i915, 9, 11)) {
2448 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2449 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2450 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2454 * Update all contexts prior writing the mux configurations as we need
2455 * to make sure all slices/subslices are ON before writing to NOA
2458 ret = lrc_configure_all_contexts(stream, oa_config, active);
2462 return emit_oa_config(stream,
2463 stream->oa_config, oa_context(stream),
2467 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2469 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2470 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2471 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2475 gen12_enable_metric_set(struct i915_perf_stream *stream,
2476 struct i915_active *active)
2478 struct intel_uncore *uncore = stream->uncore;
2479 struct i915_oa_config *oa_config = stream->oa_config;
2480 bool periodic = stream->periodic;
2481 u32 period_exponent = stream->period_exponent;
2484 intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
2485 /* Disable clk ratio reports, like previous Gens. */
2486 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2487 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2489 * If the user didn't require OA reports, instruct
2490 * the hardware not to emit ctx switch reports.
2492 oag_report_ctx_switches(stream));
2494 intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
2495 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2496 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2497 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2501 * Update all contexts prior writing the mux configurations as we need
2502 * to make sure all slices/subslices are ON before writing to NOA
2505 ret = gen12_configure_all_contexts(stream, oa_config, active);
2510 * For Gen12, performance counters are context
2511 * saved/restored. Only enable it for the context that
2515 ret = gen12_configure_oar_context(stream, active);
2520 return emit_oa_config(stream,
2521 stream->oa_config, oa_context(stream),
2525 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2527 struct intel_uncore *uncore = stream->uncore;
2529 /* Reset all contexts' slices/subslices configurations. */
2530 lrc_configure_all_contexts(stream, NULL, NULL);
2532 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2535 static void gen10_disable_metric_set(struct i915_perf_stream *stream)
2537 struct intel_uncore *uncore = stream->uncore;
2539 /* Reset all contexts' slices/subslices configurations. */
2540 lrc_configure_all_contexts(stream, NULL, NULL);
2542 /* Make sure we disable noa to save power. */
2543 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2546 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2548 struct intel_uncore *uncore = stream->uncore;
2550 /* Reset all contexts' slices/subslices configurations. */
2551 gen12_configure_all_contexts(stream, NULL, NULL);
2553 /* disable the context save/restore or OAR counters */
2555 gen12_configure_oar_context(stream, NULL);
2557 /* Make sure we disable noa to save power. */
2558 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2561 static void gen7_oa_enable(struct i915_perf_stream *stream)
2563 struct intel_uncore *uncore = stream->uncore;
2564 struct i915_gem_context *ctx = stream->ctx;
2565 u32 ctx_id = stream->specific_ctx_id;
2566 bool periodic = stream->periodic;
2567 u32 period_exponent = stream->period_exponent;
2568 u32 report_format = stream->oa_buffer.format;
2571 * Reset buf pointers so we don't forward reports from before now.
2573 * Think carefully if considering trying to avoid this, since it
2574 * also ensures status flags and the buffer itself are cleared
2575 * in error paths, and we have checks for invalid reports based
2576 * on the assumption that certain fields are written to zeroed
2577 * memory which this helps maintains.
2579 gen7_init_oa_buffer(stream);
2581 intel_uncore_write(uncore, GEN7_OACONTROL,
2582 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
2584 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
2585 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
2586 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
2587 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
2588 GEN7_OACONTROL_ENABLE);
2591 static void gen8_oa_enable(struct i915_perf_stream *stream)
2593 struct intel_uncore *uncore = stream->uncore;
2594 u32 report_format = stream->oa_buffer.format;
2597 * Reset buf pointers so we don't forward reports from before now.
2599 * Think carefully if considering trying to avoid this, since it
2600 * also ensures status flags and the buffer itself are cleared
2601 * in error paths, and we have checks for invalid reports based
2602 * on the assumption that certain fields are written to zeroed
2603 * memory which this helps maintains.
2605 gen8_init_oa_buffer(stream);
2608 * Note: we don't rely on the hardware to perform single context
2609 * filtering and instead filter on the cpu based on the context-id
2612 intel_uncore_write(uncore, GEN8_OACONTROL,
2613 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
2614 GEN8_OA_COUNTER_ENABLE);
2617 static void gen12_oa_enable(struct i915_perf_stream *stream)
2619 struct intel_uncore *uncore = stream->uncore;
2620 u32 report_format = stream->oa_buffer.format;
2623 * If we don't want OA reports from the OA buffer, then we don't even
2624 * need to program the OAG unit.
2626 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
2629 gen12_init_oa_buffer(stream);
2631 intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
2632 (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
2633 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
2637 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
2638 * @stream: An i915 perf stream opened for OA metrics
2640 * [Re]enables hardware periodic sampling according to the period configured
2641 * when opening the stream. This also starts a hrtimer that will periodically
2642 * check for data in the circular OA buffer for notifying userspace (e.g.
2643 * during a read() or poll()).
2645 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
2647 stream->pollin = false;
2649 stream->perf->ops.oa_enable(stream);
2651 if (stream->periodic)
2652 hrtimer_start(&stream->poll_check_timer,
2653 ns_to_ktime(stream->poll_oa_period),
2654 HRTIMER_MODE_REL_PINNED);
2657 static void gen7_oa_disable(struct i915_perf_stream *stream)
2659 struct intel_uncore *uncore = stream->uncore;
2661 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
2662 if (intel_wait_for_register(uncore,
2663 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
2665 drm_err(&stream->perf->i915->drm,
2666 "wait for OA to be disabled timed out\n");
2669 static void gen8_oa_disable(struct i915_perf_stream *stream)
2671 struct intel_uncore *uncore = stream->uncore;
2673 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
2674 if (intel_wait_for_register(uncore,
2675 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
2677 drm_err(&stream->perf->i915->drm,
2678 "wait for OA to be disabled timed out\n");
2681 static void gen12_oa_disable(struct i915_perf_stream *stream)
2683 struct intel_uncore *uncore = stream->uncore;
2685 intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
2686 if (intel_wait_for_register(uncore,
2687 GEN12_OAG_OACONTROL,
2688 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
2690 drm_err(&stream->perf->i915->drm,
2691 "wait for OA to be disabled timed out\n");
2693 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
2694 if (intel_wait_for_register(uncore,
2695 GEN12_OA_TLB_INV_CR,
2698 drm_err(&stream->perf->i915->drm,
2699 "wait for OA tlb invalidate timed out\n");
2703 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
2704 * @stream: An i915 perf stream opened for OA metrics
2706 * Stops the OA unit from periodically writing counter reports into the
2707 * circular OA buffer. This also stops the hrtimer that periodically checks for
2708 * data in the circular OA buffer, for notifying userspace.
2710 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
2712 stream->perf->ops.oa_disable(stream);
2714 if (stream->periodic)
2715 hrtimer_cancel(&stream->poll_check_timer);
2718 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
2719 .destroy = i915_oa_stream_destroy,
2720 .enable = i915_oa_stream_enable,
2721 .disable = i915_oa_stream_disable,
2722 .wait_unlocked = i915_oa_wait_unlocked,
2723 .poll_wait = i915_oa_poll_wait,
2724 .read = i915_oa_read,
2727 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
2729 struct i915_active *active;
2732 active = i915_active_create();
2736 err = stream->perf->ops.enable_metric_set(stream, active);
2738 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
2740 i915_active_put(active);
2745 get_default_sseu_config(struct intel_sseu *out_sseu,
2746 struct intel_engine_cs *engine)
2748 const struct sseu_dev_info *devinfo_sseu =
2749 &RUNTIME_INFO(engine->i915)->sseu;
2751 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
2753 if (IS_GEN(engine->i915, 11)) {
2755 * We only need subslice count so it doesn't matter which ones
2756 * we select - just turn off low bits in the amount of half of
2757 * all available subslices per slice.
2759 out_sseu->subslice_mask =
2760 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
2761 out_sseu->slice_mask = 0x1;
2766 get_sseu_config(struct intel_sseu *out_sseu,
2767 struct intel_engine_cs *engine,
2768 const struct drm_i915_gem_context_param_sseu *drm_sseu)
2770 if (drm_sseu->engine.engine_class != engine->uabi_class ||
2771 drm_sseu->engine.engine_instance != engine->uabi_instance)
2774 return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu);
2778 * i915_oa_stream_init - validate combined props for OA stream and init
2779 * @stream: An i915 perf stream
2780 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
2781 * @props: The property state that configures stream (individually validated)
2783 * While read_properties_unlocked() validates properties in isolation it
2784 * doesn't ensure that the combination necessarily makes sense.
2786 * At this point it has been determined that userspace wants a stream of
2787 * OA metrics, but still we need to further validate the combined
2788 * properties are OK.
2790 * If the configuration makes sense then we can allocate memory for
2791 * a circular OA buffer and apply the requested metric set configuration.
2793 * Returns: zero on success or a negative error code.
2795 static int i915_oa_stream_init(struct i915_perf_stream *stream,
2796 struct drm_i915_perf_open_param *param,
2797 struct perf_open_properties *props)
2799 struct drm_i915_private *i915 = stream->perf->i915;
2800 struct i915_perf *perf = stream->perf;
2804 if (!props->engine) {
2805 DRM_DEBUG("OA engine not specified\n");
2810 * If the sysfs metrics/ directory wasn't registered for some
2811 * reason then don't let userspace try their luck with config
2814 if (!perf->metrics_kobj) {
2815 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
2819 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
2820 (INTEL_GEN(perf->i915) < 12 || !stream->ctx)) {
2821 DRM_DEBUG("Only OA report sampling supported\n");
2825 if (!perf->ops.enable_metric_set) {
2826 DRM_DEBUG("OA unit not supported\n");
2831 * To avoid the complexity of having to accurately filter
2832 * counter reports and marshal to the appropriate client
2833 * we currently only allow exclusive access
2835 if (perf->exclusive_stream) {
2836 DRM_DEBUG("OA unit already in use\n");
2840 if (!props->oa_format) {
2841 DRM_DEBUG("OA report format not specified\n");
2845 stream->engine = props->engine;
2846 stream->uncore = stream->engine->gt->uncore;
2848 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
2850 format_size = perf->oa_formats[props->oa_format].size;
2852 stream->sample_flags = props->sample_flags;
2853 stream->sample_size += format_size;
2855 stream->oa_buffer.format_size = format_size;
2856 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format_size == 0))
2859 stream->hold_preemption = props->hold_preemption;
2861 stream->oa_buffer.format =
2862 perf->oa_formats[props->oa_format].format;
2864 stream->periodic = props->oa_periodic;
2865 if (stream->periodic)
2866 stream->period_exponent = props->oa_period_exponent;
2869 ret = oa_get_render_ctx_id(stream);
2871 DRM_DEBUG("Invalid context id to filter with\n");
2876 ret = alloc_noa_wait(stream);
2878 DRM_DEBUG("Unable to allocate NOA wait batch buffer\n");
2879 goto err_noa_wait_alloc;
2882 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
2883 if (!stream->oa_config) {
2884 DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
2889 /* PRM - observability performance counters:
2891 * OACONTROL, performance counter enable, note:
2893 * "When this bit is set, in order to have coherent counts,
2894 * RC6 power state and trunk clock gating must be disabled.
2895 * This can be achieved by programming MMIO registers as
2896 * 0xA094=0 and 0xA090[31]=1"
2898 * In our case we are expecting that taking pm + FORCEWAKE
2899 * references will effectively disable RC6.
2901 intel_engine_pm_get(stream->engine);
2902 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
2904 ret = alloc_oa_buffer(stream);
2906 goto err_oa_buf_alloc;
2908 stream->ops = &i915_oa_stream_ops;
2910 perf->sseu = props->sseu;
2911 WRITE_ONCE(perf->exclusive_stream, stream);
2913 ret = i915_perf_stream_enable_sync(stream);
2915 DRM_DEBUG("Unable to enable metric set\n");
2919 DRM_DEBUG("opening stream oa config uuid=%s\n",
2920 stream->oa_config->uuid);
2922 hrtimer_init(&stream->poll_check_timer,
2923 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2924 stream->poll_check_timer.function = oa_poll_check_timer_cb;
2925 init_waitqueue_head(&stream->poll_wq);
2926 spin_lock_init(&stream->oa_buffer.ptr_lock);
2931 WRITE_ONCE(perf->exclusive_stream, NULL);
2932 perf->ops.disable_metric_set(stream);
2934 free_oa_buffer(stream);
2937 free_oa_configs(stream);
2939 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
2940 intel_engine_pm_put(stream->engine);
2943 free_noa_wait(stream);
2947 oa_put_render_ctx_id(stream);
2952 void i915_oa_init_reg_state(const struct intel_context *ce,
2953 const struct intel_engine_cs *engine)
2955 struct i915_perf_stream *stream;
2957 if (engine->class != RENDER_CLASS)
2960 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
2961 stream = READ_ONCE(engine->i915->perf.exclusive_stream);
2962 if (stream && INTEL_GEN(stream->perf->i915) < 12)
2963 gen8_update_reg_state_unlocked(ce, stream);
2967 * i915_perf_read - handles read() FOP for i915 perf stream FDs
2968 * @file: An i915 perf stream file
2969 * @buf: destination buffer given by userspace
2970 * @count: the number of bytes userspace wants to read
2971 * @ppos: (inout) file seek position (unused)
2973 * The entry point for handling a read() on a stream file descriptor from
2974 * userspace. Most of the work is left to the i915_perf_read_locked() and
2975 * &i915_perf_stream_ops->read but to save having stream implementations (of
2976 * which we might have multiple later) we handle blocking read here.
2978 * We can also consistently treat trying to read from a disabled stream
2979 * as an IO error so implementations can assume the stream is enabled
2982 * Returns: The number of bytes copied or a negative error code on failure.
2984 static ssize_t i915_perf_read(struct file *file,
2989 struct i915_perf_stream *stream = file->private_data;
2990 struct i915_perf *perf = stream->perf;
2994 /* To ensure it's handled consistently we simply treat all reads of a
2995 * disabled stream as an error. In particular it might otherwise lead
2996 * to a deadlock for blocking file descriptors...
2998 if (!stream->enabled)
3001 if (!(file->f_flags & O_NONBLOCK)) {
3002 /* There's the small chance of false positives from
3003 * stream->ops->wait_unlocked.
3005 * E.g. with single context filtering since we only wait until
3006 * oabuffer has >= 1 report we don't immediately know whether
3007 * any reports really belong to the current context
3010 ret = stream->ops->wait_unlocked(stream);
3014 mutex_lock(&perf->lock);
3015 ret = stream->ops->read(stream, buf, count, &offset);
3016 mutex_unlock(&perf->lock);
3017 } while (!offset && !ret);
3019 mutex_lock(&perf->lock);
3020 ret = stream->ops->read(stream, buf, count, &offset);
3021 mutex_unlock(&perf->lock);
3024 /* We allow the poll checking to sometimes report false positive EPOLLIN
3025 * events where we might actually report EAGAIN on read() if there's
3026 * not really any data available. In this situation though we don't
3027 * want to enter a busy loop between poll() reporting a EPOLLIN event
3028 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3029 * effectively ensures we back off until the next hrtimer callback
3030 * before reporting another EPOLLIN event.
3031 * The exception to this is if ops->read() returned -ENOSPC which means
3032 * that more OA data is available than could fit in the user provided
3033 * buffer. In this case we want the next poll() call to not block.
3036 stream->pollin = false;
3038 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3039 return offset ?: (ret ?: -EAGAIN);
3042 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3044 struct i915_perf_stream *stream =
3045 container_of(hrtimer, typeof(*stream), poll_check_timer);
3047 if (oa_buffer_check_unlocked(stream)) {
3048 stream->pollin = true;
3049 wake_up(&stream->poll_wq);
3052 hrtimer_forward_now(hrtimer,
3053 ns_to_ktime(stream->poll_oa_period));
3055 return HRTIMER_RESTART;
3059 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3060 * @stream: An i915 perf stream
3061 * @file: An i915 perf stream file
3062 * @wait: poll() state table
3064 * For handling userspace polling on an i915 perf stream, this calls through to
3065 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3066 * will be woken for new stream data.
3068 * Note: The &perf->lock mutex has been taken to serialize
3069 * with any non-file-operation driver hooks.
3071 * Returns: any poll events that are ready without sleeping
3073 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3077 __poll_t events = 0;
3079 stream->ops->poll_wait(stream, file, wait);
3081 /* Note: we don't explicitly check whether there's something to read
3082 * here since this path may be very hot depending on what else
3083 * userspace is polling, or on the timeout in use. We rely solely on
3084 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3094 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3095 * @file: An i915 perf stream file
3096 * @wait: poll() state table
3098 * For handling userspace polling on an i915 perf stream, this ensures
3099 * poll_wait() gets called with a wait queue that will be woken for new stream
3102 * Note: Implementation deferred to i915_perf_poll_locked()
3104 * Returns: any poll events that are ready without sleeping
3106 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3108 struct i915_perf_stream *stream = file->private_data;
3109 struct i915_perf *perf = stream->perf;
3112 mutex_lock(&perf->lock);
3113 ret = i915_perf_poll_locked(stream, file, wait);
3114 mutex_unlock(&perf->lock);
3120 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3121 * @stream: A disabled i915 perf stream
3123 * [Re]enables the associated capture of data for this stream.
3125 * If a stream was previously enabled then there's currently no intention
3126 * to provide userspace any guarantee about the preservation of previously
3129 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3131 if (stream->enabled)
3134 /* Allow stream->ops->enable() to refer to this */
3135 stream->enabled = true;
3137 if (stream->ops->enable)
3138 stream->ops->enable(stream);
3140 if (stream->hold_preemption)
3141 intel_context_set_nopreempt(stream->pinned_ctx);
3145 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3146 * @stream: An enabled i915 perf stream
3148 * Disables the associated capture of data for this stream.
3150 * The intention is that disabling an re-enabling a stream will ideally be
3151 * cheaper than destroying and re-opening a stream with the same configuration,
3152 * though there are no formal guarantees about what state or buffered data
3153 * must be retained between disabling and re-enabling a stream.
3155 * Note: while a stream is disabled it's considered an error for userspace
3156 * to attempt to read from the stream (-EIO).
3158 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3160 if (!stream->enabled)
3163 /* Allow stream->ops->disable() to refer to this */
3164 stream->enabled = false;
3166 if (stream->hold_preemption)
3167 intel_context_clear_nopreempt(stream->pinned_ctx);
3169 if (stream->ops->disable)
3170 stream->ops->disable(stream);
3173 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3174 unsigned long metrics_set)
3176 struct i915_oa_config *config;
3177 long ret = stream->oa_config->id;
3179 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3183 if (config != stream->oa_config) {
3187 * If OA is bound to a specific context, emit the
3188 * reconfiguration inline from that context. The update
3189 * will then be ordered with respect to submission on that
3192 * When set globally, we use a low priority kernel context,
3193 * so it will effectively take effect when idle.
3195 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3197 config = xchg(&stream->oa_config, config);
3202 i915_oa_config_put(config);
3208 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3209 * @stream: An i915 perf stream
3210 * @cmd: the ioctl request
3211 * @arg: the ioctl data
3213 * Note: The &perf->lock mutex has been taken to serialize
3214 * with any non-file-operation driver hooks.
3216 * Returns: zero on success or a negative error code. Returns -EINVAL for
3217 * an unknown ioctl request.
3219 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3224 case I915_PERF_IOCTL_ENABLE:
3225 i915_perf_enable_locked(stream);
3227 case I915_PERF_IOCTL_DISABLE:
3228 i915_perf_disable_locked(stream);
3230 case I915_PERF_IOCTL_CONFIG:
3231 return i915_perf_config_locked(stream, arg);
3238 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3239 * @file: An i915 perf stream file
3240 * @cmd: the ioctl request
3241 * @arg: the ioctl data
3243 * Implementation deferred to i915_perf_ioctl_locked().
3245 * Returns: zero on success or a negative error code. Returns -EINVAL for
3246 * an unknown ioctl request.
3248 static long i915_perf_ioctl(struct file *file,
3252 struct i915_perf_stream *stream = file->private_data;
3253 struct i915_perf *perf = stream->perf;
3256 mutex_lock(&perf->lock);
3257 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3258 mutex_unlock(&perf->lock);
3264 * i915_perf_destroy_locked - destroy an i915 perf stream
3265 * @stream: An i915 perf stream
3267 * Frees all resources associated with the given i915 perf @stream, disabling
3268 * any associated data capture in the process.
3270 * Note: The &perf->lock mutex has been taken to serialize
3271 * with any non-file-operation driver hooks.
3273 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3275 if (stream->enabled)
3276 i915_perf_disable_locked(stream);
3278 if (stream->ops->destroy)
3279 stream->ops->destroy(stream);
3282 i915_gem_context_put(stream->ctx);
3288 * i915_perf_release - handles userspace close() of a stream file
3289 * @inode: anonymous inode associated with file
3290 * @file: An i915 perf stream file
3292 * Cleans up any resources associated with an open i915 perf stream file.
3294 * NB: close() can't really fail from the userspace point of view.
3296 * Returns: zero on success or a negative error code.
3298 static int i915_perf_release(struct inode *inode, struct file *file)
3300 struct i915_perf_stream *stream = file->private_data;
3301 struct i915_perf *perf = stream->perf;
3303 mutex_lock(&perf->lock);
3304 i915_perf_destroy_locked(stream);
3305 mutex_unlock(&perf->lock);
3307 /* Release the reference the perf stream kept on the driver. */
3308 drm_dev_put(&perf->i915->drm);
3314 static const struct file_operations fops = {
3315 .owner = THIS_MODULE,
3316 .llseek = no_llseek,
3317 .release = i915_perf_release,
3318 .poll = i915_perf_poll,
3319 .read = i915_perf_read,
3320 .unlocked_ioctl = i915_perf_ioctl,
3321 /* Our ioctl have no arguments, so it's safe to use the same function
3322 * to handle 32bits compatibility.
3324 .compat_ioctl = i915_perf_ioctl,
3329 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3330 * @perf: i915 perf instance
3331 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3332 * @props: individually validated u64 property value pairs
3335 * See i915_perf_ioctl_open() for interface details.
3337 * Implements further stream config validation and stream initialization on
3338 * behalf of i915_perf_open_ioctl() with the &perf->lock mutex
3339 * taken to serialize with any non-file-operation driver hooks.
3341 * Note: at this point the @props have only been validated in isolation and
3342 * it's still necessary to validate that the combination of properties makes
3345 * In the case where userspace is interested in OA unit metrics then further
3346 * config validation and stream initialization details will be handled by
3347 * i915_oa_stream_init(). The code here should only validate config state that
3348 * will be relevant to all stream types / backends.
3350 * Returns: zero on success or a negative error code.
3353 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3354 struct drm_i915_perf_open_param *param,
3355 struct perf_open_properties *props,
3356 struct drm_file *file)
3358 struct i915_gem_context *specific_ctx = NULL;
3359 struct i915_perf_stream *stream = NULL;
3360 unsigned long f_flags = 0;
3361 bool privileged_op = true;
3365 if (props->single_context) {
3366 u32 ctx_handle = props->ctx_handle;
3367 struct drm_i915_file_private *file_priv = file->driver_priv;
3369 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3370 if (!specific_ctx) {
3371 DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n",
3379 * On Haswell the OA unit supports clock gating off for a specific
3380 * context and in this mode there's no visibility of metrics for the
3381 * rest of the system, which we consider acceptable for a
3382 * non-privileged client.
3384 * For Gen8->11 the OA unit no longer supports clock gating off for a
3385 * specific context and the kernel can't securely stop the counters
3386 * from updating as system-wide / global values. Even though we can
3387 * filter reports based on the included context ID we can't block
3388 * clients from seeing the raw / global counter values via
3389 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3390 * enable the OA unit by default.
3392 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3393 * per context basis. So we can relax requirements there if the user
3394 * doesn't request global stream access (i.e. query based sampling
3395 * using MI_RECORD_PERF_COUNT.
3397 if (IS_HASWELL(perf->i915) && specific_ctx)
3398 privileged_op = false;
3399 else if (IS_GEN(perf->i915, 12) && specific_ctx &&
3400 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3401 privileged_op = false;
3403 if (props->hold_preemption) {
3404 if (!props->single_context) {
3405 DRM_DEBUG("preemption disable with no context\n");
3409 privileged_op = true;
3413 * Asking for SSEU configuration is a priviliged operation.
3415 if (props->has_sseu)
3416 privileged_op = true;
3418 get_default_sseu_config(&props->sseu, props->engine);
3420 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3421 * we check a dev.i915.perf_stream_paranoid sysctl option
3422 * to determine if it's ok to access system wide OA counters
3423 * without CAP_SYS_ADMIN privileges.
3425 if (privileged_op &&
3426 i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
3427 DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
3432 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3438 stream->perf = perf;
3439 stream->ctx = specific_ctx;
3440 stream->poll_oa_period = props->poll_oa_period;
3442 ret = i915_oa_stream_init(stream, param, props);
3446 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3447 * to have _stream_init check the combination of sample flags more
3448 * thoroughly, but still this is the expected result at this point.
3450 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3455 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3456 f_flags |= O_CLOEXEC;
3457 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3458 f_flags |= O_NONBLOCK;
3460 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3461 if (stream_fd < 0) {
3466 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3467 i915_perf_enable_locked(stream);
3469 /* Take a reference on the driver that will be kept with stream_fd
3470 * until its release.
3472 drm_dev_get(&perf->i915->drm);
3477 if (stream->ops->destroy)
3478 stream->ops->destroy(stream);
3483 i915_gem_context_put(specific_ctx);
3488 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3490 return div64_u64(1000000000ULL * (2ULL << exponent),
3491 1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
3495 * read_properties_unlocked - validate + copy userspace stream open properties
3496 * @perf: i915 perf instance
3497 * @uprops: The array of u64 key value pairs given by userspace
3498 * @n_props: The number of key value pairs expected in @uprops
3499 * @props: The stream configuration built up while validating properties
3501 * Note this function only validates properties in isolation it doesn't
3502 * validate that the combination of properties makes sense or that all
3503 * properties necessary for a particular kind of stream have been set.
3505 * Note that there currently aren't any ordering requirements for properties so
3506 * we shouldn't validate or assume anything about ordering here. This doesn't
3507 * rule out defining new properties with ordering requirements in the future.
3509 static int read_properties_unlocked(struct i915_perf *perf,
3512 struct perf_open_properties *props)
3514 u64 __user *uprop = uprops;
3518 memset(props, 0, sizeof(struct perf_open_properties));
3519 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
3522 DRM_DEBUG("No i915 perf properties given\n");
3526 /* At the moment we only support using i915-perf on the RCS. */
3527 props->engine = intel_engine_lookup_user(perf->i915,
3528 I915_ENGINE_CLASS_RENDER,
3530 if (!props->engine) {
3531 DRM_DEBUG("No RENDER-capable engines\n");
3535 /* Considering that ID = 0 is reserved and assuming that we don't
3536 * (currently) expect any configurations to ever specify duplicate
3537 * values for a particular property ID then the last _PROP_MAX value is
3538 * one greater than the maximum number of properties we expect to get
3541 if (n_props >= DRM_I915_PERF_PROP_MAX) {
3542 DRM_DEBUG("More i915 perf properties specified than exist\n");
3546 for (i = 0; i < n_props; i++) {
3547 u64 oa_period, oa_freq_hz;
3550 ret = get_user(id, uprop);
3554 ret = get_user(value, uprop + 1);
3558 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
3559 DRM_DEBUG("Unknown i915 perf property ID\n");
3563 switch ((enum drm_i915_perf_property_id)id) {
3564 case DRM_I915_PERF_PROP_CTX_HANDLE:
3565 props->single_context = 1;
3566 props->ctx_handle = value;
3568 case DRM_I915_PERF_PROP_SAMPLE_OA:
3570 props->sample_flags |= SAMPLE_OA_REPORT;
3572 case DRM_I915_PERF_PROP_OA_METRICS_SET:
3574 DRM_DEBUG("Unknown OA metric set ID\n");
3577 props->metrics_set = value;
3579 case DRM_I915_PERF_PROP_OA_FORMAT:
3580 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
3581 DRM_DEBUG("Out-of-range OA report format %llu\n",
3585 if (!perf->oa_formats[value].size) {
3586 DRM_DEBUG("Unsupported OA report format %llu\n",
3590 props->oa_format = value;
3592 case DRM_I915_PERF_PROP_OA_EXPONENT:
3593 if (value > OA_EXPONENT_MAX) {
3594 DRM_DEBUG("OA timer exponent too high (> %u)\n",
3599 /* Theoretically we can program the OA unit to sample
3600 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
3601 * for BXT. We don't allow such high sampling
3602 * frequencies by default unless root.
3605 BUILD_BUG_ON(sizeof(oa_period) != 8);
3606 oa_period = oa_exponent_to_ns(perf, value);
3608 /* This check is primarily to ensure that oa_period <=
3609 * UINT32_MAX (before passing to do_div which only
3610 * accepts a u32 denominator), but we can also skip
3611 * checking anything < 1Hz which implicitly can't be
3612 * limited via an integer oa_max_sample_rate.
3614 if (oa_period <= NSEC_PER_SEC) {
3615 u64 tmp = NSEC_PER_SEC;
3616 do_div(tmp, oa_period);
3621 if (oa_freq_hz > i915_oa_max_sample_rate &&
3622 !capable(CAP_SYS_ADMIN)) {
3623 DRM_DEBUG("OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without root privileges\n",
3624 i915_oa_max_sample_rate);
3628 props->oa_periodic = true;
3629 props->oa_period_exponent = value;
3631 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
3632 props->hold_preemption = !!value;
3634 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
3635 struct drm_i915_gem_context_param_sseu user_sseu;
3637 if (copy_from_user(&user_sseu,
3638 u64_to_user_ptr(value),
3639 sizeof(user_sseu))) {
3640 DRM_DEBUG("Unable to copy global sseu parameter\n");
3644 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
3646 DRM_DEBUG("Invalid SSEU configuration\n");
3649 props->has_sseu = true;
3652 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
3653 if (value < 100000 /* 100us */) {
3654 DRM_DEBUG("OA availability timer too small (%lluns < 100us)\n",
3658 props->poll_oa_period = value;
3660 case DRM_I915_PERF_PROP_MAX:
3672 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
3674 * @data: ioctl data copied from userspace (unvalidated)
3677 * Validates the stream open parameters given by userspace including flags
3678 * and an array of u64 key, value pair properties.
3680 * Very little is assumed up front about the nature of the stream being
3681 * opened (for instance we don't assume it's for periodic OA unit metrics). An
3682 * i915-perf stream is expected to be a suitable interface for other forms of
3683 * buffered data written by the GPU besides periodic OA metrics.
3685 * Note we copy the properties from userspace outside of the i915 perf
3686 * mutex to avoid an awkward lockdep with mmap_sem.
3688 * Most of the implementation details are handled by
3689 * i915_perf_open_ioctl_locked() after taking the &perf->lock
3690 * mutex for serializing with any non-file-operation driver hooks.
3692 * Return: A newly opened i915 Perf stream file descriptor or negative
3693 * error code on failure.
3695 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3696 struct drm_file *file)
3698 struct i915_perf *perf = &to_i915(dev)->perf;
3699 struct drm_i915_perf_open_param *param = data;
3700 struct perf_open_properties props;
3701 u32 known_open_flags;
3705 DRM_DEBUG("i915 perf interface not available for this system\n");
3709 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
3710 I915_PERF_FLAG_FD_NONBLOCK |
3711 I915_PERF_FLAG_DISABLED;
3712 if (param->flags & ~known_open_flags) {
3713 DRM_DEBUG("Unknown drm_i915_perf_open_param flag\n");
3717 ret = read_properties_unlocked(perf,
3718 u64_to_user_ptr(param->properties_ptr),
3719 param->num_properties,
3724 mutex_lock(&perf->lock);
3725 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
3726 mutex_unlock(&perf->lock);
3732 * i915_perf_register - exposes i915-perf to userspace
3733 * @i915: i915 device instance
3735 * In particular OA metric sets are advertised under a sysfs metrics/
3736 * directory allowing userspace to enumerate valid IDs that can be
3737 * used to open an i915-perf stream.
3739 void i915_perf_register(struct drm_i915_private *i915)
3741 struct i915_perf *perf = &i915->perf;
3746 /* To be sure we're synchronized with an attempted
3747 * i915_perf_open_ioctl(); considering that we register after
3748 * being exposed to userspace.
3750 mutex_lock(&perf->lock);
3752 perf->metrics_kobj =
3753 kobject_create_and_add("metrics",
3754 &i915->drm.primary->kdev->kobj);
3756 mutex_unlock(&perf->lock);
3760 * i915_perf_unregister - hide i915-perf from userspace
3761 * @i915: i915 device instance
3763 * i915-perf state cleanup is split up into an 'unregister' and
3764 * 'deinit' phase where the interface is first hidden from
3765 * userspace by i915_perf_unregister() before cleaning up
3766 * remaining state in i915_perf_fini().
3768 void i915_perf_unregister(struct drm_i915_private *i915)
3770 struct i915_perf *perf = &i915->perf;
3772 if (!perf->metrics_kobj)
3775 kobject_put(perf->metrics_kobj);
3776 perf->metrics_kobj = NULL;
3779 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
3781 static const i915_reg_t flex_eu_regs[] = {
3792 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
3793 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
3799 #define ADDR_IN_RANGE(addr, start, end) \
3800 ((addr) >= (start) && \
3803 #define REG_IN_RANGE(addr, start, end) \
3804 ((addr) >= i915_mmio_reg_offset(start) && \
3805 (addr) <= i915_mmio_reg_offset(end))
3807 #define REG_EQUAL(addr, mmio) \
3808 ((addr) == i915_mmio_reg_offset(mmio))
3810 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3812 return REG_IN_RANGE(addr, OASTARTTRIG1, OASTARTTRIG8) ||
3813 REG_IN_RANGE(addr, OAREPORTTRIG1, OAREPORTTRIG8) ||
3814 REG_IN_RANGE(addr, OACEC0_0, OACEC7_1);
3817 static bool gen7_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3819 return REG_EQUAL(addr, HALF_SLICE_CHICKEN2) ||
3820 REG_IN_RANGE(addr, MICRO_BP0_0, NOA_WRITE) ||
3821 REG_IN_RANGE(addr, OA_PERFCNT1_LO, OA_PERFCNT2_HI) ||
3822 REG_IN_RANGE(addr, OA_PERFMATRIX_LO, OA_PERFMATRIX_HI);
3825 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3827 return gen7_is_valid_mux_addr(perf, addr) ||
3828 REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3829 REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
3832 static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3834 return gen8_is_valid_mux_addr(perf, addr) ||
3835 REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3836 REG_IN_RANGE(addr, OA_PERFCNT3_LO, OA_PERFCNT4_HI);
3839 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3841 return gen7_is_valid_mux_addr(perf, addr) ||
3842 ADDR_IN_RANGE(addr, 0x25100, 0x2FF90) ||
3843 REG_IN_RANGE(addr, HSW_MBVID2_NOA0, HSW_MBVID2_NOA9) ||
3844 REG_EQUAL(addr, HSW_MBVID2_MISR0);
3847 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3849 return gen7_is_valid_mux_addr(perf, addr) ||
3850 ADDR_IN_RANGE(addr, 0x182300, 0x1823A4);
3853 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3855 return REG_IN_RANGE(addr, GEN12_OAG_OASTARTTRIG1, GEN12_OAG_OASTARTTRIG8) ||
3856 REG_IN_RANGE(addr, GEN12_OAG_OAREPORTTRIG1, GEN12_OAG_OAREPORTTRIG8) ||
3857 REG_IN_RANGE(addr, GEN12_OAG_CEC0_0, GEN12_OAG_CEC7_1) ||
3858 REG_IN_RANGE(addr, GEN12_OAG_SCEC0_0, GEN12_OAG_SCEC7_1) ||
3859 REG_EQUAL(addr, GEN12_OAA_DBG_REG) ||
3860 REG_EQUAL(addr, GEN12_OAG_OA_PESS) ||
3861 REG_EQUAL(addr, GEN12_OAG_SPCTR_CNF);
3864 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3866 return REG_EQUAL(addr, NOA_WRITE) ||
3867 REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
3868 REG_EQUAL(addr, GDT_CHICKEN_BITS) ||
3869 REG_EQUAL(addr, WAIT_FOR_RC6_EXIT) ||
3870 REG_EQUAL(addr, RPM_CONFIG0) ||
3871 REG_EQUAL(addr, RPM_CONFIG1) ||
3872 REG_IN_RANGE(addr, NOA_CONFIG(0), NOA_CONFIG(8));
3875 static u32 mask_reg_value(u32 reg, u32 val)
3877 /* HALF_SLICE_CHICKEN2 is programmed with a the
3878 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
3879 * programmed by userspace doesn't change this.
3881 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
3882 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
3884 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
3885 * indicated by its name and a bunch of selection fields used by OA
3888 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
3889 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
3894 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
3895 bool (*is_valid)(struct i915_perf *perf, u32 addr),
3899 struct i915_oa_reg *oa_regs;
3906 if (!access_ok(regs, n_regs * sizeof(u32) * 2))
3907 return ERR_PTR(-EFAULT);
3909 /* No is_valid function means we're not allowing any register to be programmed. */
3910 GEM_BUG_ON(!is_valid);
3912 return ERR_PTR(-EINVAL);
3914 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
3916 return ERR_PTR(-ENOMEM);
3918 for (i = 0; i < n_regs; i++) {
3921 err = get_user(addr, regs);
3925 if (!is_valid(perf, addr)) {
3926 DRM_DEBUG("Invalid oa_reg address: %X\n", addr);
3931 err = get_user(value, regs + 1);
3935 oa_regs[i].addr = _MMIO(addr);
3936 oa_regs[i].value = mask_reg_value(addr, value);
3945 return ERR_PTR(err);
3948 static ssize_t show_dynamic_id(struct device *dev,
3949 struct device_attribute *attr,
3952 struct i915_oa_config *oa_config =
3953 container_of(attr, typeof(*oa_config), sysfs_metric_id);
3955 return sprintf(buf, "%d\n", oa_config->id);
3958 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
3959 struct i915_oa_config *oa_config)
3961 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
3962 oa_config->sysfs_metric_id.attr.name = "id";
3963 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
3964 oa_config->sysfs_metric_id.show = show_dynamic_id;
3965 oa_config->sysfs_metric_id.store = NULL;
3967 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
3968 oa_config->attrs[1] = NULL;
3970 oa_config->sysfs_metric.name = oa_config->uuid;
3971 oa_config->sysfs_metric.attrs = oa_config->attrs;
3973 return sysfs_create_group(perf->metrics_kobj,
3974 &oa_config->sysfs_metric);
3978 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
3980 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
3981 * userspace (unvalidated)
3984 * Validates the submitted OA register to be saved into a new OA config that
3985 * can then be used for programming the OA unit and its NOA network.
3987 * Returns: A new allocated config number to be used with the perf open ioctl
3988 * or a negative error code on failure.
3990 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3991 struct drm_file *file)
3993 struct i915_perf *perf = &to_i915(dev)->perf;
3994 struct drm_i915_perf_oa_config *args = data;
3995 struct i915_oa_config *oa_config, *tmp;
3996 struct i915_oa_reg *regs;
4000 DRM_DEBUG("i915 perf interface not available for this system\n");
4004 if (!perf->metrics_kobj) {
4005 DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
4009 if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
4010 DRM_DEBUG("Insufficient privileges to add i915 OA config\n");
4014 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4015 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4016 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4017 DRM_DEBUG("No OA registers given\n");
4021 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4023 DRM_DEBUG("Failed to allocate memory for the OA config\n");
4027 oa_config->perf = perf;
4028 kref_init(&oa_config->ref);
4030 if (!uuid_is_valid(args->uuid)) {
4031 DRM_DEBUG("Invalid uuid format for OA config\n");
4036 /* Last character in oa_config->uuid will be 0 because oa_config is
4039 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4041 oa_config->mux_regs_len = args->n_mux_regs;
4042 regs = alloc_oa_regs(perf,
4043 perf->ops.is_valid_mux_reg,
4044 u64_to_user_ptr(args->mux_regs_ptr),
4048 DRM_DEBUG("Failed to create OA config for mux_regs\n");
4049 err = PTR_ERR(regs);
4052 oa_config->mux_regs = regs;
4054 oa_config->b_counter_regs_len = args->n_boolean_regs;
4055 regs = alloc_oa_regs(perf,
4056 perf->ops.is_valid_b_counter_reg,
4057 u64_to_user_ptr(args->boolean_regs_ptr),
4058 args->n_boolean_regs);
4061 DRM_DEBUG("Failed to create OA config for b_counter_regs\n");
4062 err = PTR_ERR(regs);
4065 oa_config->b_counter_regs = regs;
4067 if (INTEL_GEN(perf->i915) < 8) {
4068 if (args->n_flex_regs != 0) {
4073 oa_config->flex_regs_len = args->n_flex_regs;
4074 regs = alloc_oa_regs(perf,
4075 perf->ops.is_valid_flex_reg,
4076 u64_to_user_ptr(args->flex_regs_ptr),
4080 DRM_DEBUG("Failed to create OA config for flex_regs\n");
4081 err = PTR_ERR(regs);
4084 oa_config->flex_regs = regs;
4087 err = mutex_lock_interruptible(&perf->metrics_lock);
4091 /* We shouldn't have too many configs, so this iteration shouldn't be
4094 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4095 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4096 DRM_DEBUG("OA config already exists with this uuid\n");
4102 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4104 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
4108 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4109 oa_config->id = idr_alloc(&perf->metrics_idr,
4112 if (oa_config->id < 0) {
4113 DRM_DEBUG("Failed to create sysfs entry for OA config\n");
4114 err = oa_config->id;
4118 mutex_unlock(&perf->metrics_lock);
4120 DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4122 return oa_config->id;
4125 mutex_unlock(&perf->metrics_lock);
4127 i915_oa_config_put(oa_config);
4128 DRM_DEBUG("Failed to add new OA config\n");
4133 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4135 * @data: ioctl data (pointer to u64 integer) copied from userspace
4138 * Configs can be removed while being used, the will stop appearing in sysfs
4139 * and their content will be freed when the stream using the config is closed.
4141 * Returns: 0 on success or a negative error code on failure.
4143 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4144 struct drm_file *file)
4146 struct i915_perf *perf = &to_i915(dev)->perf;
4148 struct i915_oa_config *oa_config;
4152 DRM_DEBUG("i915 perf interface not available for this system\n");
4156 if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
4157 DRM_DEBUG("Insufficient privileges to remove i915 OA config\n");
4161 ret = mutex_lock_interruptible(&perf->metrics_lock);
4165 oa_config = idr_find(&perf->metrics_idr, *arg);
4167 DRM_DEBUG("Failed to remove unknown OA config\n");
4172 GEM_BUG_ON(*arg != oa_config->id);
4174 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4176 idr_remove(&perf->metrics_idr, *arg);
4178 mutex_unlock(&perf->metrics_lock);
4180 DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4182 i915_oa_config_put(oa_config);
4187 mutex_unlock(&perf->metrics_lock);
4191 static struct ctl_table oa_table[] = {
4193 .procname = "perf_stream_paranoid",
4194 .data = &i915_perf_stream_paranoid,
4195 .maxlen = sizeof(i915_perf_stream_paranoid),
4197 .proc_handler = proc_dointvec_minmax,
4198 .extra1 = SYSCTL_ZERO,
4199 .extra2 = SYSCTL_ONE,
4202 .procname = "oa_max_sample_rate",
4203 .data = &i915_oa_max_sample_rate,
4204 .maxlen = sizeof(i915_oa_max_sample_rate),
4206 .proc_handler = proc_dointvec_minmax,
4207 .extra1 = SYSCTL_ZERO,
4208 .extra2 = &oa_sample_rate_hard_limit,
4213 static struct ctl_table i915_root[] = {
4223 static struct ctl_table dev_root[] = {
4234 * i915_perf_init - initialize i915-perf state on module bind
4235 * @i915: i915 device instance
4237 * Initializes i915-perf state without exposing anything to userspace.
4239 * Note: i915-perf initialization is split into an 'init' and 'register'
4240 * phase with the i915_perf_register() exposing state to userspace.
4242 void i915_perf_init(struct drm_i915_private *i915)
4244 struct i915_perf *perf = &i915->perf;
4246 /* XXX const struct i915_perf_ops! */
4248 if (IS_HASWELL(i915)) {
4249 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
4250 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
4251 perf->ops.is_valid_flex_reg = NULL;
4252 perf->ops.enable_metric_set = hsw_enable_metric_set;
4253 perf->ops.disable_metric_set = hsw_disable_metric_set;
4254 perf->ops.oa_enable = gen7_oa_enable;
4255 perf->ops.oa_disable = gen7_oa_disable;
4256 perf->ops.read = gen7_oa_read;
4257 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
4259 perf->oa_formats = hsw_oa_formats;
4260 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
4261 /* Note: that although we could theoretically also support the
4262 * legacy ringbuffer mode on BDW (and earlier iterations of
4263 * this driver, before upstreaming did this) it didn't seem
4264 * worth the complexity to maintain now that BDW+ enable
4265 * execlist mode by default.
4267 perf->ops.read = gen8_oa_read;
4269 if (IS_GEN_RANGE(i915, 8, 9)) {
4270 perf->oa_formats = gen8_plus_oa_formats;
4272 perf->ops.is_valid_b_counter_reg =
4273 gen7_is_valid_b_counter_addr;
4274 perf->ops.is_valid_mux_reg =
4275 gen8_is_valid_mux_addr;
4276 perf->ops.is_valid_flex_reg =
4277 gen8_is_valid_flex_addr;
4279 if (IS_CHERRYVIEW(i915)) {
4280 perf->ops.is_valid_mux_reg =
4281 chv_is_valid_mux_addr;
4284 perf->ops.oa_enable = gen8_oa_enable;
4285 perf->ops.oa_disable = gen8_oa_disable;
4286 perf->ops.enable_metric_set = gen8_enable_metric_set;
4287 perf->ops.disable_metric_set = gen8_disable_metric_set;
4288 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4290 if (IS_GEN(i915, 8)) {
4291 perf->ctx_oactxctrl_offset = 0x120;
4292 perf->ctx_flexeu0_offset = 0x2ce;
4294 perf->gen8_valid_ctx_bit = BIT(25);
4296 perf->ctx_oactxctrl_offset = 0x128;
4297 perf->ctx_flexeu0_offset = 0x3de;
4299 perf->gen8_valid_ctx_bit = BIT(16);
4301 } else if (IS_GEN_RANGE(i915, 10, 11)) {
4302 perf->oa_formats = gen8_plus_oa_formats;
4304 perf->ops.is_valid_b_counter_reg =
4305 gen7_is_valid_b_counter_addr;
4306 perf->ops.is_valid_mux_reg =
4307 gen10_is_valid_mux_addr;
4308 perf->ops.is_valid_flex_reg =
4309 gen8_is_valid_flex_addr;
4311 perf->ops.oa_enable = gen8_oa_enable;
4312 perf->ops.oa_disable = gen8_oa_disable;
4313 perf->ops.enable_metric_set = gen8_enable_metric_set;
4314 perf->ops.disable_metric_set = gen10_disable_metric_set;
4315 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4317 if (IS_GEN(i915, 10)) {
4318 perf->ctx_oactxctrl_offset = 0x128;
4319 perf->ctx_flexeu0_offset = 0x3de;
4321 perf->ctx_oactxctrl_offset = 0x124;
4322 perf->ctx_flexeu0_offset = 0x78e;
4324 perf->gen8_valid_ctx_bit = BIT(16);
4325 } else if (IS_GEN(i915, 12)) {
4326 perf->oa_formats = gen12_oa_formats;
4328 perf->ops.is_valid_b_counter_reg =
4329 gen12_is_valid_b_counter_addr;
4330 perf->ops.is_valid_mux_reg =
4331 gen12_is_valid_mux_addr;
4332 perf->ops.is_valid_flex_reg =
4333 gen8_is_valid_flex_addr;
4335 perf->ops.oa_enable = gen12_oa_enable;
4336 perf->ops.oa_disable = gen12_oa_disable;
4337 perf->ops.enable_metric_set = gen12_enable_metric_set;
4338 perf->ops.disable_metric_set = gen12_disable_metric_set;
4339 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
4341 perf->ctx_flexeu0_offset = 0;
4342 perf->ctx_oactxctrl_offset = 0x144;
4346 if (perf->ops.enable_metric_set) {
4347 mutex_init(&perf->lock);
4349 oa_sample_rate_hard_limit = 1000 *
4350 (RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
4352 mutex_init(&perf->metrics_lock);
4353 idr_init(&perf->metrics_idr);
4355 /* We set up some ratelimit state to potentially throttle any
4356 * _NOTES about spurious, invalid OA reports which we don't
4357 * forward to userspace.
4359 * We print a _NOTE about any throttling when closing the
4360 * stream instead of waiting until driver _fini which no one
4363 * Using the same limiting factors as printk_ratelimit()
4365 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
4366 /* Since we use a DRM_NOTE for spurious reports it would be
4367 * inconsistent to let __ratelimit() automatically print a
4368 * warning for throttling.
4370 ratelimit_set_flags(&perf->spurious_report_rs,
4371 RATELIMIT_MSG_ON_RELEASE);
4373 ratelimit_state_init(&perf->tail_pointer_race,
4375 ratelimit_set_flags(&perf->tail_pointer_race,
4376 RATELIMIT_MSG_ON_RELEASE);
4378 atomic64_set(&perf->noa_programming_delay,
4379 500 * 1000 /* 500us */);
4385 static int destroy_config(int id, void *p, void *data)
4387 i915_oa_config_put(p);
4391 void i915_perf_sysctl_register(void)
4393 sysctl_header = register_sysctl_table(dev_root);
4396 void i915_perf_sysctl_unregister(void)
4398 unregister_sysctl_table(sysctl_header);
4402 * i915_perf_fini - Counter part to i915_perf_init()
4403 * @i915: i915 device instance
4405 void i915_perf_fini(struct drm_i915_private *i915)
4407 struct i915_perf *perf = &i915->perf;
4412 idr_for_each(&perf->metrics_idr, destroy_config, perf);
4413 idr_destroy(&perf->metrics_idr);
4415 memset(&perf->ops, 0, sizeof(perf->ops));
4420 * i915_perf_ioctl_version - Version of the i915-perf subsystem
4422 * This version number is used by userspace to detect available features.
4424 int i915_perf_ioctl_version(void)
4427 * 1: Initial version
4428 * I915_PERF_IOCTL_ENABLE
4429 * I915_PERF_IOCTL_DISABLE
4431 * 2: Added runtime modification of OA config.
4432 * I915_PERF_IOCTL_CONFIG
4434 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
4435 * preemption on a particular context so that performance data is
4436 * accessible from a delta of MI_RPC reports without looking at the
4439 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
4440 * be run for the duration of the performance recording based on
4441 * their SSEU configuration.
4443 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
4444 * interval for the hrtimer used to check for OA data.
4449 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4450 #include "selftests/i915_perf.c"